[yosys] branch master updated (4534501 -> e3b13ac)
Ruben Undheim
rubund-guest at moszumanska.debian.org
Tue Oct 28 20:39:36 UTC 2014
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a change to branch master
in repository yosys.
from 4534501 Updated timestamp in changelog
adds 2446b6f added $pmux cell translation
adds b783dbe fixed memory next issue, when same memory is written in different case statement fixed reduce_xnor, logic_not bug translation bug
adds e1743b3 Added "test_cell -script"
adds 652345c Merge pull request #38 from rubund/master
adds 34af6a1 Merge branch 'master' of github.com:cliffordwolf/yosys
adds 76f8128 Fixed autotest for non-basename arguments
adds b847ec8 Added $macc cell type
adds deff416 Fixed assignment of out-of bounds array element
adds bff4706 Added $macc simlib model (also use as techmap rule for now)
adds 680eaaa Fixed $clog2 (off by one error)
adds fa64942 Added $macc SAT model
adds 98e6463 Added $macc eval model
adds 9329a76 Various bug fixes (related to $macc model testing)
adds 15b3c54 Added "test_cell -nosat"
adds 015dcdc Added "maccmap" command
adds c50b841 Added 'techmap_maccmap' techmap attribute
adds dd887cc Using maccmap for $macc and $mul techmap
adds 6747a70 Added "test_cell -const"
adds 1a88e47 Trim msb/lsb zero bits from full adder in maccmap
adds d46bac3 Added "$fa" cell type
adds 48b00dc Another $clog2 bugfix
adds af0c887 Added $lcu cell type
adds 6dc07eb Fixes and cleanups for blackbox.v
adds fcb4613 Simplified $fa undef model
adds 44b5bd4 Fixed simlib $macc model for xilinx xsim
adds 3ae96f8 Using pkg-config to find libffi
adds aab0e3b Cleanup in wreduce
adds ff157fb alumacc skeleton
adds 0b72f0a Basic $macc extract in alumacc
adds 7b16c63 Merge $macc cells in alumacc pass
adds 0df1d9a Extract $alu cells in alumacc
adds b34ca15 alumacc fix for $pos cells
adds 124e759 Added techmap_wrap attribute
adds 014bb34 Various fixes/cleanups in alumacc and maccmap
adds 923bbbe Using alumacc in techmap.v
adds 7e156a5 Fixed techmap_wrap for techmap_celltype
adds 7815f81 Added "synth" command
adds 2442eb3 Fixed monitor notifications for removed cell
adds 2cbdbaa Fixed wreduce $shiftx handling
adds fcbda07 Improved maccmap tree bit packing
adds b470c48 Added the obvious optimizations to alumacc $macc generator
adds b86410b More aggressive $macc merging in alumacc
adds 6644e27 Fixed $macc simlib model for zero-config
adds fa96cf4 Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
adds ae02d9c Fixed $memwr/$memrd order in memory_dff
adds 9ae559b Fixed $_NOR vs. $_NOR_ typo in abc.cc
adds ba61925 Added commit count to devel version number
adds 815fab9 Added "abc -fast"
adds 4888d61 Improvements in "synth" script
adds f56b928 Do not run "scorr" in "abc -fast"
adds f7bb8f2 Alphabetically sort port names in "show" output
adds 3aa003c Using "NOT" instead of "INV" as cell name in default abc genlib file
adds 5827826 Small improvements in "abc" command handle_loops() function
adds 309623f Sorting of object names in ilang backend
adds 00964f2 Initialize RTLIL::Const from std::vector<bool>
adds a7758ef Added "test_abcloop" command
adds edf11c6 Assert on new logic loops in "share" pass
adds 8d60754 Do not introduce new logic loops in "share"
adds a6c08b4 Still loop bug in "share": changed assert to warning
adds b28be07 Added "share -limit"
adds d6e2ace Logic loop bugfix for "share" pass
adds 96e821d Various improvements regarding logic loops in "share" results
adds 13117bb Re-enabled assert for new logic loops in "share" pass
adds d3c67ad Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation
adds bcd2625 Merge pull request #39 from ahmedirfan1983/master
adds f9a307a namespace Yosys
adds 0b8cfbc Added support for "keep" on modules
adds 2ee03f5 set "keep" on modules with $assert cells in "hierarchy"
adds 7019bc0 resource sharing of $alu cells
adds 600c6cb remove buffers in opt_clean
adds c3e779a Added $_BUF_ cell type
adds 3e4b0ca added resource sharing of $macc cells
adds 56c1d43 satgen import sigbit api
adds c5c7066 sat encoding for exclusive $pmux ctrl inputs in "share" pass
adds 9dea161 sort cell types in "stat" output by name
adds 696d7ed Fixes in "hilomap" help message
adds ccf7b2e Added mxe-based cross build for win32
adds d3405c1 No rusage on win32
adds 1007f54 added .exe and .html output files to .gitignore
adds fea11f0 Added API for generic cell cost calculations
adds c7f5aab Replaced "#ifdef WIN32" with "#ifdef _WIN32"
adds 4569a74 Renamed SIZE() to GetSize() because of name collision on Win32
adds 7cb0d3a Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
adds bbd8080 Added format __attribute__ to stringf()
adds 774933a Replaced fnmatch() with patmatch()
adds ee5165c Moved patmatch() to yosys.cc
adds 986bcc1 Various win32 build fixes in yosys.cc
adds 2c68310 Added next_token() function (strtok() replacement)
adds 54bf3a9 More Win32 build fixes
adds 20d85f2 Fixed next_token()
adds df537a2 Using next_token() to parse commands
adds 93e6ebe Disabled ezminisat timeout feature for Win32
adds 0a651f1 Disabled vhdl2verilog command for win32 builds
adds 7df8cbe Not using std::to_string in ezsat (problems with mingw)
adds 51b1824 Disabled "cover -d" on win32
adds 53349fb Fixed ifdefs for plugin unloading
adds e8c66ee Fixed MXE readline support
adds 568fee5 Added proc_self_dirname() for win32
adds a32e067 Strip win32 executeables
adds 8263f6a Fixed win32 troubles with f.readsome()
adds 35fbc0b Do not the 'z' modifier in format string (another win32 fix)
adds 217c7c7 Fixed Makefile PRETTY=1 for MXE (win32) and EMCC (js) builds
adds f30aee0 Added "make dist" for mxe builds
adds 0dc249c Shrinked the copyright banner by 1 character
adds d2b8b48 Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source tree
adds b1596bc Added run_command() api to replace system() and popen()
adds 9b4d171 Using stringf() instead of asprintf() in "abc" pass
adds 0b9282a Added make_temp_{file,dir}() and remove_directory() APIs
adds 1a7684b Various small fixes for non-win32 builds
adds 2fdb3a4 Various Makefile changes for cross-compiling ABC for Win32
adds 0913e96 More win32/abc fixes
adds 09d2e5c Fixed ABC ARCHFLAGS for win32 cross build
adds c21c9da Removed CHECK() macro from libparse.cc (was using non-std c features)
adds 2873a84 Updated ABC, enabled ABC in mxe builds
adds fad0b0c Updated lexers & parsers to include prefixes
adds 0352dbf Fixed log so it will compile under Visual Studio - Included an implementation of gettimeofday
adds 069521e Define empty __attribute__ macro for non-gcc, non-clang compilers
adds 9cb2303 Made iterators extend std::iterator and added == operator
adds 6433203 Wrapped init in std::set constructor
adds 9ee3a4b Changed to explicit heap allocated memory
adds e5b8390 Changed from "and" to "&&"
adds cf85aab A few indent fixes
adds c3e9922 Replaced readsome() with read() and gcount()
adds f65e1c3 Updated .gitignore file for ilang and verilog frontends
adds 1fc6208 Check for _YOSYS_ in yosys.h
adds 8cea352 Merge branch 'win32'
adds 3445a93 Fixed MXE build
adds 2355ddf Fixed gcc warning
adds 82ed814 Replaced log_assert() do { ... } while (0) hack with a static inline function
adds 6b05a9e Fixed handling of invalid array access in mem2reg code
adds 3be5fa0 Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
adds 3838856 Print "SystemVerilog" in "read_verilog -sv" log messages
adds 66eb254 Some cleanups in opt_clean
adds 18cb8b4 Don't be too smart with $dff cells with "init" attribute on out signal
adds 34caeeb Fixed a few VS warnings
adds fda52f0 Wrapped math in int constructor
adds 31267a1 Header changes so it will compile on VS
adds 4df9026 Various MXE build fixes
adds 973d376 Added genfiles.zip to MXE "make dist"
adds 468ae92 Various win32 / vs build fixes
adds b3a6f8f More win32 (mxe and vs) build fixes
adds e8a609f Added vcxproj_files.txt to MXE "make dist"
adds c321b41 Added notes regarding building in VS
adds b5da3a6 Moved yosys-config.in to misc/
adds 85572b0 Create vcxsrc in mxe build "make dist"
adds 84ffe04 Fixed various VS warnings
adds 6bcb4f1 Fixed shell prompt and proc_self_dirname() for win32
adds 41db98b Fixed typo in test_cell
adds 57cd485 Disabled READLINE in MXE cross build
adds 0471d15 Various improvements to version reporting on win32
adds bb631c6 Also look for yosys-abc in parent dir on win32
adds 6c1c1e9 Improved new_id() for win32
adds de8adb8 Builds on Mac 10.9.2 with LLVM 3.5.
adds 3202ba6 Merge pull request #40 from parvizp/compile_mac_10.9.2
adds 750c615 minor indenting corrections
adds c5eb5e5 Re-introduced Yosys::readsome() helper function (f.read() + f.gcount() made problems with lines > 16kB)
adds 26cbe4a Fixed constant "cond ? string1 : string2" with strings of different size
adds 70b2efd Added support for $readmemh/$readmemb
adds c4a2b3c Improvements in $readmem[bh] implementation
adds f9c096e Added support for task and function args in parentheses
new 69742b8 Merge branch 'upstream'
new e3b13ac Refreshed patches for new upstream version
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
.gitignore | 7 +
CHECKLISTS | 134 ------
CodingReadme | 235 +++++++++
CodingStyle | 43 --
Makefile | 89 +++-
README | 24 +-
backends/blif/blif.cc | 4 +
backends/btor/btor.cc | 71 ++-
backends/btor/verilog2btor.sh | 4 +-
backends/edif/edif.cc | 6 +-
backends/ilang/ilang_backend.cc | 72 ++-
backends/ilang/ilang_backend.h | 4 +-
backends/intersynth/intersynth.cc | 3 +
backends/spice/spice.cc | 4 +
backends/verilog/verilog_backend.cc | 12 +-
backends/verilog/verilog_backend.h | 38 --
debian/patches/01_gitrevision.patch | 12 +-
debian/patches/02_removeabc.patch | 22 +-
debian/patches/03_notruntests.patch | 14 +-
debian/patches/04_installpath.patch | 12 +-
debian/patches/05_abc_executable.patch | 10 +-
debian/patches/06_cflags_ldflags.patch | 24 +-
frontends/ast/ast.cc | 13 +-
frontends/ast/ast.h | 2 +
frontends/ast/dpicall.cc | 12 +-
frontends/ast/genrtlil.cc | 40 +-
frontends/ast/simplify.cc | 160 +++++-
frontends/ilang/.gitignore | 8 +-
frontends/ilang/Makefile.inc | 22 +-
frontends/ilang/ilang_frontend.cc | 6 +-
frontends/ilang/{lexer.l => ilang_lexer.l} | 6 +-
frontends/ilang/{parser.y => ilang_parser.y} | 0
frontends/liberty/liberty.cc | 1 -
frontends/verific/verific.cc | 23 +-
frontends/verilog/.gitignore | 8 +-
frontends/verilog/Makefile.inc | 24 +-
frontends/verilog/preproc.cc | 4 +-
frontends/verilog/verilog_frontend.cc | 34 +-
frontends/verilog/{lexer.l => verilog_lexer.l} | 4 +-
frontends/verilog/{parser.y => verilog_parser.y} | 53 +-
frontends/vhdl2verilog/vhdl2verilog.cc | 45 +-
kernel/bitpattern.h | 4 +
kernel/calc.cc | 2 +-
kernel/celltypes.h | 28 +-
kernel/consteval.h | 100 +++-
kernel/cost.h | 84 ++++
kernel/driver.cc | 95 ++--
kernel/log.cc | 29 +-
kernel/log.h | 38 +-
kernel/macc.h | 240 +++++++++
kernel/modtools.h | 6 +-
kernel/register.cc | 48 +-
kernel/rtlil.cc | 125 +++--
kernel/rtlil.h | 16 +-
kernel/satgen.h | 298 +++++++++---
kernel/sigtools.h | 8 +-
kernel/utils.h | 12 +-
kernel/yosys.cc | 356 +++++++++++++-
kernel/yosys.h | 77 ++-
libs/ezsat/ezminisat.cc | 15 +-
libs/ezsat/ezminisat.h | 2 +
libs/ezsat/ezsat.cc | 151 +++---
libs/ezsat/ezsat.h | 7 +-
libs/sha1/sha1.cpp | 5 +-
libs/subcircuit/subcircuit.cc | 4 +
manual/CHAPTER_CellLib.tex | 2 +-
manual/CHAPTER_Prog/stubnets.cc | 4 +-
manual/PRESENTATION_Prog/my_cmd.cc | 2 +-
misc/create_vcxsrc.sh | 54 +++
yosys-config.in => misc/yosys-config.in | 0
passes/abc/abc.cc | 376 ++++++++-------
passes/abc/blifparse.cc | 7 +-
passes/abc/blifparse.h | 7 +-
passes/cmds/Makefile.inc | 2 +-
passes/cmds/add.cc | 8 +-
passes/cmds/connect.cc | 4 +
passes/cmds/connwrappers.cc | 4 +
passes/cmds/copy.cc | 4 +
passes/cmds/cover.cc | 19 +-
passes/cmds/delete.cc | 8 +-
passes/cmds/{log.cc => logcmd.cc} | 4 +
passes/cmds/plugin.cc | 9 +-
passes/cmds/rename.cc | 4 +
passes/cmds/scatter.cc | 4 +
passes/cmds/scc.cc | 4 +
passes/cmds/select.cc | 34 +-
passes/cmds/setattr.cc | 4 +
passes/cmds/setundef.cc | 4 +
passes/cmds/show.cc | 22 +-
passes/cmds/splice.cc | 4 +
passes/cmds/splitnets.cc | 4 +
passes/cmds/stat.cc | 227 ++++-----
passes/cmds/tee.cc | 4 +
passes/cmds/trace.cc | 1 +
passes/cmds/write_file.cc | 8 +-
passes/fsm/fsm.cc | 4 +
passes/fsm/fsm_detect.cc | 4 +
passes/fsm/fsm_expand.cc | 6 +-
passes/fsm/fsm_export.cc | 5 +
passes/fsm/fsm_extract.cc | 20 +-
passes/fsm/fsm_info.cc | 4 +
passes/fsm/fsm_map.cc | 12 +-
passes/fsm/fsm_opt.cc | 18 +-
passes/fsm/fsm_recode.cc | 12 +-
passes/fsm/fsmdata.h | 15 +-
passes/hierarchy/hierarchy.cc | 76 ++-
passes/hierarchy/submod.cc | 4 +
passes/memory/memory.cc | 4 +
passes/memory/memory_collect.cc | 8 +-
passes/memory/memory_dff.cc | 26 +-
passes/memory/memory_map.cc | 14 +-
passes/memory/memory_share.cc | 4 +-
passes/memory/memory_unpack.cc | 8 +-
passes/opt/opt.cc | 4 +
passes/opt/opt_clean.cc | 68 +--
passes/opt/opt_const.cc | 42 +-
passes/opt/opt_muxtree.cc | 8 +-
passes/opt/opt_reduce.cc | 4 +
passes/opt/opt_rmdff.cc | 12 +-
passes/opt/opt_share.cc | 6 +-
passes/opt/share.cc | 587 ++++++++++++++++++++---
passes/opt/wreduce.cc | 105 ++--
passes/proc/proc.cc | 4 +
passes/proc/proc_arst.cc | 17 +-
passes/proc/proc_clean.cc | 15 +-
passes/proc/proc_dff.cc | 14 +-
passes/proc/proc_init.cc | 8 +-
passes/proc/proc_mux.cc | 18 +-
passes/proc/proc_rmdead.cc | 8 +-
passes/sat/eval.cc | 12 +-
passes/sat/expose.cc | 18 +-
passes/sat/freduce.cc | 6 +-
passes/sat/miter.cc | 6 +-
passes/sat/sat.cc | 14 +-
passes/techmap/Makefile.inc | 10 +-
passes/techmap/alumacc.cc | 567 ++++++++++++++++++++++
passes/techmap/dfflibmap.cc | 14 +-
passes/techmap/extract.cc | 534 ++++++++++-----------
passes/techmap/hilomap.cc | 10 +-
passes/techmap/iopadmap.cc | 6 +-
passes/techmap/libparse.cc | 39 +-
passes/techmap/libparse.h | 2 +-
passes/techmap/maccmap.cc | 404 ++++++++++++++++
passes/techmap/simplemap.cc | 30 +-
passes/techmap/techmap.cc | 146 ++++--
passes/tests/Makefile.inc | 1 +
passes/tests/test_abcloop.cc | 289 +++++++++++
passes/tests/test_autotb.cc | 5 +-
passes/tests/test_cell.cc | 350 ++++++++++----
techlibs/common/Makefile.inc | 2 +
techlibs/common/blackbox.sed | 5 +-
techlibs/common/simcells.v | 6 +
techlibs/common/simlib.v | 141 ++++++
techlibs/common/synth.cc | 160 ++++++
techlibs/common/techmap.v | 432 ++---------------
techlibs/xilinx/synth_xilinx.cc | 6 +-
tests/simple/task_func.v | 36 +-
tests/tools/autotest.sh | 7 +-
158 files changed, 6079 insertions(+), 2240 deletions(-)
delete mode 100644 CHECKLISTS
create mode 100644 CodingReadme
delete mode 100644 CodingStyle
delete mode 100644 backends/verilog/verilog_backend.h
rename frontends/ilang/{lexer.l => ilang_lexer.l} (97%)
rename frontends/ilang/{parser.y => ilang_parser.y} (100%)
rename frontends/verilog/{lexer.l => verilog_lexer.l} (99%)
rename frontends/verilog/{parser.y => verilog_parser.y} (96%)
create mode 100644 kernel/cost.h
create mode 100644 kernel/macc.h
create mode 100644 misc/create_vcxsrc.sh
rename yosys-config.in => misc/yosys-config.in (100%)
rename passes/cmds/{log.cc => logcmd.cc} (97%)
create mode 100644 passes/techmap/alumacc.cc
create mode 100644 passes/techmap/maccmap.cc
create mode 100644 passes/tests/test_abcloop.cc
create mode 100644 techlibs/common/synth.cc
--
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