[yosys] 47/57: Fixed description

[Ruben Undheim]

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rubund-guest pushed a commit to branch master
in repository yosys.

commit 8144dbd27f1b7814bd2dab8a6f4478a61f030d05
Author: Ruben Undheim <ruben.undheim at gmail.com>
Date:   Sun Sep 14 09:43:07 2014 +0200

    Fixed description
---
 debian/control | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/debian/control b/debian/control
index e1b1371..6d29658 100644
--- a/debian/control
+++ b/debian/control
@@ -14,7 +14,7 @@ Architecture: any
 Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot,
          berkeley-abc
 Description: Yosys Open SYnthesis Suite
- Yosys is a framework for Verilog RTL synthesis. It currently has extensive
+ This is a framework for Verilog RTL synthesis. It currently has extensive
  Verilog-2005 support and provides a basic set of synthesis algorithms for
  various application domains.
  .

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