[yosys] 07/38: Skip blackbox modules in design->selected_modules()

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit 5b41470e151e3b1019e87dfddf900cea51922409
Author: Clifford Wolf <clifford at clifford.at>
Date:   Tue Feb 3 23:11:57 2015 +0100

    Skip blackbox modules in design->selected_modules()
---
 kernel/rtlil.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9b55d42..8c64217 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -460,7 +460,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_module(it.first))
+		if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
 			result.push_back(it.second);
 	return result;
 }
@@ -470,7 +470,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_whole_module(it.first))
+		if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
 			result.push_back(it.second);
 	return result;
 }
@@ -480,7 +480,9 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_whole_module(it.first))
+		if (it.second->get_bool_attribute("\\blackbox"))
+			continue;
+		else if (selected_whole_module(it.first))
 			result.push_back(it.second);
 		else if (selected_module(it.first))
 			log_warning("Ignoring partially selected module %s.\n", log_id(it.first));

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