[yosys] 14/38: Added cell->known(), cell->input(portname), cell->output(portname)
Ruben Undheim
rubund-guest at moszumanska.debian.org
Mon Feb 9 19:36:45 UTC 2015
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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.
commit dce1fae777bcc9791c2f49be4b53f1de53df7502
Author: Clifford Wolf <clifford at clifford.at>
Date: Sat Feb 7 11:40:19 2015 +0100
Added cell->known(), cell->input(portname), cell->output(portname)
---
kernel/rtlil.cc | 34 ++++++++++++++++++++++++++++++++++
kernel/rtlil.h | 5 +++++
2 files changed, 39 insertions(+)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8c64217..b1e2c0e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -19,6 +19,7 @@
#include "kernel/yosys.h"
#include "kernel/macc.h"
+#include "kernel/celltypes.h"
#include "frontends/verilog/verilog_frontend.h"
#include "backends/ilang/ilang_backend.h"
@@ -1928,6 +1929,39 @@ const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
return connections_;
}
+bool RTLIL::Cell::known() const
+{
+ if (yosys_celltypes.cell_known(type))
+ return true;
+ if (module && module->design && module->design->module(type))
+ return true;
+ return false;
+}
+
+bool RTLIL::Cell::input(RTLIL::IdString portname) const
+{
+ if (yosys_celltypes.cell_known(type))
+ return yosys_celltypes.cell_input(type, portname);
+ if (module && module->design) {
+ RTLIL::Module *m = module->design->module(type);
+ RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+ return w && w->port_input;
+ }
+ return false;
+}
+
+bool RTLIL::Cell::output(RTLIL::IdString portname) const
+{
+ if (yosys_celltypes.cell_known(type))
+ return yosys_celltypes.cell_output(type, portname);
+ if (module && module->design) {
+ RTLIL::Module *m = module->design->module(type);
+ RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+ return w && w->port_output;
+ }
+ return false;
+}
+
bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
{
return parameters.count(paramname) != 0;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c17ede3..985bffe 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1140,6 +1140,11 @@ public:
const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
+ // information about cell ports
+ bool known() const;
+ bool input(RTLIL::IdString portname) const;
+ bool output(RTLIL::IdString portname) const;
+
// access cell parameters
bool hasParam(RTLIL::IdString paramname) const;
void unsetParam(RTLIL::IdString paramname);
--
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