[qflow] branch master updated (90b8559 -> 105b877)

Ruben Undheim rubund-guest at moszumanska.debian.org
Tue May 12 19:34:44 UTC 2015


This is an automated email from the git hooks/post-receive script.

rubund-guest pushed a change to branch master
in repository qflow.

      from  90b8559   There were some problems with paths. Fixed
      adds  4144265   Modified the blif2Verilog script so that the ".nopwr.v" file adds wire statements for power and ground, assigning 1'b1 and 1'b0 to them, respectively, so that the verilog file becomes simulatible.  Also, for the purpose of verilog simulation, added the verilog libraries for the standard cell gates to the qflow distribution/installation.
      adds  fb8691e   Update at Mon Apr 20 09:31:37 EDT 2015 by tim
      adds  1c52cb3   Merge branch 'master' into work
      adds  2f42e7c   Changed all tcl scripts to use /bin/tclsh;  however, this needs to be set through a substitution, so not yet done. . .
      adds  3aea04f   Update at Thu May  7 15:48:59 EDT 2015 by tim
      adds  279b52e   Merge branch 'master' into work
      adds  27553b5   Implemented a variation of "decongest.tcl" that will take a .cel file and insert fill cells uniformly to meet a specific density. Added the placement option "initial_density" indicating the density of actively routed cells (as a fraction of the total layout area).  This gives a way to force a density rather than relying on the congestion router solution (or having to wait for an initial router failure to get the congestion router solution).
      adds  78593e3   Corrected calculation for number of fill cells to add, to get the specified density to be interpreted as the fraction of the layout comprising actively routed cells.
      adds  eeede02   Update at Fri May  8 20:08:42 EDT 2015 by tim
      adds  9298529   Merge branch 'master' into work
      adds  705fc95   Additional correction to clocktree to correctly parse a cellname when fill cells have been merged into cell instances with a specific syntax.
      adds  84dab5a   Another correction to prevent the clock tree insertion tool from screwing up when faced with fill cells added for density management.
       new  b83159a   Merge tag 'upstream/1.0.96'
       new  105b877   Updated changelog

The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.


Summary of changes:
 VERSION                       |    2 +-
 debian/changelog              |    2 +-
 scripts/addspacers.tcl        |    2 +-
 scripts/bdnet2cel.tcl         |    2 +-
 scripts/bdnet2sim.tcl         |    2 +-
 scripts/blif2sim.tcl          |    2 +-
 scripts/clocktree.tcl         |   15 +-
 scripts/decongest.tcl         |  155 ++++--
 scripts/getfillcell.tcl       |    2 +-
 scripts/outpreporig.tcl       |    2 +-
 scripts/outputprep.tcl        |    2 +-
 scripts/place2def.tcl         |    2 +-
 scripts/postproc.tcl          |    2 +-
 scripts/qflow.sh.in           |    2 +
 scripts/resynthesize.sh       |   21 +-
 scripts/rtl2bdnet.tcl         |    2 +-
 scripts/rtl2sim.tcl           |    2 +-
 scripts/setreset.tcl          |    2 +-
 scripts/synthesize_yosys.sh   |   21 +-
 scripts/vispreproc.tcl        |    2 +-
 scripts/vmunge.tcl            |    2 +-
 scripts/ybuffer.tcl           |    2 +-
 scripts/ypostproc.tcl         |    2 +-
 src/blif2Verilog.c            |    5 +
 tech/osu035/Makefile          |    1 +
 tech/osu035/Makefile.in       |    1 +
 tech/osu035/osu035_stdcells.v | 1140 +++++++++++++++++++++++++++++++++++++++++
 tech/osu050/Makefile          |    1 +
 tech/osu050/Makefile.in       |    1 +
 tech/osu050/osu05_stdcells.v  | 1140 +++++++++++++++++++++++++++++++++++++++++
 30 files changed, 2474 insertions(+), 65 deletions(-)
 create mode 100755 tech/osu035/osu035_stdcells.v
 create mode 100755 tech/osu050/osu05_stdcells.v

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