[icestorm] 03/75: Import of icestorm-snapshot-150413.zip
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 15:52:02 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository icestorm.
commit c41701ca3a2046e9cabe303cff0aa203215d70c1
Author: Clifford Wolf <clifford at clifford.at>
Date: Sat Jul 18 13:06:48 2015 +0200
Import of icestorm-snapshot-150413.zip
---
icebox/icebox.py | 269 ++++-
icebox/icebox_chipdb.py | 34 +-
icebox/icebox_diff.py | 3 +-
icebox/icebox_explain.py | 29 +-
icebox/icebox_html.py | 30 +-
icebox/icebox_maps.py | 16 +-
icebox/icebox_vlog.py | 346 +++++--
icebox/iceboxdb.py | 2575 ++++++++++++++++++++++++++++++++++++++++++++--
icepack/icepack.cc | 7 +-
9 files changed, 3106 insertions(+), 203 deletions(-)
diff --git a/icebox/icebox.py b/icebox/icebox.py
index 01cda0d..60b5dc2 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -30,19 +30,23 @@ class iceconfig:
self.device = ""
self.logic_tiles = dict()
self.io_tiles = dict()
- self.ram_tiles = dict()
- self.ram_init = dict()
+ self.ramb_tiles = dict()
+ self.ramt_tiles = dict()
self.extra_bits = set()
def setup_empty_1k(self):
self.clear()
+ self.device = "1k"
self.max_x = 13
self.max_y = 17
for x in range(1, self.max_x):
for y in range(1, self.max_y):
if x in (3, 10):
- self.ram_tiles[(x, y)] = ["0" * 42 for i in range(16)]
+ if y % 2 == 1:
+ self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)]
+ else:
+ self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)]
else:
self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)]
@@ -63,15 +67,36 @@ class iceconfig:
def tile(self, x, y):
if (x, y) in self.io_tiles: return self.io_tiles[(x, y)]
if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)]
- if (x, y) in self.ram_tiles: return self.ram_tiles[(x, y)]
+ if (x, y) in self.ramb_tiles: return self.ramb_tiles[(x, y)]
+ if (x, y) in self.ramt_tiles: return self.ramt_tiles[(x, y)]
return None
+ def pinloc_db(self):
+ assert self.device == "1k"
+ return pinloc_db
+
+ def gbufin_db(self):
+ return gbufin_db[self.device]
+
+ def icegate_db(self):
+ return icegate_db[self.device]
+
+ def padin_pio_db(self):
+ return padin_pio_db[self.device]
+
+ def extra_bits_db(self):
+ return extra_bits_db[self.device]
+
+ def ieren_db(self):
+ return ieren_db[self.device]
+
def tile_db(self, x, y):
if x == 0: return iotile_l_db
if y == 0: return iotile_b_db
if x == self.max_x: return iotile_r_db
if y == self.max_y: return iotile_t_db
- if (x, y) in self.ram_tiles: return ramtile_db
+ if (x, y) in self.ramb_tiles: return rambtile_db
+ if (x, y) in self.ramt_tiles: return ramttile_db
if (x, y) in self.logic_tiles: return logictile_db
assert False
@@ -80,7 +105,8 @@ class iceconfig:
if y == 0: return "IO"
if x == self.max_x: return "IO"
if y == self.max_y: return "IO"
- if (x, y) in self.ram_tiles: return "RAM"
+ if (x, y) in self.ramb_tiles: return "RAMB"
+ if (x, y) in self.ramt_tiles: return "RAMT"
if (x, y) in self.logic_tiles: return "LOGIC"
assert False
@@ -96,7 +122,6 @@ class iceconfig:
if entry[1] in ("routing", "buffer"):
return self.tile_has_net(x, y, entry[2]) and self.tile_has_net(x, y, entry[3])
return True
-
def tile_has_net(self, x, y, netname):
if netname.startswith("logic_op_"):
@@ -161,7 +186,12 @@ class iceconfig:
if npos is not None and pos is not None:
if npos == "x":
- return (nx, ny, "lutff_%d/out" % func)
+ if (nx, ny) in self.logic_tiles:
+ return (nx, ny, "lutff_%d/out" % func)
+ if (nx, ny) in self.ramb_tiles:
+ return (nx, ny, "ram/RDATA_%d" % func)
+ if (nx, ny) in self.ramt_tiles:
+ return (nx, ny, "ram/RDATA_%d" % (8+func))
elif pos == "x" and npos in ("l", "r", "t", "b"):
if func in (0, 4): return (nx, ny, "io_0/D_IN_0")
@@ -194,6 +224,10 @@ class iceconfig:
if match:
funcnets |= self.follow_funcnet(x, y, int(match.group(1)))
+ match = re.match(r"ram/RDATA_(\d+)", netname)
+ if match:
+ funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8)
+
return funcnets
def follow_net(self, netspec):
@@ -273,12 +307,22 @@ class iceconfig:
neighbours.add((s[0], s[1], s[2]))
return neighbours
- def group_segments(self, all_from_tiles=set()):
+ def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list()):
seed_segments = set()
seen_segments = set()
connected_segments = dict()
grouped_segments = set()
+ for seg in extra_segments:
+ seed_segments.add(seg)
+
+ for conn in extra_connections:
+ s1, s2 = conn
+ connected_segments.setdefault(s1, set()).add(s2)
+ connected_segments.setdefault(s2, set()).add(s1)
+ seed_segments.add(s1)
+ seed_segments.add(s2)
+
for idx, tile in self.io_tiles.items():
tc = tileconfig(tile)
pintypes = [ list("000000"), list("000000") ]
@@ -314,8 +358,44 @@ class iceconfig:
seed_segments.add((idx[0], idx[1], "lutff_7/cout"))
add_seed_segments(idx, tile, logictile_db)
- for idx, tile in self.ram_tiles.items():
- add_seed_segments(idx, tile, ramtile_db)
+ for idx, tile in self.ramb_tiles.items():
+ add_seed_segments(idx, tile, rambtile_db)
+
+ for idx, tile in self.ramt_tiles.items():
+ add_seed_segments(idx, tile, ramttile_db)
+
+ for padin, pio in enumerate(self.padin_pio_db()):
+ s1 = (pio[0], pio[1], "wire_gbuf/padin_%d" % pio[2])
+ s2 = (pio[0], pio[1], "glb_netwk_%d" % padin)
+ if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
+ connected_segments.setdefault(s1, set()).add(s2)
+ connected_segments.setdefault(s2, set()).add(s1)
+ seed_segments.add(s1)
+ seed_segments.add(s2)
+
+ for entry in self.icegate_db():
+ if entry[0] == 0 or entry[0] == self.max_x:
+ iocells = [(entry[0], i) for i in range(1, self.max_y)]
+ if entry[1] == 0 or entry[1] == self.max_y:
+ iocells = [(i, entry[1]) for i in range(1, self.max_x)]
+ for cell in iocells:
+ s1 = (entry[0], entry[1], "wire_gbuf/in")
+ s2 = (cell[0], cell[1], "io_global/latch")
+ if s1 in seed_segments or s2 in seed_segments or \
+ (entry[0], entry[1]) in all_from_tiles or (cell[0], cell[1]) in all_from_tiles:
+ connected_segments.setdefault(s1, set()).add(s2)
+ connected_segments.setdefault(s2, set()).add(s1)
+ seed_segments.add(s1)
+ seed_segments.add(s2)
+
+ for entry in self.gbufin_db():
+ s1 = (entry[0], entry[1], "wire_gbuf/in")
+ s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2])
+ if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
+ connected_segments.setdefault(s1, set()).add(s2)
+ connected_segments.setdefault(s2, set()).add(s1)
+ seed_segments.add(s1)
+ seed_segments.add(s2)
while seed_segments:
queue = set()
@@ -373,7 +453,7 @@ class iceconfig:
expected_data_lines -= 1
continue
assert expected_data_lines <= 0
- if line[0] in (".io_tile", ".logic_tile", ".ram_tile"):
+ if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile"):
current_data = list()
expected_data_lines = 16
self.max_x = max(self.max_x, int(line[1]))
@@ -384,8 +464,11 @@ class iceconfig:
if line[0] == ".logic_tile":
self.logic_tiles[(int(line[1]), int(line[2]))] = current_data
continue
- if line[0] == ".ram_tile":
- self.ram_tiles[(int(line[1]), int(line[2]))] = current_data
+ if line[0] == ".ramb_tile":
+ self.ramb_tiles[(int(line[1]), int(line[2]))] = current_data
+ continue
+ if line[0] == ".ramt_tile":
+ self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data
continue
if line[0] == ".extra_bit":
self.extra_bits.add((int(line[1]), int(line[2]), int(line[3])))
@@ -394,7 +477,7 @@ class iceconfig:
assert line[1] in ["1k"]
self.device = line[1]
continue
- if line[0] == ".comment":
+ if line[0] in [".comment", ".sym"]:
expected_data_lines = -1
continue
print("%sWarning: ignoring line %d: %s" % (logprefix, linenum, linetext.strip()))
@@ -532,7 +615,7 @@ def sp12v_normalize(netname, edge=""):
return netname
-def netname_normalize(netname, edge=""):
+def netname_normalize(netname, edge="", ramb=False, ramt=False):
if netname.startswith("sp4_v_"): return sp4v_normalize(netname, edge)
if netname.startswith("sp4_h_"): return sp4h_normalize(netname, edge)
if netname.startswith("sp12_v_"): return sp12v_normalize(netname, edge)
@@ -542,6 +625,12 @@ def netname_normalize(netname, edge=""):
netname = netname.replace("lc_", "lutff_")
netname = netname.replace("wire_logic_cluster/", "")
netname = netname.replace("wire_io_cluster/", "")
+ netname = netname.replace("wire_bram/", "")
+ if (ramb or ramt) and netname.startswith("input"):
+ match = re.match(r"input(\d)_(\d)", netname)
+ idx1, idx2 = (int(match.group(1)), int(match.group(2)))
+ if ramb: netname="ram/WADDR_%d" % (idx1*4 + idx2)
+ if ramt: netname="ram/RADDR_%d" % (idx1*4 + idx2)
match = re.match(r"(...)_op_(.*)", netname)
if match:
netname = "neigh_op_%s_%s" % (match.group(1), match.group(2))
@@ -739,8 +828,7 @@ def cmp_netnames(a, b):
def run_checks_neigh():
print("Running consistency checks on neighbour finder..")
ic = iceconfig()
- ic.max_x = 6
- ic.max_y = 6
+ ic.setup_empty_1k()
all_segments = set()
@@ -758,6 +846,10 @@ def run_checks_neigh():
continue
if x in (0, ic.max_x) or y in (0, ic.max_y):
add_segments((x, y), ic.tile_db(x, y))
+ elif (x, y) in ic.ramb_tiles:
+ add_segments((x, y), ic.tile_db(x, y))
+ elif (x, y) in ic.ramt_tiles:
+ add_segments((x, y), ic.tile_db(x, y))
else:
add_segments((x, y), logictile_db)
all_segments.add((x, y, "lutff_7/cout"))
@@ -789,13 +881,144 @@ def parse_db(text):
extra_bits_db = {
"1k": {
- (0, 331, 142): ("routing", "padin_1", "glb_netwk_1")
+ (0, 330, 142): ("padin_glb_netwk", "0"),
+ (0, 331, 142): ("padin_glb_netwk", "1"),
+ (1, 330, 143): ("padin_glb_netwk", "2"),
+ (1, 331, 143): ("padin_glb_netwk", "3"),
+ (1, 330, 142): ("padin_glb_netwk", "4"),
+ (1, 331, 142): ("padin_glb_netwk", "5"),
+ (0, 330, 143): ("padin_glb_netwk", "6"),
+ (0, 331, 143): ("padin_glb_netwk", "7"),
}
}
+gbufin_db = {
+ "1k": [
+ (13, 8, 7),
+ ( 0, 8, 6),
+ ( 7, 17, 1),
+ ( 7, 0, 0),
+ ( 0, 9, 3),
+ (13, 9, 2),
+ ( 6, 0, 5),
+ ( 6, 17, 4),
+ ]
+}
+
+icegate_db = {
+ "1k": [
+ ( 0, 7),
+ (13, 10),
+ ( 5, 0),
+ ( 8, 17)
+ ]
+}
+
+padin_pio_db = {
+ "1k": [
+ (13, 8, 1), # glb_netwk_0
+ ( 0, 8, 1), # glb_netwk_1
+ ( 7, 17, 0), # glb_netwk_2
+ ( 7, 0, 0), # glb_netwk_3
+ ( 0, 9, 0), # glb_netwk_4
+ (13, 9, 0), # glb_netwk_5
+ ( 6, 0, 1), # glb_netwk_6
+ ( 6, 17, 1), # glb_netwk_7
+ ]
+}
+
+ieren_db = {
+ "1k": [
+ # IO-block (X, Y, Z) <-> IeRen-block (X, Y, Z)
+ ( 0, 14, 1, 0, 14, 0),
+ ( 0, 14, 0, 0, 14, 1),
+ ( 0, 13, 1, 0, 13, 0),
+ ( 0, 13, 0, 0, 13, 1),
+ ( 0, 12, 1, 0, 12, 0),
+ ( 0, 12, 0, 0, 12, 1),
+ ( 0, 11, 1, 0, 11, 0),
+ ( 0, 11, 0, 0, 11, 1),
+ ( 0, 10, 1, 0, 10, 0),
+ ( 0, 10, 0, 0, 10, 1),
+ ( 0, 9, 1, 0, 9, 0),
+ ( 0, 8, 0, 0, 8, 1),
+ ( 0, 6, 1, 0, 6, 0),
+ ( 0, 6, 0, 0, 6, 1),
+ ( 0, 5, 1, 0, 5, 0),
+ ( 0, 5, 0, 0, 5, 1),
+ ( 0, 4, 1, 0, 4, 0),
+ ( 0, 4, 0, 0, 4, 1),
+ ( 0, 3, 1, 0, 3, 0),
+ ( 0, 3, 0, 0, 3, 1),
+ ( 0, 2, 1, 0, 2, 0),
+ ( 0, 2, 0, 0, 2, 1),
+ ( 1, 0, 0, 1, 0, 0),
+ ( 1, 0, 1, 1, 0, 1),
+ ( 2, 0, 1, 2, 0, 1),
+ ( 3, 0, 0, 3, 0, 0),
+ ( 3, 0, 1, 3, 0, 1),
+ ( 4, 0, 0, 4, 0, 0),
+ ( 4, 0, 1, 4, 0, 1),
+ ( 5, 0, 0, 5, 0, 0),
+ ( 5, 0, 1, 5, 0, 1),
+ ( 6, 0, 0, 7, 0, 0),
+ ( 7, 0, 1, 7, 0, 1),
+ ( 8, 0, 0, 8, 0, 0),
+ ( 8, 0, 1, 8, 0, 1),
+ ( 9, 0, 0, 9, 0, 0),
+ ( 9, 0, 1, 9, 0, 1),
+ (10, 0, 0, 10, 0, 0),
+ (10, 0, 1, 10, 0, 1),
+ (13, 1, 0, 13, 1, 0),
+ (13, 1, 1, 13, 1, 1),
+ (13, 2, 0, 13, 2, 0),
+ (13, 2, 1, 13, 2, 1),
+ (13, 3, 1, 13, 3, 1),
+ (13, 4, 0, 13, 4, 0),
+ (13, 4, 1, 13, 4, 1),
+ (13, 6, 0, 13, 6, 0),
+ (13, 6, 1, 13, 6, 1),
+ (13, 7, 0, 13, 7, 0),
+ (13, 7, 1, 13, 7, 1),
+ (13, 8, 0, 13, 8, 0),
+ (13, 9, 1, 13, 9, 1),
+ (13, 11, 0, 13, 10, 0),
+ (13, 11, 1, 13, 10, 1),
+ (13, 12, 0, 13, 11, 0),
+ (13, 13, 0, 13, 13, 0),
+ (13, 13, 1, 13, 13, 1),
+ (13, 14, 0, 13, 14, 0),
+ (13, 14, 1, 13, 14, 1),
+ (13, 15, 0, 13, 15, 0),
+ (13, 15, 1, 13, 15, 1),
+ (12, 17, 1, 12, 17, 1),
+ (12, 17, 0, 12, 17, 0),
+ (11, 17, 1, 11, 17, 1),
+ (11, 17, 0, 11, 17, 0),
+ (10, 17, 1, 9, 17, 1),
+ (10, 17, 0, 9, 17, 0),
+ ( 9, 17, 1, 10, 17, 1),
+ ( 9, 17, 0, 10, 17, 0),
+ ( 8, 17, 1, 8, 17, 1),
+ ( 8, 17, 0, 8, 17, 0),
+ ( 7, 17, 1, 7, 17, 1),
+ ( 5, 17, 1, 5, 17, 1),
+ ( 5, 17, 0, 5, 17, 0),
+ ( 4, 17, 1, 4, 17, 1),
+ ( 4, 17, 0, 4, 17, 0),
+ ( 3, 17, 1, 3, 17, 1),
+ ( 3, 17, 0, 3, 17, 0),
+ ( 2, 17, 1, 2, 17, 1),
+ ( 2, 17, 0, 2, 17, 0),
+ ( 1, 17, 1, 1, 17, 1),
+ ( 1, 17, 0, 1, 17, 0)
+ ]
+}
+
iotile_full_db = parse_db(iceboxdb.database_io_txt)
logictile_db = parse_db(iceboxdb.database_logic_txt)
-ramtile_db = parse_db(iceboxdb.database_ram_txt)
+rambtile_db = parse_db(iceboxdb.database_ramb_txt)
+ramttile_db = parse_db(iceboxdb.database_ramt_txt)
pinloc_db = [[int(s) for s in line.split()] for line in iceboxdb.pinloc_txt.split("\n") if line != ""]
iotile_l_db = list()
@@ -829,11 +1052,11 @@ for entry in iotile_full_db:
logictile_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"])
logictile_db.append([["B1[50]"], "CarryInSet"])
-for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, ramtile_db]:
+for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, rambtile_db, ramttile_db]:
for entry in db:
if entry[1] in ("buffer", "routing"):
- entry[2] = netname_normalize(entry[2])
- entry[3] = netname_normalize(entry[3])
+ entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
+ entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
unique_entries = dict()
while db:
entry = db.pop()
diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py
index 3441bd3..12ccfa8 100755
--- a/icebox/icebox_chipdb.py
+++ b/icebox/icebox_chipdb.py
@@ -40,10 +40,22 @@ print("""#
# Quick File Format Reference:
# ----------------------------
#
+# .device DEVICE
+#
+# declares the device type (e.g. "1k")
+#
+#
+# .pins PACKAGE
+# PIN_NUM TILE_X TILE_Y PIO_NUM PADIN_NUM
+# ...
+#
+# associates a package pin with an IO tile and block
+#
#
# .io_tile X Y
# .logic_tile X Y
-# .ram_tile X Y
+# .ramb_tile X Y
+# .ramt_tile X Y
#
# declares the existence of a IO/LOGIC/RAM tile with the given coordinates
#
@@ -73,6 +85,18 @@ print("""#
#
""")
+print(".device 1k")
+print()
+
+print(".pins tq144")
+pio_to_padin = dict()
+for padin, pio in enumerate(ic.padin_pio_db()):
+ pio_to_padin[pio] = padin
+for entry in sorted(ic.pinloc_db()):
+ pio = (entry[1], entry[2], entry[3])
+ print("%d %d %d %d %d" % tuple(entry + [pio_to_padin[pio] if pio in pio_to_padin else -1]))
+print()
+
for idx in sorted(ic.io_tiles):
print(".io_tile %d %d" % idx)
print()
@@ -81,8 +105,12 @@ for idx in sorted(ic.logic_tiles):
print(".logic_tile %d %d" % idx)
print()
-for idx in sorted(ic.ram_tiles):
- print(".ram_tile %d %d" % idx)
+for idx in sorted(ic.ramb_tiles):
+ print(".ramb_tile %d %d" % idx)
+print()
+
+for idx in sorted(ic.ramt_tiles):
+ print(".ramt_tile %d %d" % idx)
print()
for group in sorted(ic.group_segments(all_tiles)):
diff --git a/icebox/icebox_diff.py b/icebox/icebox_diff.py
index d1790a9..da7962b 100755
--- a/icebox/icebox_diff.py
+++ b/icebox/icebox_diff.py
@@ -53,5 +53,6 @@ def diff_tiles(stmt, tiles1, tiles2):
diff_tiles(".io_tile", ic1.io_tiles, ic2.io_tiles)
diff_tiles(".logic_tile", ic1.logic_tiles, ic2.logic_tiles)
-diff_tiles(".ram_tile", ic1.ram_tiles, ic2.ram_tiles)
+diff_tiles(".ramb_tile", ic1.ramb_tiles, ic2.ramb_tiles)
+diff_tiles(".ramt_tile", ic1.ramt_tiles, ic2.ramt_tiles)
diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py
index e2ca0e8..346c273 100755
--- a/icebox/icebox_explain.py
+++ b/icebox/icebox_explain.py
@@ -24,10 +24,11 @@ import getopt, sys, re
print_bits = False
print_map = False
single_tile = None
+print_all = False
def usage():
print("""
-Usage: icebox_explain [options] <bitmap.txt>
+Usage: icebox_explain [options] [bitmap.txt]
-b
print config bit names for each config statement
@@ -35,13 +36,16 @@ Usage: icebox_explain [options] <bitmap.txt>
-m
print tile config bitmaps
+ -A
+ don't skip uninteresting tiles
+
-t '<x-coordinate> <y-coordinate>'
print only the specified tile
""")
sys.exit(0)
try:
- opts, args = getopt.getopt(sys.argv[1:], "bmt:")
+ opts, args = getopt.getopt(sys.argv[1:], "bmAt:")
except:
usage()
@@ -50,11 +54,19 @@ for o, a in opts:
print_bits = True
elif o == "-m":
print_map = True
+ elif o == "-A":
+ print_all = True
elif o == "-t":
single_tile = tuple([int(s) for s in a.split()])
else:
usage()
+if len(args) == 0:
+ args.append("/dev/stdin")
+
+if len(args) != 1:
+ usage()
+
print("Reading file '%s'.." % args[0])
ic = icebox.iceconfig()
ic.read_file(args[0])
@@ -96,7 +108,7 @@ def print_tile(stmt, ic, x, y, tile, db):
text_default_mask |= 1
if entry[1] == "IoCtrl" and entry[2] == "IE_1":
text_default_mask |= 2
- if entry[1] == "RamConfig" and entry[2] == "MEMB_Power_Up_Control":
+ if entry[1] == "RamConfig" and entry[2] == "PowerUp":
text_default_mask |= 4
if print_bits:
text.add("<%s> %s" % (" ".join(entry[0]), " ".join(entry[1:])))
@@ -130,12 +142,12 @@ def print_tile(stmt, ic, x, y, tile, db):
if lutff_options[2] == "1": lutff_options += " Set_NoReset"
if lutff_options[3] == "1": lutff_options += " AsyncSetReset"
text.add("LC_%d %s %s" % (lcidx, "".join(icebox.get_lutff_lut_bits(tile, lcidx)), lutff_options))
- if not print_bitinfo:
+ if not print_bitinfo and not print_all:
if text_default_mask == 3 and len(text) == 2:
return
if text_default_mask == 4 and len(text) == 1:
return
- if len(text) or print_bitinfo:
+ if len(text) or print_bitinfo or print_all:
print("\n%s" % stmt)
if print_bitinfo:
print("Warning: No DB entries for some bits:")
@@ -151,8 +163,11 @@ for idx in ic.io_tiles:
for idx in ic.logic_tiles:
print_tile(".logic_tile %d %d" % idx, ic, idx[0], idx[1], ic.logic_tiles[idx], ic.tile_db(idx[0], idx[1]))
-for idx in ic.ram_tiles:
- print_tile(".ram_tile %d %d" % idx, ic, idx[0], idx[1], ic.ram_tiles[idx], ic.tile_db(idx[0], idx[1]))
+for idx in ic.ramb_tiles:
+ print_tile(".ramb_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramb_tiles[idx], ic.tile_db(idx[0], idx[1]))
+
+for idx in ic.ramt_tiles:
+ print_tile(".ramt_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramt_tiles[idx], ic.tile_db(idx[0], idx[1]))
for bit in ic.extra_bits:
print()
diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py
index f7ebd67..880714f 100755
--- a/icebox/icebox_html.py
+++ b/icebox/icebox_html.py
@@ -47,12 +47,15 @@ for o, a in opts:
else:
usage()
+if len(args) != 0:
+ usage()
+
ic = icebox.iceconfig()
ic.setup_empty_1k()
mktiles = set()
-for x in range(1, 6) + range(8, 13):
+for x in range(1, 13):
mktiles.add((x, 0))
mktiles.add((x, 17))
@@ -64,6 +67,10 @@ for x in range(0, 5) + range(9, 14):
mktiles.add((x, 2))
mktiles.add((x, 15))
+for y in range(7, 11):
+ mktiles.add((0, y))
+ mktiles.add((13, y))
+
for x in range(6, 8):
for y in range(8, 10):
mktiles.add((x, y))
@@ -94,7 +101,7 @@ A machine-readable form of the database can be downloaded <a href="chipdb.txt">h
print("""<p>The iCE40 FPGA fabric is organized into tiles. The configuration bits
themself have the same meaning in all tiles of the same type. But the way the tiles
are connected to each other depends on the types of neighbouring cells. Furthermore,
-some wire names are different for (e.g.) a IO tile on the left border and an IO tile on
+some wire names are different for e.g. an IO tile on the left border and an IO tile on
the top border.</p>""")
print("""<p>Click on a highlighted tile below to view the bitstream details for the
@@ -111,12 +118,14 @@ in iCE40 FPGAs.</p>""")
elif (x, y) in mktiles:
if ic.tile_type(x, y) == "IO": color = "#aee"
if ic.tile_type(x, y) == "LOGIC": color = "#eae"
- if ic.tile_type(x, y) == "RAM": color = "#eea"
+ if ic.tile_type(x, y) == "RAMB": color = "#eea"
+ if ic.tile_type(x, y) == "RAMT": color = "#eea"
print('bgcolor="%s"><small><a style="color:#000; text-decoration:none" href="tile_%d_%d.html"><b>%s<br/>(%d %d)</b></a></small></td>' % (color, x, y, ic.tile_type(x, y), x, y))
else:
if ic.tile_type(x, y) == "IO": color = "#8aa"
if ic.tile_type(x, y) == "LOGIC": color = "#a8a"
- if ic.tile_type(x, y) == "RAM": color = "#aa8"
+ if ic.tile_type(x, y) == "RAMB": color = "#aa8"
+ if ic.tile_type(x, y) == "RAMT": color = "#aa8"
print('bgcolor="%s"><small>%s<br/>(%d %d)</small></td>' % (color, ic.tile_type(x, y), x, y))
print("</tr>")
print("</table></p>")
@@ -147,12 +156,14 @@ configuration bits it has and how it is connected to its neighbourhood.</p>""" %
if (x, y) in mktiles:
if ic.tile_type(x, y) == "IO": color = "#aee"
if ic.tile_type(x, y) == "LOGIC": color = "#eae"
- if ic.tile_type(x, y) == "RAM": color = "#eea"
+ if ic.tile_type(x, y) == "RAMB": color = "#eea"
+ if ic.tile_type(x, y) == "RAMT": color = "#eea"
print('bgcolor="%s"><a style="color:#000; text-decoration:none" href="tile_%d_%d.html"><b>%s Tile<br/>(%d %d)</b></a></td>' % (color, x, y, ic.tile_type(x, y), x, y))
else:
if ic.tile_type(x, y) == "IO": color = "#8aa"
if ic.tile_type(x, y) == "LOGIC": color = "#a8a"
- if ic.tile_type(x, y) == "RAM": color = "#aa8"
+ if ic.tile_type(x, y) == "RAMB": color = "#aa8"
+ if ic.tile_type(x, y) == "RAMT": color = "#aa8"
print('bgcolor="%s">%s Tile<br/>(%d %d)</td>' % (color, ic.tile_type(x, y), x, y))
visible_tiles.add((x, y))
print("</tr>")
@@ -200,11 +211,13 @@ configuration bits it has and how it is connected to its neighbourhood.</p>""" %
elif entry[1].startswith("IOB_"):
bitmap_cells[idx1][idx2]["label"] = "I"
elif entry[1].startswith("IoCtrl"):
- bitmap_cells[idx1][idx2]["label"] = "I"
+ bitmap_cells[idx1][idx2]["label"] = "T"
+ elif entry[1] == "Icegate":
+ bitmap_cells[idx1][idx2]["label"] = "G"
elif entry[1].startswith("Cascade"):
bitmap_cells[idx1][idx2]["label"] = "A"
elif entry[1].startswith("RamConfig"):
- bitmap_cells[idx1][idx2]["label"] = "R"
+ bitmap_cells[idx1][idx2]["label"] = "M"
else:
assert False
bitmap_cells[idx1][idx2]["label"] = '<a style="color:#666; text-decoration:none" href="#B.%d.%d">%s</a>' % (idx1, idx2, bitmap_cells[idx1][idx2]["label"])
@@ -264,6 +277,7 @@ nets are connected with nets from cells in its neighbourhood.</p>""")
if netname.startswith("local_"): cat = (20, "Local Tracks")
if netname.startswith("carry_in"): cat = (25, "Logic Block")
if netname.startswith("io_"): cat = (25, "IO Block")
+ if netname.startswith("ram"): cat = (25, "RAM Block")
if netname.startswith("lutff_"): cat = (25, "Logic Block")
if netname.startswith("lutff_0"): cat = (30, "Logic Unit 0")
if netname.startswith("lutff_1"): cat = (30, "Logic Unit 1")
diff --git a/icebox/icebox_maps.py b/icebox/icebox_maps.py
index 81ce919..ff90eb1 100755
--- a/icebox/icebox_maps.py
+++ b/icebox/icebox_maps.py
@@ -31,7 +31,8 @@ def usage():
print(" icebox_maps -m io_tile_nets_t")
print(" icebox_maps -m io_tile_nets_b")
print(" icebox_maps -m logic_tile_nets")
- print(" icebox_maps -m ram_tile_nets")
+ print(" icebox_maps -m ramb_tile_nets")
+ print(" icebox_maps -m ramt_tile_nets")
sys.exit(0)
try:
@@ -45,6 +46,9 @@ for o, a in opts:
else:
usage()
+if len(args) != 0:
+ usage()
+
def get_bit_group(x, y, db):
bit = "B%d[%d]" % (y, x)
nbit = "!B%d[%d]" % (y, x)
@@ -113,7 +117,8 @@ if mode == "bitmaps":
print_tilemap(".io_tile_bitmap_t", icebox.iotile_t_db, 18)
print_tilemap(".io_tile_bitmap_b", icebox.iotile_b_db, 18)
print_tilemap(".logic_tile_bitmap", icebox.logictile_db, 54)
- print_tilemap(".ram_tile_bitmap", icebox.ramtile_db, 42)
+ print_tilemap(".ramb_tile_bitmap", icebox.rambtile_db, 42)
+ print_tilemap(".ramt_tile_bitmap", icebox.ramttile_db, 42)
print()
print(".bitmap_legend")
print("- ... unknown bit")
@@ -144,8 +149,11 @@ elif mode == "io_tile_nets_b":
elif mode == "logic_tile_nets":
print_db_nets(".logic_tile_nets", icebox.logictile_db, "c")
-elif mode == "ram_tile_nets":
- print_db_nets(".ram_tile_nets", icebox.ramtile_db, "c")
+elif mode == "ramb_tile_nets":
+ print_db_nets(".ramb_tile_nets", icebox.ramtile_db, "c")
+
+elif mode == "ramt_tile_nets":
+ print_db_nets(".ramt_tile_nets", icebox.ramtile_db, "c")
else:
usage()
diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index ded96a6..acf7913 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -24,15 +24,16 @@ import getopt, sys, re
strip_comments = False
strip_interconn = False
lookup_pins = False
+check_ieren = False
+check_driver = False
pcf_data = dict()
portnames = set()
unmatched_ports = set()
-auto_clk = False
-auto_en = False
+modname = "chip"
def usage():
print("""
-Usage: icebox_vlog [options] <bitmap.txt>
+Usage: icebox_vlog [options] [bitmap.txt]
-s
strip comments from output
@@ -40,24 +41,29 @@ Usage: icebox_vlog [options] <bitmap.txt>
-S
strip comments about interconn wires from output
- -a
- auto-detect global clock and enable signals
- (require ports "clk" and "en" in pcf file)
-
-l
convert io tile port names to chip pin numbers
+ -n <module-name>
+ name for the exported module (default: "chip")
+
-p <pcf-file>
use the set_io command from the specified pcf file
-P <pcf-file>
like -p, enable some hacks for pcf files created
by the iCEcube2 placer.
+
+ -R
+ enable IeRen database checks
+
+ -D
+ enable exactly-one-driver checks
""")
sys.exit(0)
try:
- opts, args = getopt.getopt(sys.argv[1:], "sSlap:P:")
+ opts, args = getopt.getopt(sys.argv[1:], "sSlap:P:n:RD")
except:
usage()
@@ -68,18 +74,22 @@ for o, a in opts:
strip_interconn = True
elif o == "-l":
lookup_pins = True
+ elif o == "-n":
+ modname = a
elif o == "-a":
- auto_clk = True
- auto_en = True
+ pass # ignored for backward compatibility
elif o in ("-p", "-P"):
with open(a, "r") as f:
for line in f:
+ if o == "-P" and not re.search(" # ICE_(GB_)?IO", line):
+ continue
line = re.sub(r"#.*", "", line.strip()).split()
if len(line) and line[0] == "set_io":
p = line[1]
if o == "-P":
p = p.lower()
p = p.replace("_ibuf", "")
+ p = p.replace("_obuft", "")
p = p.replace("_obuf", "")
p = p.replace("_gb_io", "")
portnames.add(p)
@@ -88,9 +98,19 @@ for o, a in opts:
unmatched_ports.add(p)
pinloc = tuple([int(s) for s in line[2:]])
pcf_data[pinloc] = p
+ elif o == "-R":
+ check_ieren = True
+ elif o == "-D":
+ check_driver = True
else:
usage()
+if len(args) == 0:
+ args.append("/dev/stdin")
+
+if len(args) != 1:
+ usage()
+
if not strip_comments:
print("// Reading file '%s'.." % args[0])
ic = icebox.iceconfig()
@@ -102,13 +122,19 @@ text_ports = list()
luts_queue = set()
text_func = list()
+failed_drivers_check = list()
netidx = [0]
nets = dict()
seg2net = dict()
-auto_clk_nets = set()
-auto_en_nets = set()
+iocells = set()
+iocells_in = set()
+iocells_out = set()
+iocells_special = set()
+iocells_type = dict()
+iocells_negclk = set()
+iocells_inbufs = set()
def is_interconn(netname):
if netname.startswith("sp4_"): return True
@@ -120,27 +146,93 @@ def is_interconn(netname):
if netname.startswith("local_"): return True
return False
+extra_connections = list()
+extra_segments = list()
+
+for bit in ic.extra_bits:
+ entry = ic.lookup_extra_bit(bit)
+ if entry[0] == "padin_glb_netwk":
+ glb = int(entry[1])
+ pin_entry = ic.padin_pio_db()[glb]
+ iocells.add((pin_entry[0], pin_entry[1], pin_entry[2]))
+ iocells_in.add((pin_entry[0], pin_entry[1], pin_entry[2]))
+ s1 = (pin_entry[0], pin_entry[1], "io_%d/PAD" % pin_entry[2])
+ s2 = (pin_entry[0], pin_entry[1], "wire_gbuf/padin_%d" % pin_entry[2])
+ extra_connections.append((s1, s2))
+
+for idx, tile in ic.io_tiles.items():
+ tc = icebox.tileconfig(tile)
+ iocells_type[(idx[0], idx[1], 0)] = ["0" for i in range(6)]
+ iocells_type[(idx[0], idx[1], 1)] = ["0" for i in range(6)]
+ for entry in ic.tile_db(idx[0], idx[1]):
+ if check_ieren and entry[1] == "IoCtrl" and entry[2].startswith("IE_") and not tc.match(entry[0]):
+ iren_idx = (idx[0], idx[1], 0 if entry[2] == "IE_0" else 1)
+ for iren_entry in ic.ieren_db():
+ if iren_idx[0] == iren_entry[3] and iren_idx[1] == iren_entry[4] and iren_idx[2] == iren_entry[5]:
+ iocells_inbufs.add((iren_entry[0], iren_entry[1], iren_entry[2]))
+ if entry[1] == "NegClk" and tc.match(entry[0]):
+ iocells_negclk.add((idx[0], idx[1], 0))
+ iocells_negclk.add((idx[0], idx[1], 1))
+ if entry[1].startswith("IOB_") and entry[2].startswith("PINTYPE_") and tc.match(entry[0]):
+ match1 = re.match("IOB_(\d+)", entry[1])
+ match2 = re.match("PINTYPE_(\d+)", entry[2])
+ assert match1 and match2
+ iocells_type[(idx[0], idx[1], int(match1.group(1)))][int(match2.group(1))] = "1"
+ iocells_type[(idx[0], idx[1], 0)] = "".join(iocells_type[(idx[0], idx[1], 0)])
+ iocells_type[(idx[0], idx[1], 1)] = "".join(iocells_type[(idx[0], idx[1], 1)])
+
for segs in sorted(ic.group_segments()):
+ for seg in segs:
+ if ic.tile_type(seg[0], seg[1]) == "IO":
+ match = re.match("io_(\d+)/D_(IN|OUT)_(\d+)", seg[2])
+ if match:
+ cell = (seg[0], seg[1], int(match.group(1)))
+ iocells.add(cell)
+ if match.group(2) == "IN":
+ if check_ieren:
+ assert cell in iocells_inbufs
+ if iocells_type[cell] != "100000" or match.group(3) != "0":
+ iocells_special.add(cell)
+ iocells_in.add(cell)
+ if match.group(2) == "OUT" and iocells_type[cell][2:6] != "0000":
+ if iocells_type[cell] != "100110" or match.group(3) != "0":
+ iocells_special.add(cell)
+ iocells_out.add(cell)
+ extra_segments.append((seg[0], seg[1], "io_%d/PAD" % int(match.group(1))))
+
+for cell in iocells:
+ if iocells_type[cell] == "100110" and not cell in iocells_special:
+ s1 = (cell[0], cell[1], "io_%d/PAD" % cell[2])
+ s2 = (cell[0], cell[1], "io_%d/D_OUT_0" % cell[2])
+ extra_connections.append((s1, s2))
+ del iocells_type[cell]
+ elif iocells_type[cell] == "100000" and not cell in iocells_special:
+ s1 = (cell[0], cell[1], "io_%d/PAD" % cell[2])
+ s2 = (cell[0], cell[1], "io_%d/D_IN_0" % cell[2])
+ extra_connections.append((s1, s2))
+ del iocells_type[cell]
+
+def next_netname():
while True:
netidx[0] += 1
n = "n%d" % netidx[0]
- if n not in portnames: break
+ if n not in portnames:
+ return n
+for segs in sorted(ic.group_segments(extra_connections=extra_connections, extra_segments=extra_segments)):
+ n = next_netname()
net_segs = set()
renamed_net_to_port = False
for s in segs:
- match = re.match("io_(\d+)/D_(IN|OUT)_(\d+)$", s[2])
+ match = re.match("io_(\d+)/PAD", s[2])
if match:
- if match.group(2) == "IN":
- p = "io_%d_%d_%s_din_%s" % (s[0], s[1], match.group(1), match.group(3))
- net_segs.add(p)
- else:
- p = "io_%d_%d_%s_dout_%s" % (s[0], s[1], match.group(1), match.group(3))
- net_segs.add(p)
+ idx = (s[0], s[1], int(match.group(1)))
+ p = "io_%d_%d_%d" % idx
+ net_segs.add(p)
if lookup_pins or pcf_data:
for entry in icebox.pinloc_db:
- if s[0] == entry[1] and s[1] == entry[2] and int(match.group(1)) == entry[3]:
+ if idx[0] == entry[1] and idx[1] == entry[2] and idx[2] == entry[3]:
if (entry[0],) in pcf_data:
p = pcf_data[(entry[0],)]
unmatched_ports.discard(p)
@@ -149,24 +241,25 @@ for segs in sorted(ic.group_segments()):
unmatched_ports.discard(p)
elif lookup_pins:
p = "pin_%d" % entry[0]
- if p == "clk":
- auto_clk = False
- if p == "en":
- auto_en = False
if not renamed_net_to_port:
n = p
- if match.group(2) == "IN":
+ if idx in iocells_in and idx not in iocells_out:
text_ports.append("input %s" % p)
- else:
+ elif idx not in iocells_in and idx in iocells_out:
text_ports.append("output %s" % p)
+ else:
+ text_ports.append("inout %s" % p)
text_wires.append("wire %s;" % n)
renamed_net_to_port = True
- elif match.group(2) == "IN":
+ elif idx in iocells_in and idx not in iocells_out:
text_ports.append("input %s" % p)
text_wires.append("assign %s = %s;" % (n, p))
- else:
+ elif idx not in iocells_in and idx in iocells_out:
text_ports.append("output %s" % p)
text_wires.append("assign %s = %s;" % (p, n))
+ else:
+ text_ports.append("inout %s" % p)
+ text_wires.append("assign %s = %s;" % (p, n))
match = re.match("lutff_(\d+)/", s[2])
if match:
@@ -187,60 +280,27 @@ for segs in sorted(ic.group_segments()):
else:
net_segs.add(s)
- if not renamed_net_to_port:
- has_clk = False
- has_cen = False
- has_global = False
- has_driver = False
- for s in sorted(net_segs):
- if s[2].startswith("glb_netwk_"):
- has_global = True
- elif re.search(r"/out", s[2]):
- has_driver = True
- elif s[2] == "lutff_global/clk":
- has_clk = True
- elif s[2] == "lutff_global/cen":
- has_cen = True
- if has_global and not has_driver:
- if has_clk:
- auto_clk_nets.add(n)
- if has_cen and not has_clk:
- auto_en_nets.add(n)
+ count_drivers = 0
+ for s in segs:
+ if re.match(r"ram/RDATA_", s[2]): count_drivers += 1
+ if re.match(r"io_./D_IN_", s[2]): count_drivers += 1
+ if re.match(r"lutff_./out", s[2]): count_drivers += 1
+
+ if count_drivers != 1 and check_driver:
+ failed_drivers_check.append(n)
if not strip_comments:
for s in sorted(net_segs):
text_wires.append("// %s" % (s,))
+ if count_drivers != 1 and check_driver:
+ text_wires.append("// Number of drivers: %d" % count_drivers)
text_wires.append("")
-for p in unmatched_ports:
- text_ports.append("input %s" % p)
-
-if auto_clk and auto_clk_nets and "clk" in unmatched_ports:
- assert len(auto_clk_nets) == 1
- if not strip_comments:
- text_wires.append("// automatically detected clock network")
- text_wires.append("assign %s = clk;" % auto_clk_nets.pop())
- if not strip_comments:
- text_wires.append("")
- unmatched_ports.remove("clk")
-
-if auto_en and auto_en_nets and "en" in unmatched_ports:
- assert len(auto_en_nets) == 1
- if not strip_comments:
- text_wires.append("// automatically detected enable network")
- text_wires.append("assign %s = en;" % auto_en_nets.pop())
- if not strip_comments:
- text_wires.append("")
- unmatched_ports.remove("en")
-
def seg_to_net(seg, default=None):
if seg not in seg2net:
if default is not None:
return default
- while True:
- netidx[0] += 1
- n = "n%d" % netidx[0]
- if n not in portnames: break
+ n = next_netname()
nets[n] = set([seg])
seg2net[seg] = n
text_wires.append("wire %s;" % n)
@@ -250,6 +310,134 @@ def seg_to_net(seg, default=None):
text_wires.append("")
return seg2net[seg]
+for cell in iocells:
+ if cell in iocells_type:
+ net_pad = seg_to_net((cell[0], cell[1], "io_%d/PAD" % cell[2]))
+ net_din0 = seg_to_net((cell[0], cell[1], "io_%d/D_IN_0" % cell[2]), "")
+ net_din1 = seg_to_net((cell[0], cell[1], "io_%d/D_IN_1" % cell[2]), "")
+ net_dout0 = seg_to_net((cell[0], cell[1], "io_%d/D_OUT_0" % cell[2]), "0")
+ net_dout1 = seg_to_net((cell[0], cell[1], "io_%d/D_OUT_1" % cell[2]), "0")
+ net_oen = seg_to_net((cell[0], cell[1], "io_%d/OUT_ENB" % cell[2]), "1")
+ net_cen = seg_to_net((cell[0], cell[1], "io_global/cen"), "1")
+ net_iclk = seg_to_net((cell[0], cell[1], "io_global/inclk"), "0")
+ net_oclk = seg_to_net((cell[0], cell[1], "io_global/outclk"), "0")
+ net_latch = seg_to_net((cell[0], cell[1], "io_global/latch"), "0")
+ iotype = iocells_type[cell]
+
+ if cell in iocells_negclk:
+ posedge = "negedge"
+ negedge = "posedge"
+ else:
+ posedge = "posedge"
+ negedge = "negedge"
+
+ text_func.append("// IO Cell %s" % (cell,))
+ if not strip_comments:
+ text_func.append("// PAD = %s" % net_pad)
+ text_func.append("// D_IN_0 = %s" % net_din0)
+ text_func.append("// D_IN_1 = %s" % net_din1)
+ text_func.append("// D_OUT_0 = %s" % net_dout0)
+ text_func.append("// D_OUT_1 = %s" % net_dout1)
+ text_func.append("// OUT_ENB = %s" % net_oen)
+ text_func.append("// CLK_EN = %s" % net_cen)
+ text_func.append("// IN_CLK = %s" % net_iclk)
+ text_func.append("// OUT_CLK = %s" % net_oclk)
+ text_func.append("// LATCH = %s" % net_latch)
+ text_func.append("// TYPE = %s (LSB:MSB)" % iotype)
+
+ if net_din0 != "" or net_din1 != "":
+ if net_cen == "1":
+ icen_cond = ""
+ else:
+ icen_cond = "if (%s) " % net_cen
+
+ if net_din0 != "":
+ if iotype[1] == "0" and iotype[0] == "0":
+ reg_din0 = next_netname()
+ text_func.append("reg %s;" % reg_din0)
+ text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_iclk, icen_cond, reg_din0, net_pad))
+ text_func.append("assign %s = %s;" % (net_din0, reg_din0))
+
+ if iotype[1] == "0" and iotype[0] == "1":
+ text_func.append("assign %s = %s;" % (net_din0, net_pad))
+
+ if iotype[1] == "1" and iotype[0] == "0":
+ reg_din0 = next_netname()
+ reg_din0_latched = next_netname()
+ text_func.append("reg %s, %s;" % (reg_din0, reg_din0_latched))
+ text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_iclk, icen_cond, reg_din0, net_pad))
+ text_func.append("always @* if (!%s) %s = %s;" % (net_latch, reg_din0_latched, reg_din0))
+ text_func.append("assign %s = %s;" % (net_din0, reg_din0_latched))
+
+ if iotype[1] == "1" and iotype[0] == "1":
+ reg_din0 = next_netname()
+ text_func.append("reg %s;" % reg_din0)
+ text_func.append("always @* if (!%s) %s = %s;" % (net_latch, reg_din0, net_pad))
+ text_func.append("assign %s = %s;" % (net_din0, reg_din0))
+
+ if net_din1 != "":
+ reg_din1 = next_netname()
+ text_func.append("reg %s;" % reg_din1)
+ text_func.append("always @(%s %s) %s%s <= %s;" % (negedge, net_iclk, icen_cond, reg_din1, net_pad))
+ text_func.append("assign %s = %s;" % (net_din1, reg_din1))
+
+ if iotype[5] != "0" or iotype[4] != "0":
+ if net_cen == "1":
+ ocen_cond = ""
+ else:
+ ocen_cond = "if (%s) " % net_cen
+
+ # effective OEN: iotype[4], iotype[5]
+
+ if iotype[5] == "0" and iotype[4] == "1":
+ eff_oen = "1"
+
+ if iotype[5] == "1" and iotype[4] == "0":
+ eff_oen = net_oen
+
+ if iotype[5] == "1" and iotype[4] == "1":
+ eff_oen = next_netname()
+ text_func.append("reg %s;" % eff_oen)
+ text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, eff_oen, net_oen))
+
+ # effective DOUT: iotype[2], iotype[3]
+
+ if iotype[2] == "0" and iotype[3] == "0":
+ ddr_posedge = next_netname()
+ ddr_negedge = next_netname()
+ text_func.append("reg %s, %s;" % (ddr_posedge, ddr_negedge))
+ text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, ddr_posedge, net_dout0))
+ text_func.append("always @(%s %s) %s%s <= %s;" % (negedge, net_oclk, ocen_cond, ddr_negedge, net_dout1))
+ eff_dout = next_netname()
+ text_func.append("wire %s;" % (eff_dout))
+ if cell in iocells_negclk:
+ text_func.append("assign %s = %s ? %s : %s;" % (eff_dout, net_oclk, ddr_negedge, ddr_posedge))
+ else:
+ text_func.append("assign %s = %s ? %s : %s;" % (eff_dout, net_oclk, ddr_posedge, ddr_negedge))
+
+ if iotype[2] == "0" and iotype[3] == "1":
+ eff_dout = net_dout0
+
+ if iotype[2] == "1" and iotype[3] == "0":
+ eff_dout = next_netname()
+ text_func.append("reg %s;" % eff_dout)
+ text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, eff_dout, net_dout0))
+
+ if iotype[2] == "1" and iotype[3] == "1":
+ eff_dout = next_netname()
+ text_func.append("reg %s;" % eff_dout)
+ text_func.append("always @(%s %s) %s%s <= !%s;" % (posedge, net_oclk, ocen_cond, eff_dout, net_dout0))
+
+ if eff_oen == "1":
+ text_func.append("assign %s = %s;" % (net_pad, eff_dout))
+ else:
+ text_func.append("assign %s = %s ? %s : 1'bz;" % (net_pad, eff_oen, eff_dout))
+
+ text_func.append("")
+
+for p in unmatched_ports:
+ text_ports.append("input %s" % p)
+
wire_to_reg = set()
lut_assigns = list()
const_assigns = list()
@@ -288,10 +476,7 @@ for lut in luts_queue:
carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" %
(lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)])
if seq_bits[1] == "1":
- while True:
- netidx[0] += 1
- n = "n%d" % netidx[0]
- if n not in portnames: break
+ n = next_netname()
text_wires.append("wire %s;" % n)
if not strip_comments:
text_wires.append("// FF %s" % (lut,))
@@ -332,7 +517,7 @@ for lut in luts_queue:
for a in const_assigns + lut_assigns + carry_assigns:
text_func.append("assign %-*s = %s;" % (max_net_len, a[0], a[1]))
-print("module chip (%s);\n" % ", ".join(text_ports))
+print("module %s (%s);\n" % (modname, ", ".join(text_ports)))
new_text_wires = list()
for line in text_wires:
@@ -365,3 +550,8 @@ if unmatched_ports:
print("endmodule")
print()
+if failed_drivers_check:
+ print("// Single-driver-check failed for %d nets:" % len(failed_drivers_check))
+ print("// %s" % " ".join(failed_drivers_check))
+ assert False
+
diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py
index dd4e0c7..2159b8d 100644
--- a/icebox/iceboxdb.py
+++ b/icebox/iceboxdb.py
@@ -1,12 +1,12 @@
database_io_txt = """
-B1[9] ColBufCtrl IO_half_column_clock_enable_0 B1[9]
-B0[9] ColBufCtrl IO_half_column_clock_enable_1 B0[9]
-B3[9] ColBufCtrl IO_half_column_clock_enable_2 B3[9]
-B2[9] ColBufCtrl IO_half_column_clock_enable_3 B2[9]
-B5[9] ColBufCtrl IO_half_column_clock_enable_4 B5[9]
-B4[9] ColBufCtrl IO_half_column_clock_enable_5 B4[9]
-B7[9] ColBufCtrl IO_half_column_clock_enable_6 B7[9]
-B6[9] ColBufCtrl IO_half_column_clock_enable_7 B6[9]
+B1[9] ColBufCtrl glb_netwk_0
+B0[9] ColBufCtrl glb_netwk_1
+B3[9] ColBufCtrl glb_netwk_2
+B2[9] ColBufCtrl glb_netwk_3
+B5[9] ColBufCtrl glb_netwk_4
+B4[9] ColBufCtrl glb_netwk_5
+B7[9] ColBufCtrl glb_netwk_6
+B6[9] ColBufCtrl glb_netwk_7
B3[17] IOB_0 PINTYPE_0
B3[16] IOB_0 PINTYPE_1
B0[17] IOB_0 PINTYPE_2
@@ -19,8 +19,10 @@ B10[17] IOB_1 PINTYPE_2
B10[16] IOB_1 PINTYPE_3
B14[16] IOB_1 PINTYPE_4
B14[17] IOB_1 PINTYPE_5
+B11[3] Icegate
B9[3] IoCtrl IE_0
B6[3] IoCtrl IE_1
+B8[2] IoCtrl LVDS
B6[2] IoCtrl REN_0
B1[3] IoCtrl REN_1
B9[13],B15[13] NegClk
@@ -852,22 +854,22 @@ B13[11],!B13[12] routing span4_vert_t_15 span4_horz_43
!B13[13],B13[14] routing span4_vert_t_15 span4_vert_b_3
"""
database_logic_txt = """
-B0[1] ColBufCtrl LH_colbuf_cntl_0 B0[1]
-B9[7] ColBufCtrl LH_colbuf_cntl_0 B9[7]
-B1[2] ColBufCtrl LH_colbuf_cntl_1 B1[2]
-B8[7] ColBufCtrl LH_colbuf_cntl_1 B8[7]
-B11[7] ColBufCtrl LH_colbuf_cntl_2 B11[7]
-B5[2] ColBufCtrl LH_colbuf_cntl_2 B5[2]
-B10[7] ColBufCtrl LH_colbuf_cntl_3 B10[7]
-B7[2] ColBufCtrl LH_colbuf_cntl_3 B7[2]
-B13[7] ColBufCtrl LH_colbuf_cntl_4 B13[7]
-B9[2] ColBufCtrl LH_colbuf_cntl_4 B9[2]
-B11[2] ColBufCtrl LH_colbuf_cntl_5 B11[2]
-B12[7] ColBufCtrl LH_colbuf_cntl_5 B12[7]
-B13[2] ColBufCtrl LH_colbuf_cntl_6 B13[2]
-B15[7] ColBufCtrl LH_colbuf_cntl_6 B15[7]
-B14[7] ColBufCtrl LH_colbuf_cntl_7 B14[7]
-B15[2] ColBufCtrl LH_colbuf_cntl_7 B15[2]
+B0[1] ColBufCtrl glb_netwk_0
+B1[2] ColBufCtrl glb_netwk_1
+B5[2] ColBufCtrl glb_netwk_2
+B7[2] ColBufCtrl glb_netwk_3
+B9[2] ColBufCtrl glb_netwk_4
+B11[2] ColBufCtrl glb_netwk_5
+B13[2] ColBufCtrl glb_netwk_6
+B15[2] ColBufCtrl glb_netwk_7
+B9[7] ColBufCtrl reserved_0
+B8[7] ColBufCtrl reserved_1
+B11[7] ColBufCtrl reserved_2
+B10[7] ColBufCtrl reserved_3
+B13[7] ColBufCtrl reserved_4
+B12[7] ColBufCtrl reserved_5
+B15[7] ColBufCtrl reserved_6
+B14[7] ColBufCtrl reserved_7
B0[36],B0[37],B0[38],B0[39],B0[40],B0[41],B0[42],B0[43],B0[44],B0[45],B1[36],B1[37],B1[38],B1[39],B1[40],B1[41],B1[42],B1[43],B1[44],B1[45] LC_0
B2[36],B2[37],B2[38],B2[39],B2[40],B2[41],B2[42],B2[43],B2[44],B2[45],B3[36],B3[37],B3[38],B3[39],B3[40],B3[41],B3[42],B3[43],B3[44],B3[45] LC_1
B4[36],B4[37],B4[38],B4[39],B4[40],B4[41],B4[42],B4[43],B4[44],B4[45],B5[36],B5[37],B5[38],B5[39],B5[40],B5[41],B5[42],B5[43],B5[44],B5[45] LC_2
@@ -932,6 +934,7 @@ B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer bot_op_5 lc_trk_g1_5
!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0
!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1
!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3
!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_logic_cluster/lc_7/clk
!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_logic_cluster/lc_7/s_r
!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
@@ -2448,82 +2451,2502 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10
B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
"""
-database_ram_txt = """
-B6[7] Cascade MEMT_LC00_inmux00_bram_cbit_7
-B4[7] Cascade MEMT_LC01_inmux00_bram_cbit_5
-B7[7] Cascade MEMT_LC01_inmux00_bram_cbit_6
-B6[7] Cascade MEMT_LC01_inmux00_bram_cbit_7
-B5[7] Cascade MEMT_LC02_inmux00_bram_cbit_4
-B4[7] Cascade MEMT_LC02_inmux00_bram_cbit_5
-B5[7] Cascade MEMT_LC03_inmux00_bram_cbit_4
-B4[7] Cascade MEMT_LC03_inmux00_bram_cbit_5
-B7[7] Cascade MEMT_LC03_inmux00_bram_cbit_6
-B6[7] Cascade MEMT_LC03_inmux00_bram_cbit_7
-B5[7] Cascade MEMT_LC04_inmux00_bram_cbit_4
-B4[7] Cascade MEMT_LC04_inmux00_bram_cbit_5
-B7[7] Cascade MEMT_LC04_inmux00_bram_cbit_6
-B6[7] Cascade MEMT_LC04_inmux00_bram_cbit_7
-B7[7] Cascade MEMT_LC05_inmux00_bram_cbit_6
-B6[7] Cascade MEMT_LC05_inmux00_bram_cbit_7
-B5[7] Cascade MEMT_LC07_inmux00_bram_cbit_4
-B4[7] Cascade MEMT_LC07_inmux00_bram_cbit_5
-B0[1] ColBufCtrl MEMB_colbuf_cntl_0 B0[1]
-B1[2] ColBufCtrl MEMB_colbuf_cntl_1 B1[2]
-B11[7] ColBufCtrl MEMB_colbuf_cntl_2 B11[7]
-B5[2] ColBufCtrl MEMB_colbuf_cntl_2 B5[2]
-B7[2] ColBufCtrl MEMB_colbuf_cntl_3 B7[2]
-B13[7] ColBufCtrl MEMB_colbuf_cntl_4 B13[7]
-B9[2] ColBufCtrl MEMB_colbuf_cntl_4 B9[2]
-B11[2] ColBufCtrl MEMB_colbuf_cntl_5 B11[2]
-B13[2] ColBufCtrl MEMB_colbuf_cntl_6 B13[2]
-B15[2] ColBufCtrl MEMB_colbuf_cntl_7 B15[2]
-B11[7] ColBufCtrl MEMT_colbuf_cntl_2 B11[7]
-B1[7] RamConfig MEMB_Power_Up_Control
+database_ramb_txt = """
+B0[1] ColBufCtrl glb_netwk_0
+B1[2] ColBufCtrl glb_netwk_1
+B5[2] ColBufCtrl glb_netwk_2
+B7[2] ColBufCtrl glb_netwk_3
+B9[2] ColBufCtrl glb_netwk_4
+B11[2] ColBufCtrl glb_netwk_5
+B13[2] ColBufCtrl glb_netwk_6
+B15[2] ColBufCtrl glb_netwk_7
+B0[0] NegClk
+B1[7] RamConfig PowerUp
+B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
+!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0
+!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2
+!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4
+!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK
+!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE
+!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
+!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
+!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
+!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK
+!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE
+B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0
+B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1
+B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2
+B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3
+B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK
+!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE
+B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
+B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
+B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2
+B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK
+!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE
+!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
+!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
+!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
+!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
+!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK
+B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE
+!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0
+!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1
+!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2
+!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
+!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK
+B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE
+B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
+B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
+B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
+B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
+B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK
+B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE
+B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
+B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1
+B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
+B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3
+B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK
+B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4
+!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6
+!B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input2_0
+!B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input2_2
+!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_1
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_3
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_5
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_7
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3
+!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5
+!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7
+!B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input2_1
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_0
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_2
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_4
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_6
+!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0
+!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2
+!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4
+!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6
+!B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input2_0
+!B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input2_2
+!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_1
+!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_3
+!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_5
+!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_7
+!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE
+!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_1
+!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_3
+!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_5
+!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_7
+!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1
+!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3
+!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5
+!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7
+!B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input2_1
+!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_0
+!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_2
+!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_4
+!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_6
+!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_0
+!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_2
+!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_4
+!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_6
+B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0
+B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2
+B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4
+B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6
+B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input2_0
+B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input2_2
+B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_1
+B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_3
+B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_5
+B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_7
+!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_1
+!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_3
+!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_5
+!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_7
+!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE
+B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1
+B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3
+B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5
+B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7
+B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input2_1
+B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_0
+B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_2
+B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_4
+B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_6
+!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_0
+!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_2
+!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_4
+!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_6
+B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0
+B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2
+B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4
+B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6
+B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input2_0
+B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input2_2
+B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_1
+B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_3
+B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_5
+B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_7
+!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_1
+!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_3
+!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_5
+!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_7
+B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1
+B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3
+B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5
+B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7
+B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input2_1
+B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_0
+B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_2
+B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_4
+B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_6
+!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_0
+!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_2
+!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_4
+!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_6
+!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1
+!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3
+!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5
+!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7
+!B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input2_1
+!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_0
+!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_2
+!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_4
+!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_6
+B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_0
+B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_2
+B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_4
+B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_6
+!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0
+!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2
+!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4
+!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6
+!B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input2_0
+!B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input2_2
+!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_1
+!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_3
+!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_5
+!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_7
+!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK
+B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_1
+B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_3
+B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_5
+B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_7
+!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1
+!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3
+!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5
+!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7
+!B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input2_1
+!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_0
+!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_2
+!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_4
+!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_6
+B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_0
+B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_2
+B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_4
+B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_6
+!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0
+!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2
+!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4
+!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6
+!B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input2_0
+!B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input2_2
+!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_1
+!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_3
+!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_5
+!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_7
+!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE
+B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_1
+B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_3
+B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_5
+B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_7
+B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1
+B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3
+B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5
+B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7
+B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input2_1
+B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_0
+B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_2
+B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_4
+B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_6
+B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_0
+B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_2
+B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_4
+B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_6
+B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0
+B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2
+B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4
+B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6
+B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input2_0
+B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input2_2
+B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_1
+B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_3
+B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_5
+B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_7
+B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_1
+B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_3
+B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_5
+B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_7
+!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE
+B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1
+B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3
+B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5
+B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7
+B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input2_1
+B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_0
+B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_2
+B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_4
+B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_6
+B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_0
+B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_2
+B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_4
+B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_6
+B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0
+B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2
+B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4
+B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6
+B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input2_0
+B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input2_2
+B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_1
+B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_3
+B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_5
+B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_7
+B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_1
+B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_3
+B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_5
+B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_7
+!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0
+!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2
+!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4
+!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6
+!B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input2_0
+!B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input2_2
+!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_1
+!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_3
+!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_5
+!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_7
+B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK
+!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_1
+!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_3
+!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_5
+!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_7
+!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1
+!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3
+!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5
+!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7
+!B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input2_1
+!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_0
+!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_2
+!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_4
+!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_6
+!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_0
+!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_2
+!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_4
+!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_6
+!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0
+!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2
+!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4
+!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6
+!B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input2_0
+!B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input2_2
+!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_1
+!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_3
+!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_5
+!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_7
+B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE
+!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_1
+!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_3
+!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_5
+!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_7
+!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1
+!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3
+!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5
+!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7
+!B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input2_1
+!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_0
+!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_2
+!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_4
+!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_6
+!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_0
+!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_2
+!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_4
+!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_6
+B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0
+B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2
+B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4
+B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6
+B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input2_0
+B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input2_2
+B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_1
+B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_3
+B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_5
+B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_7
+!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_1
+!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_3
+!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_5
+!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_7
+B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE
+B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1
+B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3
+B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5
+B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7
+B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input2_1
+B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_0
+B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_2
+B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_4
+B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_6
+!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_0
+!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_2
+!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_4
+!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_6
+B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0
+B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2
+B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4
+B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6
+B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input2_0
+B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input2_2
+B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_1
+B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_3
+B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_5
+B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_7
+!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_1
+!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_3
+!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_5
+!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_7
+B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1
+B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3
+B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5
+B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7
+B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input2_1
+B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_0
+B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_2
+B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_4
+B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_6
+!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_0
+!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_2
+!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_4
+!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_6
+!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1
+!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3
+!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5
+!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7
+!B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input2_1
+!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_0
+!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_2
+!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_4
+!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_6
+B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_0
+B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_2
+B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_4
+B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_6
+!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0
+!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2
+!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4
+!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6
+!B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input2_0
+!B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input2_2
+!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_1
+!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_3
+!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_5
+!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_7
+B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK
+B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_1
+B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_3
+B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_5
+B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_7
+!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1
+!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3
+!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5
+!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7
+!B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input2_1
+!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_0
+!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_2
+!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_4
+!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_6
+B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_0
+B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_2
+B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_4
+B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_6
+!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0
+!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2
+!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4
+!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6
+!B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input2_0
+!B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input2_2
+!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_1
+!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_3
+!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_5
+!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_7
+B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE
+B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_1
+B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_3
+B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_5
+B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_7
+B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1
+B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3
+B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5
+B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7
+B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input2_1
+B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_0
+B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_2
+B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_4
+B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_6
+B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_0
+B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_2
+B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_4
+B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_6
+B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0
+B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2
+B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4
+B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6
+B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input2_0
+B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input2_2
+B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_1
+B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_3
+B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_5
+B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_7
+B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_1
+B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_3
+B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_5
+B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_7
+B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE
+B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1
+B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3
+B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5
+B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7
+B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input2_1
+B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_0
+B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_2
+B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_4
+B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_6
+B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_0
+B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_2
+B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_4
+B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_6
+B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0
+B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2
+B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4
+B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6
+B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input2_0
+B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input2_2
+B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_1
+B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_3
+B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_5
+B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_7
+B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_1
+B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_3
+B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_5
+B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_7
+B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7
+B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2
B12[19] buffer sp12_h_l_1 sp4_h_r_13
-B6[2] buffer sp12_h_l_13 sp4_h_r_19
+!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7
+!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1
+!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0
B8[2] buffer sp12_h_l_15 sp4_h_l_9
+!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2
B10[2] buffer sp12_h_l_17 sp4_h_r_21
-B14[2] buffer sp12_h_l_21 sp4_h_l_10
+B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7
+B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4
B15[19] buffer sp12_h_l_3 sp4_h_l_3
-B14[19] buffer sp12_h_l_5 sp4_h_l_2
+B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6
B14[19] buffer sp12_h_l_5 sp4_h_r_15
+!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2
B3[1] buffer sp12_h_l_9 sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0
B13[19] buffer sp12_h_r_0 sp4_h_l_1
-B13[19] buffer sp12_h_r_0 sp4_h_r_12
-B3[1] buffer sp12_h_r_10 sp4_h_r_17
-B4[2] buffer sp12_h_r_12 sp4_h_l_7
+B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1
+!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4
B4[2] buffer sp12_h_r_12 sp4_h_r_18
+!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6
B6[2] buffer sp12_h_r_14 sp4_h_l_6
-B8[2] buffer sp12_h_r_16 sp4_h_r_20
-B10[2] buffer sp12_h_r_18 sp4_h_l_8
-B12[19] buffer sp12_h_r_2 sp4_h_r_13
+!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
B12[2] buffer sp12_h_r_20 sp4_h_l_11
-B12[2] buffer sp12_h_r_20 sp4_h_r_22
+!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6
B14[2] buffer sp12_h_r_22 sp4_h_r_23
-B0[2] buffer sp12_h_r_8 sp4_h_l_5
+B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3
+B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7
+!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0
B0[2] buffer sp12_h_r_8 sp4_h_r_16
+!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1
B1[19] buffer sp12_v_b_1 sp4_v_b_12
-B1[19] buffer sp12_v_b_1 sp4_v_t_1
-B4[19] buffer sp12_v_b_11 sp4_v_b_17
+!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5
B7[19] buffer sp12_v_b_13 sp4_v_t_7
-B9[19] buffer sp12_v_b_17 sp4_v_b_20
+!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2
+!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3
B8[19] buffer sp12_v_b_19 sp4_v_t_8
-B11[19] buffer sp12_v_b_21 sp4_v_b_22
-B10[19] buffer sp12_v_b_23 sp4_v_t_10
+!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6
+B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3
B0[19] buffer sp12_v_b_3 sp4_v_b_13
+B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5
B3[19] buffer sp12_v_b_5 sp4_v_b_14
-B2[19] buffer sp12_v_b_7 sp4_v_t_2
+!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1
B5[19] buffer sp12_v_b_9 sp4_v_b_16
-B0[19] buffer sp12_v_t_0 sp4_v_b_13
-B7[19] buffer sp12_v_t_10 sp4_v_t_7
-B6[19] buffer sp12_v_t_12 sp4_v_b_19
+B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2
+!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4
+!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7
B6[19] buffer sp12_v_t_12 sp4_v_t_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1
B9[19] buffer sp12_v_t_14 sp4_v_b_20
-B8[19] buffer sp12_v_t_16 sp4_v_t_8
+!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5
B11[19] buffer sp12_v_t_18 sp4_v_t_11
+!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7
B10[19] buffer sp12_v_t_20 sp4_v_b_23
+B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7
B2[19] buffer sp12_v_t_4 sp4_v_t_2
+B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6
+!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0
+!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3
B4[19] buffer sp12_v_t_8 sp4_v_t_4
+B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4
+B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6
+!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2
+!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6
+B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3
+B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1
+B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6
+B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3
+B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4
+!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3
+B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7
+B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2
+!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7
+!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1
+!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4
+B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5
+!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3
+!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7
+B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0
+B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1
+B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2
+B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5
+!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4
+B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0
+B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3
+B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3
+B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4
+!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0
+B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1
+B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3
+B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3
+B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7
+B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2
+B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3
+B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4
+!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6
+!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1
+!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6
+B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2
+B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6
+B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1
+!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5
+B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6
+!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2
+!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7
+B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
+B0[37] buffer wire_bram/ram/RDATA_0 sp12_h_r_8
+B0[39] buffer wire_bram/ram/RDATA_0 sp12_v_b_0
+B1[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_16
+B1[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_0
+B1[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_16
+B0[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_32
+B1[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_1
+B0[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_17
+B0[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_33
+B1[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_0
+B1[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_16
+B0[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_32
+B2[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_9
+B3[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_18
+B2[39] buffer wire_bram/ram/RDATA_1 sp12_v_t_1
+B3[37] buffer wire_bram/ram/RDATA_1 sp4_h_r_18
+B3[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_2
+B2[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_34
+B2[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_19
+B3[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_3
+B2[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_35
+B3[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_2
+B2[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_34
+B3[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_7
+B4[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_12
+B5[40] buffer wire_bram/ram/RDATA_2 sp12_v_b_20
+B4[39] buffer wire_bram/ram/RDATA_2 sp12_v_b_4
+B5[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_9
+B4[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_36
+B5[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_4
+B4[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_21
+B4[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_37
+B5[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_5
+B5[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_20
+B5[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_4
+B4[38] buffer wire_bram/ram/RDATA_2 sp4_v_t_25
+B6[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_14
+B7[40] buffer wire_bram/ram/RDATA_3 sp12_v_b_22
+B6[39] buffer wire_bram/ram/RDATA_3 sp12_v_t_5
+B7[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_11
+B6[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_27
+B7[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_6
+B6[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_23
+B6[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_39
+B7[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_7
+B7[38] buffer wire_bram/ram/RDATA_3 sp4_v_b_6
+B7[39] buffer wire_bram/ram/RDATA_3 sp4_v_t_11
+B6[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_27
+B9[38] buffer wire_bram/ram/RDATA_4 sp12_h_l_15
+B8[37] buffer wire_bram/ram/RDATA_4 sp12_h_r_0
+B9[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_7
+B9[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_24
+B8[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_40
+B9[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_8
+B8[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_25
+B8[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_41
+B9[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_9
+B8[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_40
+B9[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_8
+B8[38] buffer wire_bram/ram/RDATA_4 sp4_v_t_13
+B10[37] buffer wire_bram/ram/RDATA_5 sp12_h_l_1
+B11[38] buffer wire_bram/ram/RDATA_5 sp12_h_l_17
+B11[40] buffer wire_bram/ram/RDATA_5 sp12_v_b_10
+B11[37] buffer wire_bram/ram/RDATA_5 sp4_h_l_15
+B11[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_10
+B10[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_42
+B11[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_11
+B10[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_27
+B10[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_43
+B11[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_10
+B10[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_15
+B10[39] buffer wire_bram/ram/RDATA_5 sp4_v_t_31
+B12[37] buffer wire_bram/ram/RDATA_6 sp12_h_l_3
+B13[38] buffer wire_bram/ram/RDATA_6 sp12_h_r_20
+B13[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_11
+B13[36] buffer wire_bram/ram/RDATA_6 sp4_h_l_1
+B13[37] buffer wire_bram/ram/RDATA_6 sp4_h_r_28
+B12[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_44
+B13[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_13
+B12[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_29
+B12[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_45
+B13[39] buffer wire_bram/ram/RDATA_6 sp4_v_b_12
+B12[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_28
+B12[39] buffer wire_bram/ram/RDATA_6 sp4_v_b_44
+B14[37] buffer wire_bram/ram/RDATA_7 sp12_h_l_5
+B15[38] buffer wire_bram/ram/RDATA_7 sp12_h_r_22
+B15[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_14
+B15[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_19
+B15[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_3
+B14[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_46
+B15[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_15
+B14[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_31
+B14[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_47
+B15[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_14
+B14[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_46
+B14[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_19
+!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1
+!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1
+!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22
+!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0
+!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0
+!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23
+B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23
+B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0
+B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23
+B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22
+B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1
+B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22
+!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23
+B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0
+B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23
+!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22
+B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1
+B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22
+B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22
+B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1
+B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1
+B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23
+B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0
+B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0
+B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1
+!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4
+!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9
+B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1
+B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7
+B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36
+!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43
+!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0
+B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3
+!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8
+B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0
+B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6
+!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37
+B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40
+!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11
+!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3
+B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6
+B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3
+B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9
+!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38
+B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45
+B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10
+!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2
+B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5
+!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2
+B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8
+!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39
+!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42
+B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1
+!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5
+B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8
+B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11
+!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5
+!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40
+!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47
+!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0
+B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4
+!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7
+B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10
+B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4
+B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41
+!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44
+!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10
+!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3
+B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7
+B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1
+B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7
+!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37
+B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42
+!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2
+!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6
+B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9
+B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0
+B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6
+!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43
+B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46
+B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0
+!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5
+!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9
+B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3
+B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9
+B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39
+!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44
+B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11
+B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4
+!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8
+B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2
+!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8
+!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36
+!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45
+!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11
+B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2
+B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7
+!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11
+B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5
+!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41
+!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46
+!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1
+B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10
+!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6
+B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10
+B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4
+!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38
+B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47
+!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37
+B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38
+!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45
+!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0
+B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5
+B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37
+B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43
+B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36
+!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41
+!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44
+B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1
+!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6
+B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36
+B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42
+!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36
+!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43
+B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47
+B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10
+!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3
+B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41
+B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47
+B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39
+B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42
+!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46
+!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11
+!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4
+B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40
+!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46
+!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39
+B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40
+B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47
+!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2
+!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7
+!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39
+B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45
+!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38
+B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43
+!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46
+!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3
+B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8
+B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38
+B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44
+!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37
+B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41
+!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42
+B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4
+!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9
+B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41
+B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47
+B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36
+!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40
+B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45
+!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10
+!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5
+!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40
+B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46
+!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39
+!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43
+B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44
+B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11
+!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6
+B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37
+B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43
+!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38
+B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42
+!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47
+!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0
+B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7
+B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36
+B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42
+B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41
+!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45
+B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46
+!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1
+!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8
+B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39
+!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45
+B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37
+!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40
+!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44
+B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2
+!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9
+B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38
+B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44
+B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37
+!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40
+B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0
+B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6
+B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37
+!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38
+B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45
+!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36
+!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43
+B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1
+B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7
+!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36
+B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41
+B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44
+!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38
+!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47
+B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10
+B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4
+B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36
+B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43
+!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47
+!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41
+B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46
+B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11
+B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5
+B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39
+!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42
+!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46
+B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39
+!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42
+B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2
+B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8
+!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39
+B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40
+!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47
+B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38
+!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45
+B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3
+B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9
+B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38
+!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43
+B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46
+!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41
+!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44
+B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10
+B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4
+B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37
+!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41
+B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42
+B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40
+!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47
+B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11
+B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5
+!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36
+!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40
+B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45
+B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43
+!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46
+B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0
+B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6
+B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39
+B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43
+!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44
+!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37
+!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42
+B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1
+B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7
+B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38
+!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42
+B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47
+!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36
+B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45
+B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2
+B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8
+!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41
+!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45
+B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46
+!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39
+B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44
+B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3
+B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9
+!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37
+B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40
+B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44
+B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36
+B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42
+!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1
+!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6
+!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1
+B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4
+B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9
+B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37
+B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43
+B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0
+!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5
+B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0
+!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3
+B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8
+B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38
+B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44
+B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3
+!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8
+B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11
+B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3
+!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6
+B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39
+B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45
+B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2
+!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7
+!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10
+!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2
+B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5
+B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40
+B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46
+!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10
+B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5
+!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1
+!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5
+B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8
+B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41
+B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47
+!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4
+!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9
+B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0
+!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4
+B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7
+B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36
+B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42
+!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0
+!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7
+B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10
+B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3
+!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7
+B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37
+B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43
+!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11
+B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6
+B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2
+B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6
+!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9
+B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38
+B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44
+!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2
+B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9
+!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0
+B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5
+B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9
+B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39
+B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45
+!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1
+B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8
+B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11
+!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4
+!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8
+B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40
+B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46
+B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11
+!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4
+!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11
+B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2
+!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7
+B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41
+B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47
+!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10
+!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3
+B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
+!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10
+B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
+"""
+database_ramt_txt = """
+B0[0] NegClk
+B1[7] RamConfig CBIT_0
+B0[7] RamConfig CBIT_1
+B3[7] RamConfig CBIT_2
+B2[7] RamConfig CBIT_3
+B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK
+!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
+!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
+!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
+!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK
+!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE
+B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0
+B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1
+B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2
+B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3
+B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK
+!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE
+B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
+B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
+B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2
+B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK
+!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE
+!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
+!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
+!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
+!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
+!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK
+B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE
+!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0
+!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1
+!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2
+!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
+!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK
+B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
+B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
+B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
+B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
+B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK
+B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE
+B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
+B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1
+B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
+B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3
+B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK
+B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4
+!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6
+!B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input2_0
+!B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input2_2
+!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_11
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_13
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_15
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_9
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3
+!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5
+!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7
+!B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input2_1
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_10
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_12
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_14
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_8
+!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0
+!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2
+!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4
+!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6
+!B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input2_0
+!B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input2_2
+!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_11
+!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_13
+!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_15
+!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_9
+!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE
+!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_11
+!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_13
+!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_15
+!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_9
+!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1
+!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3
+!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5
+!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7
+!B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input2_1
+!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_10
+!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_12
+!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_14
+!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_8
+!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_10
+!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_12
+!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_14
+!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_8
+B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0
+B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2
+B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4
+B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6
+B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input2_0
+B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input2_2
+B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_11
+B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_13
+B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_15
+B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_9
+!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE
+!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_11
+!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_13
+!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_15
+!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_9
+B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1
+B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3
+B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5
+B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7
+B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input2_1
+B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_10
+B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_12
+B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_14
+B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_8
+!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_10
+!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_12
+!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_14
+!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_8
+B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0
+B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2
+B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4
+B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6
+B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input2_0
+B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input2_2
+B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_11
+B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_13
+B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_15
+B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_9
+!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_11
+!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_13
+!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_15
+!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_9
+B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1
+B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3
+B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5
+B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7
+B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input2_1
+B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_10
+B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_12
+B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_14
+B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_8
+!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_10
+!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_12
+!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_14
+!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_8
+!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1
+!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3
+!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5
+!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7
+!B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input2_1
+!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_10
+!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_12
+!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_14
+!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_8
+B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_10
+B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_12
+B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_14
+B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_8
+!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0
+!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2
+!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4
+!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6
+!B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input2_0
+!B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input2_2
+!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_11
+!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_13
+!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_15
+!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_9
+!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK
+B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_11
+B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_13
+B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_15
+B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_9
+!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1
+!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3
+!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5
+!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7
+!B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input2_1
+!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_10
+!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_12
+!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_14
+!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_8
+B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_10
+B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_12
+B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_14
+B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_8
+!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0
+!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2
+!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4
+!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6
+!B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input2_0
+!B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input2_2
+!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_11
+!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_13
+!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_15
+!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_9
+!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE
+B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_11
+B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_13
+B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_15
+B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_9
+B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1
+B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3
+B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5
+B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7
+B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input2_1
+B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_10
+B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_12
+B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_14
+B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_8
+B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_10
+B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_12
+B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_14
+B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_8
+B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0
+B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2
+B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4
+B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6
+B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input2_0
+B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input2_2
+B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_11
+B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_13
+B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_15
+B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_9
+!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE
+B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_11
+B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_13
+B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_15
+B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_9
+B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1
+B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3
+B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5
+B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7
+B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input2_1
+B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_10
+B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_12
+B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_14
+B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_8
+B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_10
+B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_12
+B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_14
+B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_8
+B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0
+B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2
+B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4
+B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6
+B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input2_0
+B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input2_2
+B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_11
+B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_13
+B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_15
+B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_9
+B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_11
+B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_13
+B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_15
+B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_9
+!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0
+!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2
+!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4
+!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6
+!B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input2_0
+!B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input2_2
+!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_11
+!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_13
+!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_15
+!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_9
+B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK
+!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_11
+!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_13
+!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_15
+!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_9
+!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1
+!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3
+!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5
+!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7
+!B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input2_1
+!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_10
+!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_12
+!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_14
+!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_8
+!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_10
+!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_12
+!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_14
+!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_8
+!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0
+!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2
+!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4
+!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6
+!B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input2_0
+!B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input2_2
+!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_11
+!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_13
+!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_15
+!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_9
+B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE
+!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_11
+!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_13
+!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_15
+!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_9
+!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1
+!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3
+!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5
+!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7
+!B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input2_1
+!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_10
+!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_12
+!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_14
+!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_8
+!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_10
+!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_12
+!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_14
+!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_8
+B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0
+B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2
+B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4
+B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6
+B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input2_0
+B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input2_2
+B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_11
+B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_13
+B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_15
+B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_9
+B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE
+!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_11
+!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_13
+!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_15
+!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_9
+B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1
+B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3
+B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5
+B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7
+B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input2_1
+B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_10
+B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_12
+B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_14
+B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_8
+!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_10
+!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_12
+!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_14
+!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_8
+B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0
+B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2
+B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4
+B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6
+B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input2_0
+B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input2_2
+B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_11
+B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_13
+B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_15
+B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_9
+!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_11
+!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_13
+!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_15
+!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_9
+B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1
+B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3
+B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5
+B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7
+B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input2_1
+B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_10
+B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_12
+B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_14
+B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_8
+!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_10
+!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_12
+!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_14
+!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_8
+!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1
+!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3
+!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5
+!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7
+!B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input2_1
+!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_10
+!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_12
+!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_14
+!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_8
+B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_10
+B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_12
+B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_14
+B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_8
+!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0
+!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2
+!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4
+!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6
+!B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input2_0
+!B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input2_2
+!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_11
+!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_13
+!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_15
+!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_9
+B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK
+B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_11
+B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_13
+B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_15
+B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_9
+!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1
+!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3
+!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5
+!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7
+!B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input2_1
+!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_10
+!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_12
+!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_14
+!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_8
+B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_10
+B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_12
+B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_14
+B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_8
+!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0
+!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2
+!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4
+!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6
+!B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input2_0
+!B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input2_2
+!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_11
+!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_13
+!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_15
+!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_9
+B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE
+B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_11
+B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_13
+B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_15
+B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_9
+B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1
+B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3
+B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5
+B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7
+B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input2_1
+B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_10
+B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_12
+B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_14
+B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_8
+B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_10
+B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_12
+B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_14
+B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_8
+B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0
+B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2
+B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4
+B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6
+B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input2_0
+B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input2_2
+B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_11
+B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_13
+B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_15
+B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_9
+B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE
+B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_11
+B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_13
+B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_15
+B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_9
+B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1
+B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3
+B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5
+B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7
+B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input2_1
+B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_10
+B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_12
+B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_14
+B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_8
+B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_10
+B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_12
+B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_14
+B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_8
+B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0
+B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2
+B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4
+B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6
+B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input2_0
+B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input2_2
+B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_11
+B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_13
+B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_15
+B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_9
+B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_11
+B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_13
+B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_15
+B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_9
+B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7
+B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3
+!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7
+!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6
+B6[2] buffer sp12_h_l_13 sp4_h_r_19
+!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3
+!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6
+B14[2] buffer sp12_h_l_21 sp4_h_l_10
+B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4
+B15[19] buffer sp12_h_l_3 sp4_h_l_3
+B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7
+B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6
+B14[19] buffer sp12_h_l_5 sp4_h_l_2
+!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1
+B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0
+B13[19] buffer sp12_h_r_0 sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2
+B3[1] buffer sp12_h_r_10 sp4_h_r_17
+!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4
+B4[2] buffer sp12_h_r_12 sp4_h_l_7
+!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5
+!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0
+B8[2] buffer sp12_h_r_16 sp4_h_r_20
+!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2
+B10[2] buffer sp12_h_r_18 sp4_h_l_8
+B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2
+B12[19] buffer sp12_h_r_2 sp4_h_r_13
+!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
+B12[2] buffer sp12_h_r_20 sp4_h_r_22
+!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7
+B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5
+!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0
+B0[2] buffer sp12_h_r_8 sp4_h_l_5
+B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1
+B1[19] buffer sp12_v_b_1 sp4_v_t_1
+!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3
+B4[19] buffer sp12_v_b_11 sp4_v_b_17
+!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0
+!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1
+B9[19] buffer sp12_v_b_17 sp4_v_b_20
+B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5
+B11[19] buffer sp12_v_b_21 sp4_v_b_22
+!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7
+B10[19] buffer sp12_v_b_23 sp4_v_t_10
+B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5
+B3[19] buffer sp12_v_b_5 sp4_v_b_14
+B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7
+B2[19] buffer sp12_v_b_7 sp4_v_t_2
+!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1
+B5[19] buffer sp12_v_b_9 sp4_v_b_16
+B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3
+B0[19] buffer sp12_v_t_0 sp4_v_b_13
+!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5
+B7[19] buffer sp12_v_t_10 sp4_v_t_7
+!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7
+B6[19] buffer sp12_v_t_12 sp4_v_b_19
+!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3
+B8[19] buffer sp12_v_t_16 sp4_v_t_8
+!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2
+!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6
+B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4
+!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2
+B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7
+!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2
+B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5
+!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7
+B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7
+B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1
+B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0
+B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1
+B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0
+B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6
+B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3
+B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0
+B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5
+!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4
+B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5
+B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1
+B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4
+B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6
+B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3
+!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6
+B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3
+B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5
+!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4
+B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2
+B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3
+!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3
+B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4
+!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6
+!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1
+B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2
+B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3
+B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6
+!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1
+!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6
+B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4
+!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1
+B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6
+!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7
+!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1
+B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7
+B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3
+B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7
+B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7
+B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3
+B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2
+B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7
+!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2
+!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4
+!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
+!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0
+!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2
+!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4
+!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6
+B4[37] buffer wire_bram/ram/RDATA_10 sp12_h_r_12
+B5[40] buffer wire_bram/ram/RDATA_10 sp12_v_t_19
+B4[39] buffer wire_bram/ram/RDATA_10 sp12_v_t_3
+B5[37] buffer wire_bram/ram/RDATA_10 sp4_h_r_20
+B4[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_36
+B5[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_4
+B4[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_21
+B4[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_37
+B5[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_5
+B5[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_20
+B5[38] buffer wire_bram/ram/RDATA_10 sp4_v_b_4
+B4[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_25
+B6[37] buffer wire_bram/ram/RDATA_11 sp12_h_l_13
+B6[39] buffer wire_bram/ram/RDATA_11 sp12_v_b_6
+B7[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_21
+B6[36] buffer wire_bram/ram/RDATA_11 sp4_h_l_27
+B7[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_22
+B7[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_6
+B6[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_23
+B6[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_39
+B7[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_7
+B7[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_22
+B6[38] buffer wire_bram/ram/RDATA_11 sp4_v_b_38
+B7[38] buffer wire_bram/ram/RDATA_11 sp4_v_b_6
+B8[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_0
+B9[38] buffer wire_bram/ram/RDATA_12 sp12_h_r_16
+B9[40] buffer wire_bram/ram/RDATA_12 sp12_v_t_7
+B9[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_13
+B8[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_29
+B9[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_8
+B8[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_25
+B8[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_41
+B9[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_9
+B8[39] buffer wire_bram/ram/RDATA_12 sp4_v_b_40
+B9[39] buffer wire_bram/ram/RDATA_12 sp4_v_b_8
+B8[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_13
+B11[38] buffer wire_bram/ram/RDATA_13 sp12_h_r_18
+B10[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_2
+B11[40] buffer wire_bram/ram/RDATA_13 sp12_v_t_9
+B11[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_15
+B11[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_10
+B10[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_42
+B11[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_11
+B10[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_27
+B10[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_43
+B11[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_10
+B10[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_26
+B10[39] buffer wire_bram/ram/RDATA_13 sp4_v_t_31
+B12[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_3
+B13[38] buffer wire_bram/ram/RDATA_14 sp12_h_r_20
+B13[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_12
+B13[37] buffer wire_bram/ram/RDATA_14 sp4_h_l_17
+B13[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_12
+B12[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_44
+B13[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_13
+B12[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_29
+B12[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_45
+B12[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_28
+B13[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_1
+B12[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_33
+B15[38] buffer wire_bram/ram/RDATA_15 sp12_h_l_21
+B14[37] buffer wire_bram/ram/RDATA_15 sp12_h_l_5
+B15[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_14
+B15[36] buffer wire_bram/ram/RDATA_15 sp4_h_l_3
+B15[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_30
+B14[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_46
+B15[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_15
+B14[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_31
+B14[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_47
+B15[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_14
+B14[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_30
+B14[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_46
+B0[37] buffer wire_bram/ram/RDATA_8 sp12_h_r_8
+B0[39] buffer wire_bram/ram/RDATA_8 sp12_v_b_0
+B1[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_16
+B0[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_21
+B1[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_5
+B1[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_0
+B1[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_1
+B0[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_17
+B0[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_33
+B1[38] buffer wire_bram/ram/RDATA_8 sp4_v_b_0
+B1[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_16
+B0[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_21
+B2[37] buffer wire_bram/ram/RDATA_9 sp12_h_r_10
+B2[39] buffer wire_bram/ram/RDATA_9 sp12_v_b_2
+B3[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_17
+B3[37] buffer wire_bram/ram/RDATA_9 sp4_h_l_7
+B3[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_2
+B2[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_34
+B2[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_19
+B3[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_3
+B2[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_35
+B3[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_2
+B2[38] buffer wire_bram/ram/RDATA_9 sp4_v_t_23
+B3[39] buffer wire_bram/ram/RDATA_9 sp4_v_t_7
!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1
!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1
!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22
diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index 1614c5e..f243e15 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -599,7 +599,7 @@ void FpgaConfig::read_ascii(std::istream &ifs)
continue;
}
- if (command == ".io_tile" || command == ".logic_tile" || command == ".ram_tile")
+ if (command == ".io_tile" || command == ".logic_tile" || command == ".ramb_tile" || command == ".ramt_tile")
{
if (!got_device)
error("Missing .device statement before %s.\n", command.c_str());
@@ -766,7 +766,7 @@ string FpgaConfig::tile_type(int x, int y) const
if (this->device == "1k") {
if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io";
- if (x == 3 || x == 10) return "ram";
+ if (x == 3 || x == 10) return y % 2 == 1 ? "ramb" : "ramt";
return "logic";
}
panic("Unkown chip type '%s'.\n", this->device.c_str());
@@ -776,7 +776,8 @@ int FpgaConfig::tile_width(const string &type) const
{
if (type == "corner") return 0;
if (type == "logic") return 54;
- if (type == "ram") return 42;
+ if (type == "ramb") return 42;
+ if (type == "ramt") return 42;
if (type == "io") return 18;
panic("Unkown tile type '%s'.\n", type.c_str());
}
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/debian-science/packages/icestorm.git
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