[icestorm] 05/75: Imported full dev sources
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 15:52:02 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository icestorm.
commit 48154cb6f452d3bdb4da36cc267b4b6c45588dc9
Author: Clifford Wolf <clifford at clifford.at>
Date: Sat Jul 18 13:10:40 2015 +0200
Imported full dev sources
---
docs/checkerboard.png | Bin 0 -> 1083 bytes
docs/checkerboard.sh | 21 +
docs/colbuf.svg | 184 ++
docs/format.html | 151 ++
docs/index.html | 321 +++
docs/io_tile.html | 496 +++++
docs/iosp.svg | 1394 ++++++++++++
docs/logic_tile.html | 327 +++
docs/ram_tile.html | 95 +
docs/sp4h.svg | 2076 ++++++++++++++++++
docs/sp4v.svg | 3982 +++++++++++++++++++++++++++++++++
icebox/Makefile | 8 +-
icebox/icebox.py | 1249 +++++++++--
icebox/icebox_chipdb.py | 89 +-
icebox/icebox_diff.py | 36 +-
icebox/icebox_html.py | 2 +-
icebox/icebox_vlog.py | 275 ++-
icebox/iceboxdb.py | 3040 +++++++++++++++++++++++--
icefuzz/Makefile | 97 +
icefuzz/cached_io.txt | 2270 +++++++++++++++++++
icefuzz/cached_logic.txt | 4140 +++++++++++++++++++++++++++++++++++
icefuzz/cached_ramb.txt | 3586 ++++++++++++++++++++++++++++++
icefuzz/cached_ramb_8k.txt | 3575 ++++++++++++++++++++++++++++++
icefuzz/cached_ramt.txt | 3586 ++++++++++++++++++++++++++++++
icefuzz/cached_ramt_8k.txt | 3597 ++++++++++++++++++++++++++++++
icefuzz/check.sh | 50 +
icefuzz/convert_ram8k.py | 28 +
icefuzz/database.py | 140 ++
icefuzz/export.py | 13 +
icefuzz/extract.py | 60 +
icefuzz/fuzzconfig.py | 36 +
icefuzz/glbmapbits.py | 34 +
icefuzz/icecube.sh | 190 ++
icefuzz/make_binop.py | 28 +
icefuzz/make_cluster.py | 29 +
icefuzz/make_fanout.py | 29 +
icefuzz/make_fflogic.py | 54 +
icefuzz/make_gbio.py | 84 +
icefuzz/make_gbio2.py | 83 +
icefuzz/make_io.py | 61 +
icefuzz/make_iopack.py | 59 +
icefuzz/make_logic.py | 34 +
icefuzz/make_mesh.py | 29 +
icefuzz/make_pin2pin.py | 27 +
icefuzz/make_pll.py | 139 ++
icefuzz/make_prim.py | 51 +
icefuzz/make_ram40.py | 113 +
icefuzz/pinloc/pinloc-1k-tq144.sh | 33 +
icefuzz/pinloc/pinloc-8k-ct256.sh | 44 +
icefuzz/pinloc/pinlocdb.py | 46 +
icefuzz/runloop.sh | 19 +
icefuzz/tests/all_luts_ffff.bin | Bin 0 -> 32299 bytes
icefuzz/tests/bitop.pcf | 3 +
icefuzz/tests/bitop.v | 3 +
icefuzz/tests/bram.pcf | 1 +
icefuzz/tests/bram.v | 40 +
icefuzz/tests/carry.v | 8 +
icefuzz/tests/colbuf.py | 22 +
icefuzz/tests/colbuf.sh | 48 +
icefuzz/tests/colbuf_8k.sh | 52 +
icefuzz/tests/colbuf_io.sh | 38 +
icefuzz/tests/colbuf_io_8k.sh | 50 +
icefuzz/tests/colbuf_logic.sh | 29 +
icefuzz/tests/colbuf_logic_8k.sh | 29 +
icefuzz/tests/colbuf_ram.sh | 57 +
icefuzz/tests/colbuf_ram_8k.sh | 57 +
icefuzz/tests/cross_0.pcf | 17 +
icefuzz/tests/cross_0.v | 9 +
icefuzz/tests/example_hx8kboard.pcf | 9 +
icefuzz/tests/example_hx8kboard.sdc | 1 +
icefuzz/tests/example_hx8kboard.sh | 2 +
icefuzz/tests/example_hx8kboard.v | 32 +
icefuzz/tests/example_icestick.pcf | 6 +
icefuzz/tests/example_icestick.sdc | 1 +
icefuzz/tests/example_icestick.sh | 2 +
icefuzz/tests/example_icestick.v | 29 +
icefuzz/tests/icegate.pcf | 4 +
icefuzz/tests/icegate.v | 18 +
icefuzz/tests/io_glb_netwk.pcf | 10 +
icefuzz/tests/io_glb_netwk.v | 42 +
icefuzz/tests/io_latched.sh | 28 +
icefuzz/tests/io_latched.v | 23 +
icefuzz/tests/ioctrl.py | 21 +
icefuzz/tests/ioctrl.sh | 30 +
icefuzz/tests/lut_cascade.pcf | 2 +
icefuzz/tests/lut_cascade.v | 23 +
icefuzz/tests/raminits.pcf | 16 +
icefuzz/tests/raminits.v | 490 +++++
icefuzz/tests/sb_dff.v | 3 +
icefuzz/tests/sb_dffe.v | 3 +
icefuzz/tests/sb_dffer.v | 3 +
icefuzz/tests/sb_dffes.v | 3 +
icefuzz/tests/sb_dffesr.v | 3 +
icefuzz/tests/sb_dffess.v | 3 +
icefuzz/tests/sb_dffr.v | 3 +
icefuzz/tests/sb_dffs.v | 3 +
icefuzz/tests/sb_dffsr.v | 3 +
icefuzz/tests/sb_dffss.v | 3 +
icefuzz/tests/sb_gb.v | 9 +
icefuzz/tests/sb_gb_io.v | 32 +
icefuzz/tests/sb_io.pcf | 12 +
icefuzz/tests/sb_io.v | 64 +
icefuzz/tests/sb_io_negclk.pcf | 2 +
icefuzz/tests/sb_io_negclk.v | 39 +
icefuzz/tests/sb_pll40_core.v | 67 +
icefuzz/tests/sb_ram40.pcf | 4 +
icefuzz/tests/sb_ram40.v | 80 +
icefuzz/tests/sb_warmboot.v | 7 +
icefuzz/tests/test_pio.sh | 60 +
icefuzz/tests/test_pio_tb.v | 126 ++
icepack/icepack.cc | 38 +-
iceprog/iceprog.c | 89 +-
112 files changed, 37659 insertions(+), 362 deletions(-)
diff --git a/docs/checkerboard.png b/docs/checkerboard.png
new file mode 100644
index 0000000..72478de
Binary files /dev/null and b/docs/checkerboard.png differ
diff --git a/docs/checkerboard.sh b/docs/checkerboard.sh
new file mode 100644
index 0000000..dd045ee
--- /dev/null
+++ b/docs/checkerboard.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+pbm_to_ppm() {
+ read line; echo "P3"
+ read line; echo "$line"; echo "2"
+ sed "s,0,x,g; s,1,y,g; s,x,$1,g; s,y,$2,g;"
+
+}
+
+../icepack/icepack -uc -B0 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 0 2" > checkerboard_0.ppm
+../icepack/icepack -ucc -B0 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_1.ppm
+../icepack/icepack -uc -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 1" > checkerboard_2.ppm
+../icepack/icepack -ucc -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 0" > checkerboard_3.ppm
+../icepack/icepack -uc -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 1" > checkerboard_4.ppm
+../icepack/icepack -ucc -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 0" > checkerboard_5.ppm
+../icepack/icepack -uc -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 1" > checkerboard_6.ppm
+../icepack/icepack -ucc -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_7.ppm
+
+convert -evaluate-sequence add checkerboard_[01234567].ppm checkerboard.png
+rm -f checkerboard_[01234567].ppm
+
diff --git a/docs/colbuf.svg b/docs/colbuf.svg
new file mode 100644
index 0000000..e903e19
--- /dev/null
+++ b/docs/colbuf.svg
@@ -0,0 +1,184 @@
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+<circle cx="355" cy="415" r="5" fill="gray" />
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+<circle cx="355" cy="175" r="5" fill="gray" />
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+<circle cx="415" cy="385" r="5" fill="gray" />
+<circle cx="415" cy="175" r="5" fill="gray" />
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+<circle cx="115" cy="205" r="5" fill="gray" />
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+<circle cx="325" cy="445" r="5" fill="gray" />
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+<circle cx="325" cy="205" r="5" fill="gray" />
+<circle cx="325" cy="145" r="5" fill="gray" />
+</svg>
diff --git a/docs/format.html b/docs/format.html
new file mode 100644
index 0000000..654a75d
--- /dev/null
+++ b/docs/format.html
@@ -0,0 +1,151 @@
+<title>Project IceStorm – Bitstream File Format Documentation</title>
+<h1>Project IceStorm – Bitstream File Format Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>General Description of the File Format</h2>
+
+<p>
+The bitstream file starts with the bytes 0xFF 0x00, followed by a sequence of
+zero-terminated comment strings, followed by 0x00 0xFF. However, there seems to be
+a bug in the Lattice "bitstream" tool that moves the terminating 0x00 0xFF a few
+bytes into the comment string in some cases.
+</p>
+
+<p>
+After the comment sections the token 0x7EAA997E (MSB first) starts the actual
+bit stream. The bitstream consists of one-byte commands, followed by a payload
+word, followed by an optional block of data. The MSB nibble of the command byte
+is the command opcode, the LSB nibble is the length of the command payload in
+bytes. The commands that do not require a payload are using the opcode 0, with
+the command encoded in the payload field. Note that this "payload" in this
+context refers to a single integer argument, not the blocks of data that
+follows the command in case of the CRAM and BRAM commands.
+</p>
+
+<p>
+The following commands are known:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Opcode</th><th>Description</th></tr>
+<tr><td>0</td><td>payload=0: CRAM Data<br/>
+ payload=3: BRAM Data<br/>
+ payload=5: Reset CRC<br/>
+ payload=6: Wakeup</td></tr>
+<tr><td>1</td><td>Set bank number</td></tr>
+<tr><td>2</td><td>CRC check</td></tr>
+<tr><td>5</td><td>Set internal oscillator frequency range<br/>
+ payload=0: low<br/>
+ payload=1: medium<br/>
+ payload=2: high</td></tr>
+<tr><td>6</td><td>Set bank width</td></tr>
+<tr><td>7</td><td>Set bank height</td></tr>
+<tr><td>8</td><td>Set bank offset</td></tr>
+<tr><td>9</td><td>payload=0: Disable warm boot<br/>
+ payload=32: Enable warm boot</td></tr>
+</table>
+</p>
+
+<p>
+Use <tt>iceunpack -vv</tt> to display the commands as they are interpreted by the tool.
+</p>
+
+<p>
+Note: The format itself seems to be very flexible. At the moment it is unclear what the FPGA
+devices will do when presented with a bitstream that use the commands in a different way
+than the bitstreams generated by the lattice tools.
+</p>
+
+<h2>Writing SRAM content</h2>
+
+<p>
+Most bytes in the bitstream are SRAM data bytes that should be written to the various SRAM banks
+in the FPGA. The following sequence is used to program an SRAM cell:
+</p>
+
+<p><ul>
+<li>Set bank width (opcode 6)</li>
+<li>Set bank height (opcode 7)</li>
+<li>Set bank offset (opcode 8)</li>
+<li>Set bank number (opcode 1)</li>
+<li>CRAM or BRAM Data Command</li>
+<li>(width * height / 8) data bytes</li>
+<li>two zero bytes</li>
+</ul></p>
+
+<p>
+The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can
+be written in smaller junks. In this case height parameter may be smaller and the offset parameter
+reflects the vertical start position.
+</p>
+
+<p>
+There are four CRAM and four BRAM banks in an iCE40 FPGA. The different devices from the family
+use different widths and heights, but the same number of banks.
+</p>
+
+<p>
+The CRAM banks hold the configuration bits for the FPGA fabric and hard IP blocks, the BRAM
+corresponds to the contents of the block ram resources.
+</p>
+
+<p>
+The ordering of the data bits is in MSB first row-major order.
+</p>
+
+<h2>Organization of the CRAM</h2>
+
+<p><a href="checkerboard.png"><img style="float:right; padding:1em; padding-top:0" height="200" src="checkerboard.png" border="0"></a></p>
+
+<p>
+The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant.
+The address 0 is always the corner of the quadrant, i.e. in one quadrant the bit addresses increase with the tile x/y
+coordinates, in another they increase with the tile x coordinate but decrease with the tile y coordinate, and so on.
+</p>
+
+<p>
+For an iCE40 1k device, that has 12 x 16 tiles (not counting the io tiles), the CRAM bank 0 is the one containing the corner tile (1 1),
+the CRAM bank 1 contains the corner tile (1 16), the CRAM bank 2 contains the corner tile (12 1) and the CRAM bank 3 contains the
+corner tile (12 16). The entire CRAM of such a device is depicted on the right (bank 0 is in the lower left corner in blue/green).
+</p>
+
+<p>
+The checkerboard pattern in the picture visualizes which bits are assoziated
+with which tile. The height of the configuration block is 16 for all tile
+types, but the width is different for each tile type. IO tiles have
+configurations that are 18 bits wide, LOGIC tiles are 54 bits wide, and
+RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM tiles.)
+</p>
+
+<p>
+The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that
+their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit
+positions are vertically permutated as well. The <tt>CramIndexConverter</tt> class in <tt>icepack.cc</tt> encapsulates the calculations
+that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.
+</p>
+
+<p>
+The black pixels in the image correspond to CRAM bits that are not assoziated with any IO, LOGIC or RAM tile.
+Some of them are unused, others are used by hard IPs or other global resources. The <tt>iceunpack</tt> tool reports
+such bits, when set, with the "<tt>.extra_bit <i>bank x y</i></tt>" statement in the ASCII output format.
+</p>
+
+<h2>Organization of the BRAM</h2>
+
+<p>
+This part of the documentation has not been written yet.
+</p>
+
+<h2>CRC Check</h2>
+
+<p>
+The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). The "Reset CRC" command sets
+the CRC to 0xFFFF. No zero padding is performed.
+</p>
+
diff --git a/docs/index.html b/docs/index.html
new file mode 100644
index 0000000..dbd8ba6
--- /dev/null
+++ b/docs/index.html
@@ -0,0 +1,321 @@
+<title>Project IceStorm</title>
+<h1>Project IceStorm</h1>
+
+<p>
+<b>2015-05-27:</b> We have a working fully Open Source flow with <a href="http://www.clifford.at/yosys/">Yosys</a> and <a href="https://github.com/cseed/arachne-pnr">Arachne-pnr</a>! Video: <a href="http://youtu.be/yUiNlmvVOq8">http://youtu.be/yUiNlmvVOq8</a><br/>
+<b>2015-04-13:</b> Complete rewrite of IceUnpack, added IcePack, some major documentation updates<br/>
+<b>2015-03-22:</b> First public release and short YouTube video demonstrating our work: <a href="http://youtu.be/u1ZHcSNDQMM">http://youtu.be/u1ZHcSNDQMM</a>
+</p>
+
+<h2>What is Project IceStorm?</h2>
+
+<p>
+Project IceStorm aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+At the moment the focus of the project is on the HX1K-TQ144 device, but
+most of the information is device-independent.
+</p>
+
+<h2>Why the Lattice iCE40?</h2>
+
+<p>
+It has a very minimalistic architecture with a very regular structure. There are not many
+different kinds of tiles or special function units. This makes it both ideal for
+reverse engineering and as a reference platform for general purpose FPGA tool development.
+</p>
+
+<p>
+Also, with the <a href="http://www.latticesemi.com/icestick">iCEstick</a> there is
+a cheap and easy to use development platform available, which makes the part interesting
+for all kinds of projects.
+</p>
+
+<h2>What is the Status of the Project?</h2>
+
+<p>
+We have enough bits mapped that we can create a functional verilog model for almost all
+bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144, as long as no
+block memories or PLLs are used. (Both are fully documented, but the
+<tt>icebox_vlog.py</tt> script does not create verilog models for them yet.)
+</p>
+
+<p>
+Next on the TODO list: PLLs, Timing Analysis, support for HX8K chips.
+</p>
+
+<h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
+
+<p>
+Synthesis for iCE40 FPGAs can be done with <a href="http://www.clifford.at/yosys/">Yosys</a>.
+Place-and-route can be done with <a href="https://github.com/cseed/arachne-pnr">arachne-pnr</a>.
+Here is an example script for implementing and programming the <a
+href="https://github.com/cseed/arachne-pnr/tree/master/examples/rot">rot example from
+arachne-pnr</a> (this example targets the iCEstick development board):
+</p>
+
+<pre style="padding-left: 3em">yosys -p "synth_ice40 -blif rot.blif" rot.v
+arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.txt
+icepack rot.txt rot.bin
+iceprog rot.bin</pre>
+
+<h2>Where are the Tools?</h2>
+
+<p>
+Here is the current snapshot of our toolchain: <a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a><br/>
+<i>This is work under construction and highly experimental! Use at your own risk!</i>
+</p>
+
+<p style="margin-bottom: 0.5em;">
+All snapshots in reverse chronological order:
+</p>
+
+<ul style="margin-top: 0.5em;">
+<li><a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a></li>
+<li><a href="icestorm-snapshot-150413.zip">icestorm-snapshot-150413.zip</a></li>
+<li><a href="icestorm-snapshot-150401.zip">icestorm-snapshot-150401.zip</a></li>
+<li><a href="icestorm-snapshot-150322.zip">icestorm-snapshot-150322.zip</a></li>
+</ul>
+
+<h3>IcePack/IceUnpack</h3>
+
+<p>
+The <tt>iceunpack</tt> program converts an iCE40 <tt>.bin</tt> file into the IceBox ASCII format
+that has blocks of <tt>0</tt> and <tt>1</tt> for the config bits for each tile in the chip. The
+<tt>icepack</tt> program converts such an ASCII file back to an iCE40 <tt>.bin</tt> file.
+</p>
+
+<h3>IceBox</h3>
+
+<p>
+A python library and various tools for working with IceBox ASCII files and accessing
+the device database. For example <tt>icebox_vlog.py</tt> converts our ASCII file
+dump of a bitstream into a verilog file that implements an equivalent circuit.
+</p>
+
+<h3>IceProg</h3>
+
+<p>
+A small driver programm for the FTDI-based programmer used on the iCEstick and HX8K development boards.
+</p>
+
+<p>
+<i>The tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser.</i>
+</p>
+
+<h2>Where is the Documentation?</h2>
+
+<p>
+Recommended reading:
+<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf">Lattice iCE40 LP/HX Family Datasheet</a>,
+<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201412.pdf">Lattice iCE Technology Library</a>
+(Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in
+the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)
+</p>
+
+<p>
+The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
+</p>
+
+<ul>
+<li><a href="logic_tile.html">LOGIC Tile Documentation</a></li>
+<li><a href="io_tile.html">IO Tile Documentation</a></li>
+<li><a href="ram_tile.html">RAM Tile Documentation</a></li>
+<li><a href="format.html">The Bitstream File Format</a></li>
+<li><a href="bitdocs/">Tile Bits Reference Docs</a></li>
+</ul>
+
+<p>
+The <tt>iceunpack</tt> program can be used to convert the bitstream into an ASCII file
+that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For example:
+</p>
+
+<pre style="padding-left: 3em">.logic_tile 12 12
+000000000000000000000000000000000000000000000000000000
+000000000000000000000011010000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000001011000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000000000000000000000000000000000
+000000000000000000000000001000001000010101010000000000
+000000000000000000000000000101010000101010100000000000</pre>
+
+<p>
+This bits are referred to as <tt>B<i>y</i>[<i>x</i>]</tt> in the documentation. For example, <tt>B0</tt> is the first
+line, <tt>B0[0]</tt> the first bit in the first line, and <tt>B15[53]</tt> the last bit in the last line.
+</p>
+
+<p>
+The <tt>icebox_explain.py</tt> program can be used to turn this block of config bits into a description of the cell
+configuration:
+</p>
+
+<pre style="padding-left: 3em">.logic_tile 12 12
+LC_7 0101010110101010 0000
+buffer local_g0_2 lutff_7/in_3
+buffer local_g1_4 lutff_7/in_0
+buffer sp12_h_r_18 local_g0_2
+buffer sp12_h_r_20 local_g1_4</pre>
+
+<p>
+IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed
+via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API
+to export this database into a format that fits the target application. See <tt>icebox_chipdb.py</tt> for
+an example program that does that.
+</p>
+
+<p>
+The recommended approach for learning how to use this documentation is to synthesize very simple circuits using
+Lattice iCEcube2, run our toolchain on the resulting bitstream files, and analyze the results using the HTML export of the database
+mentioned above. <tt>icebox_vlog.py</tt> can be used to convert the bitstream to verilog. The output file of
+this tool will also outline the signal paths in comments added to the generated verilog.
+</p>
+
+<p>
+For example, using the <tt>top_bitmap.bin</tt> from the following Verilog and PCF files:
+</p>
+
+<pre style="padding-left: 3em">module top (input a, b, output y);
+ assign y = a & b;
+endmodule
+
+set_io a 1
+set_io b 10
+set_io y 11</pre>
+
+<p>
+We would get something like the following <tt>icebox_explain.py</tt> output:
+</p>
+
+<pre style="padding-left: 3em">$ iceunpack top_bitmap.bin top_bitmap.txt
+$ icebox_explain top_bitmap.txt
+Reading file 'top_bitmap.txt'..
+Fabric size (without IO tiles): 12 x 16
+
+.io_tile 0 10
+IOB_1 PINTYPE_0
+IOB_1 PINTYPE_3
+IOB_1 PINTYPE_4
+IoCtrl IE_0
+IoCtrl IE_1
+IoCtrl REN_0
+buffer local_g1_2 io_1/D_OUT_0
+buffer logic_op_tnr_2 local_g1_2
+
+.io_tile 0 14
+IOB_1 PINTYPE_0
+IoCtrl IE_1
+IoCtrl REN_0
+buffer io_1/D_IN_0 span4_horz_28
+
+.io_tile 0 11
+IOB_0 PINTYPE_0
+IoCtrl IE_0
+IoCtrl REN_1
+
+.logic_tile 1 11
+LC_2 0000000001010101 0000
+buffer local_g1_4 lutff_2/in_3
+buffer local_g3_1 lutff_2/in_0
+buffer neigh_op_lft_4 local_g1_4
+buffer sp4_r_v_b_41 local_g3_1
+
+.logic_tile 2 14
+routing sp4_h_l_41 sp4_v_b_4</pre>
+
+<p>
+And something like the following <tt>icebox_vlog.py</tt> output:
+</p>
+
+<pre style="padding-left: 3em">$ icebox_vlog top_bitmap.txt
+// Reading file 'top_bitmap.txt'..
+
+module chip (output io_0_10_1, input io_0_11_0, input io_0_14_1);
+
+wire io_0_10_1;
+// io_0_10_1
+// (0, 10, 'io_1/D_OUT_0')
+// (0, 10, 'io_1/PAD')
+// (0, 10, 'local_g1_2')
+// (0, 10, 'logic_op_tnr_2')
+// (0, 11, 'logic_op_rgt_2')
+// (0, 12, 'logic_op_bnr_2')
+// (1, 10, 'neigh_op_top_2')
+// (1, 11, 'lutff_2/out')
+// (1, 12, 'neigh_op_bot_2')
+// (2, 10, 'neigh_op_tnl_2')
+// (2, 11, 'neigh_op_lft_2')
+// (2, 12, 'neigh_op_bnl_2')
+
+wire io_0_11_0;
+// io_0_11_0
+// (0, 11, 'io_0/D_IN_0')
+// (0, 11, 'io_0/PAD')
+// (1, 10, 'neigh_op_tnl_0')
+// (1, 10, 'neigh_op_tnl_4')
+// (1, 11, 'local_g1_4')
+// (1, 11, 'lutff_2/in_3')
+// (1, 11, 'neigh_op_lft_0')
+// (1, 11, 'neigh_op_lft_4')
+// (1, 12, 'neigh_op_bnl_0')
+// (1, 12, 'neigh_op_bnl_4')
+
+wire io_0_14_1;
+// io_0_14_1
+// (0, 14, 'io_1/D_IN_0')
+// (0, 14, 'io_1/PAD')
+// (0, 14, 'span4_horz_28')
+// (1, 11, 'local_g3_1')
+// (1, 11, 'lutff_2/in_0')
+// (1, 11, 'sp4_r_v_b_41')
+// (1, 12, 'sp4_r_v_b_28')
+// (1, 13, 'neigh_op_tnl_2')
+// (1, 13, 'neigh_op_tnl_6')
+// (1, 13, 'sp4_r_v_b_17')
+// (1, 14, 'neigh_op_lft_2')
+// (1, 14, 'neigh_op_lft_6')
+// (1, 14, 'sp4_h_r_41')
+// (1, 14, 'sp4_r_v_b_4')
+// (1, 15, 'neigh_op_bnl_2')
+// (1, 15, 'neigh_op_bnl_6')
+// (2, 10, 'sp4_v_t_41')
+// (2, 11, 'sp4_v_b_41')
+// (2, 12, 'sp4_v_b_28')
+// (2, 13, 'sp4_v_b_17')
+// (2, 14, 'sp4_h_l_41')
+// (2, 14, 'sp4_v_b_4')
+
+assign io_0_10_1 = /* LUT 1 11 2 */ io_0_11_0 ? io_0_14_1 : 0;
+
+endmodule</pre>
+
+<p>
+<hr>
+</p>
+
+<p>
+In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
+e.g. using the following BibTeX code:
+</p>
+
+<pre>@MISC{IceStorm,
+ author = {Clifford Wolf and Mathias Lasser},
+ title = {Project IceStorm},
+ howpublished = "\url{http://www.clifford.at/icestorm/}"
+}</pre>
+
+<p>
+<hr>
+</p>
+
+<p>
+<i>Documentation mostly by Clifford Wolf <clifford at clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
+Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here. Buy a few because you might break some..</i>
+</p>
diff --git a/docs/io_tile.html b/docs/io_tile.html
new file mode 100644
index 0000000..0324ac8
--- /dev/null
+++ b/docs/io_tile.html
@@ -0,0 +1,496 @@
+<title>Project IceStorm – IO Tile Documentation</title>
+<h1>Project IceStorm – IO Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p><a href="iosp.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="iosp.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the span-wires of a left (or right) io cell (click to enlarge).
+</p>
+
+<p>
+A left/right io cell has 16 connections named <tt>span4_vert_t_0</tt> to <tt>span4_vert_t_15</tt> on its top edge and
+16 connections named <tt>span4_vert_b_0</tt> to <tt>span4_vert_b_15</tt> on its bottom edge. The nets <tt>span4_vert_t_0</tt>
+to <tt>span4_vert_t_11</tt> are connected to <tt>span4_vert_b_4</tt> to <tt>span4_vert_b_15</tt>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <tt>span4_horz_0</tt> to <tt>span4_horz_47</tt> and <tt>span12_horz_0</tt>
+to <tt>span12_horz_23</tt>.
+</p>
+
+<p>
+A top/bottom io cell has 16 connections named <tt>span4_vert_l_0</tt> to <tt>span4_vert_l_15</tt> on its top edge and
+16 connections named <tt>span4_vert_r_0</tt> to <tt>span4_vert_r_15</tt> on its bottom edge. The nets <tt>span4_vert_l_0</tt>
+to <tt>span4_vert_l_11</tt> are connected to <tt>span4_vert_r_4</tt> to <tt>span4_vert_r_15</tt>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <tt>span4_vert_0</tt> to <tt>span4_vert_47</tt> and <tt>span12_vert_0</tt>
+to <tt>span12_vert_23</tt>.
+</p>
+
+<p>
+The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom
+io cells. For example <tt>span4_vert_b_0</tt> of IO cell (0 1) is connected to <tt>span4_horz_l_0</tt> (<tt>span4_horz_r_4</tt>)
+of IO cell (1 0).
+</p>
+
+<p>
+Note that unlike the span-wires connection LOGIC and RAM tiles, the span-wires
+connecting IO tiles to each other are not pairwised crossed out.
+</p>
+
+<h2>IO Blocks</h2>
+
+<p>
+Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt>
+primitive from the <a href="http://www.latticesemi.com/~/media/Documents/TechnicalBriefs/iCETechnologyLibrary.PDF">Lattice iCE Technology Library</a>.
+Some inputs are shared between the two IO blocks. The following table lists how the
+wires in the logic tile map to the <tt>SB_IO</tt> primitive ports:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_IO Port</th><th>IO Block 0</th><th>IO Block 1</th></tr>
+<tr><td>D_IN_0</td><td><tt>io_0/D_IN_0</tt></td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>D_IN_1</td><td><tt>io_0/D_IN_1</tt></td><td><tt>io_1/D_IN_1</tt></td></tr>
+<tr><td>D_OUT_0</td><td><tt>io_0/D_OUT_0</tt></td><td><tt>io_1/D_OUT_0</tt></td></tr>
+<tr><td>D_OUT_1</td><td><tt>io_0/D_OUT_1</tt></td><td><tt>io_1/D_OUT_1</tt></td></tr>
+<tr><td>OUTPUT_ENABLE</td><td><tt>io_0/OUT_ENB</tt></td><td><tt>io_1/OUT_ENB</tt></td></tr>
+<tr><td>CLOCK_ENABLE</td><td colspan="2"><tt>io_global/cen</tt></td></tr>
+<tr><td>INPUT_CLK</td><td colspan="2"><tt>io_global/inclk</tt></td></tr>
+<tr><td>OUTPUT_CLK</td><td colspan="2"><tt>io_global/outclk</tt></td></tr>
+<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><tt>io_global/latch</tt></td></tr>
+</table>
+</p>
+
+<p>
+Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal
+is first routed to one of 16 local tracks in the IO tile and then from the local track to the IO block.
+</p>
+
+<p>
+The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>wire_gbuf/in</tt>
+from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <tt>io_global/latch</tt> signal are:
+(0, 7), (13, 10), (5, 0), and (8, 17)
+</p>
+
+<p>
+A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <tt>D_IN</tt>
+signals created by its two IO blocks. The <tt>D_IN</tt> signals map to logic function indices as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Function Index</th><th>D_IN Wire</th></tr>
+<tr><td>0</td><td><tt>io_0/D_IN_0</tt></td></tr>
+<tr><td>1</td><td><tt>io_0/D_IN_1</tt></td></tr>
+<tr><td>2</td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>3</td><td><tt>io_1/D_IN_1</tt></td></tr>
+<tr><td>4</td><td><tt>io_0/D_IN_0</tt></td></tr>
+<tr><td>5</td><td><tt>io_0/D_IN_1</tt></td></tr>
+<tr><td>6</td><td><tt>io_1/D_IN_0</tt></td></tr>
+<tr><td>7</td><td><tt>io_1/D_IN_1</tt></td></tr>
+</table>
+</p>
+
+<p>
+For example the signal <tt>io_1/D_IN_0</tt> in IO tile (0, 5) can be seen as <tt>neigh_op_lft_2</tt> and <tt>neigh_op_lft_6</tt> in LOGIC tile (1, 5).
+</p>
+
+<p>
+Each IO Tile has 2 <tt>NegClk</tt> configuration bits, suggesting that the
+clock signals can be inverted independently for the the two IO blocks in the
+tile. However, the Lattice tools refuse to pack to IO blocks with different block
+polarity into the same IO tile. In our tests we only managed to either set or clear
+both NegClk bits.
+</p>
+
+<p>
+Each IO block has two <tt>IoCtrl IE</tt> bits that enable the input buffers and
+two <tt>IoCtrl REN</tt> bits that enable the pull up resistors. Both bits are active
+low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the
+default behavior is to enable pullup resistors on all unused pins). Note that
+<tt>icebox_explain.py</tt> will ignore all IO tiles that only have the two <tt>IoCtrl
+IE</tt> bits set.
+</p>
+
+<p>
+However, the <tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> do not
+necessarily configure the IO PIN that are connected to the IO block in the same tile,
+and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins
+on the right and bottom side of the chips match up with the IO blocks and for the pins
+on the left and top side the numbers must be swapped. But in some cases the IO block
+and the set of <tt>IE/REN</tt> are not even located in the same tile. The following
+table lists the correlation between IO blocks and <tt>IE/REN</tt> bits for the
+1K chip:
+</p>
+
+<p align="center">
+<table cellpadding="10">
+<tr><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 1</td><td align="center">0 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 0</td><td align="center">0 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 1</td><td align="center">0 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 0</td><td align="center">0 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 1</td><td align="center">0 12 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 0</td><td align="center">0 12 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 1</td><td align="center">0 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 0</td><td align="center">0 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 1</td><td align="center">0 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 0</td><td align="center">0 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 1</td><td align="center">0 9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 0</td><td align="center">0 9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 1</td><td align="center">0 8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 0</td><td align="center">0 8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 1</td><td align="center">0 6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 0</td><td align="center">0 6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 1</td><td align="center">0 5 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 0</td><td align="center">0 5 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 1</td><td align="center">0 4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 0</td><td align="center">0 4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 1</td><td align="center">0 3 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 0</td><td align="center">0 3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 1</td><td align="center">0 2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 0</td><td align="center">0 2 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 0</td><td align="center"> 1 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 1</td><td align="center"> 1 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 0</td><td align="center"> 2 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 1</td><td align="center"> 2 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 0</td><td align="center"> 3 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 1</td><td align="center"> 3 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 0</td><td align="center"> 4 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 1</td><td align="center"> 4 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 0</td><td align="center"> 5 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 1</td><td align="center"> 5 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 1</td><td align="center"> 6 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 0</td><td align="center"> 6 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 0</td><td align="center"> 7 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 1</td><td align="center"> 7 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 0</td><td align="center"> 8 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 1</td><td align="center"> 8 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 0</td><td align="center"> 9 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 1</td><td align="center"> 9 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 0</td><td align="center">10 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 1</td><td align="center">10 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 0</td><td align="center">11 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 1</td><td align="center">11 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 0</td><td align="center">12 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 1</td><td align="center">12 0 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 0</td><td align="center">13 1 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 1</td><td align="center">13 1 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 0</td><td align="center">13 2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 1</td><td align="center">13 2 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 3 1</td><td align="center">13 3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 0</td><td align="center">13 4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 1</td><td align="center">13 4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 0</td><td align="center">13 6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 1</td><td align="center">13 6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 0</td><td align="center">13 7 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 1</td><td align="center">13 7 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 0</td><td align="center">13 8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 1</td><td align="center">13 8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 0</td><td align="center">13 9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 1</td><td align="center">13 9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 0</td><td align="center">13 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 1</td><td align="center">13 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 0</td><td align="center">13 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 1</td><td align="center">13 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 0</td><td align="center">13 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 1</td><td align="center">13 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 0</td><td align="center">13 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 1</td><td align="center">13 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 0</td><td align="center">13 15 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 1</td><td align="center">13 15 1</td></tr>
+</table>
+
+</td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Block</th><th>IE/REN Block</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 1</td><td align="center">12 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 0</td><td align="center">12 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 1</td><td align="center">11 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 0</td><td align="center">11 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 1</td><td align="center"> 9 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 0</td><td align="center"> 9 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 1</td><td align="center">10 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 0</td><td align="center">10 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 1</td><td align="center"> 8 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 0</td><td align="center"> 8 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 1</td><td align="center"> 7 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 0</td><td align="center"> 7 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 17 1</td><td align="center"> 6 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 1</td><td align="center"> 5 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 0</td><td align="center"> 5 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 1</td><td align="center"> 4 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 0</td><td align="center"> 4 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 1</td><td align="center"> 3 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 0</td><td align="center"> 3 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 1</td><td align="center"> 2 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 0</td><td align="center"> 2 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 1</td><td align="center"> 1 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 0</td><td align="center"> 1 17 0</td></tr>
+</table>
+
+</table>
+</p>
+
+<p>
+When an input pin pair is used as LVDS pair (IO standard
+<tt>SB_LVDS_INPUT</tt>, bank 3 / left edge only), then the four bits
+<tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> are all set, as well
+as the <tt>IoCtrl LVDS</tt> bit.
+</p>
+
+<p>
+In the iCE 8k devices the <tt>IoCtrl IE</tt> bits are active high. So an unused
+IO tile on an 8k chip has all bits cleared.
+</p>
+
+<h2>Global Nets</h2>
+
+<p>
+iCE40 FPGAs have 8 global nets. Each global net can be driven directly from an
+IO pin. In the FPGA bitstream, routing of external signals to global nets is
+not controlled by bits in the IO tile. Instead bits that do not belong to any
+tile are used. In IceBox nomenclature such bits are called "extra bits".
+</p>
+
+<p>
+The following table lists which pins / IO blocks may be used to drive
+which global net, and what <tt>.extra</tt> statements in the IceBox ASCII file
+format to represent the corresponding configuration bits:
+</p>
+
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Glb Net</th><th>Pin<br/>(HX1K-TQ144)</th><th>IO Tile +<br/>Block #</th><th>IceBox Statement</th></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">0</td><td align="center"> 93</td><td align="center">13 8 1</td><td align="center">.extra_bit 0 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">1</td><td align="center"> 21</td><td align="center"> 0 8 1</td><td align="center">.extra_bit 0 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">2</td><td align="center">128</td><td align="center"> 7 17 0</td><td align="center">.extra_bit 1 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">3</td><td align="center"> 50</td><td align="center"> 7 0 0</td><td align="center">.extra_bit 1 331 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">4</td><td align="center"> 20</td><td align="center"> 0 9 0</td><td align="center">.extra_bit 1 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">5</td><td align="center"> 94</td><td align="center">13 9 0</td><td align="center">.extra_bit 1 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">6</td><td align="center"> 49</td><td align="center"> 6 0 1</td><td align="center">.extra_bit 0 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td align="center">7</td><td align="center">129</td><td align="center"> 6 17 1</td><td align="center">.extra_bit 0 331 143</td></tr>
+</table>
+</p>
+
+<p>
+Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal
+to the <tt>wire_gbuf/in</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this
+case each of the I/O tiles corresponds to a different global net:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Glb Net</th>
+<td align="center">0</td>
+<td align="center">1</td>
+<td align="center">2</td>
+<td align="center">3</td>
+<td align="center">4</td>
+<td align="center">5</td>
+<td align="center">6</td>
+<td align="center">7</td></tr>
+<tr><th>IO Tile</th>
+<td style="white-space: pre; font-family: monospace" align="center"> 7 0</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 7 17</td>
+<td style="white-space: pre; font-family: monospace" align="center">13 9</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 0 9</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 6 17</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 6 0</td>
+<td style="white-space: pre; font-family: monospace" align="center"> 0 8</td>
+<td style="white-space: pre; font-family: monospace" align="center">13 8</td></tr>
+</table>
+</p>
+
+<p><a href="colbuf.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="colbuf.svg" border="0"></a></p>
+
+<h3>Column Buffer Control Bits</h3>
+
+<p>
+Each LOGIC, IO, and RAMB tile has 8 ColBufCtrl bits, one for each global net. In most tiles this
+bits have no function, but in tiles in rows 4, 5, 12, and 13 (for RAM columns: rows 3, 5, 11, and 13) this bits
+control which global nets are driven to the column of tiles below and/or above that tile (including that tile),
+as illustrated in the image to the right (click to enlarge).
+</p>
+
+<p>
+In 8k chips the rows 8, 9, 24, and 25 contain the column buffers. 8k RAMB and
+RAMT tiles can control column buffers, so the pattern looks the same for RAM, LOGIC, and
+IO columns.
+</p>
+
+<h2>Warmboot</h2>
+
+<p>
+The <tt>SB_WARMBOOT</tt> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell
+are driven by the <tt>wire_gbuf/in</tt> signal from three IO tiles. In HX1K chips the tiles connected to the
+<tt>SB_WARMBOOT</tt> primitive are:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Warmboot Pin</th><th>IO Tile</th></tr>
+<tr><td>BOOT</td><td><tt>12 0</tt></td></tr>
+<tr><td>S0</td><td><tt>13 1</tt></td></tr>
+<tr><td>S1</td><td><tt>13 2</tt></td></tr>
+</table>
+</p>
+
+<h2>PLL Cores</h2>
+
+<p>
+The PLL primitives in iCE40 FPGAs are configured using the <tt>PLLCONFIG_*</tt>
+bits in the IO tiles. The configuration for a single PLL cell is spread out
+over many IO tiles. For example, the PLL cell in the 1K chip are configured as
+follows (bits listed from LSB to MSB):
+</p>
+
+<p align="center">
+<table cellpadding="10"><tr><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3">Select PLL Type:<br/>
+000 = DISABLED<br/>
+010 = SB_PLL40_PAD<br/>
+100 = SB_PLL40_2_PAD<br/>
+110 = SB_PLL40_2F_PAD<br/>
+011 = SB_PLL40_CORE<br/>
+111 = SB_PLL40_2F_CORE</td></tr>
+<tr><td>0 5</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 5</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3"><tt>FEEDBACK_PATH</tt><br/>
+000 = "DELAY"<br/>
+001 = "SIMPLE"<br/>
+010 = "PHASE_AND_DELAY"<br/>
+110 = "EXTERNAL"</td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_9</tt></td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_1</tt></td></tr>
+
+<tr><td>0 4</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_FEEDBACK</tt><br/>
+0 = "FIXED"<br/>
+1 = "DYNAMIC"</td></tr>
+
+<tr><td>0 4</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_RELATIVE</tt><br/>
+0 = "FIXED"<br/>
+1 = "DYNAMIC"</td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="2"><tt>PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</tt><br/>
+00 = "GENCLK"<br/>
+01 = "GENCLK_HALF"<br/>
+10 = "SHIFTREG_90deg"<br/>
+11 = "SHIFTREG_0deg"</td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_7</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_2</tt></td><td rowspan="2"><tt>PLLOUT_SELECT_PORTB</tt><br/>
+00 = "GENCLK"<br/>
+01 = "GENCLK_HALF"<br/>
+10 = "SHIFTREG_90deg"<br/>
+11 = "SHIFTREG_0deg"</td></tr>
+<tr><td>0 3</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>SHIFTREG_DIV_MODE</tt></td></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_8</tt></td><td rowspan="1"><tt>TEST_MODE</tt></td></tr>
+
+</table></td><td valign="top">
+
+<table cellpadding="3" border>
+<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
+
+<tr><td>0 3</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="4"><tt>FDA_FEEDBACK</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_2</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_3</tt></td></tr>
+
+<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="4"><tt>FDA_RELATIVE</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_6</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 4</td><td><tt>PLLCONFIG_8</tt></td></tr>
+
+<tr><td>0 1</td><td><tt>PLLCONFIG_1</tt></td><td rowspan="4"><tt>DIVR</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_2</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_3</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_4</tt></td></tr>
+
+<tr><td>0 1</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="7"><tt>DIVF</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_6</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_8</tt></td></tr>
+<tr><td>0 1</td><td><tt>PLLCONFIG_9</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_2</tt></td></tr>
+
+<tr><td>0 2</td><td><tt>PLLCONFIG_3</tt></td><td rowspan="3"><tt>DIVQ</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_4</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_5</tt></td></tr>
+
+<tr><td>0 2</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="3"><tt>FILTER_RANGE</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 2</td><td><tt>PLLCONFIG_8</tt></td></tr>
+
+</table>
+</table>
+</p>
+
+<p>
+The PLL inputs are routed to the PLL via the <tt>wire_gbuf/in</tt> signal from various IO tiles. The non-clock
+PLL outputs are routed via otherwise unused <tt>neigh_op_*</tt> signals in fabric corners. For example in case
+of the 1k chip:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Tile</th><th>Net-Segment</th><th>SB_PLL40_* Port Name</th></tr>
+<tr><td>0 1</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr>
+<tr><td>0 2</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr>
+<tr><td>0 4</td><td><tt>wire_gbuf/in</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr>
+<tr><td>0 5</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 6</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 10</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 11</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 12</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 13</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>0 14</td><td><tt>wire_gbuf/in</tt></td></tr>
+<tr><td>1 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>LOCK</tt></td></tr>
+<tr><td>1 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr>
+<tr><td>2 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr>
+<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr>
+<tr><td>12 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>SDO</tt></td></tr>
+<tr><td>4 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SDI</tt></td></tr>
+<tr><td>5 0</td><td><tt>wire_gbuf/in</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr>
+</table>
+</p>
+
+<p>
+The PLL clock outputs are fed directly into the input path of certain IO tiles.
+In case of the 1k chip the PORTA clock is fed into PIO 1 of IO Tile (6 0) and
+the PORTB clock is fed into PIO 0 of IO Tile (7 0). Because of this, those two
+PIOs can only be used as output Pins by the FPGA fabric when the PLL ports
+are being used.
+</p>
+
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diff --git a/docs/logic_tile.html b/docs/logic_tile.html
new file mode 100644
index 0000000..8e3dcad
--- /dev/null
+++ b/docs/logic_tile.html
@@ -0,0 +1,327 @@
+<title>Project IceStorm – LOGIC Tile Documentation</title>
+<h1>Project IceStorm – LOGIC Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p>
+The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in iCE40 FPGAs. They "span" (have a length of)
+4 or 12 cells in horizontal or vertical direction.
+</p>
+
+<p>
+The bits marked <tt>routing</tt> in the bitstream do enable switches (transfer gates) that can
+be used to connect wire segments bidirectionally to each other in order to create larger
+segments. The bits marked <tt>buffer</tt> in the bitstream enable tristate buffers that drive
+the signal in one direction from one wire to another. Both types of bits exist for routing between
+span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
+</p>
+
+<p>
+Only directional tristate buffers are used to route signals between the span-wires and the logic cells.
+</p>
+
+<h3 style="clear:both">Span-4 Horizontal</h3>
+
+<p><a href="sp4h.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4h.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>horizontal span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+On the left side of the cell there are 48 connections named <tt>sp4_h_l_0</tt> to <tt>sp4_h_l_47</tt>. The lower 36 of those
+wires are connected to <tt>sp4_h_r_12</tt> to <tt>sp4_h_r_47</tt> on the right side of the cell. (IceStorm normalizes this
+wire names to <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_35</tt>. Note: the Lattice tools use a different normalization scheme
+for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.
+</p>
+
+<p>
+The wires <tt>sp4_h_l_36</tt> to <tt>sp4_h_l_47</tt> terminate in the cell, so do the wires <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_11</tt>.
+</p>
+
+<p>
+This wires "span" 4 cells, i.e. they connect 5 cells if you count the cells on
+both ends of the wire.
+</p>
+
+<p>
+For example, the wire <tt>sp4_h_r_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_h_l_* wire name</th><th>sp4_h_r_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_h_r_0</tt></td></tr>
+<tr><td>x+1, y</td><td><tt>sp4_h_l_0</tt></td><td><tt>sp4_h_r_13</tt></td></tr>
+<tr><td>x+2, y</td><td><tt>sp4_h_l_13</tt></td><td><tt>sp4_h_r_24</tt></td></tr>
+<tr><td>x+3, y</td><td><tt>sp4_h_l_24</tt></td><td><tt>sp4_h_r_37</tt></td></tr>
+<tr><td>x+4, y</td><td><tt>sp4_h_l_37</tt></td><td><tt>-</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-4 Vertical</h3>
+
+<p><a href="sp4v.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4v.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>veritical span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+Similar to the horizontal span-4 wires there are 48 connections on the top (<tt>sp4_v_t_0</tt> to <tt>sp4_v_t_47</tt>) and
+48 connections on the bottom (<tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt>). The wires <tt>sp4_v_t_0</tt> to <tt>sp4_v_t_35</tt>
+are connected to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt> (with pairwise crossing out). Wire names are normalized
+to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt>.
+</p>
+
+<p>
+But in addition to that, each cell also has access to <tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt> of its right neighbour.
+This are the wires <tt>sp4_r_v_b_0</tt> to <tt>sp4_r_v_b_47</tt>. So over all a single veritical span-4 wire
+connects 9 cells. For example, the wire <tt>sp4_v_b_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_v_t_* wire name</th><th>sp4_v_b_* wire name</th><th>sp4_r_v_b_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_v_b_0</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-1</td><td><tt>sp4_v_t_0</tt></td><td><tt>sp4_v_b_13</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-2</td><td><tt>sp4_v_t_13</tt></td><td><tt>sp4_v_b_24</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-3</td><td><tt>sp4_v_t_24</tt></td><td><tt>sp4_v_b_37</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-4</td><td><tt>sp4_v_t_37</tt></td><td><tt>-</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x-1, y</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_0</tt></td></tr>
+<tr><td>x-1, y-1</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_13</tt></td></tr>
+<tr><td>x-1, y-2</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_24</tt></td></tr>
+<tr><td>x-1, y-3</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_37</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-12 Horizontal and Vertical</h3>
+
+<p>
+Similar to the span-4 wires there are also longer horizontal and vertical span-12 wires.
+</p>
+
+<p>
+There are 24 connections <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_23</tt> on the top of the
+cell and 24 connections <tt>sp12_v_b_0</tt> to <tt>sp12_v_b_23</tt> on the bottom of the
+cell. The wires <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_21</tt> are connected to
+<tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_v_b_0</tt>, <tt>sp12_v_b_1</tt>, <tt>sp12_v_t_22</tt>, and <tt>sp12_v_t_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt>.
+</p>
+
+<p>
+There are also 24 connections <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_23</tt> on the left of the
+cell and 24 connections <tt>sp12_h_r_0</tt> to <tt>sp12_h_r_23</tt> on the right of the
+cell. The wires <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_21</tt> are connected to
+<tt>sp12_h_r_2</tt> to <tt>sp12_h_r_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_h_r_0</tt>, <tt>sp12_h_r_1</tt>, <tt>sp12_h_l_22</tt>, and <tt>sp12_h_l_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_r_2</tt> to <tt>sp12_h_r_23</tt>.
+</p>
+
+<h2>Local Tracks</h2>
+
+<p>
+The <i>local tracks</i> are the gateway to the logic cell inputs. Signals from the span-wires
+and the logic cell ouputs of the eight neighbour cells can be routed to the local tracks and
+signals from the local tracks can be routed to the logic cell inputs.
+</p>
+
+<p>
+Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each:
+<tt>local_g0_0</tt> to <tt>local_g3_7</tt>.
+</p>
+
+<p>
+The span wires, global signals, and neighbour outputs can be routed to the local tracks. But not
+every of those signals can be routed to every of the local tracks. Instead there is a different
+mix of 16 signals for each local track.
+</p>
+
+<p>
+The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select
+the input wire. For example for <tt>local_g0_0</tt> (copy&paste from the bitstream doku):
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.14">B0[14]</a></th>
+<th style="width:5em"><a name="B.1.14">B1[14]</a></th>
+<th style="width:5em"><a name="B.1.15">B1[15]</a></th>
+<th style="width:5em"><a name="B.1.16">B1[16]</a></th>
+<th style="width:5em"><a name="B.1.17">B1[17]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_24</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bot_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_35</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_top_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>lutff_0/out</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_lft_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bnr_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before,
+not every local track can be routed to every logic cell input pin. Instead there is a different mix
+of 16 local track for each logic cell input. For example for <tt>lutff_0/in_0</tt>:
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.26">B0[26]</a></th>
+<th style="width:5em"><a name="B.1.26">B1[26]</a></th>
+<th style="width:5em"><a name="B.1.27">B1[27]</a></th>
+<th style="width:5em"><a name="B.1.28">B1[28]</a></th>
+<th style="width:5em"><a name="B.1.29">B1[29]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
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+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
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+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+The 8 global nets on the iCE40 can be routed to the local track via the <tt>glb2local_0</tt> to <tt>glb2local_3</tt>
+nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven
+directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven
+from any of the global nets and from a few local tracks. See the bitstream documentation for details.
+</p>
+
+<h2>Logic Block</h2>
+
+<p>
+Each logic tile has a logic block containing 8 logic cells. Each logic cell contains a 4-input LUT, a carry
+unit and a flip-flop. Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the
+bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if
+the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous
+or asynchrouns exist for each logic cell individually.
+</p>
+
+<p>
+Each LUT <i>i</i> has four input wires <tt>lutff_<i>i</i>/in_0</tt> to <tt>lutff_<i>i</i>/in_3</tt>. Input
+<tt>lutff_<i>i</i>/in_3</tt> can be configured to be driven by the carry output of the previous logic cell,
+or by <tt>carry_in_mux</tt> in case of <i>i</i>=0. Input <tt>lutff_<i>i</i>/in_2</tt> can be configured to
+be driven by the output of the previous LUT for <i>i</i>>0. The LUT uses its 4 input signals to
+calculate <tt>lutff_<i>i</i>/out</tt>.
+</p>
+
+<p>
+The carry unit calculates <tt>lutff_<i>i</i>/cout</tt> = <tt>lutff_<i>i</i>/in_1</tt> + <tt>lutff_<i>i</i>/in_2</tt> + <tt>lutff_<i>(i-1)</i>/cout</tt> > 1</tt>. In case of <i>i</i>=0, <tt>carry_in_mux</tt> is used as third input. <tt>carry_in_mux</tt> can be configured to be constant 0, 1 or the <tt>lutff_7/cout</tt> signal from the logic tile below.
+</p>
+
+<p>
+Part of the functionality described above is documented as part of the routing
+bitstream documentation (see the buffers for <tt>luttff_</tt> inputs). The <tt>NegClk</tt>
+bit switches all 8 FFs in the tile to negative edge mode. The <tt>CarryInSet</tt>
+bit drives the <tt>carry_in_mux</tt> high (it defaults to low when not driven via the buffer from
+<tt>carry_in</tt>).
+</p>
+
+<p>
+The remaining functions of the logic cell are configured via the <tt>LC_<i>i</i></tt> bits. This
+are 20 bit per logic cell. We have arbitrarily labeld those bits as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Label</th><th>LC_0</th><th>LC_1</th><th>LC_2</th><th>LC_3</th><th>LC_4</th><th>LC_5</th><th>LC_6</th><th>LC_7</th></tr>
+<tr><td>LC_<i>i</i>[0]</tt></td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr>
+<tr><td>LC_<i>i</i>[1]</tt></td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr>
+<tr><td>LC_<i>i</i>[2]</tt></td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr>
+<tr><td>LC_<i>i</i>[3]</tt></td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr>
+<tr><td>LC_<i>i</i>[4]</tt></td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr>
+<tr><td>LC_<i>i</i>[5]</tt></td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr>
+<tr><td>LC_<i>i</i>[6]</tt></td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr>
+<tr><td>LC_<i>i</i>[7]</tt></td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr>
+<tr><td>LC_<i>i</i>[8]</tt></td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr>
+<tr><td>LC_<i>i</i>[9]</tt></td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr>
+<tr><td>LC_<i>i</i>[10]</tt></td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr>
+<tr><td>LC_<i>i</i>[11]</tt></td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr>
+<tr><td>LC_<i>i</i>[12]</tt></td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr>
+<tr><td>LC_<i>i</i>[13]</tt></td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr>
+<tr><td>LC_<i>i</i>[14]</tt></td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr>
+<tr><td>LC_<i>i</i>[15]</tt></td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr>
+<tr><td>LC_<i>i</i>[16]</tt></td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr>
+<tr><td>LC_<i>i</i>[17]</tt></td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr>
+<tr><td>LC_<i>i</i>[18]</tt></td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr>
+<tr><td>LC_<i>i</i>[19]</tt></td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr>
+</table>
+</p>
+
+<p>
+<tt>LC_<i>i</i>[8]</tt> is the <tt>CarryEnable</tt> bit. This bit must be set if the carry logic is used.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[9]</tt> is the <tt>DffEnable</tt> bit. It enables the output flip-flop for the LUT.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[18]</tt> is the <tt>Set_NoReset</tt> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[19]</tt> is the <tt>AsyncSetReset</tt> bit. When this bit is set then the set/reset signal is asynchronous to the clock.
+</p>
+
+<p>
+The LUT implements the following truth table:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>in_3</th><th>in_2</th><th>in_1</th><th>in_0</th><th>out</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[4]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[14]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[15]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[5]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[6]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[16]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[17]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[7]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[3]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[13]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[12]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[2]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[1]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[11]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[10]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[0]</tt></td></tr>
+</table>
+</p>
+
+<p>
+LUT inputs that are not connected to anything are driven low. The set/reset
+signal is also driven low if not connected to any other driver, and the clock
+enable signal is driven high when left unconnected.
+</p>
+
diff --git a/docs/ram_tile.html b/docs/ram_tile.html
new file mode 100644
index 0000000..3121f57
--- /dev/null
+++ b/docs/ram_tile.html
@@ -0,0 +1,95 @@
+<title>Project IceStorm – RAM Tile Documentation</title>
+<h1>Project IceStorm – RAM Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p>
+Regarding the Span-4 and Span-12 Wires a RAM tile behaves exactly like a LOGIC tile. So for simple
+applications that do not need the block ram resources, the RAM tiles can be handled like a LOGIC
+tiles without logic cells in them.
+</p>
+
+<h2>Block RAM Resources</h2>
+
+<p>
+A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with
+LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram
+inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates
+are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <tt>SB_RAM40_4K</tt> cell. The
+cell ports are spread out over the two tiles as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_RAM40_4K</th><th>RAMB Tile</th><th>RAMT Tile</th></tr>
+<tr><td><tt>RDATA[15:0]</tt></td><td><tt>RDATA[7:0]</tt></td><td><tt>RDATA[15:8]</tt></td></tr>
+<tr><td><tt>RADDR[10:0]</tt></td><td><tt>-</tt></td><td><tt>RADDR[10:0]</tt></td></tr>
+<tr><td><tt>WADDR[10:0]</tt></td><td><tt>WADDR[10:0]</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>MASK[15:0]</tt></td><td><tt>MASK[7:0]</tt></td><td><tt>MASK[15:8]</tt></td></tr>
+<tr><td><tt>WDATA[15:0]</tt></td><td><tt>WDATA[7:0]</tt></td><td><tt>WDATA[15:8]</tt></td></tr>
+<tr><td><tt>RCLKE</tt></td><td><tt>-</tt></td><td><tt>RCLKE</tt></td></tr>
+<tr><td><tt>RCLK</tt></td><td><tt>-</tt></td><td><tt>RCLK</tt></td></tr>
+<tr><td><tt>RE</tt></td><td><tt>-</tt></td><td><tt>RE</tt></td></tr>
+<tr><td><tt>WCLKE</tt></td><td><tt>WCLKE</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>WCLK</tt></td><td><tt>WCLK</tt></td><td><tt>-</tt></td></tr>
+<tr><td><tt>WE</tt></td><td><tt>WE</tt></td><td><tt>-</tt></td></tr>
+</table>
+</p>
+
+<p>
+The configuration bit <tt>RamConfig PowerUp</tt> in the RAMB tile enables the memory. This bit
+is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <tt>icebox_explain.py</tt>
+will ignore all RAMB tiles that only have the <tt>RamConfig PowerUp</tt> bit set.
+</p>
+
+<p>
+In 8k chips the <tt>RamConfig PowerUp</tt> bit is active-high. So an unused RAM block has all bits cleared
+in the 8k config bitstream.
+</p>
+
+<p>
+The <tt>RamConfig CBIT_*</tt> bits in the RAMT tile configure the read/write width of the
+memory. Those bits map to the <tt>SB_RAM40_4K</tt> cell parameters as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>SB_RAM40_4K</th><th>RAMT Config Bit</th></tr>
+<tr><td><tt>WRITE_MODE[0]</tt></td><td><tt>RamConfig CBIT_0</tt></td></tr>
+<tr><td><tt>WRITE_MODE[1]</tt></td><td><tt>RamConfig CBIT_1</tt></td></tr>
+<tr><td><tt>READ_MODE[0]</tt></td><td><tt>RamConfig CBIT_2</tt></td></tr>
+<tr><td><tt>READ_MODE[1]</tt></td><td><tt>RamConfig CBIT_3</tt></td></tr>
+</table>
+</p>
+
+<p>
+The read/write mode selects the width of the read/write port:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>MODE</th><th>DATA Width</th><th>Used WDATA/RDATA Bits</th></tr>
+<tr><td>0</td><td>16</td><td>15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0</td></tr>
+<tr><td>1</td><td>8</td><td>14, 12, 10, 8, 6, 4, 2, 0</td></tr>
+<tr><td>2</td><td>4</td><td>13, 9, 5, 1</td></tr>
+<tr><td>3</td><td>2</td><td>11, 3</td></tr>
+</table>
+</p>
+
+<p>
+The <tt>NegClk</tt> bit in the RAMB tile negates the polarity of the <tt>WCLK</tt> port,
+and the <tt>NegClk</tt> bit in the RAMT tile negates the polarity of the <tt>RCLK</tt> port.
+</p>
+
+<p>
+A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing
+with the <tt>RDATA</tt> outputs. Each RAMB tile exports its <tt>RDATA[7:0]</tt> outputs and each RAMT tile
+exports its <tt>RDATA[15:8]</tt> outputs via this mechanism.
+</p>
+
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diff --git a/icebox/Makefile b/icebox/Makefile
index 64549b3..000836a 100644
--- a/icebox/Makefile
+++ b/icebox/Makefile
@@ -1,13 +1,18 @@
-chipdb: chipdb-1k.txt
+chipdb: chipdb-1k.txt chipdb-8k.txt
chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py
python icebox_chipdb.py > chipdb-1k.new
mv chipdb-1k.new chipdb-1k.txt
+chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py
+ python icebox_chipdb.py -8 > chipdb-8k.new
+ mv chipdb-8k.new chipdb-8k.txt
+
install: chipdb
mkdir -p /usr/local/share/icebox
cp chipdb-1k.txt /usr/local/share/icebox/
+ cp chipdb-8k.txt /usr/local/share/icebox/
cp icebox.py /usr/local/bin/icebox.py
cp iceboxdb.py /usr/local/bin/iceboxdb.py
cp icebox_chipdb.py /usr/local/bin/icebox_chipdb
@@ -27,6 +32,7 @@ uninstall:
rm -f /usr/local/bin/icebox_maps
rm -f /usr/local/bin/icebox_vlog
rm -f /usr/local/share/icebox/chipdb-1k.txt
+ rm -f /usr/local/share/icebox/chipdb-8k.txt
-rmdir /usr/local/share/icebox
.PHONY: install uninstall
diff --git a/icebox/icebox.py b/icebox/icebox.py
index cad6831..c7d76ce 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -59,6 +59,30 @@ class iceconfig:
self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)]
self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)]
+ def setup_empty_8k(self):
+ self.clear()
+ self.device = "8k"
+ self.max_x = 33
+ self.max_y = 33
+
+ for x in range(1, self.max_x):
+ for y in range(1, self.max_y):
+ if x in (8, 25):
+ if y % 2 == 1:
+ self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)]
+ else:
+ self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)]
+ else:
+ self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)]
+
+ for x in range(1, self.max_x):
+ self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)]
+ self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)]
+
+ for y in range(1, self.max_y):
+ self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)]
+ self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)]
+
def lookup_extra_bit(self, bit):
assert self.device in extra_bits_db
if bit in extra_bits_db[self.device]:
@@ -73,8 +97,9 @@ class iceconfig:
return None
def pinloc_db(self):
- assert self.device == "1k"
- return pinloc_db
+ if self.device == "1k": return pinloc_db["1k-tq144"]
+ if self.device == "8k": return pinloc_db["8k-ct256"]
+ assert False
def gbufin_db(self):
return gbufin_db[self.device]
@@ -91,29 +116,55 @@ class iceconfig:
def ieren_db(self):
return ieren_db[self.device]
+ def pll_list(self):
+ if self.device == "1k":
+ return ["1k"]
+ if self.device == "8k":
+ return ["8k_0", "8k_1"]
+ assert False
+
def colbuf_db(self):
- assert self.device == "1k"
- entries = list()
- for x in range(self.max_x+1):
- for y in range(self.max_y+1):
- src_y = None
- if 0 <= y <= 4: src_y = 4
- if 5 <= y <= 8: src_y = 5
- if 9 <= y <= 12: src_y = 12
- if 13 <= y <= 17: src_y = 13
- if x in [3, 10] and src_y == 4: src_y = 3
- if x in [3, 10] and src_y == 12: src_y = 11
- entries.append((x, src_y, x, y))
- return entries
+ if self.device == "1k":
+ entries = list()
+ for x in range(self.max_x+1):
+ for y in range(self.max_y+1):
+ src_y = None
+ if 0 <= y <= 4: src_y = 4
+ if 5 <= y <= 8: src_y = 5
+ if 9 <= y <= 12: src_y = 12
+ if 13 <= y <= 17: src_y = 13
+ if x in [3, 10] and src_y == 4: src_y = 3
+ if x in [3, 10] and src_y == 12: src_y = 11
+ entries.append((x, src_y, x, y))
+ return entries
+
+ if self.device == "8k":
+ entries = list()
+ for x in range(self.max_x+1):
+ for y in range(self.max_y+1):
+ src_y = None
+ if 0 <= y <= 8: src_y = 8
+ if 9 <= y <= 16: src_y = 9
+ if 17 <= y <= 24: src_y = 24
+ if 25 <= y <= 33: src_y = 25
+ entries.append((x, src_y, x, y))
+ return entries
+
+ assert False
def tile_db(self, x, y):
if x == 0: return iotile_l_db
if y == 0: return iotile_b_db
if x == self.max_x: return iotile_r_db
if y == self.max_y: return iotile_t_db
- if (x, y) in self.ramb_tiles: return rambtile_db
- if (x, y) in self.ramt_tiles: return ramttile_db
- if (x, y) in self.logic_tiles: return logictile_db
+ if self.device == "1k":
+ if (x, y) in self.logic_tiles: return logictile_db
+ if (x, y) in self.ramb_tiles: return rambtile_db
+ if (x, y) in self.ramt_tiles: return ramttile_db
+ if self.device == "8k":
+ if (x, y) in self.logic_tiles: return logictile_8k_db
+ if (x, y) in self.ramb_tiles: return rambtile_8k_db
+ if (x, y) in self.ramt_tiles: return ramttile_8k_db
assert False
def tile_type(self, x, y):
@@ -205,9 +256,19 @@ class iceconfig:
if (nx, ny) in self.logic_tiles:
return (nx, ny, "lutff_%d/out" % func)
if (nx, ny) in self.ramb_tiles:
- return (nx, ny, "ram/RDATA_%d" % func)
+ if self.device == "1k":
+ return (nx, ny, "ram/RDATA_%d" % func)
+ elif self.device == "8k":
+ return (nx, ny, "ram/RDATA_%d" % (15-func))
+ else:
+ assert False
if (nx, ny) in self.ramt_tiles:
- return (nx, ny, "ram/RDATA_%d" % (8+func))
+ if self.device == "1k":
+ return (nx, ny, "ram/RDATA_%d" % (8+func))
+ elif self.device == "8k":
+ return (nx, ny, "ram/RDATA_%d" % (7-func))
+ else:
+ assert False
elif pos == "x" and npos in ("l", "r", "t", "b"):
if func in (0, 4): return (nx, ny, "io_0/D_IN_0")
@@ -242,7 +303,12 @@ class iceconfig:
match = re.match(r"ram/RDATA_(\d+)", netname)
if match:
- funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8)
+ if self.device == "1k":
+ funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8)
+ elif self.device == "8k":
+ funcnets |= self.follow_funcnet(x, y, 7 - int(match.group(1)) % 8)
+ else:
+ assert False
return funcnets
@@ -372,16 +438,31 @@ class iceconfig:
for idx, tile in self.logic_tiles.items():
if idx in all_from_tiles:
seed_segments.add((idx[0], idx[1], "lutff_7/cout"))
- add_seed_segments(idx, tile, logictile_db)
+ if self.device == "1k":
+ add_seed_segments(idx, tile, logictile_db)
+ elif self.device == "8k":
+ add_seed_segments(idx, tile, logictile_8k_db)
+ else:
+ assert False
for idx, tile in self.ramb_tiles.items():
- add_seed_segments(idx, tile, rambtile_db)
+ if self.device == "1k":
+ add_seed_segments(idx, tile, rambtile_db)
+ elif self.device == "8k":
+ add_seed_segments(idx, tile, rambtile_8k_db)
+ else:
+ assert False
for idx, tile in self.ramt_tiles.items():
- add_seed_segments(idx, tile, ramttile_db)
+ if self.device == "1k":
+ add_seed_segments(idx, tile, ramttile_db)
+ elif self.device == "8k":
+ add_seed_segments(idx, tile, ramttile_8k_db)
+ else:
+ assert False
for padin, pio in enumerate(self.padin_pio_db()):
- s1 = (pio[0], pio[1], "wire_gbuf/padin_%d" % pio[2])
+ s1 = (pio[0], pio[1], "padin_%d" % pio[2])
s2 = (pio[0], pio[1], "glb_netwk_%d" % padin)
if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
connected_segments.setdefault(s1, set()).add(s2)
@@ -395,7 +476,7 @@ class iceconfig:
if entry[1] == 0 or entry[1] == self.max_y:
iocells = [(i, entry[1]) for i in range(1, self.max_x)]
for cell in iocells:
- s1 = (entry[0], entry[1], "wire_gbuf/in")
+ s1 = (entry[0], entry[1], "fabout")
s2 = (cell[0], cell[1], "io_global/latch")
if s1 in seed_segments or s2 in seed_segments or \
(entry[0], entry[1]) in all_from_tiles or (cell[0], cell[1]) in all_from_tiles:
@@ -406,7 +487,7 @@ class iceconfig:
if connect_gb:
for entry in self.gbufin_db():
- s1 = (entry[0], entry[1], "wire_gbuf/in")
+ s1 = (entry[0], entry[1], "fabout")
s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2])
if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles:
connected_segments.setdefault(s1, set()).add(s2)
@@ -494,7 +575,7 @@ class iceconfig:
self.extra_bits.add((int(line[1]), int(line[2]), int(line[3])))
continue
if line[0] == ".device":
- assert line[1] in ["1k"]
+ assert line[1] in ["1k", "8k"]
self.device = line[1]
continue
if line[0] in [".comment", ".sym"]:
@@ -636,7 +717,7 @@ def sp12v_normalize(netname, edge=""):
return netname
-def netname_normalize(netname, edge="", ramb=False, ramt=False):
+def netname_normalize(netname, edge="", ramb=False, ramt=False, ramb_8k=False, ramt_8k=False):
if netname.startswith("sp4_v_"): return sp4v_normalize(netname, edge)
if netname.startswith("sp4_h_"): return sp4h_normalize(netname, edge)
if netname.startswith("sp12_v_"): return sp12v_normalize(netname, edge)
@@ -647,11 +728,13 @@ def netname_normalize(netname, edge="", ramb=False, ramt=False):
netname = netname.replace("wire_logic_cluster/", "")
netname = netname.replace("wire_io_cluster/", "")
netname = netname.replace("wire_bram/", "")
- if (ramb or ramt) and netname.startswith("input"):
+ if (ramb or ramt or ramb_8k or ramt_8k) and netname.startswith("input"):
match = re.match(r"input(\d)_(\d)", netname)
idx1, idx2 = (int(match.group(1)), int(match.group(2)))
if ramb: netname="ram/WADDR_%d" % (idx1*4 + idx2)
if ramt: netname="ram/RADDR_%d" % (idx1*4 + idx2)
+ if ramb_8k: netname="ram/RADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2])
+ if ramt_8k: netname="ram/WADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2])
match = re.match(r"(...)_op_(.*)", netname)
if match:
netname = "neigh_op_%s_%s" % (match.group(1), match.group(2))
@@ -850,6 +933,7 @@ def run_checks_neigh():
print("Running consistency checks on neighbour finder..")
ic = iceconfig()
ic.setup_empty_1k()
+ # ic.setup_empty_8k()
all_segments = set()
@@ -865,17 +949,12 @@ def run_checks_neigh():
for y in range(ic.max_x+1):
if x in (0, ic.max_x) and y in (0, ic.max_y):
continue
- if x in (0, ic.max_x) or y in (0, ic.max_y):
- add_segments((x, y), ic.tile_db(x, y))
- elif (x, y) in ic.ramb_tiles:
- add_segments((x, y), ic.tile_db(x, y))
- elif (x, y) in ic.ramt_tiles:
- add_segments((x, y), ic.tile_db(x, y))
- else:
- add_segments((x, y), logictile_db)
+ add_segments((x, y), ic.tile_db(x, y))
+ if (x, y) in ic.logic_tiles:
all_segments.add((x, y, "lutff_7/cout"))
for s1 in all_segments:
+ # if s1[1] > 4: continue
for s2 in ic.follow_net(s1):
if s1 not in ic.follow_net(s2):
print("ERROR: %s -> %s, but not vice versa!" % (s1, s2))
@@ -890,9 +969,19 @@ def run_checks_neigh():
def run_checks():
run_checks_neigh()
-def parse_db(text):
+def parse_db(text, grep_8k=False):
db = list()
for line in text.split("\n"):
+ line_1k = line.replace("1k_glb_netwk_", "glb_netwk_")
+ line_8k = line.replace("8k_glb_netwk_", "glb_netwk_")
+ if line_1k != line:
+ if grep_8k:
+ continue
+ line = line_1k
+ elif line_8k != line:
+ if not grep_8k:
+ continue
+ line = line_8k
line = line.split("\t")
if len(line) == 0 or line[0] == "":
continue
@@ -910,6 +999,16 @@ extra_bits_db = {
(1, 331, 142): ("padin_glb_netwk", "5"),
(0, 330, 143): ("padin_glb_netwk", "6"),
(0, 331, 143): ("padin_glb_netwk", "7"),
+ },
+ "8k": {
+ (0, 870, 270): ("padin_glb_netwk", "0"),
+ (0, 871, 270): ("padin_glb_netwk", "1"),
+ (1, 870, 271): ("padin_glb_netwk", "2"),
+ (1, 871, 271): ("padin_glb_netwk", "3"),
+ (1, 870, 270): ("padin_glb_netwk", "4"),
+ (1, 871, 270): ("padin_glb_netwk", "5"),
+ (0, 870, 271): ("padin_glb_netwk", "6"),
+ (0, 871, 271): ("padin_glb_netwk", "7"),
}
}
@@ -923,6 +1022,16 @@ gbufin_db = {
(13, 9, 2),
( 6, 0, 5),
( 6, 17, 4),
+ ],
+ "8k": [
+ (33, 16, 7),
+ ( 0, 16, 6),
+ (17, 33, 1),
+ (17, 0, 0),
+ ( 0, 17, 3),
+ (33, 17, 2),
+ (16, 0, 5),
+ (16, 33, 4),
]
}
@@ -931,43 +1040,311 @@ iolatch_db = {
( 0, 7),
(13, 10),
( 5, 0),
- ( 8, 17)
- ]
+ ( 8, 17),
+ ],
+ "8k": [
+ ( 0, 15),
+ (33, 18),
+ (18, 0),
+ (15, 33),
+ ],
}
-pllinfo_db = {
+warmbootinfo_db = {
"1k": {
- "SHIFTREG_DIV_MODE": (0, 3, "B2[2]"),
- "FDA_FEEDBACK_0": (0, 3, "B7[3]"),
- "FDA_FEEDBACK_1": (0, 4, "B0[2]"),
- "FDA_FEEDBACK_2": (0, 4, "B0[3]"),
- "FDA_FEEDBACK_3": (0, 4, "B3[3]"),
- "FDA_RELATIVE_0": (0, 4, "B2[3]"),
- "FDA_RELATIVE_1": (0, 4, "B5[3]"),
- "FDA_RELATIVE_2": (0, 4, "B4[2]"),
- "FDA_RELATIVE_3": (0, 4, "B4[3]"),
- "DIVR_0": (0, 1, "B0[2]"),
- "DIVR_1": (0, 1, "B0[3]"),
- "DIVR_2": (0, 1, "B3[3]"),
- "DIVR_3": (0, 1, "B2[2]"),
- "DIVF_0": (0, 1, "B2[3]"),
- "DIVF_1": (0, 1, "B5[3]"),
- "DIVF_2": (0, 1, "B4[2]"),
- "DIVF_3": (0, 1, "B4[3]"),
- "DIVF_4": (0, 1, "B7[3]"),
- "DIVF_5": (0, 2, "B0[2]"),
- "DIVF_6": (0, 2, "B0[3]"),
- "DIVQ_0": (0, 0, "?"),
- "DIVQ_1": (0, 0, "?"),
- "DIVQ_2": (0, 0, "?"),
- "FILTER_RANGE_0": (0, 2, "B5[3]"),
- "FILTER_RANGE_1": (0, 2, "B4[2]"),
- "FILTER_RANGE_2": (0, 2, "B4[3]"),
- "ENABLE_ICEGATE": (0, 0, "?"),
- "TEST_MODE": (0, 3, "B4[3]"),
+ "BOOT": ( 12, 0, "fabout" ),
+ "S0": ( 13, 1, "fabout" ),
+ "S1": ( 13, 2, "fabout" ),
+ },
+ "8k": {
+ "BOOT": ( 31, 0, "fabout" ),
+ "S0": ( 33, 1, "fabout" ),
+ "S1": ( 33, 2, "fabout" ),
}
}
+pllinfo_db = {
+ "1k": {
+ "LOC" : (6, 0),
+
+ # 3'b000 = "DISABLED"
+ # 3'b010 = "SB_PLL40_PAD"
+ # 3'b100 = "SB_PLL40_2_PAD"
+ # 3'b110 = "SB_PLL40_2F_PAD"
+ # 3'b011 = "SB_PLL40_CORE"
+ # 3'b111 = "SB_PLL40_2F_CORE"
+ "PLLTYPE_0": ( 0, 3, "PLLCONFIG_5"),
+ "PLLTYPE_1": ( 0, 5, "PLLCONFIG_1"),
+ "PLLTYPE_2": ( 0, 5, "PLLCONFIG_3"),
+
+ # 3'b000 = "DELAY"
+ # 3'b001 = "SIMPLE"
+ # 3'b010 = "PHASE_AND_DELAY"
+ # 3'b110 = "EXTERNAL"
+ "FEEDBACK_PATH_0": ( 0, 5, "PLLCONFIG_5"),
+ "FEEDBACK_PATH_1": ( 0, 2, "PLLCONFIG_9"),
+ "FEEDBACK_PATH_2": ( 0, 3, "PLLCONFIG_1"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111)
+ "DELAY_ADJMODE_FB": ( 0, 4, "PLLCONFIG_4"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111)
+ "DELAY_ADJMODE_REL": ( 0, 4, "PLLCONFIG_9"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_A_0": ( 0, 3, "PLLCONFIG_6"),
+ "PLLOUT_SELECT_A_1": ( 0, 3, "PLLCONFIG_7"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_B_0": ( 0, 3, "PLLCONFIG_2"),
+ "PLLOUT_SELECT_B_1": ( 0, 3, "PLLCONFIG_3"),
+
+ # Numeric Parameters
+ "SHIFTREG_DIV_MODE": ( 0, 3, "PLLCONFIG_4"),
+ "FDA_FEEDBACK_0": ( 0, 3, "PLLCONFIG_9"),
+ "FDA_FEEDBACK_1": ( 0, 4, "PLLCONFIG_1"),
+ "FDA_FEEDBACK_2": ( 0, 4, "PLLCONFIG_2"),
+ "FDA_FEEDBACK_3": ( 0, 4, "PLLCONFIG_3"),
+ "FDA_RELATIVE_0": ( 0, 4, "PLLCONFIG_5"),
+ "FDA_RELATIVE_1": ( 0, 4, "PLLCONFIG_6"),
+ "FDA_RELATIVE_2": ( 0, 4, "PLLCONFIG_7"),
+ "FDA_RELATIVE_3": ( 0, 4, "PLLCONFIG_8"),
+ "DIVR_0": ( 0, 1, "PLLCONFIG_1"),
+ "DIVR_1": ( 0, 1, "PLLCONFIG_2"),
+ "DIVR_2": ( 0, 1, "PLLCONFIG_3"),
+ "DIVR_3": ( 0, 1, "PLLCONFIG_4"),
+ "DIVF_0": ( 0, 1, "PLLCONFIG_5"),
+ "DIVF_1": ( 0, 1, "PLLCONFIG_6"),
+ "DIVF_2": ( 0, 1, "PLLCONFIG_7"),
+ "DIVF_3": ( 0, 1, "PLLCONFIG_8"),
+ "DIVF_4": ( 0, 1, "PLLCONFIG_9"),
+ "DIVF_5": ( 0, 2, "PLLCONFIG_1"),
+ "DIVF_6": ( 0, 2, "PLLCONFIG_2"),
+ "DIVQ_0": ( 0, 2, "PLLCONFIG_3"),
+ "DIVQ_1": ( 0, 2, "PLLCONFIG_4"),
+ "DIVQ_2": ( 0, 2, "PLLCONFIG_5"),
+ "FILTER_RANGE_0": ( 0, 2, "PLLCONFIG_6"),
+ "FILTER_RANGE_1": ( 0, 2, "PLLCONFIG_7"),
+ "FILTER_RANGE_2": ( 0, 2, "PLLCONFIG_8"),
+ "TEST_MODE": ( 0, 3, "PLLCONFIG_8"),
+
+ # PLL Ports
+ "PLLOUT_A": ( 6, 0, 1),
+ "PLLOUT_B": ( 7, 0, 0),
+ "REFERENCECLK": ( 0, 1, "fabout"),
+ "EXTFEEDBACK": ( 0, 2, "fabout"),
+ "DYNAMICDELAY_0": ( 0, 4, "fabout"),
+ "DYNAMICDELAY_1": ( 0, 5, "fabout"),
+ "DYNAMICDELAY_2": ( 0, 6, "fabout"),
+ "DYNAMICDELAY_3": ( 0, 10, "fabout"),
+ "DYNAMICDELAY_4": ( 0, 11, "fabout"),
+ "DYNAMICDELAY_5": ( 0, 12, "fabout"),
+ "DYNAMICDELAY_6": ( 0, 13, "fabout"),
+ "DYNAMICDELAY_7": ( 0, 14, "fabout"),
+ "LOCK": ( 1, 1, "neigh_op_bnl_1"),
+ "BYPASS": ( 1, 0, "fabout"),
+ "RESETB": ( 2, 0, "fabout"),
+ "LATCHINPUTVALUE": ( 5, 0, "fabout"),
+ "SDO": (12, 1, "neigh_op_bnr_3"),
+ "SDI": ( 4, 0, "fabout"),
+ "SCLK": ( 3, 0, "fabout"),
+ },
+ "8k_0": {
+ "LOC" : (16, 0),
+
+ # 3'b000 = "DISABLED"
+ # 3'b010 = "SB_PLL40_PAD"
+ # 3'b100 = "SB_PLL40_2_PAD"
+ # 3'b110 = "SB_PLL40_2F_PAD"
+ # 3'b011 = "SB_PLL40_CORE"
+ # 3'b111 = "SB_PLL40_2F_CORE"
+ "PLLTYPE_0": ( 16, 0, "PLLCONFIG_5"),
+ "PLLTYPE_1": ( 18, 0, "PLLCONFIG_1"),
+ "PLLTYPE_2": ( 18, 0, "PLLCONFIG_3"),
+
+ # 3'b000 = "DELAY"
+ # 3'b001 = "SIMPLE"
+ # 3'b010 = "PHASE_AND_DELAY"
+ # 3'b110 = "EXTERNAL"
+ "FEEDBACK_PATH_0": ( 18, 0, "PLLCONFIG_5"),
+ "FEEDBACK_PATH_1": ( 15, 0, "PLLCONFIG_9"),
+ "FEEDBACK_PATH_2": ( 16, 0, "PLLCONFIG_1"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111)
+ "DELAY_ADJMODE_FB": ( 17, 0, "PLLCONFIG_4"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111)
+ "DELAY_ADJMODE_REL": ( 17, 0, "PLLCONFIG_9"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_A_0": ( 16, 0, "PLLCONFIG_6"),
+ "PLLOUT_SELECT_A_1": ( 16, 0, "PLLCONFIG_7"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_B_0": ( 16, 0, "PLLCONFIG_2"),
+ "PLLOUT_SELECT_B_1": ( 16, 0, "PLLCONFIG_3"),
+
+ # Numeric Parameters
+ "SHIFTREG_DIV_MODE": ( 16, 0, "PLLCONFIG_4"),
+ "FDA_FEEDBACK_0": ( 16, 0, "PLLCONFIG_9"),
+ "FDA_FEEDBACK_1": ( 17, 0, "PLLCONFIG_1"),
+ "FDA_FEEDBACK_2": ( 17, 0, "PLLCONFIG_2"),
+ "FDA_FEEDBACK_3": ( 17, 0, "PLLCONFIG_3"),
+ "FDA_RELATIVE_0": ( 17, 0, "PLLCONFIG_5"),
+ "FDA_RELATIVE_1": ( 17, 0, "PLLCONFIG_6"),
+ "FDA_RELATIVE_2": ( 17, 0, "PLLCONFIG_7"),
+ "FDA_RELATIVE_3": ( 17, 0, "PLLCONFIG_8"),
+ "DIVR_0": ( 14, 0, "PLLCONFIG_1"),
+ "DIVR_1": ( 14, 0, "PLLCONFIG_2"),
+ "DIVR_2": ( 14, 0, "PLLCONFIG_3"),
+ "DIVR_3": ( 14, 0, "PLLCONFIG_4"),
+ "DIVF_0": ( 14, 0, "PLLCONFIG_5"),
+ "DIVF_1": ( 14, 0, "PLLCONFIG_6"),
+ "DIVF_2": ( 14, 0, "PLLCONFIG_7"),
+ "DIVF_3": ( 14, 0, "PLLCONFIG_8"),
+ "DIVF_4": ( 14, 0, "PLLCONFIG_9"),
+ "DIVF_5": ( 15, 0, "PLLCONFIG_1"),
+ "DIVF_6": ( 15, 0, "PLLCONFIG_2"),
+ "DIVQ_0": ( 15, 0, "PLLCONFIG_3"),
+ "DIVQ_1": ( 15, 0, "PLLCONFIG_4"),
+ "DIVQ_2": ( 15, 0, "PLLCONFIG_5"),
+ "FILTER_RANGE_0": ( 15, 0, "PLLCONFIG_6"),
+ "FILTER_RANGE_1": ( 15, 0, "PLLCONFIG_7"),
+ "FILTER_RANGE_2": ( 15, 0, "PLLCONFIG_8"),
+ "TEST_MODE": ( 16, 0, "PLLCONFIG_8"),
+
+ # PLL Ports
+ "PLLOUT_A": ( 16, 0, 1),
+ "PLLOUT_B": ( 17, 0, 0),
+ "REFERENCECLK": ( 13, 0, "fabout"),
+ "EXTFEEDBACK": ( 14, 0, "fabout"),
+ "DYNAMICDELAY_0": ( 5, 0, "fabout"),
+ "DYNAMICDELAY_1": ( 6, 0, "fabout"),
+ "DYNAMICDELAY_2": ( 7, 0, "fabout"),
+ "DYNAMICDELAY_3": ( 8, 0, "fabout"),
+ "DYNAMICDELAY_4": ( 9, 0, "fabout"),
+ "DYNAMICDELAY_5": ( 10, 0, "fabout"),
+ "DYNAMICDELAY_6": ( 11, 0, "fabout"),
+ "DYNAMICDELAY_7": ( 12, 0, "fabout"),
+ "LOCK": ( 1, 1, "neigh_op_bnl_1"),
+ "BYPASS": ( 19, 0, "fabout"),
+ "RESETB": ( 20, 0, "fabout"),
+ "LATCHINPUTVALUE": ( 15, 0, "fabout"),
+ "SDO": ( 32, 1, "neigh_op_bnr_3"),
+ "SDI": ( 22, 0, "fabout"),
+ "SCLK": ( 21, 0, "fabout"),
+ },
+ "8k_1": {
+ "LOC" : (16, 33),
+
+ # 3'b000 = "DISABLED"
+ # 3'b010 = "SB_PLL40_PAD"
+ # 3'b100 = "SB_PLL40_2_PAD"
+ # 3'b110 = "SB_PLL40_2F_PAD"
+ # 3'b011 = "SB_PLL40_CORE"
+ # 3'b111 = "SB_PLL40_2F_CORE"
+ "PLLTYPE_0": ( 16, 33, "PLLCONFIG_5"),
+ "PLLTYPE_1": ( 18, 33, "PLLCONFIG_1"),
+ "PLLTYPE_2": ( 18, 33, "PLLCONFIG_3"),
+
+ # 3'b000 = "DELAY"
+ # 3'b001 = "SIMPLE"
+ # 3'b010 = "PHASE_AND_DELAY"
+ # 3'b110 = "EXTERNAL"
+ "FEEDBACK_PATH_0": ( 18, 33, "PLLCONFIG_5"),
+ "FEEDBACK_PATH_1": ( 15, 33, "PLLCONFIG_9"),
+ "FEEDBACK_PATH_2": ( 16, 33, "PLLCONFIG_1"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111)
+ "DELAY_ADJMODE_FB": ( 17, 33, "PLLCONFIG_4"),
+
+ # 1'b0 = "FIXED"
+ # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111)
+ "DELAY_ADJMODE_REL": ( 17, 33, "PLLCONFIG_9"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_A_0": ( 16, 33, "PLLCONFIG_6"),
+ "PLLOUT_SELECT_A_1": ( 16, 33, "PLLCONFIG_7"),
+
+ # 2'b00 = "GENCLK"
+ # 2'b01 = "GENCLK_HALF"
+ # 2'b10 = "SHIFTREG_90deg"
+ # 2'b11 = "SHIFTREG_0deg"
+ "PLLOUT_SELECT_B_0": ( 16, 33, "PLLCONFIG_2"),
+ "PLLOUT_SELECT_B_1": ( 16, 33, "PLLCONFIG_3"),
+
+ # Numeric Parameters
+ "SHIFTREG_DIV_MODE": ( 16, 33, "PLLCONFIG_4"),
+ "FDA_FEEDBACK_0": ( 16, 33, "PLLCONFIG_9"),
+ "FDA_FEEDBACK_1": ( 17, 33, "PLLCONFIG_1"),
+ "FDA_FEEDBACK_2": ( 17, 33, "PLLCONFIG_2"),
+ "FDA_FEEDBACK_3": ( 17, 33, "PLLCONFIG_3"),
+ "FDA_RELATIVE_0": ( 17, 33, "PLLCONFIG_5"),
+ "FDA_RELATIVE_1": ( 17, 33, "PLLCONFIG_6"),
+ "FDA_RELATIVE_2": ( 17, 33, "PLLCONFIG_7"),
+ "FDA_RELATIVE_3": ( 17, 33, "PLLCONFIG_8"),
+ "DIVR_0": ( 14, 33, "PLLCONFIG_1"),
+ "DIVR_1": ( 14, 33, "PLLCONFIG_2"),
+ "DIVR_2": ( 14, 33, "PLLCONFIG_3"),
+ "DIVR_3": ( 14, 33, "PLLCONFIG_4"),
+ "DIVF_0": ( 14, 33, "PLLCONFIG_5"),
+ "DIVF_1": ( 14, 33, "PLLCONFIG_6"),
+ "DIVF_2": ( 14, 33, "PLLCONFIG_7"),
+ "DIVF_3": ( 14, 33, "PLLCONFIG_8"),
+ "DIVF_4": ( 14, 33, "PLLCONFIG_9"),
+ "DIVF_5": ( 15, 33, "PLLCONFIG_1"),
+ "DIVF_6": ( 15, 33, "PLLCONFIG_2"),
+ "DIVQ_0": ( 15, 33, "PLLCONFIG_3"),
+ "DIVQ_1": ( 15, 33, "PLLCONFIG_4"),
+ "DIVQ_2": ( 15, 33, "PLLCONFIG_5"),
+ "FILTER_RANGE_0": ( 15, 33, "PLLCONFIG_6"),
+ "FILTER_RANGE_1": ( 15, 33, "PLLCONFIG_7"),
+ "FILTER_RANGE_2": ( 15, 33, "PLLCONFIG_8"),
+ "TEST_MODE": ( 16, 33, "PLLCONFIG_8"),
+
+ # PLL Ports
+ "PLLOUT_A": ( 16, 33, 1),
+ "PLLOUT_B": ( 17, 33, 0),
+ "REFERENCECLK": ( 13, 33, "fabout"),
+ "EXTFEEDBACK": ( 14, 33, "fabout"),
+ "DYNAMICDELAY_0": ( 5, 33, "fabout"),
+ "DYNAMICDELAY_1": ( 6, 33, "fabout"),
+ "DYNAMICDELAY_2": ( 7, 33, "fabout"),
+ "DYNAMICDELAY_3": ( 8, 33, "fabout"),
+ "DYNAMICDELAY_4": ( 9, 33, "fabout"),
+ "DYNAMICDELAY_5": ( 10, 33, "fabout"),
+ "DYNAMICDELAY_6": ( 11, 33, "fabout"),
+ "DYNAMICDELAY_7": ( 12, 33, "fabout"),
+ "LOCK": ( 1, 32, "neigh_op_tnl_1"),
+ "BYPASS": ( 19, 33, "fabout"),
+ "RESETB": ( 20, 33, "fabout"),
+ "LATCHINPUTVALUE": ( 15, 33, "fabout"),
+ "SDO": ( 32, 32, "neigh_op_tnr_1"),
+ "SDI": ( 22, 33, "fabout"),
+ "SCLK": ( 21, 33, "fabout"),
+ },
+}
+
padin_pio_db = {
"1k": [
(13, 8, 1), # glb_netwk_0
@@ -978,116 +1355,645 @@ padin_pio_db = {
(13, 9, 0), # glb_netwk_5
( 6, 0, 1), # glb_netwk_6
( 6, 17, 1), # glb_netwk_7
+ ],
+ "8k": [
+ (33, 16, 1),
+ ( 0, 16, 1),
+ (17, 33, 0),
+ (17, 0, 0),
+ ( 0, 17, 0),
+ (33, 17, 0),
+ (16, 0, 1),
+ (16, 33, 1),
]
}
ieren_db = {
"1k": [
# IO-block (X, Y, Z) <-> IeRen-block (X, Y, Z)
- ( 0, 14, 1, 0, 14, 0),
- ( 0, 14, 0, 0, 14, 1),
- ( 0, 13, 1, 0, 13, 0),
- ( 0, 13, 0, 0, 13, 1),
- ( 0, 12, 1, 0, 12, 0),
- ( 0, 12, 0, 0, 12, 1),
- ( 0, 11, 1, 0, 11, 0),
- ( 0, 11, 0, 0, 11, 1),
- ( 0, 10, 1, 0, 10, 0),
- ( 0, 10, 0, 0, 10, 1),
- ( 0, 9, 1, 0, 9, 0),
- ( 0, 9, 0, 0, 9, 1),
- ( 0, 8, 1, 0, 8, 0),
- ( 0, 8, 0, 0, 8, 1),
- ( 0, 6, 1, 0, 6, 0),
- ( 0, 6, 0, 0, 6, 1),
- ( 0, 5, 1, 0, 5, 0),
- ( 0, 5, 0, 0, 5, 1),
- ( 0, 4, 1, 0, 4, 0),
- ( 0, 4, 0, 0, 4, 1),
- ( 0, 3, 1, 0, 3, 0),
- ( 0, 3, 0, 0, 3, 1),
- ( 0, 2, 1, 0, 2, 0),
- ( 0, 2, 0, 0, 2, 1),
- ( 1, 0, 0, 1, 0, 0),
- ( 1, 0, 1, 1, 0, 1),
- ( 2, 0, 0, 2, 0, 0),
- ( 2, 0, 1, 2, 0, 1),
- ( 3, 0, 0, 3, 0, 0),
- ( 3, 0, 1, 3, 0, 1),
- ( 4, 0, 0, 4, 0, 0),
- ( 4, 0, 1, 4, 0, 1),
- ( 5, 0, 0, 5, 0, 0),
- ( 5, 0, 1, 5, 0, 1),
- ( 6, 0, 1, 6, 0, 0),
- ( 7, 0, 0, 6, 0, 1),
- ( 6, 0, 0, 7, 0, 0),
- ( 7, 0, 1, 7, 0, 1),
- ( 8, 0, 0, 8, 0, 0),
- ( 8, 0, 1, 8, 0, 1),
- ( 9, 0, 0, 9, 0, 0),
- ( 9, 0, 1, 9, 0, 1),
- (10, 0, 0, 10, 0, 0),
- (10, 0, 1, 10, 0, 1),
- (11, 0, 0, 11, 0, 0),
- (11, 0, 1, 11, 0, 1),
- (12, 0, 0, 12, 0, 0),
- (12, 0, 1, 12, 0, 1),
- (13, 1, 0, 13, 1, 0),
- (13, 1, 1, 13, 1, 1),
- (13, 2, 0, 13, 2, 0),
- (13, 2, 1, 13, 2, 1),
- (13, 3, 1, 13, 3, 1),
- (13, 4, 0, 13, 4, 0),
- (13, 4, 1, 13, 4, 1),
- (13, 6, 0, 13, 6, 0),
- (13, 6, 1, 13, 6, 1),
- (13, 7, 0, 13, 7, 0),
- (13, 7, 1, 13, 7, 1),
- (13, 8, 0, 13, 8, 0),
- (13, 8, 1, 13, 8, 1),
- (13, 9, 0, 13, 9, 0),
- (13, 9, 1, 13, 9, 1),
- (13, 11, 0, 13, 10, 0),
- (13, 11, 1, 13, 10, 1),
- (13, 12, 0, 13, 11, 0),
- (13, 12, 1, 13, 11, 1),
- (13, 13, 0, 13, 13, 0),
- (13, 13, 1, 13, 13, 1),
- (13, 14, 0, 13, 14, 0),
- (13, 14, 1, 13, 14, 1),
- (13, 15, 0, 13, 15, 0),
- (13, 15, 1, 13, 15, 1),
- (12, 17, 1, 12, 17, 1),
- (12, 17, 0, 12, 17, 0),
- (11, 17, 1, 11, 17, 1),
- (11, 17, 0, 11, 17, 0),
- (10, 17, 1, 9, 17, 1),
- (10, 17, 0, 9, 17, 0),
- ( 9, 17, 1, 10, 17, 1),
- ( 9, 17, 0, 10, 17, 0),
- ( 8, 17, 1, 8, 17, 1),
- ( 8, 17, 0, 8, 17, 0),
- ( 7, 17, 1, 7, 17, 1),
- ( 7, 17, 0, 7, 17, 0),
- ( 6, 17, 1, 6, 17, 1),
- ( 5, 17, 1, 5, 17, 1),
- ( 5, 17, 0, 5, 17, 0),
- ( 4, 17, 1, 4, 17, 1),
- ( 4, 17, 0, 4, 17, 0),
- ( 3, 17, 1, 3, 17, 1),
- ( 3, 17, 0, 3, 17, 0),
- ( 2, 17, 1, 2, 17, 1),
- ( 2, 17, 0, 2, 17, 0),
- ( 1, 17, 1, 1, 17, 1),
- ( 1, 17, 0, 1, 17, 0)
+ ( 0, 2, 0, 0, 2, 1),
+ ( 0, 2, 1, 0, 2, 0),
+ ( 0, 3, 0, 0, 3, 1),
+ ( 0, 3, 1, 0, 3, 0),
+ ( 0, 4, 0, 0, 4, 1),
+ ( 0, 4, 1, 0, 4, 0),
+ ( 0, 5, 0, 0, 5, 1),
+ ( 0, 5, 1, 0, 5, 0),
+ ( 0, 6, 0, 0, 6, 1),
+ ( 0, 6, 1, 0, 6, 0),
+ ( 0, 8, 0, 0, 8, 1),
+ ( 0, 8, 1, 0, 8, 0),
+ ( 0, 9, 0, 0, 9, 1),
+ ( 0, 9, 1, 0, 9, 0),
+ ( 0, 10, 0, 0, 10, 1),
+ ( 0, 10, 1, 0, 10, 0),
+ ( 0, 11, 0, 0, 11, 1),
+ ( 0, 11, 1, 0, 11, 0),
+ ( 0, 12, 0, 0, 12, 1),
+ ( 0, 12, 1, 0, 12, 0),
+ ( 0, 13, 0, 0, 13, 1),
+ ( 0, 13, 1, 0, 13, 0),
+ ( 0, 14, 0, 0, 14, 1),
+ ( 0, 14, 1, 0, 14, 0),
+ ( 1, 0, 0, 1, 0, 0),
+ ( 1, 0, 1, 1, 0, 1),
+ ( 1, 17, 0, 1, 17, 0),
+ ( 1, 17, 1, 1, 17, 1),
+ ( 2, 0, 0, 2, 0, 0),
+ ( 2, 0, 1, 2, 0, 1),
+ ( 2, 17, 0, 2, 17, 0),
+ ( 2, 17, 1, 2, 17, 1),
+ ( 3, 0, 0, 3, 0, 0),
+ ( 3, 0, 1, 3, 0, 1),
+ ( 3, 17, 0, 3, 17, 0),
+ ( 3, 17, 1, 3, 17, 1),
+ ( 4, 0, 0, 4, 0, 0),
+ ( 4, 0, 1, 4, 0, 1),
+ ( 4, 17, 0, 4, 17, 0),
+ ( 4, 17, 1, 4, 17, 1),
+ ( 5, 0, 0, 5, 0, 0),
+ ( 5, 0, 1, 5, 0, 1),
+ ( 5, 17, 0, 5, 17, 0),
+ ( 5, 17, 1, 5, 17, 1),
+ ( 6, 0, 0, 7, 0, 0),
+ ( 6, 0, 1, 6, 0, 0),
+ ( 6, 17, 1, 6, 17, 1),
+ ( 7, 0, 0, 6, 0, 1),
+ ( 7, 0, 1, 7, 0, 1),
+ ( 7, 17, 0, 7, 17, 0),
+ ( 7, 17, 1, 7, 17, 1),
+ ( 8, 0, 0, 8, 0, 0),
+ ( 8, 0, 1, 8, 0, 1),
+ ( 8, 17, 0, 8, 17, 0),
+ ( 8, 17, 1, 8, 17, 1),
+ ( 9, 0, 0, 9, 0, 0),
+ ( 9, 0, 1, 9, 0, 1),
+ ( 9, 17, 0, 10, 17, 0),
+ ( 9, 17, 1, 10, 17, 1),
+ (10, 0, 0, 10, 0, 0),
+ (10, 0, 1, 10, 0, 1),
+ (10, 17, 0, 9, 17, 0),
+ (10, 17, 1, 9, 17, 1),
+ (11, 0, 0, 11, 0, 0),
+ (11, 0, 1, 11, 0, 1),
+ (11, 17, 0, 11, 17, 0),
+ (11, 17, 1, 11, 17, 1),
+ (12, 0, 0, 12, 0, 0),
+ (12, 0, 1, 12, 0, 1),
+ (12, 17, 0, 12, 17, 0),
+ (12, 17, 1, 12, 17, 1),
+ (13, 1, 0, 13, 1, 0),
+ (13, 1, 1, 13, 1, 1),
+ (13, 2, 0, 13, 2, 0),
+ (13, 2, 1, 13, 2, 1),
+ (13, 3, 1, 13, 3, 1),
+ (13, 4, 0, 13, 4, 0),
+ (13, 4, 1, 13, 4, 1),
+ (13, 6, 0, 13, 6, 0),
+ (13, 6, 1, 13, 6, 1),
+ (13, 7, 0, 13, 7, 0),
+ (13, 7, 1, 13, 7, 1),
+ (13, 8, 0, 13, 8, 0),
+ (13, 8, 1, 13, 8, 1),
+ (13, 9, 0, 13, 9, 0),
+ (13, 9, 1, 13, 9, 1),
+ (13, 11, 0, 13, 10, 0),
+ (13, 11, 1, 13, 10, 1),
+ (13, 12, 0, 13, 11, 0),
+ (13, 12, 1, 13, 11, 1),
+ (13, 13, 0, 13, 13, 0),
+ (13, 13, 1, 13, 13, 1),
+ (13, 14, 0, 13, 14, 0),
+ (13, 14, 1, 13, 14, 1),
+ (13, 15, 0, 13, 15, 0),
+ (13, 15, 1, 13, 15, 1),
+ ],
+ "8k": [
+ ( 0, 3, 0, 0, 3, 0),
+ ( 0, 3, 1, 0, 3, 1),
+ ( 0, 4, 0, 0, 4, 0),
+ ( 0, 4, 1, 0, 4, 1),
+ ( 0, 5, 0, 0, 5, 0),
+ ( 0, 5, 1, 0, 5, 1),
+ ( 0, 6, 0, 0, 6, 0),
+ ( 0, 6, 1, 0, 6, 1),
+ ( 0, 7, 0, 0, 7, 0),
+ ( 0, 7, 1, 0, 7, 1),
+ ( 0, 8, 0, 0, 8, 0),
+ ( 0, 8, 1, 0, 8, 1),
+ ( 0, 9, 0, 0, 9, 0),
+ ( 0, 9, 1, 0, 9, 1),
+ ( 0, 10, 0, 0, 10, 0),
+ ( 0, 10, 1, 0, 10, 1),
+ ( 0, 11, 0, 0, 11, 0),
+ ( 0, 11, 1, 0, 11, 1),
+ ( 0, 12, 0, 0, 12, 0),
+ ( 0, 12, 1, 0, 12, 1),
+ ( 0, 13, 0, 0, 13, 0),
+ ( 0, 13, 1, 0, 13, 1),
+ ( 0, 14, 0, 0, 14, 0),
+ ( 0, 14, 1, 0, 14, 1),
+ ( 0, 16, 0, 0, 16, 0),
+ ( 0, 16, 1, 0, 16, 1),
+ ( 0, 17, 0, 0, 17, 0),
+ ( 0, 17, 1, 0, 17, 1),
+ ( 0, 18, 0, 0, 18, 0),
+ ( 0, 18, 1, 0, 18, 1),
+ ( 0, 19, 0, 0, 19, 0),
+ ( 0, 19, 1, 0, 19, 1),
+ ( 0, 20, 0, 0, 20, 0),
+ ( 0, 20, 1, 0, 20, 1),
+ ( 0, 21, 0, 0, 21, 0),
+ ( 0, 21, 1, 0, 21, 1),
+ ( 0, 22, 0, 0, 22, 0),
+ ( 0, 22, 1, 0, 22, 1),
+ ( 0, 23, 0, 0, 23, 0),
+ ( 0, 23, 1, 0, 23, 1),
+ ( 0, 24, 0, 0, 24, 0),
+ ( 0, 24, 1, 0, 24, 1),
+ ( 0, 25, 0, 0, 25, 0),
+ ( 0, 25, 1, 0, 25, 1),
+ ( 0, 27, 0, 0, 27, 0),
+ ( 0, 27, 1, 0, 27, 1),
+ ( 0, 28, 0, 0, 28, 0),
+ ( 0, 28, 1, 0, 28, 1),
+ ( 0, 30, 0, 0, 30, 0),
+ ( 0, 30, 1, 0, 30, 1),
+ ( 0, 31, 0, 0, 31, 0),
+ ( 0, 31, 1, 0, 31, 1),
+ ( 1, 33, 0, 1, 33, 0),
+ ( 1, 33, 1, 1, 33, 1),
+ ( 2, 0, 0, 2, 0, 0),
+ ( 2, 0, 1, 2, 0, 1),
+ ( 2, 33, 0, 2, 33, 0),
+ ( 2, 33, 1, 2, 33, 1),
+ ( 3, 0, 0, 3, 0, 0),
+ ( 3, 0, 1, 3, 0, 1),
+ ( 3, 33, 0, 3, 33, 0),
+ ( 3, 33, 1, 3, 33, 1),
+ ( 4, 0, 0, 4, 0, 0),
+ ( 4, 0, 1, 4, 0, 1),
+ ( 4, 33, 0, 4, 33, 0),
+ ( 4, 33, 1, 4, 33, 1),
+ ( 5, 0, 0, 5, 0, 0),
+ ( 5, 0, 1, 5, 0, 1),
+ ( 5, 33, 0, 5, 33, 0),
+ ( 5, 33, 1, 5, 33, 1),
+ ( 6, 0, 0, 6, 0, 0),
+ ( 6, 0, 1, 6, 0, 1),
+ ( 6, 33, 1, 6, 33, 1),
+ ( 7, 0, 1, 7, 0, 1),
+ ( 7, 33, 0, 7, 33, 0),
+ ( 7, 33, 1, 7, 33, 1),
+ ( 8, 0, 0, 8, 0, 0),
+ ( 8, 33, 0, 8, 33, 0),
+ ( 8, 33, 1, 8, 33, 1),
+ ( 9, 0, 0, 9, 0, 0),
+ ( 9, 0, 1, 9, 0, 1),
+ ( 9, 33, 0, 9, 33, 0),
+ ( 9, 33, 1, 9, 33, 1),
+ (10, 0, 0, 10, 0, 0),
+ (10, 0, 1, 10, 0, 1),
+ (10, 33, 0, 10, 33, 0),
+ (10, 33, 1, 10, 33, 1),
+ (11, 0, 1, 11, 0, 1),
+ (11, 33, 0, 11, 33, 0),
+ (11, 33, 1, 11, 33, 1),
+ (12, 0, 0, 12, 0, 0),
+ (12, 0, 1, 12, 0, 1),
+ (12, 33, 0, 12, 33, 0),
+ (13, 0, 0, 13, 0, 0),
+ (13, 0, 1, 13, 0, 1),
+ (13, 33, 0, 13, 33, 0),
+ (14, 0, 0, 14, 0, 0),
+ (14, 0, 1, 14, 0, 1),
+ (14, 33, 1, 14, 33, 1),
+ (15, 0, 0, 15, 0, 0),
+ (15, 0, 1, 15, 0, 1),
+ (16, 0, 0, 16, 0, 0),
+ (16, 0, 1, 16, 0, 1),
+ (16, 33, 0, 16, 33, 0),
+ (16, 33, 1, 16, 33, 1),
+ (17, 0, 0, 17, 0, 0),
+ (17, 0, 1, 17, 0, 1),
+ (17, 33, 0, 17, 33, 0),
+ (17, 33, 1, 17, 33, 1),
+ (18, 33, 1, 18, 33, 1),
+ (19, 0, 0, 19, 0, 0),
+ (19, 0, 1, 19, 0, 1),
+ (19, 33, 0, 19, 33, 0),
+ (19, 33, 1, 19, 33, 1),
+ (20, 0, 0, 20, 0, 0),
+ (20, 0, 1, 20, 0, 1),
+ (20, 33, 0, 20, 33, 0),
+ (20, 33, 1, 20, 33, 1),
+ (21, 0, 0, 21, 0, 0),
+ (21, 0, 1, 21, 0, 1),
+ (22, 0, 1, 22, 0, 1),
+ (22, 33, 0, 22, 33, 0),
+ (22, 33, 1, 22, 33, 1),
+ (23, 0, 0, 23, 0, 0),
+ (23, 0, 1, 23, 0, 1),
+ (23, 33, 0, 23, 33, 0),
+ (23, 33, 1, 23, 33, 1),
+ (24, 0, 0, 24, 0, 0),
+ (24, 33, 0, 24, 33, 0),
+ (24, 33, 1, 24, 33, 1),
+ (25, 33, 0, 25, 33, 0),
+ (25, 33, 1, 25, 33, 1),
+ (26, 0, 0, 26, 0, 0),
+ (26, 0, 1, 26, 0, 1),
+ (26, 33, 0, 26, 33, 0),
+ (26, 33, 1, 26, 33, 1),
+ (27, 0, 0, 27, 0, 0),
+ (27, 0, 1, 27, 0, 1),
+ (27, 33, 0, 27, 33, 0),
+ (27, 33, 1, 27, 33, 1),
+ (28, 0, 0, 28, 0, 0),
+ (28, 33, 1, 28, 33, 1),
+ (29, 0, 0, 29, 0, 0),
+ (29, 0, 1, 29, 0, 1),
+ (29, 33, 0, 29, 33, 0),
+ (29, 33, 1, 29, 33, 1),
+ (30, 0, 0, 30, 0, 0),
+ (30, 0, 1, 30, 0, 1),
+ (30, 33, 0, 30, 33, 0),
+ (30, 33, 1, 30, 33, 1),
+ (31, 0, 0, 31, 0, 0),
+ (31, 0, 1, 31, 0, 1),
+ (31, 33, 0, 31, 33, 0),
+ (31, 33, 1, 31, 33, 1),
+ (33, 1, 0, 33, 1, 0),
+ (33, 1, 1, 33, 1, 1),
+ (33, 2, 0, 33, 2, 0),
+ (33, 2, 1, 33, 2, 1),
+ (33, 3, 0, 33, 3, 0),
+ (33, 3, 1, 33, 3, 1),
+ (33, 4, 0, 33, 4, 0),
+ (33, 4, 1, 33, 4, 1),
+ (33, 5, 0, 33, 5, 0),
+ (33, 5, 1, 33, 5, 1),
+ (33, 6, 0, 33, 6, 0),
+ (33, 6, 1, 33, 6, 1),
+ (33, 7, 0, 33, 7, 0),
+ (33, 7, 1, 33, 7, 1),
+ (33, 8, 0, 33, 8, 0),
+ (33, 9, 1, 33, 9, 1),
+ (33, 10, 0, 33, 10, 0),
+ (33, 10, 1, 33, 10, 1),
+ (33, 11, 0, 33, 11, 0),
+ (33, 11, 1, 33, 11, 1),
+ (33, 12, 0, 33, 12, 0),
+ (33, 13, 0, 33, 13, 0),
+ (33, 13, 1, 33, 13, 1),
+ (33, 14, 1, 33, 14, 1),
+ (33, 15, 0, 33, 15, 0),
+ (33, 15, 1, 33, 15, 1),
+ (33, 16, 0, 33, 16, 0),
+ (33, 16, 1, 33, 16, 1),
+ (33, 17, 0, 33, 17, 0),
+ (33, 17, 1, 33, 17, 1),
+ (33, 19, 0, 33, 19, 0),
+ (33, 19, 1, 33, 19, 1),
+ (33, 20, 0, 33, 20, 0),
+ (33, 20, 1, 33, 20, 1),
+ (33, 21, 0, 33, 21, 0),
+ (33, 21, 1, 33, 21, 1),
+ (33, 22, 0, 33, 22, 0),
+ (33, 22, 1, 33, 22, 1),
+ (33, 23, 0, 33, 23, 0),
+ (33, 23, 1, 33, 23, 1),
+ (33, 24, 0, 33, 24, 0),
+ (33, 24, 1, 33, 24, 1),
+ (33, 25, 0, 33, 25, 0),
+ (33, 25, 1, 33, 25, 1),
+ (33, 26, 0, 33, 26, 0),
+ (33, 26, 1, 33, 26, 1),
+ (33, 27, 1, 33, 27, 1),
+ (33, 28, 0, 33, 28, 0),
+ (33, 28, 1, 33, 28, 1),
+ (33, 30, 0, 33, 30, 0),
+ (33, 30, 1, 33, 30, 1),
+ (33, 31, 0, 33, 31, 0),
+ ]
+}
+
+pinloc_db = {
+ "1k-tq144": [
+ ( "1", 0, 14, 1),
+ ( "10", 0, 11, 0),
+ ("101", 13, 13, 0),
+ ("102", 13, 13, 1),
+ ("104", 13, 14, 0),
+ ("105", 13, 14, 1),
+ ("106", 13, 15, 0),
+ ("107", 13, 15, 1),
+ ( "11", 0, 10, 1),
+ ("112", 12, 17, 1),
+ ("113", 12, 17, 0),
+ ("114", 11, 17, 1),
+ ("115", 11, 17, 0),
+ ("116", 10, 17, 1),
+ ("117", 10, 17, 0),
+ ("118", 9, 17, 1),
+ ("119", 9, 17, 0),
+ ( "12", 0, 10, 0),
+ ("120", 8, 17, 1),
+ ("121", 8, 17, 0),
+ ("122", 7, 17, 1),
+ ("128", 7, 17, 0),
+ ("129", 6, 17, 1),
+ ("134", 5, 17, 1),
+ ("135", 5, 17, 0),
+ ("136", 4, 17, 1),
+ ("137", 4, 17, 0),
+ ("138", 3, 17, 1),
+ ("139", 3, 17, 0),
+ ("141", 2, 17, 1),
+ ("142", 2, 17, 0),
+ ("143", 1, 17, 1),
+ ("144", 1, 17, 0),
+ ( "19", 0, 9, 1),
+ ( "2", 0, 14, 0),
+ ( "20", 0, 9, 0),
+ ( "21", 0, 8, 1),
+ ( "22", 0, 8, 0),
+ ( "23", 0, 6, 1),
+ ( "24", 0, 6, 0),
+ ( "25", 0, 5, 1),
+ ( "26", 0, 5, 0),
+ ( "28", 0, 4, 1),
+ ( "29", 0, 4, 0),
+ ( "3", 0, 13, 1),
+ ( "31", 0, 3, 1),
+ ( "32", 0, 3, 0),
+ ( "33", 0, 2, 1),
+ ( "34", 0, 2, 0),
+ ( "37", 1, 0, 0),
+ ( "38", 1, 0, 1),
+ ( "39", 2, 0, 0),
+ ( "4", 0, 13, 0),
+ ( "41", 2, 0, 1),
+ ( "42", 3, 0, 0),
+ ( "43", 3, 0, 1),
+ ( "44", 4, 0, 0),
+ ( "45", 4, 0, 1),
+ ( "47", 5, 0, 0),
+ ( "48", 5, 0, 1),
+ ( "49", 6, 0, 1),
+ ( "50", 7, 0, 0),
+ ( "52", 6, 0, 0),
+ ( "56", 7, 0, 1),
+ ( "58", 8, 0, 0),
+ ( "60", 8, 0, 1),
+ ( "61", 9, 0, 0),
+ ( "62", 9, 0, 1),
+ ( "63", 10, 0, 0),
+ ( "64", 10, 0, 1),
+ ( "67", 11, 0, 0),
+ ( "68", 11, 0, 1),
+ ( "7", 0, 12, 1),
+ ( "70", 12, 0, 0),
+ ( "71", 12, 0, 1),
+ ( "73", 13, 1, 0),
+ ( "74", 13, 1, 1),
+ ( "75", 13, 2, 0),
+ ( "76", 13, 2, 1),
+ ( "78", 13, 3, 1),
+ ( "79", 13, 4, 0),
+ ( "8", 0, 12, 0),
+ ( "80", 13, 4, 1),
+ ( "81", 13, 6, 0),
+ ( "87", 13, 6, 1),
+ ( "88", 13, 7, 0),
+ ( "9", 0, 11, 1),
+ ( "90", 13, 7, 1),
+ ( "91", 13, 8, 0),
+ ( "93", 13, 8, 1),
+ ( "94", 13, 9, 0),
+ ( "95", 13, 9, 1),
+ ( "96", 13, 11, 0),
+ ( "97", 13, 11, 1),
+ ( "98", 13, 12, 0),
+ ( "99", 13, 12, 1),
+ ],
+ "8k-ct256": [
+ ( "A1", 4, 33, 1),
+ ("A10", 22, 33, 1),
+ ("A11", 22, 33, 0),
+ ("A15", 27, 33, 0),
+ ("A16", 27, 33, 1),
+ ( "A2", 5, 33, 1),
+ ( "A5", 8, 33, 0),
+ ( "A6", 9, 33, 0),
+ ( "A7", 12, 33, 0),
+ ( "A9", 18, 33, 1),
+ ( "B1", 0, 30, 0),
+ ("B10", 24, 33, 0),
+ ("B11", 23, 33, 1),
+ ("B12", 24, 33, 1),
+ ("B13", 26, 33, 1),
+ ("B14", 30, 33, 0),
+ ("B15", 31, 33, 0),
+ ("B16", 33, 30, 0),
+ ( "B2", 0, 31, 0),
+ ( "B3", 3, 33, 0),
+ ( "B4", 6, 33, 1),
+ ( "B5", 7, 33, 1),
+ ( "B6", 10, 33, 1),
+ ( "B7", 11, 33, 0),
+ ( "B8", 13, 33, 0),
+ ( "B9", 16, 33, 0),
+ ( "C1", 0, 28, 1),
+ ("C10", 23, 33, 0),
+ ("C11", 25, 33, 1),
+ ("C12", 29, 33, 1),
+ ("C13", 28, 33, 1),
+ ("C14", 31, 33, 1),
+ ("C16", 33, 28, 0),
+ ( "C2", 0, 28, 0),
+ ( "C3", 1, 33, 0),
+ ( "C4", 3, 33, 1),
+ ( "C5", 4, 33, 0),
+ ( "C6", 10, 33, 0),
+ ( "C7", 11, 33, 1),
+ ( "C8", 17, 33, 0),
+ ( "C9", 20, 33, 0),
+ ( "D1", 0, 25, 0),
+ ("D10", 20, 33, 1),
+ ("D11", 25, 33, 0),
+ ("D13", 30, 33, 1),
+ ("D14", 33, 31, 0),
+ ("D15", 33, 26, 0),
+ ("D16", 33, 24, 0),
+ ( "D2", 0, 27, 0),
+ ( "D3", 1, 33, 1),
+ ( "D4", 2, 33, 1),
+ ( "D5", 5, 33, 0),
+ ( "D6", 8, 33, 1),
+ ( "D7", 9, 33, 1),
+ ( "D8", 14, 33, 1),
+ ( "D9", 19, 33, 0),
+ ("E10", 26, 33, 0),
+ ("E11", 29, 33, 0),
+ ("E13", 33, 30, 1),
+ ("E14", 33, 27, 1),
+ ("E16", 33, 23, 0),
+ ( "E2", 0, 23, 0),
+ ( "E3", 0, 24, 0),
+ ( "E4", 0, 31, 1),
+ ( "E5", 2, 33, 0),
+ ( "E6", 7, 33, 0),
+ ( "E9", 19, 33, 1),
+ ( "F1", 0, 20, 0),
+ ("F11", 33, 26, 1),
+ ("F12", 33, 25, 1),
+ ("F13", 33, 28, 1),
+ ("F14", 33, 25, 0),
+ ("F15", 33, 22, 0),
+ ("F16", 33, 21, 0),
+ ( "F2", 0, 21, 0),
+ ( "F3", 0, 22, 0),
+ ( "F4", 0, 27, 1),
+ ( "F5", 0, 30, 1),
+ ( "F7", 16, 33, 1),
+ ( "F9", 17, 33, 1),
+ ( "G1", 0, 17, 0),
+ ("G10", 33, 20, 1),
+ ("G11", 33, 21, 1),
+ ("G12", 33, 24, 1),
+ ("G13", 33, 23, 1),
+ ("G14", 33, 22, 1),
+ ("G15", 33, 20, 0),
+ ("G16", 33, 19, 0),
+ ( "G2", 0, 19, 0),
+ ( "G3", 0, 22, 1),
+ ( "G4", 0, 24, 1),
+ ( "G5", 0, 25, 1),
+ ( "H1", 0, 16, 0),
+ ("H11", 33, 16, 1),
+ ("H12", 33, 19, 1),
+ ("H13", 33, 16, 0),
+ ("H14", 33, 17, 1),
+ ("H16", 33, 17, 0),
+ ( "H2", 0, 18, 0),
+ ( "H3", 0, 21, 1),
+ ( "H4", 0, 19, 1),
+ ( "H5", 0, 23, 1),
+ ( "H6", 0, 20, 1),
+ ( "J1", 0, 14, 0),
+ ("J10", 33, 7, 1),
+ ("J11", 33, 9, 1),
+ ("J12", 33, 14, 1),
+ ("J13", 33, 15, 0),
+ ("J14", 33, 13, 1),
+ ("J15", 33, 11, 1),
+ ("J16", 33, 15, 1),
+ ( "J2", 0, 14, 1),
+ ( "J3", 0, 16, 1),
+ ( "J4", 0, 18, 1),
+ ( "J5", 0, 17, 1),
+ ( "K1", 0, 13, 1),
+ ("K11", 29, 0, 0),
+ ("K12", 33, 6, 1),
+ ("K13", 33, 10, 1),
+ ("K14", 33, 11, 0),
+ ("K15", 33, 12, 0),
+ ("K16", 33, 13, 0),
+ ( "K3", 0, 13, 0),
+ ( "K4", 0, 11, 1),
+ ( "K5", 0, 9, 1),
+ ( "K9", 17, 0, 0),
+ ( "L1", 0, 12, 0),
+ ("L10", 19, 0, 1),
+ ("L11", 26, 0, 1),
+ ("L12", 33, 4, 1),
+ ("L13", 33, 5, 1),
+ ("L14", 33, 6, 0),
+ ("L16", 33, 10, 0),
+ ( "L3", 0, 10, 0),
+ ( "L4", 0, 12, 1),
+ ( "L5", 0, 6, 1),
+ ( "L6", 0, 10, 1),
+ ( "L7", 0, 8, 1),
+ ( "L9", 13, 0, 0),
+ ( "M1", 0, 11, 0),
+ ("M11", 23, 0, 1),
+ ("M12", 27, 0, 1),
+ ("M13", 33, 3, 1),
+ ("M14", 33, 4, 0),
+ ("M15", 33, 8, 0),
+ ("M16", 33, 7, 0),
+ ( "M2", 0, 9, 0),
+ ( "M3", 0, 7, 0),
+ ( "M4", 0, 5, 0),
+ ( "M5", 0, 4, 0),
+ ( "M6", 0, 7, 1),
+ ( "M7", 8, 0, 0),
+ ( "M8", 10, 0, 0),
+ ( "M9", 16, 0, 0),
+ ("N10", 20, 0, 1),
+ ("N12", 26, 0, 0),
+ ("N16", 33, 5, 0),
+ ( "N2", 0, 8, 0),
+ ( "N3", 0, 6, 0),
+ ( "N4", 0, 3, 0),
+ ( "N5", 4, 0, 0),
+ ( "N6", 2, 0, 0),
+ ( "N7", 9, 0, 0),
+ ( "N9", 15, 0, 0),
+ ( "P1", 0, 5, 1),
+ ("P10", 20, 0, 0),
+ ("P11", 30, 0, 1),
+ ("P12", 30, 0, 0),
+ ("P13", 29, 0, 1),
+ ("P14", 33, 2, 0),
+ ("P15", 33, 2, 1),
+ ("P16", 33, 3, 0),
+ ( "P2", 0, 4, 1),
+ ( "P4", 3, 0, 0),
+ ( "P5", 5, 0, 0),
+ ( "P6", 9, 0, 1),
+ ( "P7", 14, 0, 1),
+ ( "P8", 12, 0, 0),
+ ( "P9", 17, 0, 1),
+ ( "R1", 0, 3, 1),
+ ("R10", 19, 0, 0),
+ ("R11", 31, 0, 0),
+ ("R12", 31, 0, 1),
+ ("R14", 33, 1, 0),
+ ("R15", 33, 1, 1),
+ ("R16", 28, 0, 0),
+ ( "R2", 3, 0, 1),
+ ( "R3", 5, 0, 1),
+ ( "R4", 7, 0, 1),
+ ( "R5", 6, 0, 0),
+ ( "R6", 11, 0, 1),
+ ( "R9", 16, 0, 1),
+ ( "T1", 2, 0, 1),
+ ("T10", 21, 0, 0),
+ ("T11", 21, 0, 1),
+ ("T13", 24, 0, 0),
+ ("T14", 23, 0, 0),
+ ("T15", 22, 0, 1),
+ ("T16", 27, 0, 0),
+ ( "T2", 4, 0, 1),
+ ( "T3", 6, 0, 1),
+ ( "T5", 10, 0, 1),
+ ( "T6", 12, 0, 1),
+ ( "T7", 13, 0, 1),
+ ( "T8", 14, 0, 0),
+ ( "T9", 15, 0, 1),
]
}
iotile_full_db = parse_db(iceboxdb.database_io_txt)
logictile_db = parse_db(iceboxdb.database_logic_txt)
+logictile_8k_db = parse_db(iceboxdb.database_logic_txt, True)
rambtile_db = parse_db(iceboxdb.database_ramb_txt)
ramttile_db = parse_db(iceboxdb.database_ramt_txt)
-pinloc_db = [[int(s) for s in line.split()] for line in iceboxdb.pinloc_txt.split("\n") if line != ""]
+rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, True)
+ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, True)
iotile_l_db = list()
iotile_r_db = list()
@@ -1120,11 +2026,14 @@ for entry in iotile_full_db:
logictile_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"])
logictile_db.append([["B1[50]"], "CarryInSet"])
-for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, rambtile_db, ramttile_db]:
+logictile_8k_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"])
+logictile_8k_db.append([["B1[50]"], "CarryInSet"])
+
+for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, logictile_8k_db, rambtile_db, ramttile_db, rambtile_8k_db, ramttile_8k_db]:
for entry in db:
if entry[1] in ("buffer", "routing"):
- entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
- entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db))
+ entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db))
+ entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db))
unique_entries = dict()
while db:
entry = db.pop()
diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py
index c673f54..6fa0eaf 100755
--- a/icebox/icebox_chipdb.py
+++ b/icebox/icebox_chipdb.py
@@ -21,8 +21,33 @@ from __future__ import print_function
import icebox
import getopt, sys, re
+mode_8k = False
+
+def usage():
+ print("""
+Usage: icebox_chipdb [options] [bitmap.txt]
+
+ -8
+ create chipdb for 8k device
+""")
+ sys.exit(0)
+
+try:
+ opts, args = getopt.getopt(sys.argv[1:], "8")
+except:
+ usage()
+
+for o, a in opts:
+ if o == "-8":
+ mode_8k = True
+ else:
+ usage()
+
ic = icebox.iceconfig()
-ic.setup_empty_1k()
+if mode_8k:
+ ic.setup_empty_8k()
+else:
+ ic.setup_empty_1k()
all_tiles = set()
for x in range(ic.max_x+1):
@@ -34,7 +59,7 @@ seg_to_net = dict()
net_to_segs = list()
print("""#
-# IceBox Database Dump for iCE40 HX1K / LP1K
+# IceBox Chip Database Dump (iCE40 %s)
#
#
# Quick File Format Reference:
@@ -42,11 +67,11 @@ print("""#
#
# .device DEVICE WIDTH HEIGHT NUM_NETS
#
-# declares the device type (e.g. "1k")
+# declares the device type
#
#
# .pins PACKAGE
-# PIN_NUM TILE_X TILE_Y PIO_NUM GLB_NUM
+# PIN_NUM TILE_X TILE_Y PIO_NUM
# ...
#
# associates a package pin with an IO tile and block, and global network
@@ -56,14 +81,21 @@ print("""#
# TILE_X TILE_Y GLB_NUM
# ...
#
-# associates an IO tile with the global network it drives via wire_gbuf/in
+# associates an IO tile with the global network can drive via fabout
+#
+#
+# .gbufpin
+# TILE_X TILE_Y PIO_NUM GLB_NUM
+# ...
+#
+# associates an IO tile with the global network can drive via the pad
#
#
# .iolatch
# TILE_X TILE_Y
# ...
#
-# specifies the IO tiles that drive the latch signal for the bank via wire_gbuf/in
+# specifies the IO tiles that drive the latch signal for the bank via fabout
#
#
# .ieren
@@ -99,6 +131,13 @@ print("""#
# declares non-routing configuration bits of IO/LOGIC/RAM tiles
#
#
+# .extra_cell X Y <cell-type>
+# KEY MULTI-FIELD-VALUE
+# ....
+#
+# declares a special-purpose cell that is not part of the FPGA fabric
+#
+#
# .extra_bits
# FUNCTION BANK_NUM ADDR_X ADDR_Y
# ...
@@ -129,27 +168,32 @@ print("""#
#
# declares a routing switch in the specified tile
#
-""")
+""" % ic.device)
all_group_segments = ic.group_segments(all_tiles, connect_gb=False)
-print(".device 1k %d %d %d" % (ic.max_x+1, ic.max_y+1, len(all_group_segments)))
+print(".device %s %d %d %d" % (ic.device, ic.max_x+1, ic.max_y+1, len(all_group_segments)))
print()
-print(".pins tq144")
-pio_to_padin = dict()
-for padin, pio in enumerate(ic.padin_pio_db()):
- pio_to_padin[pio] = padin
-for entry in sorted(ic.pinloc_db()):
- pio = (entry[1], entry[2], entry[3])
- print("%d %d %d %d %d" % tuple(entry + [pio_to_padin[pio] if pio in pio_to_padin else -1]))
-print()
+for key in icebox.pinloc_db.keys():
+ key_dev, key_package = key.split("-")
+ if key_dev == ic.device:
+ print(".pins %s" % (key_package))
+ for entry in sorted(icebox.pinloc_db[key]):
+ print("%s %d %d %d" % entry)
+ print()
print(".gbufin")
for entry in sorted(ic.gbufin_db()):
print(" ".join(["%d" % k for k in entry]))
print()
+print(".gbufpin")
+for padin, pio in enumerate(ic.padin_pio_db()):
+ entry = pio + (padin,)
+ print(" ".join(["%d" % k for k in entry]))
+print()
+
print(".iolatch")
for entry in sorted(ic.iolatch_db()):
print(" ".join(["%d" % k for k in entry]))
@@ -208,6 +252,19 @@ print_tile_nonrouting_bits("io", ic.io_tiles.keys()[0])
print_tile_nonrouting_bits("ramb", ic.ramb_tiles.keys()[0])
print_tile_nonrouting_bits("ramt", ic.ramt_tiles.keys()[0])
+print(".extra_cell 0 0 WARMBOOT")
+for key in sorted(icebox.warmbootinfo_db[ic.device]):
+ print("%s %s" % (key, " ".join([str(k) for k in icebox.warmbootinfo_db[ic.device][key]])))
+print()
+
+for pllid in ic.pll_list():
+ pllinfo = icebox.pllinfo_db[pllid]
+ print(".extra_cell %d %d PLL" % pllinfo["LOC"])
+ for key in sorted(pllinfo):
+ if key != "LOC":
+ print("%s %s" % (key, " ".join([str(k) for k in pllinfo[key]])))
+ print()
+
print(".extra_bits")
extra_bits = dict()
for idx in sorted(ic.extra_bits_db()):
diff --git a/icebox/icebox_diff.py b/icebox/icebox_diff.py
index 59fa0a8..efea717 100755
--- a/icebox/icebox_diff.py
+++ b/icebox/icebox_diff.py
@@ -20,6 +20,7 @@ from __future__ import print_function
import icebox
import sys
+import re
print("Reading file '%s'.." % sys.argv[1])
ic1 = icebox.iceconfig()
@@ -38,7 +39,29 @@ def format_bits(line_nr, this_line, other_line):
else:
text += "%8s" % ""
return text
-
+
+def explained_bits(db, tile):
+ bits = set()
+ mapped_bits = set()
+ for k, line in enumerate(tile):
+ for i in range(len(line)):
+ if line[i] == "1":
+ bits.add("B%d[%d]" % (k, i))
+ else:
+ bits.add("!B%d[%d]" % (k, i))
+ text = set()
+ for entry in db:
+ if re.match(r"LC_", entry[1]):
+ continue
+ if entry[1] in ("routing", "buffer"):
+ continue
+ match = True
+ for bit in entry[0]:
+ if not bit in bits:
+ match = False
+ if match:
+ text.add("<%s> %s" % (",".join(entry[0]), " ".join(entry[1:])))
+ return text
def diff_tiles(stmt, tiles1, tiles2):
for i in sorted(set(tiles1.keys() + tiles2.keys())):
@@ -46,11 +69,13 @@ def diff_tiles(stmt, tiles1, tiles2):
print("+ %s %d %d" % (stmt, i[0], i[1]))
for line in tiles2[i]:
print("+ %s" % line)
+ print()
continue
if not i in tiles2:
print("- %s %d %d" % (stmt, i[0], i[1]))
for line in tiles1[i]:
print("- %s" % line)
+ print()
continue
if tiles1[i] == tiles2[i]:
continue
@@ -61,6 +86,15 @@ def diff_tiles(stmt, tiles1, tiles2):
else:
print("- %s%s" % (tiles1[i][c], format_bits(c, tiles1[i][c], tiles2[i][c])))
print("+ %s%s" % (tiles2[i][c], format_bits(c, tiles2[i][c], tiles1[i][c])))
+ bits1 = explained_bits(ic1.tile_db(i[0], i[1]), tiles1[i])
+ bits2 = explained_bits(ic2.tile_db(i[0], i[1]), tiles2[i])
+ for bit in sorted(bits1):
+ if bit not in bits2:
+ print("- %s" % bit)
+ for bit in sorted(bits2):
+ if bit not in bits1:
+ print("+ %s" % bit)
+ print()
diff_tiles(".io_tile", ic1.io_tiles, ic2.io_tiles)
diff_tiles(".logic_tile", ic1.logic_tiles, ic2.logic_tiles)
diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py
index d3779ab..dbd2e5d 100755
--- a/icebox/icebox_html.py
+++ b/icebox/icebox_html.py
@@ -275,7 +275,7 @@ nets are connected with nets from cells in its neighbourhood.</p>""")
cat = (99, "Unsorted")
if netname.startswith("glb_netwk_"): cat = (10, "Global Networks")
if netname.startswith("glb2local_"): cat = (10, "Global Networks")
- if netname.startswith("wire_gbuf"): cat = (10, "Global Networks")
+ if netname.startswith("fabout"): cat = (10, "Global Networks")
if netname.startswith("local_"): cat = (20, "Local Tracks")
if netname.startswith("carry_in"): cat = (25, "Logic Block")
if netname.startswith("io_"): cat = (25, "IO Block")
diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index acf7913..8db925f 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -96,7 +96,10 @@ for o, a in opts:
if not re.match(r"[a-zA-Z_][a-zA-Z0-9_]*$", p):
p = "\\%s " % p
unmatched_ports.add(p)
- pinloc = tuple([int(s) for s in line[2:]])
+ if len(line) > 3:
+ pinloc = tuple([int(s) for s in line[2:]])
+ else:
+ pinloc = (line[2],)
pcf_data[pinloc] = p
elif o == "-R":
check_ieren = True
@@ -135,6 +138,8 @@ iocells_special = set()
iocells_type = dict()
iocells_negclk = set()
iocells_inbufs = set()
+iocells_skip = set()
+iocells_pll = set()
def is_interconn(netname):
if netname.startswith("sp4_"): return True
@@ -146,6 +151,36 @@ def is_interconn(netname):
if netname.startswith("local_"): return True
return False
+pll_config_bitidx = dict()
+pll_gbuf = dict()
+
+for entry in icebox.iotile_l_db:
+ if entry[1] == "PLL":
+ match = re.match(r"B(\d+)\[(\d+)\]", entry[0][0]);
+ assert match
+ pll_config_bitidx[entry[2]] = (int(match.group(1)), int(match.group(2)))
+
+def get_pll_bit(pllinfo, name):
+ bit = pllinfo[name]
+ assert bit[2] in pll_config_bitidx
+ return ic.tile(bit[0], bit[1])[pll_config_bitidx[bit[2]][0]][pll_config_bitidx[bit[2]][1]]
+
+def get_pll_bits(pllinfo, name, n):
+ return "".join([get_pll_bit(pllinfo, "%s_%d" % (name, i)) for i in range(n-1, -1, -1)])
+
+for pllid in ic.pll_list():
+ pllinfo = icebox.pllinfo_db[pllid]
+ plltype = get_pll_bits(pllinfo, "PLLTYPE", 3)
+ if plltype != "000":
+ if plltype in ["010", "100", "110"]:
+ iocells_special.add(pllinfo["PLLOUT_A"])
+ else:
+ iocells_skip.add(pllinfo["PLLOUT_A"])
+ iocells_pll.add(pllinfo["PLLOUT_A"])
+ if plltype not in ["010", "011"]:
+ iocells_skip.add(pllinfo["PLLOUT_B"])
+ iocells_pll.add(pllinfo["PLLOUT_B"])
+
extra_connections = list()
extra_segments = list()
@@ -154,11 +189,15 @@ for bit in ic.extra_bits:
if entry[0] == "padin_glb_netwk":
glb = int(entry[1])
pin_entry = ic.padin_pio_db()[glb]
- iocells.add((pin_entry[0], pin_entry[1], pin_entry[2]))
- iocells_in.add((pin_entry[0], pin_entry[1], pin_entry[2]))
- s1 = (pin_entry[0], pin_entry[1], "io_%d/PAD" % pin_entry[2])
- s2 = (pin_entry[0], pin_entry[1], "wire_gbuf/padin_%d" % pin_entry[2])
- extra_connections.append((s1, s2))
+ if pin_entry in iocells_pll:
+ pll_gbuf[pin_entry] = (pin_entry[0], pin_entry[1], "padin_%d" % pin_entry[2])
+ extra_segments.append(pll_gbuf[pin_entry])
+ else:
+ iocells.add((pin_entry[0], pin_entry[1], pin_entry[2]))
+ iocells_in.add((pin_entry[0], pin_entry[1], pin_entry[2]))
+ s1 = (pin_entry[0], pin_entry[1], "io_%d/PAD" % pin_entry[2])
+ s2 = (pin_entry[0], pin_entry[1], "padin_%d" % pin_entry[2])
+ extra_connections.append((s1, s2))
for idx, tile in ic.io_tiles.items():
tc = icebox.tileconfig(tile)
@@ -187,6 +226,8 @@ for segs in sorted(ic.group_segments()):
match = re.match("io_(\d+)/D_(IN|OUT)_(\d+)", seg[2])
if match:
cell = (seg[0], seg[1], int(match.group(1)))
+ if cell in iocells_skip:
+ continue
iocells.add(cell)
if match.group(2) == "IN":
if check_ieren:
@@ -231,7 +272,7 @@ for segs in sorted(ic.group_segments(extra_connections=extra_connections, extra_
p = "io_%d_%d_%d" % idx
net_segs.add(p)
if lookup_pins or pcf_data:
- for entry in icebox.pinloc_db:
+ for entry in ic.pinloc_db():
if idx[0] == entry[1] and idx[1] == entry[2] and idx[2] == entry[3]:
if (entry[0],) in pcf_data:
p = pcf_data[(entry[0],)]
@@ -310,6 +351,167 @@ def seg_to_net(seg, default=None):
text_wires.append("")
return seg2net[seg]
+wb_boot = seg_to_net(icebox.warmbootinfo_db[ic.device]["BOOT"], "")
+wb_s0 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S0"], "")
+wb_s1 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S1"], "")
+
+if wb_boot != "" or wb_s0 != "" or wb_s1 != "":
+ text_func.append("SB_WARMBOOT (")
+ text_func.append(" .BOOT(%s)," % wb_boot)
+ text_func.append(" .S0(%s)," % wb_s0)
+ text_func.append(" .S1(%s)," % wb_s1)
+ text_func.append(");")
+ text_func.append("")
+
+def get_pll_feedback_path(pllinfo):
+ v = get_pll_bits(pllinfo, "FEEDBACK_PATH", 3)
+ if v == "000": return "DELAY"
+ if v == "001": return "SIMPLE"
+ if v == "010": return "PHASE_AND_DELAY"
+ if v == "110": return "EXTERNAL"
+ assert False
+
+def get_pll_adjmode(pllinfo, name):
+ v = get_pll_bit(pllinfo, name)
+ if v == "0": return "FIXED"
+ if v == "1": return "DYNAMIC"
+ assert False
+
+def get_pll_outsel(pllinfo, name):
+ v = get_pll_bits(pllinfo, name, 2)
+ if v == "00": return "GENCLK"
+ if v == "01": return "GENCLK_HALF"
+ if v == "10": return "SHIFTREG_90deg"
+ if v == "11": return "SHIFTREG_0deg"
+ assert False
+
+for pllid in ic.pll_list():
+ pllinfo = icebox.pllinfo_db[pllid]
+ plltype = get_pll_bits(pllinfo, "PLLTYPE", 3)
+
+ if plltype == "000":
+ continue
+
+ if not strip_comments:
+ text_func.append("// plltype = %s" % plltype)
+ for ti in sorted(ic.io_tiles):
+ for bit in sorted(pll_config_bitidx):
+ if ic.io_tiles[ti][pll_config_bitidx[bit][0]][pll_config_bitidx[bit][1]] == "1":
+ resolved_bitname = ""
+ for bitname in pllinfo:
+ if pllinfo[bitname] == (ti[0], ti[1], bit):
+ resolved_bitname = " " + bitname
+ text_func.append("// (%2d, %2d, \"%s\")%s" % (ti[0], ti[1], bit, resolved_bitname))
+
+ if plltype in ["010", "100", "110"]:
+ if plltype == "010": text_func.append("SB_PLL40_PAD #(")
+ if plltype == "100": text_func.append("SB_PLL40_2_PAD #(")
+ if plltype == "110": text_func.append("SB_PLL40_2F_PAD #(")
+ text_func.append(" .FEEDBACK_PATH(\"%s\")," % get_pll_feedback_path(pllinfo))
+ text_func.append(" .DELAY_ADJUSTMENT_MODE_FEEDBACK(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_FB"))
+ text_func.append(" .DELAY_ADJUSTMENT_MODE_RELATIVE(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_REL"))
+ if plltype == "010":
+ text_func.append(" .PLLOUT_SELECT(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A"))
+ else:
+ if plltype != "100":
+ text_func.append(" .PLLOUT_SELECT_PORTA(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A"))
+ text_func.append(" .PLLOUT_SELECT_PORTB(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_B"))
+ text_func.append(" .SHIFTREG_DIV_MODE(1'b%s)," % get_pll_bit(pllinfo, "SHIFTREG_DIV_MODE"))
+ text_func.append(" .FDA_FEEDBACK(4'b%s)," % get_pll_bits(pllinfo, "FDA_FEEDBACK", 4))
+ text_func.append(" .FDA_RELATIVE(4'b%s)," % get_pll_bits(pllinfo, "FDA_RELATIVE", 4))
+ text_func.append(" .DIVR(4'b%s)," % get_pll_bits(pllinfo, "DIVR", 4))
+ text_func.append(" .DIVF(7'b%s)," % get_pll_bits(pllinfo, "DIVF", 7))
+ text_func.append(" .DIVQ(3'b%s)," % get_pll_bits(pllinfo, "DIVQ", 3))
+ text_func.append(" .FILTER_RANGE(3'b%s)," % get_pll_bits(pllinfo, "FILTER_RANGE", 3))
+ if plltype == "010":
+ text_func.append(" .ENABLE_ICEGATE(1'b0),")
+ else:
+ text_func.append(" .ENABLE_ICEGATE_PORTA(1'b0),")
+ text_func.append(" .ENABLE_ICEGATE_PORTB(1'b0),")
+ text_func.append(" .TEST_MODE(1'b%s)" % get_pll_bit(pllinfo, "TEST_MODE"))
+ text_func.append(") PLL_%d_%d (" % pllinfo["LOC"])
+ if plltype == "010":
+ pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/PAD" % pllinfo["PLLOUT_A"][2])
+ text_func.append(" .PACKAGEPIN(%s)," % seg_to_net(pad_segment))
+ del seg2net[pad_segment]
+ text_func.append(" .PLLOUTCORE(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_A"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBAL(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]]))
+ else:
+ pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/PAD" % pllinfo["PLLOUT_A"][2])
+ text_func.append(" .PACKAGEPIN(%s)," % seg_to_net(pad_segment))
+ del seg2net[pad_segment]
+ text_func.append(" .PLLOUTCOREA(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_A"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBALA(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]]))
+ pad_segment = (pllinfo["PLLOUT_B"][0], pllinfo["PLLOUT_B"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_B"][2])
+ text_func.append(" .PLLOUTCOREB(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_B"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBALB(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_B"]]))
+ text_func.append(" .EXTFEEDBACK(%s)," % seg_to_net(pllinfo["EXTFEEDBACK"], "1'b0"))
+ text_func.append(" .DYNAMICDELAY({%s})," % ", ".join([seg_to_net(pllinfo["DYNAMICDELAY_%d" % i], "1'b0") for i in range(7, -1, -1)]))
+ text_func.append(" .LOCK(%s)," % seg_to_net(pllinfo["LOCK"]))
+ text_func.append(" .BYPASS(%s)," % seg_to_net(pllinfo["BYPASS"], "1'b0"))
+ text_func.append(" .RESETB(%s)," % seg_to_net(pllinfo["RESETB"], "1'b0"))
+ text_func.append(" .LATCHINPUTVALUE(%s)," % seg_to_net(pllinfo["LATCHINPUTVALUE"], "1'b0"))
+ text_func.append(" .SDO(%s)," % seg_to_net(pllinfo["SDO"]))
+ text_func.append(" .SDI(%s)," % seg_to_net(pllinfo["SDI"], "1'b0"))
+ text_func.append(" .SCLK(%s)" % seg_to_net(pllinfo["SCLK"], "1'b0"))
+ text_func.append(");")
+
+ if plltype in ["011", "111"]:
+ if plltype == "011": text_func.append("SB_PLL40_CORE #(")
+ if plltype == "111": text_func.append("SB_PLL40_2F_CORE #(")
+ text_func.append(" .FEEDBACK_PATH(\"%s\")," % get_pll_feedback_path(pllinfo))
+ text_func.append(" .DELAY_ADJUSTMENT_MODE_FEEDBACK(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_FB"))
+ text_func.append(" .DELAY_ADJUSTMENT_MODE_RELATIVE(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_REL"))
+ if plltype == "011":
+ text_func.append(" .PLLOUT_SELECT(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A"))
+ else:
+ text_func.append(" .PLLOUT_SELECT_PORTA(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A"))
+ text_func.append(" .PLLOUT_SELECT_PORTB(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_B"))
+ text_func.append(" .SHIFTREG_DIV_MODE(1'b%s)," % get_pll_bit(pllinfo, "SHIFTREG_DIV_MODE"))
+ text_func.append(" .FDA_FEEDBACK(4'b%s)," % get_pll_bits(pllinfo, "FDA_FEEDBACK", 4))
+ text_func.append(" .FDA_RELATIVE(4'b%s)," % get_pll_bits(pllinfo, "FDA_RELATIVE", 4))
+ text_func.append(" .DIVR(4'b%s)," % get_pll_bits(pllinfo, "DIVR", 4))
+ text_func.append(" .DIVF(7'b%s)," % get_pll_bits(pllinfo, "DIVF", 7))
+ text_func.append(" .DIVQ(3'b%s)," % get_pll_bits(pllinfo, "DIVQ", 3))
+ text_func.append(" .FILTER_RANGE(3'b%s)," % get_pll_bits(pllinfo, "FILTER_RANGE", 3))
+ if plltype == "011":
+ text_func.append(" .ENABLE_ICEGATE(1'b0),")
+ else:
+ text_func.append(" .ENABLE_ICEGATE_PORTA(1'b0),")
+ text_func.append(" .ENABLE_ICEGATE_PORTB(1'b0),")
+ text_func.append(" .TEST_MODE(1'b%s)" % get_pll_bit(pllinfo, "TEST_MODE"))
+ text_func.append(") PLL_%d_%d (" % pllinfo["LOC"])
+ text_func.append(" .REFERENCECLK(%s)," % seg_to_net(pllinfo["REFERENCECLK"], "1'b0"))
+ if plltype == "011":
+ pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_A"][2])
+ text_func.append(" .PLLOUTCORE(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_A"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBAL(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]]))
+ else:
+ pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_A"][2])
+ text_func.append(" .PLLOUTCOREA(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_A"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBALA(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]]))
+ pad_segment = (pllinfo["PLLOUT_B"][0], pllinfo["PLLOUT_B"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_B"][2])
+ text_func.append(" .PLLOUTCOREB(%s)," % seg_to_net(pad_segment))
+ if pllinfo["PLLOUT_B"] in pll_gbuf:
+ text_func.append(" .PLLOUTGLOBALB(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_B"]]))
+ text_func.append(" .EXTFEEDBACK(%s)," % seg_to_net(pllinfo["EXTFEEDBACK"], "1'b0"))
+ text_func.append(" .DYNAMICDELAY({%s})," % ", ".join([seg_to_net(pllinfo["DYNAMICDELAY_%d" % i], "1'b0") for i in range(7, -1, -1)]))
+ text_func.append(" .LOCK(%s)," % seg_to_net(pllinfo["LOCK"]))
+ text_func.append(" .BYPASS(%s)," % seg_to_net(pllinfo["BYPASS"], "1'b0"))
+ text_func.append(" .RESETB(%s)," % seg_to_net(pllinfo["RESETB"], "1'b0"))
+ text_func.append(" .LATCHINPUTVALUE(%s)," % seg_to_net(pllinfo["LATCHINPUTVALUE"], "1'b0"))
+ text_func.append(" .SDO(%s)," % seg_to_net(pllinfo["SDO"]))
+ text_func.append(" .SDI(%s)," % seg_to_net(pllinfo["SDI"], "1'b0"))
+ text_func.append(" .SCLK(%s)" % seg_to_net(pllinfo["SCLK"], "1'b0"))
+ text_func.append(");")
+
+ text_func.append("")
+
for cell in iocells:
if cell in iocells_type:
net_pad = seg_to_net((cell[0], cell[1], "io_%d/PAD" % cell[2]))
@@ -438,6 +640,65 @@ for cell in iocells:
for p in unmatched_ports:
text_ports.append("input %s" % p)
+ram_config_bitidx = dict()
+
+for tile in ic.ramb_tiles:
+ for entry in ic.tile_db(tile[0], tile[1]):
+ if entry[1] == "RamConfig":
+ assert entry[2] not in ram_config_bitidx
+ ram_config_bitidx[entry[2]] = ('B', entry[0])
+ for entry in ic.tile_db(tile[0], tile[1]+1):
+ if entry[1] == "RamConfig":
+ assert entry[2] not in ram_config_bitidx
+ ram_config_bitidx[entry[2]] = ('T', entry[0])
+ break
+
+for tile in ic.ramb_tiles:
+ ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1]))
+ ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1))
+ def get_ram_config(name):
+ assert name in ram_config_bitidx
+ if ram_config_bitidx[name][0] == 'B':
+ return ramb_config.match(ram_config_bitidx[name][1])
+ elif ram_config_bitidx[name][0] == 'T':
+ return ramt_config.match(ram_config_bitidx[name][1])
+ else:
+ assert False
+ def get_ram_wire(name, msb, lsb):
+ wire_bits = []
+ for i in range(msb, lsb-1, -1):
+ if msb != lsb:
+ n = "ram/%s_%d" % (name, i)
+ else:
+ n = "ram/" + name
+ b = seg_to_net((tile[0], tile[1], n), "1'b0")
+ b = seg_to_net((tile[0], tile[1]+1, n), b)
+ if len(wire_bits) != 0 or b != "1'b0" or i == lsb:
+ wire_bits.append(b)
+ if len(wire_bits) > 1:
+ return "{%s}" % ", ".join(wire_bits)
+ return wire_bits[0]
+ if get_ram_config('PowerUp') == (ic.device == "8k"):
+ if not strip_comments:
+ text_func.append("// RAM TILE %d %d" % tile)
+ text_func.append("SB_RAM40_4K #(");
+ text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0)));
+ text_func.append(" .WRITE_MODE(%d)" % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
+ text_func.append(") ram40_%d_%d (" % tile);
+ text_func.append(" .WADDR(%s)," % get_ram_wire('WADDR', 10, 0))
+ text_func.append(" .RADDR(%s)," % get_ram_wire('RADDR', 10, 0))
+ text_func.append(" .MASK(%s)," % get_ram_wire('MASK', 15, 0))
+ text_func.append(" .WDATA(%s)," % get_ram_wire('WDATA', 15, 0))
+ text_func.append(" .RDATA(%s)," % get_ram_wire('RDATA', 15, 0))
+ text_func.append(" .WE(%s)," % get_ram_wire('WE', 0, 0))
+ text_func.append(" .WCLKE(%s)," % get_ram_wire('WCLKE', 0, 0))
+ text_func.append(" .WCLK(%s)," % get_ram_wire('WCLK', 0, 0))
+ text_func.append(" .RE(%s)," % get_ram_wire('RE', 0, 0))
+ text_func.append(" .RCLKE(%s)," % get_ram_wire('RCLKE', 0, 0))
+ text_func.append(" .RCLK(%s)" % get_ram_wire('RCLK', 0, 0))
+ text_func.append(");")
+ text_func.append("")
+
wire_to_reg = set()
lut_assigns = list()
const_assigns = list()
diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py
index 52aa3d0..5488cee 100644
--- a/icebox/iceboxdb.py
+++ b/icebox/iceboxdb.py
@@ -26,15 +26,15 @@ B8[2] IoCtrl LVDS
B6[2] IoCtrl REN_0
B1[3] IoCtrl REN_1
B9[13],B15[13] NegClk
-B0[2] PLL pll_cf_bit_1
-B0[3] PLL pll_cf_bit_2
-B3[3] PLL pll_cf_bit_3
-B2[2] PLL pll_cf_bit_4
-B2[3] PLL pll_cf_bit_5
-B5[3] PLL pll_cf_bit_6
-B4[2] PLL pll_cf_bit_7
-B4[3] PLL pll_cf_bit_8
-B7[3] PLL pll_cf_bit_9
+B0[2] PLL PLLCONFIG_1
+B0[3] PLL PLLCONFIG_2
+B3[3] PLL PLLCONFIG_3
+B2[2] PLL PLLCONFIG_4
+B2[3] PLL PLLCONFIG_5
+B5[3] PLL PLLCONFIG_6
+B4[2] PLL PLLCONFIG_7
+B4[3] PLL PLLCONFIG_8
+B7[3] PLL PLLCONFIG_9
B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnl_0 lc_trk_g0_0
B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnl_0 lc_trk_g1_0
!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_B.logic_op_tnl_1 lc_trk_g0_1
@@ -247,7 +247,7 @@ B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_7 wire_io_cluster/io_1
!B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1
!B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB
!B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g0_0 wire_io_cluster/io_1/inclk
-!B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_1 wire_gbuf/in
+!B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_1 fabout
!B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1
!B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB
!B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0
@@ -256,7 +256,7 @@ B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_7 wire_io_cluster/io_1
!B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1
!B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB
!B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_2 wire_io_cluster/io_1/cen
-B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 wire_gbuf/in
+B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 fabout
!B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1
!B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB
!B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
@@ -265,7 +265,7 @@ B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 wire_gbuf/in
B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1
B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB
!B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g0_4 wire_io_cluster/io_1/outclk
-!B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_5 wire_gbuf/in
+!B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_5 fabout
B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1
B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB
!B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0
@@ -273,11 +273,11 @@ B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_5 wire_io_cluster/io_1/cen
!B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0
B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1
B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB
-B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_7 wire_gbuf/in
+B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_7 fabout
B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1
B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB
!B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0
-!B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_0 wire_gbuf/in
+!B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_0 fabout
!B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1
!B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB
B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0
@@ -286,7 +286,7 @@ B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0
!B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1
!B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB
B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g1_1 wire_io_cluster/io_1/outclk
-B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_2 wire_gbuf/in
+B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_2 fabout
!B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1
!B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB
B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0
@@ -295,7 +295,7 @@ B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0
!B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1
!B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB
B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g1_3 wire_io_cluster/io_1/inclk
-!B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_4 wire_gbuf/in
+!B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_4 fabout
B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1
B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB
B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0
@@ -304,7 +304,7 @@ B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0
B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1
B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB
B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_5 wire_io_cluster/io_1/cen
-B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_6 wire_gbuf/in
+B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_6 fabout
B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1
B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB
B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0
@@ -863,22 +863,22 @@ B13[11],!B13[12] routing span4_vert_t_15 span4_horz_43
!B13[13],B13[14] routing span4_vert_t_15 span4_vert_b_3
"""
database_logic_txt = """
-B0[1] ColBufCtrl glb_netwk_0
-B1[2] ColBufCtrl glb_netwk_1
-B5[2] ColBufCtrl glb_netwk_2
-B7[2] ColBufCtrl glb_netwk_3
-B9[2] ColBufCtrl glb_netwk_4
-B11[2] ColBufCtrl glb_netwk_5
-B13[2] ColBufCtrl glb_netwk_6
-B15[2] ColBufCtrl glb_netwk_7
-B9[7] ColBufCtrl reserved_0
-B8[7] ColBufCtrl reserved_1
-B11[7] ColBufCtrl reserved_2
-B10[7] ColBufCtrl reserved_3
-B13[7] ColBufCtrl reserved_4
-B12[7] ColBufCtrl reserved_5
-B15[7] ColBufCtrl reserved_6
-B14[7] ColBufCtrl reserved_7
+B0[1] ColBufCtrl 1k_glb_netwk_0
+B1[2] ColBufCtrl 1k_glb_netwk_1
+B5[2] ColBufCtrl 1k_glb_netwk_2
+B7[2] ColBufCtrl 1k_glb_netwk_3
+B9[2] ColBufCtrl 1k_glb_netwk_4
+B11[2] ColBufCtrl 1k_glb_netwk_5
+B13[2] ColBufCtrl 1k_glb_netwk_6
+B15[2] ColBufCtrl 1k_glb_netwk_7
+B9[7] ColBufCtrl 8k_glb_netwk_0
+B8[7] ColBufCtrl 8k_glb_netwk_1
+B11[7] ColBufCtrl 8k_glb_netwk_2
+B10[7] ColBufCtrl 8k_glb_netwk_3
+B13[7] ColBufCtrl 8k_glb_netwk_4
+B12[7] ColBufCtrl 8k_glb_netwk_5
+B15[7] ColBufCtrl 8k_glb_netwk_6
+B14[7] ColBufCtrl 8k_glb_netwk_7
B0[36],B0[37],B0[38],B0[39],B0[40],B0[41],B0[42],B0[43],B0[44],B0[45],B1[36],B1[37],B1[38],B1[39],B1[40],B1[41],B1[42],B1[43],B1[44],B1[45] LC_0
B2[36],B2[37],B2[38],B2[39],B2[40],B2[41],B2[42],B2[43],B2[44],B2[45],B3[36],B3[37],B3[38],B3[39],B3[40],B3[41],B3[42],B3[43],B3[44],B3[45] LC_1
B4[36],B4[37],B4[38],B4[39],B4[40],B4[41],B4[42],B4[43],B4[44],B4[45],B5[36],B5[37],B5[38],B5[39],B5[40],B5[41],B5[42],B5[43],B5[44],B5[45] LC_2
@@ -2461,14 +2461,14 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
"""
database_ramb_txt = """
-B0[1] ColBufCtrl glb_netwk_0
-B1[2] ColBufCtrl glb_netwk_1
-B5[2] ColBufCtrl glb_netwk_2
-B7[2] ColBufCtrl glb_netwk_3
-B9[2] ColBufCtrl glb_netwk_4
-B11[2] ColBufCtrl glb_netwk_5
-B13[2] ColBufCtrl glb_netwk_6
-B15[2] ColBufCtrl glb_netwk_7
+B0[1] ColBufCtrl 1k_glb_netwk_0
+B1[2] ColBufCtrl 1k_glb_netwk_1
+B5[2] ColBufCtrl 1k_glb_netwk_2
+B7[2] ColBufCtrl 1k_glb_netwk_3
+B9[2] ColBufCtrl 1k_glb_netwk_4
+B11[2] ColBufCtrl 1k_glb_netwk_5
+B13[2] ColBufCtrl 1k_glb_netwk_6
+B15[2] ColBufCtrl 1k_glb_netwk_7
B0[0] NegClk
B1[7] RamConfig PowerUp
B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0
@@ -5317,101 +5317,2865 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10
B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
"""
-pinloc_txt = """
-10 0 11 0
-101 13 13 0
-1 0 14 1
-102 13 13 1
-104 13 14 0
-105 13 14 1
-106 13 15 0
-107 13 15 1
-11 0 10 1
-112 12 17 1
-113 12 17 0
-114 11 17 1
-115 11 17 0
-116 10 17 1
-117 10 17 0
-118 9 17 1
-119 9 17 0
-12 0 10 0
-120 8 17 1
-121 8 17 0
-122 7 17 1
-128 7 17 0
-129 6 17 1
-134 5 17 1
-135 5 17 0
-136 4 17 1
-137 4 17 0
-138 3 17 1
-139 3 17 0
-141 2 17 1
-142 2 17 0
-143 1 17 1
-144 1 17 0
-19 0 9 1
-20 0 9 0
-2 0 14 0
-21 0 8 1
-22 0 8 0
-23 0 6 1
-24 0 6 0
-25 0 5 1
-26 0 5 0
-28 0 4 1
-29 0 4 0
-3 0 13 1
-31 0 3 1
-32 0 3 0
-33 0 2 1
-34 0 2 0
-37 1 0 0
-38 1 0 1
-39 2 0 0
-4 0 13 0
-41 2 0 1
-42 3 0 0
-43 3 0 1
-44 4 0 0
-45 4 0 1
-47 5 0 0
-48 5 0 1
-49 6 0 1
-50 7 0 0
-52 6 0 0
-56 7 0 1
-58 8 0 0
-60 8 0 1
-61 9 0 0
-62 9 0 1
-63 10 0 0
-64 10 0 1
-67 11 0 0
-68 11 0 1
-70 12 0 0
-7 0 12 1
-71 12 0 1
-73 13 1 0
-74 13 1 1
-75 13 2 0
-76 13 2 1
-78 13 3 1
-79 13 4 0
-8 0 12 0
-80 13 4 1
-81 13 6 0
-87 13 6 1
-88 13 7 0
-9 0 11 1
-90 13 7 1
-91 13 8 0
-93 13 8 1
-94 13 9 0
-95 13 9 1
-96 13 11 0
-97 13 11 1
-98 13 12 0
-99 13 12 1
+database_ramb_8k_txt = """
+B9[7] ColBufCtrl 8k_glb_netwk_0
+B8[7] ColBufCtrl 8k_glb_netwk_1
+B11[7] ColBufCtrl 8k_glb_netwk_2
+B10[7] ColBufCtrl 8k_glb_netwk_3
+B13[7] ColBufCtrl 8k_glb_netwk_4
+B12[7] ColBufCtrl 8k_glb_netwk_5
+B15[7] ColBufCtrl 8k_glb_netwk_6
+B14[7] ColBufCtrl 8k_glb_netwk_7
+B0[0] NegClk
+B1[7] RamConfig PowerUp
+B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
+!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0
+!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK
+!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE
+!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
+!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
+!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
+!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK
+!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE
+B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0
+B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1
+B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2
+B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3
+B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK
+!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE
+B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
+B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
+B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2
+B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK
+!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE
+!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
+!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
+!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
+!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
+!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK
+B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE
+!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0
+!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2
+!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
+!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK
+B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE
+B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
+B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
+B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
+B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
+B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK
+B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE
+B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
+B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1
+B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
+B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3
+B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK
+B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4
+!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6
+!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6
+!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3
+!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5
+!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7
+!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5
+!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9
+!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0
+!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2
+!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4
+!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6
+!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6
+!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10
+!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12
+!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14
+!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8
+!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE
+!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10
+!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12
+!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14
+!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8
+!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1
+!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3
+!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5
+!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7
+!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5
+!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7
+!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11
+!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13
+!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15
+!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9
+!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11
+!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13
+!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15
+!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9
+B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0
+B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2
+B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4
+B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6
+B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6
+B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10
+B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12
+B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14
+B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8
+!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE
+!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10
+!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12
+!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14
+!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8
+B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1
+B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3
+B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5
+B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7
+B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5
+B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7
+B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11
+B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13
+B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15
+B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9
+!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11
+!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13
+!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15
+!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9
+B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0
+B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2
+B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4
+B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6
+B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6
+B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10
+B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12
+B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14
+B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8
+!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10
+!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12
+!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14
+!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8
+B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1
+B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3
+B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5
+B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7
+B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5
+B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7
+B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11
+B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13
+B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15
+B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9
+!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11
+!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13
+!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15
+!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9
+!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1
+!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3
+!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5
+!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7
+!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5
+!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7
+!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11
+!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13
+!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15
+!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9
+B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11
+B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13
+B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15
+B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9
+!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0
+!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2
+!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4
+!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6
+!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6
+!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10
+!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12
+!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14
+!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8
+!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK
+B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10
+B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12
+B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14
+B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8
+!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1
+!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3
+!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5
+!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7
+!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5
+!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7
+!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11
+!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13
+!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15
+!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9
+B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11
+B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13
+B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15
+B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9
+!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0
+!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2
+!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4
+!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6
+!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6
+!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10
+!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12
+!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14
+!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8
+!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE
+B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10
+B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12
+B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14
+B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8
+B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1
+B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3
+B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5
+B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7
+B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5
+B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7
+B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11
+B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13
+B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15
+B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9
+B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11
+B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13
+B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15
+B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9
+B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0
+B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2
+B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4
+B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6
+B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6
+B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10
+B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12
+B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14
+B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8
+!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE
+B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10
+B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12
+B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14
+B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8
+B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1
+B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3
+B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5
+B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7
+B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5
+B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7
+B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11
+B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13
+B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15
+B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9
+B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11
+B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13
+B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15
+B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9
+B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0
+B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2
+B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4
+B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6
+B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6
+B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10
+B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12
+B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14
+B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8
+B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10
+B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12
+B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14
+B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8
+!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0
+!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2
+!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4
+!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6
+!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6
+!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10
+!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12
+!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14
+!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8
+B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK
+!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10
+!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12
+!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14
+!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8
+!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1
+!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3
+!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5
+!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7
+!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5
+!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7
+!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11
+!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13
+!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15
+!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9
+!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11
+!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13
+!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15
+!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9
+!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0
+!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2
+!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4
+!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6
+!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6
+!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10
+!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12
+!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14
+!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8
+B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE
+!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10
+!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12
+!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14
+!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8
+!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1
+!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3
+!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5
+!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7
+!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5
+!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7
+!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11
+!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13
+!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15
+!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9
+!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11
+!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13
+!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15
+!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9
+B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0
+B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2
+B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4
+B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6
+B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6
+B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10
+B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12
+B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14
+B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8
+B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE
+!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10
+!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12
+!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14
+!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8
+B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1
+B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3
+B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5
+B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7
+B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5
+B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7
+B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11
+B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13
+B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15
+B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9
+!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11
+!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13
+!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15
+!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9
+B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0
+B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2
+B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4
+B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6
+B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6
+B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10
+B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12
+B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14
+B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8
+!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10
+!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12
+!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14
+!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8
+B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1
+B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3
+B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5
+B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7
+B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5
+B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7
+B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11
+B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13
+B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15
+B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9
+!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11
+!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13
+!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15
+!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9
+!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1
+!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3
+!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5
+!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7
+!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5
+!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7
+!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11
+!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13
+!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15
+!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9
+B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11
+B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13
+B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15
+B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9
+!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0
+!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2
+!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4
+!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6
+!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6
+!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10
+!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12
+!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14
+!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8
+B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK
+B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10
+B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12
+B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14
+B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8
+!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1
+!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3
+!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5
+!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7
+!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5
+!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7
+!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11
+!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13
+!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15
+!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9
+B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11
+B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13
+B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15
+B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9
+!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0
+!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2
+!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4
+!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6
+!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6
+!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10
+!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12
+!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14
+!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8
+B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE
+B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10
+B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12
+B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14
+B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8
+B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1
+B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3
+B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5
+B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7
+B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5
+B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7
+B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11
+B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13
+B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15
+B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9
+B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11
+B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13
+B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15
+B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9
+B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0
+B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2
+B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4
+B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6
+B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6
+B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10
+B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12
+B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14
+B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8
+B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE
+B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10
+B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12
+B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14
+B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8
+B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1
+B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3
+B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5
+B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7
+B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5
+B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7
+B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11
+B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13
+B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15
+B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9
+B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11
+B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13
+B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15
+B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9
+B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0
+B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2
+B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4
+B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6
+B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6
+B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10
+B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12
+B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14
+B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8
+B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10
+B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12
+B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14
+B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8
+B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7
+B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2
+B12[19] buffer sp12_h_l_1 sp4_h_r_13
+!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7
+!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1
+!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0
+B8[2] buffer sp12_h_l_15 sp4_h_l_9
+!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3
+!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2
+B10[2] buffer sp12_h_l_17 sp4_h_r_21
+B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5
+!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7
+B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4
+B15[19] buffer sp12_h_l_3 sp4_h_l_3
+B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6
+B14[19] buffer sp12_h_l_5 sp4_h_r_15
+!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2
+B3[1] buffer sp12_h_l_9 sp4_h_r_17
+B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0
+B13[19] buffer sp12_h_r_0 sp4_h_l_1
+B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1
+!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4
+B4[2] buffer sp12_h_r_12 sp4_h_r_18
+!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6
+B6[2] buffer sp12_h_r_14 sp4_h_l_6
+!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
+B12[2] buffer sp12_h_r_20 sp4_h_l_11
+!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6
+B14[2] buffer sp12_h_r_22 sp4_h_r_23
+B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3
+B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7
+!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0
+B0[2] buffer sp12_h_r_8 sp4_h_r_16
+!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1
+B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1
+B1[19] buffer sp12_v_b_1 sp4_v_b_12
+!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5
+B7[19] buffer sp12_v_b_13 sp4_v_t_7
+!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2
+!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3
+B8[19] buffer sp12_v_b_19 sp4_v_t_8
+!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6
+B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3
+B0[19] buffer sp12_v_b_3 sp4_v_b_13
+B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5
+B3[19] buffer sp12_v_b_5 sp4_v_b_14
+!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1
+B5[19] buffer sp12_v_b_9 sp4_v_b_16
+B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2
+!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4
+!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7
+B6[19] buffer sp12_v_t_12 sp4_v_t_6
+!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1
+B9[19] buffer sp12_v_t_14 sp4_v_b_20
+!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5
+B11[19] buffer sp12_v_t_18 sp4_v_t_11
+!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7
+B10[19] buffer sp12_v_t_20 sp4_v_b_23
+B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7
+B2[19] buffer sp12_v_t_4 sp4_v_t_2
+B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6
+!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0
+!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3
+B4[19] buffer sp12_v_t_8 sp4_v_t_4
+B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4
+B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6
+!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2
+!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6
+B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3
+B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1
+B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6
+B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3
+B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4
+!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3
+B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7
+B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2
+!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5
+B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7
+!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1
+!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4
+B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5
+!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3
+!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7
+B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0
+B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1
+B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2
+B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5
+!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4
+B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0
+B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3
+B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3
+B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4
+!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0
+B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1
+B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3
+B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3
+B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7
+B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2
+B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3
+B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4
+!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6
+!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1
+!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6
+B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0
+B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2
+B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6
+B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7
+!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1
+!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5
+B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6
+!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2
+!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7
+B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
+B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1
+B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17
+B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10
+B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15
+B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10
+B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42
+B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11
+B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27
+B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43
+B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10
+B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15
+B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31
+B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15
+B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0
+B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7
+B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24
+B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40
+B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8
+B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25
+B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41
+B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9
+B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40
+B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8
+B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13
+B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14
+B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22
+B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5
+B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11
+B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27
+B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6
+B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23
+B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39
+B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7
+B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6
+B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11
+B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27
+B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12
+B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20
+B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4
+B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9
+B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36
+B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4
+B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21
+B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37
+B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5
+B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20
+B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4
+B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25
+B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9
+B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18
+B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1
+B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18
+B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2
+B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34
+B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19
+B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3
+B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35
+B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2
+B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34
+B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7
+B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8
+B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0
+B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16
+B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0
+B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16
+B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32
+B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1
+B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17
+B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33
+B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0
+B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16
+B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32
+B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5
+B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22
+B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14
+B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19
+B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3
+B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46
+B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15
+B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31
+B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47
+B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14
+B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46
+B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19
+B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3
+B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20
+B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11
+B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1
+B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28
+B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44
+B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13
+B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29
+B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45
+B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12
+B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28
+B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44
+!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1
+!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1
+!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22
+!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0
+!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0
+!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23
+B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23
+B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0
+B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23
+B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22
+B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1
+B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22
+!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23
+B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0
+B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23
+!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22
+B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1
+B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22
+B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22
+B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1
+B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1
+B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23
+B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0
+B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0
+B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1
+!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4
+!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9
+B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1
+B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7
+B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36
+!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43
+!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0
+B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3
+!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8
+B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0
+B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6
+!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37
+B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40
+!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11
+!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3
+B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6
+B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3
+B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9
+!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38
+B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45
+B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10
+!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2
+B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5
+!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2
+B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8
+!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39
+!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42
+B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1
+!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5
+B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8
+B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11
+!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5
+!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40
+!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47
+!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0
+B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4
+!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7
+B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10
+B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4
+B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41
+!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44
+!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10
+!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3
+B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7
+B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1
+B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7
+!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37
+B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42
+!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2
+!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6
+B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9
+B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0
+B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6
+!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43
+B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46
+B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0
+!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5
+!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9
+B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3
+B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9
+B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39
+!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44
+B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11
+B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4
+!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8
+B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2
+!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8
+!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36
+!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45
+!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11
+B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2
+B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7
+!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11
+B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5
+!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41
+!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46
+!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1
+B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10
+!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6
+B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10
+B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4
+!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38
+B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47
+!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37
+B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38
+!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45
+!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0
+B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5
+B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37
+B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43
+B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36
+!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41
+!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44
+B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1
+!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6
+B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36
+B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42
+!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36
+!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43
+B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47
+B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10
+!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3
+B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41
+B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47
+B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39
+B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42
+!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46
+!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11
+!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4
+B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40
+!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46
+!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39
+B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40
+B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47
+!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2
+!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7
+!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39
+B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45
+!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38
+B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43
+!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46
+!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3
+B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8
+B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38
+B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44
+!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37
+B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41
+!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42
+B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4
+!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9
+B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41
+B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47
+B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36
+!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40
+B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45
+!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10
+!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5
+!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40
+B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46
+!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39
+!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43
+B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44
+B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11
+!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6
+B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37
+B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43
+!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38
+B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42
+!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47
+!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0
+B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7
+B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36
+B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42
+B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41
+!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45
+B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46
+!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1
+!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8
+B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39
+!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45
+B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37
+!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40
+!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44
+B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2
+!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9
+B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38
+B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44
+B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37
+!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40
+B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0
+B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6
+B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37
+!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38
+B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45
+!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36
+!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43
+B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1
+B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7
+!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36
+B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41
+B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44
+!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38
+!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47
+B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10
+B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4
+B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36
+B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43
+!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47
+!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41
+B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46
+B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11
+B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5
+B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39
+!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42
+!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46
+B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39
+!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42
+B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2
+B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8
+!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39
+B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40
+!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47
+B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38
+!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45
+B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3
+B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9
+B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38
+!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43
+B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46
+!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41
+!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44
+B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10
+B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4
+B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37
+!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41
+B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42
+B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40
+!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47
+B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11
+B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5
+!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36
+!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40
+B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45
+B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43
+!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46
+B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0
+B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6
+B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39
+B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43
+!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44
+!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37
+!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42
+B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1
+B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7
+B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38
+!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42
+B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47
+!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36
+B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45
+B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2
+B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8
+!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41
+!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45
+B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46
+!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39
+B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44
+B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3
+B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9
+!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37
+B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40
+B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44
+B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36
+B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42
+!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1
+!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6
+!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1
+B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4
+B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9
+B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37
+B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43
+B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0
+!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5
+B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0
+!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3
+B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8
+B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38
+B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44
+B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3
+!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8
+B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11
+B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3
+!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6
+B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39
+B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45
+B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2
+!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7
+!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10
+!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2
+B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5
+B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40
+B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46
+!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10
+B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5
+!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1
+!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5
+B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8
+B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41
+B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47
+!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4
+!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9
+B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0
+!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4
+B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7
+B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36
+B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42
+!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0
+!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7
+B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10
+B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3
+!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7
+B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37
+B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43
+!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11
+B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6
+B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2
+B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6
+!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9
+B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38
+B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44
+!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2
+B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9
+!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0
+B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5
+B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9
+B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39
+B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45
+!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1
+B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8
+B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11
+!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4
+!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8
+B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40
+B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46
+B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11
+!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4
+!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11
+B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2
+!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7
+B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41
+B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47
+!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10
+!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3
+B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
+!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10
+B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
+"""
+database_ramt_8k_txt = """
+B9[7] ColBufCtrl 8k_glb_netwk_0
+B8[7] ColBufCtrl 8k_glb_netwk_1
+B11[7] ColBufCtrl 8k_glb_netwk_2
+B10[7] ColBufCtrl 8k_glb_netwk_3
+B13[7] ColBufCtrl 8k_glb_netwk_4
+B12[7] ColBufCtrl 8k_glb_netwk_5
+B15[7] ColBufCtrl 8k_glb_netwk_6
+B14[7] ColBufCtrl 8k_glb_netwk_7
+B0[0] NegClk
+B1[7] RamConfig CBIT_0
+B0[7] RamConfig CBIT_1
+B3[7] RamConfig CBIT_2
+B2[7] RamConfig CBIT_3
+B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0
+B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0
+!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1
+!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3
+B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4
+B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4
+!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5
+!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7
+B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0
+B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3
+B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4
+B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7
+!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4
+!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5
+!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6
+!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7
+!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0
+!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1
+!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2
+!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3
+!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK
+!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE
+!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0
+!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1
+!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2
+!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3
+!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK
+!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE
+B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0
+B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1
+B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2
+B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3
+B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK
+!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE
+B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0
+B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1
+B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2
+B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3
+B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK
+!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE
+!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0
+!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1
+!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2
+!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3
+!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK
+B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE
+!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0
+!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1
+!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2
+!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3
+!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK
+B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE
+B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0
+B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1
+B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2
+B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3
+B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK
+B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE
+B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0
+B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1
+B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2
+B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3
+B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK
+B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE
+!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0
+!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2
+!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4
+!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6
+!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6
+!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK
+!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0
+!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2
+!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4
+!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6
+!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1
+!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3
+!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5
+!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7
+!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5
+!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7
+!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1
+!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3
+!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5
+!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7
+!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0
+!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2
+!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4
+!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6
+!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6
+!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0
+!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2
+!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4
+!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6
+!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE
+!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0
+!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2
+!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4
+!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6
+!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1
+!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3
+!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5
+!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7
+!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5
+!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7
+!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1
+!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3
+!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5
+!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7
+!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1
+!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3
+!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5
+!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7
+B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0
+B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2
+B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4
+B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6
+B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6
+B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0
+B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2
+B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4
+B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6
+!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0
+!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2
+!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4
+!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6
+!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE
+B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1
+B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3
+B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5
+B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7
+B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5
+B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7
+B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1
+B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3
+B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5
+B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7
+!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1
+!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3
+!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5
+!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7
+B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0
+B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2
+B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4
+B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6
+B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6
+B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0
+B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2
+B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4
+B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6
+!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0
+!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2
+!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4
+!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6
+B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1
+B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3
+B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5
+B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7
+B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5
+B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7
+B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1
+B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3
+B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5
+B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7
+!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1
+!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3
+!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5
+!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7
+!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1
+!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3
+!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5
+!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7
+!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5
+!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7
+!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1
+!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3
+!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5
+!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7
+B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1
+B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3
+B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5
+B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7
+!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0
+!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2
+!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4
+!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6
+!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6
+!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0
+!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2
+!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4
+!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6
+!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK
+B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0
+B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2
+B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4
+B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6
+!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1
+!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3
+!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5
+!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7
+!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5
+!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7
+!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1
+!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3
+!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5
+!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7
+B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1
+B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3
+B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5
+B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7
+!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0
+!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2
+!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4
+!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6
+!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6
+!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0
+!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2
+!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4
+!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6
+!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE
+B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0
+B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2
+B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4
+B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6
+B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1
+B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3
+B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5
+B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7
+B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5
+B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7
+B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1
+B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3
+B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5
+B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7
+B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1
+B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3
+B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5
+B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7
+B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0
+B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2
+B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4
+B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6
+B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6
+B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0
+B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2
+B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4
+B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6
+B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0
+B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2
+B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4
+B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6
+!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE
+B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1
+B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3
+B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5
+B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7
+B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5
+B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7
+B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1
+B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3
+B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5
+B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7
+B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1
+B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3
+B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5
+B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7
+B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0
+B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2
+B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4
+B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6
+B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6
+B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0
+B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2
+B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4
+B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6
+B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0
+B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2
+B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4
+B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6
+!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0
+!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2
+!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4
+!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6
+!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6
+!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0
+!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2
+!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4
+!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6
+B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK
+!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0
+!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2
+!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4
+!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6
+!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1
+!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3
+!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5
+!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7
+!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5
+!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7
+!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1
+!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3
+!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5
+!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7
+!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1
+!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3
+!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5
+!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7
+!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0
+!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2
+!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4
+!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6
+!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6
+!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0
+!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2
+!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4
+!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6
+B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE
+!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0
+!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2
+!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4
+!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6
+!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1
+!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3
+!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5
+!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7
+!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5
+!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7
+!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1
+!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3
+!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5
+!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7
+!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1
+!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3
+!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5
+!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7
+B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0
+B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2
+B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4
+B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6
+B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6
+B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0
+B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2
+B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4
+B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6
+!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0
+!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2
+!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4
+!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6
+B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE
+B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1
+B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3
+B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5
+B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7
+B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5
+B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7
+B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1
+B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3
+B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5
+B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7
+!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1
+!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3
+!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5
+!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7
+B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0
+B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2
+B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4
+B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6
+B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6
+B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0
+B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2
+B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4
+B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6
+!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0
+!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2
+!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4
+!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6
+B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1
+B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3
+B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5
+B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7
+B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5
+B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7
+B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1
+B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3
+B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5
+B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7
+!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1
+!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3
+!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5
+!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7
+!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1
+!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3
+!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5
+!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7
+!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5
+!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7
+!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1
+!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3
+!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5
+!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7
+B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1
+B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3
+B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5
+B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7
+!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0
+!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2
+!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4
+!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6
+!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6
+!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0
+!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2
+!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4
+!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6
+B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK
+B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0
+B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2
+B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4
+B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6
+!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1
+!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3
+!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5
+!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7
+!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5
+!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7
+!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1
+!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3
+!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5
+!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7
+B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1
+B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3
+B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5
+B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7
+!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0
+!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2
+!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4
+!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6
+!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6
+!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0
+!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2
+!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4
+!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6
+B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE
+B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0
+B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2
+B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4
+B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6
+B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1
+B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3
+B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5
+B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7
+B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5
+B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7
+B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1
+B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3
+B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5
+B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7
+B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1
+B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3
+B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5
+B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7
+B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0
+B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2
+B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4
+B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6
+B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6
+B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0
+B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2
+B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4
+B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6
+B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0
+B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2
+B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4
+B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6
+B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE
+B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1
+B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3
+B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5
+B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7
+B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5
+B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7
+B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1
+B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3
+B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5
+B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7
+B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1
+B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3
+B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5
+B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7
+B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0
+B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2
+B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4
+B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6
+B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6
+B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0
+B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2
+B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4
+B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6
+B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0
+B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2
+B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4
+B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6
+B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0
+B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0
+B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1
+B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2
+B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3
+B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4
+B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4
+B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5
+B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6
+B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7
+B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0
+B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1
+B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2
+B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3
+B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4
+B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5
+B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7
+B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3
+B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3
+!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7
+!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6
+B6[2] buffer sp12_h_l_13 sp4_h_r_19
+!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3
+!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5
+!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6
+!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6
+B14[2] buffer sp12_h_l_21 sp4_h_l_10
+B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4
+B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4
+B15[19] buffer sp12_h_l_3 sp4_h_l_3
+B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7
+B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7
+B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6
+B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6
+B14[19] buffer sp12_h_l_5 sp4_h_l_2
+!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1
+B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0
+B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0
+B13[19] buffer sp12_h_r_0 sp4_h_r_12
+B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1
+B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2
+B3[1] buffer sp12_h_r_10 sp4_h_r_17
+!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3
+!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3
+!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4
+!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4
+B4[2] buffer sp12_h_r_12 sp4_h_l_7
+!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5
+!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0
+B8[2] buffer sp12_h_r_16 sp4_h_r_20
+!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1
+!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1
+!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2
+!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2
+B10[2] buffer sp12_h_r_18 sp4_h_l_8
+B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2
+B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2
+B12[19] buffer sp12_h_r_2 sp4_h_r_13
+!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4
+B12[2] buffer sp12_h_r_20 sp4_h_r_22
+!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7
+!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7
+B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5
+B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5
+!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0
+!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0
+B0[2] buffer sp12_h_r_8 sp4_h_l_5
+B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0
+B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1
+B1[19] buffer sp12_v_b_1 sp4_v_t_1
+!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3
+B4[19] buffer sp12_v_b_11 sp4_v_b_17
+!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4
+!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6
+!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0
+!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0
+!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1
+B9[19] buffer sp12_v_b_17 sp4_v_b_20
+B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2
+B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2
+!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5
+B11[19] buffer sp12_v_b_21 sp4_v_b_22
+!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7
+B10[19] buffer sp12_v_b_23 sp4_v_t_10
+B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5
+B3[19] buffer sp12_v_b_5 sp4_v_b_14
+B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6
+B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6
+B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7
+B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7
+B2[19] buffer sp12_v_b_7 sp4_v_t_2
+!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1
+!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1
+B5[19] buffer sp12_v_b_9 sp4_v_b_16
+B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3
+B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3
+B0[19] buffer sp12_v_t_0 sp4_v_b_13
+!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5
+!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5
+B7[19] buffer sp12_v_t_10 sp4_v_t_7
+!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7
+!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7
+B6[19] buffer sp12_v_t_12 sp4_v_b_19
+!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3
+!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3
+B8[19] buffer sp12_v_t_16 sp4_v_t_8
+!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2
+!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4
+!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4
+!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6
+!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6
+B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4
+B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4
+!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0
+!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0
+!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2
+!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2
+B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7
+!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0
+!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0
+!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2
+B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5
+!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4
+!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4
+!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7
+B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7
+B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1
+B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0
+B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0
+B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7
+B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6
+B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1
+B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1
+B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0
+B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0
+B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6
+B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3
+B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0
+B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0
+B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5
+!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3
+B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4
+B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4
+B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5
+B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5
+B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1
+B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3
+B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3
+!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2
+B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4
+B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4
+B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6
+B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6
+B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1
+!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3
+!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3
+!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6
+B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2
+B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3
+B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3
+B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4
+B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5
+!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4
+B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2
+B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2
+B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4
+B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4
+B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5
+B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6
+B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6
+B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7
+B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7
+B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5
+!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6
+!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7
+B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0
+B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0
+B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1
+B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1
+!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0
+!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1
+!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2
+!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3
+!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7
+!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3
+!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2
+!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7
+!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0
+!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0
+!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1
+!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1
+!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2
+!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3
+!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3
+!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4
+!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4
+!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5
+!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5
+!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3
+!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6
+!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7
+!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7
+!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3
+!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0
+!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2
+!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1
+!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1
+!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2
+!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0
+!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3
+!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4
+!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5
+!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6
+!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7
+!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4
+!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0
+!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1
+!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2
+!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3
+!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4
+!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5
+!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6
+!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7
+!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5
+!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6
+!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7
+!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0
+!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1
+B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0
+B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1
+B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2
+B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3
+!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6
+!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0
+!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0
+B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1
+B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1
+!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3
+!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3
+B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2
+B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2
+!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4
+!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4
+!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6
+!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6
+!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1
+B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2
+B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4
+B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4
+!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5
+B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3
+B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3
+B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6
+!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1
+!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1
+!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5
+!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5
+B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6
+B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6
+B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4
+B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4
+!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0
+B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1
+B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1
+B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5
+B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5
+!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6
+!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6
+!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7
+!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7
+!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5
+!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5
+B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6
+B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6
+B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7
+B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0
+B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0
+!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1
+!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1
+B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4
+B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4
+!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7
+!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7
+B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0
+B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3
+B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7
+B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7
+B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7
+B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0
+B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0
+B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3
+B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3
+B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2
+B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2
+B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4
+B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4
+B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7
+B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7
+!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3
+!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3
+!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2
+!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2
+!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4
+!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2
+!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2
+B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5
+B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5
+!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0
+!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3
+!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4
+!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7
+!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0
+!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0
+B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1
+B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1
+!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2
+!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2
+!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3
+!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3
+!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4
+!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4
+B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5
+B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5
+!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6
+!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6
+!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7
+!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7
+!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0
+!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0
+!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2
+!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2
+!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4
+!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4
+!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6
+!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6
+B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21
+B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5
+B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14
+B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3
+B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30
+B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46
+B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15
+B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31
+B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47
+B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14
+B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30
+B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46
+B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3
+B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20
+B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12
+B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17
+B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12
+B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44
+B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13
+B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29
+B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45
+B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28
+B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1
+B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33
+B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18
+B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2
+B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9
+B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15
+B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10
+B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42
+B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11
+B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27
+B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43
+B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10
+B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26
+B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31
+B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0
+B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16
+B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7
+B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13
+B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29
+B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8
+B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25
+B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41
+B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9
+B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40
+B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8
+B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13
+B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13
+B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6
+B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21
+B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27
+B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22
+B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6
+B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23
+B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39
+B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7
+B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22
+B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38
+B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6
+B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12
+B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19
+B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3
+B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20
+B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36
+B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4
+B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21
+B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37
+B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5
+B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20
+B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4
+B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25
+B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10
+B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2
+B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17
+B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7
+B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2
+B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34
+B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19
+B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3
+B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35
+B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2
+B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23
+B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7
+B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8
+B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0
+B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16
+B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21
+B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5
+B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0
+B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1
+B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17
+B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33
+B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0
+B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16
+B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21
+!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1
+!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1
+!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22
+!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0
+!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0
+!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23
+B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23
+B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0
+B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23
+B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22
+B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1
+B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22
+!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23
+B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0
+B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23
+!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22
+B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1
+B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22
+B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22
+B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1
+B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1
+B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23
+B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0
+B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0
+B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1
+!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4
+!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9
+B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1
+B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7
+B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36
+!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43
+!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0
+B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3
+!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8
+B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0
+B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6
+!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37
+B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40
+!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11
+!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3
+B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6
+B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3
+B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9
+!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38
+B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45
+B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10
+!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2
+B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5
+!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2
+B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8
+!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39
+!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42
+B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1
+!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5
+B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8
+B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11
+!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5
+!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40
+!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47
+!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0
+B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4
+!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7
+B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10
+B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4
+B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41
+!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44
+!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10
+!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3
+B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7
+B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1
+B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7
+!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37
+B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42
+!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2
+!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6
+B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9
+B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0
+B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6
+!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43
+B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46
+B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0
+!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5
+!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9
+B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3
+B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9
+B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39
+!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44
+B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11
+B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4
+!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8
+B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2
+!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8
+!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36
+!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45
+!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11
+B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2
+B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7
+!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11
+B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5
+!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41
+!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46
+!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1
+B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10
+!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6
+B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10
+B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4
+!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38
+B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47
+!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37
+B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38
+!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45
+!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0
+B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5
+B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37
+B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43
+B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36
+!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41
+!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44
+B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1
+!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6
+B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36
+B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42
+!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36
+!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43
+B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47
+B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10
+!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3
+B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41
+B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47
+B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39
+B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42
+!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46
+!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11
+!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4
+B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40
+!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46
+!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39
+B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40
+B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47
+!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2
+!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7
+!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39
+B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45
+!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38
+B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43
+!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46
+!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3
+B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8
+B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38
+B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44
+!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37
+B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41
+!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42
+B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4
+!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9
+B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41
+B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47
+B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36
+!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40
+B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45
+!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10
+!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5
+!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40
+B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46
+!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39
+!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43
+B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44
+B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11
+!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6
+B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37
+B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43
+!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38
+B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42
+!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47
+!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0
+B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7
+B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36
+B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42
+B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41
+!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45
+B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46
+!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1
+!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8
+B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39
+!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45
+B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37
+!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40
+!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44
+B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2
+!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9
+B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38
+B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44
+B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37
+!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40
+B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0
+B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6
+B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37
+!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38
+B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45
+!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36
+!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43
+B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1
+B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7
+!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36
+B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41
+B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44
+!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38
+!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47
+B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10
+B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4
+B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36
+B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43
+!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47
+!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41
+B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46
+B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11
+B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5
+B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39
+!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42
+!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46
+B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39
+!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42
+B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2
+B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8
+!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39
+B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40
+!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47
+B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38
+!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45
+B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3
+B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9
+B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38
+!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43
+B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46
+!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41
+!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44
+B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10
+B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4
+B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37
+!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41
+B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42
+B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40
+!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47
+B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11
+B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5
+!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36
+!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40
+B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45
+B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43
+!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46
+B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0
+B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6
+B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39
+B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43
+!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44
+!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37
+!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42
+B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1
+B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7
+B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38
+!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42
+B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47
+!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36
+B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45
+B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2
+B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8
+!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41
+!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45
+B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46
+!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39
+B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44
+B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3
+B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9
+!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37
+B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40
+B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44
+B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36
+B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42
+!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1
+!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6
+!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1
+B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4
+B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9
+B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37
+B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43
+B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0
+!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5
+B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0
+!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3
+B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8
+B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38
+B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44
+B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3
+!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8
+B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11
+B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3
+!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6
+B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39
+B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45
+B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2
+!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7
+!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10
+!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2
+B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5
+B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40
+B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46
+!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10
+B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5
+!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1
+!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5
+B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8
+B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41
+B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47
+!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4
+!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9
+B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0
+!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4
+B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7
+B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36
+B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42
+!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0
+!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7
+B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10
+B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3
+!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7
+B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37
+B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43
+!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11
+B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6
+B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2
+B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6
+!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9
+B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38
+B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44
+!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2
+B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9
+!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0
+B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5
+B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9
+B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39
+B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45
+!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1
+B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8
+B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11
+!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4
+!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8
+B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40
+B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46
+B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11
+!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4
+!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11
+B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2
+!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7
+B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41
+B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47
+!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10
+!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3
+B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1
+!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10
+B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6
"""
diff --git a/icefuzz/Makefile b/icefuzz/Makefile
new file mode 100644
index 0000000..d388f3f
--- /dev/null
+++ b/icefuzz/Makefile
@@ -0,0 +1,97 @@
+
+export LC_ALL=C
+
+TESTS =
+TESTS += binop
+TESTS += pin2pin
+TESTS += mesh
+TESTS += fanout
+TESTS += logic
+TESTS += cluster
+TESTS += iopack
+TESTS += io
+TESTS += gbio
+TESTS += gbio2
+TESTS += prim
+TESTS += fflogic
+TESTS += ram40
+TESTS += pll
+
+EIGTHK = _8k
+
+database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(EIGTHK).txt bitdata_ramt$(EIGTHK).txt
+ifeq ($(EIGTHK),_8k)
+ cp cached_ramb.txt bitdata_ramb.txt
+ cp cached_ramt.txt bitdata_ramt.txt
+else
+ cp cached_ramb_8k.txt bitdata_ramb_8k.txt
+ cp cached_ramt_8k.txt bitdata_ramt_8k.txt
+endif
+ python database.py
+ python export.py
+ diff -U0 cached_io.txt bitdata_io.txt || cp -v bitdata_io.txt cached_io.txt
+ diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt
+ diff -U0 cached_ramb.txt bitdata_ramb.txt || cp -v bitdata_ramb.txt cached_ramb.txt
+ diff -U0 cached_ramt.txt bitdata_ramt.txt || cp -v bitdata_ramt.txt cached_ramt.txt
+ diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt
+ diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt
+
+data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt
+ gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
+ gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new
+ gawk '{ print "ramb$(EIGTHK)", $$0; }' cached_ramb$(EIGTHK).txt >> data_cached.new
+ gawk '{ print "ramt$(EIGTHK)", $$0; }' cached_ramt$(EIGTHK).txt >> data_cached.new
+ mv data_cached.new data_cached.txt
+
+bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
+ grep ^io $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
+
+bitdata_logic.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
+ grep ^logic $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
+
+bitdata_ramb$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
+ grep ^ramb$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
+
+bitdata_ramt$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS)))
+ grep ^ramt$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@
+
+datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS)))
+
+../icepack/icepack:
+ $(MAKE) -C ../icepack
+
+define data_template
+data_$(1).txt: make_$(1).py ../icepack/icepack
+ifeq ($(EIGTHK),_8k)
+ ICE8KPINS=1 python make_$(1).py
+ ICEDEV=hx8k-ct256 $$(MAKE) -C work_$(1)
+ python extract.py -8 work_$(1)/*.glb > $$@
+else
+ python make_$(1).py
+ $$(MAKE) -C work_$(1)
+ python extract.py work_$(1)/*.glb > $$@
+endif
+endef
+
+$(foreach test,$(TESTS),$(eval $(call data_template,$(test))))
+
+%.ok: %.bin
+ bash check.sh $<
+
+check: $(addsuffix .ok,$(basename $(wildcard work_binop/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_pin2pin/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_mesh/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_fanout/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_logic/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_cluster/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_iopack/*.bin)))
+check: $(addsuffix .ok,$(basename $(wildcard work_pll/*.bin)))
+
+clean:
+ rm -rf work_*
+ rm -rf data_*.txt
+ rm -rf bitdata_*.txt
+ rm -rf database_*.txt
+
+.PHONY: database datafiles check clean
+
diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt
new file mode 100644
index 0000000..257e8d0
--- /dev/null
+++ b/icefuzz/cached_io.txt
@@ -0,0 +1,2270 @@
+(0 0) Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_16
+(0 0) Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_16
+(0 1) Enable bit of Mux _out_links/OutMux0_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_0
+(0 1) Enable bit of Mux _out_links/OutMux0_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_0
+(0 10) Enable bit of Mux _out_links/OutMux7_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_6
+(0 10) Enable bit of Mux _out_links/OutMux7_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_6
+(0 11) Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_44
+(0 11) Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_44
+(0 12) Enable bit of Mux _out_links/OutMux2_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_22
+(0 12) Enable bit of Mux _out_links/OutMux2_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_22
+(0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_6
+(0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_6
+(0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_7
+(0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_7
+(0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_46
+(0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_4
+(0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_4
+(0 3) Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_40
+(0 3) Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
+(0 4) Enable bit of Mux _out_links/OutMux2_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_18
+(0 4) Enable bit of Mux _out_links/OutMux2_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_18
+(0 5) Enable bit of Mux _out_links/OutMux0_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_2
+(0 5) Enable bit of Mux _out_links/OutMux0_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_2
+(0 6) Enable bit of Mux _out_links/OutMux7_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_5
+(0 6) Enable bit of Mux _out_links/OutMux7_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_5
+(0 7) Enable bit of Mux _out_links/OutMux5_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_42
+(0 7) Enable bit of Mux _out_links/OutMux5_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_42
+(0 8) Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_20
+(0 8) Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_20
+(0 9) Enable bit of Mux _out_links/OutMux0_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_4
+(0 9) Enable bit of Mux _out_links/OutMux0_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_4
+(1 0) Enable bit of Mux _out_links/OutMux3_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_24
+(1 0) Enable bit of Mux _out_links/OutMux3_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_24
+(1 1) Enable bit of Mux _out_links/OutMux1_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_8
+(1 1) Enable bit of Mux _out_links/OutMux1_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_8
+(1 10) Enable bit of Mux _out_links/OutMux8_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_10
+(1 10) Enable bit of Mux _out_links/OutMux8_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_10
+(1 11) Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2
+(1 11) Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_2
+(1 12) Enable bit of Mux _out_links/OutMux3_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_30
+(1 12) Enable bit of Mux _out_links/OutMux3_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_30
+(1 13) Enable bit of Mux _out_links/OutMux1_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_14
+(1 13) Enable bit of Mux _out_links/OutMux1_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_14
+(1 14) Enable bit of Mux _out_links/OutMux8_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_11
+(1 14) Enable bit of Mux _out_links/OutMux8_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_11
+(1 15) Enable bit of Mux _out_links/OutMux6_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_3
+(1 15) Enable bit of Mux _out_links/OutMux6_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_3
+(1 2) Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_8
+(1 2) Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_8
+(1 3) Enable bit of Mux _out_links/OutMux6_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_0
+(1 3) Enable bit of Mux _out_links/OutMux6_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_0
+(1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_26
+(1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_26
+(1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_10
+(1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_9
+(1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_9
+(1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_1
+(1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_1
+(1 8) Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_28
+(1 8) Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_28
+(1 9) Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_12
+(1 9) Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_12
+(10 10) routing lc_trk_g0_4 <X> wire_io_cluster/io_1/OUT_ENB
+(10 10) routing lc_trk_g0_6 <X> wire_io_cluster/io_1/OUT_ENB
+(10 10) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/OUT_ENB
+(10 10) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/OUT_ENB
+(10 11) routing lc_trk_g0_2 <X> wire_io_cluster/io_1/OUT_ENB
+(10 11) routing lc_trk_g0_6 <X> wire_io_cluster/io_1/OUT_ENB
+(10 11) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/OUT_ENB
+(10 11) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/OUT_ENB
+(10 14) routing lc_trk_g0_4 <X> wire_io_cluster/io_1/D_OUT_1
+(10 14) routing lc_trk_g0_6 <X> wire_io_cluster/io_1/D_OUT_1
+(10 14) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/D_OUT_1
+(10 14) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/D_OUT_1
+(10 15) routing lc_trk_g0_2 <X> wire_io_cluster/io_1/D_OUT_1
+(10 15) routing lc_trk_g0_6 <X> wire_io_cluster/io_1/D_OUT_1
+(10 15) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/D_OUT_1
+(10 15) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/D_OUT_1
+(10 4) routing lc_trk_g0_5 <X> wire_io_cluster/io_0/OUT_ENB
+(10 4) routing lc_trk_g0_7 <X> wire_io_cluster/io_0/OUT_ENB
+(10 4) routing lc_trk_g1_4 <X> wire_io_cluster/io_0/OUT_ENB
+(10 4) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/OUT_ENB
+(10 5) routing lc_trk_g0_3 <X> wire_io_cluster/io_0/OUT_ENB
+(10 5) routing lc_trk_g0_7 <X> wire_io_cluster/io_0/OUT_ENB
+(10 5) routing lc_trk_g1_2 <X> wire_io_cluster/io_0/OUT_ENB
+(10 5) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/OUT_ENB
+(10 8) routing lc_trk_g0_5 <X> wire_io_cluster/io_0/D_OUT_1
+(10 8) routing lc_trk_g0_7 <X> wire_io_cluster/io_0/D_OUT_1
+(10 8) routing lc_trk_g1_4 <X> wire_io_cluster/io_0/D_OUT_1
+(10 8) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/D_OUT_1
+(10 9) routing lc_trk_g0_3 <X> wire_io_cluster/io_0/D_OUT_1
+(10 9) routing lc_trk_g0_7 <X> wire_io_cluster/io_0/D_OUT_1
+(10 9) routing lc_trk_g1_2 <X> wire_io_cluster/io_0/D_OUT_1
+(10 9) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/D_OUT_1
+(11 0) routing span4_horz_1 <X> span4_vert_t_12
+(11 0) routing span4_horz_r_0 <X> span4_horz_l_12
+(11 0) routing span4_vert_1 <X> span4_horz_l_12
+(11 0) routing span4_vert_b_0 <X> span4_vert_t_12
+(11 1) routing span4_horz_1 <X> span4_horz_25
+(11 1) routing span4_horz_l_12 <X> span4_vert_25
+(11 1) routing span4_vert_1 <X> span4_vert_25
+(11 1) routing span4_vert_t_12 <X> span4_horz_25
+(11 10) routing lc_trk_g1_1 <X> wire_io_cluster/io_1/OUT_ENB
+(11 10) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/OUT_ENB
+(11 10) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/OUT_ENB
+(11 10) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB
+(11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB
+(11 12) routing span4_horz_19 <X> span4_vert_t_15
+(11 12) routing span4_horz_r_3 <X> span4_horz_l_15
+(11 12) routing span4_vert_19 <X> span4_horz_l_15
+(11 12) routing span4_vert_b_3 <X> span4_vert_t_15
+(11 13) routing span4_horz_19 <X> span4_horz_43
+(11 13) routing span4_horz_l_15 <X> span4_vert_43
+(11 13) routing span4_vert_19 <X> span4_vert_43
+(11 13) routing span4_vert_t_15 <X> span4_horz_43
+(11 14) routing lc_trk_g1_1 <X> wire_io_cluster/io_1/D_OUT_1
+(11 14) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/D_OUT_1
+(11 14) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/D_OUT_1
+(11 14) routing lc_trk_g1_7 <X> wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1
+(11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1
+(11 2) routing span4_horz_7 <X> span4_vert_t_13
+(11 2) routing span4_horz_r_1 <X> span4_horz_l_13
+(11 2) routing span4_vert_7 <X> span4_horz_l_13
+(11 2) routing span4_vert_b_1 <X> span4_vert_t_13
+(11 3) routing span4_horz_7 <X> span4_horz_31
+(11 3) routing span4_horz_l_13 <X> span4_vert_31
+(11 3) routing span4_vert_7 <X> span4_vert_31
+(11 3) routing span4_vert_t_13 <X> span4_horz_31
+(11 4) routing lc_trk_g1_0 <X> wire_io_cluster/io_0/OUT_ENB
+(11 4) routing lc_trk_g1_2 <X> wire_io_cluster/io_0/OUT_ENB
+(11 4) routing lc_trk_g1_4 <X> wire_io_cluster/io_0/OUT_ENB
+(11 4) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB
+(11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB
+(11 6) routing span4_horz_13 <X> span4_vert_t_14
+(11 6) routing span4_horz_r_2 <X> span4_horz_l_14
+(11 6) routing span4_vert_13 <X> span4_horz_l_14
+(11 6) routing span4_vert_b_2 <X> span4_vert_t_14
+(11 7) routing span4_horz_13 <X> span4_horz_37
+(11 7) routing span4_horz_l_14 <X> span4_vert_37
+(11 7) routing span4_vert_13 <X> span4_vert_37
+(11 7) routing span4_vert_t_14 <X> span4_horz_37
+(11 8) routing lc_trk_g1_0 <X> wire_io_cluster/io_0/D_OUT_1
+(11 8) routing lc_trk_g1_2 <X> wire_io_cluster/io_0/D_OUT_1
+(11 8) routing lc_trk_g1_4 <X> wire_io_cluster/io_0/D_OUT_1
+(11 8) routing lc_trk_g1_6 <X> wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1
+(11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1
+(12 0) routing span4_horz_1 <X> span4_vert_t_12
+(12 0) routing span4_horz_25 <X> span4_vert_t_12
+(12 0) routing span4_vert_1 <X> span4_horz_l_12
+(12 0) routing span4_vert_25 <X> span4_horz_l_12
+(12 1) routing span4_horz_1 <X> span4_horz_25
+(12 1) routing span4_horz_r_0 <X> span4_vert_25
+(12 1) routing span4_vert_1 <X> span4_vert_25
+(12 1) routing span4_vert_b_0 <X> span4_horz_25
+(12 10) routing lc_trk_g1_0 <X> wire_io_cluster/io_1/D_OUT_0
+(12 10) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/D_OUT_0
+(12 10) routing lc_trk_g1_4 <X> wire_io_cluster/io_1/D_OUT_0
+(12 10) routing lc_trk_g1_6 <X> wire_io_cluster/io_1/D_OUT_0
+(12 11) routing lc_trk_g0_3 <X> wire_io_cluster/io_1/D_OUT_0
+(12 11) routing lc_trk_g0_7 <X> wire_io_cluster/io_1/D_OUT_0
+(12 11) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/D_OUT_0
+(12 11) routing lc_trk_g1_6 <X> wire_io_cluster/io_1/D_OUT_0
+(12 12) routing span4_horz_19 <X> span4_vert_t_15
+(12 12) routing span4_horz_43 <X> span4_vert_t_15
+(12 12) routing span4_vert_19 <X> span4_horz_l_15
+(12 12) routing span4_vert_43 <X> span4_horz_l_15
+(12 13) routing span4_horz_19 <X> span4_horz_43
+(12 13) routing span4_horz_r_3 <X> span4_vert_43
+(12 13) routing span4_vert_19 <X> span4_vert_43
+(12 13) routing span4_vert_b_3 <X> span4_horz_43
+(12 14) routing glb_netwk_2 <X> wire_io_cluster/io_1/outclk
+(12 14) routing glb_netwk_3 <X> wire_io_cluster/io_1/outclk
+(12 14) routing glb_netwk_6 <X> wire_io_cluster/io_1/outclk
+(12 14) routing glb_netwk_7 <X> wire_io_cluster/io_1/outclk
+(12 14) routing lc_trk_g1_1 <X> wire_io_cluster/io_1/outclk
+(12 14) routing lc_trk_g1_4 <X> wire_io_cluster/io_1/outclk
+(12 15) routing glb_netwk_1 <X> wire_io_cluster/io_1/outclk
+(12 15) routing glb_netwk_3 <X> wire_io_cluster/io_1/outclk
+(12 15) routing glb_netwk_5 <X> wire_io_cluster/io_1/outclk
+(12 15) routing glb_netwk_7 <X> wire_io_cluster/io_1/outclk
+(12 15) routing lc_trk_g0_4 <X> wire_io_cluster/io_1/outclk
+(12 15) routing lc_trk_g1_4 <X> wire_io_cluster/io_1/outclk
+(12 2) routing span4_horz_31 <X> span4_vert_t_13
+(12 2) routing span4_horz_7 <X> span4_vert_t_13
+(12 2) routing span4_vert_31 <X> span4_horz_l_13
+(12 2) routing span4_vert_7 <X> span4_horz_l_13
+(12 3) routing span4_horz_7 <X> span4_horz_31
+(12 3) routing span4_horz_r_1 <X> span4_vert_31
+(12 3) routing span4_vert_7 <X> span4_vert_31
+(12 3) routing span4_vert_b_1 <X> span4_horz_31
+(12 4) routing lc_trk_g1_1 <X> wire_io_cluster/io_0/D_OUT_0
+(12 4) routing lc_trk_g1_3 <X> wire_io_cluster/io_0/D_OUT_0
+(12 4) routing lc_trk_g1_5 <X> wire_io_cluster/io_0/D_OUT_0
+(12 4) routing lc_trk_g1_7 <X> wire_io_cluster/io_0/D_OUT_0
+(12 5) routing lc_trk_g0_2 <X> wire_io_cluster/io_0/D_OUT_0
+(12 5) routing lc_trk_g0_6 <X> wire_io_cluster/io_0/D_OUT_0
+(12 5) routing lc_trk_g1_3 <X> wire_io_cluster/io_0/D_OUT_0
+(12 5) routing lc_trk_g1_7 <X> wire_io_cluster/io_0/D_OUT_0
+(12 6) routing span4_horz_13 <X> span4_vert_t_14
+(12 6) routing span4_horz_37 <X> span4_vert_t_14
+(12 6) routing span4_vert_13 <X> span4_horz_l_14
+(12 6) routing span4_vert_37 <X> span4_horz_l_14
+(12 7) routing span4_horz_13 <X> span4_horz_37
+(12 7) routing span4_horz_r_2 <X> span4_vert_37
+(12 7) routing span4_vert_13 <X> span4_vert_37
+(12 7) routing span4_vert_b_2 <X> span4_horz_37
+(12 8) routing glb_netwk_2 <X> wire_io_cluster/io_1/inclk
+(12 8) routing glb_netwk_3 <X> wire_io_cluster/io_1/inclk
+(12 8) routing glb_netwk_6 <X> wire_io_cluster/io_1/inclk
+(12 8) routing glb_netwk_7 <X> wire_io_cluster/io_1/inclk
+(12 8) routing lc_trk_g1_0 <X> wire_io_cluster/io_1/inclk
+(12 8) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/inclk
+(12 9) routing glb_netwk_1 <X> wire_io_cluster/io_1/inclk
+(12 9) routing glb_netwk_3 <X> wire_io_cluster/io_1/inclk
+(12 9) routing glb_netwk_5 <X> wire_io_cluster/io_1/inclk
+(12 9) routing glb_netwk_7 <X> wire_io_cluster/io_1/inclk
+(12 9) routing lc_trk_g0_3 <X> wire_io_cluster/io_1/inclk
+(12 9) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/inclk
+(13 0) routing span4_horz_25 <X> span4_horz_1
+(13 0) routing span4_horz_r_0 <X> span4_vert_1
+(13 0) routing span4_vert_25 <X> span4_vert_1
+(13 0) routing span4_vert_b_0 <X> span4_horz_1
+(13 1) routing span4_horz_1 <X> span4_vert_b_0
+(13 1) routing span4_horz_25 <X> span4_vert_b_0
+(13 1) routing span4_vert_1 <X> span4_horz_r_0
+(13 1) routing span4_vert_25 <X> span4_horz_r_0
+(13 10) routing lc_trk_g0_5 <X> wire_io_cluster/io_1/D_OUT_0
+(13 10) routing lc_trk_g0_7 <X> wire_io_cluster/io_1/D_OUT_0
+(13 10) routing lc_trk_g1_4 <X> wire_io_cluster/io_1/D_OUT_0
+(13 10) routing lc_trk_g1_6 <X> wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0
+(13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0
+(13 12) routing span4_horz_43 <X> span4_horz_19
+(13 12) routing span4_horz_r_3 <X> span4_vert_19
+(13 12) routing span4_vert_43 <X> span4_vert_19
+(13 12) routing span4_vert_b_3 <X> span4_horz_19
+(13 13) routing span4_horz_19 <X> span4_vert_b_3
+(13 13) routing span4_horz_43 <X> span4_vert_b_3
+(13 13) routing span4_vert_19 <X> span4_horz_r_3
+(13 13) routing span4_vert_43 <X> span4_horz_r_3
+(13 14) routing lc_trk_g0_1 <X> wire_io_cluster/io_1/outclk
+(13 14) routing lc_trk_g0_4 <X> wire_io_cluster/io_1/outclk
+(13 14) routing lc_trk_g1_1 <X> wire_io_cluster/io_1/outclk
+(13 14) routing lc_trk_g1_4 <X> wire_io_cluster/io_1/outclk
+(13 15) Negative Clock bit
+(13 2) routing span4_horz_31 <X> span4_horz_7
+(13 2) routing span4_horz_r_1 <X> span4_vert_7
+(13 2) routing span4_vert_31 <X> span4_vert_7
+(13 2) routing span4_vert_b_1 <X> span4_horz_7
+(13 3) routing span4_horz_31 <X> span4_vert_b_1
+(13 3) routing span4_horz_7 <X> span4_vert_b_1
+(13 3) routing span4_vert_31 <X> span4_horz_r_1
+(13 3) routing span4_vert_7 <X> span4_horz_r_1
+(13 4) routing lc_trk_g0_4 <X> wire_io_cluster/io_0/D_OUT_0
+(13 4) routing lc_trk_g0_6 <X> wire_io_cluster/io_0/D_OUT_0
+(13 4) routing lc_trk_g1_5 <X> wire_io_cluster/io_0/D_OUT_0
+(13 4) routing lc_trk_g1_7 <X> wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0
+(13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0
+(13 6) routing span4_horz_37 <X> span4_horz_13
+(13 6) routing span4_horz_r_2 <X> span4_vert_13
+(13 6) routing span4_vert_37 <X> span4_vert_13
+(13 6) routing span4_vert_b_2 <X> span4_horz_13
+(13 7) routing span4_horz_13 <X> span4_vert_b_2
+(13 7) routing span4_horz_37 <X> span4_vert_b_2
+(13 7) routing span4_vert_13 <X> span4_horz_r_2
+(13 7) routing span4_vert_37 <X> span4_horz_r_2
+(13 8) routing lc_trk_g0_0 <X> wire_io_cluster/io_1/inclk
+(13 8) routing lc_trk_g0_3 <X> wire_io_cluster/io_1/inclk
+(13 8) routing lc_trk_g1_0 <X> wire_io_cluster/io_1/inclk
+(13 8) routing lc_trk_g1_3 <X> wire_io_cluster/io_1/inclk
+(13 9) Negative Clock bit
+(14 0) routing span4_horz_l_12 <X> span4_vert_1
+(14 0) routing span4_horz_r_0 <X> span4_vert_1
+(14 0) routing span4_vert_b_0 <X> span4_horz_1
+(14 0) routing span4_vert_t_12 <X> span4_horz_1
+(14 1) routing span4_horz_1 <X> span4_vert_b_0
+(14 1) routing span4_horz_l_12 <X> span4_horz_r_0
+(14 1) routing span4_vert_1 <X> span4_horz_r_0
+(14 1) routing span4_vert_t_12 <X> span4_vert_b_0
+(14 10) routing lc_trk_g0_5 <X> wire_io_cluster/io_1/cen
+(14 10) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/cen
+(14 11) routing lc_trk_g0_2 <X> wire_io_cluster/io_1/cen
+(14 11) routing lc_trk_g0_5 <X> wire_io_cluster/io_1/cen
+(14 11) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/cen
+(14 11) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/cen
+(14 12) routing span4_horz_l_15 <X> span4_vert_19
+(14 12) routing span4_horz_r_3 <X> span4_vert_19
+(14 12) routing span4_vert_b_3 <X> span4_horz_19
+(14 12) routing span4_vert_t_15 <X> span4_horz_19
+(14 13) routing span4_horz_19 <X> span4_vert_b_3
+(14 13) routing span4_horz_l_15 <X> span4_horz_r_3
+(14 13) routing span4_vert_19 <X> span4_horz_r_3
+(14 13) routing span4_vert_t_15 <X> span4_vert_b_3
+(14 14) routing glb_netwk_4 <X> wire_io_cluster/io_1/outclk
+(14 14) routing glb_netwk_5 <X> wire_io_cluster/io_1/outclk
+(14 14) routing glb_netwk_6 <X> wire_io_cluster/io_1/outclk
+(14 14) routing glb_netwk_7 <X> wire_io_cluster/io_1/outclk
+(14 2) routing span4_horz_l_13 <X> span4_vert_7
+(14 2) routing span4_horz_r_1 <X> span4_vert_7
+(14 2) routing span4_vert_b_1 <X> span4_horz_7
+(14 2) routing span4_vert_t_13 <X> span4_horz_7
+(14 3) routing span4_horz_7 <X> span4_vert_b_1
+(14 3) routing span4_horz_l_13 <X> span4_horz_r_1
+(14 3) routing span4_vert_7 <X> span4_horz_r_1
+(14 3) routing span4_vert_t_13 <X> span4_vert_b_1
+(14 4) routing lc_trk_g0_3 <X> fabout
+(14 4) routing lc_trk_g0_3 <X> wire_gbuf/in
+(14 4) routing lc_trk_g0_7 <X> fabout
+(14 4) routing lc_trk_g0_7 <X> wire_gbuf/in
+(14 4) routing lc_trk_g1_2 <X> fabout
+(14 4) routing lc_trk_g1_2 <X> wire_gbuf/in
+(14 4) routing lc_trk_g1_6 <X> fabout
+(14 4) routing lc_trk_g1_6 <X> wire_gbuf/in
+(14 5) routing lc_trk_g1_0 <X> fabout
+(14 5) routing lc_trk_g1_0 <X> wire_gbuf/in
+(14 5) routing lc_trk_g1_2 <X> fabout
+(14 5) routing lc_trk_g1_2 <X> wire_gbuf/in
+(14 5) routing lc_trk_g1_4 <X> fabout
+(14 5) routing lc_trk_g1_4 <X> wire_gbuf/in
+(14 5) routing lc_trk_g1_6 <X> fabout
+(14 5) routing lc_trk_g1_6 <X> wire_gbuf/in
+(14 6) routing span4_horz_l_14 <X> span4_vert_13
+(14 6) routing span4_horz_r_2 <X> span4_vert_13
+(14 6) routing span4_vert_b_2 <X> span4_horz_13
+(14 6) routing span4_vert_t_14 <X> span4_horz_13
+(14 7) routing span4_horz_13 <X> span4_vert_b_2
+(14 7) routing span4_horz_l_14 <X> span4_horz_r_2
+(14 7) routing span4_vert_13 <X> span4_horz_r_2
+(14 7) routing span4_vert_t_14 <X> span4_vert_b_2
+(14 8) routing glb_netwk_4 <X> wire_io_cluster/io_1/inclk
+(14 8) routing glb_netwk_5 <X> wire_io_cluster/io_1/inclk
+(14 8) routing glb_netwk_6 <X> wire_io_cluster/io_1/inclk
+(14 8) routing glb_netwk_7 <X> wire_io_cluster/io_1/inclk
+(15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g0_2 wire_io_cluster/io_1/cen
+(15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g0_5 wire_io_cluster/io_1/cen
+(15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g1_2 wire_io_cluster/io_1/cen
+(15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g1_5 wire_io_cluster/io_1/cen
+(15 11) routing lc_trk_g1_2 <X> wire_io_cluster/io_1/cen
+(15 11) routing lc_trk_g1_5 <X> wire_io_cluster/io_1/cen
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_0 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_1 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_2 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_3 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_4 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_5 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_6 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_7 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g0_1 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g0_4 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g1_1 wire_io_cluster/io_1/outclk
+(15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g1_4 wire_io_cluster/io_1/outclk
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_1 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_1 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_3 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_3 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_5 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_5 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_7 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_7 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_0 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_0 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_2 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_2 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_4 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_4 wire_gbuf/in
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_6 fabout
+(15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_6 wire_gbuf/in
+(15 5) routing lc_trk_g0_5 <X> fabout
+(15 5) routing lc_trk_g0_5 <X> wire_gbuf/in
+(15 5) routing lc_trk_g0_7 <X> fabout
+(15 5) routing lc_trk_g0_7 <X> wire_gbuf/in
+(15 5) routing lc_trk_g1_4 <X> fabout
+(15 5) routing lc_trk_g1_4 <X> wire_gbuf/in
+(15 5) routing lc_trk_g1_6 <X> fabout
+(15 5) routing lc_trk_g1_6 <X> wire_gbuf/in
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_0 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_1 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_2 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_3 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_4 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_5 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_6 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_7 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g0_0 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g0_3 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g1_0 wire_io_cluster/io_1/inclk
+(15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g1_3 wire_io_cluster/io_1/inclk
+(16 0) IOB_0 IO Functioning bit
+(16 0) IOB_0 PINTYPE_3
+(16 10) IOB_1 IO Functioning bit
+(16 10) IOB_1 PINTYPE_3
+(16 13) IOB_1 IO Functioning bit
+(16 13) IOB_1 PINTYPE_1
+(16 14) IOB_1 IO Functioning bit
+(16 14) IOB_1 PINTYPE_4
+(16 3) IOB_0 IO Functioning bit
+(16 3) IOB_0 PINTYPE_1
+(16 4) IOB_0 IO Functioning bit
+(16 4) IOB_0 PINTYPE_4
+(16 6) Enable bit of Mux _out_links/OutMuxc_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_18
+(16 6) Enable bit of Mux _out_links/OutMuxc_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_18
+(16 7) Enable bit of Mux _out_links/OutMuxa_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_2
+(16 7) Enable bit of Mux _out_links/OutMuxa_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_2
+(16 8) Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_20
+(16 8) Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_20
+(16 9) Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4
+(16 9) Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_4
+(17 0) IOB_0 IO Functioning bit
+(17 0) IOB_0 PINTYPE_2
+(17 1) Enable bit of Mux _out_links/OutMuxa_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_0
+(17 1) Enable bit of Mux _out_links/OutMuxa_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_0
+(17 10) IOB_1 IO Functioning bit
+(17 10) IOB_1 PINTYPE_2
+(17 11) Enable bit of Mux _out_links/OutMuxa_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_6
+(17 11) Enable bit of Mux _out_links/OutMuxa_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_6
+(17 12) Enable bit of Mux _out_links/OutMuxb_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_14
+(17 12) Enable bit of Mux _out_links/OutMuxb_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_14
+(17 13) IOB_1 IO Functioning bit
+(17 13) IOB_1 PINTYPE_0
+(17 14) IOB_1 IO Functioning bit
+(17 14) IOB_1 PINTYPE_5
+(17 15) Enable bit of Mux _out_links/OutMuxc_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_22
+(17 15) Enable bit of Mux _out_links/OutMuxc_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_22
+(17 2) Enable bit of Mux _out_links/OutMuxb_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_8
+(17 2) Enable bit of Mux _out_links/OutMuxb_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_8
+(17 3) IOB_0 IO Functioning bit
+(17 3) IOB_0 PINTYPE_0
+(17 4) IOB_0 IO Functioning bit
+(17 4) IOB_0 PINTYPE_5
+(17 5) Enable bit of Mux _out_links/OutMuxc_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_16
+(17 5) Enable bit of Mux _out_links/OutMuxc_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_16
+(17 7) Enable bit of Mux _out_links/OutMuxb_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_10
+(17 7) Enable bit of Mux _out_links/OutMuxb_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_10
+(17 9) Enable bit of Mux _out_links/OutMuxb_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_12
+(17 9) Enable bit of Mux _out_links/OutMuxb_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_12
+(2 0) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_1
+(2 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_1
+(2 1) Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_32
+(2 1) Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_32
+(2 11) Enable bit of Mux _out_links/OutMux9_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_14
+(2 11) Enable bit of Mux _out_links/OutMux9_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_14
+(2 13) Enable bit of Mux _out_links/OutMux4_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_38
+(2 13) Enable bit of Mux _out_links/OutMux4_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_38
+(2 15) Enable bit of Mux _out_links/OutMux9_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_15
+(2 15) Enable bit of Mux _out_links/OutMux9_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_15
+(2 2) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_4
+(2 3) Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_12
+(2 3) Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_12
+(2 4) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_7
+(2 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_7
+(2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_34
+(2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_34
+(2 6) IO control bit: BIODOWN_REN_0
+(2 6) IO control bit: BIOLEFT_REN_0
+(2 6) IO control bit: BIORIGHT_REN_0
+(2 6) IO control bit: BIOUP_REN_0
+(2 6) IO control bit: GIODOWN0_REN_0
+(2 6) IO control bit: GIODOWN1_REN_0
+(2 6) IO control bit: GIOLEFT0_REN_0
+(2 6) IO control bit: GIOLEFT1_REN_0
+(2 6) IO control bit: GIORIGHT0_REN_0
+(2 6) IO control bit: GIORIGHT1_REN_0
+(2 6) IO control bit: GIOUP0_REN_0
+(2 6) IO control bit: GIOUP1_REN_0
+(2 6) IO control bit: IODOWN_REN_0
+(2 6) IO control bit: IOLEFT_REN_0
+(2 6) IO control bit: IORIGHT_REN_0
+(2 6) IO control bit: IOUP_REN_0
+(2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_13
+(2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_13
+(2 8) IO control bit: BIOLEFT_LVDS_en
+(2 9) Enable bit of Mux _out_links/OutMux4_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_36
+(2 9) Enable bit of Mux _out_links/OutMux4_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_36
+(3 0) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_2
+(3 0) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_2
+(3 1) IO control bit: BIODOWN_REN_1
+(3 1) IO control bit: BIOLEFT_REN_1
+(3 1) IO control bit: BIORIGHT_REN_1
+(3 1) IO control bit: BIOUP_REN_1
+(3 1) IO control bit: GIODOWN0_REN_1
+(3 1) IO control bit: GIODOWN1_REN_1
+(3 1) IO control bit: GIOLEFT0_REN_1
+(3 1) IO control bit: GIOLEFT1_REN_1
+(3 1) IO control bit: GIORIGHT0_REN_1
+(3 1) IO control bit: GIORIGHT1_REN_1
+(3 1) IO control bit: GIOUP0_REN_1
+(3 1) IO control bit: GIOUP1_REN_1
+(3 1) IO control bit: IODOWN_REN_1
+(3 1) IO control bit: IOLEFT_REN_1
+(3 1) IO control bit: IORIGHT_REN_1
+(3 1) IO control bit: IOUP_REN_1
+(3 11) Icegate Enable bit: GIODOWN0_padin_latch_enable
+(3 11) Icegate Enable bit: GIODOWN1_padin_latch_enable
+(3 11) Icegate Enable bit: GIOLEFT0_padin_latch_enable
+(3 11) Icegate Enable bit: GIOLEFT1_padin_latch_enable
+(3 11) Icegate Enable bit: GIORIGHT0_padin_latch_enable
+(3 11) Icegate Enable bit: GIORIGHT1_padin_latch_enable
+(3 11) Icegate Enable bit: GIOUP0_padin_latch_enable
+(3 11) Icegate Enable bit: GIOUP1_padin_latch_enable
+(3 2) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_5
+(3 3) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_3
+(3 4) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_8
+(3 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_8
+(3 5) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_6
+(3 6) IO control bit: BIODOWN_IE_1
+(3 6) IO control bit: BIOLEFT_IE_1
+(3 6) IO control bit: BIORIGHT_IE_1
+(3 6) IO control bit: BIOUP_IE_1
+(3 6) IO control bit: GIODOWN0_IE_1
+(3 6) IO control bit: GIODOWN1_IE_1
+(3 6) IO control bit: GIOLEFT0_IE_1
+(3 6) IO control bit: GIOLEFT1_IE_1
+(3 6) IO control bit: GIORIGHT0_IE_1
+(3 6) IO control bit: GIORIGHT1_IE_1
+(3 6) IO control bit: GIOUP0_IE_1
+(3 6) IO control bit: GIOUP1_IE_1
+(3 6) IO control bit: IODOWN_IE_1
+(3 6) IO control bit: IOLEFT_IE_1
+(3 6) IO control bit: IORIGHT_IE_1
+(3 6) IO control bit: IOUP_IE_1
+(3 7) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_9
+(3 7) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_9
+(3 9) IO control bit: BIODOWN_IE_0
+(3 9) IO control bit: BIOLEFT_IE_0
+(3 9) IO control bit: BIORIGHT_IE_0
+(3 9) IO control bit: BIOUP_IE_0
+(3 9) IO control bit: GIODOWN0_IE_0
+(3 9) IO control bit: GIODOWN1_IE_0
+(3 9) IO control bit: GIOLEFT0_IE_0
+(3 9) IO control bit: GIOLEFT1_IE_0
+(3 9) IO control bit: GIORIGHT0_IE_0
+(3 9) IO control bit: GIORIGHT1_IE_0
+(3 9) IO control bit: GIOUP0_IE_0
+(3 9) IO control bit: GIOUP1_IE_0
+(3 9) IO control bit: IODOWN_IE_0
+(3 9) IO control bit: IOLEFT_IE_0
+(3 9) IO control bit: IORIGHT_IE_0
+(3 9) IO control bit: IOUP_IE_0
+(4 0) routing IO_B.logic_op_tnl_0 <X> lc_trk_g0_0
+(4 0) routing IO_B.logic_op_top_0 <X> lc_trk_g0_0
+(4 0) routing IO_L.logic_op_rgt_0 <X> lc_trk_g0_0
+(4 0) routing IO_L.logic_op_tnr_0 <X> lc_trk_g0_0
+(4 0) routing IO_R.logic_op_lft_0 <X> lc_trk_g0_0
+(4 0) routing IO_R.logic_op_tnl_0 <X> lc_trk_g0_0
+(4 0) routing IO_T.logic_op_bnl_0 <X> lc_trk_g0_0
+(4 0) routing IO_T.logic_op_bot_0 <X> lc_trk_g0_0
+(4 0) routing span12_horz_0 <X> lc_trk_g0_0
+(4 0) routing span12_vert_0 <X> lc_trk_g0_0
+(4 0) routing span4_horz_0 <X> lc_trk_g0_0
+(4 0) routing span4_horz_32 <X> lc_trk_g0_0
+(4 0) routing span4_horz_40 <X> lc_trk_g0_0
+(4 0) routing span4_horz_8 <X> lc_trk_g0_0
+(4 0) routing span4_horz_r_8 <X> lc_trk_g0_0
+(4 0) routing span4_vert_0 <X> lc_trk_g0_0
+(4 0) routing span4_vert_32 <X> lc_trk_g0_0
+(4 0) routing span4_vert_40 <X> lc_trk_g0_0
+(4 0) routing span4_vert_8 <X> lc_trk_g0_0
+(4 0) routing span4_vert_b_8 <X> lc_trk_g0_0
+(4 1) routing IO_B.logic_op_top_0 <X> lc_trk_g0_0
+(4 1) routing IO_L.logic_op_rgt_0 <X> lc_trk_g0_0
+(4 1) routing IO_R.logic_op_lft_0 <X> lc_trk_g0_0
+(4 1) routing IO_T.logic_op_bot_0 <X> lc_trk_g0_0
+(4 1) routing span12_horz_0 <X> lc_trk_g0_0
+(4 1) routing span12_horz_16 <X> lc_trk_g0_0
+(4 1) routing span12_vert_0 <X> lc_trk_g0_0
+(4 1) routing span12_vert_16 <X> lc_trk_g0_0
+(4 1) routing span4_horz_24 <X> lc_trk_g0_0
+(4 1) routing span4_horz_40 <X> lc_trk_g0_0
+(4 1) routing span4_horz_8 <X> lc_trk_g0_0
+(4 1) routing span4_horz_r_0 <X> lc_trk_g0_0
+(4 1) routing span4_vert_24 <X> lc_trk_g0_0
+(4 1) routing span4_vert_40 <X> lc_trk_g0_0
+(4 1) routing span4_vert_8 <X> lc_trk_g0_0
+(4 1) routing span4_vert_b_0 <X> lc_trk_g0_0
+(4 10) routing IO_B.logic_op_tnl_2 <X> lc_trk_g1_2
+(4 10) routing IO_B.logic_op_top_2 <X> lc_trk_g1_2
+(4 10) routing IO_L.logic_op_rgt_2 <X> lc_trk_g1_2
+(4 10) routing IO_L.logic_op_tnr_2 <X> lc_trk_g1_2
+(4 10) routing IO_R.logic_op_lft_2 <X> lc_trk_g1_2
+(4 10) routing IO_R.logic_op_tnl_2 <X> lc_trk_g1_2
+(4 10) routing IO_T.logic_op_bnl_2 <X> lc_trk_g1_2
+(4 10) routing IO_T.logic_op_bot_2 <X> lc_trk_g1_2
+(4 10) routing span12_horz_2 <X> lc_trk_g1_2
+(4 10) routing span12_vert_2 <X> lc_trk_g1_2
+(4 10) routing span4_horz_10 <X> lc_trk_g1_2
+(4 10) routing span4_horz_2 <X> lc_trk_g1_2
+(4 10) routing span4_horz_34 <X> lc_trk_g1_2
+(4 10) routing span4_horz_42 <X> lc_trk_g1_2
+(4 10) routing span4_horz_r_10 <X> lc_trk_g1_2
+(4 10) routing span4_vert_10 <X> lc_trk_g1_2
+(4 10) routing span4_vert_2 <X> lc_trk_g1_2
+(4 10) routing span4_vert_34 <X> lc_trk_g1_2
+(4 10) routing span4_vert_42 <X> lc_trk_g1_2
+(4 10) routing span4_vert_b_10 <X> lc_trk_g1_2
+(4 11) routing IO_B.logic_op_top_2 <X> lc_trk_g1_2
+(4 11) routing IO_L.logic_op_rgt_2 <X> lc_trk_g1_2
+(4 11) routing IO_R.logic_op_lft_2 <X> lc_trk_g1_2
+(4 11) routing IO_T.logic_op_bot_2 <X> lc_trk_g1_2
+(4 11) routing span12_horz_18 <X> lc_trk_g1_2
+(4 11) routing span12_horz_2 <X> lc_trk_g1_2
+(4 11) routing span12_vert_18 <X> lc_trk_g1_2
+(4 11) routing span12_vert_2 <X> lc_trk_g1_2
+(4 11) routing span4_horz_10 <X> lc_trk_g1_2
+(4 11) routing span4_horz_26 <X> lc_trk_g1_2
+(4 11) routing span4_horz_42 <X> lc_trk_g1_2
+(4 11) routing span4_horz_r_2 <X> lc_trk_g1_2
+(4 11) routing span4_vert_10 <X> lc_trk_g1_2
+(4 11) routing span4_vert_26 <X> lc_trk_g1_2
+(4 11) routing span4_vert_42 <X> lc_trk_g1_2
+(4 11) routing span4_vert_b_2 <X> lc_trk_g1_2
+(4 12) routing IO_B.logic_op_tnl_4 <X> lc_trk_g1_4
+(4 12) routing IO_B.logic_op_top_4 <X> lc_trk_g1_4
+(4 12) routing IO_L.logic_op_rgt_4 <X> lc_trk_g1_4
+(4 12) routing IO_L.logic_op_tnr_4 <X> lc_trk_g1_4
+(4 12) routing IO_R.logic_op_lft_4 <X> lc_trk_g1_4
+(4 12) routing IO_R.logic_op_tnl_4 <X> lc_trk_g1_4
+(4 12) routing IO_T.logic_op_bnl_4 <X> lc_trk_g1_4
+(4 12) routing IO_T.logic_op_bot_4 <X> lc_trk_g1_4
+(4 12) routing span12_horz_4 <X> lc_trk_g1_4
+(4 12) routing span12_vert_4 <X> lc_trk_g1_4
+(4 12) routing span4_horz_12 <X> lc_trk_g1_4
+(4 12) routing span4_horz_36 <X> lc_trk_g1_4
+(4 12) routing span4_horz_4 <X> lc_trk_g1_4
+(4 12) routing span4_horz_44 <X> lc_trk_g1_4
+(4 12) routing span4_horz_r_12 <X> lc_trk_g1_4
+(4 12) routing span4_vert_12 <X> lc_trk_g1_4
+(4 12) routing span4_vert_36 <X> lc_trk_g1_4
+(4 12) routing span4_vert_4 <X> lc_trk_g1_4
+(4 12) routing span4_vert_44 <X> lc_trk_g1_4
+(4 12) routing span4_vert_b_12 <X> lc_trk_g1_4
+(4 13) routing IO_B.logic_op_top_4 <X> lc_trk_g1_4
+(4 13) routing IO_L.logic_op_rgt_4 <X> lc_trk_g1_4
+(4 13) routing IO_R.logic_op_lft_4 <X> lc_trk_g1_4
+(4 13) routing IO_T.logic_op_bot_4 <X> lc_trk_g1_4
+(4 13) routing span12_horz_20 <X> lc_trk_g1_4
+(4 13) routing span12_horz_4 <X> lc_trk_g1_4
+(4 13) routing span12_vert_20 <X> lc_trk_g1_4
+(4 13) routing span12_vert_4 <X> lc_trk_g1_4
+(4 13) routing span4_horz_12 <X> lc_trk_g1_4
+(4 13) routing span4_horz_28 <X> lc_trk_g1_4
+(4 13) routing span4_horz_44 <X> lc_trk_g1_4
+(4 13) routing span4_horz_r_4 <X> lc_trk_g1_4
+(4 13) routing span4_vert_12 <X> lc_trk_g1_4
+(4 13) routing span4_vert_28 <X> lc_trk_g1_4
+(4 13) routing span4_vert_44 <X> lc_trk_g1_4
+(4 13) routing span4_vert_b_4 <X> lc_trk_g1_4
+(4 14) routing IO_B.logic_op_tnl_6 <X> lc_trk_g1_6
+(4 14) routing IO_B.logic_op_top_6 <X> lc_trk_g1_6
+(4 14) routing IO_L.logic_op_rgt_6 <X> lc_trk_g1_6
+(4 14) routing IO_L.logic_op_tnr_6 <X> lc_trk_g1_6
+(4 14) routing IO_R.logic_op_lft_6 <X> lc_trk_g1_6
+(4 14) routing IO_R.logic_op_tnl_6 <X> lc_trk_g1_6
+(4 14) routing IO_T.logic_op_bnl_6 <X> lc_trk_g1_6
+(4 14) routing IO_T.logic_op_bot_6 <X> lc_trk_g1_6
+(4 14) routing span12_horz_6 <X> lc_trk_g1_6
+(4 14) routing span12_vert_6 <X> lc_trk_g1_6
+(4 14) routing span4_horz_14 <X> lc_trk_g1_6
+(4 14) routing span4_horz_38 <X> lc_trk_g1_6
+(4 14) routing span4_horz_46 <X> lc_trk_g1_6
+(4 14) routing span4_horz_6 <X> lc_trk_g1_6
+(4 14) routing span4_horz_r_14 <X> lc_trk_g1_6
+(4 14) routing span4_vert_14 <X> lc_trk_g1_6
+(4 14) routing span4_vert_38 <X> lc_trk_g1_6
+(4 14) routing span4_vert_46 <X> lc_trk_g1_6
+(4 14) routing span4_vert_6 <X> lc_trk_g1_6
+(4 14) routing span4_vert_b_14 <X> lc_trk_g1_6
+(4 15) routing IO_B.logic_op_top_6 <X> lc_trk_g1_6
+(4 15) routing IO_L.logic_op_rgt_6 <X> lc_trk_g1_6
+(4 15) routing IO_R.logic_op_lft_6 <X> lc_trk_g1_6
+(4 15) routing IO_T.logic_op_bot_6 <X> lc_trk_g1_6
+(4 15) routing span12_horz_22 <X> lc_trk_g1_6
+(4 15) routing span12_horz_6 <X> lc_trk_g1_6
+(4 15) routing span12_vert_22 <X> lc_trk_g1_6
+(4 15) routing span12_vert_6 <X> lc_trk_g1_6
+(4 15) routing span4_horz_14 <X> lc_trk_g1_6
+(4 15) routing span4_horz_30 <X> lc_trk_g1_6
+(4 15) routing span4_horz_46 <X> lc_trk_g1_6
+(4 15) routing span4_horz_r_6 <X> lc_trk_g1_6
+(4 15) routing span4_vert_14 <X> lc_trk_g1_6
+(4 15) routing span4_vert_30 <X> lc_trk_g1_6
+(4 15) routing span4_vert_46 <X> lc_trk_g1_6
+(4 15) routing span4_vert_b_6 <X> lc_trk_g1_6
+(4 2) routing IO_B.logic_op_tnl_2 <X> lc_trk_g0_2
+(4 2) routing IO_B.logic_op_top_2 <X> lc_trk_g0_2
+(4 2) routing IO_L.logic_op_rgt_2 <X> lc_trk_g0_2
+(4 2) routing IO_L.logic_op_tnr_2 <X> lc_trk_g0_2
+(4 2) routing IO_R.logic_op_lft_2 <X> lc_trk_g0_2
+(4 2) routing IO_R.logic_op_tnl_2 <X> lc_trk_g0_2
+(4 2) routing IO_T.logic_op_bnl_2 <X> lc_trk_g0_2
+(4 2) routing IO_T.logic_op_bot_2 <X> lc_trk_g0_2
+(4 2) routing span12_horz_2 <X> lc_trk_g0_2
+(4 2) routing span12_vert_2 <X> lc_trk_g0_2
+(4 2) routing span4_horz_10 <X> lc_trk_g0_2
+(4 2) routing span4_horz_2 <X> lc_trk_g0_2
+(4 2) routing span4_horz_34 <X> lc_trk_g0_2
+(4 2) routing span4_horz_42 <X> lc_trk_g0_2
+(4 2) routing span4_horz_r_10 <X> lc_trk_g0_2
+(4 2) routing span4_vert_10 <X> lc_trk_g0_2
+(4 2) routing span4_vert_2 <X> lc_trk_g0_2
+(4 2) routing span4_vert_34 <X> lc_trk_g0_2
+(4 2) routing span4_vert_42 <X> lc_trk_g0_2
+(4 2) routing span4_vert_b_10 <X> lc_trk_g0_2
+(4 3) routing IO_B.logic_op_top_2 <X> lc_trk_g0_2
+(4 3) routing IO_L.logic_op_rgt_2 <X> lc_trk_g0_2
+(4 3) routing IO_R.logic_op_lft_2 <X> lc_trk_g0_2
+(4 3) routing IO_T.logic_op_bot_2 <X> lc_trk_g0_2
+(4 3) routing span12_horz_18 <X> lc_trk_g0_2
+(4 3) routing span12_horz_2 <X> lc_trk_g0_2
+(4 3) routing span12_vert_18 <X> lc_trk_g0_2
+(4 3) routing span12_vert_2 <X> lc_trk_g0_2
+(4 3) routing span4_horz_10 <X> lc_trk_g0_2
+(4 3) routing span4_horz_26 <X> lc_trk_g0_2
+(4 3) routing span4_horz_42 <X> lc_trk_g0_2
+(4 3) routing span4_horz_r_2 <X> lc_trk_g0_2
+(4 3) routing span4_vert_10 <X> lc_trk_g0_2
+(4 3) routing span4_vert_26 <X> lc_trk_g0_2
+(4 3) routing span4_vert_42 <X> lc_trk_g0_2
+(4 3) routing span4_vert_b_2 <X> lc_trk_g0_2
+(4 4) routing IO_B.logic_op_tnl_4 <X> lc_trk_g0_4
+(4 4) routing IO_B.logic_op_top_4 <X> lc_trk_g0_4
+(4 4) routing IO_L.logic_op_rgt_4 <X> lc_trk_g0_4
+(4 4) routing IO_L.logic_op_tnr_4 <X> lc_trk_g0_4
+(4 4) routing IO_R.logic_op_lft_4 <X> lc_trk_g0_4
+(4 4) routing IO_R.logic_op_tnl_4 <X> lc_trk_g0_4
+(4 4) routing IO_T.logic_op_bnl_4 <X> lc_trk_g0_4
+(4 4) routing IO_T.logic_op_bot_4 <X> lc_trk_g0_4
+(4 4) routing span12_horz_4 <X> lc_trk_g0_4
+(4 4) routing span12_vert_4 <X> lc_trk_g0_4
+(4 4) routing span4_horz_12 <X> lc_trk_g0_4
+(4 4) routing span4_horz_36 <X> lc_trk_g0_4
+(4 4) routing span4_horz_4 <X> lc_trk_g0_4
+(4 4) routing span4_horz_44 <X> lc_trk_g0_4
+(4 4) routing span4_horz_r_12 <X> lc_trk_g0_4
+(4 4) routing span4_vert_12 <X> lc_trk_g0_4
+(4 4) routing span4_vert_36 <X> lc_trk_g0_4
+(4 4) routing span4_vert_4 <X> lc_trk_g0_4
+(4 4) routing span4_vert_44 <X> lc_trk_g0_4
+(4 4) routing span4_vert_b_12 <X> lc_trk_g0_4
+(4 5) routing IO_B.logic_op_top_4 <X> lc_trk_g0_4
+(4 5) routing IO_L.logic_op_rgt_4 <X> lc_trk_g0_4
+(4 5) routing IO_R.logic_op_lft_4 <X> lc_trk_g0_4
+(4 5) routing IO_T.logic_op_bot_4 <X> lc_trk_g0_4
+(4 5) routing span12_horz_20 <X> lc_trk_g0_4
+(4 5) routing span12_horz_4 <X> lc_trk_g0_4
+(4 5) routing span12_vert_20 <X> lc_trk_g0_4
+(4 5) routing span12_vert_4 <X> lc_trk_g0_4
+(4 5) routing span4_horz_12 <X> lc_trk_g0_4
+(4 5) routing span4_horz_28 <X> lc_trk_g0_4
+(4 5) routing span4_horz_44 <X> lc_trk_g0_4
+(4 5) routing span4_horz_r_4 <X> lc_trk_g0_4
+(4 5) routing span4_vert_12 <X> lc_trk_g0_4
+(4 5) routing span4_vert_28 <X> lc_trk_g0_4
+(4 5) routing span4_vert_44 <X> lc_trk_g0_4
+(4 5) routing span4_vert_b_4 <X> lc_trk_g0_4
+(4 6) routing IO_B.logic_op_tnl_6 <X> lc_trk_g0_6
+(4 6) routing IO_B.logic_op_top_6 <X> lc_trk_g0_6
+(4 6) routing IO_L.logic_op_rgt_6 <X> lc_trk_g0_6
+(4 6) routing IO_L.logic_op_tnr_6 <X> lc_trk_g0_6
+(4 6) routing IO_R.logic_op_lft_6 <X> lc_trk_g0_6
+(4 6) routing IO_R.logic_op_tnl_6 <X> lc_trk_g0_6
+(4 6) routing IO_T.logic_op_bnl_6 <X> lc_trk_g0_6
+(4 6) routing IO_T.logic_op_bot_6 <X> lc_trk_g0_6
+(4 6) routing span12_horz_6 <X> lc_trk_g0_6
+(4 6) routing span12_vert_6 <X> lc_trk_g0_6
+(4 6) routing span4_horz_14 <X> lc_trk_g0_6
+(4 6) routing span4_horz_38 <X> lc_trk_g0_6
+(4 6) routing span4_horz_46 <X> lc_trk_g0_6
+(4 6) routing span4_horz_6 <X> lc_trk_g0_6
+(4 6) routing span4_horz_r_14 <X> lc_trk_g0_6
+(4 6) routing span4_vert_14 <X> lc_trk_g0_6
+(4 6) routing span4_vert_38 <X> lc_trk_g0_6
+(4 6) routing span4_vert_46 <X> lc_trk_g0_6
+(4 6) routing span4_vert_6 <X> lc_trk_g0_6
+(4 6) routing span4_vert_b_14 <X> lc_trk_g0_6
+(4 7) routing IO_B.logic_op_top_6 <X> lc_trk_g0_6
+(4 7) routing IO_L.logic_op_rgt_6 <X> lc_trk_g0_6
+(4 7) routing IO_R.logic_op_lft_6 <X> lc_trk_g0_6
+(4 7) routing IO_T.logic_op_bot_6 <X> lc_trk_g0_6
+(4 7) routing span12_horz_22 <X> lc_trk_g0_6
+(4 7) routing span12_horz_6 <X> lc_trk_g0_6
+(4 7) routing span12_vert_22 <X> lc_trk_g0_6
+(4 7) routing span12_vert_6 <X> lc_trk_g0_6
+(4 7) routing span4_horz_14 <X> lc_trk_g0_6
+(4 7) routing span4_horz_30 <X> lc_trk_g0_6
+(4 7) routing span4_horz_46 <X> lc_trk_g0_6
+(4 7) routing span4_horz_r_6 <X> lc_trk_g0_6
+(4 7) routing span4_vert_14 <X> lc_trk_g0_6
+(4 7) routing span4_vert_30 <X> lc_trk_g0_6
+(4 7) routing span4_vert_46 <X> lc_trk_g0_6
+(4 7) routing span4_vert_b_6 <X> lc_trk_g0_6
+(4 8) routing IO_B.logic_op_tnl_0 <X> lc_trk_g1_0
+(4 8) routing IO_B.logic_op_top_0 <X> lc_trk_g1_0
+(4 8) routing IO_L.logic_op_rgt_0 <X> lc_trk_g1_0
+(4 8) routing IO_L.logic_op_tnr_0 <X> lc_trk_g1_0
+(4 8) routing IO_R.logic_op_lft_0 <X> lc_trk_g1_0
+(4 8) routing IO_R.logic_op_tnl_0 <X> lc_trk_g1_0
+(4 8) routing IO_T.logic_op_bnl_0 <X> lc_trk_g1_0
+(4 8) routing IO_T.logic_op_bot_0 <X> lc_trk_g1_0
+(4 8) routing span12_horz_0 <X> lc_trk_g1_0
+(4 8) routing span12_vert_0 <X> lc_trk_g1_0
+(4 8) routing span4_horz_0 <X> lc_trk_g1_0
+(4 8) routing span4_horz_32 <X> lc_trk_g1_0
+(4 8) routing span4_horz_40 <X> lc_trk_g1_0
+(4 8) routing span4_horz_8 <X> lc_trk_g1_0
+(4 8) routing span4_horz_r_8 <X> lc_trk_g1_0
+(4 8) routing span4_vert_0 <X> lc_trk_g1_0
+(4 8) routing span4_vert_32 <X> lc_trk_g1_0
+(4 8) routing span4_vert_40 <X> lc_trk_g1_0
+(4 8) routing span4_vert_8 <X> lc_trk_g1_0
+(4 8) routing span4_vert_b_8 <X> lc_trk_g1_0
+(4 9) routing IO_B.logic_op_top_0 <X> lc_trk_g1_0
+(4 9) routing IO_L.logic_op_rgt_0 <X> lc_trk_g1_0
+(4 9) routing IO_R.logic_op_lft_0 <X> lc_trk_g1_0
+(4 9) routing IO_T.logic_op_bot_0 <X> lc_trk_g1_0
+(4 9) routing span12_horz_0 <X> lc_trk_g1_0
+(4 9) routing span12_horz_16 <X> lc_trk_g1_0
+(4 9) routing span12_vert_0 <X> lc_trk_g1_0
+(4 9) routing span12_vert_16 <X> lc_trk_g1_0
+(4 9) routing span4_horz_24 <X> lc_trk_g1_0
+(4 9) routing span4_horz_40 <X> lc_trk_g1_0
+(4 9) routing span4_horz_8 <X> lc_trk_g1_0
+(4 9) routing span4_horz_r_0 <X> lc_trk_g1_0
+(4 9) routing span4_vert_24 <X> lc_trk_g1_0
+(4 9) routing span4_vert_40 <X> lc_trk_g1_0
+(4 9) routing span4_vert_8 <X> lc_trk_g1_0
+(4 9) routing span4_vert_b_0 <X> lc_trk_g1_0
+(5 0) routing IO_B.logic_op_tnr_1 <X> lc_trk_g0_1
+(5 0) routing IO_L.logic_op_bnr_1 <X> lc_trk_g0_1
+(5 0) routing IO_R.logic_op_bnl_1 <X> lc_trk_g0_1
+(5 0) routing IO_T.logic_op_bnr_1 <X> lc_trk_g0_1
+(5 0) routing span12_horz_1 <X> lc_trk_g0_1
+(5 0) routing span12_vert_1 <X> lc_trk_g0_1
+(5 0) routing span4_horz_17 <X> lc_trk_g0_1
+(5 0) routing span4_horz_25 <X> lc_trk_g0_1
+(5 0) routing span4_horz_33 <X> lc_trk_g0_1
+(5 0) routing span4_horz_41 <X> lc_trk_g0_1
+(5 0) routing span4_horz_r_1 <X> lc_trk_g0_1
+(5 0) routing span4_horz_r_9 <X> lc_trk_g0_1
+(5 0) routing span4_vert_17 <X> lc_trk_g0_1
+(5 0) routing span4_vert_25 <X> lc_trk_g0_1
+(5 0) routing span4_vert_33 <X> lc_trk_g0_1
+(5 0) routing span4_vert_41 <X> lc_trk_g0_1
+(5 0) routing span4_vert_b_1 <X> lc_trk_g0_1
+(5 0) routing span4_vert_b_9 <X> lc_trk_g0_1
+(5 1) routing IO_B.logic_op_tnr_0 <X> lc_trk_g0_0
+(5 1) routing IO_L.logic_op_bnr_0 <X> lc_trk_g0_0
+(5 1) routing IO_R.logic_op_bnl_0 <X> lc_trk_g0_0
+(5 1) routing IO_T.logic_op_bnr_0 <X> lc_trk_g0_0
+(5 1) routing span12_horz_0 <X> lc_trk_g0_0
+(5 1) routing span12_vert_0 <X> lc_trk_g0_0
+(5 1) routing span4_horz_16 <X> lc_trk_g0_0
+(5 1) routing span4_horz_24 <X> lc_trk_g0_0
+(5 1) routing span4_horz_32 <X> lc_trk_g0_0
+(5 1) routing span4_horz_40 <X> lc_trk_g0_0
+(5 1) routing span4_horz_r_0 <X> lc_trk_g0_0
+(5 1) routing span4_horz_r_8 <X> lc_trk_g0_0
+(5 1) routing span4_vert_16 <X> lc_trk_g0_0
+(5 1) routing span4_vert_24 <X> lc_trk_g0_0
+(5 1) routing span4_vert_32 <X> lc_trk_g0_0
+(5 1) routing span4_vert_40 <X> lc_trk_g0_0
+(5 1) routing span4_vert_b_0 <X> lc_trk_g0_0
+(5 1) routing span4_vert_b_8 <X> lc_trk_g0_0
+(5 10) routing IO_B.logic_op_tnr_3 <X> lc_trk_g1_3
+(5 10) routing IO_L.logic_op_bnr_3 <X> lc_trk_g1_3
+(5 10) routing IO_R.logic_op_bnl_3 <X> lc_trk_g1_3
+(5 10) routing IO_T.logic_op_bnr_3 <X> lc_trk_g1_3
+(5 10) routing span12_horz_3 <X> lc_trk_g1_3
+(5 10) routing span12_vert_3 <X> lc_trk_g1_3
+(5 10) routing span4_horz_19 <X> lc_trk_g1_3
+(5 10) routing span4_horz_27 <X> lc_trk_g1_3
+(5 10) routing span4_horz_35 <X> lc_trk_g1_3
+(5 10) routing span4_horz_43 <X> lc_trk_g1_3
+(5 10) routing span4_horz_r_11 <X> lc_trk_g1_3
+(5 10) routing span4_horz_r_3 <X> lc_trk_g1_3
+(5 10) routing span4_vert_19 <X> lc_trk_g1_3
+(5 10) routing span4_vert_27 <X> lc_trk_g1_3
+(5 10) routing span4_vert_35 <X> lc_trk_g1_3
+(5 10) routing span4_vert_43 <X> lc_trk_g1_3
+(5 10) routing span4_vert_b_11 <X> lc_trk_g1_3
+(5 10) routing span4_vert_b_3 <X> lc_trk_g1_3
+(5 11) routing IO_B.logic_op_tnr_2 <X> lc_trk_g1_2
+(5 11) routing IO_L.logic_op_bnr_2 <X> lc_trk_g1_2
+(5 11) routing IO_R.logic_op_bnl_2 <X> lc_trk_g1_2
+(5 11) routing IO_T.logic_op_bnr_2 <X> lc_trk_g1_2
+(5 11) routing span12_horz_2 <X> lc_trk_g1_2
+(5 11) routing span12_vert_2 <X> lc_trk_g1_2
+(5 11) routing span4_horz_18 <X> lc_trk_g1_2
+(5 11) routing span4_horz_26 <X> lc_trk_g1_2
+(5 11) routing span4_horz_34 <X> lc_trk_g1_2
+(5 11) routing span4_horz_42 <X> lc_trk_g1_2
+(5 11) routing span4_horz_r_10 <X> lc_trk_g1_2
+(5 11) routing span4_horz_r_2 <X> lc_trk_g1_2
+(5 11) routing span4_vert_18 <X> lc_trk_g1_2
+(5 11) routing span4_vert_26 <X> lc_trk_g1_2
+(5 11) routing span4_vert_34 <X> lc_trk_g1_2
+(5 11) routing span4_vert_42 <X> lc_trk_g1_2
+(5 11) routing span4_vert_b_10 <X> lc_trk_g1_2
+(5 11) routing span4_vert_b_2 <X> lc_trk_g1_2
+(5 12) routing IO_B.logic_op_tnr_5 <X> lc_trk_g1_5
+(5 12) routing IO_L.logic_op_bnr_5 <X> lc_trk_g1_5
+(5 12) routing IO_R.logic_op_bnl_5 <X> lc_trk_g1_5
+(5 12) routing IO_T.logic_op_bnr_5 <X> lc_trk_g1_5
+(5 12) routing span12_horz_5 <X> lc_trk_g1_5
+(5 12) routing span12_vert_5 <X> lc_trk_g1_5
+(5 12) routing span4_horz_21 <X> lc_trk_g1_5
+(5 12) routing span4_horz_29 <X> lc_trk_g1_5
+(5 12) routing span4_horz_37 <X> lc_trk_g1_5
+(5 12) routing span4_horz_45 <X> lc_trk_g1_5
+(5 12) routing span4_horz_r_13 <X> lc_trk_g1_5
+(5 12) routing span4_horz_r_5 <X> lc_trk_g1_5
+(5 12) routing span4_vert_21 <X> lc_trk_g1_5
+(5 12) routing span4_vert_29 <X> lc_trk_g1_5
+(5 12) routing span4_vert_37 <X> lc_trk_g1_5
+(5 12) routing span4_vert_45 <X> lc_trk_g1_5
+(5 12) routing span4_vert_b_13 <X> lc_trk_g1_5
+(5 12) routing span4_vert_b_5 <X> lc_trk_g1_5
+(5 13) routing IO_B.logic_op_tnr_4 <X> lc_trk_g1_4
+(5 13) routing IO_L.logic_op_bnr_4 <X> lc_trk_g1_4
+(5 13) routing IO_R.logic_op_bnl_4 <X> lc_trk_g1_4
+(5 13) routing IO_T.logic_op_bnr_4 <X> lc_trk_g1_4
+(5 13) routing span12_horz_4 <X> lc_trk_g1_4
+(5 13) routing span12_vert_4 <X> lc_trk_g1_4
+(5 13) routing span4_horz_20 <X> lc_trk_g1_4
+(5 13) routing span4_horz_28 <X> lc_trk_g1_4
+(5 13) routing span4_horz_36 <X> lc_trk_g1_4
+(5 13) routing span4_horz_44 <X> lc_trk_g1_4
+(5 13) routing span4_horz_r_12 <X> lc_trk_g1_4
+(5 13) routing span4_horz_r_4 <X> lc_trk_g1_4
+(5 13) routing span4_vert_20 <X> lc_trk_g1_4
+(5 13) routing span4_vert_28 <X> lc_trk_g1_4
+(5 13) routing span4_vert_36 <X> lc_trk_g1_4
+(5 13) routing span4_vert_44 <X> lc_trk_g1_4
+(5 13) routing span4_vert_b_12 <X> lc_trk_g1_4
+(5 13) routing span4_vert_b_4 <X> lc_trk_g1_4
+(5 14) routing IO_B.logic_op_tnr_7 <X> lc_trk_g1_7
+(5 14) routing IO_L.logic_op_bnr_7 <X> lc_trk_g1_7
+(5 14) routing IO_R.logic_op_bnl_7 <X> lc_trk_g1_7
+(5 14) routing IO_T.logic_op_bnr_7 <X> lc_trk_g1_7
+(5 14) routing span12_horz_7 <X> lc_trk_g1_7
+(5 14) routing span12_vert_7 <X> lc_trk_g1_7
+(5 14) routing span4_horz_23 <X> lc_trk_g1_7
+(5 14) routing span4_horz_31 <X> lc_trk_g1_7
+(5 14) routing span4_horz_39 <X> lc_trk_g1_7
+(5 14) routing span4_horz_47 <X> lc_trk_g1_7
+(5 14) routing span4_horz_r_15 <X> lc_trk_g1_7
+(5 14) routing span4_horz_r_7 <X> lc_trk_g1_7
+(5 14) routing span4_vert_23 <X> lc_trk_g1_7
+(5 14) routing span4_vert_31 <X> lc_trk_g1_7
+(5 14) routing span4_vert_39 <X> lc_trk_g1_7
+(5 14) routing span4_vert_47 <X> lc_trk_g1_7
+(5 14) routing span4_vert_b_15 <X> lc_trk_g1_7
+(5 14) routing span4_vert_b_7 <X> lc_trk_g1_7
+(5 15) routing IO_B.logic_op_tnr_6 <X> lc_trk_g1_6
+(5 15) routing IO_L.logic_op_bnr_6 <X> lc_trk_g1_6
+(5 15) routing IO_R.logic_op_bnl_6 <X> lc_trk_g1_6
+(5 15) routing IO_T.logic_op_bnr_6 <X> lc_trk_g1_6
+(5 15) routing span12_horz_6 <X> lc_trk_g1_6
+(5 15) routing span12_vert_6 <X> lc_trk_g1_6
+(5 15) routing span4_horz_22 <X> lc_trk_g1_6
+(5 15) routing span4_horz_30 <X> lc_trk_g1_6
+(5 15) routing span4_horz_38 <X> lc_trk_g1_6
+(5 15) routing span4_horz_46 <X> lc_trk_g1_6
+(5 15) routing span4_horz_r_14 <X> lc_trk_g1_6
+(5 15) routing span4_horz_r_6 <X> lc_trk_g1_6
+(5 15) routing span4_vert_22 <X> lc_trk_g1_6
+(5 15) routing span4_vert_30 <X> lc_trk_g1_6
+(5 15) routing span4_vert_38 <X> lc_trk_g1_6
+(5 15) routing span4_vert_46 <X> lc_trk_g1_6
+(5 15) routing span4_vert_b_14 <X> lc_trk_g1_6
+(5 15) routing span4_vert_b_6 <X> lc_trk_g1_6
+(5 2) routing IO_B.logic_op_tnr_3 <X> lc_trk_g0_3
+(5 2) routing IO_L.logic_op_bnr_3 <X> lc_trk_g0_3
+(5 2) routing IO_R.logic_op_bnl_3 <X> lc_trk_g0_3
+(5 2) routing IO_T.logic_op_bnr_3 <X> lc_trk_g0_3
+(5 2) routing span12_horz_3 <X> lc_trk_g0_3
+(5 2) routing span12_vert_3 <X> lc_trk_g0_3
+(5 2) routing span4_horz_19 <X> lc_trk_g0_3
+(5 2) routing span4_horz_27 <X> lc_trk_g0_3
+(5 2) routing span4_horz_35 <X> lc_trk_g0_3
+(5 2) routing span4_horz_43 <X> lc_trk_g0_3
+(5 2) routing span4_horz_r_11 <X> lc_trk_g0_3
+(5 2) routing span4_horz_r_3 <X> lc_trk_g0_3
+(5 2) routing span4_vert_19 <X> lc_trk_g0_3
+(5 2) routing span4_vert_27 <X> lc_trk_g0_3
+(5 2) routing span4_vert_35 <X> lc_trk_g0_3
+(5 2) routing span4_vert_43 <X> lc_trk_g0_3
+(5 2) routing span4_vert_b_11 <X> lc_trk_g0_3
+(5 2) routing span4_vert_b_3 <X> lc_trk_g0_3
+(5 3) routing IO_B.logic_op_tnr_2 <X> lc_trk_g0_2
+(5 3) routing IO_L.logic_op_bnr_2 <X> lc_trk_g0_2
+(5 3) routing IO_R.logic_op_bnl_2 <X> lc_trk_g0_2
+(5 3) routing IO_T.logic_op_bnr_2 <X> lc_trk_g0_2
+(5 3) routing span12_horz_2 <X> lc_trk_g0_2
+(5 3) routing span12_vert_2 <X> lc_trk_g0_2
+(5 3) routing span4_horz_18 <X> lc_trk_g0_2
+(5 3) routing span4_horz_26 <X> lc_trk_g0_2
+(5 3) routing span4_horz_34 <X> lc_trk_g0_2
+(5 3) routing span4_horz_42 <X> lc_trk_g0_2
+(5 3) routing span4_horz_r_10 <X> lc_trk_g0_2
+(5 3) routing span4_horz_r_2 <X> lc_trk_g0_2
+(5 3) routing span4_vert_18 <X> lc_trk_g0_2
+(5 3) routing span4_vert_26 <X> lc_trk_g0_2
+(5 3) routing span4_vert_34 <X> lc_trk_g0_2
+(5 3) routing span4_vert_42 <X> lc_trk_g0_2
+(5 3) routing span4_vert_b_10 <X> lc_trk_g0_2
+(5 3) routing span4_vert_b_2 <X> lc_trk_g0_2
+(5 4) routing IO_B.logic_op_tnr_5 <X> lc_trk_g0_5
+(5 4) routing IO_L.logic_op_bnr_5 <X> lc_trk_g0_5
+(5 4) routing IO_R.logic_op_bnl_5 <X> lc_trk_g0_5
+(5 4) routing IO_T.logic_op_bnr_5 <X> lc_trk_g0_5
+(5 4) routing span12_horz_5 <X> lc_trk_g0_5
+(5 4) routing span12_vert_5 <X> lc_trk_g0_5
+(5 4) routing span4_horz_21 <X> lc_trk_g0_5
+(5 4) routing span4_horz_29 <X> lc_trk_g0_5
+(5 4) routing span4_horz_37 <X> lc_trk_g0_5
+(5 4) routing span4_horz_45 <X> lc_trk_g0_5
+(5 4) routing span4_horz_r_13 <X> lc_trk_g0_5
+(5 4) routing span4_horz_r_5 <X> lc_trk_g0_5
+(5 4) routing span4_vert_21 <X> lc_trk_g0_5
+(5 4) routing span4_vert_29 <X> lc_trk_g0_5
+(5 4) routing span4_vert_37 <X> lc_trk_g0_5
+(5 4) routing span4_vert_45 <X> lc_trk_g0_5
+(5 4) routing span4_vert_b_13 <X> lc_trk_g0_5
+(5 4) routing span4_vert_b_5 <X> lc_trk_g0_5
+(5 5) routing IO_B.logic_op_tnr_4 <X> lc_trk_g0_4
+(5 5) routing IO_L.logic_op_bnr_4 <X> lc_trk_g0_4
+(5 5) routing IO_R.logic_op_bnl_4 <X> lc_trk_g0_4
+(5 5) routing IO_T.logic_op_bnr_4 <X> lc_trk_g0_4
+(5 5) routing span12_horz_4 <X> lc_trk_g0_4
+(5 5) routing span12_vert_4 <X> lc_trk_g0_4
+(5 5) routing span4_horz_20 <X> lc_trk_g0_4
+(5 5) routing span4_horz_28 <X> lc_trk_g0_4
+(5 5) routing span4_horz_36 <X> lc_trk_g0_4
+(5 5) routing span4_horz_44 <X> lc_trk_g0_4
+(5 5) routing span4_horz_r_12 <X> lc_trk_g0_4
+(5 5) routing span4_horz_r_4 <X> lc_trk_g0_4
+(5 5) routing span4_vert_20 <X> lc_trk_g0_4
+(5 5) routing span4_vert_28 <X> lc_trk_g0_4
+(5 5) routing span4_vert_36 <X> lc_trk_g0_4
+(5 5) routing span4_vert_44 <X> lc_trk_g0_4
+(5 5) routing span4_vert_b_12 <X> lc_trk_g0_4
+(5 5) routing span4_vert_b_4 <X> lc_trk_g0_4
+(5 6) routing IO_B.logic_op_tnr_7 <X> lc_trk_g0_7
+(5 6) routing IO_L.logic_op_bnr_7 <X> lc_trk_g0_7
+(5 6) routing IO_R.logic_op_bnl_7 <X> lc_trk_g0_7
+(5 6) routing IO_T.logic_op_bnr_7 <X> lc_trk_g0_7
+(5 6) routing span12_horz_7 <X> lc_trk_g0_7
+(5 6) routing span12_vert_7 <X> lc_trk_g0_7
+(5 6) routing span4_horz_23 <X> lc_trk_g0_7
+(5 6) routing span4_horz_31 <X> lc_trk_g0_7
+(5 6) routing span4_horz_39 <X> lc_trk_g0_7
+(5 6) routing span4_horz_47 <X> lc_trk_g0_7
+(5 6) routing span4_horz_r_15 <X> lc_trk_g0_7
+(5 6) routing span4_horz_r_7 <X> lc_trk_g0_7
+(5 6) routing span4_vert_23 <X> lc_trk_g0_7
+(5 6) routing span4_vert_31 <X> lc_trk_g0_7
+(5 6) routing span4_vert_39 <X> lc_trk_g0_7
+(5 6) routing span4_vert_47 <X> lc_trk_g0_7
+(5 6) routing span4_vert_b_15 <X> lc_trk_g0_7
+(5 6) routing span4_vert_b_7 <X> lc_trk_g0_7
+(5 7) routing IO_B.logic_op_tnr_6 <X> lc_trk_g0_6
+(5 7) routing IO_L.logic_op_bnr_6 <X> lc_trk_g0_6
+(5 7) routing IO_R.logic_op_bnl_6 <X> lc_trk_g0_6
+(5 7) routing IO_T.logic_op_bnr_6 <X> lc_trk_g0_6
+(5 7) routing span12_horz_6 <X> lc_trk_g0_6
+(5 7) routing span12_vert_6 <X> lc_trk_g0_6
+(5 7) routing span4_horz_22 <X> lc_trk_g0_6
+(5 7) routing span4_horz_30 <X> lc_trk_g0_6
+(5 7) routing span4_horz_38 <X> lc_trk_g0_6
+(5 7) routing span4_horz_46 <X> lc_trk_g0_6
+(5 7) routing span4_horz_r_14 <X> lc_trk_g0_6
+(5 7) routing span4_horz_r_6 <X> lc_trk_g0_6
+(5 7) routing span4_vert_22 <X> lc_trk_g0_6
+(5 7) routing span4_vert_30 <X> lc_trk_g0_6
+(5 7) routing span4_vert_38 <X> lc_trk_g0_6
+(5 7) routing span4_vert_46 <X> lc_trk_g0_6
+(5 7) routing span4_vert_b_14 <X> lc_trk_g0_6
+(5 7) routing span4_vert_b_6 <X> lc_trk_g0_6
+(5 8) routing IO_B.logic_op_tnr_1 <X> lc_trk_g1_1
+(5 8) routing IO_L.logic_op_bnr_1 <X> lc_trk_g1_1
+(5 8) routing IO_R.logic_op_bnl_1 <X> lc_trk_g1_1
+(5 8) routing IO_T.logic_op_bnr_1 <X> lc_trk_g1_1
+(5 8) routing span12_horz_1 <X> lc_trk_g1_1
+(5 8) routing span12_vert_1 <X> lc_trk_g1_1
+(5 8) routing span4_horz_17 <X> lc_trk_g1_1
+(5 8) routing span4_horz_25 <X> lc_trk_g1_1
+(5 8) routing span4_horz_33 <X> lc_trk_g1_1
+(5 8) routing span4_horz_41 <X> lc_trk_g1_1
+(5 8) routing span4_horz_r_1 <X> lc_trk_g1_1
+(5 8) routing span4_horz_r_9 <X> lc_trk_g1_1
+(5 8) routing span4_vert_17 <X> lc_trk_g1_1
+(5 8) routing span4_vert_25 <X> lc_trk_g1_1
+(5 8) routing span4_vert_33 <X> lc_trk_g1_1
+(5 8) routing span4_vert_41 <X> lc_trk_g1_1
+(5 8) routing span4_vert_b_1 <X> lc_trk_g1_1
+(5 8) routing span4_vert_b_9 <X> lc_trk_g1_1
+(5 9) routing IO_B.logic_op_tnr_0 <X> lc_trk_g1_0
+(5 9) routing IO_L.logic_op_bnr_0 <X> lc_trk_g1_0
+(5 9) routing IO_R.logic_op_bnl_0 <X> lc_trk_g1_0
+(5 9) routing IO_T.logic_op_bnr_0 <X> lc_trk_g1_0
+(5 9) routing span12_horz_0 <X> lc_trk_g1_0
+(5 9) routing span12_vert_0 <X> lc_trk_g1_0
+(5 9) routing span4_horz_16 <X> lc_trk_g1_0
+(5 9) routing span4_horz_24 <X> lc_trk_g1_0
+(5 9) routing span4_horz_32 <X> lc_trk_g1_0
+(5 9) routing span4_horz_40 <X> lc_trk_g1_0
+(5 9) routing span4_horz_r_0 <X> lc_trk_g1_0
+(5 9) routing span4_horz_r_8 <X> lc_trk_g1_0
+(5 9) routing span4_vert_16 <X> lc_trk_g1_0
+(5 9) routing span4_vert_24 <X> lc_trk_g1_0
+(5 9) routing span4_vert_32 <X> lc_trk_g1_0
+(5 9) routing span4_vert_40 <X> lc_trk_g1_0
+(5 9) routing span4_vert_b_0 <X> lc_trk_g1_0
+(5 9) routing span4_vert_b_8 <X> lc_trk_g1_0
+(6 0) routing span12_horz_17 <X> lc_trk_g0_1
+(6 0) routing span12_horz_9 <X> lc_trk_g0_1
+(6 0) routing span12_vert_17 <X> lc_trk_g0_1
+(6 0) routing span12_vert_9 <X> lc_trk_g0_1
+(6 0) routing span4_horz_1 <X> lc_trk_g0_1
+(6 0) routing span4_horz_17 <X> lc_trk_g0_1
+(6 0) routing span4_horz_25 <X> lc_trk_g0_1
+(6 0) routing span4_horz_33 <X> lc_trk_g0_1
+(6 0) routing span4_horz_41 <X> lc_trk_g0_1
+(6 0) routing span4_horz_9 <X> lc_trk_g0_1
+(6 0) routing span4_vert_1 <X> lc_trk_g0_1
+(6 0) routing span4_vert_17 <X> lc_trk_g0_1
+(6 0) routing span4_vert_25 <X> lc_trk_g0_1
+(6 0) routing span4_vert_33 <X> lc_trk_g0_1
+(6 0) routing span4_vert_41 <X> lc_trk_g0_1
+(6 0) routing span4_vert_9 <X> lc_trk_g0_1
+(6 1) routing span12_horz_16 <X> lc_trk_g0_0
+(6 1) routing span12_horz_8 <X> lc_trk_g0_0
+(6 1) routing span12_vert_16 <X> lc_trk_g0_0
+(6 1) routing span12_vert_8 <X> lc_trk_g0_0
+(6 1) routing span4_horz_0 <X> lc_trk_g0_0
+(6 1) routing span4_horz_16 <X> lc_trk_g0_0
+(6 1) routing span4_horz_24 <X> lc_trk_g0_0
+(6 1) routing span4_horz_32 <X> lc_trk_g0_0
+(6 1) routing span4_horz_40 <X> lc_trk_g0_0
+(6 1) routing span4_horz_8 <X> lc_trk_g0_0
+(6 1) routing span4_vert_0 <X> lc_trk_g0_0
+(6 1) routing span4_vert_16 <X> lc_trk_g0_0
+(6 1) routing span4_vert_24 <X> lc_trk_g0_0
+(6 1) routing span4_vert_32 <X> lc_trk_g0_0
+(6 1) routing span4_vert_40 <X> lc_trk_g0_0
+(6 1) routing span4_vert_8 <X> lc_trk_g0_0
+(6 10) routing span12_horz_11 <X> lc_trk_g1_3
+(6 10) routing span12_horz_19 <X> lc_trk_g1_3
+(6 10) routing span12_vert_11 <X> lc_trk_g1_3
+(6 10) routing span12_vert_19 <X> lc_trk_g1_3
+(6 10) routing span4_horz_11 <X> lc_trk_g1_3
+(6 10) routing span4_horz_19 <X> lc_trk_g1_3
+(6 10) routing span4_horz_27 <X> lc_trk_g1_3
+(6 10) routing span4_horz_3 <X> lc_trk_g1_3
+(6 10) routing span4_horz_35 <X> lc_trk_g1_3
+(6 10) routing span4_horz_43 <X> lc_trk_g1_3
+(6 10) routing span4_vert_11 <X> lc_trk_g1_3
+(6 10) routing span4_vert_19 <X> lc_trk_g1_3
+(6 10) routing span4_vert_27 <X> lc_trk_g1_3
+(6 10) routing span4_vert_3 <X> lc_trk_g1_3
+(6 10) routing span4_vert_35 <X> lc_trk_g1_3
+(6 10) routing span4_vert_43 <X> lc_trk_g1_3
+(6 11) routing span12_horz_10 <X> lc_trk_g1_2
+(6 11) routing span12_horz_18 <X> lc_trk_g1_2
+(6 11) routing span12_vert_10 <X> lc_trk_g1_2
+(6 11) routing span12_vert_18 <X> lc_trk_g1_2
+(6 11) routing span4_horz_10 <X> lc_trk_g1_2
+(6 11) routing span4_horz_18 <X> lc_trk_g1_2
+(6 11) routing span4_horz_2 <X> lc_trk_g1_2
+(6 11) routing span4_horz_26 <X> lc_trk_g1_2
+(6 11) routing span4_horz_34 <X> lc_trk_g1_2
+(6 11) routing span4_horz_42 <X> lc_trk_g1_2
+(6 11) routing span4_vert_10 <X> lc_trk_g1_2
+(6 11) routing span4_vert_18 <X> lc_trk_g1_2
+(6 11) routing span4_vert_2 <X> lc_trk_g1_2
+(6 11) routing span4_vert_26 <X> lc_trk_g1_2
+(6 11) routing span4_vert_34 <X> lc_trk_g1_2
+(6 11) routing span4_vert_42 <X> lc_trk_g1_2
+(6 12) routing span12_horz_13 <X> lc_trk_g1_5
+(6 12) routing span12_horz_21 <X> lc_trk_g1_5
+(6 12) routing span12_vert_13 <X> lc_trk_g1_5
+(6 12) routing span12_vert_21 <X> lc_trk_g1_5
+(6 12) routing span4_horz_13 <X> lc_trk_g1_5
+(6 12) routing span4_horz_21 <X> lc_trk_g1_5
+(6 12) routing span4_horz_29 <X> lc_trk_g1_5
+(6 12) routing span4_horz_37 <X> lc_trk_g1_5
+(6 12) routing span4_horz_45 <X> lc_trk_g1_5
+(6 12) routing span4_horz_5 <X> lc_trk_g1_5
+(6 12) routing span4_vert_13 <X> lc_trk_g1_5
+(6 12) routing span4_vert_21 <X> lc_trk_g1_5
+(6 12) routing span4_vert_29 <X> lc_trk_g1_5
+(6 12) routing span4_vert_37 <X> lc_trk_g1_5
+(6 12) routing span4_vert_45 <X> lc_trk_g1_5
+(6 12) routing span4_vert_5 <X> lc_trk_g1_5
+(6 13) routing span12_horz_12 <X> lc_trk_g1_4
+(6 13) routing span12_horz_20 <X> lc_trk_g1_4
+(6 13) routing span12_vert_12 <X> lc_trk_g1_4
+(6 13) routing span12_vert_20 <X> lc_trk_g1_4
+(6 13) routing span4_horz_12 <X> lc_trk_g1_4
+(6 13) routing span4_horz_20 <X> lc_trk_g1_4
+(6 13) routing span4_horz_28 <X> lc_trk_g1_4
+(6 13) routing span4_horz_36 <X> lc_trk_g1_4
+(6 13) routing span4_horz_4 <X> lc_trk_g1_4
+(6 13) routing span4_horz_44 <X> lc_trk_g1_4
+(6 13) routing span4_vert_12 <X> lc_trk_g1_4
+(6 13) routing span4_vert_20 <X> lc_trk_g1_4
+(6 13) routing span4_vert_28 <X> lc_trk_g1_4
+(6 13) routing span4_vert_36 <X> lc_trk_g1_4
+(6 13) routing span4_vert_4 <X> lc_trk_g1_4
+(6 13) routing span4_vert_44 <X> lc_trk_g1_4
+(6 14) routing span12_horz_15 <X> lc_trk_g1_7
+(6 14) routing span12_horz_23 <X> lc_trk_g1_7
+(6 14) routing span12_vert_15 <X> lc_trk_g1_7
+(6 14) routing span12_vert_23 <X> lc_trk_g1_7
+(6 14) routing span4_horz_15 <X> lc_trk_g1_7
+(6 14) routing span4_horz_23 <X> lc_trk_g1_7
+(6 14) routing span4_horz_31 <X> lc_trk_g1_7
+(6 14) routing span4_horz_39 <X> lc_trk_g1_7
+(6 14) routing span4_horz_47 <X> lc_trk_g1_7
+(6 14) routing span4_horz_7 <X> lc_trk_g1_7
+(6 14) routing span4_vert_15 <X> lc_trk_g1_7
+(6 14) routing span4_vert_23 <X> lc_trk_g1_7
+(6 14) routing span4_vert_31 <X> lc_trk_g1_7
+(6 14) routing span4_vert_39 <X> lc_trk_g1_7
+(6 14) routing span4_vert_47 <X> lc_trk_g1_7
+(6 14) routing span4_vert_7 <X> lc_trk_g1_7
+(6 15) routing span12_horz_14 <X> lc_trk_g1_6
+(6 15) routing span12_horz_22 <X> lc_trk_g1_6
+(6 15) routing span12_vert_14 <X> lc_trk_g1_6
+(6 15) routing span12_vert_22 <X> lc_trk_g1_6
+(6 15) routing span4_horz_14 <X> lc_trk_g1_6
+(6 15) routing span4_horz_22 <X> lc_trk_g1_6
+(6 15) routing span4_horz_30 <X> lc_trk_g1_6
+(6 15) routing span4_horz_38 <X> lc_trk_g1_6
+(6 15) routing span4_horz_46 <X> lc_trk_g1_6
+(6 15) routing span4_horz_6 <X> lc_trk_g1_6
+(6 15) routing span4_vert_14 <X> lc_trk_g1_6
+(6 15) routing span4_vert_22 <X> lc_trk_g1_6
+(6 15) routing span4_vert_30 <X> lc_trk_g1_6
+(6 15) routing span4_vert_38 <X> lc_trk_g1_6
+(6 15) routing span4_vert_46 <X> lc_trk_g1_6
+(6 15) routing span4_vert_6 <X> lc_trk_g1_6
+(6 2) routing span12_horz_11 <X> lc_trk_g0_3
+(6 2) routing span12_horz_19 <X> lc_trk_g0_3
+(6 2) routing span12_vert_11 <X> lc_trk_g0_3
+(6 2) routing span12_vert_19 <X> lc_trk_g0_3
+(6 2) routing span4_horz_11 <X> lc_trk_g0_3
+(6 2) routing span4_horz_19 <X> lc_trk_g0_3
+(6 2) routing span4_horz_27 <X> lc_trk_g0_3
+(6 2) routing span4_horz_3 <X> lc_trk_g0_3
+(6 2) routing span4_horz_35 <X> lc_trk_g0_3
+(6 2) routing span4_horz_43 <X> lc_trk_g0_3
+(6 2) routing span4_vert_11 <X> lc_trk_g0_3
+(6 2) routing span4_vert_19 <X> lc_trk_g0_3
+(6 2) routing span4_vert_27 <X> lc_trk_g0_3
+(6 2) routing span4_vert_3 <X> lc_trk_g0_3
+(6 2) routing span4_vert_35 <X> lc_trk_g0_3
+(6 2) routing span4_vert_43 <X> lc_trk_g0_3
+(6 3) routing span12_horz_10 <X> lc_trk_g0_2
+(6 3) routing span12_horz_18 <X> lc_trk_g0_2
+(6 3) routing span12_vert_10 <X> lc_trk_g0_2
+(6 3) routing span12_vert_18 <X> lc_trk_g0_2
+(6 3) routing span4_horz_10 <X> lc_trk_g0_2
+(6 3) routing span4_horz_18 <X> lc_trk_g0_2
+(6 3) routing span4_horz_2 <X> lc_trk_g0_2
+(6 3) routing span4_horz_26 <X> lc_trk_g0_2
+(6 3) routing span4_horz_34 <X> lc_trk_g0_2
+(6 3) routing span4_horz_42 <X> lc_trk_g0_2
+(6 3) routing span4_vert_10 <X> lc_trk_g0_2
+(6 3) routing span4_vert_18 <X> lc_trk_g0_2
+(6 3) routing span4_vert_2 <X> lc_trk_g0_2
+(6 3) routing span4_vert_26 <X> lc_trk_g0_2
+(6 3) routing span4_vert_34 <X> lc_trk_g0_2
+(6 3) routing span4_vert_42 <X> lc_trk_g0_2
+(6 4) routing span12_horz_13 <X> lc_trk_g0_5
+(6 4) routing span12_horz_21 <X> lc_trk_g0_5
+(6 4) routing span12_vert_13 <X> lc_trk_g0_5
+(6 4) routing span12_vert_21 <X> lc_trk_g0_5
+(6 4) routing span4_horz_13 <X> lc_trk_g0_5
+(6 4) routing span4_horz_21 <X> lc_trk_g0_5
+(6 4) routing span4_horz_29 <X> lc_trk_g0_5
+(6 4) routing span4_horz_37 <X> lc_trk_g0_5
+(6 4) routing span4_horz_45 <X> lc_trk_g0_5
+(6 4) routing span4_horz_5 <X> lc_trk_g0_5
+(6 4) routing span4_vert_13 <X> lc_trk_g0_5
+(6 4) routing span4_vert_21 <X> lc_trk_g0_5
+(6 4) routing span4_vert_29 <X> lc_trk_g0_5
+(6 4) routing span4_vert_37 <X> lc_trk_g0_5
+(6 4) routing span4_vert_45 <X> lc_trk_g0_5
+(6 4) routing span4_vert_5 <X> lc_trk_g0_5
+(6 5) routing span12_horz_12 <X> lc_trk_g0_4
+(6 5) routing span12_horz_20 <X> lc_trk_g0_4
+(6 5) routing span12_vert_12 <X> lc_trk_g0_4
+(6 5) routing span12_vert_20 <X> lc_trk_g0_4
+(6 5) routing span4_horz_12 <X> lc_trk_g0_4
+(6 5) routing span4_horz_20 <X> lc_trk_g0_4
+(6 5) routing span4_horz_28 <X> lc_trk_g0_4
+(6 5) routing span4_horz_36 <X> lc_trk_g0_4
+(6 5) routing span4_horz_4 <X> lc_trk_g0_4
+(6 5) routing span4_horz_44 <X> lc_trk_g0_4
+(6 5) routing span4_vert_12 <X> lc_trk_g0_4
+(6 5) routing span4_vert_20 <X> lc_trk_g0_4
+(6 5) routing span4_vert_28 <X> lc_trk_g0_4
+(6 5) routing span4_vert_36 <X> lc_trk_g0_4
+(6 5) routing span4_vert_4 <X> lc_trk_g0_4
+(6 5) routing span4_vert_44 <X> lc_trk_g0_4
+(6 6) routing span12_horz_15 <X> lc_trk_g0_7
+(6 6) routing span12_horz_23 <X> lc_trk_g0_7
+(6 6) routing span12_vert_15 <X> lc_trk_g0_7
+(6 6) routing span12_vert_23 <X> lc_trk_g0_7
+(6 6) routing span4_horz_15 <X> lc_trk_g0_7
+(6 6) routing span4_horz_23 <X> lc_trk_g0_7
+(6 6) routing span4_horz_31 <X> lc_trk_g0_7
+(6 6) routing span4_horz_39 <X> lc_trk_g0_7
+(6 6) routing span4_horz_47 <X> lc_trk_g0_7
+(6 6) routing span4_horz_7 <X> lc_trk_g0_7
+(6 6) routing span4_vert_15 <X> lc_trk_g0_7
+(6 6) routing span4_vert_23 <X> lc_trk_g0_7
+(6 6) routing span4_vert_31 <X> lc_trk_g0_7
+(6 6) routing span4_vert_39 <X> lc_trk_g0_7
+(6 6) routing span4_vert_47 <X> lc_trk_g0_7
+(6 6) routing span4_vert_7 <X> lc_trk_g0_7
+(6 7) routing span12_horz_14 <X> lc_trk_g0_6
+(6 7) routing span12_horz_22 <X> lc_trk_g0_6
+(6 7) routing span12_vert_14 <X> lc_trk_g0_6
+(6 7) routing span12_vert_22 <X> lc_trk_g0_6
+(6 7) routing span4_horz_14 <X> lc_trk_g0_6
+(6 7) routing span4_horz_22 <X> lc_trk_g0_6
+(6 7) routing span4_horz_30 <X> lc_trk_g0_6
+(6 7) routing span4_horz_38 <X> lc_trk_g0_6
+(6 7) routing span4_horz_46 <X> lc_trk_g0_6
+(6 7) routing span4_horz_6 <X> lc_trk_g0_6
+(6 7) routing span4_vert_14 <X> lc_trk_g0_6
+(6 7) routing span4_vert_22 <X> lc_trk_g0_6
+(6 7) routing span4_vert_30 <X> lc_trk_g0_6
+(6 7) routing span4_vert_38 <X> lc_trk_g0_6
+(6 7) routing span4_vert_46 <X> lc_trk_g0_6
+(6 7) routing span4_vert_6 <X> lc_trk_g0_6
+(6 8) routing span12_horz_17 <X> lc_trk_g1_1
+(6 8) routing span12_horz_9 <X> lc_trk_g1_1
+(6 8) routing span12_vert_17 <X> lc_trk_g1_1
+(6 8) routing span12_vert_9 <X> lc_trk_g1_1
+(6 8) routing span4_horz_1 <X> lc_trk_g1_1
+(6 8) routing span4_horz_17 <X> lc_trk_g1_1
+(6 8) routing span4_horz_25 <X> lc_trk_g1_1
+(6 8) routing span4_horz_33 <X> lc_trk_g1_1
+(6 8) routing span4_horz_41 <X> lc_trk_g1_1
+(6 8) routing span4_horz_9 <X> lc_trk_g1_1
+(6 8) routing span4_vert_1 <X> lc_trk_g1_1
+(6 8) routing span4_vert_17 <X> lc_trk_g1_1
+(6 8) routing span4_vert_25 <X> lc_trk_g1_1
+(6 8) routing span4_vert_33 <X> lc_trk_g1_1
+(6 8) routing span4_vert_41 <X> lc_trk_g1_1
+(6 8) routing span4_vert_9 <X> lc_trk_g1_1
+(6 9) routing span12_horz_16 <X> lc_trk_g1_0
+(6 9) routing span12_horz_8 <X> lc_trk_g1_0
+(6 9) routing span12_vert_16 <X> lc_trk_g1_0
+(6 9) routing span12_vert_8 <X> lc_trk_g1_0
+(6 9) routing span4_horz_0 <X> lc_trk_g1_0
+(6 9) routing span4_horz_16 <X> lc_trk_g1_0
+(6 9) routing span4_horz_24 <X> lc_trk_g1_0
+(6 9) routing span4_horz_32 <X> lc_trk_g1_0
+(6 9) routing span4_horz_40 <X> lc_trk_g1_0
+(6 9) routing span4_horz_8 <X> lc_trk_g1_0
+(6 9) routing span4_vert_0 <X> lc_trk_g1_0
+(6 9) routing span4_vert_16 <X> lc_trk_g1_0
+(6 9) routing span4_vert_24 <X> lc_trk_g1_0
+(6 9) routing span4_vert_32 <X> lc_trk_g1_0
+(6 9) routing span4_vert_40 <X> lc_trk_g1_0
+(6 9) routing span4_vert_8 <X> lc_trk_g1_0
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bnl_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bnr_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bot_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_lft_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_rgt_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_tnl_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_tnr_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_top_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_17 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_9 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_17 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_9 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_17 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_25 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_33 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_41 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_9 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_r_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_r_9 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_17 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_25 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_33 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_41 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_9 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_b_1 lc_trk_g0_1
+(7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_b_9 lc_trk_g0_1
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bnl_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bnr_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bot_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_lft_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_rgt_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_tnl_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_tnr_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_top_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_16 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_8 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_16 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_8 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_16 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_24 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_32 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_40 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_8 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_r_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_r_8 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_16 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_24 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_32 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_40 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_8 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_b_0 lc_trk_g0_0
+(7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_b_8 lc_trk_g0_0
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bnl_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bnr_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bot_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_lft_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_rgt_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_tnl_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_tnr_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_top_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_19 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_19 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_19 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_27 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_35 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_43 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_r_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_r_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_19 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_27 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_3 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_35 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_43 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_b_11 lc_trk_g1_3
+(7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_b_3 lc_trk_g1_3
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bnl_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bnr_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bot_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_lft_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_rgt_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_tnl_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_tnr_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_top_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_18 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_18 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_18 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_26 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_34 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_42 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_r_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_r_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_18 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_2 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_26 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_34 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_42 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_b_10 lc_trk_g1_2
+(7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_b_2 lc_trk_g1_2
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bnl_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bnr_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bot_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_lft_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_rgt_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_tnl_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_tnr_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_top_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_21 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_21 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_21 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_29 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_37 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_45 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_r_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_r_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_21 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_29 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_37 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_45 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_5 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_b_13 lc_trk_g1_5
+(7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_b_5 lc_trk_g1_5
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bnl_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bnr_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bot_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_lft_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_rgt_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_tnl_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_tnr_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_top_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_20 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_20 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_20 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_28 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_36 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_44 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_r_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_r_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_20 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_28 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_36 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_4 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_44 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_b_12 lc_trk_g1_4
+(7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_b_4 lc_trk_g1_4
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bnl_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bnr_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bot_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_lft_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_rgt_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_tnl_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_tnr_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_top_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_23 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_23 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_23 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_31 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_39 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_47 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_r_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_r_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_23 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_31 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_39 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_47 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_7 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_15 lc_trk_g1_7
+(7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_7 lc_trk_g1_7
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bnl_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bnr_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bot_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_lft_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_rgt_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_tnl_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_tnr_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_top_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_22 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_22 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_22 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_30 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_38 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_46 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_r_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_r_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_22 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_30 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_38 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_46 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_6 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_b_14 lc_trk_g1_6
+(7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_b_6 lc_trk_g1_6
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bnl_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bnr_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bot_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_lft_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_rgt_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_tnl_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_tnr_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_top_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_19 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_19 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_19 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_27 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_35 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_43 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_r_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_r_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_19 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_27 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_3 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_35 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_43 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_11 lc_trk_g0_3
+(7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_3 lc_trk_g0_3
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bnl_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bnr_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bot_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_lft_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_rgt_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_tnl_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_tnr_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_top_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_18 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_18 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_18 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_26 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_34 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_42 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_r_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_r_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_18 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_2 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_26 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_34 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_42 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_b_10 lc_trk_g0_2
+(7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_b_2 lc_trk_g0_2
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bnl_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bnr_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bot_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_lft_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_rgt_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_tnl_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_tnr_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_top_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_21 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_21 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_21 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_29 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_37 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_45 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_r_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_r_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_21 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_29 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_37 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_45 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_5 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_b_13 lc_trk_g0_5
+(7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_b_5 lc_trk_g0_5
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bnl_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bnr_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bot_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_lft_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_rgt_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_tnl_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_tnr_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_top_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_20 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_20 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_20 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_28 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_36 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_44 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_r_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_r_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_20 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_28 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_36 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_4 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_44 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_b_12 lc_trk_g0_4
+(7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_b_4 lc_trk_g0_4
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bnl_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bnr_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bot_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_lft_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_rgt_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_tnl_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_tnr_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_top_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_23 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_23 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_23 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_31 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_39 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_47 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_r_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_r_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_23 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_31 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_39 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_47 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_7 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_b_15 lc_trk_g0_7
+(7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_b_7 lc_trk_g0_7
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bnl_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bnr_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bot_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_lft_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_rgt_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_tnl_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_tnr_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_top_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_22 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_22 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_22 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_30 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_38 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_46 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_r_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_r_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_22 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_30 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_38 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_46 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_6 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_b_14 lc_trk_g0_6
+(7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_b_6 lc_trk_g0_6
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bnl_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bnr_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bot_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_lft_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_rgt_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_tnl_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_tnr_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_top_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_17 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_9 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_17 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_9 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_17 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_25 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_33 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_41 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_9 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_r_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_r_9 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_17 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_25 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_33 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_41 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_9 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_b_1 lc_trk_g1_1
+(7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_b_9 lc_trk_g1_1
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bnl_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bnr_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bot_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_lft_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_rgt_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_tnl_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_tnr_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_top_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_16 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_8 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_16 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_8 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_16 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_24 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_32 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_40 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_8 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_r_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_r_8 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_16 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_24 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_32 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_40 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_8 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_b_0 lc_trk_g1_0
+(7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_b_8 lc_trk_g1_0
+(8 0) routing IO_B.logic_op_tnl_1 <X> lc_trk_g0_1
+(8 0) routing IO_B.logic_op_top_1 <X> lc_trk_g0_1
+(8 0) routing IO_L.logic_op_rgt_1 <X> lc_trk_g0_1
+(8 0) routing IO_L.logic_op_tnr_1 <X> lc_trk_g0_1
+(8 0) routing IO_R.logic_op_lft_1 <X> lc_trk_g0_1
+(8 0) routing IO_R.logic_op_tnl_1 <X> lc_trk_g0_1
+(8 0) routing IO_T.logic_op_bnl_1 <X> lc_trk_g0_1
+(8 0) routing IO_T.logic_op_bot_1 <X> lc_trk_g0_1
+(8 0) routing span12_horz_1 <X> lc_trk_g0_1
+(8 0) routing span12_vert_1 <X> lc_trk_g0_1
+(8 0) routing span4_horz_1 <X> lc_trk_g0_1
+(8 0) routing span4_horz_33 <X> lc_trk_g0_1
+(8 0) routing span4_horz_41 <X> lc_trk_g0_1
+(8 0) routing span4_horz_9 <X> lc_trk_g0_1
+(8 0) routing span4_horz_r_9 <X> lc_trk_g0_1
+(8 0) routing span4_vert_1 <X> lc_trk_g0_1
+(8 0) routing span4_vert_33 <X> lc_trk_g0_1
+(8 0) routing span4_vert_41 <X> lc_trk_g0_1
+(8 0) routing span4_vert_9 <X> lc_trk_g0_1
+(8 0) routing span4_vert_b_9 <X> lc_trk_g0_1
+(8 1) routing IO_B.logic_op_top_1 <X> lc_trk_g0_1
+(8 1) routing IO_L.logic_op_rgt_1 <X> lc_trk_g0_1
+(8 1) routing IO_R.logic_op_lft_1 <X> lc_trk_g0_1
+(8 1) routing IO_T.logic_op_bot_1 <X> lc_trk_g0_1
+(8 1) routing span12_horz_1 <X> lc_trk_g0_1
+(8 1) routing span12_horz_17 <X> lc_trk_g0_1
+(8 1) routing span12_vert_1 <X> lc_trk_g0_1
+(8 1) routing span12_vert_17 <X> lc_trk_g0_1
+(8 1) routing span4_horz_25 <X> lc_trk_g0_1
+(8 1) routing span4_horz_41 <X> lc_trk_g0_1
+(8 1) routing span4_horz_9 <X> lc_trk_g0_1
+(8 1) routing span4_horz_r_1 <X> lc_trk_g0_1
+(8 1) routing span4_vert_25 <X> lc_trk_g0_1
+(8 1) routing span4_vert_41 <X> lc_trk_g0_1
+(8 1) routing span4_vert_9 <X> lc_trk_g0_1
+(8 1) routing span4_vert_b_1 <X> lc_trk_g0_1
+(8 10) routing IO_B.logic_op_tnl_3 <X> lc_trk_g1_3
+(8 10) routing IO_B.logic_op_top_3 <X> lc_trk_g1_3
+(8 10) routing IO_L.logic_op_rgt_3 <X> lc_trk_g1_3
+(8 10) routing IO_L.logic_op_tnr_3 <X> lc_trk_g1_3
+(8 10) routing IO_R.logic_op_lft_3 <X> lc_trk_g1_3
+(8 10) routing IO_R.logic_op_tnl_3 <X> lc_trk_g1_3
+(8 10) routing IO_T.logic_op_bnl_3 <X> lc_trk_g1_3
+(8 10) routing IO_T.logic_op_bot_3 <X> lc_trk_g1_3
+(8 10) routing span12_horz_3 <X> lc_trk_g1_3
+(8 10) routing span12_vert_3 <X> lc_trk_g1_3
+(8 10) routing span4_horz_11 <X> lc_trk_g1_3
+(8 10) routing span4_horz_3 <X> lc_trk_g1_3
+(8 10) routing span4_horz_35 <X> lc_trk_g1_3
+(8 10) routing span4_horz_43 <X> lc_trk_g1_3
+(8 10) routing span4_horz_r_11 <X> lc_trk_g1_3
+(8 10) routing span4_vert_11 <X> lc_trk_g1_3
+(8 10) routing span4_vert_3 <X> lc_trk_g1_3
+(8 10) routing span4_vert_35 <X> lc_trk_g1_3
+(8 10) routing span4_vert_43 <X> lc_trk_g1_3
+(8 10) routing span4_vert_b_11 <X> lc_trk_g1_3
+(8 11) routing IO_B.logic_op_top_3 <X> lc_trk_g1_3
+(8 11) routing IO_L.logic_op_rgt_3 <X> lc_trk_g1_3
+(8 11) routing IO_R.logic_op_lft_3 <X> lc_trk_g1_3
+(8 11) routing IO_T.logic_op_bot_3 <X> lc_trk_g1_3
+(8 11) routing span12_horz_19 <X> lc_trk_g1_3
+(8 11) routing span12_horz_3 <X> lc_trk_g1_3
+(8 11) routing span12_vert_19 <X> lc_trk_g1_3
+(8 11) routing span12_vert_3 <X> lc_trk_g1_3
+(8 11) routing span4_horz_11 <X> lc_trk_g1_3
+(8 11) routing span4_horz_27 <X> lc_trk_g1_3
+(8 11) routing span4_horz_43 <X> lc_trk_g1_3
+(8 11) routing span4_horz_r_3 <X> lc_trk_g1_3
+(8 11) routing span4_vert_11 <X> lc_trk_g1_3
+(8 11) routing span4_vert_27 <X> lc_trk_g1_3
+(8 11) routing span4_vert_43 <X> lc_trk_g1_3
+(8 11) routing span4_vert_b_3 <X> lc_trk_g1_3
+(8 12) routing IO_B.logic_op_tnl_5 <X> lc_trk_g1_5
+(8 12) routing IO_B.logic_op_top_5 <X> lc_trk_g1_5
+(8 12) routing IO_L.logic_op_rgt_5 <X> lc_trk_g1_5
+(8 12) routing IO_L.logic_op_tnr_5 <X> lc_trk_g1_5
+(8 12) routing IO_R.logic_op_lft_5 <X> lc_trk_g1_5
+(8 12) routing IO_R.logic_op_tnl_5 <X> lc_trk_g1_5
+(8 12) routing IO_T.logic_op_bnl_5 <X> lc_trk_g1_5
+(8 12) routing IO_T.logic_op_bot_5 <X> lc_trk_g1_5
+(8 12) routing span12_horz_5 <X> lc_trk_g1_5
+(8 12) routing span12_vert_5 <X> lc_trk_g1_5
+(8 12) routing span4_horz_13 <X> lc_trk_g1_5
+(8 12) routing span4_horz_37 <X> lc_trk_g1_5
+(8 12) routing span4_horz_45 <X> lc_trk_g1_5
+(8 12) routing span4_horz_5 <X> lc_trk_g1_5
+(8 12) routing span4_horz_r_13 <X> lc_trk_g1_5
+(8 12) routing span4_vert_13 <X> lc_trk_g1_5
+(8 12) routing span4_vert_37 <X> lc_trk_g1_5
+(8 12) routing span4_vert_45 <X> lc_trk_g1_5
+(8 12) routing span4_vert_5 <X> lc_trk_g1_5
+(8 12) routing span4_vert_b_13 <X> lc_trk_g1_5
+(8 13) routing IO_B.logic_op_top_5 <X> lc_trk_g1_5
+(8 13) routing IO_L.logic_op_rgt_5 <X> lc_trk_g1_5
+(8 13) routing IO_R.logic_op_lft_5 <X> lc_trk_g1_5
+(8 13) routing IO_T.logic_op_bot_5 <X> lc_trk_g1_5
+(8 13) routing span12_horz_21 <X> lc_trk_g1_5
+(8 13) routing span12_horz_5 <X> lc_trk_g1_5
+(8 13) routing span12_vert_21 <X> lc_trk_g1_5
+(8 13) routing span12_vert_5 <X> lc_trk_g1_5
+(8 13) routing span4_horz_13 <X> lc_trk_g1_5
+(8 13) routing span4_horz_29 <X> lc_trk_g1_5
+(8 13) routing span4_horz_45 <X> lc_trk_g1_5
+(8 13) routing span4_horz_r_5 <X> lc_trk_g1_5
+(8 13) routing span4_vert_13 <X> lc_trk_g1_5
+(8 13) routing span4_vert_29 <X> lc_trk_g1_5
+(8 13) routing span4_vert_45 <X> lc_trk_g1_5
+(8 13) routing span4_vert_b_5 <X> lc_trk_g1_5
+(8 14) routing IO_B.logic_op_tnl_7 <X> lc_trk_g1_7
+(8 14) routing IO_B.logic_op_top_7 <X> lc_trk_g1_7
+(8 14) routing IO_L.logic_op_rgt_7 <X> lc_trk_g1_7
+(8 14) routing IO_L.logic_op_tnr_7 <X> lc_trk_g1_7
+(8 14) routing IO_R.logic_op_lft_7 <X> lc_trk_g1_7
+(8 14) routing IO_R.logic_op_tnl_7 <X> lc_trk_g1_7
+(8 14) routing IO_T.logic_op_bnl_7 <X> lc_trk_g1_7
+(8 14) routing IO_T.logic_op_bot_7 <X> lc_trk_g1_7
+(8 14) routing span12_horz_7 <X> lc_trk_g1_7
+(8 14) routing span12_vert_7 <X> lc_trk_g1_7
+(8 14) routing span4_horz_15 <X> lc_trk_g1_7
+(8 14) routing span4_horz_39 <X> lc_trk_g1_7
+(8 14) routing span4_horz_47 <X> lc_trk_g1_7
+(8 14) routing span4_horz_7 <X> lc_trk_g1_7
+(8 14) routing span4_horz_r_15 <X> lc_trk_g1_7
+(8 14) routing span4_vert_15 <X> lc_trk_g1_7
+(8 14) routing span4_vert_39 <X> lc_trk_g1_7
+(8 14) routing span4_vert_47 <X> lc_trk_g1_7
+(8 14) routing span4_vert_7 <X> lc_trk_g1_7
+(8 14) routing span4_vert_b_15 <X> lc_trk_g1_7
+(8 15) routing IO_B.logic_op_top_7 <X> lc_trk_g1_7
+(8 15) routing IO_L.logic_op_rgt_7 <X> lc_trk_g1_7
+(8 15) routing IO_R.logic_op_lft_7 <X> lc_trk_g1_7
+(8 15) routing IO_T.logic_op_bot_7 <X> lc_trk_g1_7
+(8 15) routing span12_horz_23 <X> lc_trk_g1_7
+(8 15) routing span12_horz_7 <X> lc_trk_g1_7
+(8 15) routing span12_vert_23 <X> lc_trk_g1_7
+(8 15) routing span12_vert_7 <X> lc_trk_g1_7
+(8 15) routing span4_horz_15 <X> lc_trk_g1_7
+(8 15) routing span4_horz_31 <X> lc_trk_g1_7
+(8 15) routing span4_horz_47 <X> lc_trk_g1_7
+(8 15) routing span4_horz_r_7 <X> lc_trk_g1_7
+(8 15) routing span4_vert_15 <X> lc_trk_g1_7
+(8 15) routing span4_vert_31 <X> lc_trk_g1_7
+(8 15) routing span4_vert_47 <X> lc_trk_g1_7
+(8 15) routing span4_vert_b_7 <X> lc_trk_g1_7
+(8 2) routing IO_B.logic_op_tnl_3 <X> lc_trk_g0_3
+(8 2) routing IO_B.logic_op_top_3 <X> lc_trk_g0_3
+(8 2) routing IO_L.logic_op_rgt_3 <X> lc_trk_g0_3
+(8 2) routing IO_L.logic_op_tnr_3 <X> lc_trk_g0_3
+(8 2) routing IO_R.logic_op_lft_3 <X> lc_trk_g0_3
+(8 2) routing IO_R.logic_op_tnl_3 <X> lc_trk_g0_3
+(8 2) routing IO_T.logic_op_bnl_3 <X> lc_trk_g0_3
+(8 2) routing IO_T.logic_op_bot_3 <X> lc_trk_g0_3
+(8 2) routing span12_horz_3 <X> lc_trk_g0_3
+(8 2) routing span12_vert_3 <X> lc_trk_g0_3
+(8 2) routing span4_horz_11 <X> lc_trk_g0_3
+(8 2) routing span4_horz_3 <X> lc_trk_g0_3
+(8 2) routing span4_horz_35 <X> lc_trk_g0_3
+(8 2) routing span4_horz_43 <X> lc_trk_g0_3
+(8 2) routing span4_horz_r_11 <X> lc_trk_g0_3
+(8 2) routing span4_vert_11 <X> lc_trk_g0_3
+(8 2) routing span4_vert_3 <X> lc_trk_g0_3
+(8 2) routing span4_vert_35 <X> lc_trk_g0_3
+(8 2) routing span4_vert_43 <X> lc_trk_g0_3
+(8 2) routing span4_vert_b_11 <X> lc_trk_g0_3
+(8 3) routing IO_B.logic_op_top_3 <X> lc_trk_g0_3
+(8 3) routing IO_L.logic_op_rgt_3 <X> lc_trk_g0_3
+(8 3) routing IO_R.logic_op_lft_3 <X> lc_trk_g0_3
+(8 3) routing IO_T.logic_op_bot_3 <X> lc_trk_g0_3
+(8 3) routing span12_horz_19 <X> lc_trk_g0_3
+(8 3) routing span12_horz_3 <X> lc_trk_g0_3
+(8 3) routing span12_vert_19 <X> lc_trk_g0_3
+(8 3) routing span12_vert_3 <X> lc_trk_g0_3
+(8 3) routing span4_horz_11 <X> lc_trk_g0_3
+(8 3) routing span4_horz_27 <X> lc_trk_g0_3
+(8 3) routing span4_horz_43 <X> lc_trk_g0_3
+(8 3) routing span4_horz_r_3 <X> lc_trk_g0_3
+(8 3) routing span4_vert_11 <X> lc_trk_g0_3
+(8 3) routing span4_vert_27 <X> lc_trk_g0_3
+(8 3) routing span4_vert_43 <X> lc_trk_g0_3
+(8 3) routing span4_vert_b_3 <X> lc_trk_g0_3
+(8 4) routing IO_B.logic_op_tnl_5 <X> lc_trk_g0_5
+(8 4) routing IO_B.logic_op_top_5 <X> lc_trk_g0_5
+(8 4) routing IO_L.logic_op_rgt_5 <X> lc_trk_g0_5
+(8 4) routing IO_L.logic_op_tnr_5 <X> lc_trk_g0_5
+(8 4) routing IO_R.logic_op_lft_5 <X> lc_trk_g0_5
+(8 4) routing IO_R.logic_op_tnl_5 <X> lc_trk_g0_5
+(8 4) routing IO_T.logic_op_bnl_5 <X> lc_trk_g0_5
+(8 4) routing IO_T.logic_op_bot_5 <X> lc_trk_g0_5
+(8 4) routing span12_horz_5 <X> lc_trk_g0_5
+(8 4) routing span12_vert_5 <X> lc_trk_g0_5
+(8 4) routing span4_horz_13 <X> lc_trk_g0_5
+(8 4) routing span4_horz_37 <X> lc_trk_g0_5
+(8 4) routing span4_horz_45 <X> lc_trk_g0_5
+(8 4) routing span4_horz_5 <X> lc_trk_g0_5
+(8 4) routing span4_horz_r_13 <X> lc_trk_g0_5
+(8 4) routing span4_vert_13 <X> lc_trk_g0_5
+(8 4) routing span4_vert_37 <X> lc_trk_g0_5
+(8 4) routing span4_vert_45 <X> lc_trk_g0_5
+(8 4) routing span4_vert_5 <X> lc_trk_g0_5
+(8 4) routing span4_vert_b_13 <X> lc_trk_g0_5
+(8 5) routing IO_B.logic_op_top_5 <X> lc_trk_g0_5
+(8 5) routing IO_L.logic_op_rgt_5 <X> lc_trk_g0_5
+(8 5) routing IO_R.logic_op_lft_5 <X> lc_trk_g0_5
+(8 5) routing IO_T.logic_op_bot_5 <X> lc_trk_g0_5
+(8 5) routing span12_horz_21 <X> lc_trk_g0_5
+(8 5) routing span12_horz_5 <X> lc_trk_g0_5
+(8 5) routing span12_vert_21 <X> lc_trk_g0_5
+(8 5) routing span12_vert_5 <X> lc_trk_g0_5
+(8 5) routing span4_horz_13 <X> lc_trk_g0_5
+(8 5) routing span4_horz_29 <X> lc_trk_g0_5
+(8 5) routing span4_horz_45 <X> lc_trk_g0_5
+(8 5) routing span4_horz_r_5 <X> lc_trk_g0_5
+(8 5) routing span4_vert_13 <X> lc_trk_g0_5
+(8 5) routing span4_vert_29 <X> lc_trk_g0_5
+(8 5) routing span4_vert_45 <X> lc_trk_g0_5
+(8 5) routing span4_vert_b_5 <X> lc_trk_g0_5
+(8 6) routing IO_B.logic_op_tnl_7 <X> lc_trk_g0_7
+(8 6) routing IO_B.logic_op_top_7 <X> lc_trk_g0_7
+(8 6) routing IO_L.logic_op_rgt_7 <X> lc_trk_g0_7
+(8 6) routing IO_L.logic_op_tnr_7 <X> lc_trk_g0_7
+(8 6) routing IO_R.logic_op_lft_7 <X> lc_trk_g0_7
+(8 6) routing IO_R.logic_op_tnl_7 <X> lc_trk_g0_7
+(8 6) routing IO_T.logic_op_bnl_7 <X> lc_trk_g0_7
+(8 6) routing IO_T.logic_op_bot_7 <X> lc_trk_g0_7
+(8 6) routing span12_horz_7 <X> lc_trk_g0_7
+(8 6) routing span12_vert_7 <X> lc_trk_g0_7
+(8 6) routing span4_horz_15 <X> lc_trk_g0_7
+(8 6) routing span4_horz_39 <X> lc_trk_g0_7
+(8 6) routing span4_horz_47 <X> lc_trk_g0_7
+(8 6) routing span4_horz_7 <X> lc_trk_g0_7
+(8 6) routing span4_horz_r_15 <X> lc_trk_g0_7
+(8 6) routing span4_vert_15 <X> lc_trk_g0_7
+(8 6) routing span4_vert_39 <X> lc_trk_g0_7
+(8 6) routing span4_vert_47 <X> lc_trk_g0_7
+(8 6) routing span4_vert_7 <X> lc_trk_g0_7
+(8 6) routing span4_vert_b_15 <X> lc_trk_g0_7
+(8 7) routing IO_B.logic_op_top_7 <X> lc_trk_g0_7
+(8 7) routing IO_L.logic_op_rgt_7 <X> lc_trk_g0_7
+(8 7) routing IO_R.logic_op_lft_7 <X> lc_trk_g0_7
+(8 7) routing IO_T.logic_op_bot_7 <X> lc_trk_g0_7
+(8 7) routing span12_horz_23 <X> lc_trk_g0_7
+(8 7) routing span12_horz_7 <X> lc_trk_g0_7
+(8 7) routing span12_vert_23 <X> lc_trk_g0_7
+(8 7) routing span12_vert_7 <X> lc_trk_g0_7
+(8 7) routing span4_horz_15 <X> lc_trk_g0_7
+(8 7) routing span4_horz_31 <X> lc_trk_g0_7
+(8 7) routing span4_horz_47 <X> lc_trk_g0_7
+(8 7) routing span4_horz_r_7 <X> lc_trk_g0_7
+(8 7) routing span4_vert_15 <X> lc_trk_g0_7
+(8 7) routing span4_vert_31 <X> lc_trk_g0_7
+(8 7) routing span4_vert_47 <X> lc_trk_g0_7
+(8 7) routing span4_vert_b_7 <X> lc_trk_g0_7
+(8 8) routing IO_B.logic_op_tnl_1 <X> lc_trk_g1_1
+(8 8) routing IO_B.logic_op_top_1 <X> lc_trk_g1_1
+(8 8) routing IO_L.logic_op_rgt_1 <X> lc_trk_g1_1
+(8 8) routing IO_L.logic_op_tnr_1 <X> lc_trk_g1_1
+(8 8) routing IO_R.logic_op_lft_1 <X> lc_trk_g1_1
+(8 8) routing IO_R.logic_op_tnl_1 <X> lc_trk_g1_1
+(8 8) routing IO_T.logic_op_bnl_1 <X> lc_trk_g1_1
+(8 8) routing IO_T.logic_op_bot_1 <X> lc_trk_g1_1
+(8 8) routing span12_horz_1 <X> lc_trk_g1_1
+(8 8) routing span12_vert_1 <X> lc_trk_g1_1
+(8 8) routing span4_horz_1 <X> lc_trk_g1_1
+(8 8) routing span4_horz_33 <X> lc_trk_g1_1
+(8 8) routing span4_horz_41 <X> lc_trk_g1_1
+(8 8) routing span4_horz_9 <X> lc_trk_g1_1
+(8 8) routing span4_horz_r_9 <X> lc_trk_g1_1
+(8 8) routing span4_vert_1 <X> lc_trk_g1_1
+(8 8) routing span4_vert_33 <X> lc_trk_g1_1
+(8 8) routing span4_vert_41 <X> lc_trk_g1_1
+(8 8) routing span4_vert_9 <X> lc_trk_g1_1
+(8 8) routing span4_vert_b_9 <X> lc_trk_g1_1
+(8 9) routing IO_B.logic_op_top_1 <X> lc_trk_g1_1
+(8 9) routing IO_L.logic_op_rgt_1 <X> lc_trk_g1_1
+(8 9) routing IO_R.logic_op_lft_1 <X> lc_trk_g1_1
+(8 9) routing IO_T.logic_op_bot_1 <X> lc_trk_g1_1
+(8 9) routing span12_horz_1 <X> lc_trk_g1_1
+(8 9) routing span12_horz_17 <X> lc_trk_g1_1
+(8 9) routing span12_vert_1 <X> lc_trk_g1_1
+(8 9) routing span12_vert_17 <X> lc_trk_g1_1
+(8 9) routing span4_horz_25 <X> lc_trk_g1_1
+(8 9) routing span4_horz_41 <X> lc_trk_g1_1
+(8 9) routing span4_horz_9 <X> lc_trk_g1_1
+(8 9) routing span4_horz_r_1 <X> lc_trk_g1_1
+(8 9) routing span4_vert_25 <X> lc_trk_g1_1
+(8 9) routing span4_vert_41 <X> lc_trk_g1_1
+(8 9) routing span4_vert_9 <X> lc_trk_g1_1
+(8 9) routing span4_vert_b_1 <X> lc_trk_g1_1
+(9 0) Column buffer control bit: BIOLEFT_half_column_clock_enable_1
+(9 0) Column buffer control bit: IOLEFT_half_column_clock_enable_1
+(9 0) Column buffer control bit: IORIGHT_half_column_clock_enable_1
+(9 1) Column buffer control bit: BIOLEFT_half_column_clock_enable_0
+(9 1) Column buffer control bit: IOLEFT_half_column_clock_enable_0
+(9 1) Column buffer control bit: IORIGHT_half_column_clock_enable_0
+(9 2) Column buffer control bit: BIOLEFT_half_column_clock_enable_3
+(9 2) Column buffer control bit: IOLEFT_half_column_clock_enable_3
+(9 2) Column buffer control bit: IORIGHT_half_column_clock_enable_3
+(9 3) Column buffer control bit: BIOLEFT_half_column_clock_enable_2
+(9 3) Column buffer control bit: IOLEFT_half_column_clock_enable_2
+(9 3) Column buffer control bit: IORIGHT_half_column_clock_enable_2
+(9 4) Column buffer control bit: BIOLEFT_half_column_clock_enable_5
+(9 4) Column buffer control bit: IOLEFT_half_column_clock_enable_5
+(9 4) Column buffer control bit: IORIGHT_half_column_clock_enable_5
+(9 5) Column buffer control bit: BIOLEFT_half_column_clock_enable_4
+(9 5) Column buffer control bit: IOLEFT_half_column_clock_enable_4
+(9 5) Column buffer control bit: IORIGHT_half_column_clock_enable_4
+(9 6) Column buffer control bit: BIOLEFT_half_column_clock_enable_7
+(9 6) Column buffer control bit: IOLEFT_half_column_clock_enable_7
+(9 6) Column buffer control bit: IORIGHT_half_column_clock_enable_7
+(9 7) Column buffer control bit: BIOLEFT_half_column_clock_enable_6
+(9 7) Column buffer control bit: IOLEFT_half_column_clock_enable_6
+(9 7) Column buffer control bit: IORIGHT_half_column_clock_enable_6
diff --git a/icefuzz/cached_logic.txt b/icefuzz/cached_logic.txt
new file mode 100644
index 0000000..404124b
--- /dev/null
+++ b/icefuzz/cached_logic.txt
@@ -0,0 +1,4140 @@
+(0 0) Negative Clock bit
+(0 10) routing glb_netwk_2 <X> glb2local_2
+(0 10) routing glb_netwk_3 <X> glb2local_2
+(0 10) routing glb_netwk_6 <X> glb2local_2
+(0 10) routing glb_netwk_7 <X> glb2local_2
+(0 11) routing glb_netwk_1 <X> glb2local_2
+(0 11) routing glb_netwk_3 <X> glb2local_2
+(0 11) routing glb_netwk_5 <X> glb2local_2
+(0 11) routing glb_netwk_7 <X> glb2local_2
+(0 12) routing glb_netwk_2 <X> glb2local_3
+(0 12) routing glb_netwk_3 <X> glb2local_3
+(0 12) routing glb_netwk_6 <X> glb2local_3
+(0 12) routing glb_netwk_7 <X> glb2local_3
+(0 13) routing glb_netwk_1 <X> glb2local_3
+(0 13) routing glb_netwk_3 <X> glb2local_3
+(0 13) routing glb_netwk_5 <X> glb2local_3
+(0 13) routing glb_netwk_7 <X> glb2local_3
+(0 14) routing glb_netwk_4 <X> wire_logic_cluster/lc_7/s_r
+(0 14) routing glb_netwk_6 <X> wire_logic_cluster/lc_7/s_r
+(0 14) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/s_r
+(0 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/s_r
+(0 15) routing glb_netwk_2 <X> wire_logic_cluster/lc_7/s_r
+(0 15) routing glb_netwk_6 <X> wire_logic_cluster/lc_7/s_r
+(0 15) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/s_r
+(0 15) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/s_r
+(0 2) routing glb_netwk_2 <X> wire_logic_cluster/lc_7/clk
+(0 2) routing glb_netwk_3 <X> wire_logic_cluster/lc_7/clk
+(0 2) routing glb_netwk_6 <X> wire_logic_cluster/lc_7/clk
+(0 2) routing glb_netwk_7 <X> wire_logic_cluster/lc_7/clk
+(0 2) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_7/clk
+(0 2) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing glb_netwk_1 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing glb_netwk_3 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing glb_netwk_5 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing glb_netwk_7 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_7/clk
+(0 3) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/clk
+(0 4) routing glb_netwk_5 <X> wire_logic_cluster/lc_7/cen
+(0 4) routing glb_netwk_7 <X> wire_logic_cluster/lc_7/cen
+(0 4) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/cen
+(0 4) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/cen
+(0 5) routing glb_netwk_3 <X> wire_logic_cluster/lc_7/cen
+(0 5) routing glb_netwk_7 <X> wire_logic_cluster/lc_7/cen
+(0 5) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/cen
+(0 5) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/cen
+(0 6) routing glb_netwk_2 <X> glb2local_0
+(0 6) routing glb_netwk_3 <X> glb2local_0
+(0 6) routing glb_netwk_6 <X> glb2local_0
+(0 6) routing glb_netwk_7 <X> glb2local_0
+(0 7) routing glb_netwk_1 <X> glb2local_0
+(0 7) routing glb_netwk_3 <X> glb2local_0
+(0 7) routing glb_netwk_5 <X> glb2local_0
+(0 7) routing glb_netwk_7 <X> glb2local_0
+(0 8) routing glb_netwk_2 <X> glb2local_1
+(0 8) routing glb_netwk_3 <X> glb2local_1
+(0 8) routing glb_netwk_6 <X> glb2local_1
+(0 8) routing glb_netwk_7 <X> glb2local_1
+(0 9) routing glb_netwk_1 <X> glb2local_1
+(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_5 <X> glb2local_1
+(0 9) routing glb_netwk_7 <X> glb2local_1
+(1 0) Column buffer control bit: LH_colbuf_cntl_0
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2
+(1 11) routing glb_netwk_4 <X> glb2local_2
+(1 11) routing glb_netwk_5 <X> glb2local_2
+(1 11) routing glb_netwk_6 <X> glb2local_2
+(1 11) routing glb_netwk_7 <X> glb2local_2
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3
+(1 13) routing glb_netwk_4 <X> glb2local_3
+(1 13) routing glb_netwk_5 <X> glb2local_3
+(1 13) routing glb_netwk_6 <X> glb2local_3
+(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_logic_cluster/lc_7/s_r
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_logic_cluster/lc_7/s_r
+(1 15) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_7/s_r
+(1 15) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/s_r
+(1 15) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/s_r
+(1 15) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/s_r
+(1 2) routing glb_netwk_4 <X> wire_logic_cluster/lc_7/clk
+(1 2) routing glb_netwk_5 <X> wire_logic_cluster/lc_7/clk
+(1 2) routing glb_netwk_6 <X> wire_logic_cluster/lc_7/clk
+(1 2) routing glb_netwk_7 <X> wire_logic_cluster/lc_7/clk
+(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_l_4
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_logic_cluster/lc_7/cen
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_logic_cluster/lc_7/cen
+(1 5) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_7/cen
+(1 5) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/cen
+(1 5) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/cen
+(1 5) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/cen
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0
+(1 7) routing glb_netwk_4 <X> glb2local_0
+(1 7) routing glb_netwk_5 <X> glb2local_0
+(1 7) routing glb_netwk_6 <X> glb2local_0
+(1 7) routing glb_netwk_7 <X> glb2local_0
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
+(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_5 <X> glb2local_1
+(1 9) routing glb_netwk_6 <X> glb2local_1
+(1 9) routing glb_netwk_7 <X> glb2local_1
+(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(10 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(10 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(10 0) routing sp4_v_t_45 <X> sp4_h_r_1
+(10 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(10 1) routing sp4_h_r_8 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(10 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(10 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(10 10) routing sp4_v_b_2 <X> sp4_h_l_42
+(10 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(10 11) routing sp4_h_l_39 <X> sp4_v_t_42
+(10 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(10 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(10 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(10 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(10 12) routing sp4_v_t_40 <X> sp4_h_r_10
+(10 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(10 13) routing sp4_h_r_5 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(10 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(10 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(10 14) routing sp4_v_b_5 <X> sp4_h_l_47
+(10 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(10 15) routing sp4_h_l_40 <X> sp4_v_t_47
+(10 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(10 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(10 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(10 2) routing sp4_v_b_8 <X> sp4_h_l_36
+(10 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(10 3) routing sp4_h_l_45 <X> sp4_v_t_36
+(10 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(10 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(10 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(10 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(10 4) routing sp4_v_t_46 <X> sp4_h_r_4
+(10 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(10 5) routing sp4_h_r_11 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(10 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(10 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(10 6) routing sp4_v_b_11 <X> sp4_h_l_41
+(10 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(10 7) routing sp4_h_l_46 <X> sp4_v_t_41
+(10 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(10 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(10 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(10 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(10 8) routing sp4_v_t_39 <X> sp4_h_r_7
+(10 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(10 9) routing sp4_h_r_2 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_46 <X> sp4_v_b_7
+(11 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(11 0) routing sp4_h_r_9 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_46 <X> sp4_v_b_2
+(11 1) routing sp4_h_l_39 <X> sp4_h_r_2
+(11 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_2 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(11 10) routing sp4_h_l_38 <X> sp4_v_t_45
+(11 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_5 <X> sp4_v_t_45
+(11 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(11 11) routing sp4_h_r_8 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_45 <X> sp4_h_l_45
+(11 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(11 12) routing sp4_h_r_6 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_45 <X> sp4_v_b_11
+(11 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(11 13) routing sp4_h_l_46 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_11 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(11 14) routing sp4_h_l_43 <X> sp4_v_t_46
+(11 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_8 <X> sp4_v_t_46
+(11 15) routing sp4_h_r_11 <X> sp4_h_l_46
+(11 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_46 <X> sp4_h_l_46
+(11 2) routing sp4_h_l_44 <X> sp4_v_t_39
+(11 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_11 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(11 3) routing sp4_h_r_2 <X> sp4_h_l_39
+(11 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_39 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(11 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(11 4) routing sp4_h_r_0 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_39 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(11 5) routing sp4_h_l_40 <X> sp4_h_r_5
+(11 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_5 <X> sp4_h_r_5
+(11 6) routing sp4_h_l_37 <X> sp4_v_t_40
+(11 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_2 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(11 7) routing sp4_h_r_5 <X> sp4_h_l_40
+(11 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_40 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(11 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(11 8) routing sp4_h_r_3 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_40 <X> sp4_v_b_8
+(11 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(11 9) routing sp4_h_l_45 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 0) routing sp4_h_l_46 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_2 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_8 <X> sp4_h_r_2
+(12 0) routing sp4_v_t_39 <X> sp4_h_r_2
+(12 1) routing sp4_h_l_39 <X> sp4_v_b_2
+(12 1) routing sp4_h_l_45 <X> sp4_v_b_2
+(12 1) routing sp4_h_r_2 <X> sp4_v_b_2
+(12 1) routing sp4_v_t_46 <X> sp4_v_b_2
+(12 10) routing sp4_h_r_5 <X> sp4_h_l_45
+(12 10) routing sp4_v_b_8 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_39 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_45 <X> sp4_h_l_45
+(12 11) routing sp4_h_l_45 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_2 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_8 <X> sp4_v_t_45
+(12 11) routing sp4_v_b_5 <X> sp4_v_t_45
+(12 12) routing sp4_h_l_45 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_11 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_5 <X> sp4_h_r_11
+(12 12) routing sp4_v_t_46 <X> sp4_h_r_11
+(12 13) routing sp4_h_l_40 <X> sp4_v_b_11
+(12 13) routing sp4_h_l_46 <X> sp4_v_b_11
+(12 13) routing sp4_h_r_11 <X> sp4_v_b_11
+(12 13) routing sp4_v_t_45 <X> sp4_v_b_11
+(12 14) routing sp4_h_r_8 <X> sp4_h_l_46
+(12 14) routing sp4_v_b_11 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_40 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_46 <X> sp4_h_l_46
+(12 15) routing sp4_h_l_46 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_11 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_5 <X> sp4_v_t_46
+(12 15) routing sp4_v_b_8 <X> sp4_v_t_46
+(12 2) routing sp4_h_r_11 <X> sp4_h_l_39
+(12 2) routing sp4_v_b_2 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_39 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_45 <X> sp4_h_l_39
+(12 3) routing sp4_h_l_39 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_2 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_8 <X> sp4_v_t_39
+(12 3) routing sp4_v_b_11 <X> sp4_v_t_39
+(12 4) routing sp4_h_l_39 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_11 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_5 <X> sp4_h_r_5
+(12 4) routing sp4_v_t_40 <X> sp4_h_r_5
+(12 5) routing sp4_h_l_40 <X> sp4_v_b_5
+(12 5) routing sp4_h_l_46 <X> sp4_v_b_5
+(12 5) routing sp4_h_r_5 <X> sp4_v_b_5
+(12 5) routing sp4_v_t_39 <X> sp4_v_b_5
+(12 6) routing sp4_h_r_2 <X> sp4_h_l_40
+(12 6) routing sp4_v_b_5 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_40 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_46 <X> sp4_h_l_40
+(12 7) routing sp4_h_l_40 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_11 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_5 <X> sp4_v_t_40
+(12 7) routing sp4_v_b_2 <X> sp4_v_t_40
+(12 8) routing sp4_h_l_40 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_2 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 8) routing sp4_v_t_45 <X> sp4_h_r_8
+(12 9) routing sp4_h_l_39 <X> sp4_v_b_8
+(12 9) routing sp4_h_l_45 <X> sp4_v_b_8
+(12 9) routing sp4_h_r_8 <X> sp4_v_b_8
+(12 9) routing sp4_v_t_40 <X> sp4_v_b_8
+(13 0) routing sp4_h_l_39 <X> sp4_v_b_2
+(13 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_39 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(13 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(13 1) routing sp4_h_l_46 <X> sp4_h_r_2
+(13 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(13 1) routing sp4_v_t_44 <X> sp4_h_r_2
+(13 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(13 10) routing sp4_h_r_8 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_8 <X> sp4_v_t_45
+(13 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(13 11) routing sp4_h_r_5 <X> sp4_h_l_45
+(13 11) routing sp4_v_b_3 <X> sp4_h_l_45
+(13 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(13 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(13 12) routing sp4_h_l_46 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_46 <X> sp4_v_b_11
+(13 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(13 13) routing sp4_h_l_45 <X> sp4_h_r_11
+(13 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(13 13) routing sp4_v_t_43 <X> sp4_h_r_11
+(13 14) routing sp4_h_r_11 <X> sp4_v_t_46
+(13 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_11 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(13 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(13 15) routing sp4_h_r_8 <X> sp4_h_l_46
+(13 15) routing sp4_v_b_6 <X> sp4_h_l_46
+(13 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(13 2) routing sp4_h_r_2 <X> sp4_v_t_39
+(13 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_2 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(13 3) routing sp4_h_r_11 <X> sp4_h_l_39
+(13 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(13 3) routing sp4_v_b_9 <X> sp4_h_l_39
+(13 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(13 4) routing sp4_h_l_40 <X> sp4_v_b_5
+(13 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_40 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(13 5) routing sp4_h_l_39 <X> sp4_h_r_5
+(13 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(13 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(13 5) routing sp4_v_t_37 <X> sp4_h_r_5
+(13 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(13 6) routing sp4_h_r_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(13 7) routing sp4_h_r_2 <X> sp4_h_l_40
+(13 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(13 7) routing sp4_v_b_0 <X> sp4_h_l_40
+(13 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(13 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(13 8) routing sp4_h_l_45 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_45 <X> sp4_v_b_8
+(13 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(13 9) routing sp4_h_l_40 <X> sp4_h_r_8
+(13 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(13 9) routing sp4_v_t_38 <X> sp4_h_r_8
+(14 0) routing bnr_op_0 <X> lc_trk_g0_0
+(14 0) routing lft_op_0 <X> lc_trk_g0_0
+(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 0) routing wire_logic_cluster/lc_0/out <X> lc_trk_g0_0
+(14 1) routing bnr_op_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0
+(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing top_op_0 <X> lc_trk_g0_0
+(14 10) routing bnl_op_4 <X> lc_trk_g2_4
+(14 10) routing rgt_op_4 <X> lc_trk_g2_4
+(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 10) routing sp4_v_b_36 <X> lc_trk_g2_4
+(14 10) routing sp4_v_t_17 <X> lc_trk_g2_4
+(14 10) routing wire_logic_cluster/lc_4/out <X> lc_trk_g2_4
+(14 11) routing bnl_op_4 <X> lc_trk_g2_4
+(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4
+(14 11) routing sp4_v_b_36 <X> lc_trk_g2_4
+(14 11) routing tnl_op_4 <X> lc_trk_g2_4
+(14 12) routing bnl_op_0 <X> lc_trk_g3_0
+(14 12) routing rgt_op_0 <X> lc_trk_g3_0
+(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0
+(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 12) routing sp4_v_b_24 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 12) routing wire_logic_cluster/lc_0/out <X> lc_trk_g3_0
+(14 13) routing bnl_op_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0
+(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 13) routing tnl_op_0 <X> lc_trk_g3_0
+(14 14) routing bnl_op_4 <X> lc_trk_g3_4
+(14 14) routing rgt_op_4 <X> lc_trk_g3_4
+(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 14) routing sp4_v_b_36 <X> lc_trk_g3_4
+(14 14) routing sp4_v_t_17 <X> lc_trk_g3_4
+(14 14) routing wire_logic_cluster/lc_4/out <X> lc_trk_g3_4
+(14 15) routing bnl_op_4 <X> lc_trk_g3_4
+(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4
+(14 15) routing sp4_v_b_36 <X> lc_trk_g3_4
+(14 15) routing tnl_op_4 <X> lc_trk_g3_4
+(14 2) routing bnr_op_4 <X> lc_trk_g0_4
+(14 2) routing lft_op_4 <X> lc_trk_g0_4
+(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_1 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4
+(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 2) routing wire_logic_cluster/lc_4/out <X> lc_trk_g0_4
+(14 3) routing bnr_op_4 <X> lc_trk_g0_4
+(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4
+(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 3) routing top_op_4 <X> lc_trk_g0_4
+(14 4) routing bnr_op_0 <X> lc_trk_g1_0
+(14 4) routing lft_op_0 <X> lc_trk_g1_0
+(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 4) routing wire_logic_cluster/lc_0/out <X> lc_trk_g1_0
+(14 5) routing bnr_op_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0
+(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing top_op_0 <X> lc_trk_g1_0
+(14 6) routing bnr_op_4 <X> lc_trk_g1_4
+(14 6) routing lft_op_4 <X> lc_trk_g1_4
+(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_1 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4
+(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 6) routing wire_logic_cluster/lc_4/out <X> lc_trk_g1_4
+(14 7) routing bnr_op_4 <X> lc_trk_g1_4
+(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4
+(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 7) routing top_op_4 <X> lc_trk_g1_4
+(14 8) routing bnl_op_0 <X> lc_trk_g2_0
+(14 8) routing rgt_op_0 <X> lc_trk_g2_0
+(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0
+(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 8) routing sp4_v_b_24 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 8) routing wire_logic_cluster/lc_0/out <X> lc_trk_g2_0
+(14 9) routing bnl_op_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0
+(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 0) routing bot_op_1 <X> lc_trk_g0_1
+(15 0) routing lft_op_1 <X> lc_trk_g0_1
+(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_l_4 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(15 0) routing top_op_1 <X> lc_trk_g0_1
+(15 1) routing bot_op_0 <X> lc_trk_g0_0
+(15 1) routing lft_op_0 <X> lc_trk_g0_0
+(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(15 1) routing sp4_v_t_5 <X> lc_trk_g0_0
+(15 1) routing top_op_0 <X> lc_trk_g0_0
+(15 10) routing rgt_op_5 <X> lc_trk_g2_5
+(15 10) routing sp12_v_t_2 <X> lc_trk_g2_5
+(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(15 10) routing sp4_h_l_24 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(15 10) routing sp4_v_t_32 <X> lc_trk_g2_5
+(15 10) routing tnl_op_5 <X> lc_trk_g2_5
+(15 10) routing tnr_op_5 <X> lc_trk_g2_5
+(15 11) routing rgt_op_4 <X> lc_trk_g2_4
+(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(15 11) routing tnl_op_4 <X> lc_trk_g2_4
+(15 11) routing tnr_op_4 <X> lc_trk_g2_4
+(15 12) routing rgt_op_1 <X> lc_trk_g3_1
+(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_41 <X> lc_trk_g3_1
+(15 12) routing sp4_v_t_28 <X> lc_trk_g3_1
+(15 12) routing tnl_op_1 <X> lc_trk_g3_1
+(15 12) routing tnr_op_1 <X> lc_trk_g3_1
+(15 13) routing rgt_op_0 <X> lc_trk_g3_0
+(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(15 13) routing sp4_v_t_29 <X> lc_trk_g3_0
+(15 13) routing tnl_op_0 <X> lc_trk_g3_0
+(15 13) routing tnr_op_0 <X> lc_trk_g3_0
+(15 14) routing rgt_op_5 <X> lc_trk_g3_5
+(15 14) routing sp12_v_t_2 <X> lc_trk_g3_5
+(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(15 14) routing sp4_h_l_24 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(15 14) routing sp4_v_t_32 <X> lc_trk_g3_5
+(15 14) routing tnl_op_5 <X> lc_trk_g3_5
+(15 14) routing tnr_op_5 <X> lc_trk_g3_5
+(15 15) routing rgt_op_4 <X> lc_trk_g3_4
+(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(15 15) routing tnl_op_4 <X> lc_trk_g3_4
+(15 15) routing tnr_op_4 <X> lc_trk_g3_4
+(15 2) routing bot_op_5 <X> lc_trk_g0_5
+(15 2) routing lft_op_5 <X> lc_trk_g0_5
+(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_v_b_21 <X> lc_trk_g0_5
+(15 2) routing top_op_5 <X> lc_trk_g0_5
+(15 3) routing bot_op_4 <X> lc_trk_g0_4
+(15 3) routing lft_op_4 <X> lc_trk_g0_4
+(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(15 3) routing sp4_v_t_9 <X> lc_trk_g0_4
+(15 3) routing top_op_4 <X> lc_trk_g0_4
+(15 4) routing bot_op_1 <X> lc_trk_g1_1
+(15 4) routing lft_op_1 <X> lc_trk_g1_1
+(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_l_4 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(15 4) routing top_op_1 <X> lc_trk_g1_1
+(15 5) routing bot_op_0 <X> lc_trk_g1_0
+(15 5) routing lft_op_0 <X> lc_trk_g1_0
+(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(15 5) routing sp4_v_t_5 <X> lc_trk_g1_0
+(15 5) routing top_op_0 <X> lc_trk_g1_0
+(15 6) routing bot_op_5 <X> lc_trk_g1_5
+(15 6) routing lft_op_5 <X> lc_trk_g1_5
+(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_v_b_21 <X> lc_trk_g1_5
+(15 6) routing top_op_5 <X> lc_trk_g1_5
+(15 7) routing bot_op_4 <X> lc_trk_g1_4
+(15 7) routing lft_op_4 <X> lc_trk_g1_4
+(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(15 7) routing sp4_v_t_9 <X> lc_trk_g1_4
+(15 7) routing top_op_4 <X> lc_trk_g1_4
+(15 8) routing rgt_op_1 <X> lc_trk_g2_1
+(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_41 <X> lc_trk_g2_1
+(15 8) routing sp4_v_t_28 <X> lc_trk_g2_1
+(15 8) routing tnl_op_1 <X> lc_trk_g2_1
+(15 8) routing tnr_op_1 <X> lc_trk_g2_1
+(15 9) routing rgt_op_0 <X> lc_trk_g2_0
+(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(15 9) routing sp4_v_t_29 <X> lc_trk_g2_0
+(15 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 9) routing tnr_op_0 <X> lc_trk_g2_0
+(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1
+(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_h_l_4 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_t_5 <X> lc_trk_g0_0
+(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5
+(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5
+(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(16 10) routing sp4_h_l_24 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(16 10) routing sp4_v_t_16 <X> lc_trk_g2_5
+(16 10) routing sp4_v_t_32 <X> lc_trk_g2_5
+(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4
+(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_36 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_17 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1
+(16 12) routing sp12_v_t_6 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_41 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(16 12) routing sp4_v_t_12 <X> lc_trk_g3_1
+(16 12) routing sp4_v_t_28 <X> lc_trk_g3_1
+(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(16 13) routing sp12_v_b_8 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_24 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_29 <X> lc_trk_g3_0
+(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5
+(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5
+(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(16 14) routing sp4_h_l_24 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(16 14) routing sp4_v_t_16 <X> lc_trk_g3_5
+(16 14) routing sp4_v_t_32 <X> lc_trk_g3_5
+(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4
+(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_36 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_17 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5
+(16 2) routing sp12_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_21 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(16 3) routing sp4_v_t_9 <X> lc_trk_g0_4
+(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1
+(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_h_l_4 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_t_5 <X> lc_trk_g1_0
+(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5
+(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_21 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(16 7) routing sp4_v_t_9 <X> lc_trk_g1_4
+(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1
+(16 8) routing sp12_v_t_6 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_41 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(16 8) routing sp4_v_t_12 <X> lc_trk_g2_1
+(16 8) routing sp4_v_t_28 <X> lc_trk_g2_1
+(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(16 9) routing sp12_v_b_8 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_24 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_29 <X> lc_trk_g2_0
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bot_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_l_4 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => top_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g0_1
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g0_0
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_2 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_32 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g2_5
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g2_4
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_6 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g3_1
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g3_0
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_2 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_32 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g3_5
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g3_4
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bot_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => top_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g0_5
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g0_4
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bot_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_l_4 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => top_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g1_1
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g1_0
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bot_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => top_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g1_5
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g1_4
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_6 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g2_1
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g2_0
+(18 0) routing bnr_op_1 <X> lc_trk_g0_1
+(18 0) routing lft_op_1 <X> lc_trk_g0_1
+(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 0) routing sp4_h_l_4 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 0) routing wire_logic_cluster/lc_1/out <X> lc_trk_g0_1
+(18 1) routing bnr_op_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_l_4 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1
+(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 1) routing top_op_1 <X> lc_trk_g0_1
+(18 10) routing bnl_op_5 <X> lc_trk_g2_5
+(18 10) routing rgt_op_5 <X> lc_trk_g2_5
+(18 10) routing sp12_v_t_2 <X> lc_trk_g2_5
+(18 10) routing sp4_h_l_24 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 10) routing sp4_v_t_16 <X> lc_trk_g2_5
+(18 10) routing wire_logic_cluster/lc_5/out <X> lc_trk_g2_5
+(18 11) routing bnl_op_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5
+(18 11) routing sp12_v_t_2 <X> lc_trk_g2_5
+(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5
+(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 11) routing tnl_op_5 <X> lc_trk_g2_5
+(18 12) routing bnl_op_1 <X> lc_trk_g3_1
+(18 12) routing rgt_op_1 <X> lc_trk_g3_1
+(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(18 12) routing sp4_h_r_41 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 12) routing sp4_v_t_12 <X> lc_trk_g3_1
+(18 12) routing wire_logic_cluster/lc_1/out <X> lc_trk_g3_1
+(18 13) routing bnl_op_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_41 <X> lc_trk_g3_1
+(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1
+(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 13) routing tnl_op_1 <X> lc_trk_g3_1
+(18 14) routing bnl_op_5 <X> lc_trk_g3_5
+(18 14) routing rgt_op_5 <X> lc_trk_g3_5
+(18 14) routing sp12_v_t_2 <X> lc_trk_g3_5
+(18 14) routing sp4_h_l_24 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 14) routing sp4_v_t_16 <X> lc_trk_g3_5
+(18 14) routing wire_logic_cluster/lc_5/out <X> lc_trk_g3_5
+(18 15) routing bnl_op_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5
+(18 15) routing sp12_v_t_2 <X> lc_trk_g3_5
+(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5
+(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 15) routing tnl_op_5 <X> lc_trk_g3_5
+(18 2) routing bnr_op_5 <X> lc_trk_g0_5
+(18 2) routing lft_op_5 <X> lc_trk_g0_5
+(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(18 2) routing wire_logic_cluster/lc_5/out <X> lc_trk_g0_5
+(18 3) routing bnr_op_5 <X> lc_trk_g0_5
+(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5
+(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5
+(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 3) routing top_op_5 <X> lc_trk_g0_5
+(18 4) routing bnr_op_1 <X> lc_trk_g1_1
+(18 4) routing lft_op_1 <X> lc_trk_g1_1
+(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 4) routing sp4_h_l_4 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 4) routing wire_logic_cluster/lc_1/out <X> lc_trk_g1_1
+(18 5) routing bnr_op_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_l_4 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1
+(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 5) routing top_op_1 <X> lc_trk_g1_1
+(18 6) routing bnr_op_5 <X> lc_trk_g1_5
+(18 6) routing lft_op_5 <X> lc_trk_g1_5
+(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(18 6) routing wire_logic_cluster/lc_5/out <X> lc_trk_g1_5
+(18 7) routing bnr_op_5 <X> lc_trk_g1_5
+(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5
+(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5
+(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 7) routing top_op_5 <X> lc_trk_g1_5
+(18 8) routing bnl_op_1 <X> lc_trk_g2_1
+(18 8) routing rgt_op_1 <X> lc_trk_g2_1
+(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(18 8) routing sp4_h_r_41 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 8) routing sp4_v_t_12 <X> lc_trk_g2_1
+(18 8) routing wire_logic_cluster/lc_1/out <X> lc_trk_g2_1
+(18 9) routing bnl_op_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_41 <X> lc_trk_g2_1
+(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1
+(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 9) routing tnl_op_1 <X> lc_trk_g2_1
+(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13
+(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1
+(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23
+(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22
+(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13
+(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1
+(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2
+(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_r_14
+(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_b_15
+(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_t_2 sp4_v_t_3
+(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17
+(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_t_6 sp4_v_t_5
+(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19
+(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18
+(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_b_21
+(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9
+(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5
+(2 1) Column buffer control bit: LH_colbuf_cntl_1
+(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21
+(2 11) Column buffer control bit: LH_colbuf_cntl_5
+(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11
+(2 13) Column buffer control bit: LH_colbuf_cntl_6
+(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10
+(2 15) Column buffer control bit: LH_colbuf_cntl_7
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_logic_cluster/lc_7/clk
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_logic_cluster/lc_7/clk
+(2 3) routing lc_trk_g0_0 <X> wire_logic_cluster/lc_7/clk
+(2 3) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_7/clk
+(2 3) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_7/clk
+(2 3) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/clk
+(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7
+(2 5) Column buffer control bit: LH_colbuf_cntl_2
+(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19
+(2 7) Column buffer control bit: LH_colbuf_cntl_3
+(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_l_9
+(2 9) Column buffer control bit: LH_colbuf_cntl_4
+(21 0) routing bnr_op_3 <X> lc_trk_g0_3
+(21 0) routing lft_op_3 <X> lc_trk_g0_3
+(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(21 0) routing wire_logic_cluster/lc_3/out <X> lc_trk_g0_3
+(21 1) routing bnr_op_3 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3
+(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3
+(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 1) routing top_op_3 <X> lc_trk_g0_3
+(21 10) routing bnl_op_7 <X> lc_trk_g2_7
+(21 10) routing rgt_op_7 <X> lc_trk_g2_7
+(21 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 10) routing sp4_h_l_34 <X> lc_trk_g2_7
+(21 10) routing sp4_h_r_39 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 10) routing wire_logic_cluster/lc_7/out <X> lc_trk_g2_7
+(21 11) routing bnl_op_7 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 11) routing sp4_h_l_34 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_31 <X> lc_trk_g2_7
+(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7
+(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing tnl_op_7 <X> lc_trk_g2_7
+(21 12) routing bnl_op_3 <X> lc_trk_g3_3
+(21 12) routing rgt_op_3 <X> lc_trk_g3_3
+(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 12) routing wire_logic_cluster/lc_3/out <X> lc_trk_g3_3
+(21 13) routing bnl_op_3 <X> lc_trk_g3_3
+(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3
+(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3
+(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 13) routing tnl_op_3 <X> lc_trk_g3_3
+(21 14) routing bnl_op_7 <X> lc_trk_g3_7
+(21 14) routing rgt_op_7 <X> lc_trk_g3_7
+(21 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 14) routing sp4_h_l_34 <X> lc_trk_g3_7
+(21 14) routing sp4_h_r_39 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 14) routing wire_logic_cluster/lc_7/out <X> lc_trk_g3_7
+(21 15) routing bnl_op_7 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 15) routing sp4_h_l_34 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7
+(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7
+(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing tnl_op_7 <X> lc_trk_g3_7
+(21 2) routing bnr_op_7 <X> lc_trk_g0_7
+(21 2) routing lft_op_7 <X> lc_trk_g0_7
+(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_15 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(21 2) routing wire_logic_cluster/lc_7/out <X> lc_trk_g0_7
+(21 3) routing bnr_op_7 <X> lc_trk_g0_7
+(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7
+(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7
+(21 3) routing sp4_v_b_15 <X> lc_trk_g0_7
+(21 3) routing top_op_7 <X> lc_trk_g0_7
+(21 4) routing bnr_op_3 <X> lc_trk_g1_3
+(21 4) routing lft_op_3 <X> lc_trk_g1_3
+(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(21 4) routing wire_logic_cluster/lc_3/out <X> lc_trk_g1_3
+(21 5) routing bnr_op_3 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3
+(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3
+(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 5) routing top_op_3 <X> lc_trk_g1_3
+(21 6) routing bnr_op_7 <X> lc_trk_g1_7
+(21 6) routing lft_op_7 <X> lc_trk_g1_7
+(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_15 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(21 6) routing wire_logic_cluster/lc_7/out <X> lc_trk_g1_7
+(21 7) routing bnr_op_7 <X> lc_trk_g1_7
+(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7
+(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7
+(21 7) routing sp4_v_b_15 <X> lc_trk_g1_7
+(21 7) routing top_op_7 <X> lc_trk_g1_7
+(21 8) routing bnl_op_3 <X> lc_trk_g2_3
+(21 8) routing rgt_op_3 <X> lc_trk_g2_3
+(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 8) routing wire_logic_cluster/lc_3/out <X> lc_trk_g2_3
+(21 9) routing bnl_op_3 <X> lc_trk_g2_3
+(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3
+(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3
+(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 9) routing tnl_op_3 <X> lc_trk_g2_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bot_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => top_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g0_3
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g0_2
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g2_7
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g2_6
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g3_3
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g3_2
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g3_7
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g3_6
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bot_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => top_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g0_7
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g0_6
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bot_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => top_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g1_3
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g1_2
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bot_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => top_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g1_7
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g1_6
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g2_3
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g2_2
+(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3
+(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_18 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2
+(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7
+(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_34 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_39 <X> lc_trk_g2_7
+(23 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6
+(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_38 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3
+(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(23 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2
+(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7
+(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_34 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_39 <X> lc_trk_g3_7
+(23 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6
+(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_38 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7
+(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_15 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(23 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_14 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_t_3 <X> lc_trk_g0_6
+(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3
+(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(23 5) routing sp12_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_18 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2
+(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7
+(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_15 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_14 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_t_3 <X> lc_trk_g1_6
+(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3
+(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(23 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2
+(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(24 0) routing bot_op_3 <X> lc_trk_g0_3
+(24 0) routing lft_op_3 <X> lc_trk_g0_3
+(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(24 0) routing top_op_3 <X> lc_trk_g0_3
+(24 1) routing bot_op_2 <X> lc_trk_g0_2
+(24 1) routing lft_op_2 <X> lc_trk_g0_2
+(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_v_b_18 <X> lc_trk_g0_2
+(24 1) routing top_op_2 <X> lc_trk_g0_2
+(24 10) routing rgt_op_7 <X> lc_trk_g2_7
+(24 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_34 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_39 <X> lc_trk_g2_7
+(24 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(24 10) routing tnl_op_7 <X> lc_trk_g2_7
+(24 10) routing tnr_op_7 <X> lc_trk_g2_7
+(24 11) routing rgt_op_6 <X> lc_trk_g2_6
+(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_38 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(24 11) routing tnl_op_6 <X> lc_trk_g2_6
+(24 11) routing tnr_op_6 <X> lc_trk_g2_6
+(24 12) routing rgt_op_3 <X> lc_trk_g3_3
+(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(24 12) routing tnl_op_3 <X> lc_trk_g3_3
+(24 12) routing tnr_op_3 <X> lc_trk_g3_3
+(24 13) routing rgt_op_2 <X> lc_trk_g3_2
+(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(24 13) routing sp4_v_b_42 <X> lc_trk_g3_2
+(24 13) routing tnl_op_2 <X> lc_trk_g3_2
+(24 13) routing tnr_op_2 <X> lc_trk_g3_2
+(24 14) routing rgt_op_7 <X> lc_trk_g3_7
+(24 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_34 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_39 <X> lc_trk_g3_7
+(24 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(24 14) routing tnl_op_7 <X> lc_trk_g3_7
+(24 14) routing tnr_op_7 <X> lc_trk_g3_7
+(24 15) routing rgt_op_6 <X> lc_trk_g3_6
+(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_38 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(24 15) routing tnl_op_6 <X> lc_trk_g3_6
+(24 15) routing tnr_op_6 <X> lc_trk_g3_6
+(24 2) routing bot_op_7 <X> lc_trk_g0_7
+(24 2) routing lft_op_7 <X> lc_trk_g0_7
+(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(24 2) routing top_op_7 <X> lc_trk_g0_7
+(24 3) routing bot_op_6 <X> lc_trk_g0_6
+(24 3) routing lft_op_6 <X> lc_trk_g0_6
+(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_14 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(24 3) routing top_op_6 <X> lc_trk_g0_6
+(24 4) routing bot_op_3 <X> lc_trk_g1_3
+(24 4) routing lft_op_3 <X> lc_trk_g1_3
+(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(24 4) routing top_op_3 <X> lc_trk_g1_3
+(24 5) routing bot_op_2 <X> lc_trk_g1_2
+(24 5) routing lft_op_2 <X> lc_trk_g1_2
+(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_v_b_18 <X> lc_trk_g1_2
+(24 5) routing top_op_2 <X> lc_trk_g1_2
+(24 6) routing bot_op_7 <X> lc_trk_g1_7
+(24 6) routing lft_op_7 <X> lc_trk_g1_7
+(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(24 6) routing top_op_7 <X> lc_trk_g1_7
+(24 7) routing bot_op_6 <X> lc_trk_g1_6
+(24 7) routing lft_op_6 <X> lc_trk_g1_6
+(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_14 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(24 7) routing top_op_6 <X> lc_trk_g1_6
+(24 8) routing rgt_op_3 <X> lc_trk_g2_3
+(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(24 8) routing tnl_op_3 <X> lc_trk_g2_3
+(24 8) routing tnr_op_3 <X> lc_trk_g2_3
+(24 9) routing rgt_op_2 <X> lc_trk_g2_2
+(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(24 9) routing sp4_v_b_42 <X> lc_trk_g2_2
+(24 9) routing tnl_op_2 <X> lc_trk_g2_2
+(24 9) routing tnr_op_2 <X> lc_trk_g2_2
+(25 0) routing bnr_op_2 <X> lc_trk_g0_2
+(25 0) routing lft_op_2 <X> lc_trk_g0_2
+(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2
+(25 0) routing wire_logic_cluster/lc_2/out <X> lc_trk_g0_2
+(25 1) routing bnr_op_2 <X> lc_trk_g0_2
+(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2
+(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 1) routing top_op_2 <X> lc_trk_g0_2
+(25 10) routing bnl_op_6 <X> lc_trk_g2_6
+(25 10) routing rgt_op_6 <X> lc_trk_g2_6
+(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_38 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 10) routing wire_logic_cluster/lc_6/out <X> lc_trk_g2_6
+(25 11) routing bnl_op_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6
+(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 11) routing tnl_op_6 <X> lc_trk_g2_6
+(25 12) routing bnl_op_2 <X> lc_trk_g3_2
+(25 12) routing rgt_op_2 <X> lc_trk_g3_2
+(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2
+(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 12) routing wire_logic_cluster/lc_2/out <X> lc_trk_g3_2
+(25 13) routing bnl_op_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2
+(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 13) routing tnl_op_2 <X> lc_trk_g3_2
+(25 14) routing bnl_op_6 <X> lc_trk_g3_6
+(25 14) routing rgt_op_6 <X> lc_trk_g3_6
+(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_38 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 14) routing wire_logic_cluster/lc_6/out <X> lc_trk_g3_6
+(25 15) routing bnl_op_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6
+(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 15) routing tnl_op_6 <X> lc_trk_g3_6
+(25 2) routing bnr_op_6 <X> lc_trk_g0_6
+(25 2) routing lft_op_6 <X> lc_trk_g0_6
+(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 2) routing sp4_h_r_14 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6
+(25 2) routing sp4_v_t_3 <X> lc_trk_g0_6
+(25 2) routing wire_logic_cluster/lc_6/out <X> lc_trk_g0_6
+(25 3) routing bnr_op_6 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6
+(25 3) routing sp4_v_t_3 <X> lc_trk_g0_6
+(25 3) routing top_op_6 <X> lc_trk_g0_6
+(25 4) routing bnr_op_2 <X> lc_trk_g1_2
+(25 4) routing lft_op_2 <X> lc_trk_g1_2
+(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2
+(25 4) routing wire_logic_cluster/lc_2/out <X> lc_trk_g1_2
+(25 5) routing bnr_op_2 <X> lc_trk_g1_2
+(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2
+(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 5) routing top_op_2 <X> lc_trk_g1_2
+(25 6) routing bnr_op_6 <X> lc_trk_g1_6
+(25 6) routing lft_op_6 <X> lc_trk_g1_6
+(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 6) routing sp4_h_r_14 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6
+(25 6) routing sp4_v_t_3 <X> lc_trk_g1_6
+(25 6) routing wire_logic_cluster/lc_6/out <X> lc_trk_g1_6
+(25 7) routing bnr_op_6 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6
+(25 7) routing sp4_v_t_3 <X> lc_trk_g1_6
+(25 7) routing top_op_6 <X> lc_trk_g1_6
+(25 8) routing bnl_op_2 <X> lc_trk_g2_2
+(25 8) routing rgt_op_2 <X> lc_trk_g2_2
+(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2
+(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 8) routing wire_logic_cluster/lc_2/out <X> lc_trk_g2_2
+(25 9) routing bnl_op_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2
+(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 9) routing tnl_op_2 <X> lc_trk_g2_2
+(26 0) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_0/in_0
+(26 0) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_0/in_0
+(26 1) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_0/in_0
+(26 10) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_5/in_0
+(26 10) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_5/in_0
+(26 11) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_5/in_0
+(26 12) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_6/in_0
+(26 12) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_6/in_0
+(26 13) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_6/in_0
+(26 14) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_7/in_0
+(26 14) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_7/in_0
+(26 15) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_7/in_0
+(26 2) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_1/in_0
+(26 2) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_1/in_0
+(26 3) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_1/in_0
+(26 4) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_2/in_0
+(26 4) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_2/in_0
+(26 5) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_2/in_0
+(26 6) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_3/in_0
+(26 6) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_3/in_0
+(26 7) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_3/in_0
+(26 8) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_4/in_0
+(26 8) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_4/in_0
+(26 9) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_4/in_0
+(27 0) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_1
+(27 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_1
+(27 1) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_0/in_0
+(27 1) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_0/in_0
+(27 10) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_1
+(27 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_1
+(27 11) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_5/in_0
+(27 11) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_5/in_0
+(27 12) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_1
+(27 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_1
+(27 13) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_6/in_0
+(27 13) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_6/in_0
+(27 14) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_1
+(27 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_1
+(27 15) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_7/in_0
+(27 15) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_7/in_0
+(27 2) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_1
+(27 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_1
+(27 3) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_1/in_0
+(27 3) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_1/in_0
+(27 4) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_1
+(27 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_1
+(27 5) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_2/in_0
+(27 5) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_2/in_0
+(27 6) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_1
+(27 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_1
+(27 7) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_3/in_0
+(27 7) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_3/in_0
+(27 8) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_1
+(27 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_1
+(27 9) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_4/in_0
+(27 9) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_4/in_0
+(28 0) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_1
+(28 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_1
+(28 1) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_0/in_0
+(28 1) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_0/in_0
+(28 10) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_1
+(28 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_1
+(28 11) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_5/in_0
+(28 11) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_5/in_0
+(28 12) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_1
+(28 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_1
+(28 13) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_6/in_0
+(28 13) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_6/in_0
+(28 14) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_1
+(28 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_1
+(28 15) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_7/in_0
+(28 15) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_7/in_0
+(28 2) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_1
+(28 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_1
+(28 3) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_1/in_0
+(28 3) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_1/in_0
+(28 4) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_1
+(28 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_1
+(28 5) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_2/in_0
+(28 5) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_2/in_0
+(28 6) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_1
+(28 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_1
+(28 7) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_3/in_0
+(28 7) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_3/in_0
+(28 8) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_1
+(28 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_1
+(28 9) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_4/in_0
+(28 9) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_4/in_0
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_1 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_3 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_5 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_7 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_0 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_2 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_4 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_6 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_1 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_3 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_5 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_7 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_0 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_2 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_4 wire_logic_cluster/lc_0/in_1
+(29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_6 wire_logic_cluster/lc_0/in_1
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_0 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_2 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_4 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_6 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_1 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_3 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_5 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_7 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_0 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_2 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_4 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_6 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_1 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_3 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_5 wire_logic_cluster/lc_0/in_0
+(29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_7 wire_logic_cluster/lc_0/in_0
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_0 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_2 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_4 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_6 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_1 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_3 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_5 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_7 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_0 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_2 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_4 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_6 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_1 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_3 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_5 wire_logic_cluster/lc_5/in_1
+(29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_7 wire_logic_cluster/lc_5/in_1
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_1 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_3 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_5 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_7 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_0 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_2 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_4 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_6 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_1 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_3 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_5 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_7 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_0 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_2 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_4 wire_logic_cluster/lc_5/in_0
+(29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_6 wire_logic_cluster/lc_5/in_0
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_1 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_3 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_5 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_7 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_0 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_2 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_4 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_6 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_1 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_3 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_5 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_7 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_0 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_2 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_4 wire_logic_cluster/lc_6/in_1
+(29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_6 wire_logic_cluster/lc_6/in_1
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_0 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_2 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_4 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_6 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_1 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_3 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_5 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_7 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_0 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_2 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_4 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_6 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_1 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_3 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_5 wire_logic_cluster/lc_6/in_0
+(29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_7 wire_logic_cluster/lc_6/in_0
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_0 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_2 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_4 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_6 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_1 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_3 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_5 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_7 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_0 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_2 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_4 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_6 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_1 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_3 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_5 wire_logic_cluster/lc_7/in_1
+(29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_7 wire_logic_cluster/lc_7/in_1
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_1 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_3 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_5 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_7 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_0 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_2 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_4 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_6 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_1 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_3 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_5 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_7 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_0 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_2 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_4 wire_logic_cluster/lc_7/in_0
+(29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_6 wire_logic_cluster/lc_7/in_0
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_0 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_2 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_4 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_6 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_1 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_3 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_5 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_7 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_0 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_2 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_4 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_6 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_1 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_3 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_5 wire_logic_cluster/lc_1/in_1
+(29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_7 wire_logic_cluster/lc_1/in_1
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_1 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_3 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_5 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_7 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_0 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_2 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_4 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_6 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_1 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_3 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_5 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_7 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_0 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_2 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_4 wire_logic_cluster/lc_1/in_0
+(29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_6 wire_logic_cluster/lc_1/in_0
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_1 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_3 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_5 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_7 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_0 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_2 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_4 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_6 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_1 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_3 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_5 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_7 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_0 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_2 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_4 wire_logic_cluster/lc_2/in_1
+(29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_6 wire_logic_cluster/lc_2/in_1
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_0 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_2 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_4 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_6 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_1 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_3 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_5 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_7 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_0 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_2 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_4 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_6 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_1 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_3 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_5 wire_logic_cluster/lc_2/in_0
+(29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_7 wire_logic_cluster/lc_2/in_0
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_0 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_2 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_4 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_6 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_1 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_3 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_5 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_7 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_0 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_2 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_4 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_6 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_1 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_3 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_5 wire_logic_cluster/lc_3/in_1
+(29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_7 wire_logic_cluster/lc_3/in_1
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_1 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_3 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_5 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_7 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_0 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_2 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_4 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_6 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_1 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_3 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_5 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_7 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_0 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_2 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_4 wire_logic_cluster/lc_3/in_0
+(29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_6 wire_logic_cluster/lc_3/in_0
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_1 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_3 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_5 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_7 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_0 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_2 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_4 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_6 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_1 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_3 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_5 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_7 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_0 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_2 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_4 wire_logic_cluster/lc_4/in_1
+(29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_6 wire_logic_cluster/lc_4/in_1
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_0 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_2 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_4 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_6 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_1 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_3 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_5 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_7 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_0 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_2 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_4 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_6 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_1 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_3 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_5 wire_logic_cluster/lc_4/in_0
+(29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_7 wire_logic_cluster/lc_4/in_0
+(3 0) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 0) routing sp12_v_t_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_l_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 10) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 10) routing sp12_v_t_22 <X> sp12_h_l_22
+(3 11) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 11) routing sp12_v_b_1 <X> sp12_h_l_22
+(3 12) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 12) routing sp12_v_t_22 <X> sp12_h_r_1
+(3 13) routing sp12_h_l_22 <X> sp12_h_r_1
+(3 13) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 14) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 14) routing sp12_v_b_1 <X> sp12_v_t_22
+(3 15) routing sp12_h_l_22 <X> sp12_v_t_22
+(3 15) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 2) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 2) routing sp12_v_t_23 <X> sp12_h_l_23
+(3 3) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 3) routing sp12_v_b_0 <X> sp12_h_l_23
+(3 4) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 4) routing sp12_v_t_23 <X> sp12_h_r_0
+(3 5) routing sp12_h_l_23 <X> sp12_h_r_0
+(3 5) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 6) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 6) routing sp12_v_b_0 <X> sp12_v_t_23
+(3 7) routing sp12_h_l_23 <X> sp12_v_t_23
+(3 7) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 8) routing sp12_h_r_1 <X> sp12_v_b_1
+(3 8) routing sp12_v_t_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_l_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_r_1 <X> sp12_v_b_1
+(30 0) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_1
+(30 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_1
+(30 1) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_1
+(30 10) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_1
+(30 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_1
+(30 11) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_1
+(30 12) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_1
+(30 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_1
+(30 13) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_1
+(30 14) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_1
+(30 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_1
+(30 15) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_1
+(30 2) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_1
+(30 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_1
+(30 3) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_1
+(30 4) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_1
+(30 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_1
+(30 5) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_1
+(30 6) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_1
+(30 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_1
+(30 7) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_1
+(30 8) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_1
+(30 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_1
+(30 9) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_1
+(31 0) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_3
+(31 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_3
+(31 1) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_3
+(31 10) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_3
+(31 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_3
+(31 11) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_3
+(31 12) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_3
+(31 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_3
+(31 13) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_3
+(31 14) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_3
+(31 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_3
+(31 15) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_3
+(31 2) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_3
+(31 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_3
+(31 3) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_3
+(31 4) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_3
+(31 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_3
+(31 5) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_3
+(31 6) routing lc_trk_g0_4 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_3
+(31 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g0_2 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g0_6 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_3
+(31 7) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_3
+(31 8) routing lc_trk_g0_5 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_3
+(31 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g0_3 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g0_7 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_3
+(31 9) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_3 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_5 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_7 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_0 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_2 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_4 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_6 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_1 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_3 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_5 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_7 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_0 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_2 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_4 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_6 wire_logic_cluster/lc_0/in_3
+(32 0) Enable bit of Mux _logic_cluster/lcb3_0 => wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_0 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_2 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_4 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_6 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_1 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_3 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_5 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_7 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_0 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_2 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_4 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_6 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_1 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_3 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_5 input_2_0
+(32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_7 input_2_0
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_2 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_4 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_6 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_1 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_3 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_5 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_7 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_0 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_2 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_4 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_6 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_1 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_3 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_5 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_7 wire_logic_cluster/lc_5/in_3
+(32 10) Enable bit of Mux _logic_cluster/lcb3_5 => wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_1 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_3 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_5 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_7 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_0 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_2 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_4 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_6 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_1 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_3 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_5 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_7 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_0 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_2 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_4 input_2_5
+(32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_6 input_2_5
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_3 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_5 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_7 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_0 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_2 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_4 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_6 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_1 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_3 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_5 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_7 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_0 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_2 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_4 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_6 wire_logic_cluster/lc_6/in_3
+(32 12) Enable bit of Mux _logic_cluster/lcb3_6 => wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_0 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_2 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_4 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_6 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_1 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_3 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_5 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_7 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_0 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_2 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_4 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_6 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_1 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_3 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_5 input_2_6
+(32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_7 input_2_6
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_2 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_4 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_6 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_1 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_3 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_5 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_7 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_0 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_2 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_4 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_6 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_1 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_3 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_5 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_7 wire_logic_cluster/lc_7/in_3
+(32 14) Enable bit of Mux _logic_cluster/lcb3_7 => wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_1 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_3 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_5 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_7 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_0 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_2 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_4 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_6 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_1 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_3 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_5 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_7 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_0 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_2 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_4 input_2_7
+(32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_6 input_2_7
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_2 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_4 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_6 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_1 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_3 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_5 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_7 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_0 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_2 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_4 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_6 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_1 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_3 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_5 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_7 wire_logic_cluster/lc_1/in_3
+(32 2) Enable bit of Mux _logic_cluster/lcb3_1 => wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_1 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_3 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_5 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_7 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_0 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_2 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_4 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_6 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_1 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_3 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_5 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_7 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_0 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_2 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_4 input_2_1
+(32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_6 input_2_1
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_3 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_5 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_7 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_0 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_2 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_4 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_6 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_1 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_3 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_5 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_7 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_0 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_2 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_4 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_6 wire_logic_cluster/lc_2/in_3
+(32 4) Enable bit of Mux _logic_cluster/lcb3_2 => wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_0 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_2 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_4 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_6 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_1 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_3 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_5 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_7 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_0 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_2 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_4 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_6 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_1 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_3 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_5 input_2_2
+(32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_7 input_2_2
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_2 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_4 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_6 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_1 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_3 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_5 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_7 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_0 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_2 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_4 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_6 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_1 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_3 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_5 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_7 wire_logic_cluster/lc_3/in_3
+(32 6) Enable bit of Mux _logic_cluster/lcb3_3 => wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_1 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_3 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_5 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_7 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_0 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_2 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_4 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_6 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_1 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_3 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_5 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_7 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_0 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_2 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_4 input_2_3
+(32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_6 input_2_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_3 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_5 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_7 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_0 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_2 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_4 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_6 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_1 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_3 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_5 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_7 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_0 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_2 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_4 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_6 wire_logic_cluster/lc_4/in_3
+(32 8) Enable bit of Mux _logic_cluster/lcb3_4 => wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_0 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_2 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_4 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_6 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_1 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_3 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_5 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_7 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_0 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_2 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_4 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_6 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_1 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_3 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_5 input_2_4
+(32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_7 input_2_4
+(33 0) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_3
+(33 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_3
+(33 1) routing lc_trk_g2_0 <X> input_2_0
+(33 1) routing lc_trk_g2_2 <X> input_2_0
+(33 1) routing lc_trk_g2_4 <X> input_2_0
+(33 1) routing lc_trk_g2_6 <X> input_2_0
+(33 1) routing lc_trk_g3_1 <X> input_2_0
+(33 1) routing lc_trk_g3_3 <X> input_2_0
+(33 1) routing lc_trk_g3_5 <X> input_2_0
+(33 1) routing lc_trk_g3_7 <X> input_2_0
+(33 10) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_3
+(33 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_3
+(33 11) routing lc_trk_g2_1 <X> input_2_5
+(33 11) routing lc_trk_g2_3 <X> input_2_5
+(33 11) routing lc_trk_g2_5 <X> input_2_5
+(33 11) routing lc_trk_g2_7 <X> input_2_5
+(33 11) routing lc_trk_g3_0 <X> input_2_5
+(33 11) routing lc_trk_g3_2 <X> input_2_5
+(33 11) routing lc_trk_g3_4 <X> input_2_5
+(33 11) routing lc_trk_g3_6 <X> input_2_5
+(33 12) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_3
+(33 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_3
+(33 13) routing lc_trk_g2_0 <X> input_2_6
+(33 13) routing lc_trk_g2_2 <X> input_2_6
+(33 13) routing lc_trk_g2_4 <X> input_2_6
+(33 13) routing lc_trk_g2_6 <X> input_2_6
+(33 13) routing lc_trk_g3_1 <X> input_2_6
+(33 13) routing lc_trk_g3_3 <X> input_2_6
+(33 13) routing lc_trk_g3_5 <X> input_2_6
+(33 13) routing lc_trk_g3_7 <X> input_2_6
+(33 14) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_3
+(33 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_3
+(33 15) routing lc_trk_g2_1 <X> input_2_7
+(33 15) routing lc_trk_g2_3 <X> input_2_7
+(33 15) routing lc_trk_g2_5 <X> input_2_7
+(33 15) routing lc_trk_g2_7 <X> input_2_7
+(33 15) routing lc_trk_g3_0 <X> input_2_7
+(33 15) routing lc_trk_g3_2 <X> input_2_7
+(33 15) routing lc_trk_g3_4 <X> input_2_7
+(33 15) routing lc_trk_g3_6 <X> input_2_7
+(33 2) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_3
+(33 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_3
+(33 3) routing lc_trk_g2_1 <X> input_2_1
+(33 3) routing lc_trk_g2_3 <X> input_2_1
+(33 3) routing lc_trk_g2_5 <X> input_2_1
+(33 3) routing lc_trk_g2_7 <X> input_2_1
+(33 3) routing lc_trk_g3_0 <X> input_2_1
+(33 3) routing lc_trk_g3_2 <X> input_2_1
+(33 3) routing lc_trk_g3_4 <X> input_2_1
+(33 3) routing lc_trk_g3_6 <X> input_2_1
+(33 4) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_3
+(33 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_3
+(33 5) routing lc_trk_g2_0 <X> input_2_2
+(33 5) routing lc_trk_g2_2 <X> input_2_2
+(33 5) routing lc_trk_g2_4 <X> input_2_2
+(33 5) routing lc_trk_g2_6 <X> input_2_2
+(33 5) routing lc_trk_g3_1 <X> input_2_2
+(33 5) routing lc_trk_g3_3 <X> input_2_2
+(33 5) routing lc_trk_g3_5 <X> input_2_2
+(33 5) routing lc_trk_g3_7 <X> input_2_2
+(33 6) routing lc_trk_g2_0 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g2_2 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g2_4 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g2_6 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_3
+(33 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_3
+(33 7) routing lc_trk_g2_1 <X> input_2_3
+(33 7) routing lc_trk_g2_3 <X> input_2_3
+(33 7) routing lc_trk_g2_5 <X> input_2_3
+(33 7) routing lc_trk_g2_7 <X> input_2_3
+(33 7) routing lc_trk_g3_0 <X> input_2_3
+(33 7) routing lc_trk_g3_2 <X> input_2_3
+(33 7) routing lc_trk_g3_4 <X> input_2_3
+(33 7) routing lc_trk_g3_6 <X> input_2_3
+(33 8) routing lc_trk_g2_1 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g2_3 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g2_5 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g2_7 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_3
+(33 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_3
+(33 9) routing lc_trk_g2_0 <X> input_2_4
+(33 9) routing lc_trk_g2_2 <X> input_2_4
+(33 9) routing lc_trk_g2_4 <X> input_2_4
+(33 9) routing lc_trk_g2_6 <X> input_2_4
+(33 9) routing lc_trk_g3_1 <X> input_2_4
+(33 9) routing lc_trk_g3_3 <X> input_2_4
+(33 9) routing lc_trk_g3_5 <X> input_2_4
+(33 9) routing lc_trk_g3_7 <X> input_2_4
+(34 0) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_0/in_3
+(34 0) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_0/in_3
+(34 1) routing lc_trk_g1_1 <X> input_2_0
+(34 1) routing lc_trk_g1_3 <X> input_2_0
+(34 1) routing lc_trk_g1_5 <X> input_2_0
+(34 1) routing lc_trk_g1_7 <X> input_2_0
+(34 1) routing lc_trk_g3_1 <X> input_2_0
+(34 1) routing lc_trk_g3_3 <X> input_2_0
+(34 1) routing lc_trk_g3_5 <X> input_2_0
+(34 1) routing lc_trk_g3_7 <X> input_2_0
+(34 10) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_5/in_3
+(34 10) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_5/in_3
+(34 11) routing lc_trk_g1_0 <X> input_2_5
+(34 11) routing lc_trk_g1_2 <X> input_2_5
+(34 11) routing lc_trk_g1_4 <X> input_2_5
+(34 11) routing lc_trk_g1_6 <X> input_2_5
+(34 11) routing lc_trk_g3_0 <X> input_2_5
+(34 11) routing lc_trk_g3_2 <X> input_2_5
+(34 11) routing lc_trk_g3_4 <X> input_2_5
+(34 11) routing lc_trk_g3_6 <X> input_2_5
+(34 12) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_6/in_3
+(34 12) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_6/in_3
+(34 13) routing lc_trk_g1_1 <X> input_2_6
+(34 13) routing lc_trk_g1_3 <X> input_2_6
+(34 13) routing lc_trk_g1_5 <X> input_2_6
+(34 13) routing lc_trk_g1_7 <X> input_2_6
+(34 13) routing lc_trk_g3_1 <X> input_2_6
+(34 13) routing lc_trk_g3_3 <X> input_2_6
+(34 13) routing lc_trk_g3_5 <X> input_2_6
+(34 13) routing lc_trk_g3_7 <X> input_2_6
+(34 14) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_7/in_3
+(34 14) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_7/in_3
+(34 15) routing lc_trk_g1_0 <X> input_2_7
+(34 15) routing lc_trk_g1_2 <X> input_2_7
+(34 15) routing lc_trk_g1_4 <X> input_2_7
+(34 15) routing lc_trk_g1_6 <X> input_2_7
+(34 15) routing lc_trk_g3_0 <X> input_2_7
+(34 15) routing lc_trk_g3_2 <X> input_2_7
+(34 15) routing lc_trk_g3_4 <X> input_2_7
+(34 15) routing lc_trk_g3_6 <X> input_2_7
+(34 2) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_1/in_3
+(34 2) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_1/in_3
+(34 3) routing lc_trk_g1_0 <X> input_2_1
+(34 3) routing lc_trk_g1_2 <X> input_2_1
+(34 3) routing lc_trk_g1_4 <X> input_2_1
+(34 3) routing lc_trk_g1_6 <X> input_2_1
+(34 3) routing lc_trk_g3_0 <X> input_2_1
+(34 3) routing lc_trk_g3_2 <X> input_2_1
+(34 3) routing lc_trk_g3_4 <X> input_2_1
+(34 3) routing lc_trk_g3_6 <X> input_2_1
+(34 4) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_2/in_3
+(34 4) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_2/in_3
+(34 5) routing lc_trk_g1_1 <X> input_2_2
+(34 5) routing lc_trk_g1_3 <X> input_2_2
+(34 5) routing lc_trk_g1_5 <X> input_2_2
+(34 5) routing lc_trk_g1_7 <X> input_2_2
+(34 5) routing lc_trk_g3_1 <X> input_2_2
+(34 5) routing lc_trk_g3_3 <X> input_2_2
+(34 5) routing lc_trk_g3_5 <X> input_2_2
+(34 5) routing lc_trk_g3_7 <X> input_2_2
+(34 6) routing lc_trk_g1_1 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g1_3 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g1_5 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g1_7 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g3_1 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g3_3 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g3_5 <X> wire_logic_cluster/lc_3/in_3
+(34 6) routing lc_trk_g3_7 <X> wire_logic_cluster/lc_3/in_3
+(34 7) routing lc_trk_g1_0 <X> input_2_3
+(34 7) routing lc_trk_g1_2 <X> input_2_3
+(34 7) routing lc_trk_g1_4 <X> input_2_3
+(34 7) routing lc_trk_g1_6 <X> input_2_3
+(34 7) routing lc_trk_g3_0 <X> input_2_3
+(34 7) routing lc_trk_g3_2 <X> input_2_3
+(34 7) routing lc_trk_g3_4 <X> input_2_3
+(34 7) routing lc_trk_g3_6 <X> input_2_3
+(34 8) routing lc_trk_g1_0 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g1_2 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g1_4 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g1_6 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g3_0 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g3_2 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g3_4 <X> wire_logic_cluster/lc_4/in_3
+(34 8) routing lc_trk_g3_6 <X> wire_logic_cluster/lc_4/in_3
+(34 9) routing lc_trk_g1_1 <X> input_2_4
+(34 9) routing lc_trk_g1_3 <X> input_2_4
+(34 9) routing lc_trk_g1_5 <X> input_2_4
+(34 9) routing lc_trk_g1_7 <X> input_2_4
+(34 9) routing lc_trk_g3_1 <X> input_2_4
+(34 9) routing lc_trk_g3_3 <X> input_2_4
+(34 9) routing lc_trk_g3_5 <X> input_2_4
+(34 9) routing lc_trk_g3_7 <X> input_2_4
+(35 0) routing lc_trk_g0_4 <X> input_2_0
+(35 0) routing lc_trk_g0_6 <X> input_2_0
+(35 0) routing lc_trk_g1_5 <X> input_2_0
+(35 0) routing lc_trk_g1_7 <X> input_2_0
+(35 0) routing lc_trk_g2_4 <X> input_2_0
+(35 0) routing lc_trk_g2_6 <X> input_2_0
+(35 0) routing lc_trk_g3_5 <X> input_2_0
+(35 0) routing lc_trk_g3_7 <X> input_2_0
+(35 1) routing lc_trk_g0_2 <X> input_2_0
+(35 1) routing lc_trk_g0_6 <X> input_2_0
+(35 1) routing lc_trk_g1_3 <X> input_2_0
+(35 1) routing lc_trk_g1_7 <X> input_2_0
+(35 1) routing lc_trk_g2_2 <X> input_2_0
+(35 1) routing lc_trk_g2_6 <X> input_2_0
+(35 1) routing lc_trk_g3_3 <X> input_2_0
+(35 1) routing lc_trk_g3_7 <X> input_2_0
+(35 10) routing lc_trk_g0_5 <X> input_2_5
+(35 10) routing lc_trk_g0_7 <X> input_2_5
+(35 10) routing lc_trk_g1_4 <X> input_2_5
+(35 10) routing lc_trk_g1_6 <X> input_2_5
+(35 10) routing lc_trk_g2_5 <X> input_2_5
+(35 10) routing lc_trk_g2_7 <X> input_2_5
+(35 10) routing lc_trk_g3_4 <X> input_2_5
+(35 10) routing lc_trk_g3_6 <X> input_2_5
+(35 11) routing lc_trk_g0_3 <X> input_2_5
+(35 11) routing lc_trk_g0_7 <X> input_2_5
+(35 11) routing lc_trk_g1_2 <X> input_2_5
+(35 11) routing lc_trk_g1_6 <X> input_2_5
+(35 11) routing lc_trk_g2_3 <X> input_2_5
+(35 11) routing lc_trk_g2_7 <X> input_2_5
+(35 11) routing lc_trk_g3_2 <X> input_2_5
+(35 11) routing lc_trk_g3_6 <X> input_2_5
+(35 12) routing lc_trk_g0_4 <X> input_2_6
+(35 12) routing lc_trk_g0_6 <X> input_2_6
+(35 12) routing lc_trk_g1_5 <X> input_2_6
+(35 12) routing lc_trk_g1_7 <X> input_2_6
+(35 12) routing lc_trk_g2_4 <X> input_2_6
+(35 12) routing lc_trk_g2_6 <X> input_2_6
+(35 12) routing lc_trk_g3_5 <X> input_2_6
+(35 12) routing lc_trk_g3_7 <X> input_2_6
+(35 13) routing lc_trk_g0_2 <X> input_2_6
+(35 13) routing lc_trk_g0_6 <X> input_2_6
+(35 13) routing lc_trk_g1_3 <X> input_2_6
+(35 13) routing lc_trk_g1_7 <X> input_2_6
+(35 13) routing lc_trk_g2_2 <X> input_2_6
+(35 13) routing lc_trk_g2_6 <X> input_2_6
+(35 13) routing lc_trk_g3_3 <X> input_2_6
+(35 13) routing lc_trk_g3_7 <X> input_2_6
+(35 14) routing lc_trk_g0_5 <X> input_2_7
+(35 14) routing lc_trk_g0_7 <X> input_2_7
+(35 14) routing lc_trk_g1_4 <X> input_2_7
+(35 14) routing lc_trk_g1_6 <X> input_2_7
+(35 14) routing lc_trk_g2_5 <X> input_2_7
+(35 14) routing lc_trk_g2_7 <X> input_2_7
+(35 14) routing lc_trk_g3_4 <X> input_2_7
+(35 14) routing lc_trk_g3_6 <X> input_2_7
+(35 15) routing lc_trk_g0_3 <X> input_2_7
+(35 15) routing lc_trk_g0_7 <X> input_2_7
+(35 15) routing lc_trk_g1_2 <X> input_2_7
+(35 15) routing lc_trk_g1_6 <X> input_2_7
+(35 15) routing lc_trk_g2_3 <X> input_2_7
+(35 15) routing lc_trk_g2_7 <X> input_2_7
+(35 15) routing lc_trk_g3_2 <X> input_2_7
+(35 15) routing lc_trk_g3_6 <X> input_2_7
+(35 2) routing lc_trk_g0_5 <X> input_2_1
+(35 2) routing lc_trk_g0_7 <X> input_2_1
+(35 2) routing lc_trk_g1_4 <X> input_2_1
+(35 2) routing lc_trk_g1_6 <X> input_2_1
+(35 2) routing lc_trk_g2_5 <X> input_2_1
+(35 2) routing lc_trk_g2_7 <X> input_2_1
+(35 2) routing lc_trk_g3_4 <X> input_2_1
+(35 2) routing lc_trk_g3_6 <X> input_2_1
+(35 3) routing lc_trk_g0_3 <X> input_2_1
+(35 3) routing lc_trk_g0_7 <X> input_2_1
+(35 3) routing lc_trk_g1_2 <X> input_2_1
+(35 3) routing lc_trk_g1_6 <X> input_2_1
+(35 3) routing lc_trk_g2_3 <X> input_2_1
+(35 3) routing lc_trk_g2_7 <X> input_2_1
+(35 3) routing lc_trk_g3_2 <X> input_2_1
+(35 3) routing lc_trk_g3_6 <X> input_2_1
+(35 4) routing lc_trk_g0_4 <X> input_2_2
+(35 4) routing lc_trk_g0_6 <X> input_2_2
+(35 4) routing lc_trk_g1_5 <X> input_2_2
+(35 4) routing lc_trk_g1_7 <X> input_2_2
+(35 4) routing lc_trk_g2_4 <X> input_2_2
+(35 4) routing lc_trk_g2_6 <X> input_2_2
+(35 4) routing lc_trk_g3_5 <X> input_2_2
+(35 4) routing lc_trk_g3_7 <X> input_2_2
+(35 5) routing lc_trk_g0_2 <X> input_2_2
+(35 5) routing lc_trk_g0_6 <X> input_2_2
+(35 5) routing lc_trk_g1_3 <X> input_2_2
+(35 5) routing lc_trk_g1_7 <X> input_2_2
+(35 5) routing lc_trk_g2_2 <X> input_2_2
+(35 5) routing lc_trk_g2_6 <X> input_2_2
+(35 5) routing lc_trk_g3_3 <X> input_2_2
+(35 5) routing lc_trk_g3_7 <X> input_2_2
+(35 6) routing lc_trk_g0_5 <X> input_2_3
+(35 6) routing lc_trk_g0_7 <X> input_2_3
+(35 6) routing lc_trk_g1_4 <X> input_2_3
+(35 6) routing lc_trk_g1_6 <X> input_2_3
+(35 6) routing lc_trk_g2_5 <X> input_2_3
+(35 6) routing lc_trk_g2_7 <X> input_2_3
+(35 6) routing lc_trk_g3_4 <X> input_2_3
+(35 6) routing lc_trk_g3_6 <X> input_2_3
+(35 7) routing lc_trk_g0_3 <X> input_2_3
+(35 7) routing lc_trk_g0_7 <X> input_2_3
+(35 7) routing lc_trk_g1_2 <X> input_2_3
+(35 7) routing lc_trk_g1_6 <X> input_2_3
+(35 7) routing lc_trk_g2_3 <X> input_2_3
+(35 7) routing lc_trk_g2_7 <X> input_2_3
+(35 7) routing lc_trk_g3_2 <X> input_2_3
+(35 7) routing lc_trk_g3_6 <X> input_2_3
+(35 8) routing lc_trk_g0_4 <X> input_2_4
+(35 8) routing lc_trk_g0_6 <X> input_2_4
+(35 8) routing lc_trk_g1_5 <X> input_2_4
+(35 8) routing lc_trk_g1_7 <X> input_2_4
+(35 8) routing lc_trk_g2_4 <X> input_2_4
+(35 8) routing lc_trk_g2_6 <X> input_2_4
+(35 8) routing lc_trk_g3_5 <X> input_2_4
+(35 8) routing lc_trk_g3_7 <X> input_2_4
+(35 9) routing lc_trk_g0_2 <X> input_2_4
+(35 9) routing lc_trk_g0_6 <X> input_2_4
+(35 9) routing lc_trk_g1_3 <X> input_2_4
+(35 9) routing lc_trk_g1_7 <X> input_2_4
+(35 9) routing lc_trk_g2_2 <X> input_2_4
+(35 9) routing lc_trk_g2_6 <X> input_2_4
+(35 9) routing lc_trk_g3_3 <X> input_2_4
+(35 9) routing lc_trk_g3_7 <X> input_2_4
+(36 0) LC_0 Logic Functioning bit
+(36 1) LC_0 Logic Functioning bit
+(36 10) LC_5 Logic Functioning bit
+(36 11) LC_5 Logic Functioning bit
+(36 12) LC_6 Logic Functioning bit
+(36 13) LC_6 Logic Functioning bit
+(36 14) LC_7 Logic Functioning bit
+(36 15) LC_7 Logic Functioning bit
+(36 2) LC_1 Logic Functioning bit
+(36 3) LC_1 Logic Functioning bit
+(36 4) LC_2 Logic Functioning bit
+(36 5) LC_2 Logic Functioning bit
+(36 6) LC_3 Logic Functioning bit
+(36 7) LC_3 Logic Functioning bit
+(36 8) LC_4 Logic Functioning bit
+(36 9) LC_4 Logic Functioning bit
+(37 0) LC_0 Logic Functioning bit
+(37 1) LC_0 Logic Functioning bit
+(37 10) LC_5 Logic Functioning bit
+(37 11) LC_5 Logic Functioning bit
+(37 12) LC_6 Logic Functioning bit
+(37 13) LC_6 Logic Functioning bit
+(37 14) LC_7 Logic Functioning bit
+(37 15) LC_7 Logic Functioning bit
+(37 2) LC_1 Logic Functioning bit
+(37 3) LC_1 Logic Functioning bit
+(37 4) LC_2 Logic Functioning bit
+(37 5) LC_2 Logic Functioning bit
+(37 6) LC_3 Logic Functioning bit
+(37 7) LC_3 Logic Functioning bit
+(37 8) LC_4 Logic Functioning bit
+(37 9) LC_4 Logic Functioning bit
+(38 0) LC_0 Logic Functioning bit
+(38 1) LC_0 Logic Functioning bit
+(38 10) LC_5 Logic Functioning bit
+(38 11) LC_5 Logic Functioning bit
+(38 12) LC_6 Logic Functioning bit
+(38 13) LC_6 Logic Functioning bit
+(38 14) LC_7 Logic Functioning bit
+(38 15) LC_7 Logic Functioning bit
+(38 2) LC_1 Logic Functioning bit
+(38 3) LC_1 Logic Functioning bit
+(38 4) LC_2 Logic Functioning bit
+(38 5) LC_2 Logic Functioning bit
+(38 6) LC_3 Logic Functioning bit
+(38 7) LC_3 Logic Functioning bit
+(38 8) LC_4 Logic Functioning bit
+(38 9) LC_4 Logic Functioning bit
+(39 0) LC_0 Logic Functioning bit
+(39 1) LC_0 Logic Functioning bit
+(39 10) LC_5 Logic Functioning bit
+(39 11) LC_5 Logic Functioning bit
+(39 12) LC_6 Logic Functioning bit
+(39 13) LC_6 Logic Functioning bit
+(39 14) LC_7 Logic Functioning bit
+(39 15) LC_7 Logic Functioning bit
+(39 2) LC_1 Logic Functioning bit
+(39 3) LC_1 Logic Functioning bit
+(39 4) LC_2 Logic Functioning bit
+(39 5) LC_2 Logic Functioning bit
+(39 6) LC_3 Logic Functioning bit
+(39 7) LC_3 Logic Functioning bit
+(39 8) LC_4 Logic Functioning bit
+(39 9) LC_4 Logic Functioning bit
+(4 0) routing sp4_h_l_37 <X> sp4_v_b_0
+(4 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_37 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(4 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(4 1) routing sp4_h_l_44 <X> sp4_h_r_0
+(4 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(4 1) routing sp4_v_t_42 <X> sp4_h_r_0
+(4 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(4 10) routing sp4_h_r_6 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_6 <X> sp4_v_t_43
+(4 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(4 11) routing sp4_h_r_3 <X> sp4_h_l_43
+(4 11) routing sp4_v_b_1 <X> sp4_h_l_43
+(4 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(4 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(4 12) routing sp4_h_l_44 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_44 <X> sp4_v_b_9
+(4 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(4 13) routing sp4_h_l_43 <X> sp4_h_r_9
+(4 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(4 13) routing sp4_v_t_41 <X> sp4_h_r_9
+(4 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(4 14) routing sp4_h_r_9 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_9 <X> sp4_v_t_44
+(4 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(4 15) routing sp4_h_r_6 <X> sp4_h_l_44
+(4 15) routing sp4_v_b_4 <X> sp4_h_l_44
+(4 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(4 2) routing sp4_h_r_0 <X> sp4_v_t_37
+(4 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_0 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(4 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(4 3) routing sp4_h_r_9 <X> sp4_h_l_37
+(4 3) routing sp4_v_b_7 <X> sp4_h_l_37
+(4 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(4 4) routing sp4_h_l_38 <X> sp4_v_b_3
+(4 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_38 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(4 5) routing sp4_h_l_37 <X> sp4_h_r_3
+(4 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(4 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(4 5) routing sp4_v_t_47 <X> sp4_h_r_3
+(4 6) routing sp4_h_r_3 <X> sp4_v_t_38
+(4 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_3 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(4 7) routing sp4_h_r_0 <X> sp4_h_l_38
+(4 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(4 7) routing sp4_v_b_10 <X> sp4_h_l_38
+(4 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(4 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(4 8) routing sp4_h_l_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(4 9) routing sp4_h_l_38 <X> sp4_h_r_6
+(4 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(4 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(4 9) routing sp4_v_t_36 <X> sp4_h_r_6
+(40 0) LC_0 Logic Functioning bit
+(40 1) LC_0 Logic Functioning bit
+(40 10) LC_5 Logic Functioning bit
+(40 11) LC_5 Logic Functioning bit
+(40 12) LC_6 Logic Functioning bit
+(40 13) LC_6 Logic Functioning bit
+(40 14) LC_7 Logic Functioning bit
+(40 15) LC_7 Logic Functioning bit
+(40 2) LC_1 Logic Functioning bit
+(40 3) LC_1 Logic Functioning bit
+(40 4) LC_2 Logic Functioning bit
+(40 5) LC_2 Logic Functioning bit
+(40 6) LC_3 Logic Functioning bit
+(40 7) LC_3 Logic Functioning bit
+(40 8) LC_4 Logic Functioning bit
+(40 9) LC_4 Logic Functioning bit
+(41 0) LC_0 Logic Functioning bit
+(41 1) LC_0 Logic Functioning bit
+(41 10) LC_5 Logic Functioning bit
+(41 11) LC_5 Logic Functioning bit
+(41 12) LC_6 Logic Functioning bit
+(41 13) LC_6 Logic Functioning bit
+(41 14) LC_7 Logic Functioning bit
+(41 15) LC_7 Logic Functioning bit
+(41 2) LC_1 Logic Functioning bit
+(41 3) LC_1 Logic Functioning bit
+(41 4) LC_2 Logic Functioning bit
+(41 5) LC_2 Logic Functioning bit
+(41 6) LC_3 Logic Functioning bit
+(41 7) LC_3 Logic Functioning bit
+(41 8) LC_4 Logic Functioning bit
+(41 9) LC_4 Logic Functioning bit
+(42 0) LC_0 Logic Functioning bit
+(42 1) LC_0 Logic Functioning bit
+(42 10) LC_5 Logic Functioning bit
+(42 11) LC_5 Logic Functioning bit
+(42 12) LC_6 Logic Functioning bit
+(42 13) LC_6 Logic Functioning bit
+(42 14) LC_7 Logic Functioning bit
+(42 15) LC_7 Logic Functioning bit
+(42 2) LC_1 Logic Functioning bit
+(42 3) LC_1 Logic Functioning bit
+(42 4) LC_2 Logic Functioning bit
+(42 5) LC_2 Logic Functioning bit
+(42 6) LC_3 Logic Functioning bit
+(42 7) LC_3 Logic Functioning bit
+(42 8) LC_4 Logic Functioning bit
+(42 9) LC_4 Logic Functioning bit
+(43 0) LC_0 Logic Functioning bit
+(43 1) LC_0 Logic Functioning bit
+(43 10) LC_5 Logic Functioning bit
+(43 11) LC_5 Logic Functioning bit
+(43 12) LC_6 Logic Functioning bit
+(43 13) LC_6 Logic Functioning bit
+(43 14) LC_7 Logic Functioning bit
+(43 15) LC_7 Logic Functioning bit
+(43 2) LC_1 Logic Functioning bit
+(43 3) LC_1 Logic Functioning bit
+(43 4) LC_2 Logic Functioning bit
+(43 5) LC_2 Logic Functioning bit
+(43 6) LC_3 Logic Functioning bit
+(43 7) LC_3 Logic Functioning bit
+(43 8) LC_4 Logic Functioning bit
+(43 9) LC_4 Logic Functioning bit
+(44 0) LC_0 Logic Functioning bit
+(44 1) LC_0 Logic Functioning bit
+(44 10) LC_5 Logic Functioning bit
+(44 11) LC_5 Logic Functioning bit
+(44 12) LC_6 Logic Functioning bit
+(44 13) LC_6 Logic Functioning bit
+(44 14) LC_7 Logic Functioning bit
+(44 15) LC_7 Logic Functioning bit
+(44 2) LC_1 Logic Functioning bit
+(44 3) LC_1 Logic Functioning bit
+(44 4) LC_2 Logic Functioning bit
+(44 5) LC_2 Logic Functioning bit
+(44 6) LC_3 Logic Functioning bit
+(44 7) LC_3 Logic Functioning bit
+(44 8) LC_4 Logic Functioning bit
+(44 9) LC_4 Logic Functioning bit
+(45 0) LC_0 Logic Functioning bit
+(45 1) LC_0 Logic Functioning bit
+(45 10) LC_5 Logic Functioning bit
+(45 11) LC_5 Logic Functioning bit
+(45 12) LC_6 Logic Functioning bit
+(45 13) LC_6 Logic Functioning bit
+(45 14) LC_7 Logic Functioning bit
+(45 15) LC_7 Logic Functioning bit
+(45 2) LC_1 Logic Functioning bit
+(45 3) LC_1 Logic Functioning bit
+(45 4) LC_2 Logic Functioning bit
+(45 5) LC_2 Logic Functioning bit
+(45 6) LC_3 Logic Functioning bit
+(45 7) LC_3 Logic Functioning bit
+(45 8) LC_4 Logic Functioning bit
+(45 9) LC_4 Logic Functioning bit
+(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_logic_cluster/lc_0/out sp4_h_l_5
+(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_logic_cluster/lc_0/out sp4_h_r_0
+(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_logic_cluster/lc_5/out sp4_h_l_15
+(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_logic_cluster/lc_5/out sp4_h_r_10
+(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_logic_cluster/lc_6/out sp4_h_l_17
+(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_logic_cluster/lc_6/out sp4_h_l_1
+(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_logic_cluster/lc_7/out sp4_h_r_30
+(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_logic_cluster/lc_7/out sp4_h_r_14
+(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_logic_cluster/lc_1/out sp4_h_l_7
+(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_logic_cluster/lc_1/out sp4_h_r_2
+(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_logic_cluster/lc_2/out sp4_h_l_9
+(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_logic_cluster/lc_2/out sp4_h_r_4
+(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_logic_cluster/lc_3/out sp4_h_l_11
+(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_logic_cluster/lc_3/out sp4_h_r_6
+(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_logic_cluster/lc_4/out sp4_h_r_24
+(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_logic_cluster/lc_4/out sp4_h_r_8
+(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_logic_cluster/lc_0/out sp12_h_r_8
+(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_logic_cluster/lc_0/out sp4_h_l_21
+(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_logic_cluster/lc_5/out sp12_h_r_2
+(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_logic_cluster/lc_5/out sp4_h_r_42
+(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_logic_cluster/lc_6/out sp12_h_l_3
+(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_logic_cluster/lc_6/out sp4_h_r_44
+(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_logic_cluster/lc_7/out sp12_h_l_5
+(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_logic_cluster/lc_7/out sp4_h_r_46
+(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_logic_cluster/lc_1/out sp12_h_r_10
+(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_logic_cluster/lc_1/out sp4_h_r_34
+(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_logic_cluster/lc_2/out sp12_h_r_12
+(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_logic_cluster/lc_2/out sp4_h_r_36
+(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_logic_cluster/lc_3/out sp12_h_r_14
+(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_logic_cluster/lc_3/out sp4_h_r_38
+(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_logic_cluster/lc_4/out sp12_h_r_0
+(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_logic_cluster/lc_4/out sp4_h_r_40
+(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_logic_cluster/lc_0/out sp4_v_b_0
+(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_logic_cluster/lc_0/out sp4_v_t_5
+(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_logic_cluster/lc_5/out sp12_h_l_17
+(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_logic_cluster/lc_5/out sp4_v_b_10
+(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_logic_cluster/lc_6/out sp12_h_r_20
+(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_logic_cluster/lc_6/out sp4_v_t_1
+(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_logic_cluster/lc_7/out sp12_h_l_21
+(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_logic_cluster/lc_7/out sp4_v_t_3
+(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_logic_cluster/lc_1/out sp4_v_b_2
+(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_logic_cluster/lc_1/out sp4_v_b_18
+(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_logic_cluster/lc_2/out sp4_v_b_4
+(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_logic_cluster/lc_2/out sp4_v_t_9
+(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_logic_cluster/lc_3/out sp4_v_b_6
+(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_logic_cluster/lc_3/out sp4_v_b_22
+(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_logic_cluster/lc_4/out sp12_h_r_16
+(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_logic_cluster/lc_4/out sp4_v_b_8
+(49 1) Carry_In_Mux bit
+(49 1) Carry_In_Mux bit
+(5 0) routing sp4_h_l_44 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_0 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_6 <X> sp4_h_r_0
+(5 0) routing sp4_v_t_37 <X> sp4_h_r_0
+(5 1) routing sp4_h_l_37 <X> sp4_v_b_0
+(5 1) routing sp4_h_l_43 <X> sp4_v_b_0
+(5 1) routing sp4_h_r_0 <X> sp4_v_b_0
+(5 1) routing sp4_v_t_44 <X> sp4_v_b_0
+(5 10) routing sp4_h_r_3 <X> sp4_h_l_43
+(5 10) routing sp4_v_b_6 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_37 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_43 <X> sp4_h_l_43
+(5 11) routing sp4_h_l_43 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_0 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_6 <X> sp4_v_t_43
+(5 11) routing sp4_v_b_3 <X> sp4_v_t_43
+(5 12) routing sp4_h_l_43 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_3 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_9 <X> sp4_h_r_9
+(5 12) routing sp4_v_t_44 <X> sp4_h_r_9
+(5 13) routing sp4_h_l_38 <X> sp4_v_b_9
+(5 13) routing sp4_h_l_44 <X> sp4_v_b_9
+(5 13) routing sp4_h_r_9 <X> sp4_v_b_9
+(5 13) routing sp4_v_t_43 <X> sp4_v_b_9
+(5 14) routing sp4_h_r_6 <X> sp4_h_l_44
+(5 14) routing sp4_v_b_9 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_38 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_44 <X> sp4_h_l_44
+(5 15) routing sp4_h_l_44 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_3 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_9 <X> sp4_v_t_44
+(5 15) routing sp4_v_b_6 <X> sp4_v_t_44
+(5 2) routing sp4_h_r_9 <X> sp4_h_l_37
+(5 2) routing sp4_v_b_0 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_37 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_43 <X> sp4_h_l_37
+(5 3) routing sp4_h_l_37 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_0 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_6 <X> sp4_v_t_37
+(5 3) routing sp4_v_b_9 <X> sp4_v_t_37
+(5 4) routing sp4_h_l_37 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_3 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_9 <X> sp4_h_r_3
+(5 4) routing sp4_v_t_38 <X> sp4_h_r_3
+(5 5) routing sp4_h_l_38 <X> sp4_v_b_3
+(5 5) routing sp4_h_l_44 <X> sp4_v_b_3
+(5 5) routing sp4_h_r_3 <X> sp4_v_b_3
+(5 5) routing sp4_v_t_37 <X> sp4_v_b_3
+(5 6) routing sp4_h_r_0 <X> sp4_h_l_38
+(5 6) routing sp4_v_b_3 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_38 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_44 <X> sp4_h_l_38
+(5 7) routing sp4_h_l_38 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_3 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_9 <X> sp4_v_t_38
+(5 7) routing sp4_v_b_0 <X> sp4_v_t_38
+(5 8) routing sp4_h_l_38 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_0 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_6 <X> sp4_h_r_6
+(5 8) routing sp4_v_t_43 <X> sp4_h_r_6
+(5 9) routing sp4_h_l_37 <X> sp4_v_b_6
+(5 9) routing sp4_h_l_43 <X> sp4_v_b_6
+(5 9) routing sp4_h_r_6 <X> sp4_v_b_6
+(5 9) routing sp4_v_t_38 <X> sp4_v_b_6
+(50 1) Carry_In_Mux bit
+(50 1) Carry_In_Mux bit
+(50 10) Cascade bit: LH_LC05_inmux02_5
+(50 12) Cascade bit: LH_LC06_inmux02_5
+(50 14) Cascade bit: LH_LC07_inmux02_5
+(50 2) Cascade bit: LH_LC01_inmux02_5
+(50 4) Cascade bit: LH_LC02_inmux02_5
+(50 6) Cascade bit: LH_LC03_inmux02_5
+(50 8) Cascade bit: LH_LC04_inmux02_5
+(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_logic_cluster/lc_0/out sp12_v_b_0
+(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_logic_cluster/lc_0/out sp4_v_t_21
+(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_logic_cluster/lc_5/out sp4_v_b_42
+(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_logic_cluster/lc_5/out sp4_v_b_26
+(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_logic_cluster/lc_6/out sp4_v_t_33
+(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_logic_cluster/lc_6/out sp4_v_t_17
+(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_logic_cluster/lc_7/out sp4_v_b_46
+(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_logic_cluster/lc_7/out sp4_v_b_30
+(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_logic_cluster/lc_1/out sp12_v_t_1
+(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_logic_cluster/lc_1/out sp4_v_t_23
+(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_logic_cluster/lc_2/out sp12_v_t_3
+(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_logic_cluster/lc_2/out sp4_v_b_36
+(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_logic_cluster/lc_3/out sp12_v_b_6
+(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_logic_cluster/lc_3/out sp4_v_b_38
+(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_logic_cluster/lc_4/out sp4_v_t_29
+(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_logic_cluster/lc_4/out sp4_v_b_24
+(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_logic_cluster/lc_0/out sp12_v_b_16
+(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_1
+(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_logic_cluster/lc_5/out sp12_v_t_9
+(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_11
+(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_logic_cluster/lc_6/out sp12_v_b_12
+(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_13
+(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_logic_cluster/lc_7/out sp12_v_b_14
+(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_15
+(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_logic_cluster/lc_1/out sp12_v_b_18
+(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_3
+(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_logic_cluster/lc_2/out sp12_v_b_20
+(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_5
+(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_logic_cluster/lc_3/out sp12_v_t_21
+(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_7
+(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_logic_cluster/lc_4/out sp12_v_b_8
+(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_9
+(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_17
+(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_33
+(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_27
+(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_43
+(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_29
+(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_45
+(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_31
+(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_47
+(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_19
+(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_35
+(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_21
+(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_37
+(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_23
+(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_39
+(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_25
+(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_41
+(6 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(6 0) routing sp4_h_r_7 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_44 <X> sp4_v_b_0
+(6 1) routing sp4_h_l_37 <X> sp4_h_r_0
+(6 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_0 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(6 10) routing sp4_h_l_36 <X> sp4_v_t_43
+(6 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_3 <X> sp4_v_t_43
+(6 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(6 11) routing sp4_h_r_6 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_43 <X> sp4_h_l_43
+(6 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(6 12) routing sp4_h_r_4 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_43 <X> sp4_v_b_9
+(6 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(6 13) routing sp4_h_l_44 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_9 <X> sp4_h_r_9
+(6 14) routing sp4_h_l_41 <X> sp4_v_t_44
+(6 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_6 <X> sp4_v_t_44
+(6 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(6 15) routing sp4_h_r_9 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_44 <X> sp4_h_l_44
+(6 2) routing sp4_h_l_42 <X> sp4_v_t_37
+(6 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_9 <X> sp4_v_t_37
+(6 3) routing sp4_h_r_0 <X> sp4_h_l_37
+(6 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_37 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(6 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(6 4) routing sp4_h_r_10 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_37 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(6 5) routing sp4_h_l_38 <X> sp4_h_r_3
+(6 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_3 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(6 6) routing sp4_h_l_47 <X> sp4_v_t_38
+(6 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_0 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(6 7) routing sp4_h_r_3 <X> sp4_h_l_38
+(6 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_38 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(6 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(6 8) routing sp4_h_r_1 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(6 9) routing sp4_h_l_43 <X> sp4_h_r_6
+(6 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_6 <X> sp4_h_r_6
+(7 10) Column buffer control bit: LH_colbuf_cntl_3
+(7 11) Column buffer control bit: LH_colbuf_cntl_2
+(7 12) Column buffer control bit: LH_colbuf_cntl_5
+(7 13) Column buffer control bit: LH_colbuf_cntl_4
+(7 14) Column buffer control bit: LH_colbuf_cntl_7
+(7 15) Column buffer control bit: LH_colbuf_cntl_6
+(7 8) Column buffer control bit: LH_colbuf_cntl_1
+(7 9) Column buffer control bit: LH_colbuf_cntl_0
+(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
+(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(8 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(8 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(8 1) routing sp4_h_r_1 <X> sp4_v_b_1
+(8 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(8 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(8 10) routing sp4_h_r_7 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(8 11) routing sp4_h_l_42 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(8 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(8 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(8 12) routing sp4_h_l_47 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(8 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(8 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(8 13) routing sp4_h_r_10 <X> sp4_v_b_10
+(8 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(8 14) routing sp4_h_r_10 <X> sp4_h_l_47
+(8 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(8 15) routing sp4_h_l_47 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(8 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(8 2) routing sp4_h_r_1 <X> sp4_h_l_36
+(8 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(8 3) routing sp4_h_l_36 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(8 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(8 4) routing sp4_h_l_41 <X> sp4_h_r_4
+(8 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(8 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(8 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(8 5) routing sp4_h_r_4 <X> sp4_v_b_4
+(8 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(8 6) routing sp4_h_r_4 <X> sp4_h_l_41
+(8 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(8 7) routing sp4_h_l_41 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(8 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(8 8) routing sp4_h_l_42 <X> sp4_h_r_7
+(8 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(8 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(8 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(8 9) routing sp4_h_r_7 <X> sp4_v_b_7
+(8 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(9 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(9 0) routing sp4_v_t_36 <X> sp4_h_r_1
+(9 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(9 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_36 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(9 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(9 10) routing sp4_v_b_7 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(9 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(9 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_7 <X> sp4_v_t_42
+(9 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(9 12) routing sp4_v_t_47 <X> sp4_h_r_10
+(9 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(9 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_47 <X> sp4_v_b_10
+(9 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(9 14) routing sp4_v_b_10 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(9 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(9 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_10 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(9 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(9 2) routing sp4_v_b_1 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(9 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(9 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_1 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(9 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(9 4) routing sp4_v_t_41 <X> sp4_h_r_4
+(9 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(9 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_41 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(9 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(9 6) routing sp4_v_b_4 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(9 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(9 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(9 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(9 8) routing sp4_v_t_42 <X> sp4_h_r_7
+(9 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(9 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_46 <X> sp4_v_b_7
diff --git a/icefuzz/cached_ramb.txt b/icefuzz/cached_ramb.txt
new file mode 100644
index 0000000..64ed35c
--- /dev/null
+++ b/icefuzz/cached_ramb.txt
@@ -0,0 +1,3586 @@
+(0 0) Negative Clock bit
+(0 10) routing glb_netwk_2 <X> glb2local_2
+(0 10) routing glb_netwk_3 <X> glb2local_2
+(0 10) routing glb_netwk_6 <X> glb2local_2
+(0 10) routing glb_netwk_7 <X> glb2local_2
+(0 11) routing glb_netwk_1 <X> glb2local_2
+(0 11) routing glb_netwk_3 <X> glb2local_2
+(0 11) routing glb_netwk_5 <X> glb2local_2
+(0 11) routing glb_netwk_7 <X> glb2local_2
+(0 12) routing glb_netwk_2 <X> glb2local_3
+(0 12) routing glb_netwk_3 <X> glb2local_3
+(0 12) routing glb_netwk_6 <X> glb2local_3
+(0 12) routing glb_netwk_7 <X> glb2local_3
+(0 13) routing glb_netwk_1 <X> glb2local_3
+(0 13) routing glb_netwk_3 <X> glb2local_3
+(0 13) routing glb_netwk_5 <X> glb2local_3
+(0 13) routing glb_netwk_7 <X> glb2local_3
+(0 14) routing glb_netwk_4 <X> wire_bram/ram/WE
+(0 14) routing glb_netwk_6 <X> wire_bram/ram/WE
+(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/WE
+(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(0 15) routing glb_netwk_2 <X> wire_bram/ram/WE
+(0 15) routing glb_netwk_6 <X> wire_bram/ram/WE
+(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE
+(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(0 2) routing glb_netwk_2 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_3 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK
+(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_1 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_3 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_5 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK
+(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(0 4) routing glb_netwk_5 <X> wire_bram/ram/WCLKE
+(0 4) routing glb_netwk_7 <X> wire_bram/ram/WCLKE
+(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE
+(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(0 5) routing glb_netwk_3 <X> wire_bram/ram/WCLKE
+(0 5) routing glb_netwk_7 <X> wire_bram/ram/WCLKE
+(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE
+(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(0 6) routing glb_netwk_2 <X> glb2local_0
+(0 6) routing glb_netwk_3 <X> glb2local_0
+(0 6) routing glb_netwk_6 <X> glb2local_0
+(0 6) routing glb_netwk_7 <X> glb2local_0
+(0 7) routing glb_netwk_1 <X> glb2local_0
+(0 7) routing glb_netwk_3 <X> glb2local_0
+(0 7) routing glb_netwk_5 <X> glb2local_0
+(0 7) routing glb_netwk_7 <X> glb2local_0
+(0 8) routing glb_netwk_2 <X> glb2local_1
+(0 8) routing glb_netwk_3 <X> glb2local_1
+(0 8) routing glb_netwk_6 <X> glb2local_1
+(0 8) routing glb_netwk_7 <X> glb2local_1
+(0 9) routing glb_netwk_1 <X> glb2local_1
+(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_5 <X> glb2local_1
+(0 9) routing glb_netwk_7 <X> glb2local_1
+(1 0) Column buffer control bit: MEMB_colbuf_cntl_0
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2
+(1 11) routing glb_netwk_4 <X> glb2local_2
+(1 11) routing glb_netwk_5 <X> glb2local_2
+(1 11) routing glb_netwk_6 <X> glb2local_2
+(1 11) routing glb_netwk_7 <X> glb2local_2
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3
+(1 13) routing glb_netwk_4 <X> glb2local_3
+(1 13) routing glb_netwk_5 <X> glb2local_3
+(1 13) routing glb_netwk_6 <X> glb2local_3
+(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE
+(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(1 2) routing glb_netwk_4 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_5 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0
+(1 7) routing glb_netwk_4 <X> glb2local_0
+(1 7) routing glb_netwk_5 <X> glb2local_0
+(1 7) routing glb_netwk_6 <X> glb2local_0
+(1 7) routing glb_netwk_7 <X> glb2local_0
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
+(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_5 <X> glb2local_1
+(1 9) routing glb_netwk_6 <X> glb2local_1
+(1 9) routing glb_netwk_7 <X> glb2local_1
+(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(10 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(10 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(10 0) routing sp4_v_t_45 <X> sp4_h_r_1
+(10 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(10 1) routing sp4_h_r_8 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(10 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(10 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(10 10) routing sp4_v_b_2 <X> sp4_h_l_42
+(10 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(10 11) routing sp4_h_l_39 <X> sp4_v_t_42
+(10 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(10 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(10 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(10 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(10 12) routing sp4_v_t_40 <X> sp4_h_r_10
+(10 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(10 13) routing sp4_h_r_5 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(10 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(10 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(10 14) routing sp4_v_b_5 <X> sp4_h_l_47
+(10 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(10 15) routing sp4_h_l_40 <X> sp4_v_t_47
+(10 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(10 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(10 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(10 2) routing sp4_v_b_8 <X> sp4_h_l_36
+(10 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(10 3) routing sp4_h_l_45 <X> sp4_v_t_36
+(10 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(10 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(10 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(10 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(10 4) routing sp4_v_t_46 <X> sp4_h_r_4
+(10 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(10 5) routing sp4_h_r_11 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(10 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(10 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(10 6) routing sp4_v_b_11 <X> sp4_h_l_41
+(10 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(10 7) routing sp4_h_l_46 <X> sp4_v_t_41
+(10 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(10 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(10 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(10 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(10 8) routing sp4_v_t_39 <X> sp4_h_r_7
+(10 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(10 9) routing sp4_h_r_2 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_46 <X> sp4_v_b_7
+(11 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(11 0) routing sp4_h_r_9 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_46 <X> sp4_v_b_2
+(11 1) routing sp4_h_l_39 <X> sp4_h_r_2
+(11 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_2 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(11 10) routing sp4_h_l_38 <X> sp4_v_t_45
+(11 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_5 <X> sp4_v_t_45
+(11 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(11 11) routing sp4_h_r_8 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_45 <X> sp4_h_l_45
+(11 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(11 12) routing sp4_h_r_6 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_45 <X> sp4_v_b_11
+(11 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(11 13) routing sp4_h_l_46 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_11 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(11 14) routing sp4_h_l_43 <X> sp4_v_t_46
+(11 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_8 <X> sp4_v_t_46
+(11 15) routing sp4_h_r_11 <X> sp4_h_l_46
+(11 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_46 <X> sp4_h_l_46
+(11 2) routing sp4_h_l_44 <X> sp4_v_t_39
+(11 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_11 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(11 3) routing sp4_h_r_2 <X> sp4_h_l_39
+(11 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_39 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(11 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(11 4) routing sp4_h_r_0 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_39 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(11 5) routing sp4_h_l_40 <X> sp4_h_r_5
+(11 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_5 <X> sp4_h_r_5
+(11 6) routing sp4_h_l_37 <X> sp4_v_t_40
+(11 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_2 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(11 7) routing sp4_h_r_5 <X> sp4_h_l_40
+(11 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_40 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(11 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(11 8) routing sp4_h_r_3 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_40 <X> sp4_v_b_8
+(11 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(11 9) routing sp4_h_l_45 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 0) routing sp4_h_l_46 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_2 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_8 <X> sp4_h_r_2
+(12 0) routing sp4_v_t_39 <X> sp4_h_r_2
+(12 1) routing sp4_h_l_39 <X> sp4_v_b_2
+(12 1) routing sp4_h_l_45 <X> sp4_v_b_2
+(12 1) routing sp4_h_r_2 <X> sp4_v_b_2
+(12 1) routing sp4_v_t_46 <X> sp4_v_b_2
+(12 10) routing sp4_h_r_5 <X> sp4_h_l_45
+(12 10) routing sp4_v_b_8 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_39 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_45 <X> sp4_h_l_45
+(12 11) routing sp4_h_l_45 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_2 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_8 <X> sp4_v_t_45
+(12 11) routing sp4_v_b_5 <X> sp4_v_t_45
+(12 12) routing sp4_h_l_45 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_11 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_5 <X> sp4_h_r_11
+(12 12) routing sp4_v_t_46 <X> sp4_h_r_11
+(12 13) routing sp4_h_l_40 <X> sp4_v_b_11
+(12 13) routing sp4_h_l_46 <X> sp4_v_b_11
+(12 13) routing sp4_h_r_11 <X> sp4_v_b_11
+(12 13) routing sp4_v_t_45 <X> sp4_v_b_11
+(12 14) routing sp4_h_r_8 <X> sp4_h_l_46
+(12 14) routing sp4_v_b_11 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_40 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_46 <X> sp4_h_l_46
+(12 15) routing sp4_h_l_46 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_11 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_5 <X> sp4_v_t_46
+(12 15) routing sp4_v_b_8 <X> sp4_v_t_46
+(12 2) routing sp4_h_r_11 <X> sp4_h_l_39
+(12 2) routing sp4_v_b_2 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_39 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_45 <X> sp4_h_l_39
+(12 3) routing sp4_h_l_39 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_2 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_8 <X> sp4_v_t_39
+(12 3) routing sp4_v_b_11 <X> sp4_v_t_39
+(12 4) routing sp4_h_l_39 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_11 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_5 <X> sp4_h_r_5
+(12 4) routing sp4_v_t_40 <X> sp4_h_r_5
+(12 5) routing sp4_h_l_40 <X> sp4_v_b_5
+(12 5) routing sp4_h_l_46 <X> sp4_v_b_5
+(12 5) routing sp4_h_r_5 <X> sp4_v_b_5
+(12 5) routing sp4_v_t_39 <X> sp4_v_b_5
+(12 6) routing sp4_h_r_2 <X> sp4_h_l_40
+(12 6) routing sp4_v_b_5 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_40 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_46 <X> sp4_h_l_40
+(12 7) routing sp4_h_l_40 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_11 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_5 <X> sp4_v_t_40
+(12 7) routing sp4_v_b_2 <X> sp4_v_t_40
+(12 8) routing sp4_h_l_40 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_2 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 8) routing sp4_v_t_45 <X> sp4_h_r_8
+(12 9) routing sp4_h_l_39 <X> sp4_v_b_8
+(12 9) routing sp4_h_l_45 <X> sp4_v_b_8
+(12 9) routing sp4_h_r_8 <X> sp4_v_b_8
+(12 9) routing sp4_v_t_40 <X> sp4_v_b_8
+(13 0) routing sp4_h_l_39 <X> sp4_v_b_2
+(13 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_39 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(13 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(13 1) routing sp4_h_l_46 <X> sp4_h_r_2
+(13 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(13 1) routing sp4_v_t_44 <X> sp4_h_r_2
+(13 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(13 10) routing sp4_h_r_8 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_8 <X> sp4_v_t_45
+(13 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(13 11) routing sp4_h_r_5 <X> sp4_h_l_45
+(13 11) routing sp4_v_b_3 <X> sp4_h_l_45
+(13 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(13 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(13 12) routing sp4_h_l_46 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_46 <X> sp4_v_b_11
+(13 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(13 13) routing sp4_h_l_45 <X> sp4_h_r_11
+(13 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(13 13) routing sp4_v_t_43 <X> sp4_h_r_11
+(13 14) routing sp4_h_r_11 <X> sp4_v_t_46
+(13 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_11 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(13 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(13 15) routing sp4_h_r_8 <X> sp4_h_l_46
+(13 15) routing sp4_v_b_6 <X> sp4_h_l_46
+(13 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(13 2) routing sp4_h_r_2 <X> sp4_v_t_39
+(13 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_2 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(13 3) routing sp4_h_r_11 <X> sp4_h_l_39
+(13 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(13 3) routing sp4_v_b_9 <X> sp4_h_l_39
+(13 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(13 4) routing sp4_h_l_40 <X> sp4_v_b_5
+(13 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_40 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(13 5) routing sp4_h_l_39 <X> sp4_h_r_5
+(13 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(13 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(13 5) routing sp4_v_t_37 <X> sp4_h_r_5
+(13 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(13 6) routing sp4_h_r_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(13 7) routing sp4_h_r_2 <X> sp4_h_l_40
+(13 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(13 7) routing sp4_v_b_0 <X> sp4_h_l_40
+(13 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(13 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(13 8) routing sp4_h_l_45 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_45 <X> sp4_v_b_8
+(13 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(13 9) routing sp4_h_l_40 <X> sp4_h_r_8
+(13 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(13 9) routing sp4_v_t_38 <X> sp4_h_r_8
+(14 0) routing bnr_op_0 <X> lc_trk_g0_0
+(14 0) routing lft_op_0 <X> lc_trk_g0_0
+(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing bnr_op_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0
+(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 10) routing bnl_op_4 <X> lc_trk_g2_4
+(14 10) routing rgt_op_4 <X> lc_trk_g2_4
+(14 10) routing sp12_v_b_4 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4
+(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing bnl_op_4 <X> lc_trk_g2_4
+(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(14 11) routing sp12_v_b_4 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4
+(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing tnl_op_4 <X> lc_trk_g2_4
+(14 12) routing bnl_op_0 <X> lc_trk_g3_0
+(14 12) routing rgt_op_0 <X> lc_trk_g3_0
+(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 12) routing sp4_h_r_32 <X> lc_trk_g3_0
+(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 12) routing sp4_v_b_32 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0
+(14 13) routing bnl_op_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0
+(14 13) routing sp4_v_b_32 <X> lc_trk_g3_0
+(14 13) routing tnl_op_0 <X> lc_trk_g3_0
+(14 14) routing bnl_op_4 <X> lc_trk_g3_4
+(14 14) routing rgt_op_4 <X> lc_trk_g3_4
+(14 14) routing sp12_v_b_4 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4
+(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing bnl_op_4 <X> lc_trk_g3_4
+(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(14 15) routing sp12_v_b_4 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4
+(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing tnl_op_4 <X> lc_trk_g3_4
+(14 2) routing bnr_op_4 <X> lc_trk_g0_4
+(14 2) routing lft_op_4 <X> lc_trk_g0_4
+(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_1 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_12 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4
+(14 3) routing bnr_op_4 <X> lc_trk_g0_4
+(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4
+(14 3) routing sp4_v_b_12 <X> lc_trk_g0_4
+(14 4) routing bnr_op_0 <X> lc_trk_g1_0
+(14 4) routing lft_op_0 <X> lc_trk_g1_0
+(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing bnr_op_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0
+(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 6) routing bnr_op_4 <X> lc_trk_g1_4
+(14 6) routing lft_op_4 <X> lc_trk_g1_4
+(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_1 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_12 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4
+(14 7) routing bnr_op_4 <X> lc_trk_g1_4
+(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4
+(14 7) routing sp4_v_b_12 <X> lc_trk_g1_4
+(14 8) routing bnl_op_0 <X> lc_trk_g2_0
+(14 8) routing rgt_op_0 <X> lc_trk_g2_0
+(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0
+(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 8) routing sp4_v_b_32 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0
+(14 9) routing bnl_op_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0
+(14 9) routing sp4_v_b_32 <X> lc_trk_g2_0
+(14 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 0) routing lft_op_1 <X> lc_trk_g0_1
+(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(15 0) routing sp4_v_t_4 <X> lc_trk_g0_1
+(15 1) routing bot_op_0 <X> lc_trk_g0_0
+(15 1) routing lft_op_0 <X> lc_trk_g0_0
+(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(15 10) routing rgt_op_5 <X> lc_trk_g2_5
+(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_29 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(15 10) routing tnl_op_5 <X> lc_trk_g2_5
+(15 10) routing tnr_op_5 <X> lc_trk_g2_5
+(15 11) routing rgt_op_4 <X> lc_trk_g2_4
+(15 11) routing sp12_v_b_4 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(15 11) routing sp4_v_b_44 <X> lc_trk_g2_4
+(15 11) routing tnl_op_4 <X> lc_trk_g2_4
+(15 11) routing tnr_op_4 <X> lc_trk_g2_4
+(15 12) routing rgt_op_1 <X> lc_trk_g3_1
+(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(15 12) routing tnl_op_1 <X> lc_trk_g3_1
+(15 12) routing tnr_op_1 <X> lc_trk_g3_1
+(15 13) routing rgt_op_0 <X> lc_trk_g3_0
+(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_32 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(15 13) routing tnl_op_0 <X> lc_trk_g3_0
+(15 13) routing tnr_op_0 <X> lc_trk_g3_0
+(15 14) routing rgt_op_5 <X> lc_trk_g3_5
+(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(15 14) routing tnl_op_5 <X> lc_trk_g3_5
+(15 14) routing tnr_op_5 <X> lc_trk_g3_5
+(15 15) routing rgt_op_4 <X> lc_trk_g3_4
+(15 15) routing sp12_v_b_4 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(15 15) routing sp4_v_b_44 <X> lc_trk_g3_4
+(15 15) routing tnl_op_4 <X> lc_trk_g3_4
+(15 15) routing tnr_op_4 <X> lc_trk_g3_4
+(15 2) routing lft_op_5 <X> lc_trk_g0_5
+(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(15 3) routing bot_op_4 <X> lc_trk_g0_4
+(15 3) routing lft_op_4 <X> lc_trk_g0_4
+(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(15 4) routing lft_op_1 <X> lc_trk_g1_1
+(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(15 4) routing sp4_v_t_4 <X> lc_trk_g1_1
+(15 5) routing bot_op_0 <X> lc_trk_g1_0
+(15 5) routing lft_op_0 <X> lc_trk_g1_0
+(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(15 6) routing lft_op_5 <X> lc_trk_g1_5
+(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(15 7) routing bot_op_4 <X> lc_trk_g1_4
+(15 7) routing lft_op_4 <X> lc_trk_g1_4
+(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(15 8) routing rgt_op_1 <X> lc_trk_g2_1
+(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(15 8) routing tnl_op_1 <X> lc_trk_g2_1
+(15 8) routing tnr_op_1 <X> lc_trk_g2_1
+(15 9) routing rgt_op_0 <X> lc_trk_g2_0
+(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(15 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 9) routing tnr_op_0 <X> lc_trk_g2_0
+(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1
+(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_t_4 <X> lc_trk_g0_1
+(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0
+(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(16 10) routing sp12_v_b_13 <X> lc_trk_g2_5
+(16 10) routing sp12_v_t_18 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_29 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_t_24 <X> lc_trk_g2_5
+(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(16 11) routing sp12_v_t_11 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1
+(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1
+(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_32 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_32 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0
+(16 14) routing sp12_v_b_13 <X> lc_trk_g3_5
+(16 14) routing sp12_v_t_18 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_t_24 <X> lc_trk_g3_5
+(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(16 15) routing sp12_v_t_11 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5
+(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_12 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4
+(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1
+(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_t_4 <X> lc_trk_g1_1
+(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0
+(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5
+(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_12 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4
+(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1
+(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1
+(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_32 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0
+(18 0) routing bnr_op_1 <X> lc_trk_g0_1
+(18 0) routing lft_op_1 <X> lc_trk_g0_1
+(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 1) routing bnr_op_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1
+(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 10) routing bnl_op_5 <X> lc_trk_g2_5
+(18 10) routing rgt_op_5 <X> lc_trk_g2_5
+(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(18 10) routing sp4_v_t_24 <X> lc_trk_g2_5
+(18 11) routing bnl_op_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_t_18 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_29 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5
+(18 11) routing sp4_v_t_24 <X> lc_trk_g2_5
+(18 11) routing tnl_op_5 <X> lc_trk_g2_5
+(18 12) routing bnl_op_1 <X> lc_trk_g3_1
+(18 12) routing rgt_op_1 <X> lc_trk_g3_1
+(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1
+(18 13) routing bnl_op_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1
+(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1
+(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1
+(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1
+(18 13) routing tnl_op_1 <X> lc_trk_g3_1
+(18 14) routing bnl_op_5 <X> lc_trk_g3_5
+(18 14) routing rgt_op_5 <X> lc_trk_g3_5
+(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(18 14) routing sp4_v_t_24 <X> lc_trk_g3_5
+(18 15) routing bnl_op_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_t_18 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5
+(18 15) routing sp4_v_t_24 <X> lc_trk_g3_5
+(18 15) routing tnl_op_5 <X> lc_trk_g3_5
+(18 2) routing bnr_op_5 <X> lc_trk_g0_5
+(18 2) routing lft_op_5 <X> lc_trk_g0_5
+(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(18 3) routing bnr_op_5 <X> lc_trk_g0_5
+(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5
+(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5
+(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 4) routing bnr_op_1 <X> lc_trk_g1_1
+(18 4) routing lft_op_1 <X> lc_trk_g1_1
+(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 5) routing bnr_op_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1
+(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 6) routing bnr_op_5 <X> lc_trk_g1_5
+(18 6) routing lft_op_5 <X> lc_trk_g1_5
+(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(18 7) routing bnr_op_5 <X> lc_trk_g1_5
+(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5
+(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5
+(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 8) routing bnl_op_1 <X> lc_trk_g2_1
+(18 8) routing rgt_op_1 <X> lc_trk_g2_1
+(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1
+(18 9) routing bnl_op_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1
+(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1
+(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1
+(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1
+(18 9) routing tnl_op_1 <X> lc_trk_g2_1
+(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13
+(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12
+(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23
+(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11
+(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13
+(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1
+(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15
+(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3
+(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2
+(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14
+(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4
+(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16
+(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6
+(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7
+(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8
+(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20
+(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16
+(2 1) Column buffer control bit: MEMB_colbuf_cntl_1
+(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21
+(2 11) Column buffer control bit: MEMB_colbuf_cntl_5
+(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11
+(2 13) Column buffer control bit: MEMB_colbuf_cntl_6
+(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23
+(2 15) Column buffer control bit: MEMB_colbuf_cntl_7
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK
+(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18
+(2 5) Column buffer control bit: MEMB_colbuf_cntl_2
+(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6
+(2 7) Column buffer control bit: MEMB_colbuf_cntl_3
+(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9
+(2 9) Column buffer control bit: MEMB_colbuf_cntl_4
+(21 0) routing bnr_op_3 <X> lc_trk_g0_3
+(21 0) routing lft_op_3 <X> lc_trk_g0_3
+(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(21 1) routing bnr_op_3 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3
+(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_h_l_6 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3
+(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 10) routing bnl_op_7 <X> lc_trk_g2_7
+(21 10) routing rgt_op_7 <X> lc_trk_g2_7
+(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7
+(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 10) routing sp4_v_b_31 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing bnl_op_7 <X> lc_trk_g2_7
+(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7
+(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_31 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7
+(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing tnl_op_7 <X> lc_trk_g2_7
+(21 12) routing bnl_op_3 <X> lc_trk_g3_3
+(21 12) routing rgt_op_3 <X> lc_trk_g3_3
+(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3
+(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3
+(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3
+(21 13) routing bnl_op_3 <X> lc_trk_g3_3
+(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3
+(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3
+(21 13) routing sp4_h_l_14 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3
+(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3
+(21 13) routing tnl_op_3 <X> lc_trk_g3_3
+(21 14) routing bnl_op_7 <X> lc_trk_g3_7
+(21 14) routing rgt_op_7 <X> lc_trk_g3_7
+(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7
+(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 14) routing sp4_v_b_31 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing bnl_op_7 <X> lc_trk_g3_7
+(21 15) routing sp12_v_t_20 <X> lc_trk_g3_7
+(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7
+(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing tnl_op_7 <X> lc_trk_g3_7
+(21 2) routing bnr_op_7 <X> lc_trk_g0_7
+(21 2) routing lft_op_7 <X> lc_trk_g0_7
+(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7
+(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(21 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 3) routing bnr_op_7 <X> lc_trk_g0_7
+(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7
+(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_23 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7
+(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 4) routing bnr_op_3 <X> lc_trk_g1_3
+(21 4) routing lft_op_3 <X> lc_trk_g1_3
+(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(21 5) routing bnr_op_3 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3
+(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_h_l_6 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3
+(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 6) routing bnr_op_7 <X> lc_trk_g1_7
+(21 6) routing lft_op_7 <X> lc_trk_g1_7
+(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7
+(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(21 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 7) routing bnr_op_7 <X> lc_trk_g1_7
+(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7
+(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_23 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7
+(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 8) routing bnl_op_3 <X> lc_trk_g2_3
+(21 8) routing rgt_op_3 <X> lc_trk_g2_3
+(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3
+(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3
+(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3
+(21 9) routing bnl_op_3 <X> lc_trk_g2_3
+(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3
+(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3
+(21 9) routing sp4_h_l_14 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3
+(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3
+(21 9) routing tnl_op_3 <X> lc_trk_g2_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2
+(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3
+(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_t_6 <X> lc_trk_g0_3
+(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7
+(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_b_31 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7
+(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6
+(23 11) routing sp12_v_b_22 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6
+(23 11) routing sp4_v_t_27 <X> lc_trk_g2_6
+(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3
+(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_14 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_43 <X> lc_trk_g3_3
+(23 13) routing sp12_v_b_10 <X> lc_trk_g3_2
+(23 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_34 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7
+(23 14) routing sp12_v_t_20 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_b_31 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7
+(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6
+(23 15) routing sp12_v_b_22 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_t_19 <X> lc_trk_g3_6
+(23 15) routing sp4_v_t_27 <X> lc_trk_g3_6
+(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7
+(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6
+(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6
+(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3
+(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_t_6 <X> lc_trk_g1_3
+(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7
+(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6
+(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6
+(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3
+(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_14 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_43 <X> lc_trk_g2_3
+(23 9) routing sp12_v_b_10 <X> lc_trk_g2_2
+(23 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_34 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 0) routing lft_op_3 <X> lc_trk_g0_3
+(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_v_t_6 <X> lc_trk_g0_3
+(24 1) routing bot_op_2 <X> lc_trk_g0_2
+(24 1) routing lft_op_2 <X> lc_trk_g0_2
+(24 1) routing sp12_h_l_1 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(24 10) routing rgt_op_7 <X> lc_trk_g2_7
+(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7
+(24 10) routing tnl_op_7 <X> lc_trk_g2_7
+(24 10) routing tnr_op_7 <X> lc_trk_g2_7
+(24 11) routing rgt_op_6 <X> lc_trk_g2_6
+(24 11) routing sp12_v_t_5 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(24 11) routing tnl_op_6 <X> lc_trk_g2_6
+(24 11) routing tnr_op_6 <X> lc_trk_g2_6
+(24 12) routing rgt_op_3 <X> lc_trk_g3_3
+(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_14 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(24 12) routing sp4_v_b_43 <X> lc_trk_g3_3
+(24 12) routing tnl_op_3 <X> lc_trk_g3_3
+(24 12) routing tnr_op_3 <X> lc_trk_g3_3
+(24 13) routing rgt_op_2 <X> lc_trk_g3_2
+(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(24 13) routing tnl_op_2 <X> lc_trk_g3_2
+(24 13) routing tnr_op_2 <X> lc_trk_g3_2
+(24 14) routing rgt_op_7 <X> lc_trk_g3_7
+(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7
+(24 14) routing tnl_op_7 <X> lc_trk_g3_7
+(24 14) routing tnr_op_7 <X> lc_trk_g3_7
+(24 15) routing rgt_op_6 <X> lc_trk_g3_6
+(24 15) routing sp12_v_t_5 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(24 15) routing tnl_op_6 <X> lc_trk_g3_6
+(24 15) routing tnr_op_6 <X> lc_trk_g3_6
+(24 2) routing lft_op_7 <X> lc_trk_g0_7
+(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(24 3) routing bot_op_6 <X> lc_trk_g0_6
+(24 3) routing lft_op_6 <X> lc_trk_g0_6
+(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6
+(24 4) routing lft_op_3 <X> lc_trk_g1_3
+(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_v_t_6 <X> lc_trk_g1_3
+(24 5) routing bot_op_2 <X> lc_trk_g1_2
+(24 5) routing lft_op_2 <X> lc_trk_g1_2
+(24 5) routing sp12_h_l_1 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(24 6) routing lft_op_7 <X> lc_trk_g1_7
+(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(24 7) routing bot_op_6 <X> lc_trk_g1_6
+(24 7) routing lft_op_6 <X> lc_trk_g1_6
+(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6
+(24 8) routing rgt_op_3 <X> lc_trk_g2_3
+(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_14 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(24 8) routing sp4_v_b_43 <X> lc_trk_g2_3
+(24 8) routing tnl_op_3 <X> lc_trk_g2_3
+(24 8) routing tnr_op_3 <X> lc_trk_g2_3
+(24 9) routing rgt_op_2 <X> lc_trk_g2_2
+(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 9) routing tnl_op_2 <X> lc_trk_g2_2
+(24 9) routing tnr_op_2 <X> lc_trk_g2_2
+(25 0) routing bnr_op_2 <X> lc_trk_g0_2
+(25 0) routing lft_op_2 <X> lc_trk_g0_2
+(25 0) routing sp12_h_l_1 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_18 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2
+(25 1) routing bnr_op_2 <X> lc_trk_g0_2
+(25 1) routing sp12_h_l_1 <X> lc_trk_g0_2
+(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2
+(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 10) routing bnl_op_6 <X> lc_trk_g2_6
+(25 10) routing rgt_op_6 <X> lc_trk_g2_6
+(25 10) routing sp12_v_t_5 <X> lc_trk_g2_6
+(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6
+(25 10) routing sp4_v_t_27 <X> lc_trk_g2_6
+(25 11) routing bnl_op_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_b_22 <X> lc_trk_g2_6
+(25 11) routing sp12_v_t_5 <X> lc_trk_g2_6
+(25 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6
+(25 11) routing sp4_v_t_27 <X> lc_trk_g2_6
+(25 11) routing tnl_op_6 <X> lc_trk_g2_6
+(25 12) routing bnl_op_2 <X> lc_trk_g3_2
+(25 12) routing rgt_op_2 <X> lc_trk_g3_2
+(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 12) routing sp4_v_b_34 <X> lc_trk_g3_2
+(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2
+(25 13) routing bnl_op_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2
+(25 13) routing sp4_v_b_34 <X> lc_trk_g3_2
+(25 13) routing tnl_op_2 <X> lc_trk_g3_2
+(25 14) routing bnl_op_6 <X> lc_trk_g3_6
+(25 14) routing rgt_op_6 <X> lc_trk_g3_6
+(25 14) routing sp12_v_t_5 <X> lc_trk_g3_6
+(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 14) routing sp4_v_t_19 <X> lc_trk_g3_6
+(25 14) routing sp4_v_t_27 <X> lc_trk_g3_6
+(25 15) routing bnl_op_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_b_22 <X> lc_trk_g3_6
+(25 15) routing sp12_v_t_5 <X> lc_trk_g3_6
+(25 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6
+(25 15) routing sp4_v_t_27 <X> lc_trk_g3_6
+(25 15) routing tnl_op_6 <X> lc_trk_g3_6
+(25 2) routing bnr_op_6 <X> lc_trk_g0_6
+(25 2) routing lft_op_6 <X> lc_trk_g0_6
+(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6
+(25 3) routing bnr_op_6 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6
+(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6
+(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 4) routing bnr_op_2 <X> lc_trk_g1_2
+(25 4) routing lft_op_2 <X> lc_trk_g1_2
+(25 4) routing sp12_h_l_1 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_18 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2
+(25 5) routing bnr_op_2 <X> lc_trk_g1_2
+(25 5) routing sp12_h_l_1 <X> lc_trk_g1_2
+(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2
+(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 6) routing bnr_op_6 <X> lc_trk_g1_6
+(25 6) routing lft_op_6 <X> lc_trk_g1_6
+(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6
+(25 7) routing bnr_op_6 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6
+(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6
+(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 8) routing bnl_op_2 <X> lc_trk_g2_2
+(25 8) routing rgt_op_2 <X> lc_trk_g2_2
+(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 8) routing sp4_v_b_34 <X> lc_trk_g2_2
+(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2
+(25 9) routing bnl_op_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2
+(25 9) routing sp4_v_b_34 <X> lc_trk_g2_2
+(25 9) routing tnl_op_2 <X> lc_trk_g2_2
+(26 0) routing lc_trk_g0_4 <X> input0_0
+(26 0) routing lc_trk_g0_6 <X> input0_0
+(26 0) routing lc_trk_g1_5 <X> input0_0
+(26 0) routing lc_trk_g1_7 <X> input0_0
+(26 0) routing lc_trk_g2_4 <X> input0_0
+(26 0) routing lc_trk_g2_6 <X> input0_0
+(26 0) routing lc_trk_g3_5 <X> input0_0
+(26 0) routing lc_trk_g3_7 <X> input0_0
+(26 1) routing lc_trk_g0_2 <X> input0_0
+(26 1) routing lc_trk_g0_6 <X> input0_0
+(26 1) routing lc_trk_g1_3 <X> input0_0
+(26 1) routing lc_trk_g1_7 <X> input0_0
+(26 1) routing lc_trk_g2_2 <X> input0_0
+(26 1) routing lc_trk_g2_6 <X> input0_0
+(26 1) routing lc_trk_g3_3 <X> input0_0
+(26 1) routing lc_trk_g3_7 <X> input0_0
+(26 10) routing lc_trk_g0_5 <X> input0_5
+(26 10) routing lc_trk_g0_7 <X> input0_5
+(26 10) routing lc_trk_g1_4 <X> input0_5
+(26 10) routing lc_trk_g1_6 <X> input0_5
+(26 10) routing lc_trk_g2_5 <X> input0_5
+(26 10) routing lc_trk_g2_7 <X> input0_5
+(26 10) routing lc_trk_g3_4 <X> input0_5
+(26 10) routing lc_trk_g3_6 <X> input0_5
+(26 11) routing lc_trk_g0_3 <X> input0_5
+(26 11) routing lc_trk_g0_7 <X> input0_5
+(26 11) routing lc_trk_g1_2 <X> input0_5
+(26 11) routing lc_trk_g1_6 <X> input0_5
+(26 11) routing lc_trk_g2_3 <X> input0_5
+(26 11) routing lc_trk_g2_7 <X> input0_5
+(26 11) routing lc_trk_g3_2 <X> input0_5
+(26 11) routing lc_trk_g3_6 <X> input0_5
+(26 12) routing lc_trk_g0_4 <X> input0_6
+(26 12) routing lc_trk_g0_6 <X> input0_6
+(26 12) routing lc_trk_g1_5 <X> input0_6
+(26 12) routing lc_trk_g1_7 <X> input0_6
+(26 12) routing lc_trk_g2_4 <X> input0_6
+(26 12) routing lc_trk_g2_6 <X> input0_6
+(26 12) routing lc_trk_g3_5 <X> input0_6
+(26 12) routing lc_trk_g3_7 <X> input0_6
+(26 13) routing lc_trk_g0_2 <X> input0_6
+(26 13) routing lc_trk_g0_6 <X> input0_6
+(26 13) routing lc_trk_g1_3 <X> input0_6
+(26 13) routing lc_trk_g1_7 <X> input0_6
+(26 13) routing lc_trk_g2_2 <X> input0_6
+(26 13) routing lc_trk_g2_6 <X> input0_6
+(26 13) routing lc_trk_g3_3 <X> input0_6
+(26 13) routing lc_trk_g3_7 <X> input0_6
+(26 14) routing lc_trk_g0_5 <X> input0_7
+(26 14) routing lc_trk_g0_7 <X> input0_7
+(26 14) routing lc_trk_g1_4 <X> input0_7
+(26 14) routing lc_trk_g1_6 <X> input0_7
+(26 14) routing lc_trk_g2_5 <X> input0_7
+(26 14) routing lc_trk_g2_7 <X> input0_7
+(26 14) routing lc_trk_g3_4 <X> input0_7
+(26 14) routing lc_trk_g3_6 <X> input0_7
+(26 15) routing lc_trk_g0_3 <X> input0_7
+(26 15) routing lc_trk_g0_7 <X> input0_7
+(26 15) routing lc_trk_g1_2 <X> input0_7
+(26 15) routing lc_trk_g1_6 <X> input0_7
+(26 15) routing lc_trk_g2_3 <X> input0_7
+(26 15) routing lc_trk_g2_7 <X> input0_7
+(26 15) routing lc_trk_g3_2 <X> input0_7
+(26 15) routing lc_trk_g3_6 <X> input0_7
+(26 2) routing lc_trk_g0_5 <X> input0_1
+(26 2) routing lc_trk_g0_7 <X> input0_1
+(26 2) routing lc_trk_g1_4 <X> input0_1
+(26 2) routing lc_trk_g1_6 <X> input0_1
+(26 2) routing lc_trk_g2_5 <X> input0_1
+(26 2) routing lc_trk_g2_7 <X> input0_1
+(26 2) routing lc_trk_g3_4 <X> input0_1
+(26 2) routing lc_trk_g3_6 <X> input0_1
+(26 3) routing lc_trk_g0_3 <X> input0_1
+(26 3) routing lc_trk_g0_7 <X> input0_1
+(26 3) routing lc_trk_g1_2 <X> input0_1
+(26 3) routing lc_trk_g1_6 <X> input0_1
+(26 3) routing lc_trk_g2_3 <X> input0_1
+(26 3) routing lc_trk_g2_7 <X> input0_1
+(26 3) routing lc_trk_g3_2 <X> input0_1
+(26 3) routing lc_trk_g3_6 <X> input0_1
+(26 4) routing lc_trk_g0_4 <X> input0_2
+(26 4) routing lc_trk_g0_6 <X> input0_2
+(26 4) routing lc_trk_g1_5 <X> input0_2
+(26 4) routing lc_trk_g1_7 <X> input0_2
+(26 4) routing lc_trk_g2_4 <X> input0_2
+(26 4) routing lc_trk_g2_6 <X> input0_2
+(26 4) routing lc_trk_g3_5 <X> input0_2
+(26 4) routing lc_trk_g3_7 <X> input0_2
+(26 5) routing lc_trk_g0_2 <X> input0_2
+(26 5) routing lc_trk_g0_6 <X> input0_2
+(26 5) routing lc_trk_g1_3 <X> input0_2
+(26 5) routing lc_trk_g1_7 <X> input0_2
+(26 5) routing lc_trk_g2_2 <X> input0_2
+(26 5) routing lc_trk_g2_6 <X> input0_2
+(26 5) routing lc_trk_g3_3 <X> input0_2
+(26 5) routing lc_trk_g3_7 <X> input0_2
+(26 6) routing lc_trk_g0_5 <X> input0_3
+(26 6) routing lc_trk_g0_7 <X> input0_3
+(26 6) routing lc_trk_g1_4 <X> input0_3
+(26 6) routing lc_trk_g1_6 <X> input0_3
+(26 6) routing lc_trk_g2_5 <X> input0_3
+(26 6) routing lc_trk_g2_7 <X> input0_3
+(26 6) routing lc_trk_g3_4 <X> input0_3
+(26 6) routing lc_trk_g3_6 <X> input0_3
+(26 7) routing lc_trk_g0_3 <X> input0_3
+(26 7) routing lc_trk_g0_7 <X> input0_3
+(26 7) routing lc_trk_g1_2 <X> input0_3
+(26 7) routing lc_trk_g1_6 <X> input0_3
+(26 7) routing lc_trk_g2_3 <X> input0_3
+(26 7) routing lc_trk_g2_7 <X> input0_3
+(26 7) routing lc_trk_g3_2 <X> input0_3
+(26 7) routing lc_trk_g3_6 <X> input0_3
+(26 8) routing lc_trk_g0_4 <X> input0_4
+(26 8) routing lc_trk_g0_6 <X> input0_4
+(26 8) routing lc_trk_g1_5 <X> input0_4
+(26 8) routing lc_trk_g1_7 <X> input0_4
+(26 8) routing lc_trk_g2_4 <X> input0_4
+(26 8) routing lc_trk_g2_6 <X> input0_4
+(26 8) routing lc_trk_g3_5 <X> input0_4
+(26 8) routing lc_trk_g3_7 <X> input0_4
+(26 9) routing lc_trk_g0_2 <X> input0_4
+(26 9) routing lc_trk_g0_6 <X> input0_4
+(26 9) routing lc_trk_g1_3 <X> input0_4
+(26 9) routing lc_trk_g1_7 <X> input0_4
+(26 9) routing lc_trk_g2_2 <X> input0_4
+(26 9) routing lc_trk_g2_6 <X> input0_4
+(26 9) routing lc_trk_g3_3 <X> input0_4
+(26 9) routing lc_trk_g3_7 <X> input0_4
+(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_0
+(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_0
+(27 1) routing lc_trk_g1_1 <X> input0_0
+(27 1) routing lc_trk_g1_3 <X> input0_0
+(27 1) routing lc_trk_g1_5 <X> input0_0
+(27 1) routing lc_trk_g1_7 <X> input0_0
+(27 1) routing lc_trk_g3_1 <X> input0_0
+(27 1) routing lc_trk_g3_3 <X> input0_0
+(27 1) routing lc_trk_g3_5 <X> input0_0
+(27 1) routing lc_trk_g3_7 <X> input0_0
+(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_5
+(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_5
+(27 11) routing lc_trk_g1_0 <X> input0_5
+(27 11) routing lc_trk_g1_2 <X> input0_5
+(27 11) routing lc_trk_g1_4 <X> input0_5
+(27 11) routing lc_trk_g1_6 <X> input0_5
+(27 11) routing lc_trk_g3_0 <X> input0_5
+(27 11) routing lc_trk_g3_2 <X> input0_5
+(27 11) routing lc_trk_g3_4 <X> input0_5
+(27 11) routing lc_trk_g3_6 <X> input0_5
+(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_6
+(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_6
+(27 13) routing lc_trk_g1_1 <X> input0_6
+(27 13) routing lc_trk_g1_3 <X> input0_6
+(27 13) routing lc_trk_g1_5 <X> input0_6
+(27 13) routing lc_trk_g1_7 <X> input0_6
+(27 13) routing lc_trk_g3_1 <X> input0_6
+(27 13) routing lc_trk_g3_3 <X> input0_6
+(27 13) routing lc_trk_g3_5 <X> input0_6
+(27 13) routing lc_trk_g3_7 <X> input0_6
+(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_7
+(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_7
+(27 15) routing lc_trk_g1_0 <X> input0_7
+(27 15) routing lc_trk_g1_2 <X> input0_7
+(27 15) routing lc_trk_g1_4 <X> input0_7
+(27 15) routing lc_trk_g1_6 <X> input0_7
+(27 15) routing lc_trk_g3_0 <X> input0_7
+(27 15) routing lc_trk_g3_2 <X> input0_7
+(27 15) routing lc_trk_g3_4 <X> input0_7
+(27 15) routing lc_trk_g3_6 <X> input0_7
+(27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_1
+(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_1
+(27 3) routing lc_trk_g1_0 <X> input0_1
+(27 3) routing lc_trk_g1_2 <X> input0_1
+(27 3) routing lc_trk_g1_4 <X> input0_1
+(27 3) routing lc_trk_g1_6 <X> input0_1
+(27 3) routing lc_trk_g3_0 <X> input0_1
+(27 3) routing lc_trk_g3_2 <X> input0_1
+(27 3) routing lc_trk_g3_4 <X> input0_1
+(27 3) routing lc_trk_g3_6 <X> input0_1
+(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_2
+(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_2
+(27 5) routing lc_trk_g1_1 <X> input0_2
+(27 5) routing lc_trk_g1_3 <X> input0_2
+(27 5) routing lc_trk_g1_5 <X> input0_2
+(27 5) routing lc_trk_g1_7 <X> input0_2
+(27 5) routing lc_trk_g3_1 <X> input0_2
+(27 5) routing lc_trk_g3_3 <X> input0_2
+(27 5) routing lc_trk_g3_5 <X> input0_2
+(27 5) routing lc_trk_g3_7 <X> input0_2
+(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_3
+(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_3
+(27 7) routing lc_trk_g1_0 <X> input0_3
+(27 7) routing lc_trk_g1_2 <X> input0_3
+(27 7) routing lc_trk_g1_4 <X> input0_3
+(27 7) routing lc_trk_g1_6 <X> input0_3
+(27 7) routing lc_trk_g3_0 <X> input0_3
+(27 7) routing lc_trk_g3_2 <X> input0_3
+(27 7) routing lc_trk_g3_4 <X> input0_3
+(27 7) routing lc_trk_g3_6 <X> input0_3
+(27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_4
+(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_4
+(27 9) routing lc_trk_g1_1 <X> input0_4
+(27 9) routing lc_trk_g1_3 <X> input0_4
+(27 9) routing lc_trk_g1_5 <X> input0_4
+(27 9) routing lc_trk_g1_7 <X> input0_4
+(27 9) routing lc_trk_g3_1 <X> input0_4
+(27 9) routing lc_trk_g3_3 <X> input0_4
+(27 9) routing lc_trk_g3_5 <X> input0_4
+(27 9) routing lc_trk_g3_7 <X> input0_4
+(28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_0
+(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_0
+(28 1) routing lc_trk_g2_0 <X> input0_0
+(28 1) routing lc_trk_g2_2 <X> input0_0
+(28 1) routing lc_trk_g2_4 <X> input0_0
+(28 1) routing lc_trk_g2_6 <X> input0_0
+(28 1) routing lc_trk_g3_1 <X> input0_0
+(28 1) routing lc_trk_g3_3 <X> input0_0
+(28 1) routing lc_trk_g3_5 <X> input0_0
+(28 1) routing lc_trk_g3_7 <X> input0_0
+(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_5
+(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_5
+(28 11) routing lc_trk_g2_1 <X> input0_5
+(28 11) routing lc_trk_g2_3 <X> input0_5
+(28 11) routing lc_trk_g2_5 <X> input0_5
+(28 11) routing lc_trk_g2_7 <X> input0_5
+(28 11) routing lc_trk_g3_0 <X> input0_5
+(28 11) routing lc_trk_g3_2 <X> input0_5
+(28 11) routing lc_trk_g3_4 <X> input0_5
+(28 11) routing lc_trk_g3_6 <X> input0_5
+(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_6
+(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_6
+(28 13) routing lc_trk_g2_0 <X> input0_6
+(28 13) routing lc_trk_g2_2 <X> input0_6
+(28 13) routing lc_trk_g2_4 <X> input0_6
+(28 13) routing lc_trk_g2_6 <X> input0_6
+(28 13) routing lc_trk_g3_1 <X> input0_6
+(28 13) routing lc_trk_g3_3 <X> input0_6
+(28 13) routing lc_trk_g3_5 <X> input0_6
+(28 13) routing lc_trk_g3_7 <X> input0_6
+(28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_7
+(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_7
+(28 15) routing lc_trk_g2_1 <X> input0_7
+(28 15) routing lc_trk_g2_3 <X> input0_7
+(28 15) routing lc_trk_g2_5 <X> input0_7
+(28 15) routing lc_trk_g2_7 <X> input0_7
+(28 15) routing lc_trk_g3_0 <X> input0_7
+(28 15) routing lc_trk_g3_2 <X> input0_7
+(28 15) routing lc_trk_g3_4 <X> input0_7
+(28 15) routing lc_trk_g3_6 <X> input0_7
+(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_1
+(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_1
+(28 3) routing lc_trk_g2_1 <X> input0_1
+(28 3) routing lc_trk_g2_3 <X> input0_1
+(28 3) routing lc_trk_g2_5 <X> input0_1
+(28 3) routing lc_trk_g2_7 <X> input0_1
+(28 3) routing lc_trk_g3_0 <X> input0_1
+(28 3) routing lc_trk_g3_2 <X> input0_1
+(28 3) routing lc_trk_g3_4 <X> input0_1
+(28 3) routing lc_trk_g3_6 <X> input0_1
+(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_2
+(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_2
+(28 5) routing lc_trk_g2_0 <X> input0_2
+(28 5) routing lc_trk_g2_2 <X> input0_2
+(28 5) routing lc_trk_g2_4 <X> input0_2
+(28 5) routing lc_trk_g2_6 <X> input0_2
+(28 5) routing lc_trk_g3_1 <X> input0_2
+(28 5) routing lc_trk_g3_3 <X> input0_2
+(28 5) routing lc_trk_g3_5 <X> input0_2
+(28 5) routing lc_trk_g3_7 <X> input0_2
+(28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_3
+(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_3
+(28 7) routing lc_trk_g2_1 <X> input0_3
+(28 7) routing lc_trk_g2_3 <X> input0_3
+(28 7) routing lc_trk_g2_5 <X> input0_3
+(28 7) routing lc_trk_g2_7 <X> input0_3
+(28 7) routing lc_trk_g3_0 <X> input0_3
+(28 7) routing lc_trk_g3_2 <X> input0_3
+(28 7) routing lc_trk_g3_4 <X> input0_3
+(28 7) routing lc_trk_g3_6 <X> input0_3
+(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_4
+(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_4
+(28 9) routing lc_trk_g2_0 <X> input0_4
+(28 9) routing lc_trk_g2_2 <X> input0_4
+(28 9) routing lc_trk_g2_4 <X> input0_4
+(28 9) routing lc_trk_g2_6 <X> input0_4
+(28 9) routing lc_trk_g3_1 <X> input0_4
+(28 9) routing lc_trk_g3_3 <X> input0_4
+(28 9) routing lc_trk_g3_5 <X> input0_4
+(28 9) routing lc_trk_g3_7 <X> input0_4
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_0
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_5
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_6
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_7
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_1
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_2
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_3
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_4
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4
+(3 0) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 0) routing sp12_v_t_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_l_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 10) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 10) routing sp12_v_t_22 <X> sp12_h_l_22
+(3 11) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 11) routing sp12_v_b_1 <X> sp12_h_l_22
+(3 12) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 12) routing sp12_v_t_22 <X> sp12_h_r_1
+(3 13) routing sp12_h_l_22 <X> sp12_h_r_1
+(3 13) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 14) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 14) routing sp12_v_b_1 <X> sp12_v_t_22
+(3 15) routing sp12_h_l_22 <X> sp12_v_t_22
+(3 15) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 2) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 2) routing sp12_v_t_23 <X> sp12_h_l_23
+(3 3) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 3) routing sp12_v_b_0 <X> sp12_h_l_23
+(3 4) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 4) routing sp12_v_t_23 <X> sp12_h_r_0
+(3 5) routing sp12_h_l_23 <X> sp12_h_r_0
+(3 5) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 6) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 6) routing sp12_v_b_0 <X> sp12_v_t_23
+(3 7) routing sp12_h_l_23 <X> sp12_v_t_23
+(3 7) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 8) routing sp12_h_r_1 <X> sp12_v_b_1
+(3 8) routing sp12_v_t_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_l_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_r_1 <X> sp12_v_b_1
+(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_0
+(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_0
+(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_0
+(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_5
+(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_5
+(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_5
+(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_6
+(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_6
+(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_6
+(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_7
+(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_7
+(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_7
+(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_1
+(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_1
+(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_1
+(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_2
+(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_2
+(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_2
+(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_3
+(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_3
+(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_4
+(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_4
+(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_0
+(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_0
+(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_0
+(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_5
+(31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_5
+(31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_5
+(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_6
+(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_6
+(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_6
+(31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_7
+(31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_7
+(31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_7
+(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_1
+(31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_1
+(31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_1
+(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_2
+(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_2
+(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_2
+(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_3
+(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_3
+(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_4
+(31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_4
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_0
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_0 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_2 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_4 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_6 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_1 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_3 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_5 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_7 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_0 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_2 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_4 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_6 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_1 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_3 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_5 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_7 input2_0
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_5
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_5
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_6
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_6
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_7
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_7
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_1
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_1 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_3 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_5 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_7 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_0 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_2 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_4 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_6 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_1 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_3 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_5 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_7 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_0 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_2 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_4 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_6 input2_1
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_2
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_0 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_2 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_4 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_6 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_1 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_3 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_5 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_7 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_0 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_2 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_4 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_6 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_1 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_3 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_5 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_7 input2_2
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_3
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_4
+(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_0
+(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_0
+(33 1) routing lc_trk_g2_0 <X> input2_0
+(33 1) routing lc_trk_g2_2 <X> input2_0
+(33 1) routing lc_trk_g2_4 <X> input2_0
+(33 1) routing lc_trk_g2_6 <X> input2_0
+(33 1) routing lc_trk_g3_1 <X> input2_0
+(33 1) routing lc_trk_g3_3 <X> input2_0
+(33 1) routing lc_trk_g3_5 <X> input2_0
+(33 1) routing lc_trk_g3_7 <X> input2_0
+(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_5
+(33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_5
+(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_6
+(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_6
+(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_7
+(33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_7
+(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_1
+(33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_1
+(33 3) routing lc_trk_g2_1 <X> input2_1
+(33 3) routing lc_trk_g2_3 <X> input2_1
+(33 3) routing lc_trk_g2_5 <X> input2_1
+(33 3) routing lc_trk_g2_7 <X> input2_1
+(33 3) routing lc_trk_g3_0 <X> input2_1
+(33 3) routing lc_trk_g3_2 <X> input2_1
+(33 3) routing lc_trk_g3_4 <X> input2_1
+(33 3) routing lc_trk_g3_6 <X> input2_1
+(33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_2
+(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_2
+(33 5) routing lc_trk_g2_0 <X> input2_2
+(33 5) routing lc_trk_g2_2 <X> input2_2
+(33 5) routing lc_trk_g2_4 <X> input2_2
+(33 5) routing lc_trk_g2_6 <X> input2_2
+(33 5) routing lc_trk_g3_1 <X> input2_2
+(33 5) routing lc_trk_g3_3 <X> input2_2
+(33 5) routing lc_trk_g3_5 <X> input2_2
+(33 5) routing lc_trk_g3_7 <X> input2_2
+(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_3
+(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_4
+(34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_0
+(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_0
+(34 1) routing lc_trk_g1_1 <X> input2_0
+(34 1) routing lc_trk_g1_3 <X> input2_0
+(34 1) routing lc_trk_g1_5 <X> input2_0
+(34 1) routing lc_trk_g1_7 <X> input2_0
+(34 1) routing lc_trk_g3_1 <X> input2_0
+(34 1) routing lc_trk_g3_3 <X> input2_0
+(34 1) routing lc_trk_g3_5 <X> input2_0
+(34 1) routing lc_trk_g3_7 <X> input2_0
+(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_5
+(34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_5
+(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_6
+(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_6
+(34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_7
+(34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_7
+(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_1
+(34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_1
+(34 3) routing lc_trk_g1_0 <X> input2_1
+(34 3) routing lc_trk_g1_2 <X> input2_1
+(34 3) routing lc_trk_g1_4 <X> input2_1
+(34 3) routing lc_trk_g1_6 <X> input2_1
+(34 3) routing lc_trk_g3_0 <X> input2_1
+(34 3) routing lc_trk_g3_2 <X> input2_1
+(34 3) routing lc_trk_g3_4 <X> input2_1
+(34 3) routing lc_trk_g3_6 <X> input2_1
+(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_2
+(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_2
+(34 5) routing lc_trk_g1_1 <X> input2_2
+(34 5) routing lc_trk_g1_3 <X> input2_2
+(34 5) routing lc_trk_g1_5 <X> input2_2
+(34 5) routing lc_trk_g1_7 <X> input2_2
+(34 5) routing lc_trk_g3_1 <X> input2_2
+(34 5) routing lc_trk_g3_3 <X> input2_2
+(34 5) routing lc_trk_g3_5 <X> input2_2
+(34 5) routing lc_trk_g3_7 <X> input2_2
+(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_3
+(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_4
+(35 0) routing lc_trk_g0_4 <X> input2_0
+(35 0) routing lc_trk_g0_6 <X> input2_0
+(35 0) routing lc_trk_g1_5 <X> input2_0
+(35 0) routing lc_trk_g1_7 <X> input2_0
+(35 0) routing lc_trk_g2_4 <X> input2_0
+(35 0) routing lc_trk_g2_6 <X> input2_0
+(35 0) routing lc_trk_g3_5 <X> input2_0
+(35 0) routing lc_trk_g3_7 <X> input2_0
+(35 1) routing lc_trk_g0_2 <X> input2_0
+(35 1) routing lc_trk_g0_6 <X> input2_0
+(35 1) routing lc_trk_g1_3 <X> input2_0
+(35 1) routing lc_trk_g1_7 <X> input2_0
+(35 1) routing lc_trk_g2_2 <X> input2_0
+(35 1) routing lc_trk_g2_6 <X> input2_0
+(35 1) routing lc_trk_g3_3 <X> input2_0
+(35 1) routing lc_trk_g3_7 <X> input2_0
+(35 2) routing lc_trk_g0_5 <X> input2_1
+(35 2) routing lc_trk_g0_7 <X> input2_1
+(35 2) routing lc_trk_g1_4 <X> input2_1
+(35 2) routing lc_trk_g1_6 <X> input2_1
+(35 2) routing lc_trk_g2_5 <X> input2_1
+(35 2) routing lc_trk_g2_7 <X> input2_1
+(35 2) routing lc_trk_g3_4 <X> input2_1
+(35 2) routing lc_trk_g3_6 <X> input2_1
+(35 3) routing lc_trk_g0_3 <X> input2_1
+(35 3) routing lc_trk_g0_7 <X> input2_1
+(35 3) routing lc_trk_g1_2 <X> input2_1
+(35 3) routing lc_trk_g1_6 <X> input2_1
+(35 3) routing lc_trk_g2_3 <X> input2_1
+(35 3) routing lc_trk_g2_7 <X> input2_1
+(35 3) routing lc_trk_g3_2 <X> input2_1
+(35 3) routing lc_trk_g3_6 <X> input2_1
+(35 4) routing lc_trk_g0_4 <X> input2_2
+(35 4) routing lc_trk_g0_6 <X> input2_2
+(35 4) routing lc_trk_g1_5 <X> input2_2
+(35 4) routing lc_trk_g1_7 <X> input2_2
+(35 4) routing lc_trk_g2_4 <X> input2_2
+(35 4) routing lc_trk_g2_6 <X> input2_2
+(35 4) routing lc_trk_g3_5 <X> input2_2
+(35 4) routing lc_trk_g3_7 <X> input2_2
+(35 5) routing lc_trk_g0_2 <X> input2_2
+(35 5) routing lc_trk_g0_6 <X> input2_2
+(35 5) routing lc_trk_g1_3 <X> input2_2
+(35 5) routing lc_trk_g1_7 <X> input2_2
+(35 5) routing lc_trk_g2_2 <X> input2_2
+(35 5) routing lc_trk_g2_6 <X> input2_2
+(35 5) routing lc_trk_g3_3 <X> input2_2
+(35 5) routing lc_trk_g3_7 <X> input2_2
+(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_0 sp4_h_r_32
+(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_0 sp4_h_r_0
+(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_5 sp4_h_r_42
+(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_5 sp4_h_r_10
+(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_6 sp4_h_r_44
+(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_6 sp4_h_l_1
+(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_7 sp4_h_r_46
+(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_7 sp4_h_l_3
+(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_1 sp4_h_r_34
+(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_1 sp4_h_r_2
+(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_2 sp4_h_r_36
+(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_2 sp4_h_r_4
+(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_3 sp4_h_l_27
+(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_3 sp4_h_r_6
+(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_4 sp4_h_r_40
+(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_4 sp4_h_r_8
+(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_0 sp12_h_r_8
+(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_0 sp4_h_r_16
+(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_5 sp12_h_l_1
+(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_5 sp4_h_l_15
+(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_6 sp12_h_l_3
+(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_6 sp4_h_r_28
+(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_7 sp12_h_l_5
+(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_7 sp4_h_l_19
+(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_1 sp12_h_l_9
+(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_1 sp4_h_r_18
+(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_2 sp12_h_r_12
+(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_2 sp4_h_l_9
+(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_3 sp12_h_r_14
+(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_3 sp4_h_l_11
+(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_4 sp12_h_r_0
+(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_4 sp4_h_r_24
+(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_0 sp4_v_b_32
+(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_0 sp4_v_b_0
+(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_5 sp4_v_t_15
+(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_5 sp12_h_l_17
+(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_6 sp4_v_b_28
+(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_6 sp12_h_r_20
+(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_7 sp4_v_t_19
+(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_7 sp12_h_r_22
+(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_1 sp4_v_b_34
+(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_1 sp4_v_b_2
+(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_2 sp4_v_t_25
+(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_2 sp4_v_b_4
+(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_3 sp4_v_t_27
+(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_3 sp4_v_b_6
+(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_4 sp4_v_t_13
+(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_4 sp12_h_l_15
+(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_0 sp12_v_b_0
+(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_0 sp4_v_b_16
+(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_5 sp4_v_t_31
+(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_5 sp4_v_b_10
+(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_6 sp4_v_b_44
+(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_6 sp4_v_b_12
+(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_7 sp4_v_b_46
+(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_7 sp4_v_b_14
+(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_1 sp12_v_t_1
+(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_1 sp4_v_t_7
+(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_2 sp12_v_b_4
+(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_2 sp4_v_b_20
+(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_3 sp12_v_t_5
+(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_3 sp4_v_t_11
+(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_4 sp4_v_b_40
+(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_4 sp4_v_b_8
+(4 0) routing sp4_h_l_37 <X> sp4_v_b_0
+(4 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_37 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(4 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(4 1) routing sp4_h_l_44 <X> sp4_h_r_0
+(4 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(4 1) routing sp4_v_t_42 <X> sp4_h_r_0
+(4 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(4 10) routing sp4_h_r_6 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_6 <X> sp4_v_t_43
+(4 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(4 11) routing sp4_h_r_3 <X> sp4_h_l_43
+(4 11) routing sp4_v_b_1 <X> sp4_h_l_43
+(4 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(4 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(4 12) routing sp4_h_l_44 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_44 <X> sp4_v_b_9
+(4 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(4 13) routing sp4_h_l_43 <X> sp4_h_r_9
+(4 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(4 13) routing sp4_v_t_41 <X> sp4_h_r_9
+(4 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(4 14) routing sp4_h_r_9 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_9 <X> sp4_v_t_44
+(4 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(4 15) routing sp4_h_r_6 <X> sp4_h_l_44
+(4 15) routing sp4_v_b_4 <X> sp4_h_l_44
+(4 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(4 2) routing sp4_h_r_0 <X> sp4_v_t_37
+(4 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_0 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(4 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(4 3) routing sp4_h_r_9 <X> sp4_h_l_37
+(4 3) routing sp4_v_b_7 <X> sp4_h_l_37
+(4 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(4 4) routing sp4_h_l_38 <X> sp4_v_b_3
+(4 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_38 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(4 5) routing sp4_h_l_37 <X> sp4_h_r_3
+(4 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(4 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(4 5) routing sp4_v_t_47 <X> sp4_h_r_3
+(4 6) routing sp4_h_r_3 <X> sp4_v_t_38
+(4 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_3 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(4 7) routing sp4_h_r_0 <X> sp4_h_l_38
+(4 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(4 7) routing sp4_v_b_10 <X> sp4_h_l_38
+(4 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(4 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(4 8) routing sp4_h_l_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(4 9) routing sp4_h_l_38 <X> sp4_h_r_6
+(4 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(4 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(4 9) routing sp4_v_t_36 <X> sp4_h_r_6
+(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_17
+(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_0 sp12_v_b_16
+(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_27
+(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_5 sp12_v_b_10
+(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_29
+(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_6 sp12_v_t_11
+(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_31
+(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_7 sp12_v_b_14
+(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_19
+(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_1 sp12_v_b_18
+(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_21
+(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_2 sp12_v_b_20
+(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_23
+(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_3 sp12_v_b_22
+(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_25
+(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_4 sp12_v_t_7
+(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_33
+(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_1
+(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_43
+(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_11
+(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_45
+(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_13
+(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_47
+(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_15
+(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_35
+(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_3
+(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_37
+(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_5
+(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_39
+(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_7
+(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_41
+(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_9
+(5 0) routing sp4_h_l_44 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_0 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_6 <X> sp4_h_r_0
+(5 0) routing sp4_v_t_37 <X> sp4_h_r_0
+(5 1) routing sp4_h_l_37 <X> sp4_v_b_0
+(5 1) routing sp4_h_l_43 <X> sp4_v_b_0
+(5 1) routing sp4_h_r_0 <X> sp4_v_b_0
+(5 1) routing sp4_v_t_44 <X> sp4_v_b_0
+(5 10) routing sp4_h_r_3 <X> sp4_h_l_43
+(5 10) routing sp4_v_b_6 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_37 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_43 <X> sp4_h_l_43
+(5 11) routing sp4_h_l_43 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_0 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_6 <X> sp4_v_t_43
+(5 11) routing sp4_v_b_3 <X> sp4_v_t_43
+(5 12) routing sp4_h_l_43 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_3 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_9 <X> sp4_h_r_9
+(5 12) routing sp4_v_t_44 <X> sp4_h_r_9
+(5 13) routing sp4_h_l_38 <X> sp4_v_b_9
+(5 13) routing sp4_h_l_44 <X> sp4_v_b_9
+(5 13) routing sp4_h_r_9 <X> sp4_v_b_9
+(5 13) routing sp4_v_t_43 <X> sp4_v_b_9
+(5 14) routing sp4_h_r_6 <X> sp4_h_l_44
+(5 14) routing sp4_v_b_9 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_38 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_44 <X> sp4_h_l_44
+(5 15) routing sp4_h_l_44 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_3 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_9 <X> sp4_v_t_44
+(5 15) routing sp4_v_b_6 <X> sp4_v_t_44
+(5 2) routing sp4_h_r_9 <X> sp4_h_l_37
+(5 2) routing sp4_v_b_0 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_37 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_43 <X> sp4_h_l_37
+(5 3) routing sp4_h_l_37 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_0 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_6 <X> sp4_v_t_37
+(5 3) routing sp4_v_b_9 <X> sp4_v_t_37
+(5 4) routing sp4_h_l_37 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_3 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_9 <X> sp4_h_r_3
+(5 4) routing sp4_v_t_38 <X> sp4_h_r_3
+(5 5) routing sp4_h_l_38 <X> sp4_v_b_3
+(5 5) routing sp4_h_l_44 <X> sp4_v_b_3
+(5 5) routing sp4_h_r_3 <X> sp4_v_b_3
+(5 5) routing sp4_v_t_37 <X> sp4_v_b_3
+(5 6) routing sp4_h_r_0 <X> sp4_h_l_38
+(5 6) routing sp4_v_b_3 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_38 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_44 <X> sp4_h_l_38
+(5 7) routing sp4_h_l_38 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_3 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_9 <X> sp4_v_t_38
+(5 7) routing sp4_v_b_0 <X> sp4_v_t_38
+(5 8) routing sp4_h_l_38 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_0 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_6 <X> sp4_h_r_6
+(5 8) routing sp4_v_t_43 <X> sp4_h_r_6
+(5 9) routing sp4_h_l_37 <X> sp4_v_b_6
+(5 9) routing sp4_h_l_43 <X> sp4_v_b_6
+(5 9) routing sp4_h_r_6 <X> sp4_v_b_6
+(5 9) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(6 0) routing sp4_h_r_7 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_44 <X> sp4_v_b_0
+(6 1) routing sp4_h_l_37 <X> sp4_h_r_0
+(6 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_0 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(6 10) routing sp4_h_l_36 <X> sp4_v_t_43
+(6 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_3 <X> sp4_v_t_43
+(6 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(6 11) routing sp4_h_r_6 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_43 <X> sp4_h_l_43
+(6 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(6 12) routing sp4_h_r_4 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_43 <X> sp4_v_b_9
+(6 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(6 13) routing sp4_h_l_44 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_9 <X> sp4_h_r_9
+(6 14) routing sp4_h_l_41 <X> sp4_v_t_44
+(6 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_6 <X> sp4_v_t_44
+(6 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(6 15) routing sp4_h_r_9 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_44 <X> sp4_h_l_44
+(6 2) routing sp4_h_l_42 <X> sp4_v_t_37
+(6 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_9 <X> sp4_v_t_37
+(6 3) routing sp4_h_r_0 <X> sp4_h_l_37
+(6 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_37 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(6 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(6 4) routing sp4_h_r_10 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_37 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(6 5) routing sp4_h_l_38 <X> sp4_h_r_3
+(6 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_3 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(6 6) routing sp4_h_l_47 <X> sp4_v_t_38
+(6 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_0 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(6 7) routing sp4_h_r_3 <X> sp4_h_l_38
+(6 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_38 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(6 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(6 8) routing sp4_h_r_1 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(6 9) routing sp4_h_l_43 <X> sp4_h_r_6
+(6 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_6 <X> sp4_h_r_6
+(7 1) Ram config bit: MEMB_Power_Up_Control
+(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
+(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(8 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(8 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(8 1) routing sp4_h_r_1 <X> sp4_v_b_1
+(8 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(8 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(8 10) routing sp4_h_r_7 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(8 11) routing sp4_h_l_42 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(8 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(8 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(8 12) routing sp4_h_l_47 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(8 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(8 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(8 13) routing sp4_h_r_10 <X> sp4_v_b_10
+(8 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(8 14) routing sp4_h_r_10 <X> sp4_h_l_47
+(8 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(8 15) routing sp4_h_l_47 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(8 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(8 2) routing sp4_h_r_1 <X> sp4_h_l_36
+(8 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(8 3) routing sp4_h_l_36 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(8 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(8 4) routing sp4_h_l_41 <X> sp4_h_r_4
+(8 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(8 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(8 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(8 5) routing sp4_h_r_4 <X> sp4_v_b_4
+(8 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(8 6) routing sp4_h_r_4 <X> sp4_h_l_41
+(8 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(8 7) routing sp4_h_l_41 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(8 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(8 8) routing sp4_h_l_42 <X> sp4_h_r_7
+(8 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(8 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(8 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(8 9) routing sp4_h_r_7 <X> sp4_v_b_7
+(8 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(9 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(9 0) routing sp4_v_t_36 <X> sp4_h_r_1
+(9 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(9 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_36 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(9 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(9 10) routing sp4_v_b_7 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(9 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(9 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_7 <X> sp4_v_t_42
+(9 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(9 12) routing sp4_v_t_47 <X> sp4_h_r_10
+(9 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(9 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_47 <X> sp4_v_b_10
+(9 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(9 14) routing sp4_v_b_10 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(9 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(9 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_10 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(9 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(9 2) routing sp4_v_b_1 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(9 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(9 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_1 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(9 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(9 4) routing sp4_v_t_41 <X> sp4_h_r_4
+(9 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(9 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_41 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(9 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(9 6) routing sp4_v_b_4 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(9 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(9 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(9 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(9 8) routing sp4_v_t_42 <X> sp4_h_r_7
+(9 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(9 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_46 <X> sp4_v_b_7
diff --git a/icefuzz/cached_ramb_8k.txt b/icefuzz/cached_ramb_8k.txt
new file mode 100644
index 0000000..843ce53
--- /dev/null
+++ b/icefuzz/cached_ramb_8k.txt
@@ -0,0 +1,3575 @@
+(0 0) Negative Clock bit
+(0 10) routing glb_netwk_2 <X> glb2local_2
+(0 10) routing glb_netwk_3 <X> glb2local_2
+(0 10) routing glb_netwk_6 <X> glb2local_2
+(0 10) routing glb_netwk_7 <X> glb2local_2
+(0 11) routing glb_netwk_1 <X> glb2local_2
+(0 11) routing glb_netwk_3 <X> glb2local_2
+(0 11) routing glb_netwk_5 <X> glb2local_2
+(0 11) routing glb_netwk_7 <X> glb2local_2
+(0 12) routing glb_netwk_2 <X> glb2local_3
+(0 12) routing glb_netwk_3 <X> glb2local_3
+(0 12) routing glb_netwk_6 <X> glb2local_3
+(0 12) routing glb_netwk_7 <X> glb2local_3
+(0 13) routing glb_netwk_1 <X> glb2local_3
+(0 13) routing glb_netwk_3 <X> glb2local_3
+(0 13) routing glb_netwk_5 <X> glb2local_3
+(0 13) routing glb_netwk_7 <X> glb2local_3
+(0 14) routing glb_netwk_4 <X> wire_bram/ram/RE
+(0 14) routing glb_netwk_6 <X> wire_bram/ram/RE
+(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/RE
+(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(0 15) routing glb_netwk_2 <X> wire_bram/ram/RE
+(0 15) routing glb_netwk_6 <X> wire_bram/ram/RE
+(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE
+(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(0 2) routing glb_netwk_2 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_3 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK
+(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_1 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_3 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_5 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK
+(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(0 4) routing glb_netwk_5 <X> wire_bram/ram/RCLKE
+(0 4) routing glb_netwk_7 <X> wire_bram/ram/RCLKE
+(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE
+(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(0 5) routing glb_netwk_3 <X> wire_bram/ram/RCLKE
+(0 5) routing glb_netwk_7 <X> wire_bram/ram/RCLKE
+(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE
+(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(0 6) routing glb_netwk_2 <X> glb2local_0
+(0 6) routing glb_netwk_3 <X> glb2local_0
+(0 6) routing glb_netwk_6 <X> glb2local_0
+(0 6) routing glb_netwk_7 <X> glb2local_0
+(0 7) routing glb_netwk_1 <X> glb2local_0
+(0 7) routing glb_netwk_3 <X> glb2local_0
+(0 7) routing glb_netwk_5 <X> glb2local_0
+(0 7) routing glb_netwk_7 <X> glb2local_0
+(0 8) routing glb_netwk_2 <X> glb2local_1
+(0 8) routing glb_netwk_3 <X> glb2local_1
+(0 8) routing glb_netwk_6 <X> glb2local_1
+(0 8) routing glb_netwk_7 <X> glb2local_1
+(0 9) routing glb_netwk_1 <X> glb2local_1
+(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_7 <X> glb2local_1
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2
+(1 11) routing glb_netwk_4 <X> glb2local_2
+(1 11) routing glb_netwk_5 <X> glb2local_2
+(1 11) routing glb_netwk_6 <X> glb2local_2
+(1 11) routing glb_netwk_7 <X> glb2local_2
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3
+(1 13) routing glb_netwk_4 <X> glb2local_3
+(1 13) routing glb_netwk_5 <X> glb2local_3
+(1 13) routing glb_netwk_6 <X> glb2local_3
+(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
+(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(1 2) routing glb_netwk_4 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_5 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0
+(1 7) routing glb_netwk_4 <X> glb2local_0
+(1 7) routing glb_netwk_5 <X> glb2local_0
+(1 7) routing glb_netwk_6 <X> glb2local_0
+(1 7) routing glb_netwk_7 <X> glb2local_0
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
+(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_6 <X> glb2local_1
+(1 9) routing glb_netwk_7 <X> glb2local_1
+(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(10 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(10 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(10 0) routing sp4_v_t_45 <X> sp4_h_r_1
+(10 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(10 1) routing sp4_h_r_8 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(10 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(10 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(10 10) routing sp4_v_b_2 <X> sp4_h_l_42
+(10 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(10 11) routing sp4_h_l_39 <X> sp4_v_t_42
+(10 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(10 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(10 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(10 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(10 12) routing sp4_v_t_40 <X> sp4_h_r_10
+(10 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(10 13) routing sp4_h_r_5 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(10 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(10 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(10 14) routing sp4_v_b_5 <X> sp4_h_l_47
+(10 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(10 15) routing sp4_h_l_40 <X> sp4_v_t_47
+(10 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(10 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(10 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(10 2) routing sp4_v_b_8 <X> sp4_h_l_36
+(10 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(10 3) routing sp4_h_l_45 <X> sp4_v_t_36
+(10 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(10 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(10 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(10 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(10 4) routing sp4_v_t_46 <X> sp4_h_r_4
+(10 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(10 5) routing sp4_h_r_11 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(10 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(10 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(10 6) routing sp4_v_b_11 <X> sp4_h_l_41
+(10 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(10 7) routing sp4_h_l_46 <X> sp4_v_t_41
+(10 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(10 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(10 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(10 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(10 8) routing sp4_v_t_39 <X> sp4_h_r_7
+(10 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(10 9) routing sp4_h_r_2 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_46 <X> sp4_v_b_7
+(11 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(11 0) routing sp4_h_r_9 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_46 <X> sp4_v_b_2
+(11 1) routing sp4_h_l_39 <X> sp4_h_r_2
+(11 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_2 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(11 10) routing sp4_h_l_38 <X> sp4_v_t_45
+(11 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_5 <X> sp4_v_t_45
+(11 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(11 11) routing sp4_h_r_8 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_45 <X> sp4_h_l_45
+(11 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(11 12) routing sp4_h_r_6 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_45 <X> sp4_v_b_11
+(11 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(11 13) routing sp4_h_l_46 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_11 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(11 14) routing sp4_h_l_43 <X> sp4_v_t_46
+(11 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_8 <X> sp4_v_t_46
+(11 15) routing sp4_h_r_11 <X> sp4_h_l_46
+(11 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_46 <X> sp4_h_l_46
+(11 2) routing sp4_h_l_44 <X> sp4_v_t_39
+(11 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_11 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(11 3) routing sp4_h_r_2 <X> sp4_h_l_39
+(11 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_39 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(11 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(11 4) routing sp4_h_r_0 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_39 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(11 5) routing sp4_h_l_40 <X> sp4_h_r_5
+(11 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_5 <X> sp4_h_r_5
+(11 6) routing sp4_h_l_37 <X> sp4_v_t_40
+(11 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_2 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(11 7) routing sp4_h_r_5 <X> sp4_h_l_40
+(11 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_40 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(11 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(11 8) routing sp4_h_r_3 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_40 <X> sp4_v_b_8
+(11 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(11 9) routing sp4_h_l_45 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 0) routing sp4_h_l_46 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_2 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_8 <X> sp4_h_r_2
+(12 0) routing sp4_v_t_39 <X> sp4_h_r_2
+(12 1) routing sp4_h_l_39 <X> sp4_v_b_2
+(12 1) routing sp4_h_l_45 <X> sp4_v_b_2
+(12 1) routing sp4_h_r_2 <X> sp4_v_b_2
+(12 1) routing sp4_v_t_46 <X> sp4_v_b_2
+(12 10) routing sp4_h_r_5 <X> sp4_h_l_45
+(12 10) routing sp4_v_b_8 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_39 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_45 <X> sp4_h_l_45
+(12 11) routing sp4_h_l_45 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_2 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_8 <X> sp4_v_t_45
+(12 11) routing sp4_v_b_5 <X> sp4_v_t_45
+(12 12) routing sp4_h_l_45 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_11 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_5 <X> sp4_h_r_11
+(12 12) routing sp4_v_t_46 <X> sp4_h_r_11
+(12 13) routing sp4_h_l_40 <X> sp4_v_b_11
+(12 13) routing sp4_h_l_46 <X> sp4_v_b_11
+(12 13) routing sp4_h_r_11 <X> sp4_v_b_11
+(12 13) routing sp4_v_t_45 <X> sp4_v_b_11
+(12 14) routing sp4_h_r_8 <X> sp4_h_l_46
+(12 14) routing sp4_v_b_11 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_40 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_46 <X> sp4_h_l_46
+(12 15) routing sp4_h_l_46 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_11 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_5 <X> sp4_v_t_46
+(12 15) routing sp4_v_b_8 <X> sp4_v_t_46
+(12 2) routing sp4_h_r_11 <X> sp4_h_l_39
+(12 2) routing sp4_v_b_2 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_39 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_45 <X> sp4_h_l_39
+(12 3) routing sp4_h_l_39 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_2 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_8 <X> sp4_v_t_39
+(12 3) routing sp4_v_b_11 <X> sp4_v_t_39
+(12 4) routing sp4_h_l_39 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_11 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_5 <X> sp4_h_r_5
+(12 4) routing sp4_v_t_40 <X> sp4_h_r_5
+(12 5) routing sp4_h_l_40 <X> sp4_v_b_5
+(12 5) routing sp4_h_l_46 <X> sp4_v_b_5
+(12 5) routing sp4_h_r_5 <X> sp4_v_b_5
+(12 5) routing sp4_v_t_39 <X> sp4_v_b_5
+(12 6) routing sp4_h_r_2 <X> sp4_h_l_40
+(12 6) routing sp4_v_b_5 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_40 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_46 <X> sp4_h_l_40
+(12 7) routing sp4_h_l_40 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_11 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_5 <X> sp4_v_t_40
+(12 7) routing sp4_v_b_2 <X> sp4_v_t_40
+(12 8) routing sp4_h_l_40 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_2 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 8) routing sp4_v_t_45 <X> sp4_h_r_8
+(12 9) routing sp4_h_l_39 <X> sp4_v_b_8
+(12 9) routing sp4_h_l_45 <X> sp4_v_b_8
+(12 9) routing sp4_h_r_8 <X> sp4_v_b_8
+(12 9) routing sp4_v_t_40 <X> sp4_v_b_8
+(13 0) routing sp4_h_l_39 <X> sp4_v_b_2
+(13 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_39 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(13 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(13 1) routing sp4_h_l_46 <X> sp4_h_r_2
+(13 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(13 1) routing sp4_v_t_44 <X> sp4_h_r_2
+(13 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(13 10) routing sp4_h_r_8 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_8 <X> sp4_v_t_45
+(13 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(13 11) routing sp4_h_r_5 <X> sp4_h_l_45
+(13 11) routing sp4_v_b_3 <X> sp4_h_l_45
+(13 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(13 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(13 12) routing sp4_h_l_46 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_46 <X> sp4_v_b_11
+(13 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(13 13) routing sp4_h_l_45 <X> sp4_h_r_11
+(13 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(13 13) routing sp4_v_t_43 <X> sp4_h_r_11
+(13 14) routing sp4_h_r_11 <X> sp4_v_t_46
+(13 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_11 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(13 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(13 15) routing sp4_h_r_8 <X> sp4_h_l_46
+(13 15) routing sp4_v_b_6 <X> sp4_h_l_46
+(13 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(13 2) routing sp4_h_r_2 <X> sp4_v_t_39
+(13 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_2 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(13 3) routing sp4_h_r_11 <X> sp4_h_l_39
+(13 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(13 3) routing sp4_v_b_9 <X> sp4_h_l_39
+(13 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(13 4) routing sp4_h_l_40 <X> sp4_v_b_5
+(13 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_40 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(13 5) routing sp4_h_l_39 <X> sp4_h_r_5
+(13 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(13 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(13 5) routing sp4_v_t_37 <X> sp4_h_r_5
+(13 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(13 6) routing sp4_h_r_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(13 7) routing sp4_h_r_2 <X> sp4_h_l_40
+(13 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(13 7) routing sp4_v_b_0 <X> sp4_h_l_40
+(13 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(13 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(13 8) routing sp4_h_l_45 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_45 <X> sp4_v_b_8
+(13 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(13 9) routing sp4_h_l_40 <X> sp4_h_r_8
+(13 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(13 9) routing sp4_v_t_38 <X> sp4_h_r_8
+(14 0) routing bnr_op_0 <X> lc_trk_g0_0
+(14 0) routing lft_op_0 <X> lc_trk_g0_0
+(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing bnr_op_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0
+(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 10) routing bnl_op_4 <X> lc_trk_g2_4
+(14 10) routing rgt_op_4 <X> lc_trk_g2_4
+(14 10) routing sp12_v_b_4 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4
+(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing bnl_op_4 <X> lc_trk_g2_4
+(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(14 11) routing sp12_v_b_4 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4
+(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing tnl_op_4 <X> lc_trk_g2_4
+(14 12) routing bnl_op_0 <X> lc_trk_g3_0
+(14 12) routing rgt_op_0 <X> lc_trk_g3_0
+(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 12) routing sp4_h_r_32 <X> lc_trk_g3_0
+(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 12) routing sp4_v_b_32 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0
+(14 13) routing bnl_op_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0
+(14 13) routing sp4_v_b_32 <X> lc_trk_g3_0
+(14 13) routing tnl_op_0 <X> lc_trk_g3_0
+(14 14) routing bnl_op_4 <X> lc_trk_g3_4
+(14 14) routing rgt_op_4 <X> lc_trk_g3_4
+(14 14) routing sp12_v_b_4 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4
+(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing bnl_op_4 <X> lc_trk_g3_4
+(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(14 15) routing sp12_v_b_4 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4
+(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing tnl_op_4 <X> lc_trk_g3_4
+(14 2) routing bnr_op_4 <X> lc_trk_g0_4
+(14 2) routing lft_op_4 <X> lc_trk_g0_4
+(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_1 <X> lc_trk_g0_4
+(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_12 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4
+(14 3) routing bnr_op_4 <X> lc_trk_g0_4
+(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4
+(14 3) routing sp4_v_b_12 <X> lc_trk_g0_4
+(14 4) routing bnr_op_0 <X> lc_trk_g1_0
+(14 4) routing lft_op_0 <X> lc_trk_g1_0
+(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing bnr_op_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0
+(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 6) routing bnr_op_4 <X> lc_trk_g1_4
+(14 6) routing lft_op_4 <X> lc_trk_g1_4
+(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_1 <X> lc_trk_g1_4
+(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_12 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4
+(14 7) routing bnr_op_4 <X> lc_trk_g1_4
+(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4
+(14 7) routing sp4_v_b_12 <X> lc_trk_g1_4
+(14 8) routing bnl_op_0 <X> lc_trk_g2_0
+(14 8) routing rgt_op_0 <X> lc_trk_g2_0
+(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0
+(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 8) routing sp4_v_b_32 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0
+(14 9) routing bnl_op_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0
+(14 9) routing sp4_v_b_32 <X> lc_trk_g2_0
+(14 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 0) routing lft_op_1 <X> lc_trk_g0_1
+(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(15 0) routing sp4_v_t_4 <X> lc_trk_g0_1
+(15 1) routing bot_op_0 <X> lc_trk_g0_0
+(15 1) routing lft_op_0 <X> lc_trk_g0_0
+(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(15 10) routing rgt_op_5 <X> lc_trk_g2_5
+(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_29 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(15 10) routing tnl_op_5 <X> lc_trk_g2_5
+(15 10) routing tnr_op_5 <X> lc_trk_g2_5
+(15 11) routing rgt_op_4 <X> lc_trk_g2_4
+(15 11) routing sp12_v_b_4 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(15 11) routing sp4_v_b_44 <X> lc_trk_g2_4
+(15 11) routing tnl_op_4 <X> lc_trk_g2_4
+(15 11) routing tnr_op_4 <X> lc_trk_g2_4
+(15 12) routing rgt_op_1 <X> lc_trk_g3_1
+(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(15 12) routing tnl_op_1 <X> lc_trk_g3_1
+(15 12) routing tnr_op_1 <X> lc_trk_g3_1
+(15 13) routing rgt_op_0 <X> lc_trk_g3_0
+(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_32 <X> lc_trk_g3_0
+(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(15 13) routing tnl_op_0 <X> lc_trk_g3_0
+(15 13) routing tnr_op_0 <X> lc_trk_g3_0
+(15 14) routing rgt_op_5 <X> lc_trk_g3_5
+(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(15 14) routing tnl_op_5 <X> lc_trk_g3_5
+(15 14) routing tnr_op_5 <X> lc_trk_g3_5
+(15 15) routing rgt_op_4 <X> lc_trk_g3_4
+(15 15) routing sp12_v_b_4 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(15 15) routing sp4_v_b_44 <X> lc_trk_g3_4
+(15 15) routing tnl_op_4 <X> lc_trk_g3_4
+(15 15) routing tnr_op_4 <X> lc_trk_g3_4
+(15 2) routing lft_op_5 <X> lc_trk_g0_5
+(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(15 3) routing bot_op_4 <X> lc_trk_g0_4
+(15 3) routing lft_op_4 <X> lc_trk_g0_4
+(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(15 4) routing lft_op_1 <X> lc_trk_g1_1
+(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(15 4) routing sp4_v_t_4 <X> lc_trk_g1_1
+(15 5) routing bot_op_0 <X> lc_trk_g1_0
+(15 5) routing lft_op_0 <X> lc_trk_g1_0
+(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(15 6) routing lft_op_5 <X> lc_trk_g1_5
+(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(15 7) routing bot_op_4 <X> lc_trk_g1_4
+(15 7) routing lft_op_4 <X> lc_trk_g1_4
+(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(15 8) routing rgt_op_1 <X> lc_trk_g2_1
+(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(15 8) routing tnl_op_1 <X> lc_trk_g2_1
+(15 8) routing tnr_op_1 <X> lc_trk_g2_1
+(15 9) routing rgt_op_0 <X> lc_trk_g2_0
+(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0
+(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(15 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 9) routing tnr_op_0 <X> lc_trk_g2_0
+(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1
+(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_t_4 <X> lc_trk_g0_1
+(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0
+(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(16 10) routing sp12_v_b_13 <X> lc_trk_g2_5
+(16 10) routing sp12_v_t_18 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_29 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_t_24 <X> lc_trk_g2_5
+(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4
+(16 11) routing sp12_v_t_11 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_28 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1
+(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1
+(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_24 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_32 <X> lc_trk_g3_0
+(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_32 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0
+(16 14) routing sp12_v_b_13 <X> lc_trk_g3_5
+(16 14) routing sp12_v_t_18 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_t_24 <X> lc_trk_g3_5
+(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4
+(16 15) routing sp12_v_t_11 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_28 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5
+(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_1 <X> lc_trk_g0_4
+(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_12 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4
+(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1
+(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_t_4 <X> lc_trk_g1_1
+(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0
+(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5
+(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_1 <X> lc_trk_g1_4
+(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_12 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4
+(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1
+(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1
+(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0
+(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_32 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0
+(18 0) routing bnr_op_1 <X> lc_trk_g0_1
+(18 0) routing lft_op_1 <X> lc_trk_g0_1
+(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 1) routing bnr_op_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1
+(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 10) routing bnl_op_5 <X> lc_trk_g2_5
+(18 10) routing rgt_op_5 <X> lc_trk_g2_5
+(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(18 10) routing sp4_v_t_24 <X> lc_trk_g2_5
+(18 11) routing bnl_op_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_t_18 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_29 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5
+(18 11) routing sp4_v_t_24 <X> lc_trk_g2_5
+(18 11) routing tnl_op_5 <X> lc_trk_g2_5
+(18 12) routing bnl_op_1 <X> lc_trk_g3_1
+(18 12) routing rgt_op_1 <X> lc_trk_g3_1
+(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1
+(18 13) routing bnl_op_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1
+(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1
+(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1
+(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1
+(18 13) routing tnl_op_1 <X> lc_trk_g3_1
+(18 14) routing bnl_op_5 <X> lc_trk_g3_5
+(18 14) routing rgt_op_5 <X> lc_trk_g3_5
+(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(18 14) routing sp4_v_t_24 <X> lc_trk_g3_5
+(18 15) routing bnl_op_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_t_18 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5
+(18 15) routing sp4_v_t_24 <X> lc_trk_g3_5
+(18 15) routing tnl_op_5 <X> lc_trk_g3_5
+(18 2) routing bnr_op_5 <X> lc_trk_g0_5
+(18 2) routing lft_op_5 <X> lc_trk_g0_5
+(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(18 3) routing bnr_op_5 <X> lc_trk_g0_5
+(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5
+(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5
+(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 4) routing bnr_op_1 <X> lc_trk_g1_1
+(18 4) routing lft_op_1 <X> lc_trk_g1_1
+(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 5) routing bnr_op_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1
+(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 6) routing bnr_op_5 <X> lc_trk_g1_5
+(18 6) routing lft_op_5 <X> lc_trk_g1_5
+(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(18 7) routing bnr_op_5 <X> lc_trk_g1_5
+(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5
+(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5
+(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 8) routing bnl_op_1 <X> lc_trk_g2_1
+(18 8) routing rgt_op_1 <X> lc_trk_g2_1
+(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1
+(18 9) routing bnl_op_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1
+(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1
+(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1
+(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1
+(18 9) routing tnl_op_1 <X> lc_trk_g2_1
+(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13
+(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12
+(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23
+(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11
+(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13
+(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1
+(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15
+(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3
+(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2
+(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14
+(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4
+(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16
+(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6
+(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7
+(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8
+(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20
+(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16
+(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21
+(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11
+(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK
+(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18
+(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6
+(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9
+(21 0) routing bnr_op_3 <X> lc_trk_g0_3
+(21 0) routing lft_op_3 <X> lc_trk_g0_3
+(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(21 1) routing bnr_op_3 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3
+(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_h_l_6 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3
+(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 10) routing bnl_op_7 <X> lc_trk_g2_7
+(21 10) routing rgt_op_7 <X> lc_trk_g2_7
+(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7
+(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 10) routing sp4_v_b_31 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing bnl_op_7 <X> lc_trk_g2_7
+(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7
+(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_31 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7
+(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing tnl_op_7 <X> lc_trk_g2_7
+(21 12) routing bnl_op_3 <X> lc_trk_g3_3
+(21 12) routing rgt_op_3 <X> lc_trk_g3_3
+(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3
+(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3
+(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3
+(21 13) routing bnl_op_3 <X> lc_trk_g3_3
+(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3
+(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3
+(21 13) routing sp4_h_l_14 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3
+(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3
+(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3
+(21 13) routing tnl_op_3 <X> lc_trk_g3_3
+(21 14) routing bnl_op_7 <X> lc_trk_g3_7
+(21 14) routing rgt_op_7 <X> lc_trk_g3_7
+(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7
+(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 14) routing sp4_v_b_31 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing bnl_op_7 <X> lc_trk_g3_7
+(21 15) routing sp12_v_t_20 <X> lc_trk_g3_7
+(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7
+(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing tnl_op_7 <X> lc_trk_g3_7
+(21 2) routing bnr_op_7 <X> lc_trk_g0_7
+(21 2) routing lft_op_7 <X> lc_trk_g0_7
+(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7
+(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(21 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 3) routing bnr_op_7 <X> lc_trk_g0_7
+(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7
+(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_23 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7
+(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 4) routing bnr_op_3 <X> lc_trk_g1_3
+(21 4) routing lft_op_3 <X> lc_trk_g1_3
+(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(21 5) routing bnr_op_3 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3
+(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_h_l_6 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3
+(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 6) routing bnr_op_7 <X> lc_trk_g1_7
+(21 6) routing lft_op_7 <X> lc_trk_g1_7
+(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7
+(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(21 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 7) routing bnr_op_7 <X> lc_trk_g1_7
+(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7
+(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_23 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7
+(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 8) routing bnl_op_3 <X> lc_trk_g2_3
+(21 8) routing rgt_op_3 <X> lc_trk_g2_3
+(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3
+(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3
+(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3
+(21 9) routing bnl_op_3 <X> lc_trk_g2_3
+(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3
+(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3
+(21 9) routing sp4_h_l_14 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3
+(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3
+(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3
+(21 9) routing tnl_op_3 <X> lc_trk_g2_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2
+(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3
+(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_t_6 <X> lc_trk_g0_3
+(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7
+(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_b_31 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7
+(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6
+(23 11) routing sp12_v_b_22 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6
+(23 11) routing sp4_v_t_27 <X> lc_trk_g2_6
+(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3
+(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_14 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3
+(23 12) routing sp4_v_b_43 <X> lc_trk_g3_3
+(23 13) routing sp12_v_b_10 <X> lc_trk_g3_2
+(23 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_34 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7
+(23 14) routing sp12_v_t_20 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_b_31 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7
+(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6
+(23 15) routing sp12_v_b_22 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_t_19 <X> lc_trk_g3_6
+(23 15) routing sp4_v_t_27 <X> lc_trk_g3_6
+(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7
+(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6
+(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6
+(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3
+(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_t_6 <X> lc_trk_g1_3
+(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7
+(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6
+(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6
+(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3
+(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_14 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3
+(23 8) routing sp4_v_b_43 <X> lc_trk_g2_3
+(23 9) routing sp12_v_b_10 <X> lc_trk_g2_2
+(23 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_34 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 0) routing lft_op_3 <X> lc_trk_g0_3
+(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_h_l_6 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_v_t_6 <X> lc_trk_g0_3
+(24 1) routing lft_op_2 <X> lc_trk_g0_2
+(24 1) routing sp12_h_l_1 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(24 10) routing rgt_op_7 <X> lc_trk_g2_7
+(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_31 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7
+(24 10) routing tnl_op_7 <X> lc_trk_g2_7
+(24 10) routing tnr_op_7 <X> lc_trk_g2_7
+(24 11) routing rgt_op_6 <X> lc_trk_g2_6
+(24 11) routing sp12_v_t_5 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(24 11) routing tnl_op_6 <X> lc_trk_g2_6
+(24 11) routing tnr_op_6 <X> lc_trk_g2_6
+(24 12) routing rgt_op_3 <X> lc_trk_g3_3
+(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_14 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3
+(24 12) routing sp4_v_b_43 <X> lc_trk_g3_3
+(24 12) routing tnl_op_3 <X> lc_trk_g3_3
+(24 12) routing tnr_op_3 <X> lc_trk_g3_3
+(24 13) routing rgt_op_2 <X> lc_trk_g3_2
+(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(24 13) routing tnl_op_2 <X> lc_trk_g3_2
+(24 13) routing tnr_op_2 <X> lc_trk_g3_2
+(24 14) routing rgt_op_7 <X> lc_trk_g3_7
+(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7
+(24 14) routing tnl_op_7 <X> lc_trk_g3_7
+(24 14) routing tnr_op_7 <X> lc_trk_g3_7
+(24 15) routing rgt_op_6 <X> lc_trk_g3_6
+(24 15) routing sp12_v_t_5 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(24 15) routing tnl_op_6 <X> lc_trk_g3_6
+(24 15) routing tnr_op_6 <X> lc_trk_g3_6
+(24 2) routing lft_op_7 <X> lc_trk_g0_7
+(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_23 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_v_b_23 <X> lc_trk_g0_7
+(24 3) routing lft_op_6 <X> lc_trk_g0_6
+(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6
+(24 4) routing lft_op_3 <X> lc_trk_g1_3
+(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_h_l_6 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_v_t_6 <X> lc_trk_g1_3
+(24 5) routing lft_op_2 <X> lc_trk_g1_2
+(24 5) routing sp12_h_l_1 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(24 6) routing lft_op_7 <X> lc_trk_g1_7
+(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_23 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7
+(24 7) routing lft_op_6 <X> lc_trk_g1_6
+(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6
+(24 8) routing rgt_op_3 <X> lc_trk_g2_3
+(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_14 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3
+(24 8) routing sp4_v_b_43 <X> lc_trk_g2_3
+(24 8) routing tnl_op_3 <X> lc_trk_g2_3
+(24 8) routing tnr_op_3 <X> lc_trk_g2_3
+(24 9) routing rgt_op_2 <X> lc_trk_g2_2
+(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 9) routing tnl_op_2 <X> lc_trk_g2_2
+(24 9) routing tnr_op_2 <X> lc_trk_g2_2
+(25 0) routing bnr_op_2 <X> lc_trk_g0_2
+(25 0) routing lft_op_2 <X> lc_trk_g0_2
+(25 0) routing sp12_h_l_1 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_18 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2
+(25 1) routing bnr_op_2 <X> lc_trk_g0_2
+(25 1) routing sp12_h_l_1 <X> lc_trk_g0_2
+(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_18 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2
+(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 10) routing bnl_op_6 <X> lc_trk_g2_6
+(25 10) routing rgt_op_6 <X> lc_trk_g2_6
+(25 10) routing sp12_v_t_5 <X> lc_trk_g2_6
+(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6
+(25 10) routing sp4_v_t_27 <X> lc_trk_g2_6
+(25 11) routing bnl_op_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_b_22 <X> lc_trk_g2_6
+(25 11) routing sp12_v_t_5 <X> lc_trk_g2_6
+(25 11) routing sp4_h_l_19 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6
+(25 11) routing sp4_v_t_27 <X> lc_trk_g2_6
+(25 11) routing tnl_op_6 <X> lc_trk_g2_6
+(25 12) routing bnl_op_2 <X> lc_trk_g3_2
+(25 12) routing rgt_op_2 <X> lc_trk_g3_2
+(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 12) routing sp4_v_b_34 <X> lc_trk_g3_2
+(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2
+(25 13) routing bnl_op_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_b_18 <X> lc_trk_g3_2
+(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2
+(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2
+(25 13) routing sp4_v_b_34 <X> lc_trk_g3_2
+(25 13) routing tnl_op_2 <X> lc_trk_g3_2
+(25 14) routing bnl_op_6 <X> lc_trk_g3_6
+(25 14) routing rgt_op_6 <X> lc_trk_g3_6
+(25 14) routing sp12_v_t_5 <X> lc_trk_g3_6
+(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 14) routing sp4_v_t_19 <X> lc_trk_g3_6
+(25 14) routing sp4_v_t_27 <X> lc_trk_g3_6
+(25 15) routing bnl_op_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_b_22 <X> lc_trk_g3_6
+(25 15) routing sp12_v_t_5 <X> lc_trk_g3_6
+(25 15) routing sp4_h_l_19 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6
+(25 15) routing sp4_v_t_27 <X> lc_trk_g3_6
+(25 15) routing tnl_op_6 <X> lc_trk_g3_6
+(25 2) routing bnr_op_6 <X> lc_trk_g0_6
+(25 2) routing lft_op_6 <X> lc_trk_g0_6
+(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6
+(25 3) routing bnr_op_6 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6
+(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6
+(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 4) routing bnr_op_2 <X> lc_trk_g1_2
+(25 4) routing lft_op_2 <X> lc_trk_g1_2
+(25 4) routing sp12_h_l_1 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_18 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2
+(25 5) routing bnr_op_2 <X> lc_trk_g1_2
+(25 5) routing sp12_h_l_1 <X> lc_trk_g1_2
+(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_18 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2
+(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 6) routing bnr_op_6 <X> lc_trk_g1_6
+(25 6) routing lft_op_6 <X> lc_trk_g1_6
+(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6
+(25 7) routing bnr_op_6 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6
+(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6
+(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 8) routing bnl_op_2 <X> lc_trk_g2_2
+(25 8) routing rgt_op_2 <X> lc_trk_g2_2
+(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 8) routing sp4_v_b_34 <X> lc_trk_g2_2
+(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2
+(25 9) routing bnl_op_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_b_18 <X> lc_trk_g2_2
+(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2
+(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2
+(25 9) routing sp4_v_b_34 <X> lc_trk_g2_2
+(25 9) routing tnl_op_2 <X> lc_trk_g2_2
+(26 0) routing lc_trk_g0_4 <X> input0_0
+(26 0) routing lc_trk_g0_6 <X> input0_0
+(26 0) routing lc_trk_g1_5 <X> input0_0
+(26 0) routing lc_trk_g1_7 <X> input0_0
+(26 0) routing lc_trk_g2_4 <X> input0_0
+(26 0) routing lc_trk_g2_6 <X> input0_0
+(26 0) routing lc_trk_g3_5 <X> input0_0
+(26 0) routing lc_trk_g3_7 <X> input0_0
+(26 1) routing lc_trk_g0_2 <X> input0_0
+(26 1) routing lc_trk_g0_6 <X> input0_0
+(26 1) routing lc_trk_g1_3 <X> input0_0
+(26 1) routing lc_trk_g1_7 <X> input0_0
+(26 1) routing lc_trk_g2_2 <X> input0_0
+(26 1) routing lc_trk_g2_6 <X> input0_0
+(26 1) routing lc_trk_g3_3 <X> input0_0
+(26 1) routing lc_trk_g3_7 <X> input0_0
+(26 10) routing lc_trk_g0_5 <X> input0_5
+(26 10) routing lc_trk_g0_7 <X> input0_5
+(26 10) routing lc_trk_g1_4 <X> input0_5
+(26 10) routing lc_trk_g1_6 <X> input0_5
+(26 10) routing lc_trk_g2_5 <X> input0_5
+(26 10) routing lc_trk_g2_7 <X> input0_5
+(26 10) routing lc_trk_g3_4 <X> input0_5
+(26 10) routing lc_trk_g3_6 <X> input0_5
+(26 11) routing lc_trk_g0_3 <X> input0_5
+(26 11) routing lc_trk_g0_7 <X> input0_5
+(26 11) routing lc_trk_g1_2 <X> input0_5
+(26 11) routing lc_trk_g1_6 <X> input0_5
+(26 11) routing lc_trk_g2_3 <X> input0_5
+(26 11) routing lc_trk_g2_7 <X> input0_5
+(26 11) routing lc_trk_g3_2 <X> input0_5
+(26 11) routing lc_trk_g3_6 <X> input0_5
+(26 12) routing lc_trk_g0_4 <X> input0_6
+(26 12) routing lc_trk_g0_6 <X> input0_6
+(26 12) routing lc_trk_g1_5 <X> input0_6
+(26 12) routing lc_trk_g1_7 <X> input0_6
+(26 12) routing lc_trk_g2_4 <X> input0_6
+(26 12) routing lc_trk_g2_6 <X> input0_6
+(26 12) routing lc_trk_g3_5 <X> input0_6
+(26 12) routing lc_trk_g3_7 <X> input0_6
+(26 13) routing lc_trk_g0_2 <X> input0_6
+(26 13) routing lc_trk_g0_6 <X> input0_6
+(26 13) routing lc_trk_g1_3 <X> input0_6
+(26 13) routing lc_trk_g1_7 <X> input0_6
+(26 13) routing lc_trk_g2_2 <X> input0_6
+(26 13) routing lc_trk_g2_6 <X> input0_6
+(26 13) routing lc_trk_g3_3 <X> input0_6
+(26 13) routing lc_trk_g3_7 <X> input0_6
+(26 14) routing lc_trk_g0_5 <X> input0_7
+(26 14) routing lc_trk_g0_7 <X> input0_7
+(26 14) routing lc_trk_g1_4 <X> input0_7
+(26 14) routing lc_trk_g1_6 <X> input0_7
+(26 14) routing lc_trk_g2_5 <X> input0_7
+(26 14) routing lc_trk_g2_7 <X> input0_7
+(26 14) routing lc_trk_g3_4 <X> input0_7
+(26 14) routing lc_trk_g3_6 <X> input0_7
+(26 15) routing lc_trk_g0_3 <X> input0_7
+(26 15) routing lc_trk_g0_7 <X> input0_7
+(26 15) routing lc_trk_g1_2 <X> input0_7
+(26 15) routing lc_trk_g1_6 <X> input0_7
+(26 15) routing lc_trk_g2_3 <X> input0_7
+(26 15) routing lc_trk_g2_7 <X> input0_7
+(26 15) routing lc_trk_g3_2 <X> input0_7
+(26 15) routing lc_trk_g3_6 <X> input0_7
+(26 2) routing lc_trk_g0_5 <X> input0_1
+(26 2) routing lc_trk_g0_7 <X> input0_1
+(26 2) routing lc_trk_g1_4 <X> input0_1
+(26 2) routing lc_trk_g1_6 <X> input0_1
+(26 2) routing lc_trk_g2_5 <X> input0_1
+(26 2) routing lc_trk_g2_7 <X> input0_1
+(26 2) routing lc_trk_g3_4 <X> input0_1
+(26 2) routing lc_trk_g3_6 <X> input0_1
+(26 3) routing lc_trk_g0_3 <X> input0_1
+(26 3) routing lc_trk_g0_7 <X> input0_1
+(26 3) routing lc_trk_g1_2 <X> input0_1
+(26 3) routing lc_trk_g1_6 <X> input0_1
+(26 3) routing lc_trk_g2_3 <X> input0_1
+(26 3) routing lc_trk_g2_7 <X> input0_1
+(26 3) routing lc_trk_g3_2 <X> input0_1
+(26 3) routing lc_trk_g3_6 <X> input0_1
+(26 4) routing lc_trk_g0_4 <X> input0_2
+(26 4) routing lc_trk_g0_6 <X> input0_2
+(26 4) routing lc_trk_g1_5 <X> input0_2
+(26 4) routing lc_trk_g1_7 <X> input0_2
+(26 4) routing lc_trk_g2_4 <X> input0_2
+(26 4) routing lc_trk_g2_6 <X> input0_2
+(26 4) routing lc_trk_g3_5 <X> input0_2
+(26 4) routing lc_trk_g3_7 <X> input0_2
+(26 5) routing lc_trk_g0_2 <X> input0_2
+(26 5) routing lc_trk_g0_6 <X> input0_2
+(26 5) routing lc_trk_g1_3 <X> input0_2
+(26 5) routing lc_trk_g1_7 <X> input0_2
+(26 5) routing lc_trk_g2_2 <X> input0_2
+(26 5) routing lc_trk_g2_6 <X> input0_2
+(26 5) routing lc_trk_g3_3 <X> input0_2
+(26 5) routing lc_trk_g3_7 <X> input0_2
+(26 6) routing lc_trk_g0_5 <X> input0_3
+(26 6) routing lc_trk_g0_7 <X> input0_3
+(26 6) routing lc_trk_g1_4 <X> input0_3
+(26 6) routing lc_trk_g1_6 <X> input0_3
+(26 6) routing lc_trk_g2_5 <X> input0_3
+(26 6) routing lc_trk_g2_7 <X> input0_3
+(26 6) routing lc_trk_g3_4 <X> input0_3
+(26 6) routing lc_trk_g3_6 <X> input0_3
+(26 7) routing lc_trk_g0_3 <X> input0_3
+(26 7) routing lc_trk_g0_7 <X> input0_3
+(26 7) routing lc_trk_g1_2 <X> input0_3
+(26 7) routing lc_trk_g1_6 <X> input0_3
+(26 7) routing lc_trk_g2_3 <X> input0_3
+(26 7) routing lc_trk_g2_7 <X> input0_3
+(26 7) routing lc_trk_g3_2 <X> input0_3
+(26 7) routing lc_trk_g3_6 <X> input0_3
+(26 8) routing lc_trk_g0_4 <X> input0_4
+(26 8) routing lc_trk_g0_6 <X> input0_4
+(26 8) routing lc_trk_g1_5 <X> input0_4
+(26 8) routing lc_trk_g1_7 <X> input0_4
+(26 8) routing lc_trk_g2_4 <X> input0_4
+(26 8) routing lc_trk_g2_6 <X> input0_4
+(26 8) routing lc_trk_g3_5 <X> input0_4
+(26 8) routing lc_trk_g3_7 <X> input0_4
+(26 9) routing lc_trk_g0_2 <X> input0_4
+(26 9) routing lc_trk_g0_6 <X> input0_4
+(26 9) routing lc_trk_g1_3 <X> input0_4
+(26 9) routing lc_trk_g1_7 <X> input0_4
+(26 9) routing lc_trk_g2_2 <X> input0_4
+(26 9) routing lc_trk_g2_6 <X> input0_4
+(26 9) routing lc_trk_g3_3 <X> input0_4
+(26 9) routing lc_trk_g3_7 <X> input0_4
+(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15
+(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15
+(27 1) routing lc_trk_g1_1 <X> input0_0
+(27 1) routing lc_trk_g1_3 <X> input0_0
+(27 1) routing lc_trk_g1_5 <X> input0_0
+(27 1) routing lc_trk_g1_7 <X> input0_0
+(27 1) routing lc_trk_g3_1 <X> input0_0
+(27 1) routing lc_trk_g3_3 <X> input0_0
+(27 1) routing lc_trk_g3_5 <X> input0_0
+(27 1) routing lc_trk_g3_7 <X> input0_0
+(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10
+(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10
+(27 11) routing lc_trk_g1_0 <X> input0_5
+(27 11) routing lc_trk_g1_2 <X> input0_5
+(27 11) routing lc_trk_g1_4 <X> input0_5
+(27 11) routing lc_trk_g1_6 <X> input0_5
+(27 11) routing lc_trk_g3_0 <X> input0_5
+(27 11) routing lc_trk_g3_2 <X> input0_5
+(27 11) routing lc_trk_g3_4 <X> input0_5
+(27 11) routing lc_trk_g3_6 <X> input0_5
+(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9
+(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9
+(27 13) routing lc_trk_g1_1 <X> input0_6
+(27 13) routing lc_trk_g1_3 <X> input0_6
+(27 13) routing lc_trk_g1_5 <X> input0_6
+(27 13) routing lc_trk_g1_7 <X> input0_6
+(27 13) routing lc_trk_g3_1 <X> input0_6
+(27 13) routing lc_trk_g3_3 <X> input0_6
+(27 13) routing lc_trk_g3_5 <X> input0_6
+(27 13) routing lc_trk_g3_7 <X> input0_6
+(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8
+(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8
+(27 15) routing lc_trk_g1_0 <X> input0_7
+(27 15) routing lc_trk_g1_2 <X> input0_7
+(27 15) routing lc_trk_g1_4 <X> input0_7
+(27 15) routing lc_trk_g1_6 <X> input0_7
+(27 15) routing lc_trk_g3_0 <X> input0_7
+(27 15) routing lc_trk_g3_2 <X> input0_7
+(27 15) routing lc_trk_g3_4 <X> input0_7
+(27 15) routing lc_trk_g3_6 <X> input0_7
+(27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14
+(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14
+(27 3) routing lc_trk_g1_0 <X> input0_1
+(27 3) routing lc_trk_g1_2 <X> input0_1
+(27 3) routing lc_trk_g1_4 <X> input0_1
+(27 3) routing lc_trk_g1_6 <X> input0_1
+(27 3) routing lc_trk_g3_0 <X> input0_1
+(27 3) routing lc_trk_g3_2 <X> input0_1
+(27 3) routing lc_trk_g3_4 <X> input0_1
+(27 3) routing lc_trk_g3_6 <X> input0_1
+(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13
+(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13
+(27 5) routing lc_trk_g1_1 <X> input0_2
+(27 5) routing lc_trk_g1_3 <X> input0_2
+(27 5) routing lc_trk_g1_5 <X> input0_2
+(27 5) routing lc_trk_g1_7 <X> input0_2
+(27 5) routing lc_trk_g3_1 <X> input0_2
+(27 5) routing lc_trk_g3_3 <X> input0_2
+(27 5) routing lc_trk_g3_5 <X> input0_2
+(27 5) routing lc_trk_g3_7 <X> input0_2
+(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12
+(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12
+(27 7) routing lc_trk_g1_0 <X> input0_3
+(27 7) routing lc_trk_g1_2 <X> input0_3
+(27 7) routing lc_trk_g1_4 <X> input0_3
+(27 7) routing lc_trk_g1_6 <X> input0_3
+(27 7) routing lc_trk_g3_0 <X> input0_3
+(27 7) routing lc_trk_g3_2 <X> input0_3
+(27 7) routing lc_trk_g3_4 <X> input0_3
+(27 7) routing lc_trk_g3_6 <X> input0_3
+(27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11
+(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11
+(27 9) routing lc_trk_g1_1 <X> input0_4
+(27 9) routing lc_trk_g1_3 <X> input0_4
+(27 9) routing lc_trk_g1_5 <X> input0_4
+(27 9) routing lc_trk_g1_7 <X> input0_4
+(27 9) routing lc_trk_g3_1 <X> input0_4
+(27 9) routing lc_trk_g3_3 <X> input0_4
+(27 9) routing lc_trk_g3_5 <X> input0_4
+(27 9) routing lc_trk_g3_7 <X> input0_4
+(28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15
+(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15
+(28 1) routing lc_trk_g2_0 <X> input0_0
+(28 1) routing lc_trk_g2_2 <X> input0_0
+(28 1) routing lc_trk_g2_4 <X> input0_0
+(28 1) routing lc_trk_g2_6 <X> input0_0
+(28 1) routing lc_trk_g3_1 <X> input0_0
+(28 1) routing lc_trk_g3_3 <X> input0_0
+(28 1) routing lc_trk_g3_5 <X> input0_0
+(28 1) routing lc_trk_g3_7 <X> input0_0
+(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10
+(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10
+(28 11) routing lc_trk_g2_1 <X> input0_5
+(28 11) routing lc_trk_g2_3 <X> input0_5
+(28 11) routing lc_trk_g2_5 <X> input0_5
+(28 11) routing lc_trk_g2_7 <X> input0_5
+(28 11) routing lc_trk_g3_0 <X> input0_5
+(28 11) routing lc_trk_g3_2 <X> input0_5
+(28 11) routing lc_trk_g3_4 <X> input0_5
+(28 11) routing lc_trk_g3_6 <X> input0_5
+(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9
+(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9
+(28 13) routing lc_trk_g2_0 <X> input0_6
+(28 13) routing lc_trk_g2_2 <X> input0_6
+(28 13) routing lc_trk_g2_4 <X> input0_6
+(28 13) routing lc_trk_g2_6 <X> input0_6
+(28 13) routing lc_trk_g3_1 <X> input0_6
+(28 13) routing lc_trk_g3_3 <X> input0_6
+(28 13) routing lc_trk_g3_5 <X> input0_6
+(28 13) routing lc_trk_g3_7 <X> input0_6
+(28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8
+(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8
+(28 15) routing lc_trk_g2_1 <X> input0_7
+(28 15) routing lc_trk_g2_3 <X> input0_7
+(28 15) routing lc_trk_g2_5 <X> input0_7
+(28 15) routing lc_trk_g2_7 <X> input0_7
+(28 15) routing lc_trk_g3_0 <X> input0_7
+(28 15) routing lc_trk_g3_2 <X> input0_7
+(28 15) routing lc_trk_g3_4 <X> input0_7
+(28 15) routing lc_trk_g3_6 <X> input0_7
+(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14
+(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14
+(28 3) routing lc_trk_g2_1 <X> input0_1
+(28 3) routing lc_trk_g2_3 <X> input0_1
+(28 3) routing lc_trk_g2_5 <X> input0_1
+(28 3) routing lc_trk_g2_7 <X> input0_1
+(28 3) routing lc_trk_g3_0 <X> input0_1
+(28 3) routing lc_trk_g3_2 <X> input0_1
+(28 3) routing lc_trk_g3_4 <X> input0_1
+(28 3) routing lc_trk_g3_6 <X> input0_1
+(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13
+(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13
+(28 5) routing lc_trk_g2_0 <X> input0_2
+(28 5) routing lc_trk_g2_2 <X> input0_2
+(28 5) routing lc_trk_g2_4 <X> input0_2
+(28 5) routing lc_trk_g2_6 <X> input0_2
+(28 5) routing lc_trk_g3_1 <X> input0_2
+(28 5) routing lc_trk_g3_3 <X> input0_2
+(28 5) routing lc_trk_g3_5 <X> input0_2
+(28 5) routing lc_trk_g3_7 <X> input0_2
+(28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12
+(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12
+(28 7) routing lc_trk_g2_1 <X> input0_3
+(28 7) routing lc_trk_g2_3 <X> input0_3
+(28 7) routing lc_trk_g2_5 <X> input0_3
+(28 7) routing lc_trk_g2_7 <X> input0_3
+(28 7) routing lc_trk_g3_0 <X> input0_3
+(28 7) routing lc_trk_g3_2 <X> input0_3
+(28 7) routing lc_trk_g3_4 <X> input0_3
+(28 7) routing lc_trk_g3_6 <X> input0_3
+(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11
+(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11
+(28 9) routing lc_trk_g2_0 <X> input0_4
+(28 9) routing lc_trk_g2_2 <X> input0_4
+(28 9) routing lc_trk_g2_4 <X> input0_4
+(28 9) routing lc_trk_g2_6 <X> input0_4
+(28 9) routing lc_trk_g3_1 <X> input0_4
+(28 9) routing lc_trk_g3_3 <X> input0_4
+(28 9) routing lc_trk_g3_5 <X> input0_4
+(28 9) routing lc_trk_g3_7 <X> input0_4
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_9
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_9
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_13
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_13
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_12
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_12
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4
+(3 0) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 0) routing sp12_v_t_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_l_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 10) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 10) routing sp12_v_t_22 <X> sp12_h_l_22
+(3 11) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 11) routing sp12_v_b_1 <X> sp12_h_l_22
+(3 12) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 12) routing sp12_v_t_22 <X> sp12_h_r_1
+(3 13) routing sp12_h_l_22 <X> sp12_h_r_1
+(3 13) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 14) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 14) routing sp12_v_b_1 <X> sp12_v_t_22
+(3 15) routing sp12_h_l_22 <X> sp12_v_t_22
+(3 15) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 2) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 2) routing sp12_v_t_23 <X> sp12_h_l_23
+(3 3) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 3) routing sp12_v_b_0 <X> sp12_h_l_23
+(3 4) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 4) routing sp12_v_t_23 <X> sp12_h_r_0
+(3 5) routing sp12_h_l_23 <X> sp12_h_r_0
+(3 5) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 6) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 6) routing sp12_v_b_0 <X> sp12_v_t_23
+(3 7) routing sp12_h_l_23 <X> sp12_v_t_23
+(3 7) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 8) routing sp12_h_r_1 <X> sp12_v_b_1
+(3 8) routing sp12_v_t_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_l_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_r_1 <X> sp12_v_b_1
+(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15
+(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15
+(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15
+(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10
+(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10
+(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10
+(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_9
+(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_9
+(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9
+(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8
+(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8
+(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8
+(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14
+(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14
+(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14
+(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_13
+(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13
+(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13
+(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12
+(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12
+(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11
+(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11
+(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15
+(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15
+(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15
+(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10
+(31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10
+(31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10
+(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9
+(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9
+(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9
+(31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8
+(31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8
+(31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8
+(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14
+(31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14
+(31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14
+(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13
+(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13
+(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13
+(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12
+(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12
+(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11
+(31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11
+(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15
+(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15
+(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10
+(33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10
+(33 11) routing lc_trk_g2_1 <X> input2_5
+(33 11) routing lc_trk_g2_3 <X> input2_5
+(33 11) routing lc_trk_g2_5 <X> input2_5
+(33 11) routing lc_trk_g2_7 <X> input2_5
+(33 11) routing lc_trk_g3_0 <X> input2_5
+(33 11) routing lc_trk_g3_2 <X> input2_5
+(33 11) routing lc_trk_g3_4 <X> input2_5
+(33 11) routing lc_trk_g3_6 <X> input2_5
+(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9
+(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9
+(33 13) routing lc_trk_g2_0 <X> input2_6
+(33 13) routing lc_trk_g2_2 <X> input2_6
+(33 13) routing lc_trk_g2_4 <X> input2_6
+(33 13) routing lc_trk_g2_6 <X> input2_6
+(33 13) routing lc_trk_g3_1 <X> input2_6
+(33 13) routing lc_trk_g3_3 <X> input2_6
+(33 13) routing lc_trk_g3_5 <X> input2_6
+(33 13) routing lc_trk_g3_7 <X> input2_6
+(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8
+(33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8
+(33 15) routing lc_trk_g2_1 <X> input2_7
+(33 15) routing lc_trk_g2_3 <X> input2_7
+(33 15) routing lc_trk_g2_5 <X> input2_7
+(33 15) routing lc_trk_g2_7 <X> input2_7
+(33 15) routing lc_trk_g3_0 <X> input2_7
+(33 15) routing lc_trk_g3_2 <X> input2_7
+(33 15) routing lc_trk_g3_4 <X> input2_7
+(33 15) routing lc_trk_g3_6 <X> input2_7
+(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14
+(33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14
+(33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13
+(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13
+(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12
+(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11
+(34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15
+(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15
+(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10
+(34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10
+(34 11) routing lc_trk_g1_0 <X> input2_5
+(34 11) routing lc_trk_g1_2 <X> input2_5
+(34 11) routing lc_trk_g1_4 <X> input2_5
+(34 11) routing lc_trk_g1_6 <X> input2_5
+(34 11) routing lc_trk_g3_0 <X> input2_5
+(34 11) routing lc_trk_g3_2 <X> input2_5
+(34 11) routing lc_trk_g3_4 <X> input2_5
+(34 11) routing lc_trk_g3_6 <X> input2_5
+(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9
+(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9
+(34 13) routing lc_trk_g1_1 <X> input2_6
+(34 13) routing lc_trk_g1_3 <X> input2_6
+(34 13) routing lc_trk_g1_5 <X> input2_6
+(34 13) routing lc_trk_g1_7 <X> input2_6
+(34 13) routing lc_trk_g3_1 <X> input2_6
+(34 13) routing lc_trk_g3_3 <X> input2_6
+(34 13) routing lc_trk_g3_5 <X> input2_6
+(34 13) routing lc_trk_g3_7 <X> input2_6
+(34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8
+(34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8
+(34 15) routing lc_trk_g1_0 <X> input2_7
+(34 15) routing lc_trk_g1_2 <X> input2_7
+(34 15) routing lc_trk_g1_4 <X> input2_7
+(34 15) routing lc_trk_g1_6 <X> input2_7
+(34 15) routing lc_trk_g3_0 <X> input2_7
+(34 15) routing lc_trk_g3_2 <X> input2_7
+(34 15) routing lc_trk_g3_4 <X> input2_7
+(34 15) routing lc_trk_g3_6 <X> input2_7
+(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14
+(34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14
+(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13
+(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13
+(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12
+(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11
+(35 10) routing lc_trk_g0_5 <X> input2_5
+(35 10) routing lc_trk_g0_7 <X> input2_5
+(35 10) routing lc_trk_g1_4 <X> input2_5
+(35 10) routing lc_trk_g1_6 <X> input2_5
+(35 10) routing lc_trk_g2_5 <X> input2_5
+(35 10) routing lc_trk_g2_7 <X> input2_5
+(35 10) routing lc_trk_g3_4 <X> input2_5
+(35 10) routing lc_trk_g3_6 <X> input2_5
+(35 11) routing lc_trk_g0_3 <X> input2_5
+(35 11) routing lc_trk_g0_7 <X> input2_5
+(35 11) routing lc_trk_g1_2 <X> input2_5
+(35 11) routing lc_trk_g1_6 <X> input2_5
+(35 11) routing lc_trk_g2_3 <X> input2_5
+(35 11) routing lc_trk_g2_7 <X> input2_5
+(35 11) routing lc_trk_g3_2 <X> input2_5
+(35 11) routing lc_trk_g3_6 <X> input2_5
+(35 12) routing lc_trk_g0_4 <X> input2_6
+(35 12) routing lc_trk_g0_6 <X> input2_6
+(35 12) routing lc_trk_g1_5 <X> input2_6
+(35 12) routing lc_trk_g1_7 <X> input2_6
+(35 12) routing lc_trk_g2_4 <X> input2_6
+(35 12) routing lc_trk_g2_6 <X> input2_6
+(35 12) routing lc_trk_g3_5 <X> input2_6
+(35 12) routing lc_trk_g3_7 <X> input2_6
+(35 13) routing lc_trk_g0_2 <X> input2_6
+(35 13) routing lc_trk_g0_6 <X> input2_6
+(35 13) routing lc_trk_g1_3 <X> input2_6
+(35 13) routing lc_trk_g1_7 <X> input2_6
+(35 13) routing lc_trk_g2_2 <X> input2_6
+(35 13) routing lc_trk_g2_6 <X> input2_6
+(35 13) routing lc_trk_g3_3 <X> input2_6
+(35 13) routing lc_trk_g3_7 <X> input2_6
+(35 14) routing lc_trk_g0_5 <X> input2_7
+(35 14) routing lc_trk_g0_7 <X> input2_7
+(35 14) routing lc_trk_g1_4 <X> input2_7
+(35 14) routing lc_trk_g1_6 <X> input2_7
+(35 14) routing lc_trk_g2_5 <X> input2_7
+(35 14) routing lc_trk_g2_7 <X> input2_7
+(35 14) routing lc_trk_g3_4 <X> input2_7
+(35 14) routing lc_trk_g3_6 <X> input2_7
+(35 15) routing lc_trk_g0_3 <X> input2_7
+(35 15) routing lc_trk_g0_7 <X> input2_7
+(35 15) routing lc_trk_g1_2 <X> input2_7
+(35 15) routing lc_trk_g1_6 <X> input2_7
+(35 15) routing lc_trk_g2_3 <X> input2_7
+(35 15) routing lc_trk_g2_7 <X> input2_7
+(35 15) routing lc_trk_g3_2 <X> input2_7
+(35 15) routing lc_trk_g3_6 <X> input2_7
+(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32
+(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0
+(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42
+(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10
+(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44
+(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1
+(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46
+(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3
+(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34
+(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2
+(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36
+(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4
+(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27
+(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6
+(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40
+(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8
+(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8
+(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16
+(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1
+(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_10 sp4_h_l_15
+(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_9 sp12_h_l_3
+(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_9 sp4_h_r_28
+(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_8 sp12_h_l_5
+(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_8 sp4_h_l_19
+(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_14 sp12_h_l_9
+(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_14 sp4_h_r_18
+(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_13 sp12_h_r_12
+(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_13 sp4_h_l_9
+(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_12 sp12_h_r_14
+(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_12 sp4_h_l_11
+(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_11 sp12_h_r_0
+(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24
+(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32
+(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0
+(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15
+(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17
+(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28
+(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20
+(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19
+(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22
+(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34
+(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2
+(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25
+(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4
+(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27
+(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6
+(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13
+(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15
+(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0
+(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16
+(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31
+(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_10 sp4_v_b_10
+(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_9 sp4_v_b_44
+(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_9 sp4_v_b_12
+(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_8 sp4_v_b_46
+(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_8 sp4_v_b_14
+(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_14 sp12_v_t_1
+(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_14 sp4_v_t_7
+(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_13 sp12_v_b_4
+(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_13 sp4_v_b_20
+(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_12 sp12_v_t_5
+(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_12 sp4_v_t_11
+(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_11 sp4_v_b_40
+(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_11 sp4_v_b_8
+(4 0) routing sp4_h_l_37 <X> sp4_v_b_0
+(4 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_37 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(4 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(4 1) routing sp4_h_l_44 <X> sp4_h_r_0
+(4 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(4 1) routing sp4_v_t_42 <X> sp4_h_r_0
+(4 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(4 10) routing sp4_h_r_6 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_6 <X> sp4_v_t_43
+(4 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(4 11) routing sp4_h_r_3 <X> sp4_h_l_43
+(4 11) routing sp4_v_b_1 <X> sp4_h_l_43
+(4 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(4 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(4 12) routing sp4_h_l_44 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_44 <X> sp4_v_b_9
+(4 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(4 13) routing sp4_h_l_43 <X> sp4_h_r_9
+(4 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(4 13) routing sp4_v_t_41 <X> sp4_h_r_9
+(4 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(4 14) routing sp4_h_r_9 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_9 <X> sp4_v_t_44
+(4 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(4 15) routing sp4_h_r_6 <X> sp4_h_l_44
+(4 15) routing sp4_v_b_4 <X> sp4_h_l_44
+(4 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(4 2) routing sp4_h_r_0 <X> sp4_v_t_37
+(4 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_0 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(4 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(4 3) routing sp4_h_r_9 <X> sp4_h_l_37
+(4 3) routing sp4_v_b_7 <X> sp4_h_l_37
+(4 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(4 4) routing sp4_h_l_38 <X> sp4_v_b_3
+(4 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_38 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(4 5) routing sp4_h_l_37 <X> sp4_h_r_3
+(4 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(4 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(4 5) routing sp4_v_t_47 <X> sp4_h_r_3
+(4 6) routing sp4_h_r_3 <X> sp4_v_t_38
+(4 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_3 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(4 7) routing sp4_h_r_0 <X> sp4_h_l_38
+(4 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(4 7) routing sp4_v_b_10 <X> sp4_h_l_38
+(4 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(4 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(4 8) routing sp4_h_l_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(4 9) routing sp4_h_l_38 <X> sp4_h_r_6
+(4 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(4 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(4 9) routing sp4_v_t_36 <X> sp4_h_r_6
+(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17
+(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16
+(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27
+(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10
+(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29
+(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11
+(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31
+(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14
+(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19
+(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18
+(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_21
+(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_13 sp12_v_b_20
+(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_23
+(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_12 sp12_v_b_22
+(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_25
+(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_11 sp12_v_t_7
+(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_33
+(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_1
+(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_43
+(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_11
+(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_45
+(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_13
+(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47
+(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15
+(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35
+(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3
+(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37
+(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5
+(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39
+(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_7
+(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_41
+(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_9
+(5 0) routing sp4_h_l_44 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_0 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_6 <X> sp4_h_r_0
+(5 0) routing sp4_v_t_37 <X> sp4_h_r_0
+(5 1) routing sp4_h_l_37 <X> sp4_v_b_0
+(5 1) routing sp4_h_l_43 <X> sp4_v_b_0
+(5 1) routing sp4_h_r_0 <X> sp4_v_b_0
+(5 1) routing sp4_v_t_44 <X> sp4_v_b_0
+(5 10) routing sp4_h_r_3 <X> sp4_h_l_43
+(5 10) routing sp4_v_b_6 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_37 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_43 <X> sp4_h_l_43
+(5 11) routing sp4_h_l_43 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_0 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_6 <X> sp4_v_t_43
+(5 11) routing sp4_v_b_3 <X> sp4_v_t_43
+(5 12) routing sp4_h_l_43 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_3 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_9 <X> sp4_h_r_9
+(5 12) routing sp4_v_t_44 <X> sp4_h_r_9
+(5 13) routing sp4_h_l_38 <X> sp4_v_b_9
+(5 13) routing sp4_h_l_44 <X> sp4_v_b_9
+(5 13) routing sp4_h_r_9 <X> sp4_v_b_9
+(5 13) routing sp4_v_t_43 <X> sp4_v_b_9
+(5 14) routing sp4_h_r_6 <X> sp4_h_l_44
+(5 14) routing sp4_v_b_9 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_38 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_44 <X> sp4_h_l_44
+(5 15) routing sp4_h_l_44 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_3 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_9 <X> sp4_v_t_44
+(5 15) routing sp4_v_b_6 <X> sp4_v_t_44
+(5 2) routing sp4_h_r_9 <X> sp4_h_l_37
+(5 2) routing sp4_v_b_0 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_37 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_43 <X> sp4_h_l_37
+(5 3) routing sp4_h_l_37 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_0 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_6 <X> sp4_v_t_37
+(5 3) routing sp4_v_b_9 <X> sp4_v_t_37
+(5 4) routing sp4_h_l_37 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_3 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_9 <X> sp4_h_r_3
+(5 4) routing sp4_v_t_38 <X> sp4_h_r_3
+(5 5) routing sp4_h_l_38 <X> sp4_v_b_3
+(5 5) routing sp4_h_l_44 <X> sp4_v_b_3
+(5 5) routing sp4_h_r_3 <X> sp4_v_b_3
+(5 5) routing sp4_v_t_37 <X> sp4_v_b_3
+(5 6) routing sp4_h_r_0 <X> sp4_h_l_38
+(5 6) routing sp4_v_b_3 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_38 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_44 <X> sp4_h_l_38
+(5 7) routing sp4_h_l_38 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_3 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_9 <X> sp4_v_t_38
+(5 7) routing sp4_v_b_0 <X> sp4_v_t_38
+(5 8) routing sp4_h_l_38 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_0 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_6 <X> sp4_h_r_6
+(5 8) routing sp4_v_t_43 <X> sp4_h_r_6
+(5 9) routing sp4_h_l_37 <X> sp4_v_b_6
+(5 9) routing sp4_h_l_43 <X> sp4_v_b_6
+(5 9) routing sp4_h_r_6 <X> sp4_v_b_6
+(5 9) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(6 0) routing sp4_h_r_7 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_44 <X> sp4_v_b_0
+(6 1) routing sp4_h_l_37 <X> sp4_h_r_0
+(6 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_0 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(6 10) routing sp4_h_l_36 <X> sp4_v_t_43
+(6 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_3 <X> sp4_v_t_43
+(6 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(6 11) routing sp4_h_r_6 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_43 <X> sp4_h_l_43
+(6 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(6 12) routing sp4_h_r_4 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_43 <X> sp4_v_b_9
+(6 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(6 13) routing sp4_h_l_44 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_9 <X> sp4_h_r_9
+(6 14) routing sp4_h_l_41 <X> sp4_v_t_44
+(6 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_6 <X> sp4_v_t_44
+(6 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(6 15) routing sp4_h_r_9 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_44 <X> sp4_h_l_44
+(6 2) routing sp4_h_l_42 <X> sp4_v_t_37
+(6 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_9 <X> sp4_v_t_37
+(6 3) routing sp4_h_r_0 <X> sp4_h_l_37
+(6 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_37 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(6 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(6 4) routing sp4_h_r_10 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_37 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(6 5) routing sp4_h_l_38 <X> sp4_h_r_3
+(6 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_3 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(6 6) routing sp4_h_l_47 <X> sp4_v_t_38
+(6 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_0 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(6 7) routing sp4_h_r_3 <X> sp4_h_l_38
+(6 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_38 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(6 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(6 8) routing sp4_h_r_1 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(6 9) routing sp4_h_l_43 <X> sp4_h_r_6
+(6 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_6 <X> sp4_h_r_6
+(7 1) Ram config bit: MEMB_Power_Up_Control
+(7 10) Column buffer control bit: MEMB_colbuf_cntl_3
+(7 11) Column buffer control bit: MEMB_colbuf_cntl_2
+(7 12) Column buffer control bit: MEMB_colbuf_cntl_5
+(7 13) Column buffer control bit: MEMB_colbuf_cntl_4
+(7 14) Column buffer control bit: MEMB_colbuf_cntl_7
+(7 15) Column buffer control bit: MEMB_colbuf_cntl_6
+(7 8) Column buffer control bit: MEMB_colbuf_cntl_1
+(7 9) Column buffer control bit: MEMB_colbuf_cntl_0
+(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
+(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(8 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(8 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(8 1) routing sp4_h_r_1 <X> sp4_v_b_1
+(8 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(8 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(8 10) routing sp4_h_r_7 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(8 11) routing sp4_h_l_42 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(8 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(8 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(8 12) routing sp4_h_l_47 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(8 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(8 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(8 13) routing sp4_h_r_10 <X> sp4_v_b_10
+(8 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(8 14) routing sp4_h_r_10 <X> sp4_h_l_47
+(8 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(8 15) routing sp4_h_l_47 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(8 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(8 2) routing sp4_h_r_1 <X> sp4_h_l_36
+(8 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(8 3) routing sp4_h_l_36 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(8 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(8 4) routing sp4_h_l_41 <X> sp4_h_r_4
+(8 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(8 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(8 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(8 5) routing sp4_h_r_4 <X> sp4_v_b_4
+(8 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(8 6) routing sp4_h_r_4 <X> sp4_h_l_41
+(8 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(8 7) routing sp4_h_l_41 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(8 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(8 8) routing sp4_h_l_42 <X> sp4_h_r_7
+(8 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(8 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(8 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(8 9) routing sp4_h_r_7 <X> sp4_v_b_7
+(8 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(9 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(9 0) routing sp4_v_t_36 <X> sp4_h_r_1
+(9 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(9 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_36 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(9 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(9 10) routing sp4_v_b_7 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(9 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(9 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_7 <X> sp4_v_t_42
+(9 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(9 12) routing sp4_v_t_47 <X> sp4_h_r_10
+(9 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(9 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_47 <X> sp4_v_b_10
+(9 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(9 14) routing sp4_v_b_10 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(9 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(9 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_10 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(9 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(9 2) routing sp4_v_b_1 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(9 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(9 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_1 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(9 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(9 4) routing sp4_v_t_41 <X> sp4_h_r_4
+(9 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(9 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_41 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(9 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(9 6) routing sp4_v_b_4 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(9 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(9 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(9 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(9 8) routing sp4_v_t_42 <X> sp4_h_r_7
+(9 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(9 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_46 <X> sp4_v_b_7
diff --git a/icefuzz/cached_ramt.txt b/icefuzz/cached_ramt.txt
new file mode 100644
index 0000000..c51dafa
--- /dev/null
+++ b/icefuzz/cached_ramt.txt
@@ -0,0 +1,3586 @@
+(0 0) Negative Clock bit
+(0 10) routing glb_netwk_2 <X> glb2local_2
+(0 10) routing glb_netwk_3 <X> glb2local_2
+(0 10) routing glb_netwk_6 <X> glb2local_2
+(0 10) routing glb_netwk_7 <X> glb2local_2
+(0 11) routing glb_netwk_1 <X> glb2local_2
+(0 11) routing glb_netwk_3 <X> glb2local_2
+(0 11) routing glb_netwk_5 <X> glb2local_2
+(0 11) routing glb_netwk_7 <X> glb2local_2
+(0 12) routing glb_netwk_2 <X> glb2local_3
+(0 12) routing glb_netwk_3 <X> glb2local_3
+(0 12) routing glb_netwk_6 <X> glb2local_3
+(0 12) routing glb_netwk_7 <X> glb2local_3
+(0 13) routing glb_netwk_1 <X> glb2local_3
+(0 13) routing glb_netwk_3 <X> glb2local_3
+(0 13) routing glb_netwk_5 <X> glb2local_3
+(0 13) routing glb_netwk_7 <X> glb2local_3
+(0 14) routing glb_netwk_4 <X> wire_bram/ram/RE
+(0 14) routing glb_netwk_6 <X> wire_bram/ram/RE
+(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/RE
+(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(0 15) routing glb_netwk_2 <X> wire_bram/ram/RE
+(0 15) routing glb_netwk_6 <X> wire_bram/ram/RE
+(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE
+(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(0 2) routing glb_netwk_2 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_3 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK
+(0 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK
+(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_1 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_3 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_5 <X> wire_bram/ram/RCLK
+(0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK
+(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(0 4) routing glb_netwk_7 <X> wire_bram/ram/RCLKE
+(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE
+(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(0 5) routing glb_netwk_3 <X> wire_bram/ram/RCLKE
+(0 5) routing glb_netwk_7 <X> wire_bram/ram/RCLKE
+(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE
+(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(0 6) routing glb_netwk_2 <X> glb2local_0
+(0 6) routing glb_netwk_3 <X> glb2local_0
+(0 6) routing glb_netwk_6 <X> glb2local_0
+(0 6) routing glb_netwk_7 <X> glb2local_0
+(0 7) routing glb_netwk_1 <X> glb2local_0
+(0 7) routing glb_netwk_3 <X> glb2local_0
+(0 7) routing glb_netwk_5 <X> glb2local_0
+(0 7) routing glb_netwk_7 <X> glb2local_0
+(0 8) routing glb_netwk_2 <X> glb2local_1
+(0 8) routing glb_netwk_3 <X> glb2local_1
+(0 8) routing glb_netwk_6 <X> glb2local_1
+(0 8) routing glb_netwk_7 <X> glb2local_1
+(0 9) routing glb_netwk_1 <X> glb2local_1
+(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_5 <X> glb2local_1
+(0 9) routing glb_netwk_7 <X> glb2local_1
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2
+(1 11) routing glb_netwk_4 <X> glb2local_2
+(1 11) routing glb_netwk_5 <X> glb2local_2
+(1 11) routing glb_netwk_6 <X> glb2local_2
+(1 11) routing glb_netwk_7 <X> glb2local_2
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3
+(1 13) routing glb_netwk_4 <X> glb2local_3
+(1 13) routing glb_netwk_5 <X> glb2local_3
+(1 13) routing glb_netwk_6 <X> glb2local_3
+(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
+(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/RE
+(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE
+(1 2) routing glb_netwk_4 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_5 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK
+(1 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK
+(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE
+(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0
+(1 7) routing glb_netwk_4 <X> glb2local_0
+(1 7) routing glb_netwk_5 <X> glb2local_0
+(1 7) routing glb_netwk_6 <X> glb2local_0
+(1 7) routing glb_netwk_7 <X> glb2local_0
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
+(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_5 <X> glb2local_1
+(1 9) routing glb_netwk_6 <X> glb2local_1
+(1 9) routing glb_netwk_7 <X> glb2local_1
+(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(10 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(10 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(10 0) routing sp4_v_t_45 <X> sp4_h_r_1
+(10 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(10 1) routing sp4_h_r_8 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(10 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(10 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(10 10) routing sp4_v_b_2 <X> sp4_h_l_42
+(10 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(10 11) routing sp4_h_l_39 <X> sp4_v_t_42
+(10 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(10 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(10 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(10 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(10 12) routing sp4_v_t_40 <X> sp4_h_r_10
+(10 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(10 13) routing sp4_h_r_5 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(10 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(10 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(10 14) routing sp4_v_b_5 <X> sp4_h_l_47
+(10 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(10 15) routing sp4_h_l_40 <X> sp4_v_t_47
+(10 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(10 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(10 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(10 2) routing sp4_v_b_8 <X> sp4_h_l_36
+(10 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(10 3) routing sp4_h_l_45 <X> sp4_v_t_36
+(10 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(10 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(10 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(10 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(10 4) routing sp4_v_t_46 <X> sp4_h_r_4
+(10 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(10 5) routing sp4_h_r_11 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(10 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(10 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(10 6) routing sp4_v_b_11 <X> sp4_h_l_41
+(10 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(10 7) routing sp4_h_l_46 <X> sp4_v_t_41
+(10 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(10 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(10 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(10 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(10 8) routing sp4_v_t_39 <X> sp4_h_r_7
+(10 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(10 9) routing sp4_h_r_2 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_46 <X> sp4_v_b_7
+(11 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(11 0) routing sp4_h_r_9 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_46 <X> sp4_v_b_2
+(11 1) routing sp4_h_l_39 <X> sp4_h_r_2
+(11 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_2 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(11 10) routing sp4_h_l_38 <X> sp4_v_t_45
+(11 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_5 <X> sp4_v_t_45
+(11 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(11 11) routing sp4_h_r_8 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_45 <X> sp4_h_l_45
+(11 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(11 12) routing sp4_h_r_6 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_45 <X> sp4_v_b_11
+(11 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(11 13) routing sp4_h_l_46 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_11 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(11 14) routing sp4_h_l_43 <X> sp4_v_t_46
+(11 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_8 <X> sp4_v_t_46
+(11 15) routing sp4_h_r_11 <X> sp4_h_l_46
+(11 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_46 <X> sp4_h_l_46
+(11 2) routing sp4_h_l_44 <X> sp4_v_t_39
+(11 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_11 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(11 3) routing sp4_h_r_2 <X> sp4_h_l_39
+(11 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_39 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(11 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(11 4) routing sp4_h_r_0 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_39 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(11 5) routing sp4_h_l_40 <X> sp4_h_r_5
+(11 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_5 <X> sp4_h_r_5
+(11 6) routing sp4_h_l_37 <X> sp4_v_t_40
+(11 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_2 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(11 7) routing sp4_h_r_5 <X> sp4_h_l_40
+(11 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_40 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(11 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(11 8) routing sp4_h_r_3 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_40 <X> sp4_v_b_8
+(11 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(11 9) routing sp4_h_l_45 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 0) routing sp4_h_l_46 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_2 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_8 <X> sp4_h_r_2
+(12 0) routing sp4_v_t_39 <X> sp4_h_r_2
+(12 1) routing sp4_h_l_39 <X> sp4_v_b_2
+(12 1) routing sp4_h_l_45 <X> sp4_v_b_2
+(12 1) routing sp4_h_r_2 <X> sp4_v_b_2
+(12 1) routing sp4_v_t_46 <X> sp4_v_b_2
+(12 10) routing sp4_h_r_5 <X> sp4_h_l_45
+(12 10) routing sp4_v_b_8 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_39 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_45 <X> sp4_h_l_45
+(12 11) routing sp4_h_l_45 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_2 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_8 <X> sp4_v_t_45
+(12 11) routing sp4_v_b_5 <X> sp4_v_t_45
+(12 12) routing sp4_h_l_45 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_11 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_5 <X> sp4_h_r_11
+(12 12) routing sp4_v_t_46 <X> sp4_h_r_11
+(12 13) routing sp4_h_l_40 <X> sp4_v_b_11
+(12 13) routing sp4_h_l_46 <X> sp4_v_b_11
+(12 13) routing sp4_h_r_11 <X> sp4_v_b_11
+(12 13) routing sp4_v_t_45 <X> sp4_v_b_11
+(12 14) routing sp4_h_r_8 <X> sp4_h_l_46
+(12 14) routing sp4_v_b_11 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_40 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_46 <X> sp4_h_l_46
+(12 15) routing sp4_h_l_46 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_11 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_5 <X> sp4_v_t_46
+(12 15) routing sp4_v_b_8 <X> sp4_v_t_46
+(12 2) routing sp4_h_r_11 <X> sp4_h_l_39
+(12 2) routing sp4_v_b_2 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_39 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_45 <X> sp4_h_l_39
+(12 3) routing sp4_h_l_39 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_2 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_8 <X> sp4_v_t_39
+(12 3) routing sp4_v_b_11 <X> sp4_v_t_39
+(12 4) routing sp4_h_l_39 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_11 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_5 <X> sp4_h_r_5
+(12 4) routing sp4_v_t_40 <X> sp4_h_r_5
+(12 5) routing sp4_h_l_40 <X> sp4_v_b_5
+(12 5) routing sp4_h_l_46 <X> sp4_v_b_5
+(12 5) routing sp4_h_r_5 <X> sp4_v_b_5
+(12 5) routing sp4_v_t_39 <X> sp4_v_b_5
+(12 6) routing sp4_h_r_2 <X> sp4_h_l_40
+(12 6) routing sp4_v_b_5 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_40 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_46 <X> sp4_h_l_40
+(12 7) routing sp4_h_l_40 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_11 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_5 <X> sp4_v_t_40
+(12 7) routing sp4_v_b_2 <X> sp4_v_t_40
+(12 8) routing sp4_h_l_40 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_2 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 8) routing sp4_v_t_45 <X> sp4_h_r_8
+(12 9) routing sp4_h_l_39 <X> sp4_v_b_8
+(12 9) routing sp4_h_l_45 <X> sp4_v_b_8
+(12 9) routing sp4_h_r_8 <X> sp4_v_b_8
+(12 9) routing sp4_v_t_40 <X> sp4_v_b_8
+(13 0) routing sp4_h_l_39 <X> sp4_v_b_2
+(13 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_39 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(13 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(13 1) routing sp4_h_l_46 <X> sp4_h_r_2
+(13 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(13 1) routing sp4_v_t_44 <X> sp4_h_r_2
+(13 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(13 10) routing sp4_h_r_8 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_8 <X> sp4_v_t_45
+(13 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(13 11) routing sp4_h_r_5 <X> sp4_h_l_45
+(13 11) routing sp4_v_b_3 <X> sp4_h_l_45
+(13 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(13 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(13 12) routing sp4_h_l_46 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_46 <X> sp4_v_b_11
+(13 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(13 13) routing sp4_h_l_45 <X> sp4_h_r_11
+(13 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(13 13) routing sp4_v_t_43 <X> sp4_h_r_11
+(13 14) routing sp4_h_r_11 <X> sp4_v_t_46
+(13 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_11 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(13 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(13 15) routing sp4_h_r_8 <X> sp4_h_l_46
+(13 15) routing sp4_v_b_6 <X> sp4_h_l_46
+(13 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(13 2) routing sp4_h_r_2 <X> sp4_v_t_39
+(13 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_2 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(13 3) routing sp4_h_r_11 <X> sp4_h_l_39
+(13 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(13 3) routing sp4_v_b_9 <X> sp4_h_l_39
+(13 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(13 4) routing sp4_h_l_40 <X> sp4_v_b_5
+(13 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_40 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(13 5) routing sp4_h_l_39 <X> sp4_h_r_5
+(13 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(13 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(13 5) routing sp4_v_t_37 <X> sp4_h_r_5
+(13 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(13 6) routing sp4_h_r_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(13 7) routing sp4_h_r_2 <X> sp4_h_l_40
+(13 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(13 7) routing sp4_v_b_0 <X> sp4_h_l_40
+(13 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(13 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(13 8) routing sp4_h_l_45 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_45 <X> sp4_v_b_8
+(13 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(13 9) routing sp4_h_l_40 <X> sp4_h_r_8
+(13 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(13 9) routing sp4_v_t_38 <X> sp4_h_r_8
+(14 0) routing bnr_op_0 <X> lc_trk_g0_0
+(14 0) routing lft_op_0 <X> lc_trk_g0_0
+(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing bnr_op_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0
+(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing top_op_0 <X> lc_trk_g0_0
+(14 10) routing bnl_op_4 <X> lc_trk_g2_4
+(14 10) routing rgt_op_4 <X> lc_trk_g2_4
+(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4
+(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing bnl_op_4 <X> lc_trk_g2_4
+(14 11) routing sp12_v_t_19 <X> lc_trk_g2_4
+(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4
+(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing tnl_op_4 <X> lc_trk_g2_4
+(14 12) routing bnl_op_0 <X> lc_trk_g3_0
+(14 12) routing rgt_op_0 <X> lc_trk_g3_0
+(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0
+(14 12) routing sp4_h_l_29 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 13) routing bnl_op_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(14 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0
+(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 13) routing tnl_op_0 <X> lc_trk_g3_0
+(14 14) routing bnl_op_4 <X> lc_trk_g3_4
+(14 14) routing rgt_op_4 <X> lc_trk_g3_4
+(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4
+(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing bnl_op_4 <X> lc_trk_g3_4
+(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4
+(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4
+(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing tnl_op_4 <X> lc_trk_g3_4
+(14 2) routing bnr_op_4 <X> lc_trk_g0_4
+(14 2) routing lft_op_4 <X> lc_trk_g0_4
+(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4
+(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4
+(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 3) routing bnr_op_4 <X> lc_trk_g0_4
+(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4
+(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 3) routing top_op_4 <X> lc_trk_g0_4
+(14 4) routing bnr_op_0 <X> lc_trk_g1_0
+(14 4) routing lft_op_0 <X> lc_trk_g1_0
+(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing bnr_op_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0
+(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing top_op_0 <X> lc_trk_g1_0
+(14 6) routing bnr_op_4 <X> lc_trk_g1_4
+(14 6) routing lft_op_4 <X> lc_trk_g1_4
+(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4
+(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4
+(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 7) routing bnr_op_4 <X> lc_trk_g1_4
+(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4
+(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 7) routing top_op_4 <X> lc_trk_g1_4
+(14 8) routing bnl_op_0 <X> lc_trk_g2_0
+(14 8) routing rgt_op_0 <X> lc_trk_g2_0
+(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0
+(14 8) routing sp4_h_l_29 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 9) routing bnl_op_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(14 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0
+(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 0) routing lft_op_1 <X> lc_trk_g0_1
+(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(15 1) routing lft_op_0 <X> lc_trk_g0_0
+(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(15 1) routing top_op_0 <X> lc_trk_g0_0
+(15 10) routing rgt_op_5 <X> lc_trk_g2_5
+(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(15 10) routing tnl_op_5 <X> lc_trk_g2_5
+(15 10) routing tnr_op_5 <X> lc_trk_g2_5
+(15 11) routing rgt_op_4 <X> lc_trk_g2_4
+(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(15 11) routing tnl_op_4 <X> lc_trk_g2_4
+(15 11) routing tnr_op_4 <X> lc_trk_g2_4
+(15 12) routing rgt_op_1 <X> lc_trk_g3_1
+(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(15 12) routing tnl_op_1 <X> lc_trk_g3_1
+(15 12) routing tnr_op_1 <X> lc_trk_g3_1
+(15 13) routing rgt_op_0 <X> lc_trk_g3_0
+(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(15 13) routing tnl_op_0 <X> lc_trk_g3_0
+(15 13) routing tnr_op_0 <X> lc_trk_g3_0
+(15 14) routing rgt_op_5 <X> lc_trk_g3_5
+(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(15 14) routing tnl_op_5 <X> lc_trk_g3_5
+(15 14) routing tnr_op_5 <X> lc_trk_g3_5
+(15 15) routing rgt_op_4 <X> lc_trk_g3_4
+(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(15 15) routing tnl_op_4 <X> lc_trk_g3_4
+(15 15) routing tnr_op_4 <X> lc_trk_g3_4
+(15 2) routing lft_op_5 <X> lc_trk_g0_5
+(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(15 3) routing lft_op_4 <X> lc_trk_g0_4
+(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(15 3) routing top_op_4 <X> lc_trk_g0_4
+(15 4) routing lft_op_1 <X> lc_trk_g1_1
+(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(15 5) routing lft_op_0 <X> lc_trk_g1_0
+(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(15 5) routing top_op_0 <X> lc_trk_g1_0
+(15 6) routing lft_op_5 <X> lc_trk_g1_5
+(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(15 7) routing lft_op_4 <X> lc_trk_g1_4
+(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(15 7) routing top_op_4 <X> lc_trk_g1_4
+(15 8) routing rgt_op_1 <X> lc_trk_g2_1
+(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(15 8) routing tnl_op_1 <X> lc_trk_g2_1
+(15 8) routing tnr_op_1 <X> lc_trk_g2_1
+(15 9) routing rgt_op_0 <X> lc_trk_g2_0
+(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(15 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 9) routing tnr_op_0 <X> lc_trk_g2_0
+(16 0) routing sp12_h_l_6 <X> lc_trk_g0_1
+(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5
+(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5
+(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4
+(16 11) routing sp12_v_t_19 <X> lc_trk_g2_4
+(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(16 12) routing sp12_v_b_17 <X> lc_trk_g3_1
+(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5
+(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5
+(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4
+(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4
+(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5
+(16 2) routing sp12_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(16 4) routing sp12_h_l_6 <X> lc_trk_g1_1
+(16 4) routing sp12_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5
+(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(16 8) routing sp12_v_b_17 <X> lc_trk_g2_1
+(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0
+(18 0) routing bnr_op_1 <X> lc_trk_g0_1
+(18 0) routing lft_op_1 <X> lc_trk_g0_1
+(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 1) routing bnr_op_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1
+(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 10) routing bnl_op_5 <X> lc_trk_g2_5
+(18 10) routing rgt_op_5 <X> lc_trk_g2_5
+(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 11) routing bnl_op_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5
+(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 11) routing tnl_op_5 <X> lc_trk_g2_5
+(18 12) routing bnl_op_1 <X> lc_trk_g3_1
+(18 12) routing rgt_op_1 <X> lc_trk_g3_1
+(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 13) routing bnl_op_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_17 <X> lc_trk_g3_1
+(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1
+(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1
+(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 13) routing tnl_op_1 <X> lc_trk_g3_1
+(18 14) routing bnl_op_5 <X> lc_trk_g3_5
+(18 14) routing rgt_op_5 <X> lc_trk_g3_5
+(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 15) routing bnl_op_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5
+(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 15) routing tnl_op_5 <X> lc_trk_g3_5
+(18 2) routing bnr_op_5 <X> lc_trk_g0_5
+(18 2) routing lft_op_5 <X> lc_trk_g0_5
+(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(18 3) routing bnr_op_5 <X> lc_trk_g0_5
+(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5
+(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_h_l_8 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5
+(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 4) routing bnr_op_1 <X> lc_trk_g1_1
+(18 4) routing lft_op_1 <X> lc_trk_g1_1
+(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 5) routing bnr_op_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1
+(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 6) routing bnr_op_5 <X> lc_trk_g1_5
+(18 6) routing lft_op_5 <X> lc_trk_g1_5
+(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(18 7) routing bnr_op_5 <X> lc_trk_g1_5
+(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5
+(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_h_l_8 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5
+(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 8) routing bnl_op_1 <X> lc_trk_g2_1
+(18 8) routing rgt_op_1 <X> lc_trk_g2_1
+(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 9) routing bnl_op_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_17 <X> lc_trk_g2_1
+(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1
+(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1
+(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 9) routing tnl_op_1 <X> lc_trk_g2_1
+(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13
+(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1
+(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10
+(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22
+(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13
+(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12
+(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2
+(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3
+(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2
+(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14
+(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17
+(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16
+(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19
+(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7
+(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8
+(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20
+(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5
+(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8
+(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22
+(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK
+(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK
+(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7
+(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19
+(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20
+(21 0) routing bnr_op_3 <X> lc_trk_g0_3
+(21 0) routing lft_op_3 <X> lc_trk_g0_3
+(21 0) routing sp12_h_l_0 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(21 1) routing bnr_op_3 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_0 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3
+(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 10) routing bnl_op_7 <X> lc_trk_g2_7
+(21 10) routing rgt_op_7 <X> lc_trk_g2_7
+(21 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing bnl_op_7 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 11) routing sp4_h_l_18 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7
+(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing tnl_op_7 <X> lc_trk_g2_7
+(21 12) routing bnl_op_3 <X> lc_trk_g3_3
+(21 12) routing rgt_op_3 <X> lc_trk_g3_3
+(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 13) routing bnl_op_3 <X> lc_trk_g3_3
+(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 13) routing sp12_v_t_16 <X> lc_trk_g3_3
+(21 13) routing sp4_h_l_30 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3
+(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3
+(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 13) routing tnl_op_3 <X> lc_trk_g3_3
+(21 14) routing bnl_op_7 <X> lc_trk_g3_7
+(21 14) routing rgt_op_7 <X> lc_trk_g3_7
+(21 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing bnl_op_7 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 15) routing sp4_h_l_18 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7
+(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing tnl_op_7 <X> lc_trk_g3_7
+(21 2) routing bnr_op_7 <X> lc_trk_g0_7
+(21 2) routing lft_op_7 <X> lc_trk_g0_7
+(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 3) routing bnr_op_7 <X> lc_trk_g0_7
+(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7
+(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7
+(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 4) routing bnr_op_3 <X> lc_trk_g1_3
+(21 4) routing lft_op_3 <X> lc_trk_g1_3
+(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(21 5) routing bnr_op_3 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3
+(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 6) routing bnr_op_7 <X> lc_trk_g1_7
+(21 6) routing lft_op_7 <X> lc_trk_g1_7
+(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 7) routing bnr_op_7 <X> lc_trk_g1_7
+(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7
+(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7
+(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 8) routing bnl_op_3 <X> lc_trk_g2_3
+(21 8) routing rgt_op_3 <X> lc_trk_g2_3
+(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 9) routing bnl_op_3 <X> lc_trk_g2_3
+(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 9) routing sp12_v_t_16 <X> lc_trk_g2_3
+(21 9) routing sp4_h_l_30 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3
+(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3
+(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 9) routing tnl_op_3 <X> lc_trk_g2_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2
+(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3
+(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2
+(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7
+(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_18 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6
+(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3
+(23 12) routing sp12_v_t_16 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2
+(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2
+(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7
+(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_18 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6
+(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7
+(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6
+(23 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6
+(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3
+(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(23 5) routing sp12_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2
+(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7
+(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6
+(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6
+(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3
+(23 8) routing sp12_v_t_16 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2
+(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2
+(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 0) routing lft_op_3 <X> lc_trk_g0_3
+(24 0) routing sp12_h_l_0 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(24 1) routing lft_op_2 <X> lc_trk_g0_2
+(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(24 1) routing top_op_2 <X> lc_trk_g0_2
+(24 10) routing rgt_op_7 <X> lc_trk_g2_7
+(24 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_18 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(24 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(24 10) routing tnl_op_7 <X> lc_trk_g2_7
+(24 10) routing tnr_op_7 <X> lc_trk_g2_7
+(24 11) routing rgt_op_6 <X> lc_trk_g2_6
+(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(24 11) routing tnl_op_6 <X> lc_trk_g2_6
+(24 11) routing tnr_op_6 <X> lc_trk_g2_6
+(24 12) routing rgt_op_3 <X> lc_trk_g3_3
+(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(24 12) routing tnl_op_3 <X> lc_trk_g3_3
+(24 12) routing tnr_op_3 <X> lc_trk_g3_3
+(24 13) routing rgt_op_2 <X> lc_trk_g3_2
+(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2
+(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(24 13) routing tnl_op_2 <X> lc_trk_g3_2
+(24 13) routing tnr_op_2 <X> lc_trk_g3_2
+(24 14) routing rgt_op_7 <X> lc_trk_g3_7
+(24 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_18 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(24 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(24 14) routing tnl_op_7 <X> lc_trk_g3_7
+(24 14) routing tnr_op_7 <X> lc_trk_g3_7
+(24 15) routing rgt_op_6 <X> lc_trk_g3_6
+(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(24 15) routing tnl_op_6 <X> lc_trk_g3_6
+(24 15) routing tnr_op_6 <X> lc_trk_g3_6
+(24 2) routing lft_op_7 <X> lc_trk_g0_7
+(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7
+(24 3) routing lft_op_6 <X> lc_trk_g0_6
+(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(24 3) routing top_op_6 <X> lc_trk_g0_6
+(24 4) routing lft_op_3 <X> lc_trk_g1_3
+(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(24 5) routing lft_op_2 <X> lc_trk_g1_2
+(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(24 5) routing top_op_2 <X> lc_trk_g1_2
+(24 6) routing lft_op_7 <X> lc_trk_g1_7
+(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7
+(24 7) routing lft_op_6 <X> lc_trk_g1_6
+(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(24 7) routing top_op_6 <X> lc_trk_g1_6
+(24 8) routing rgt_op_3 <X> lc_trk_g2_3
+(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(24 8) routing tnl_op_3 <X> lc_trk_g2_3
+(24 8) routing tnr_op_3 <X> lc_trk_g2_3
+(24 9) routing rgt_op_2 <X> lc_trk_g2_2
+(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2
+(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 9) routing tnl_op_2 <X> lc_trk_g2_2
+(24 9) routing tnr_op_2 <X> lc_trk_g2_2
+(25 0) routing bnr_op_2 <X> lc_trk_g0_2
+(25 0) routing lft_op_2 <X> lc_trk_g0_2
+(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2
+(25 1) routing bnr_op_2 <X> lc_trk_g0_2
+(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2
+(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2
+(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 1) routing top_op_2 <X> lc_trk_g0_2
+(25 10) routing bnl_op_6 <X> lc_trk_g2_6
+(25 10) routing rgt_op_6 <X> lc_trk_g2_6
+(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 11) routing bnl_op_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6
+(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 11) routing tnl_op_6 <X> lc_trk_g2_6
+(25 12) routing bnl_op_2 <X> lc_trk_g3_2
+(25 12) routing rgt_op_2 <X> lc_trk_g3_2
+(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2
+(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 13) routing bnl_op_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2
+(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2
+(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 13) routing tnl_op_2 <X> lc_trk_g3_2
+(25 14) routing bnl_op_6 <X> lc_trk_g3_6
+(25 14) routing rgt_op_6 <X> lc_trk_g3_6
+(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 15) routing bnl_op_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6
+(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 15) routing tnl_op_6 <X> lc_trk_g3_6
+(25 2) routing bnr_op_6 <X> lc_trk_g0_6
+(25 2) routing lft_op_6 <X> lc_trk_g0_6
+(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6
+(25 2) routing sp4_h_r_22 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6
+(25 3) routing bnr_op_6 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6
+(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 3) routing top_op_6 <X> lc_trk_g0_6
+(25 4) routing bnr_op_2 <X> lc_trk_g1_2
+(25 4) routing lft_op_2 <X> lc_trk_g1_2
+(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2
+(25 5) routing bnr_op_2 <X> lc_trk_g1_2
+(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2
+(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2
+(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 5) routing top_op_2 <X> lc_trk_g1_2
+(25 6) routing bnr_op_6 <X> lc_trk_g1_6
+(25 6) routing lft_op_6 <X> lc_trk_g1_6
+(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6
+(25 6) routing sp4_h_r_22 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6
+(25 7) routing bnr_op_6 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6
+(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 7) routing top_op_6 <X> lc_trk_g1_6
+(25 8) routing bnl_op_2 <X> lc_trk_g2_2
+(25 8) routing rgt_op_2 <X> lc_trk_g2_2
+(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2
+(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 9) routing bnl_op_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2
+(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2
+(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 9) routing tnl_op_2 <X> lc_trk_g2_2
+(26 0) routing lc_trk_g0_4 <X> input0_0
+(26 0) routing lc_trk_g0_6 <X> input0_0
+(26 0) routing lc_trk_g1_5 <X> input0_0
+(26 0) routing lc_trk_g1_7 <X> input0_0
+(26 0) routing lc_trk_g2_4 <X> input0_0
+(26 0) routing lc_trk_g2_6 <X> input0_0
+(26 0) routing lc_trk_g3_5 <X> input0_0
+(26 0) routing lc_trk_g3_7 <X> input0_0
+(26 1) routing lc_trk_g0_2 <X> input0_0
+(26 1) routing lc_trk_g0_6 <X> input0_0
+(26 1) routing lc_trk_g1_3 <X> input0_0
+(26 1) routing lc_trk_g1_7 <X> input0_0
+(26 1) routing lc_trk_g2_2 <X> input0_0
+(26 1) routing lc_trk_g2_6 <X> input0_0
+(26 1) routing lc_trk_g3_3 <X> input0_0
+(26 1) routing lc_trk_g3_7 <X> input0_0
+(26 10) routing lc_trk_g0_5 <X> input0_5
+(26 10) routing lc_trk_g0_7 <X> input0_5
+(26 10) routing lc_trk_g1_4 <X> input0_5
+(26 10) routing lc_trk_g1_6 <X> input0_5
+(26 10) routing lc_trk_g2_5 <X> input0_5
+(26 10) routing lc_trk_g2_7 <X> input0_5
+(26 10) routing lc_trk_g3_4 <X> input0_5
+(26 10) routing lc_trk_g3_6 <X> input0_5
+(26 11) routing lc_trk_g0_3 <X> input0_5
+(26 11) routing lc_trk_g0_7 <X> input0_5
+(26 11) routing lc_trk_g1_2 <X> input0_5
+(26 11) routing lc_trk_g1_6 <X> input0_5
+(26 11) routing lc_trk_g2_3 <X> input0_5
+(26 11) routing lc_trk_g2_7 <X> input0_5
+(26 11) routing lc_trk_g3_2 <X> input0_5
+(26 11) routing lc_trk_g3_6 <X> input0_5
+(26 12) routing lc_trk_g0_4 <X> input0_6
+(26 12) routing lc_trk_g0_6 <X> input0_6
+(26 12) routing lc_trk_g1_5 <X> input0_6
+(26 12) routing lc_trk_g1_7 <X> input0_6
+(26 12) routing lc_trk_g2_4 <X> input0_6
+(26 12) routing lc_trk_g2_6 <X> input0_6
+(26 12) routing lc_trk_g3_5 <X> input0_6
+(26 12) routing lc_trk_g3_7 <X> input0_6
+(26 13) routing lc_trk_g0_2 <X> input0_6
+(26 13) routing lc_trk_g0_6 <X> input0_6
+(26 13) routing lc_trk_g1_3 <X> input0_6
+(26 13) routing lc_trk_g1_7 <X> input0_6
+(26 13) routing lc_trk_g2_2 <X> input0_6
+(26 13) routing lc_trk_g2_6 <X> input0_6
+(26 13) routing lc_trk_g3_3 <X> input0_6
+(26 13) routing lc_trk_g3_7 <X> input0_6
+(26 14) routing lc_trk_g0_5 <X> input0_7
+(26 14) routing lc_trk_g0_7 <X> input0_7
+(26 14) routing lc_trk_g1_4 <X> input0_7
+(26 14) routing lc_trk_g1_6 <X> input0_7
+(26 14) routing lc_trk_g2_5 <X> input0_7
+(26 14) routing lc_trk_g2_7 <X> input0_7
+(26 14) routing lc_trk_g3_4 <X> input0_7
+(26 14) routing lc_trk_g3_6 <X> input0_7
+(26 15) routing lc_trk_g0_3 <X> input0_7
+(26 15) routing lc_trk_g0_7 <X> input0_7
+(26 15) routing lc_trk_g1_2 <X> input0_7
+(26 15) routing lc_trk_g1_6 <X> input0_7
+(26 15) routing lc_trk_g2_3 <X> input0_7
+(26 15) routing lc_trk_g2_7 <X> input0_7
+(26 15) routing lc_trk_g3_2 <X> input0_7
+(26 15) routing lc_trk_g3_6 <X> input0_7
+(26 2) routing lc_trk_g0_5 <X> input0_1
+(26 2) routing lc_trk_g0_7 <X> input0_1
+(26 2) routing lc_trk_g1_4 <X> input0_1
+(26 2) routing lc_trk_g1_6 <X> input0_1
+(26 2) routing lc_trk_g2_5 <X> input0_1
+(26 2) routing lc_trk_g2_7 <X> input0_1
+(26 2) routing lc_trk_g3_4 <X> input0_1
+(26 2) routing lc_trk_g3_6 <X> input0_1
+(26 3) routing lc_trk_g0_3 <X> input0_1
+(26 3) routing lc_trk_g0_7 <X> input0_1
+(26 3) routing lc_trk_g1_2 <X> input0_1
+(26 3) routing lc_trk_g1_6 <X> input0_1
+(26 3) routing lc_trk_g2_3 <X> input0_1
+(26 3) routing lc_trk_g2_7 <X> input0_1
+(26 3) routing lc_trk_g3_2 <X> input0_1
+(26 3) routing lc_trk_g3_6 <X> input0_1
+(26 4) routing lc_trk_g0_4 <X> input0_2
+(26 4) routing lc_trk_g0_6 <X> input0_2
+(26 4) routing lc_trk_g1_5 <X> input0_2
+(26 4) routing lc_trk_g1_7 <X> input0_2
+(26 4) routing lc_trk_g2_4 <X> input0_2
+(26 4) routing lc_trk_g2_6 <X> input0_2
+(26 4) routing lc_trk_g3_5 <X> input0_2
+(26 4) routing lc_trk_g3_7 <X> input0_2
+(26 5) routing lc_trk_g0_2 <X> input0_2
+(26 5) routing lc_trk_g0_6 <X> input0_2
+(26 5) routing lc_trk_g1_3 <X> input0_2
+(26 5) routing lc_trk_g1_7 <X> input0_2
+(26 5) routing lc_trk_g2_2 <X> input0_2
+(26 5) routing lc_trk_g2_6 <X> input0_2
+(26 5) routing lc_trk_g3_3 <X> input0_2
+(26 5) routing lc_trk_g3_7 <X> input0_2
+(26 6) routing lc_trk_g0_5 <X> input0_3
+(26 6) routing lc_trk_g0_7 <X> input0_3
+(26 6) routing lc_trk_g1_4 <X> input0_3
+(26 6) routing lc_trk_g1_6 <X> input0_3
+(26 6) routing lc_trk_g2_5 <X> input0_3
+(26 6) routing lc_trk_g2_7 <X> input0_3
+(26 6) routing lc_trk_g3_4 <X> input0_3
+(26 6) routing lc_trk_g3_6 <X> input0_3
+(26 7) routing lc_trk_g0_3 <X> input0_3
+(26 7) routing lc_trk_g0_7 <X> input0_3
+(26 7) routing lc_trk_g1_2 <X> input0_3
+(26 7) routing lc_trk_g1_6 <X> input0_3
+(26 7) routing lc_trk_g2_3 <X> input0_3
+(26 7) routing lc_trk_g2_7 <X> input0_3
+(26 7) routing lc_trk_g3_2 <X> input0_3
+(26 7) routing lc_trk_g3_6 <X> input0_3
+(26 8) routing lc_trk_g0_4 <X> input0_4
+(26 8) routing lc_trk_g0_6 <X> input0_4
+(26 8) routing lc_trk_g1_5 <X> input0_4
+(26 8) routing lc_trk_g1_7 <X> input0_4
+(26 8) routing lc_trk_g2_4 <X> input0_4
+(26 8) routing lc_trk_g2_6 <X> input0_4
+(26 8) routing lc_trk_g3_5 <X> input0_4
+(26 8) routing lc_trk_g3_7 <X> input0_4
+(26 9) routing lc_trk_g0_2 <X> input0_4
+(26 9) routing lc_trk_g0_6 <X> input0_4
+(26 9) routing lc_trk_g1_3 <X> input0_4
+(26 9) routing lc_trk_g1_7 <X> input0_4
+(26 9) routing lc_trk_g2_2 <X> input0_4
+(26 9) routing lc_trk_g2_6 <X> input0_4
+(26 9) routing lc_trk_g3_3 <X> input0_4
+(26 9) routing lc_trk_g3_7 <X> input0_4
+(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_8
+(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_8
+(27 1) routing lc_trk_g1_1 <X> input0_0
+(27 1) routing lc_trk_g1_3 <X> input0_0
+(27 1) routing lc_trk_g1_5 <X> input0_0
+(27 1) routing lc_trk_g1_7 <X> input0_0
+(27 1) routing lc_trk_g3_1 <X> input0_0
+(27 1) routing lc_trk_g3_3 <X> input0_0
+(27 1) routing lc_trk_g3_5 <X> input0_0
+(27 1) routing lc_trk_g3_7 <X> input0_0
+(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_13
+(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_13
+(27 11) routing lc_trk_g1_0 <X> input0_5
+(27 11) routing lc_trk_g1_2 <X> input0_5
+(27 11) routing lc_trk_g1_4 <X> input0_5
+(27 11) routing lc_trk_g1_6 <X> input0_5
+(27 11) routing lc_trk_g3_0 <X> input0_5
+(27 11) routing lc_trk_g3_2 <X> input0_5
+(27 11) routing lc_trk_g3_4 <X> input0_5
+(27 11) routing lc_trk_g3_6 <X> input0_5
+(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_14
+(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_14
+(27 13) routing lc_trk_g1_1 <X> input0_6
+(27 13) routing lc_trk_g1_3 <X> input0_6
+(27 13) routing lc_trk_g1_5 <X> input0_6
+(27 13) routing lc_trk_g1_7 <X> input0_6
+(27 13) routing lc_trk_g3_1 <X> input0_6
+(27 13) routing lc_trk_g3_3 <X> input0_6
+(27 13) routing lc_trk_g3_5 <X> input0_6
+(27 13) routing lc_trk_g3_7 <X> input0_6
+(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_15
+(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_15
+(27 15) routing lc_trk_g1_0 <X> input0_7
+(27 15) routing lc_trk_g1_2 <X> input0_7
+(27 15) routing lc_trk_g1_4 <X> input0_7
+(27 15) routing lc_trk_g1_6 <X> input0_7
+(27 15) routing lc_trk_g3_0 <X> input0_7
+(27 15) routing lc_trk_g3_2 <X> input0_7
+(27 15) routing lc_trk_g3_4 <X> input0_7
+(27 15) routing lc_trk_g3_6 <X> input0_7
+(27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_9
+(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_9
+(27 3) routing lc_trk_g1_0 <X> input0_1
+(27 3) routing lc_trk_g1_2 <X> input0_1
+(27 3) routing lc_trk_g1_4 <X> input0_1
+(27 3) routing lc_trk_g1_6 <X> input0_1
+(27 3) routing lc_trk_g3_0 <X> input0_1
+(27 3) routing lc_trk_g3_2 <X> input0_1
+(27 3) routing lc_trk_g3_4 <X> input0_1
+(27 3) routing lc_trk_g3_6 <X> input0_1
+(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_10
+(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_10
+(27 5) routing lc_trk_g1_1 <X> input0_2
+(27 5) routing lc_trk_g1_3 <X> input0_2
+(27 5) routing lc_trk_g1_5 <X> input0_2
+(27 5) routing lc_trk_g1_7 <X> input0_2
+(27 5) routing lc_trk_g3_1 <X> input0_2
+(27 5) routing lc_trk_g3_3 <X> input0_2
+(27 5) routing lc_trk_g3_5 <X> input0_2
+(27 5) routing lc_trk_g3_7 <X> input0_2
+(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_11
+(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_11
+(27 7) routing lc_trk_g1_0 <X> input0_3
+(27 7) routing lc_trk_g1_2 <X> input0_3
+(27 7) routing lc_trk_g1_4 <X> input0_3
+(27 7) routing lc_trk_g1_6 <X> input0_3
+(27 7) routing lc_trk_g3_0 <X> input0_3
+(27 7) routing lc_trk_g3_2 <X> input0_3
+(27 7) routing lc_trk_g3_4 <X> input0_3
+(27 7) routing lc_trk_g3_6 <X> input0_3
+(27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_12
+(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_12
+(27 9) routing lc_trk_g1_1 <X> input0_4
+(27 9) routing lc_trk_g1_3 <X> input0_4
+(27 9) routing lc_trk_g1_5 <X> input0_4
+(27 9) routing lc_trk_g1_7 <X> input0_4
+(27 9) routing lc_trk_g3_1 <X> input0_4
+(27 9) routing lc_trk_g3_3 <X> input0_4
+(27 9) routing lc_trk_g3_5 <X> input0_4
+(27 9) routing lc_trk_g3_7 <X> input0_4
+(28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_8
+(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_8
+(28 1) routing lc_trk_g2_0 <X> input0_0
+(28 1) routing lc_trk_g2_2 <X> input0_0
+(28 1) routing lc_trk_g2_4 <X> input0_0
+(28 1) routing lc_trk_g2_6 <X> input0_0
+(28 1) routing lc_trk_g3_1 <X> input0_0
+(28 1) routing lc_trk_g3_3 <X> input0_0
+(28 1) routing lc_trk_g3_5 <X> input0_0
+(28 1) routing lc_trk_g3_7 <X> input0_0
+(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_13
+(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_13
+(28 11) routing lc_trk_g2_1 <X> input0_5
+(28 11) routing lc_trk_g2_3 <X> input0_5
+(28 11) routing lc_trk_g2_5 <X> input0_5
+(28 11) routing lc_trk_g2_7 <X> input0_5
+(28 11) routing lc_trk_g3_0 <X> input0_5
+(28 11) routing lc_trk_g3_2 <X> input0_5
+(28 11) routing lc_trk_g3_4 <X> input0_5
+(28 11) routing lc_trk_g3_6 <X> input0_5
+(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_14
+(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_14
+(28 13) routing lc_trk_g2_0 <X> input0_6
+(28 13) routing lc_trk_g2_2 <X> input0_6
+(28 13) routing lc_trk_g2_4 <X> input0_6
+(28 13) routing lc_trk_g2_6 <X> input0_6
+(28 13) routing lc_trk_g3_1 <X> input0_6
+(28 13) routing lc_trk_g3_3 <X> input0_6
+(28 13) routing lc_trk_g3_5 <X> input0_6
+(28 13) routing lc_trk_g3_7 <X> input0_6
+(28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_15
+(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_15
+(28 15) routing lc_trk_g2_1 <X> input0_7
+(28 15) routing lc_trk_g2_3 <X> input0_7
+(28 15) routing lc_trk_g2_5 <X> input0_7
+(28 15) routing lc_trk_g2_7 <X> input0_7
+(28 15) routing lc_trk_g3_0 <X> input0_7
+(28 15) routing lc_trk_g3_2 <X> input0_7
+(28 15) routing lc_trk_g3_4 <X> input0_7
+(28 15) routing lc_trk_g3_6 <X> input0_7
+(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_9
+(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_9
+(28 3) routing lc_trk_g2_1 <X> input0_1
+(28 3) routing lc_trk_g2_3 <X> input0_1
+(28 3) routing lc_trk_g2_5 <X> input0_1
+(28 3) routing lc_trk_g2_7 <X> input0_1
+(28 3) routing lc_trk_g3_0 <X> input0_1
+(28 3) routing lc_trk_g3_2 <X> input0_1
+(28 3) routing lc_trk_g3_4 <X> input0_1
+(28 3) routing lc_trk_g3_6 <X> input0_1
+(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_10
+(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_10
+(28 5) routing lc_trk_g2_0 <X> input0_2
+(28 5) routing lc_trk_g2_2 <X> input0_2
+(28 5) routing lc_trk_g2_4 <X> input0_2
+(28 5) routing lc_trk_g2_6 <X> input0_2
+(28 5) routing lc_trk_g3_1 <X> input0_2
+(28 5) routing lc_trk_g3_3 <X> input0_2
+(28 5) routing lc_trk_g3_5 <X> input0_2
+(28 5) routing lc_trk_g3_7 <X> input0_2
+(28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_11
+(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_11
+(28 7) routing lc_trk_g2_1 <X> input0_3
+(28 7) routing lc_trk_g2_3 <X> input0_3
+(28 7) routing lc_trk_g2_5 <X> input0_3
+(28 7) routing lc_trk_g2_7 <X> input0_3
+(28 7) routing lc_trk_g3_0 <X> input0_3
+(28 7) routing lc_trk_g3_2 <X> input0_3
+(28 7) routing lc_trk_g3_4 <X> input0_3
+(28 7) routing lc_trk_g3_6 <X> input0_3
+(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_12
+(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_12
+(28 9) routing lc_trk_g2_0 <X> input0_4
+(28 9) routing lc_trk_g2_2 <X> input0_4
+(28 9) routing lc_trk_g2_4 <X> input0_4
+(28 9) routing lc_trk_g2_6 <X> input0_4
+(28 9) routing lc_trk_g3_1 <X> input0_4
+(28 9) routing lc_trk_g3_3 <X> input0_4
+(28 9) routing lc_trk_g3_5 <X> input0_4
+(28 9) routing lc_trk_g3_7 <X> input0_4
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_8
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_8
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_13
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_13
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_14
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_14
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_15
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_15
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_9
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_9
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_10
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_10
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_11
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_11
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_12
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_12
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4
+(3 0) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 0) routing sp12_v_t_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_l_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 10) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 10) routing sp12_v_t_22 <X> sp12_h_l_22
+(3 11) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 11) routing sp12_v_b_1 <X> sp12_h_l_22
+(3 12) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 12) routing sp12_v_t_22 <X> sp12_h_r_1
+(3 13) routing sp12_h_l_22 <X> sp12_h_r_1
+(3 13) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 14) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 14) routing sp12_v_b_1 <X> sp12_v_t_22
+(3 15) routing sp12_h_l_22 <X> sp12_v_t_22
+(3 15) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 2) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 2) routing sp12_v_t_23 <X> sp12_h_l_23
+(3 3) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 3) routing sp12_v_b_0 <X> sp12_h_l_23
+(3 4) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 4) routing sp12_v_t_23 <X> sp12_h_r_0
+(3 5) routing sp12_h_l_23 <X> sp12_h_r_0
+(3 5) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 6) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 6) routing sp12_v_b_0 <X> sp12_v_t_23
+(3 7) routing sp12_h_l_23 <X> sp12_v_t_23
+(3 7) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 8) routing sp12_h_r_1 <X> sp12_v_b_1
+(3 8) routing sp12_v_t_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_l_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_r_1 <X> sp12_v_b_1
+(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_8
+(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_8
+(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_8
+(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_13
+(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_13
+(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_13
+(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_14
+(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_14
+(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_14
+(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_15
+(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_15
+(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_15
+(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_9
+(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_9
+(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_9
+(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_10
+(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_10
+(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_10
+(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_11
+(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_11
+(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_11
+(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_12
+(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_12
+(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_12
+(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_8
+(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_8
+(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_8
+(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_13
+(31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_13
+(31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_13
+(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_14
+(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_14
+(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_14
+(31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_15
+(31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_15
+(31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_15
+(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_9
+(31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_9
+(31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_9
+(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_10
+(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_10
+(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_10
+(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_11
+(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_11
+(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_11
+(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_12
+(31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_12
+(31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_12
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_8
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_8
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_0 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_2 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_4 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_6 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_1 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_3 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_5 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_7 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_0 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_2 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_4 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_6 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_1 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_3 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_5 input2_0
+(32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_7 input2_0
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_13
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_13
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_14
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_14
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_15
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_15
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_9
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_9
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_1 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_3 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_5 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_7 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_0 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_2 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_4 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_6 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_1 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_3 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_5 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_7 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_0 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_2 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_4 input2_1
+(32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_6 input2_1
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_10
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_10
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_0 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_2 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_4 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_6 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_1 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_3 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_5 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_7 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_0 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_2 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_4 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_6 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_1 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_3 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_5 input2_2
+(32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_7 input2_2
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_11
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_11
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_12
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_12
+(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_8
+(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_8
+(33 1) routing lc_trk_g2_0 <X> input2_0
+(33 1) routing lc_trk_g2_2 <X> input2_0
+(33 1) routing lc_trk_g2_4 <X> input2_0
+(33 1) routing lc_trk_g2_6 <X> input2_0
+(33 1) routing lc_trk_g3_1 <X> input2_0
+(33 1) routing lc_trk_g3_3 <X> input2_0
+(33 1) routing lc_trk_g3_5 <X> input2_0
+(33 1) routing lc_trk_g3_7 <X> input2_0
+(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_13
+(33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_13
+(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_14
+(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_14
+(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_15
+(33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_15
+(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_9
+(33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_9
+(33 3) routing lc_trk_g2_1 <X> input2_1
+(33 3) routing lc_trk_g2_3 <X> input2_1
+(33 3) routing lc_trk_g2_5 <X> input2_1
+(33 3) routing lc_trk_g2_7 <X> input2_1
+(33 3) routing lc_trk_g3_0 <X> input2_1
+(33 3) routing lc_trk_g3_2 <X> input2_1
+(33 3) routing lc_trk_g3_4 <X> input2_1
+(33 3) routing lc_trk_g3_6 <X> input2_1
+(33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_10
+(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_10
+(33 5) routing lc_trk_g2_0 <X> input2_2
+(33 5) routing lc_trk_g2_2 <X> input2_2
+(33 5) routing lc_trk_g2_4 <X> input2_2
+(33 5) routing lc_trk_g2_6 <X> input2_2
+(33 5) routing lc_trk_g3_1 <X> input2_2
+(33 5) routing lc_trk_g3_3 <X> input2_2
+(33 5) routing lc_trk_g3_5 <X> input2_2
+(33 5) routing lc_trk_g3_7 <X> input2_2
+(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_11
+(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_11
+(33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_12
+(33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_12
+(34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_8
+(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_8
+(34 1) routing lc_trk_g1_1 <X> input2_0
+(34 1) routing lc_trk_g1_3 <X> input2_0
+(34 1) routing lc_trk_g1_5 <X> input2_0
+(34 1) routing lc_trk_g1_7 <X> input2_0
+(34 1) routing lc_trk_g3_1 <X> input2_0
+(34 1) routing lc_trk_g3_3 <X> input2_0
+(34 1) routing lc_trk_g3_5 <X> input2_0
+(34 1) routing lc_trk_g3_7 <X> input2_0
+(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_13
+(34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_13
+(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_14
+(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_14
+(34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_15
+(34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_15
+(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_9
+(34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_9
+(34 3) routing lc_trk_g1_0 <X> input2_1
+(34 3) routing lc_trk_g1_2 <X> input2_1
+(34 3) routing lc_trk_g1_4 <X> input2_1
+(34 3) routing lc_trk_g1_6 <X> input2_1
+(34 3) routing lc_trk_g3_0 <X> input2_1
+(34 3) routing lc_trk_g3_2 <X> input2_1
+(34 3) routing lc_trk_g3_4 <X> input2_1
+(34 3) routing lc_trk_g3_6 <X> input2_1
+(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_10
+(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_10
+(34 5) routing lc_trk_g1_1 <X> input2_2
+(34 5) routing lc_trk_g1_3 <X> input2_2
+(34 5) routing lc_trk_g1_5 <X> input2_2
+(34 5) routing lc_trk_g1_7 <X> input2_2
+(34 5) routing lc_trk_g3_1 <X> input2_2
+(34 5) routing lc_trk_g3_3 <X> input2_2
+(34 5) routing lc_trk_g3_5 <X> input2_2
+(34 5) routing lc_trk_g3_7 <X> input2_2
+(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_11
+(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_11
+(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_12
+(34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_12
+(35 0) routing lc_trk_g0_4 <X> input2_0
+(35 0) routing lc_trk_g0_6 <X> input2_0
+(35 0) routing lc_trk_g1_5 <X> input2_0
+(35 0) routing lc_trk_g1_7 <X> input2_0
+(35 0) routing lc_trk_g2_4 <X> input2_0
+(35 0) routing lc_trk_g2_6 <X> input2_0
+(35 0) routing lc_trk_g3_5 <X> input2_0
+(35 0) routing lc_trk_g3_7 <X> input2_0
+(35 1) routing lc_trk_g0_2 <X> input2_0
+(35 1) routing lc_trk_g0_6 <X> input2_0
+(35 1) routing lc_trk_g1_3 <X> input2_0
+(35 1) routing lc_trk_g1_7 <X> input2_0
+(35 1) routing lc_trk_g2_2 <X> input2_0
+(35 1) routing lc_trk_g2_6 <X> input2_0
+(35 1) routing lc_trk_g3_3 <X> input2_0
+(35 1) routing lc_trk_g3_7 <X> input2_0
+(35 2) routing lc_trk_g0_5 <X> input2_1
+(35 2) routing lc_trk_g0_7 <X> input2_1
+(35 2) routing lc_trk_g1_4 <X> input2_1
+(35 2) routing lc_trk_g1_6 <X> input2_1
+(35 2) routing lc_trk_g2_5 <X> input2_1
+(35 2) routing lc_trk_g2_7 <X> input2_1
+(35 2) routing lc_trk_g3_4 <X> input2_1
+(35 2) routing lc_trk_g3_6 <X> input2_1
+(35 3) routing lc_trk_g0_3 <X> input2_1
+(35 3) routing lc_trk_g0_7 <X> input2_1
+(35 3) routing lc_trk_g1_2 <X> input2_1
+(35 3) routing lc_trk_g1_6 <X> input2_1
+(35 3) routing lc_trk_g2_3 <X> input2_1
+(35 3) routing lc_trk_g2_7 <X> input2_1
+(35 3) routing lc_trk_g3_2 <X> input2_1
+(35 3) routing lc_trk_g3_6 <X> input2_1
+(35 4) routing lc_trk_g0_4 <X> input2_2
+(35 4) routing lc_trk_g0_6 <X> input2_2
+(35 4) routing lc_trk_g1_5 <X> input2_2
+(35 4) routing lc_trk_g1_7 <X> input2_2
+(35 4) routing lc_trk_g2_4 <X> input2_2
+(35 4) routing lc_trk_g2_6 <X> input2_2
+(35 4) routing lc_trk_g3_5 <X> input2_2
+(35 4) routing lc_trk_g3_7 <X> input2_2
+(35 5) routing lc_trk_g0_2 <X> input2_2
+(35 5) routing lc_trk_g0_6 <X> input2_2
+(35 5) routing lc_trk_g1_3 <X> input2_2
+(35 5) routing lc_trk_g1_7 <X> input2_2
+(35 5) routing lc_trk_g2_2 <X> input2_2
+(35 5) routing lc_trk_g2_6 <X> input2_2
+(35 5) routing lc_trk_g3_3 <X> input2_2
+(35 5) routing lc_trk_g3_7 <X> input2_2
+(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_8 sp4_h_l_21
+(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_8 sp4_h_r_0
+(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_13 sp4_h_r_42
+(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_13 sp4_h_r_10
+(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_14 sp4_h_r_44
+(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_14 sp4_h_r_12
+(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_15 sp4_h_r_46
+(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_15 sp4_h_l_3
+(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_9 sp4_h_r_34
+(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_9 sp4_h_r_2
+(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_10 sp4_h_r_36
+(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_10 sp4_h_r_4
+(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_11 sp4_h_l_27
+(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_11 sp4_h_r_6
+(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_12 sp4_h_l_29
+(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_12 sp4_h_r_8
+(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_8 sp12_h_r_8
+(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_8 sp4_h_l_5
+(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_13 sp12_h_r_2
+(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_13 sp4_h_l_15
+(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_14 sp12_h_l_3
+(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_14 sp4_h_l_17
+(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_15 sp12_h_l_5
+(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_15 sp4_h_r_30
+(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_9 sp12_h_r_10
+(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_9 sp4_h_l_7
+(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_10 sp12_h_r_12
+(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_10 sp4_h_r_20
+(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_11 sp12_h_l_13
+(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_11 sp4_h_r_22
+(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_12 sp12_h_r_0
+(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_12 sp4_h_l_13
+(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_8 sp4_v_t_21
+(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_8 sp4_v_b_0
+(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_13 sp4_v_b_26
+(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_13 sp12_h_r_18
+(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_14 sp4_v_b_28
+(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_14 sp12_h_r_20
+(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_15 sp4_v_b_30
+(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_15 sp12_h_l_21
+(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_9 sp4_v_t_23
+(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_9 sp4_v_b_2
+(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_10 sp4_v_t_25
+(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_10 sp4_v_b_4
+(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_11 sp4_v_b_38
+(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_11 sp4_v_b_6
+(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_12 sp4_v_t_13
+(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_12 sp12_h_r_16
+(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_8 sp12_v_b_0
+(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_8 sp4_v_b_16
+(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_13 sp4_v_t_31
+(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_13 sp4_v_b_10
+(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_14 sp4_v_t_33
+(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_14 sp4_v_t_1
+(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_15 sp4_v_b_46
+(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_15 sp4_v_b_14
+(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_9 sp12_v_b_2
+(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_9 sp4_v_t_7
+(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_10 sp12_v_t_3
+(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_10 sp4_v_b_20
+(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_11 sp12_v_b_6
+(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_11 sp4_v_b_22
+(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_12 sp4_v_b_40
+(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_12 sp4_v_b_8
+(4 0) routing sp4_h_l_37 <X> sp4_v_b_0
+(4 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_37 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(4 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(4 1) routing sp4_h_l_44 <X> sp4_h_r_0
+(4 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(4 1) routing sp4_v_t_42 <X> sp4_h_r_0
+(4 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(4 10) routing sp4_h_r_6 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_6 <X> sp4_v_t_43
+(4 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(4 11) routing sp4_h_r_3 <X> sp4_h_l_43
+(4 11) routing sp4_v_b_1 <X> sp4_h_l_43
+(4 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(4 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(4 12) routing sp4_h_l_44 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_44 <X> sp4_v_b_9
+(4 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(4 13) routing sp4_h_l_43 <X> sp4_h_r_9
+(4 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(4 13) routing sp4_v_t_41 <X> sp4_h_r_9
+(4 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(4 14) routing sp4_h_r_9 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_9 <X> sp4_v_t_44
+(4 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(4 15) routing sp4_h_r_6 <X> sp4_h_l_44
+(4 15) routing sp4_v_b_4 <X> sp4_h_l_44
+(4 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(4 2) routing sp4_h_r_0 <X> sp4_v_t_37
+(4 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_0 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(4 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(4 3) routing sp4_h_r_9 <X> sp4_h_l_37
+(4 3) routing sp4_v_b_7 <X> sp4_h_l_37
+(4 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(4 4) routing sp4_h_l_38 <X> sp4_v_b_3
+(4 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_38 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(4 5) routing sp4_h_l_37 <X> sp4_h_r_3
+(4 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(4 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(4 5) routing sp4_v_t_47 <X> sp4_h_r_3
+(4 6) routing sp4_h_r_3 <X> sp4_v_t_38
+(4 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_3 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(4 7) routing sp4_h_r_0 <X> sp4_h_l_38
+(4 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(4 7) routing sp4_v_b_10 <X> sp4_h_l_38
+(4 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(4 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(4 8) routing sp4_h_l_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(4 9) routing sp4_h_l_38 <X> sp4_h_r_6
+(4 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(4 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(4 9) routing sp4_v_t_36 <X> sp4_h_r_6
+(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_17
+(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_8 sp12_v_b_16
+(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_27
+(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_13 sp12_v_t_9
+(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_29
+(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_14 sp12_v_b_12
+(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_31
+(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_15 sp12_v_b_14
+(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_19
+(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_9 sp12_v_t_17
+(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_21
+(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_10 sp12_v_t_19
+(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_23
+(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_11 sp12_v_t_21
+(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_25
+(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_12 sp12_v_t_7
+(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_33
+(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_1
+(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_43
+(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_11
+(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_45
+(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_13
+(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_47
+(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_15
+(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_35
+(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_3
+(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_37
+(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_5
+(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_39
+(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_7
+(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_41
+(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_9
+(5 0) routing sp4_h_l_44 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_0 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_6 <X> sp4_h_r_0
+(5 0) routing sp4_v_t_37 <X> sp4_h_r_0
+(5 1) routing sp4_h_l_37 <X> sp4_v_b_0
+(5 1) routing sp4_h_l_43 <X> sp4_v_b_0
+(5 1) routing sp4_h_r_0 <X> sp4_v_b_0
+(5 1) routing sp4_v_t_44 <X> sp4_v_b_0
+(5 10) routing sp4_h_r_3 <X> sp4_h_l_43
+(5 10) routing sp4_v_b_6 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_37 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_43 <X> sp4_h_l_43
+(5 11) routing sp4_h_l_43 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_0 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_6 <X> sp4_v_t_43
+(5 11) routing sp4_v_b_3 <X> sp4_v_t_43
+(5 12) routing sp4_h_l_43 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_3 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_9 <X> sp4_h_r_9
+(5 12) routing sp4_v_t_44 <X> sp4_h_r_9
+(5 13) routing sp4_h_l_38 <X> sp4_v_b_9
+(5 13) routing sp4_h_l_44 <X> sp4_v_b_9
+(5 13) routing sp4_h_r_9 <X> sp4_v_b_9
+(5 13) routing sp4_v_t_43 <X> sp4_v_b_9
+(5 14) routing sp4_h_r_6 <X> sp4_h_l_44
+(5 14) routing sp4_v_b_9 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_38 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_44 <X> sp4_h_l_44
+(5 15) routing sp4_h_l_44 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_3 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_9 <X> sp4_v_t_44
+(5 15) routing sp4_v_b_6 <X> sp4_v_t_44
+(5 2) routing sp4_h_r_9 <X> sp4_h_l_37
+(5 2) routing sp4_v_b_0 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_37 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_43 <X> sp4_h_l_37
+(5 3) routing sp4_h_l_37 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_0 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_6 <X> sp4_v_t_37
+(5 3) routing sp4_v_b_9 <X> sp4_v_t_37
+(5 4) routing sp4_h_l_37 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_3 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_9 <X> sp4_h_r_3
+(5 4) routing sp4_v_t_38 <X> sp4_h_r_3
+(5 5) routing sp4_h_l_38 <X> sp4_v_b_3
+(5 5) routing sp4_h_l_44 <X> sp4_v_b_3
+(5 5) routing sp4_h_r_3 <X> sp4_v_b_3
+(5 5) routing sp4_v_t_37 <X> sp4_v_b_3
+(5 6) routing sp4_h_r_0 <X> sp4_h_l_38
+(5 6) routing sp4_v_b_3 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_38 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_44 <X> sp4_h_l_38
+(5 7) routing sp4_h_l_38 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_3 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_9 <X> sp4_v_t_38
+(5 7) routing sp4_v_b_0 <X> sp4_v_t_38
+(5 8) routing sp4_h_l_38 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_0 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_6 <X> sp4_h_r_6
+(5 8) routing sp4_v_t_43 <X> sp4_h_r_6
+(5 9) routing sp4_h_l_37 <X> sp4_v_b_6
+(5 9) routing sp4_h_l_43 <X> sp4_v_b_6
+(5 9) routing sp4_h_r_6 <X> sp4_v_b_6
+(5 9) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(6 0) routing sp4_h_r_7 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_44 <X> sp4_v_b_0
+(6 1) routing sp4_h_l_37 <X> sp4_h_r_0
+(6 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_0 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(6 10) routing sp4_h_l_36 <X> sp4_v_t_43
+(6 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_3 <X> sp4_v_t_43
+(6 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(6 11) routing sp4_h_r_6 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_43 <X> sp4_h_l_43
+(6 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(6 12) routing sp4_h_r_4 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_43 <X> sp4_v_b_9
+(6 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(6 13) routing sp4_h_l_44 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_9 <X> sp4_h_r_9
+(6 14) routing sp4_h_l_41 <X> sp4_v_t_44
+(6 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_6 <X> sp4_v_t_44
+(6 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(6 15) routing sp4_h_r_9 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_44 <X> sp4_h_l_44
+(6 2) routing sp4_h_l_42 <X> sp4_v_t_37
+(6 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_9 <X> sp4_v_t_37
+(6 3) routing sp4_h_r_0 <X> sp4_h_l_37
+(6 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_37 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(6 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(6 4) routing sp4_h_r_10 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_37 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(6 5) routing sp4_h_l_38 <X> sp4_h_r_3
+(6 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_3 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(6 6) routing sp4_h_l_47 <X> sp4_v_t_38
+(6 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_0 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(6 7) routing sp4_h_r_3 <X> sp4_h_l_38
+(6 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_38 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(6 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(6 8) routing sp4_h_r_1 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(6 9) routing sp4_h_l_43 <X> sp4_h_r_6
+(6 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_6 <X> sp4_h_r_6
+(7 0) Ram config bit: MEMT_bram_cbit_1
+(7 1) Ram config bit: MEMT_bram_cbit_0
+(7 2) Ram config bit: MEMT_bram_cbit_3
+(7 3) Ram config bit: MEMT_bram_cbit_2
+(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
+(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(8 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(8 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(8 1) routing sp4_h_r_1 <X> sp4_v_b_1
+(8 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(8 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(8 10) routing sp4_h_r_7 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(8 11) routing sp4_h_l_42 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(8 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(8 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(8 12) routing sp4_h_l_47 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(8 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(8 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(8 13) routing sp4_h_r_10 <X> sp4_v_b_10
+(8 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(8 14) routing sp4_h_r_10 <X> sp4_h_l_47
+(8 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(8 15) routing sp4_h_l_47 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(8 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(8 2) routing sp4_h_r_1 <X> sp4_h_l_36
+(8 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(8 3) routing sp4_h_l_36 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(8 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(8 4) routing sp4_h_l_41 <X> sp4_h_r_4
+(8 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(8 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(8 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(8 5) routing sp4_h_r_4 <X> sp4_v_b_4
+(8 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(8 6) routing sp4_h_r_4 <X> sp4_h_l_41
+(8 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(8 7) routing sp4_h_l_41 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(8 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(8 8) routing sp4_h_l_42 <X> sp4_h_r_7
+(8 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(8 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(8 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(8 9) routing sp4_h_r_7 <X> sp4_v_b_7
+(8 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(9 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(9 0) routing sp4_v_t_36 <X> sp4_h_r_1
+(9 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(9 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_36 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(9 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(9 10) routing sp4_v_b_7 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(9 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(9 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_7 <X> sp4_v_t_42
+(9 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(9 12) routing sp4_v_t_47 <X> sp4_h_r_10
+(9 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(9 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_47 <X> sp4_v_b_10
+(9 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(9 14) routing sp4_v_b_10 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(9 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(9 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_10 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(9 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(9 2) routing sp4_v_b_1 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(9 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(9 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_1 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(9 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(9 4) routing sp4_v_t_41 <X> sp4_h_r_4
+(9 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(9 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_41 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(9 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(9 6) routing sp4_v_b_4 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(9 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(9 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(9 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(9 8) routing sp4_v_t_42 <X> sp4_h_r_7
+(9 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(9 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_46 <X> sp4_v_b_7
diff --git a/icefuzz/cached_ramt_8k.txt b/icefuzz/cached_ramt_8k.txt
new file mode 100644
index 0000000..6a7c7a1
--- /dev/null
+++ b/icefuzz/cached_ramt_8k.txt
@@ -0,0 +1,3597 @@
+(0 0) Negative Clock bit
+(0 10) routing glb_netwk_2 <X> glb2local_2
+(0 10) routing glb_netwk_3 <X> glb2local_2
+(0 10) routing glb_netwk_6 <X> glb2local_2
+(0 10) routing glb_netwk_7 <X> glb2local_2
+(0 11) routing glb_netwk_1 <X> glb2local_2
+(0 11) routing glb_netwk_3 <X> glb2local_2
+(0 11) routing glb_netwk_5 <X> glb2local_2
+(0 11) routing glb_netwk_7 <X> glb2local_2
+(0 12) routing glb_netwk_2 <X> glb2local_3
+(0 12) routing glb_netwk_3 <X> glb2local_3
+(0 12) routing glb_netwk_6 <X> glb2local_3
+(0 12) routing glb_netwk_7 <X> glb2local_3
+(0 13) routing glb_netwk_1 <X> glb2local_3
+(0 13) routing glb_netwk_3 <X> glb2local_3
+(0 13) routing glb_netwk_5 <X> glb2local_3
+(0 13) routing glb_netwk_7 <X> glb2local_3
+(0 14) routing glb_netwk_4 <X> wire_bram/ram/WE
+(0 14) routing glb_netwk_6 <X> wire_bram/ram/WE
+(0 14) routing lc_trk_g2_4 <X> wire_bram/ram/WE
+(0 14) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(0 15) routing glb_netwk_2 <X> wire_bram/ram/WE
+(0 15) routing glb_netwk_6 <X> wire_bram/ram/WE
+(0 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE
+(0 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(0 2) routing glb_netwk_2 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_3 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK
+(0 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(0 2) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK
+(0 2) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_1 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_3 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_5 <X> wire_bram/ram/WCLK
+(0 3) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK
+(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(0 4) routing glb_netwk_5 <X> wire_bram/ram/WCLKE
+(0 4) routing glb_netwk_7 <X> wire_bram/ram/WCLKE
+(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE
+(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(0 5) routing glb_netwk_3 <X> wire_bram/ram/WCLKE
+(0 5) routing glb_netwk_7 <X> wire_bram/ram/WCLKE
+(0 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE
+(0 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(0 6) routing glb_netwk_2 <X> glb2local_0
+(0 6) routing glb_netwk_3 <X> glb2local_0
+(0 6) routing glb_netwk_6 <X> glb2local_0
+(0 6) routing glb_netwk_7 <X> glb2local_0
+(0 7) routing glb_netwk_1 <X> glb2local_0
+(0 7) routing glb_netwk_3 <X> glb2local_0
+(0 7) routing glb_netwk_5 <X> glb2local_0
+(0 7) routing glb_netwk_7 <X> glb2local_0
+(0 8) routing glb_netwk_2 <X> glb2local_1
+(0 8) routing glb_netwk_3 <X> glb2local_1
+(0 8) routing glb_netwk_6 <X> glb2local_1
+(0 8) routing glb_netwk_7 <X> glb2local_1
+(0 9) routing glb_netwk_1 <X> glb2local_1
+(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_5 <X> glb2local_1
+(0 9) routing glb_netwk_7 <X> glb2local_1
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2
+(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2
+(1 11) routing glb_netwk_4 <X> glb2local_2
+(1 11) routing glb_netwk_5 <X> glb2local_2
+(1 11) routing glb_netwk_6 <X> glb2local_2
+(1 11) routing glb_netwk_7 <X> glb2local_2
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3
+(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3
+(1 13) routing glb_netwk_4 <X> glb2local_3
+(1 13) routing glb_netwk_5 <X> glb2local_3
+(1 13) routing glb_netwk_6 <X> glb2local_3
+(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE
+(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE
+(1 15) routing lc_trk_g0_4 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g2_4 <X> wire_bram/ram/WE
+(1 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE
+(1 2) routing glb_netwk_4 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_5 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK
+(1 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK
+(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g0_2 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE
+(1 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0
+(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0
+(1 7) routing glb_netwk_4 <X> glb2local_0
+(1 7) routing glb_netwk_5 <X> glb2local_0
+(1 7) routing glb_netwk_6 <X> glb2local_0
+(1 7) routing glb_netwk_7 <X> glb2local_0
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
+(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_5 <X> glb2local_1
+(1 9) routing glb_netwk_6 <X> glb2local_1
+(1 9) routing glb_netwk_7 <X> glb2local_1
+(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(10 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(10 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(10 0) routing sp4_v_t_45 <X> sp4_h_r_1
+(10 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(10 1) routing sp4_h_r_8 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(10 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(10 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(10 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(10 10) routing sp4_v_b_2 <X> sp4_h_l_42
+(10 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(10 11) routing sp4_h_l_39 <X> sp4_v_t_42
+(10 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(10 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(10 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(10 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(10 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(10 12) routing sp4_v_t_40 <X> sp4_h_r_10
+(10 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(10 13) routing sp4_h_r_5 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(10 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(10 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(10 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(10 14) routing sp4_v_b_5 <X> sp4_h_l_47
+(10 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(10 15) routing sp4_h_l_40 <X> sp4_v_t_47
+(10 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(10 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(10 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(10 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(10 2) routing sp4_v_b_8 <X> sp4_h_l_36
+(10 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(10 3) routing sp4_h_l_45 <X> sp4_v_t_36
+(10 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(10 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(10 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(10 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(10 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(10 4) routing sp4_v_t_46 <X> sp4_h_r_4
+(10 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(10 5) routing sp4_h_r_11 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(10 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(10 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(10 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(10 6) routing sp4_v_b_11 <X> sp4_h_l_41
+(10 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(10 7) routing sp4_h_l_46 <X> sp4_v_t_41
+(10 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(10 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(10 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(10 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(10 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(10 8) routing sp4_v_t_39 <X> sp4_h_r_7
+(10 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(10 9) routing sp4_h_r_2 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(10 9) routing sp4_v_t_46 <X> sp4_v_b_7
+(11 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(11 0) routing sp4_h_r_9 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(11 0) routing sp4_v_t_46 <X> sp4_v_b_2
+(11 1) routing sp4_h_l_39 <X> sp4_h_r_2
+(11 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_2 <X> sp4_h_r_2
+(11 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(11 10) routing sp4_h_l_38 <X> sp4_v_t_45
+(11 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(11 10) routing sp4_v_b_5 <X> sp4_v_t_45
+(11 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(11 11) routing sp4_h_r_8 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(11 11) routing sp4_v_t_45 <X> sp4_h_l_45
+(11 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(11 12) routing sp4_h_r_6 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(11 12) routing sp4_v_t_45 <X> sp4_v_b_11
+(11 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(11 13) routing sp4_h_l_46 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_11 <X> sp4_h_r_11
+(11 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(11 14) routing sp4_h_l_43 <X> sp4_v_t_46
+(11 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(11 14) routing sp4_v_b_8 <X> sp4_v_t_46
+(11 15) routing sp4_h_r_11 <X> sp4_h_l_46
+(11 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(11 15) routing sp4_v_t_46 <X> sp4_h_l_46
+(11 2) routing sp4_h_l_44 <X> sp4_v_t_39
+(11 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_11 <X> sp4_v_t_39
+(11 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(11 3) routing sp4_h_r_2 <X> sp4_h_l_39
+(11 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_39 <X> sp4_h_l_39
+(11 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(11 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(11 4) routing sp4_h_r_0 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_39 <X> sp4_v_b_5
+(11 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(11 5) routing sp4_h_l_40 <X> sp4_h_r_5
+(11 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(11 5) routing sp4_v_b_5 <X> sp4_h_r_5
+(11 6) routing sp4_h_l_37 <X> sp4_v_t_40
+(11 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_2 <X> sp4_v_t_40
+(11 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(11 7) routing sp4_h_r_5 <X> sp4_h_l_40
+(11 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_40 <X> sp4_h_l_40
+(11 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(11 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(11 8) routing sp4_h_r_3 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(11 8) routing sp4_v_t_40 <X> sp4_v_b_8
+(11 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(11 9) routing sp4_h_l_45 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(11 9) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 0) routing sp4_h_l_46 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_2 <X> sp4_h_r_2
+(12 0) routing sp4_v_b_8 <X> sp4_h_r_2
+(12 0) routing sp4_v_t_39 <X> sp4_h_r_2
+(12 1) routing sp4_h_l_39 <X> sp4_v_b_2
+(12 1) routing sp4_h_l_45 <X> sp4_v_b_2
+(12 1) routing sp4_h_r_2 <X> sp4_v_b_2
+(12 1) routing sp4_v_t_46 <X> sp4_v_b_2
+(12 10) routing sp4_h_r_5 <X> sp4_h_l_45
+(12 10) routing sp4_v_b_8 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_39 <X> sp4_h_l_45
+(12 10) routing sp4_v_t_45 <X> sp4_h_l_45
+(12 11) routing sp4_h_l_45 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_2 <X> sp4_v_t_45
+(12 11) routing sp4_h_r_8 <X> sp4_v_t_45
+(12 11) routing sp4_v_b_5 <X> sp4_v_t_45
+(12 12) routing sp4_h_l_45 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_11 <X> sp4_h_r_11
+(12 12) routing sp4_v_b_5 <X> sp4_h_r_11
+(12 12) routing sp4_v_t_46 <X> sp4_h_r_11
+(12 13) routing sp4_h_l_40 <X> sp4_v_b_11
+(12 13) routing sp4_h_l_46 <X> sp4_v_b_11
+(12 13) routing sp4_h_r_11 <X> sp4_v_b_11
+(12 13) routing sp4_v_t_45 <X> sp4_v_b_11
+(12 14) routing sp4_h_r_8 <X> sp4_h_l_46
+(12 14) routing sp4_v_b_11 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_40 <X> sp4_h_l_46
+(12 14) routing sp4_v_t_46 <X> sp4_h_l_46
+(12 15) routing sp4_h_l_46 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_11 <X> sp4_v_t_46
+(12 15) routing sp4_h_r_5 <X> sp4_v_t_46
+(12 15) routing sp4_v_b_8 <X> sp4_v_t_46
+(12 2) routing sp4_h_r_11 <X> sp4_h_l_39
+(12 2) routing sp4_v_b_2 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_39 <X> sp4_h_l_39
+(12 2) routing sp4_v_t_45 <X> sp4_h_l_39
+(12 3) routing sp4_h_l_39 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_2 <X> sp4_v_t_39
+(12 3) routing sp4_h_r_8 <X> sp4_v_t_39
+(12 3) routing sp4_v_b_11 <X> sp4_v_t_39
+(12 4) routing sp4_h_l_39 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_11 <X> sp4_h_r_5
+(12 4) routing sp4_v_b_5 <X> sp4_h_r_5
+(12 4) routing sp4_v_t_40 <X> sp4_h_r_5
+(12 5) routing sp4_h_l_40 <X> sp4_v_b_5
+(12 5) routing sp4_h_l_46 <X> sp4_v_b_5
+(12 5) routing sp4_h_r_5 <X> sp4_v_b_5
+(12 5) routing sp4_v_t_39 <X> sp4_v_b_5
+(12 6) routing sp4_h_r_2 <X> sp4_h_l_40
+(12 6) routing sp4_v_b_5 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_40 <X> sp4_h_l_40
+(12 6) routing sp4_v_t_46 <X> sp4_h_l_40
+(12 7) routing sp4_h_l_40 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_11 <X> sp4_v_t_40
+(12 7) routing sp4_h_r_5 <X> sp4_v_t_40
+(12 7) routing sp4_v_b_2 <X> sp4_v_t_40
+(12 8) routing sp4_h_l_40 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_2 <X> sp4_h_r_8
+(12 8) routing sp4_v_b_8 <X> sp4_h_r_8
+(12 8) routing sp4_v_t_45 <X> sp4_h_r_8
+(12 9) routing sp4_h_l_39 <X> sp4_v_b_8
+(12 9) routing sp4_h_l_45 <X> sp4_v_b_8
+(12 9) routing sp4_h_r_8 <X> sp4_v_b_8
+(12 9) routing sp4_v_t_40 <X> sp4_v_b_8
+(13 0) routing sp4_h_l_39 <X> sp4_v_b_2
+(13 0) routing sp4_h_l_45 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_39 <X> sp4_v_b_2
+(13 0) routing sp4_v_t_43 <X> sp4_v_b_2
+(13 1) routing sp4_h_l_43 <X> sp4_h_r_2
+(13 1) routing sp4_h_l_46 <X> sp4_h_r_2
+(13 1) routing sp4_v_b_8 <X> sp4_h_r_2
+(13 1) routing sp4_v_t_44 <X> sp4_h_r_2
+(13 10) routing sp4_h_r_2 <X> sp4_v_t_45
+(13 10) routing sp4_h_r_8 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_0 <X> sp4_v_t_45
+(13 10) routing sp4_v_b_8 <X> sp4_v_t_45
+(13 11) routing sp4_h_r_0 <X> sp4_h_l_45
+(13 11) routing sp4_h_r_5 <X> sp4_h_l_45
+(13 11) routing sp4_v_b_3 <X> sp4_h_l_45
+(13 11) routing sp4_v_t_39 <X> sp4_h_l_45
+(13 12) routing sp4_h_l_40 <X> sp4_v_b_11
+(13 12) routing sp4_h_l_46 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_38 <X> sp4_v_b_11
+(13 12) routing sp4_v_t_46 <X> sp4_v_b_11
+(13 13) routing sp4_h_l_38 <X> sp4_h_r_11
+(13 13) routing sp4_h_l_45 <X> sp4_h_r_11
+(13 13) routing sp4_v_b_5 <X> sp4_h_r_11
+(13 13) routing sp4_v_t_43 <X> sp4_h_r_11
+(13 14) routing sp4_h_r_11 <X> sp4_v_t_46
+(13 14) routing sp4_h_r_5 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_11 <X> sp4_v_t_46
+(13 14) routing sp4_v_b_3 <X> sp4_v_t_46
+(13 15) routing sp4_h_r_3 <X> sp4_h_l_46
+(13 15) routing sp4_h_r_8 <X> sp4_h_l_46
+(13 15) routing sp4_v_b_6 <X> sp4_h_l_46
+(13 15) routing sp4_v_t_40 <X> sp4_h_l_46
+(13 2) routing sp4_h_r_2 <X> sp4_v_t_39
+(13 2) routing sp4_h_r_8 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_2 <X> sp4_v_t_39
+(13 2) routing sp4_v_b_6 <X> sp4_v_t_39
+(13 3) routing sp4_h_r_11 <X> sp4_h_l_39
+(13 3) routing sp4_h_r_6 <X> sp4_h_l_39
+(13 3) routing sp4_v_b_9 <X> sp4_h_l_39
+(13 3) routing sp4_v_t_45 <X> sp4_h_l_39
+(13 4) routing sp4_h_l_40 <X> sp4_v_b_5
+(13 4) routing sp4_h_l_46 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_40 <X> sp4_v_b_5
+(13 4) routing sp4_v_t_44 <X> sp4_v_b_5
+(13 5) routing sp4_h_l_39 <X> sp4_h_r_5
+(13 5) routing sp4_h_l_44 <X> sp4_h_r_5
+(13 5) routing sp4_v_b_11 <X> sp4_h_r_5
+(13 5) routing sp4_v_t_37 <X> sp4_h_r_5
+(13 6) routing sp4_h_r_11 <X> sp4_v_t_40
+(13 6) routing sp4_h_r_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_5 <X> sp4_v_t_40
+(13 6) routing sp4_v_b_9 <X> sp4_v_t_40
+(13 7) routing sp4_h_r_2 <X> sp4_h_l_40
+(13 7) routing sp4_h_r_9 <X> sp4_h_l_40
+(13 7) routing sp4_v_b_0 <X> sp4_h_l_40
+(13 7) routing sp4_v_t_46 <X> sp4_h_l_40
+(13 8) routing sp4_h_l_39 <X> sp4_v_b_8
+(13 8) routing sp4_h_l_45 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_37 <X> sp4_v_b_8
+(13 8) routing sp4_v_t_45 <X> sp4_v_b_8
+(13 9) routing sp4_h_l_37 <X> sp4_h_r_8
+(13 9) routing sp4_h_l_40 <X> sp4_h_r_8
+(13 9) routing sp4_v_b_2 <X> sp4_h_r_8
+(13 9) routing sp4_v_t_38 <X> sp4_h_r_8
+(14 0) routing bnr_op_0 <X> lc_trk_g0_0
+(14 0) routing lft_op_0 <X> lc_trk_g0_0
+(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0
+(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing bnr_op_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0
+(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(14 1) routing top_op_0 <X> lc_trk_g0_0
+(14 10) routing bnl_op_4 <X> lc_trk_g2_4
+(14 10) routing rgt_op_4 <X> lc_trk_g2_4
+(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4
+(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4
+(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing bnl_op_4 <X> lc_trk_g2_4
+(14 11) routing sp12_v_t_19 <X> lc_trk_g2_4
+(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4
+(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(14 11) routing tnl_op_4 <X> lc_trk_g2_4
+(14 12) routing bnl_op_0 <X> lc_trk_g3_0
+(14 12) routing rgt_op_0 <X> lc_trk_g3_0
+(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0
+(14 12) routing sp4_h_l_29 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0
+(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 13) routing bnl_op_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(14 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0
+(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(14 13) routing tnl_op_0 <X> lc_trk_g3_0
+(14 14) routing bnl_op_4 <X> lc_trk_g3_4
+(14 14) routing rgt_op_4 <X> lc_trk_g3_4
+(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4
+(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4
+(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing bnl_op_4 <X> lc_trk_g3_4
+(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4
+(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4
+(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(14 15) routing tnl_op_4 <X> lc_trk_g3_4
+(14 2) routing bnr_op_4 <X> lc_trk_g0_4
+(14 2) routing lft_op_4 <X> lc_trk_g0_4
+(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4
+(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4
+(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4
+(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 3) routing bnr_op_4 <X> lc_trk_g0_4
+(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4
+(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(14 3) routing top_op_4 <X> lc_trk_g0_4
+(14 4) routing bnr_op_0 <X> lc_trk_g1_0
+(14 4) routing lft_op_0 <X> lc_trk_g1_0
+(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0
+(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing bnr_op_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0
+(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(14 5) routing top_op_0 <X> lc_trk_g1_0
+(14 6) routing bnr_op_4 <X> lc_trk_g1_4
+(14 6) routing lft_op_4 <X> lc_trk_g1_4
+(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4
+(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4
+(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4
+(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 7) routing bnr_op_4 <X> lc_trk_g1_4
+(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4
+(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(14 7) routing top_op_4 <X> lc_trk_g1_4
+(14 8) routing bnl_op_0 <X> lc_trk_g2_0
+(14 8) routing rgt_op_0 <X> lc_trk_g2_0
+(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0
+(14 8) routing sp4_h_l_29 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0
+(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 9) routing bnl_op_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(14 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0
+(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(14 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 0) routing lft_op_1 <X> lc_trk_g0_1
+(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(15 1) routing lft_op_0 <X> lc_trk_g0_0
+(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(15 1) routing top_op_0 <X> lc_trk_g0_0
+(15 10) routing rgt_op_5 <X> lc_trk_g2_5
+(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(15 10) routing tnl_op_5 <X> lc_trk_g2_5
+(15 10) routing tnr_op_5 <X> lc_trk_g2_5
+(15 11) routing rgt_op_4 <X> lc_trk_g2_4
+(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4
+(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(15 11) routing tnl_op_4 <X> lc_trk_g2_4
+(15 11) routing tnr_op_4 <X> lc_trk_g2_4
+(15 12) routing rgt_op_1 <X> lc_trk_g3_1
+(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(15 12) routing tnl_op_1 <X> lc_trk_g3_1
+(15 12) routing tnr_op_1 <X> lc_trk_g3_1
+(15 13) routing rgt_op_0 <X> lc_trk_g3_0
+(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(15 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(15 13) routing tnl_op_0 <X> lc_trk_g3_0
+(15 13) routing tnr_op_0 <X> lc_trk_g3_0
+(15 14) routing rgt_op_5 <X> lc_trk_g3_5
+(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(15 14) routing tnl_op_5 <X> lc_trk_g3_5
+(15 14) routing tnr_op_5 <X> lc_trk_g3_5
+(15 15) routing rgt_op_4 <X> lc_trk_g3_4
+(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4
+(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(15 15) routing tnl_op_4 <X> lc_trk_g3_4
+(15 15) routing tnr_op_4 <X> lc_trk_g3_4
+(15 2) routing lft_op_5 <X> lc_trk_g0_5
+(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(15 3) routing lft_op_4 <X> lc_trk_g0_4
+(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(15 3) routing top_op_4 <X> lc_trk_g0_4
+(15 4) routing lft_op_1 <X> lc_trk_g1_1
+(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(15 5) routing lft_op_0 <X> lc_trk_g1_0
+(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(15 5) routing top_op_0 <X> lc_trk_g1_0
+(15 6) routing lft_op_5 <X> lc_trk_g1_5
+(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(15 7) routing lft_op_4 <X> lc_trk_g1_4
+(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(15 7) routing top_op_4 <X> lc_trk_g1_4
+(15 8) routing rgt_op_1 <X> lc_trk_g2_1
+(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(15 8) routing tnl_op_1 <X> lc_trk_g2_1
+(15 8) routing tnr_op_1 <X> lc_trk_g2_1
+(15 9) routing rgt_op_0 <X> lc_trk_g2_0
+(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(15 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(15 9) routing tnl_op_0 <X> lc_trk_g2_0
+(15 9) routing tnr_op_0 <X> lc_trk_g2_0
+(16 0) routing sp12_h_l_6 <X> lc_trk_g0_1
+(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1
+(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0
+(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0
+(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0
+(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0
+(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5
+(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5
+(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5
+(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4
+(16 11) routing sp12_v_t_19 <X> lc_trk_g2_4
+(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4
+(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4
+(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4
+(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4
+(16 12) routing sp12_v_b_17 <X> lc_trk_g3_1
+(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1
+(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0
+(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0
+(16 13) routing sp4_h_l_29 <X> lc_trk_g3_0
+(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0
+(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0
+(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5
+(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5
+(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5
+(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4
+(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4
+(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4
+(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4
+(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4
+(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4
+(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5
+(16 2) routing sp12_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5
+(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4
+(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4
+(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4
+(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4
+(16 4) routing sp12_h_l_6 <X> lc_trk_g1_1
+(16 4) routing sp12_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1
+(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0
+(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0
+(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0
+(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0
+(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5
+(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5
+(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4
+(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4
+(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4
+(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4
+(16 8) routing sp12_v_b_17 <X> lc_trk_g2_1
+(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1
+(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0
+(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0
+(16 9) routing sp4_h_l_29 <X> lc_trk_g2_0
+(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0
+(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1
+(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0
+(17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5
+(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4
+(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1
+(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0
+(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
+(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4
+(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5
+(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4
+(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1
+(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0
+(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5
+(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4
+(17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1
+(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0
+(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0
+(18 0) routing bnr_op_1 <X> lc_trk_g0_1
+(18 0) routing lft_op_1 <X> lc_trk_g0_1
+(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1
+(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 1) routing bnr_op_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1
+(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1
+(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1
+(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1
+(18 10) routing bnl_op_5 <X> lc_trk_g2_5
+(18 10) routing rgt_op_5 <X> lc_trk_g2_5
+(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5
+(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5
+(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 11) routing bnl_op_5 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5
+(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5
+(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5
+(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5
+(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5
+(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5
+(18 11) routing tnl_op_5 <X> lc_trk_g2_5
+(18 12) routing bnl_op_1 <X> lc_trk_g3_1
+(18 12) routing rgt_op_1 <X> lc_trk_g3_1
+(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1
+(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1
+(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 13) routing bnl_op_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1
+(18 13) routing sp12_v_b_17 <X> lc_trk_g3_1
+(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1
+(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1
+(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1
+(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1
+(18 13) routing tnl_op_1 <X> lc_trk_g3_1
+(18 14) routing bnl_op_5 <X> lc_trk_g3_5
+(18 14) routing rgt_op_5 <X> lc_trk_g3_5
+(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5
+(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5
+(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 15) routing bnl_op_5 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5
+(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5
+(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5
+(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5
+(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5
+(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5
+(18 15) routing tnl_op_5 <X> lc_trk_g3_5
+(18 2) routing bnr_op_5 <X> lc_trk_g0_5
+(18 2) routing lft_op_5 <X> lc_trk_g0_5
+(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 2) routing sp4_h_l_8 <X> lc_trk_g0_5
+(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5
+(18 3) routing bnr_op_5 <X> lc_trk_g0_5
+(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5
+(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_h_l_8 <X> lc_trk_g0_5
+(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5
+(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5
+(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5
+(18 4) routing bnr_op_1 <X> lc_trk_g1_1
+(18 4) routing lft_op_1 <X> lc_trk_g1_1
+(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1
+(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 5) routing bnr_op_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp12_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1
+(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1
+(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1
+(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1
+(18 6) routing bnr_op_5 <X> lc_trk_g1_5
+(18 6) routing lft_op_5 <X> lc_trk_g1_5
+(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 6) routing sp4_h_l_8 <X> lc_trk_g1_5
+(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5
+(18 7) routing bnr_op_5 <X> lc_trk_g1_5
+(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5
+(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_h_l_8 <X> lc_trk_g1_5
+(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5
+(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5
+(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5
+(18 8) routing bnl_op_1 <X> lc_trk_g2_1
+(18 8) routing rgt_op_1 <X> lc_trk_g2_1
+(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1
+(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1
+(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 9) routing bnl_op_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1
+(18 9) routing sp12_v_b_17 <X> lc_trk_g2_1
+(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1
+(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1
+(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1
+(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1
+(18 9) routing tnl_op_1 <X> lc_trk_g2_1
+(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13
+(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1
+(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10
+(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22
+(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13
+(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12
+(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2
+(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3
+(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2
+(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14
+(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17
+(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16
+(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19
+(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7
+(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8
+(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20
+(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5
+(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8
+(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22
+(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK
+(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK
+(2 3) routing lc_trk_g0_0 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK
+(2 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK
+(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7
+(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19
+(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20
+(21 0) routing bnr_op_3 <X> lc_trk_g0_3
+(21 0) routing lft_op_3 <X> lc_trk_g0_3
+(21 0) routing sp12_h_l_0 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(21 1) routing bnr_op_3 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_0 <X> lc_trk_g0_3
+(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3
+(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3
+(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3
+(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3
+(21 10) routing bnl_op_7 <X> lc_trk_g2_7
+(21 10) routing rgt_op_7 <X> lc_trk_g2_7
+(21 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing bnl_op_7 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7
+(21 11) routing sp12_v_b_7 <X> lc_trk_g2_7
+(21 11) routing sp4_h_l_18 <X> lc_trk_g2_7
+(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7
+(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7
+(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7
+(21 11) routing tnl_op_7 <X> lc_trk_g2_7
+(21 12) routing bnl_op_3 <X> lc_trk_g3_3
+(21 12) routing rgt_op_3 <X> lc_trk_g3_3
+(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 13) routing bnl_op_3 <X> lc_trk_g3_3
+(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3
+(21 13) routing sp12_v_t_16 <X> lc_trk_g3_3
+(21 13) routing sp4_h_l_30 <X> lc_trk_g3_3
+(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3
+(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3
+(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3
+(21 13) routing tnl_op_3 <X> lc_trk_g3_3
+(21 14) routing bnl_op_7 <X> lc_trk_g3_7
+(21 14) routing rgt_op_7 <X> lc_trk_g3_7
+(21 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing bnl_op_7 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7
+(21 15) routing sp12_v_b_7 <X> lc_trk_g3_7
+(21 15) routing sp4_h_l_18 <X> lc_trk_g3_7
+(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7
+(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7
+(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7
+(21 15) routing tnl_op_7 <X> lc_trk_g3_7
+(21 2) routing bnr_op_7 <X> lc_trk_g0_7
+(21 2) routing lft_op_7 <X> lc_trk_g0_7
+(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 3) routing bnr_op_7 <X> lc_trk_g0_7
+(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7
+(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7
+(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7
+(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7
+(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7
+(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7
+(21 4) routing bnr_op_3 <X> lc_trk_g1_3
+(21 4) routing lft_op_3 <X> lc_trk_g1_3
+(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(21 5) routing bnr_op_3 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3
+(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3
+(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3
+(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3
+(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3
+(21 6) routing bnr_op_7 <X> lc_trk_g1_7
+(21 6) routing lft_op_7 <X> lc_trk_g1_7
+(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 7) routing bnr_op_7 <X> lc_trk_g1_7
+(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7
+(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7
+(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7
+(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7
+(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7
+(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7
+(21 8) routing bnl_op_3 <X> lc_trk_g2_3
+(21 8) routing rgt_op_3 <X> lc_trk_g2_3
+(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 9) routing bnl_op_3 <X> lc_trk_g2_3
+(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3
+(21 9) routing sp12_v_t_16 <X> lc_trk_g2_3
+(21 9) routing sp4_h_l_30 <X> lc_trk_g2_3
+(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3
+(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3
+(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3
+(21 9) routing tnl_op_3 <X> lc_trk_g2_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3
+(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2
+(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7
+(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6
+(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3
+(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2
+(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7
+(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6
+(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7
+(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6
+(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3
+(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2
+(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7
+(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6
+(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3
+(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2
+(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2
+(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3
+(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3
+(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2
+(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2
+(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7
+(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_18 <X> lc_trk_g2_7
+(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7
+(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7
+(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6
+(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3
+(23 12) routing sp12_v_t_16 <X> lc_trk_g3_3
+(23 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_14 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3
+(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2
+(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2
+(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7
+(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_18 <X> lc_trk_g3_7
+(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7
+(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7
+(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6
+(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7
+(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(23 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7
+(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7
+(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6
+(23 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6
+(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3
+(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3
+(23 5) routing sp12_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2
+(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2
+(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7
+(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7
+(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7
+(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6
+(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6
+(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3
+(23 8) routing sp12_v_t_16 <X> lc_trk_g2_3
+(23 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_14 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3
+(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2
+(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2
+(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 0) routing lft_op_3 <X> lc_trk_g0_3
+(24 0) routing sp12_h_l_0 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3
+(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3
+(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3
+(24 1) routing lft_op_2 <X> lc_trk_g0_2
+(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2
+(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2
+(24 1) routing top_op_2 <X> lc_trk_g0_2
+(24 10) routing rgt_op_7 <X> lc_trk_g2_7
+(24 10) routing sp12_v_b_7 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_18 <X> lc_trk_g2_7
+(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7
+(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7
+(24 10) routing sp4_v_b_47 <X> lc_trk_g2_7
+(24 10) routing tnl_op_7 <X> lc_trk_g2_7
+(24 10) routing tnr_op_7 <X> lc_trk_g2_7
+(24 11) routing rgt_op_6 <X> lc_trk_g2_6
+(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6
+(24 11) routing tnl_op_6 <X> lc_trk_g2_6
+(24 11) routing tnr_op_6 <X> lc_trk_g2_6
+(24 12) routing rgt_op_3 <X> lc_trk_g3_3
+(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3
+(24 12) routing sp4_h_l_30 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3
+(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3
+(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3
+(24 12) routing tnl_op_3 <X> lc_trk_g3_3
+(24 12) routing tnr_op_3 <X> lc_trk_g3_3
+(24 13) routing rgt_op_2 <X> lc_trk_g3_2
+(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2
+(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2
+(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2
+(24 13) routing tnl_op_2 <X> lc_trk_g3_2
+(24 13) routing tnr_op_2 <X> lc_trk_g3_2
+(24 14) routing rgt_op_7 <X> lc_trk_g3_7
+(24 14) routing sp12_v_b_7 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_18 <X> lc_trk_g3_7
+(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7
+(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7
+(24 14) routing sp4_v_b_47 <X> lc_trk_g3_7
+(24 14) routing tnl_op_7 <X> lc_trk_g3_7
+(24 14) routing tnr_op_7 <X> lc_trk_g3_7
+(24 15) routing rgt_op_6 <X> lc_trk_g3_6
+(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6
+(24 15) routing tnl_op_6 <X> lc_trk_g3_6
+(24 15) routing tnr_op_6 <X> lc_trk_g3_6
+(24 2) routing lft_op_7 <X> lc_trk_g0_7
+(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7
+(24 2) routing sp4_h_l_2 <X> lc_trk_g0_7
+(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7
+(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7
+(24 3) routing lft_op_6 <X> lc_trk_g0_6
+(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6
+(24 3) routing top_op_6 <X> lc_trk_g0_6
+(24 4) routing lft_op_3 <X> lc_trk_g1_3
+(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3
+(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3
+(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3
+(24 5) routing lft_op_2 <X> lc_trk_g1_2
+(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2
+(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2
+(24 5) routing top_op_2 <X> lc_trk_g1_2
+(24 6) routing lft_op_7 <X> lc_trk_g1_7
+(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7
+(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7
+(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7
+(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7
+(24 7) routing lft_op_6 <X> lc_trk_g1_6
+(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6
+(24 7) routing top_op_6 <X> lc_trk_g1_6
+(24 8) routing rgt_op_3 <X> lc_trk_g2_3
+(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3
+(24 8) routing sp4_h_l_30 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3
+(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3
+(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3
+(24 8) routing tnl_op_3 <X> lc_trk_g2_3
+(24 8) routing tnr_op_3 <X> lc_trk_g2_3
+(24 9) routing rgt_op_2 <X> lc_trk_g2_2
+(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2
+(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2
+(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2
+(24 9) routing tnl_op_2 <X> lc_trk_g2_2
+(24 9) routing tnr_op_2 <X> lc_trk_g2_2
+(25 0) routing bnr_op_2 <X> lc_trk_g0_2
+(25 0) routing lft_op_2 <X> lc_trk_g0_2
+(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2
+(25 1) routing bnr_op_2 <X> lc_trk_g0_2
+(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2
+(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2
+(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2
+(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2
+(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2
+(25 1) routing top_op_2 <X> lc_trk_g0_2
+(25 10) routing bnl_op_6 <X> lc_trk_g2_6
+(25 10) routing rgt_op_6 <X> lc_trk_g2_6
+(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6
+(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6
+(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 11) routing bnl_op_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6
+(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6
+(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6
+(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6
+(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6
+(25 11) routing tnl_op_6 <X> lc_trk_g2_6
+(25 12) routing bnl_op_2 <X> lc_trk_g3_2
+(25 12) routing rgt_op_2 <X> lc_trk_g3_2
+(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2
+(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2
+(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 13) routing bnl_op_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2
+(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2
+(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2
+(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2
+(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2
+(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2
+(25 13) routing tnl_op_2 <X> lc_trk_g3_2
+(25 14) routing bnl_op_6 <X> lc_trk_g3_6
+(25 14) routing rgt_op_6 <X> lc_trk_g3_6
+(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6
+(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6
+(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 15) routing bnl_op_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6
+(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6
+(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6
+(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6
+(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6
+(25 15) routing tnl_op_6 <X> lc_trk_g3_6
+(25 2) routing bnr_op_6 <X> lc_trk_g0_6
+(25 2) routing lft_op_6 <X> lc_trk_g0_6
+(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6
+(25 2) routing sp4_h_r_22 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6
+(25 3) routing bnr_op_6 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_21 <X> lc_trk_g0_6
+(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_22 <X> lc_trk_g0_6
+(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6
+(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6
+(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6
+(25 3) routing top_op_6 <X> lc_trk_g0_6
+(25 4) routing bnr_op_2 <X> lc_trk_g1_2
+(25 4) routing lft_op_2 <X> lc_trk_g1_2
+(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2
+(25 5) routing bnr_op_2 <X> lc_trk_g1_2
+(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2
+(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2
+(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2
+(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2
+(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2
+(25 5) routing top_op_2 <X> lc_trk_g1_2
+(25 6) routing bnr_op_6 <X> lc_trk_g1_6
+(25 6) routing lft_op_6 <X> lc_trk_g1_6
+(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6
+(25 6) routing sp4_h_r_22 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6
+(25 7) routing bnr_op_6 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6
+(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_22 <X> lc_trk_g1_6
+(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6
+(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6
+(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6
+(25 7) routing top_op_6 <X> lc_trk_g1_6
+(25 8) routing bnl_op_2 <X> lc_trk_g2_2
+(25 8) routing rgt_op_2 <X> lc_trk_g2_2
+(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2
+(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2
+(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 9) routing bnl_op_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2
+(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2
+(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2
+(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2
+(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2
+(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2
+(25 9) routing tnl_op_2 <X> lc_trk_g2_2
+(26 0) routing lc_trk_g0_4 <X> input0_0
+(26 0) routing lc_trk_g0_6 <X> input0_0
+(26 0) routing lc_trk_g1_5 <X> input0_0
+(26 0) routing lc_trk_g1_7 <X> input0_0
+(26 0) routing lc_trk_g2_4 <X> input0_0
+(26 0) routing lc_trk_g2_6 <X> input0_0
+(26 0) routing lc_trk_g3_5 <X> input0_0
+(26 0) routing lc_trk_g3_7 <X> input0_0
+(26 1) routing lc_trk_g0_2 <X> input0_0
+(26 1) routing lc_trk_g0_6 <X> input0_0
+(26 1) routing lc_trk_g1_3 <X> input0_0
+(26 1) routing lc_trk_g1_7 <X> input0_0
+(26 1) routing lc_trk_g2_2 <X> input0_0
+(26 1) routing lc_trk_g2_6 <X> input0_0
+(26 1) routing lc_trk_g3_3 <X> input0_0
+(26 1) routing lc_trk_g3_7 <X> input0_0
+(26 10) routing lc_trk_g0_5 <X> input0_5
+(26 10) routing lc_trk_g0_7 <X> input0_5
+(26 10) routing lc_trk_g1_4 <X> input0_5
+(26 10) routing lc_trk_g1_6 <X> input0_5
+(26 10) routing lc_trk_g2_5 <X> input0_5
+(26 10) routing lc_trk_g2_7 <X> input0_5
+(26 10) routing lc_trk_g3_4 <X> input0_5
+(26 10) routing lc_trk_g3_6 <X> input0_5
+(26 11) routing lc_trk_g0_3 <X> input0_5
+(26 11) routing lc_trk_g0_7 <X> input0_5
+(26 11) routing lc_trk_g1_2 <X> input0_5
+(26 11) routing lc_trk_g1_6 <X> input0_5
+(26 11) routing lc_trk_g2_3 <X> input0_5
+(26 11) routing lc_trk_g2_7 <X> input0_5
+(26 11) routing lc_trk_g3_2 <X> input0_5
+(26 11) routing lc_trk_g3_6 <X> input0_5
+(26 12) routing lc_trk_g0_4 <X> input0_6
+(26 12) routing lc_trk_g0_6 <X> input0_6
+(26 12) routing lc_trk_g1_5 <X> input0_6
+(26 12) routing lc_trk_g1_7 <X> input0_6
+(26 12) routing lc_trk_g2_4 <X> input0_6
+(26 12) routing lc_trk_g2_6 <X> input0_6
+(26 12) routing lc_trk_g3_5 <X> input0_6
+(26 12) routing lc_trk_g3_7 <X> input0_6
+(26 13) routing lc_trk_g0_2 <X> input0_6
+(26 13) routing lc_trk_g0_6 <X> input0_6
+(26 13) routing lc_trk_g1_3 <X> input0_6
+(26 13) routing lc_trk_g1_7 <X> input0_6
+(26 13) routing lc_trk_g2_2 <X> input0_6
+(26 13) routing lc_trk_g2_6 <X> input0_6
+(26 13) routing lc_trk_g3_3 <X> input0_6
+(26 13) routing lc_trk_g3_7 <X> input0_6
+(26 14) routing lc_trk_g0_5 <X> input0_7
+(26 14) routing lc_trk_g0_7 <X> input0_7
+(26 14) routing lc_trk_g1_4 <X> input0_7
+(26 14) routing lc_trk_g1_6 <X> input0_7
+(26 14) routing lc_trk_g2_5 <X> input0_7
+(26 14) routing lc_trk_g2_7 <X> input0_7
+(26 14) routing lc_trk_g3_4 <X> input0_7
+(26 14) routing lc_trk_g3_6 <X> input0_7
+(26 15) routing lc_trk_g0_3 <X> input0_7
+(26 15) routing lc_trk_g0_7 <X> input0_7
+(26 15) routing lc_trk_g1_2 <X> input0_7
+(26 15) routing lc_trk_g1_6 <X> input0_7
+(26 15) routing lc_trk_g2_3 <X> input0_7
+(26 15) routing lc_trk_g2_7 <X> input0_7
+(26 15) routing lc_trk_g3_2 <X> input0_7
+(26 15) routing lc_trk_g3_6 <X> input0_7
+(26 2) routing lc_trk_g0_5 <X> input0_1
+(26 2) routing lc_trk_g0_7 <X> input0_1
+(26 2) routing lc_trk_g1_4 <X> input0_1
+(26 2) routing lc_trk_g1_6 <X> input0_1
+(26 2) routing lc_trk_g2_5 <X> input0_1
+(26 2) routing lc_trk_g2_7 <X> input0_1
+(26 2) routing lc_trk_g3_4 <X> input0_1
+(26 2) routing lc_trk_g3_6 <X> input0_1
+(26 3) routing lc_trk_g0_3 <X> input0_1
+(26 3) routing lc_trk_g0_7 <X> input0_1
+(26 3) routing lc_trk_g1_2 <X> input0_1
+(26 3) routing lc_trk_g1_6 <X> input0_1
+(26 3) routing lc_trk_g2_3 <X> input0_1
+(26 3) routing lc_trk_g2_7 <X> input0_1
+(26 3) routing lc_trk_g3_2 <X> input0_1
+(26 3) routing lc_trk_g3_6 <X> input0_1
+(26 4) routing lc_trk_g0_4 <X> input0_2
+(26 4) routing lc_trk_g0_6 <X> input0_2
+(26 4) routing lc_trk_g1_5 <X> input0_2
+(26 4) routing lc_trk_g1_7 <X> input0_2
+(26 4) routing lc_trk_g2_4 <X> input0_2
+(26 4) routing lc_trk_g2_6 <X> input0_2
+(26 4) routing lc_trk_g3_5 <X> input0_2
+(26 4) routing lc_trk_g3_7 <X> input0_2
+(26 5) routing lc_trk_g0_2 <X> input0_2
+(26 5) routing lc_trk_g0_6 <X> input0_2
+(26 5) routing lc_trk_g1_3 <X> input0_2
+(26 5) routing lc_trk_g1_7 <X> input0_2
+(26 5) routing lc_trk_g2_2 <X> input0_2
+(26 5) routing lc_trk_g2_6 <X> input0_2
+(26 5) routing lc_trk_g3_3 <X> input0_2
+(26 5) routing lc_trk_g3_7 <X> input0_2
+(26 6) routing lc_trk_g0_5 <X> input0_3
+(26 6) routing lc_trk_g0_7 <X> input0_3
+(26 6) routing lc_trk_g1_4 <X> input0_3
+(26 6) routing lc_trk_g1_6 <X> input0_3
+(26 6) routing lc_trk_g2_5 <X> input0_3
+(26 6) routing lc_trk_g2_7 <X> input0_3
+(26 6) routing lc_trk_g3_4 <X> input0_3
+(26 6) routing lc_trk_g3_6 <X> input0_3
+(26 7) routing lc_trk_g0_3 <X> input0_3
+(26 7) routing lc_trk_g0_7 <X> input0_3
+(26 7) routing lc_trk_g1_2 <X> input0_3
+(26 7) routing lc_trk_g1_6 <X> input0_3
+(26 7) routing lc_trk_g2_3 <X> input0_3
+(26 7) routing lc_trk_g2_7 <X> input0_3
+(26 7) routing lc_trk_g3_2 <X> input0_3
+(26 7) routing lc_trk_g3_6 <X> input0_3
+(26 8) routing lc_trk_g0_4 <X> input0_4
+(26 8) routing lc_trk_g0_6 <X> input0_4
+(26 8) routing lc_trk_g1_5 <X> input0_4
+(26 8) routing lc_trk_g1_7 <X> input0_4
+(26 8) routing lc_trk_g2_4 <X> input0_4
+(26 8) routing lc_trk_g2_6 <X> input0_4
+(26 8) routing lc_trk_g3_5 <X> input0_4
+(26 8) routing lc_trk_g3_7 <X> input0_4
+(26 9) routing lc_trk_g0_2 <X> input0_4
+(26 9) routing lc_trk_g0_6 <X> input0_4
+(26 9) routing lc_trk_g1_3 <X> input0_4
+(26 9) routing lc_trk_g1_7 <X> input0_4
+(26 9) routing lc_trk_g2_2 <X> input0_4
+(26 9) routing lc_trk_g2_6 <X> input0_4
+(26 9) routing lc_trk_g3_3 <X> input0_4
+(26 9) routing lc_trk_g3_7 <X> input0_4
+(27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7
+(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7
+(27 1) routing lc_trk_g1_1 <X> input0_0
+(27 1) routing lc_trk_g1_3 <X> input0_0
+(27 1) routing lc_trk_g1_5 <X> input0_0
+(27 1) routing lc_trk_g1_7 <X> input0_0
+(27 1) routing lc_trk_g3_1 <X> input0_0
+(27 1) routing lc_trk_g3_3 <X> input0_0
+(27 1) routing lc_trk_g3_5 <X> input0_0
+(27 1) routing lc_trk_g3_7 <X> input0_0
+(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2
+(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2
+(27 11) routing lc_trk_g1_0 <X> input0_5
+(27 11) routing lc_trk_g1_2 <X> input0_5
+(27 11) routing lc_trk_g1_4 <X> input0_5
+(27 11) routing lc_trk_g1_6 <X> input0_5
+(27 11) routing lc_trk_g3_0 <X> input0_5
+(27 11) routing lc_trk_g3_2 <X> input0_5
+(27 11) routing lc_trk_g3_4 <X> input0_5
+(27 11) routing lc_trk_g3_6 <X> input0_5
+(27 12) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1
+(27 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1
+(27 13) routing lc_trk_g1_1 <X> input0_6
+(27 13) routing lc_trk_g1_3 <X> input0_6
+(27 13) routing lc_trk_g1_5 <X> input0_6
+(27 13) routing lc_trk_g1_7 <X> input0_6
+(27 13) routing lc_trk_g3_1 <X> input0_6
+(27 13) routing lc_trk_g3_3 <X> input0_6
+(27 13) routing lc_trk_g3_5 <X> input0_6
+(27 13) routing lc_trk_g3_7 <X> input0_6
+(27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0
+(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0
+(27 15) routing lc_trk_g1_0 <X> input0_7
+(27 15) routing lc_trk_g1_2 <X> input0_7
+(27 15) routing lc_trk_g1_4 <X> input0_7
+(27 15) routing lc_trk_g1_6 <X> input0_7
+(27 15) routing lc_trk_g3_0 <X> input0_7
+(27 15) routing lc_trk_g3_2 <X> input0_7
+(27 15) routing lc_trk_g3_4 <X> input0_7
+(27 15) routing lc_trk_g3_6 <X> input0_7
+(27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6
+(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6
+(27 3) routing lc_trk_g1_0 <X> input0_1
+(27 3) routing lc_trk_g1_2 <X> input0_1
+(27 3) routing lc_trk_g1_4 <X> input0_1
+(27 3) routing lc_trk_g1_6 <X> input0_1
+(27 3) routing lc_trk_g3_0 <X> input0_1
+(27 3) routing lc_trk_g3_2 <X> input0_1
+(27 3) routing lc_trk_g3_4 <X> input0_1
+(27 3) routing lc_trk_g3_6 <X> input0_1
+(27 4) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5
+(27 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5
+(27 5) routing lc_trk_g1_1 <X> input0_2
+(27 5) routing lc_trk_g1_3 <X> input0_2
+(27 5) routing lc_trk_g1_5 <X> input0_2
+(27 5) routing lc_trk_g1_7 <X> input0_2
+(27 5) routing lc_trk_g3_1 <X> input0_2
+(27 5) routing lc_trk_g3_3 <X> input0_2
+(27 5) routing lc_trk_g3_5 <X> input0_2
+(27 5) routing lc_trk_g3_7 <X> input0_2
+(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4
+(27 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4
+(27 7) routing lc_trk_g1_0 <X> input0_3
+(27 7) routing lc_trk_g1_2 <X> input0_3
+(27 7) routing lc_trk_g1_4 <X> input0_3
+(27 7) routing lc_trk_g1_6 <X> input0_3
+(27 7) routing lc_trk_g3_0 <X> input0_3
+(27 7) routing lc_trk_g3_2 <X> input0_3
+(27 7) routing lc_trk_g3_4 <X> input0_3
+(27 7) routing lc_trk_g3_6 <X> input0_3
+(27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3
+(27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3
+(27 9) routing lc_trk_g1_1 <X> input0_4
+(27 9) routing lc_trk_g1_3 <X> input0_4
+(27 9) routing lc_trk_g1_5 <X> input0_4
+(27 9) routing lc_trk_g1_7 <X> input0_4
+(27 9) routing lc_trk_g3_1 <X> input0_4
+(27 9) routing lc_trk_g3_3 <X> input0_4
+(27 9) routing lc_trk_g3_5 <X> input0_4
+(27 9) routing lc_trk_g3_7 <X> input0_4
+(28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7
+(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7
+(28 1) routing lc_trk_g2_0 <X> input0_0
+(28 1) routing lc_trk_g2_2 <X> input0_0
+(28 1) routing lc_trk_g2_4 <X> input0_0
+(28 1) routing lc_trk_g2_6 <X> input0_0
+(28 1) routing lc_trk_g3_1 <X> input0_0
+(28 1) routing lc_trk_g3_3 <X> input0_0
+(28 1) routing lc_trk_g3_5 <X> input0_0
+(28 1) routing lc_trk_g3_7 <X> input0_0
+(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2
+(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2
+(28 11) routing lc_trk_g2_1 <X> input0_5
+(28 11) routing lc_trk_g2_3 <X> input0_5
+(28 11) routing lc_trk_g2_5 <X> input0_5
+(28 11) routing lc_trk_g2_7 <X> input0_5
+(28 11) routing lc_trk_g3_0 <X> input0_5
+(28 11) routing lc_trk_g3_2 <X> input0_5
+(28 11) routing lc_trk_g3_4 <X> input0_5
+(28 11) routing lc_trk_g3_6 <X> input0_5
+(28 12) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1
+(28 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1
+(28 13) routing lc_trk_g2_0 <X> input0_6
+(28 13) routing lc_trk_g2_2 <X> input0_6
+(28 13) routing lc_trk_g2_4 <X> input0_6
+(28 13) routing lc_trk_g2_6 <X> input0_6
+(28 13) routing lc_trk_g3_1 <X> input0_6
+(28 13) routing lc_trk_g3_3 <X> input0_6
+(28 13) routing lc_trk_g3_5 <X> input0_6
+(28 13) routing lc_trk_g3_7 <X> input0_6
+(28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0
+(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0
+(28 15) routing lc_trk_g2_1 <X> input0_7
+(28 15) routing lc_trk_g2_3 <X> input0_7
+(28 15) routing lc_trk_g2_5 <X> input0_7
+(28 15) routing lc_trk_g2_7 <X> input0_7
+(28 15) routing lc_trk_g3_0 <X> input0_7
+(28 15) routing lc_trk_g3_2 <X> input0_7
+(28 15) routing lc_trk_g3_4 <X> input0_7
+(28 15) routing lc_trk_g3_6 <X> input0_7
+(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6
+(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6
+(28 3) routing lc_trk_g2_1 <X> input0_1
+(28 3) routing lc_trk_g2_3 <X> input0_1
+(28 3) routing lc_trk_g2_5 <X> input0_1
+(28 3) routing lc_trk_g2_7 <X> input0_1
+(28 3) routing lc_trk_g3_0 <X> input0_1
+(28 3) routing lc_trk_g3_2 <X> input0_1
+(28 3) routing lc_trk_g3_4 <X> input0_1
+(28 3) routing lc_trk_g3_6 <X> input0_1
+(28 4) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5
+(28 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5
+(28 5) routing lc_trk_g2_0 <X> input0_2
+(28 5) routing lc_trk_g2_2 <X> input0_2
+(28 5) routing lc_trk_g2_4 <X> input0_2
+(28 5) routing lc_trk_g2_6 <X> input0_2
+(28 5) routing lc_trk_g3_1 <X> input0_2
+(28 5) routing lc_trk_g3_3 <X> input0_2
+(28 5) routing lc_trk_g3_5 <X> input0_2
+(28 5) routing lc_trk_g3_7 <X> input0_2
+(28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4
+(28 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4
+(28 7) routing lc_trk_g2_1 <X> input0_3
+(28 7) routing lc_trk_g2_3 <X> input0_3
+(28 7) routing lc_trk_g2_5 <X> input0_3
+(28 7) routing lc_trk_g2_7 <X> input0_3
+(28 7) routing lc_trk_g3_0 <X> input0_3
+(28 7) routing lc_trk_g3_2 <X> input0_3
+(28 7) routing lc_trk_g3_4 <X> input0_3
+(28 7) routing lc_trk_g3_6 <X> input0_3
+(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3
+(28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3
+(28 9) routing lc_trk_g2_0 <X> input0_4
+(28 9) routing lc_trk_g2_2 <X> input0_4
+(28 9) routing lc_trk_g2_4 <X> input0_4
+(28 9) routing lc_trk_g2_6 <X> input0_4
+(28 9) routing lc_trk_g3_1 <X> input0_4
+(28 9) routing lc_trk_g3_3 <X> input0_4
+(28 9) routing lc_trk_g3_5 <X> input0_4
+(28 9) routing lc_trk_g3_7 <X> input0_4
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7
+(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0
+(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_2
+(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_2
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5
+(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_1
+(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_1
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6
+(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_0
+(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_0
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7
+(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_6
+(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_6
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1
+(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_5
+(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_5
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2
+(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_4
+(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_4
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3
+(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_3
+(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_3
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4
+(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4
+(3 0) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 0) routing sp12_v_t_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_l_23 <X> sp12_v_b_0
+(3 1) routing sp12_h_r_0 <X> sp12_v_b_0
+(3 10) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 10) routing sp12_v_t_22 <X> sp12_h_l_22
+(3 11) routing sp12_h_r_1 <X> sp12_h_l_22
+(3 11) routing sp12_v_b_1 <X> sp12_h_l_22
+(3 12) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 12) routing sp12_v_t_22 <X> sp12_h_r_1
+(3 13) routing sp12_h_l_22 <X> sp12_h_r_1
+(3 13) routing sp12_v_b_1 <X> sp12_h_r_1
+(3 14) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 14) routing sp12_v_b_1 <X> sp12_v_t_22
+(3 15) routing sp12_h_l_22 <X> sp12_v_t_22
+(3 15) routing sp12_h_r_1 <X> sp12_v_t_22
+(3 2) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 2) routing sp12_v_t_23 <X> sp12_h_l_23
+(3 3) routing sp12_h_r_0 <X> sp12_h_l_23
+(3 3) routing sp12_v_b_0 <X> sp12_h_l_23
+(3 4) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 4) routing sp12_v_t_23 <X> sp12_h_r_0
+(3 5) routing sp12_h_l_23 <X> sp12_h_r_0
+(3 5) routing sp12_v_b_0 <X> sp12_h_r_0
+(3 6) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 6) routing sp12_v_b_0 <X> sp12_v_t_23
+(3 7) routing sp12_h_l_23 <X> sp12_v_t_23
+(3 7) routing sp12_h_r_0 <X> sp12_v_t_23
+(3 8) routing sp12_h_r_1 <X> sp12_v_b_1
+(3 8) routing sp12_v_t_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_l_22 <X> sp12_v_b_1
+(3 9) routing sp12_h_r_1 <X> sp12_v_b_1
+(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7
+(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7
+(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7
+(30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2
+(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2
+(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2
+(30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_1
+(30 12) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_1
+(30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_1
+(30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_0
+(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0
+(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0
+(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6
+(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6
+(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6
+(30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_5
+(30 4) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5
+(30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5
+(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4
+(30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4
+(30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4
+(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3
+(30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3
+(30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3
+(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7
+(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7
+(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7
+(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2
+(31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2
+(31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2
+(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1
+(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1
+(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1
+(31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0
+(31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0
+(31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0
+(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6
+(31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6
+(31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6
+(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5
+(31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5
+(31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5
+(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4
+(31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4
+(31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4
+(31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3
+(31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3
+(31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7
+(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2
+(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5
+(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1
+(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6
+(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_0
+(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_0
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7
+(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_6
+(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_6
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5
+(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4
+(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3
+(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3
+(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7
+(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7
+(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2
+(33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2
+(33 11) routing lc_trk_g2_1 <X> input2_5
+(33 11) routing lc_trk_g2_3 <X> input2_5
+(33 11) routing lc_trk_g2_5 <X> input2_5
+(33 11) routing lc_trk_g2_7 <X> input2_5
+(33 11) routing lc_trk_g3_0 <X> input2_5
+(33 11) routing lc_trk_g3_2 <X> input2_5
+(33 11) routing lc_trk_g3_4 <X> input2_5
+(33 11) routing lc_trk_g3_6 <X> input2_5
+(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1
+(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1
+(33 13) routing lc_trk_g2_0 <X> input2_6
+(33 13) routing lc_trk_g2_2 <X> input2_6
+(33 13) routing lc_trk_g2_4 <X> input2_6
+(33 13) routing lc_trk_g2_6 <X> input2_6
+(33 13) routing lc_trk_g3_1 <X> input2_6
+(33 13) routing lc_trk_g3_3 <X> input2_6
+(33 13) routing lc_trk_g3_5 <X> input2_6
+(33 13) routing lc_trk_g3_7 <X> input2_6
+(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0
+(33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0
+(33 15) routing lc_trk_g2_1 <X> input2_7
+(33 15) routing lc_trk_g2_3 <X> input2_7
+(33 15) routing lc_trk_g2_5 <X> input2_7
+(33 15) routing lc_trk_g2_7 <X> input2_7
+(33 15) routing lc_trk_g3_0 <X> input2_7
+(33 15) routing lc_trk_g3_2 <X> input2_7
+(33 15) routing lc_trk_g3_4 <X> input2_7
+(33 15) routing lc_trk_g3_6 <X> input2_7
+(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6
+(33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6
+(33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5
+(33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5
+(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4
+(33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4
+(33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3
+(33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3
+(34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7
+(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7
+(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2
+(34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2
+(34 11) routing lc_trk_g1_0 <X> input2_5
+(34 11) routing lc_trk_g1_2 <X> input2_5
+(34 11) routing lc_trk_g1_4 <X> input2_5
+(34 11) routing lc_trk_g1_6 <X> input2_5
+(34 11) routing lc_trk_g3_0 <X> input2_5
+(34 11) routing lc_trk_g3_2 <X> input2_5
+(34 11) routing lc_trk_g3_4 <X> input2_5
+(34 11) routing lc_trk_g3_6 <X> input2_5
+(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1
+(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1
+(34 13) routing lc_trk_g1_1 <X> input2_6
+(34 13) routing lc_trk_g1_3 <X> input2_6
+(34 13) routing lc_trk_g1_5 <X> input2_6
+(34 13) routing lc_trk_g1_7 <X> input2_6
+(34 13) routing lc_trk_g3_1 <X> input2_6
+(34 13) routing lc_trk_g3_3 <X> input2_6
+(34 13) routing lc_trk_g3_5 <X> input2_6
+(34 13) routing lc_trk_g3_7 <X> input2_6
+(34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0
+(34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0
+(34 15) routing lc_trk_g1_0 <X> input2_7
+(34 15) routing lc_trk_g1_2 <X> input2_7
+(34 15) routing lc_trk_g1_4 <X> input2_7
+(34 15) routing lc_trk_g1_6 <X> input2_7
+(34 15) routing lc_trk_g3_0 <X> input2_7
+(34 15) routing lc_trk_g3_2 <X> input2_7
+(34 15) routing lc_trk_g3_4 <X> input2_7
+(34 15) routing lc_trk_g3_6 <X> input2_7
+(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6
+(34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6
+(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5
+(34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5
+(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4
+(34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4
+(34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3
+(34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3
+(35 10) routing lc_trk_g0_5 <X> input2_5
+(35 10) routing lc_trk_g0_7 <X> input2_5
+(35 10) routing lc_trk_g1_4 <X> input2_5
+(35 10) routing lc_trk_g1_6 <X> input2_5
+(35 10) routing lc_trk_g2_5 <X> input2_5
+(35 10) routing lc_trk_g2_7 <X> input2_5
+(35 10) routing lc_trk_g3_4 <X> input2_5
+(35 10) routing lc_trk_g3_6 <X> input2_5
+(35 11) routing lc_trk_g0_3 <X> input2_5
+(35 11) routing lc_trk_g0_7 <X> input2_5
+(35 11) routing lc_trk_g1_2 <X> input2_5
+(35 11) routing lc_trk_g1_6 <X> input2_5
+(35 11) routing lc_trk_g2_3 <X> input2_5
+(35 11) routing lc_trk_g2_7 <X> input2_5
+(35 11) routing lc_trk_g3_2 <X> input2_5
+(35 11) routing lc_trk_g3_6 <X> input2_5
+(35 12) routing lc_trk_g0_4 <X> input2_6
+(35 12) routing lc_trk_g0_6 <X> input2_6
+(35 12) routing lc_trk_g1_5 <X> input2_6
+(35 12) routing lc_trk_g1_7 <X> input2_6
+(35 12) routing lc_trk_g2_4 <X> input2_6
+(35 12) routing lc_trk_g2_6 <X> input2_6
+(35 12) routing lc_trk_g3_5 <X> input2_6
+(35 12) routing lc_trk_g3_7 <X> input2_6
+(35 13) routing lc_trk_g0_2 <X> input2_6
+(35 13) routing lc_trk_g0_6 <X> input2_6
+(35 13) routing lc_trk_g1_3 <X> input2_6
+(35 13) routing lc_trk_g1_7 <X> input2_6
+(35 13) routing lc_trk_g2_2 <X> input2_6
+(35 13) routing lc_trk_g2_6 <X> input2_6
+(35 13) routing lc_trk_g3_3 <X> input2_6
+(35 13) routing lc_trk_g3_7 <X> input2_6
+(35 14) routing lc_trk_g0_5 <X> input2_7
+(35 14) routing lc_trk_g0_7 <X> input2_7
+(35 14) routing lc_trk_g1_4 <X> input2_7
+(35 14) routing lc_trk_g1_6 <X> input2_7
+(35 14) routing lc_trk_g2_5 <X> input2_7
+(35 14) routing lc_trk_g2_7 <X> input2_7
+(35 14) routing lc_trk_g3_4 <X> input2_7
+(35 14) routing lc_trk_g3_6 <X> input2_7
+(35 15) routing lc_trk_g0_3 <X> input2_7
+(35 15) routing lc_trk_g0_7 <X> input2_7
+(35 15) routing lc_trk_g1_2 <X> input2_7
+(35 15) routing lc_trk_g1_6 <X> input2_7
+(35 15) routing lc_trk_g2_3 <X> input2_7
+(35 15) routing lc_trk_g2_7 <X> input2_7
+(35 15) routing lc_trk_g3_2 <X> input2_7
+(35 15) routing lc_trk_g3_6 <X> input2_7
+(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21
+(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0
+(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42
+(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10
+(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44
+(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12
+(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46
+(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3
+(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34
+(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2
+(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36
+(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4
+(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27
+(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6
+(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29
+(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8
+(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8
+(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5
+(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2
+(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_2 sp4_h_l_15
+(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_1 sp12_h_l_3
+(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_1 sp4_h_l_17
+(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_0 sp12_h_l_5
+(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_0 sp4_h_r_30
+(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_6 sp12_h_r_10
+(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_6 sp4_h_l_7
+(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_5 sp12_h_r_12
+(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_5 sp4_h_r_20
+(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_4 sp12_h_l_13
+(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_4 sp4_h_r_22
+(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_3 sp12_h_r_0
+(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13
+(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21
+(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0
+(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26
+(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18
+(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28
+(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20
+(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_0 sp4_v_b_30
+(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_0 sp12_h_l_21
+(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_6 sp4_v_t_23
+(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_6 sp4_v_b_2
+(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_5 sp4_v_t_25
+(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_5 sp4_v_b_4
+(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_4 sp4_v_b_38
+(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_4 sp4_v_b_6
+(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_3 sp4_v_t_13
+(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_3 sp12_h_r_16
+(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_7 sp12_v_b_0
+(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_7 sp4_v_b_16
+(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_2 sp4_v_t_31
+(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_2 sp4_v_b_10
+(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_1 sp4_v_t_33
+(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_1 sp4_v_t_1
+(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_0 sp4_v_b_46
+(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_0 sp4_v_b_14
+(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_6 sp12_v_b_2
+(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_6 sp4_v_t_7
+(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_5 sp12_v_t_3
+(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_5 sp4_v_b_20
+(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_4 sp12_v_b_6
+(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_4 sp4_v_b_22
+(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_3 sp4_v_b_40
+(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_3 sp4_v_b_8
+(4 0) routing sp4_h_l_37 <X> sp4_v_b_0
+(4 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_37 <X> sp4_v_b_0
+(4 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(4 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(4 1) routing sp4_h_l_44 <X> sp4_h_r_0
+(4 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(4 1) routing sp4_v_t_42 <X> sp4_h_r_0
+(4 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(4 10) routing sp4_h_r_6 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(4 10) routing sp4_v_b_6 <X> sp4_v_t_43
+(4 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(4 11) routing sp4_h_r_3 <X> sp4_h_l_43
+(4 11) routing sp4_v_b_1 <X> sp4_h_l_43
+(4 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(4 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(4 12) routing sp4_h_l_44 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(4 12) routing sp4_v_t_44 <X> sp4_v_b_9
+(4 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(4 13) routing sp4_h_l_43 <X> sp4_h_r_9
+(4 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(4 13) routing sp4_v_t_41 <X> sp4_h_r_9
+(4 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(4 14) routing sp4_h_r_9 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(4 14) routing sp4_v_b_9 <X> sp4_v_t_44
+(4 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(4 15) routing sp4_h_r_6 <X> sp4_h_l_44
+(4 15) routing sp4_v_b_4 <X> sp4_h_l_44
+(4 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(4 2) routing sp4_h_r_0 <X> sp4_v_t_37
+(4 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_0 <X> sp4_v_t_37
+(4 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(4 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(4 3) routing sp4_h_r_9 <X> sp4_h_l_37
+(4 3) routing sp4_v_b_7 <X> sp4_h_l_37
+(4 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(4 4) routing sp4_h_l_38 <X> sp4_v_b_3
+(4 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_38 <X> sp4_v_b_3
+(4 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(4 5) routing sp4_h_l_37 <X> sp4_h_r_3
+(4 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(4 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(4 5) routing sp4_v_t_47 <X> sp4_h_r_3
+(4 6) routing sp4_h_r_3 <X> sp4_v_t_38
+(4 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_3 <X> sp4_v_t_38
+(4 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(4 7) routing sp4_h_r_0 <X> sp4_h_l_38
+(4 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(4 7) routing sp4_v_b_10 <X> sp4_h_l_38
+(4 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(4 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(4 8) routing sp4_h_l_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_43 <X> sp4_v_b_6
+(4 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(4 9) routing sp4_h_l_38 <X> sp4_h_r_6
+(4 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(4 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(4 9) routing sp4_v_t_36 <X> sp4_h_r_6
+(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17
+(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16
+(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27
+(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9
+(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_29
+(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12
+(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31
+(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14
+(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19
+(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17
+(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21
+(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19
+(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_23
+(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_4 sp12_v_t_21
+(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25
+(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7
+(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33
+(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1
+(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43
+(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11
+(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45
+(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_13
+(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_47
+(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_15
+(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_35
+(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_3
+(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_37
+(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_5
+(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_39
+(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_7
+(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_41
+(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_9
+(5 0) routing sp4_h_l_44 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_0 <X> sp4_h_r_0
+(5 0) routing sp4_v_b_6 <X> sp4_h_r_0
+(5 0) routing sp4_v_t_37 <X> sp4_h_r_0
+(5 1) routing sp4_h_l_37 <X> sp4_v_b_0
+(5 1) routing sp4_h_l_43 <X> sp4_v_b_0
+(5 1) routing sp4_h_r_0 <X> sp4_v_b_0
+(5 1) routing sp4_v_t_44 <X> sp4_v_b_0
+(5 10) routing sp4_h_r_3 <X> sp4_h_l_43
+(5 10) routing sp4_v_b_6 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_37 <X> sp4_h_l_43
+(5 10) routing sp4_v_t_43 <X> sp4_h_l_43
+(5 11) routing sp4_h_l_43 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_0 <X> sp4_v_t_43
+(5 11) routing sp4_h_r_6 <X> sp4_v_t_43
+(5 11) routing sp4_v_b_3 <X> sp4_v_t_43
+(5 12) routing sp4_h_l_43 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_3 <X> sp4_h_r_9
+(5 12) routing sp4_v_b_9 <X> sp4_h_r_9
+(5 12) routing sp4_v_t_44 <X> sp4_h_r_9
+(5 13) routing sp4_h_l_38 <X> sp4_v_b_9
+(5 13) routing sp4_h_l_44 <X> sp4_v_b_9
+(5 13) routing sp4_h_r_9 <X> sp4_v_b_9
+(5 13) routing sp4_v_t_43 <X> sp4_v_b_9
+(5 14) routing sp4_h_r_6 <X> sp4_h_l_44
+(5 14) routing sp4_v_b_9 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_38 <X> sp4_h_l_44
+(5 14) routing sp4_v_t_44 <X> sp4_h_l_44
+(5 15) routing sp4_h_l_44 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_3 <X> sp4_v_t_44
+(5 15) routing sp4_h_r_9 <X> sp4_v_t_44
+(5 15) routing sp4_v_b_6 <X> sp4_v_t_44
+(5 2) routing sp4_h_r_9 <X> sp4_h_l_37
+(5 2) routing sp4_v_b_0 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_37 <X> sp4_h_l_37
+(5 2) routing sp4_v_t_43 <X> sp4_h_l_37
+(5 3) routing sp4_h_l_37 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_0 <X> sp4_v_t_37
+(5 3) routing sp4_h_r_6 <X> sp4_v_t_37
+(5 3) routing sp4_v_b_9 <X> sp4_v_t_37
+(5 4) routing sp4_h_l_37 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_3 <X> sp4_h_r_3
+(5 4) routing sp4_v_b_9 <X> sp4_h_r_3
+(5 4) routing sp4_v_t_38 <X> sp4_h_r_3
+(5 5) routing sp4_h_l_38 <X> sp4_v_b_3
+(5 5) routing sp4_h_l_44 <X> sp4_v_b_3
+(5 5) routing sp4_h_r_3 <X> sp4_v_b_3
+(5 5) routing sp4_v_t_37 <X> sp4_v_b_3
+(5 6) routing sp4_h_r_0 <X> sp4_h_l_38
+(5 6) routing sp4_v_b_3 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_38 <X> sp4_h_l_38
+(5 6) routing sp4_v_t_44 <X> sp4_h_l_38
+(5 7) routing sp4_h_l_38 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_3 <X> sp4_v_t_38
+(5 7) routing sp4_h_r_9 <X> sp4_v_t_38
+(5 7) routing sp4_v_b_0 <X> sp4_v_t_38
+(5 8) routing sp4_h_l_38 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_0 <X> sp4_h_r_6
+(5 8) routing sp4_v_b_6 <X> sp4_h_r_6
+(5 8) routing sp4_v_t_43 <X> sp4_h_r_6
+(5 9) routing sp4_h_l_37 <X> sp4_v_b_6
+(5 9) routing sp4_h_l_43 <X> sp4_v_b_6
+(5 9) routing sp4_h_r_6 <X> sp4_v_b_6
+(5 9) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 0) routing sp4_h_l_43 <X> sp4_v_b_0
+(6 0) routing sp4_h_r_7 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_41 <X> sp4_v_b_0
+(6 0) routing sp4_v_t_44 <X> sp4_v_b_0
+(6 1) routing sp4_h_l_37 <X> sp4_h_r_0
+(6 1) routing sp4_h_l_41 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_0 <X> sp4_h_r_0
+(6 1) routing sp4_v_b_6 <X> sp4_h_r_0
+(6 10) routing sp4_h_l_36 <X> sp4_v_t_43
+(6 10) routing sp4_h_r_0 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_10 <X> sp4_v_t_43
+(6 10) routing sp4_v_b_3 <X> sp4_v_t_43
+(6 11) routing sp4_h_r_10 <X> sp4_h_l_43
+(6 11) routing sp4_h_r_6 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_37 <X> sp4_h_l_43
+(6 11) routing sp4_v_t_43 <X> sp4_h_l_43
+(6 12) routing sp4_h_l_38 <X> sp4_v_b_9
+(6 12) routing sp4_h_r_4 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_36 <X> sp4_v_b_9
+(6 12) routing sp4_v_t_43 <X> sp4_v_b_9
+(6 13) routing sp4_h_l_36 <X> sp4_h_r_9
+(6 13) routing sp4_h_l_44 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_3 <X> sp4_h_r_9
+(6 13) routing sp4_v_b_9 <X> sp4_h_r_9
+(6 14) routing sp4_h_l_41 <X> sp4_v_t_44
+(6 14) routing sp4_h_r_3 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_1 <X> sp4_v_t_44
+(6 14) routing sp4_v_b_6 <X> sp4_v_t_44
+(6 15) routing sp4_h_r_1 <X> sp4_h_l_44
+(6 15) routing sp4_h_r_9 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_38 <X> sp4_h_l_44
+(6 15) routing sp4_v_t_44 <X> sp4_h_l_44
+(6 2) routing sp4_h_l_42 <X> sp4_v_t_37
+(6 2) routing sp4_h_r_6 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_4 <X> sp4_v_t_37
+(6 2) routing sp4_v_b_9 <X> sp4_v_t_37
+(6 3) routing sp4_h_r_0 <X> sp4_h_l_37
+(6 3) routing sp4_h_r_4 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_37 <X> sp4_h_l_37
+(6 3) routing sp4_v_t_43 <X> sp4_h_l_37
+(6 4) routing sp4_h_l_44 <X> sp4_v_b_3
+(6 4) routing sp4_h_r_10 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_37 <X> sp4_v_b_3
+(6 4) routing sp4_v_t_42 <X> sp4_v_b_3
+(6 5) routing sp4_h_l_38 <X> sp4_h_r_3
+(6 5) routing sp4_h_l_42 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_3 <X> sp4_h_r_3
+(6 5) routing sp4_v_b_9 <X> sp4_h_r_3
+(6 6) routing sp4_h_l_47 <X> sp4_v_t_38
+(6 6) routing sp4_h_r_9 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_0 <X> sp4_v_t_38
+(6 6) routing sp4_v_b_7 <X> sp4_v_t_38
+(6 7) routing sp4_h_r_3 <X> sp4_h_l_38
+(6 7) routing sp4_h_r_7 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_38 <X> sp4_h_l_38
+(6 7) routing sp4_v_t_44 <X> sp4_h_l_38
+(6 8) routing sp4_h_l_37 <X> sp4_v_b_6
+(6 8) routing sp4_h_r_1 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_38 <X> sp4_v_b_6
+(6 8) routing sp4_v_t_47 <X> sp4_v_b_6
+(6 9) routing sp4_h_l_43 <X> sp4_h_r_6
+(6 9) routing sp4_h_l_47 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_0 <X> sp4_h_r_6
+(6 9) routing sp4_v_b_6 <X> sp4_h_r_6
+(7 0) Ram config bit: MEMT_bram_cbit_1
+(7 1) Ram config bit: MEMT_bram_cbit_0
+(7 10) Column buffer control bit: MEMT_colbuf_cntl_3
+(7 11) Column buffer control bit: MEMT_colbuf_cntl_2
+(7 12) Column buffer control bit: MEMT_colbuf_cntl_5
+(7 13) Column buffer control bit: MEMT_colbuf_cntl_4
+(7 14) Column buffer control bit: MEMT_colbuf_cntl_7
+(7 15) Column buffer control bit: MEMT_colbuf_cntl_6
+(7 2) Ram config bit: MEMT_bram_cbit_3
+(7 3) Ram config bit: MEMT_bram_cbit_2
+(7 8) Column buffer control bit: MEMT_colbuf_cntl_1
+(7 9) Column buffer control bit: MEMT_colbuf_cntl_0
+(8 0) routing sp4_h_l_36 <X> sp4_h_r_1
+(8 0) routing sp4_h_l_40 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(8 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(8 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(8 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(8 1) routing sp4_h_r_1 <X> sp4_v_b_1
+(8 1) routing sp4_v_t_47 <X> sp4_v_b_1
+(8 10) routing sp4_h_r_11 <X> sp4_h_l_42
+(8 10) routing sp4_h_r_7 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(8 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(8 11) routing sp4_h_l_42 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(8 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(8 11) routing sp4_v_b_4 <X> sp4_v_t_42
+(8 12) routing sp4_h_l_39 <X> sp4_h_r_10
+(8 12) routing sp4_h_l_47 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(8 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(8 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(8 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(8 13) routing sp4_h_r_10 <X> sp4_v_b_10
+(8 13) routing sp4_v_t_42 <X> sp4_v_b_10
+(8 14) routing sp4_h_r_10 <X> sp4_h_l_47
+(8 14) routing sp4_h_r_2 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(8 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(8 15) routing sp4_h_l_47 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(8 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(8 15) routing sp4_v_b_7 <X> sp4_v_t_47
+(8 2) routing sp4_h_r_1 <X> sp4_h_l_36
+(8 2) routing sp4_h_r_5 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(8 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(8 3) routing sp4_h_l_36 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(8 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(8 3) routing sp4_v_b_10 <X> sp4_v_t_36
+(8 4) routing sp4_h_l_41 <X> sp4_h_r_4
+(8 4) routing sp4_h_l_45 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(8 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(8 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(8 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(8 5) routing sp4_h_r_4 <X> sp4_v_b_4
+(8 5) routing sp4_v_t_36 <X> sp4_v_b_4
+(8 6) routing sp4_h_r_4 <X> sp4_h_l_41
+(8 6) routing sp4_h_r_8 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(8 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(8 7) routing sp4_h_l_41 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(8 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(8 7) routing sp4_v_b_1 <X> sp4_v_t_41
+(8 8) routing sp4_h_l_42 <X> sp4_h_r_7
+(8 8) routing sp4_h_l_46 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(8 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(8 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(8 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(8 9) routing sp4_h_r_7 <X> sp4_v_b_7
+(8 9) routing sp4_v_t_41 <X> sp4_v_b_7
+(9 0) routing sp4_h_l_47 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_1 <X> sp4_h_r_1
+(9 0) routing sp4_v_b_7 <X> sp4_h_r_1
+(9 0) routing sp4_v_t_36 <X> sp4_h_r_1
+(9 1) routing sp4_h_l_36 <X> sp4_v_b_1
+(9 1) routing sp4_h_l_42 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_36 <X> sp4_v_b_1
+(9 1) routing sp4_v_t_40 <X> sp4_v_b_1
+(9 10) routing sp4_h_r_4 <X> sp4_h_l_42
+(9 10) routing sp4_v_b_7 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_36 <X> sp4_h_l_42
+(9 10) routing sp4_v_t_42 <X> sp4_h_l_42
+(9 11) routing sp4_h_r_1 <X> sp4_v_t_42
+(9 11) routing sp4_h_r_7 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_11 <X> sp4_v_t_42
+(9 11) routing sp4_v_b_7 <X> sp4_v_t_42
+(9 12) routing sp4_h_l_42 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_10 <X> sp4_h_r_10
+(9 12) routing sp4_v_b_4 <X> sp4_h_r_10
+(9 12) routing sp4_v_t_47 <X> sp4_h_r_10
+(9 13) routing sp4_h_l_41 <X> sp4_v_b_10
+(9 13) routing sp4_h_l_47 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_39 <X> sp4_v_b_10
+(9 13) routing sp4_v_t_47 <X> sp4_v_b_10
+(9 14) routing sp4_h_r_7 <X> sp4_h_l_47
+(9 14) routing sp4_v_b_10 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_41 <X> sp4_h_l_47
+(9 14) routing sp4_v_t_47 <X> sp4_h_l_47
+(9 15) routing sp4_h_r_10 <X> sp4_v_t_47
+(9 15) routing sp4_h_r_4 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_10 <X> sp4_v_t_47
+(9 15) routing sp4_v_b_2 <X> sp4_v_t_47
+(9 2) routing sp4_h_r_10 <X> sp4_h_l_36
+(9 2) routing sp4_v_b_1 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_36 <X> sp4_h_l_36
+(9 2) routing sp4_v_t_42 <X> sp4_h_l_36
+(9 3) routing sp4_h_r_1 <X> sp4_v_t_36
+(9 3) routing sp4_h_r_7 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_1 <X> sp4_v_t_36
+(9 3) routing sp4_v_b_5 <X> sp4_v_t_36
+(9 4) routing sp4_h_l_36 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_10 <X> sp4_h_r_4
+(9 4) routing sp4_v_b_4 <X> sp4_h_r_4
+(9 4) routing sp4_v_t_41 <X> sp4_h_r_4
+(9 5) routing sp4_h_l_41 <X> sp4_v_b_4
+(9 5) routing sp4_h_l_47 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_41 <X> sp4_v_b_4
+(9 5) routing sp4_v_t_45 <X> sp4_v_b_4
+(9 6) routing sp4_h_r_1 <X> sp4_h_l_41
+(9 6) routing sp4_v_b_4 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_41 <X> sp4_h_l_41
+(9 6) routing sp4_v_t_47 <X> sp4_h_l_41
+(9 7) routing sp4_h_r_10 <X> sp4_v_t_41
+(9 7) routing sp4_h_r_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_4 <X> sp4_v_t_41
+(9 7) routing sp4_v_b_8 <X> sp4_v_t_41
+(9 8) routing sp4_h_l_41 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_1 <X> sp4_h_r_7
+(9 8) routing sp4_v_b_7 <X> sp4_h_r_7
+(9 8) routing sp4_v_t_42 <X> sp4_h_r_7
+(9 9) routing sp4_h_l_36 <X> sp4_v_b_7
+(9 9) routing sp4_h_l_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_42 <X> sp4_v_b_7
+(9 9) routing sp4_v_t_46 <X> sp4_v_b_7
diff --git a/icefuzz/check.sh b/icefuzz/check.sh
new file mode 100644
index 0000000..bb23cea
--- /dev/null
+++ b/icefuzz/check.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+
+set -ex
+
+for id; do
+ id=${id%.bin}
+ icebox_vlog_opts="-Sa"
+ if test -f $id.pcf; then icebox_vlog_opts="$icebox_vlog_opts -p $id.pcf"; fi
+ if test -f $id.psb; then icebox_vlog_opts="$icebox_vlog_opts -P $id.psb"; fi
+
+ ../icepack/iceunpack $id.bin $id.txt
+ ../icebox/icebox_vlog.py $icebox_vlog_opts $id.txt > $id.ve
+
+ yosys -p "
+ read_verilog $id.v
+ read_verilog $id.ve
+ read_verilog -lib +/ice40/cells_sim.v
+ rename top gold
+ rename chip gate
+
+ proc
+ splitnets -ports
+ clean -purge
+
+ ## Variant 1 ##
+
+ # miter -equiv -flatten gold gate equiv
+ # tee -q synth -top equiv
+ # sat -verify -prove trigger 0 -show-ports equiv
+
+ ## Variant 2 ##
+
+ # miter -equiv -flatten -ignore_gold_x -make_outcmp -make_outputs gold gate equiv
+ # hierarchy -top equiv
+ # sat -max_undef -prove trigger 0 -show-ports equiv
+
+ ## Variant 3 ##
+
+ equiv_make gold gate equiv
+ hierarchy -top equiv
+ opt -share_all
+
+ equiv_simple
+ equiv_induct
+ equiv_status -assert
+ "
+
+ touch $id.ok
+done
+
diff --git a/icefuzz/convert_ram8k.py b/icefuzz/convert_ram8k.py
new file mode 100644
index 0000000..ba4fdae
--- /dev/null
+++ b/icefuzz/convert_ram8k.py
@@ -0,0 +1,28 @@
+#!/usr/bin/python
+# convert 1k ramb/ramt to 8k ramb/ramt and vice versa
+
+subst_rules = [
+ ["/RE", "/WE" ],
+ ["/RCLK", "/WCLK" ],
+ ["/RCLKE", "/WCLKE"],
+ ["DATA_8", "DATA_7"],
+ ["DATA_9", "DATA_6"],
+ ["DATA_10", "DATA_5"],
+ ["DATA_11", "DATA_4"],
+ ["DATA_12", "DATA_3"],
+ ["DATA_13", "DATA_2"],
+ ["DATA_14", "DATA_1"],
+ ["DATA_15", "DATA_0"],
+]
+
+import fileinput
+for line in fileinput.input():
+ line = line.strip()
+ for r in subst_rules:
+ if line.endswith(r[0]):
+ line = line[:-len(r[0])] + r[1]
+ break
+ if line.endswith(r[1]):
+ line = line[:-len(r[1])] + r[0]
+ break
+ print(line)
diff --git a/icefuzz/database.py b/icefuzz/database.py
new file mode 100644
index 0000000..b589f77
--- /dev/null
+++ b/icefuzz/database.py
@@ -0,0 +1,140 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+import re, sys, os
+
+def cmp_bits(a, b):
+ if a[0] == "!": a = a[1:]
+ if b[0] == "!": b = b[1:]
+ a = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a)
+ b = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), b)
+ return cmp(a, b)
+
+def read_database(filename, tile_type):
+ raw_db = list()
+ route_to_buffer = set()
+ add_mux_bits = dict()
+
+ with open(filename, "r") as f:
+ for line in f:
+ line = line.strip()
+ m = re.match(r"\s*\((\d+)\s+(\d+)\)\s+(.*)", line)
+ assert m
+ bit = "B%d[%d]" % (int(m.group(2)), int(m.group(1)))
+ line = m.group(3)
+ line = re.sub(r"^Enable bit of Mux", "MuxEn", line)
+ line = re.sub(r"^IO control bit:", "IoCtrl", line)
+ line = re.sub(r"^Column buffer control bit:", "ColBufCtrl", line)
+ line = re.sub(r"^Negative Clock bit", "NegClk", line)
+ line = re.sub(r"^Cascade (buffer Enable )?bit:", "Cascade", line)
+ line = re.sub(r"^Ram config bit:", "RamConfig", line)
+ line = re.sub(r"^PLL config bit:", "PLL", line)
+ line = re.sub(r"^Icegate Enable bit:", "Icegate", line)
+ line = line.split()
+ if line[0] == "routing":
+ if line[3] == "wire_gbuf/in": line[3] = "fabout"
+ raw_db.append((bit, (line[0], line[1], line[3])))
+ elif line[0] == "IoCtrl":
+ raw_db.append((bit, (line[0], re.sub(r"^.*?_", "", line[1]).replace("_en", ""))))
+ elif line[0] in ("IOB_0", "IOB_1"):
+ if line[1] != "IO":
+ raw_db.append((bit, (line[0], line[1])))
+ elif line[0] == "PLL":
+ line[1] = re.sub(r"CLOCK_T_\d+_\d+_IO(LEFT|RIGHT|UP|DOWN)_", "pll_", line[1])
+ line[1] = re.sub(r"pll_cf_bit_", "PLLCONFIG_", line[1])
+ raw_db.append((bit, (line[0], line[1])))
+ elif line[0] == "ColBufCtrl":
+ line[1] = re.sub(r"B?IO(LEFT|RIGHT)_", "IO_", line[1])
+ line[1] = re.sub(r"IO_half_column_clock_enable_", "glb_netwk_", line[1])
+ line[1] = re.sub(r"(LH|MEM[BT])_colbuf_cntl_", "glb_netwk_", line[1])
+ if m.group(1) == "7":
+ line[1] = re.sub(r"glb_netwk_", "8k_glb_netwk_", line[1])
+ elif m.group(1) in ["1", "2"]:
+ line[1] = re.sub(r"glb_netwk_", "1k_glb_netwk_", line[1])
+ raw_db.append((bit, (line[0], line[1])))
+ elif line[0] == "Cascade":
+ match = re.match("LH_LC0(\d)_inmux02_5", line[1])
+ if match:
+ raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/out" % (int(match.group(1))-1), "input_2_%s" % match.group(1))))
+ else:
+ raw_db.append((bit, (line[0], line[1])))
+ elif line[0] == "RamConfig":
+ if line[1] == "MEMB_Power_Up_Control": line[1] = "PowerUp"
+ line[1] = re.sub(r"MEMT_bram_cbit_", "CBIT_", line[1])
+ raw_db.append((bit, (line[0], line[1])))
+ elif line[0] == "MuxEn":
+ if line[4] == "wire_gbuf/in": line[4] = "fabout"
+ if line[3].startswith("logic_op_"):
+ for prefix in ["IO_L.", "IO_R.", "IO_T.", "IO_B."]:
+ route_to_buffer.add((prefix + line[3], line[4]))
+ add_mux_bits.setdefault(prefix + line[3], set()).add((bit, ("buffer", prefix + line[3], line[4])))
+ else:
+ raw_db.append((bit, ("buffer", line[3], line[4])))
+ route_to_buffer.add((line[3], line[4]))
+ elif line[0] == "NegClk" or line[0] == "Icegate" or re.match(r"LC_\d+", line[0]):
+ raw_db.append((bit, (line[0],)))
+ elif line[0] == "Carry_In_Mux":
+ continue
+ else:
+ print("unsupported statement: %s: %s" % (bit, line))
+ assert False
+
+ for i in range(len(raw_db)):
+ if raw_db[i][1][0] == "routing" and (raw_db[i][1][1], raw_db[i][1][2]) in route_to_buffer:
+ if raw_db[i][1][1] in add_mux_bits:
+ for entry in add_mux_bits[raw_db[i][1][1]]:
+ raw_db.append(entry)
+ raw_db[i] = (raw_db[i][0], ("buffer", raw_db[i][1][1], raw_db[i][1][2]))
+
+ func_to_bits = dict()
+ for entry in raw_db:
+ func_to_bits.setdefault(entry[1], set()).add(entry[0])
+
+ bit_groups = dict()
+ for func, bits in func_to_bits.items():
+ for bit in bits:
+ bit_groups[bit] = bit_groups.setdefault(bit, set()).union(bits)
+
+ for func in func_to_bits:
+ new_bits = set()
+ for bit2 in func_to_bits[func]:
+ for bit in bit_groups[bit2]:
+ if bit in func_to_bits[func]:
+ new_bits.add(bit)
+ else:
+ new_bits.add("!" + bit)
+ func_to_bits[func] = new_bits
+
+ database = list()
+ for func in sorted(func_to_bits):
+ bits = func_to_bits[func]
+ entry = (",".join(sorted(bits, cmp_bits)),) + func
+ database.append(entry)
+
+ return database
+
+with open("database_io.txt", "w") as f:
+ for entry in read_database("bitdata_io.txt", "io"):
+ print("\t".join(entry), file=f)
+
+with open("database_logic.txt", "w") as f:
+ for entry in read_database("bitdata_logic.txt", "logic"):
+ print("\t".join(entry), file=f)
+
+with open("database_ramb.txt", "w") as f:
+ for entry in read_database("bitdata_ramb.txt", "ramb"):
+ print("\t".join(entry), file=f)
+
+with open("database_ramt.txt", "w") as f:
+ for entry in read_database("bitdata_ramt.txt", "ramt"):
+ print("\t".join(entry), file=f)
+
+with open("database_ramb_8k.txt", "w") as f:
+ for entry in read_database("bitdata_ramb_8k.txt", "ramb_8k"):
+ print("\t".join(entry), file=f)
+
+with open("database_ramt_8k.txt", "w") as f:
+ for entry in read_database("bitdata_ramt_8k.txt", "ramt_8k"):
+ print("\t".join(entry), file=f)
+
diff --git a/icefuzz/export.py b/icefuzz/export.py
new file mode 100644
index 0000000..dc1a66f
--- /dev/null
+++ b/icefuzz/export.py
@@ -0,0 +1,13 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+
+with open("../icebox/iceboxdb.py", "w") as f:
+ for i in [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ramb_8k", "database_ramt_8k" ]:
+ print('%s_txt = """' % i, file=f)
+ with open("%s.txt" % i, "r") as fi:
+ for line in fi:
+ print(line, end="", file=f)
+ print('"""', file=f)
+
diff --git a/icefuzz/extract.py b/icefuzz/extract.py
new file mode 100644
index 0000000..9fa8a8c
--- /dev/null
+++ b/icefuzz/extract.py
@@ -0,0 +1,60 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+import sys, re
+
+db = set()
+text_db = dict()
+mode_8k = False
+cur_text_db = None
+max_x, max_y = 0, 0
+
+if sys.argv[1] == '-8':
+ sys.argv = sys.argv[1:]
+ mode_8k = True
+
+for filename in sys.argv[1:]:
+ with open(filename, "r") as f:
+ for line in f:
+ if line == "\n":
+ pass
+ elif line.startswith("GlobalNetwork"):
+ cur_text_db = set()
+ elif line.startswith("IO"):
+ match = re.match("IO_Tile_(\d+)_(\d+)", line)
+ assert match
+ max_x = max(max_x, int(match.group(1)))
+ max_y = max(max_y, int(match.group(2)))
+ cur_text_db = text_db.setdefault("io", set())
+ elif line.startswith("Logic"):
+ cur_text_db = text_db.setdefault("logic", set())
+ elif line.startswith("RAM"):
+ match = re.match(r"RAM_Tile_\d+_(\d+)", line)
+ if int(match.group(1)) % 2 == 1:
+ cur_text_db = text_db.setdefault("ramb_8k" if mode_8k else "ramb", set())
+ else:
+ cur_text_db = text_db.setdefault("ramt_8k" if mode_8k else "ramt", set())
+ else:
+ assert line.startswith(" ")
+ cur_text_db.add(line)
+
+def logic_op_prefix(match):
+ x = int(match.group(1))
+ y = int(match.group(2))
+ if x == 0: return " IO_L.logic_op_"
+ if y == 0: return " IO_B.logic_op_"
+ if x == max_x: return " IO_R.logic_op_"
+ if y == max_y: return " IO_T.logic_op_"
+ assert False
+
+for tile_type in text_db:
+ for line in text_db[tile_type]:
+ line = re.sub(" T_(\d+)_(\d+)\.logic_op_", logic_op_prefix, line)
+ line = re.sub(" T_\d+_\d+\.", " ", line)
+ m = re.match(" *(\([\d ]+\)) +\([\d ]+\) +\([\d ]+\) +(.*\S)", line)
+ if m: db.add("%s %s %s" % (tile_type, m.group(1), m.group(2)))
+
+for line in sorted(db):
+ print(line)
+
diff --git a/icefuzz/fuzzconfig.py b/icefuzz/fuzzconfig.py
new file mode 100644
index 0000000..3a2a9e3
--- /dev/null
+++ b/icefuzz/fuzzconfig.py
@@ -0,0 +1,36 @@
+import os
+
+num = 20
+
+if os.getenv('ICE8KPINS'):
+ num_ramb40 = 32
+
+ pins="""
+ A1 A2 A5 A6 A7 A9 A10 A11 A15 A16
+ B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
+ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16
+ D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16
+ E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16
+ F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16
+ G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16
+ H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16
+ J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16
+ K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16
+ L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16
+ M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16
+ N2 N3 N4 N5 N6 N7 N9 N10 N12 N16
+ P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
+ R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16
+ T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16
+ """.split()
+
+else:
+ num_ramb40 = 16
+
+ pins = """
+ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64
+ 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144
+ """.split()
+
diff --git a/icefuzz/glbmapbits.py b/icefuzz/glbmapbits.py
new file mode 100644
index 0000000..c971088
--- /dev/null
+++ b/icefuzz/glbmapbits.py
@@ -0,0 +1,34 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+
+import re
+import fileinput
+
+tiletype = ""
+x, y = 0, 0
+
+for line in fileinput.input():
+ if line.startswith("LogicTile"):
+ fields = line.split("_")
+ tiletype = "Logic"
+ x, y = int(fields[1]), int(fields[2])
+ continue
+
+ if line.startswith("RAM_Tile") or line.startswith("IO_Tile"):
+ fields = line.split("_")
+ tiletype = fields[0]
+ x, y = int(fields[2]), int(fields[3])
+ continue
+
+ if line.startswith("GlobalNetwork"):
+ tiletype = ""
+ continue
+
+ if tiletype != "":
+ fields = re.split('[ ()]*', line.strip())
+ if len(fields) <= 1: continue
+ fields = [int(fields[i+1]) for i in range(4)]
+ print("%-5s %2d %2d %2d %2d %3d %3d" % (tiletype, x, y, fields[0], fields[1], fields[2], fields[3]))
+
diff --git a/icefuzz/icecube.sh b/icefuzz/icecube.sh
new file mode 100644
index 0000000..fddaa3c
--- /dev/null
+++ b/icefuzz/icecube.sh
@@ -0,0 +1,190 @@
+#!/bin/bash
+#
+# Installing iCEcube2:
+# - Install iCEcube2.2014.08 in /opt/lscc/iCEcube2.2014.08
+# - Install License in /opt/lscc/iCEcube2.2014.08/license.dat
+#
+# Creating a project:
+# - <project_name>.v ## HDL sources (use "top" as name for the top module)
+# - <project_name>.sdc ## timing constraint file
+# - <project_name>.pcf ## physical constraint file
+#
+# Running iCEcube2:
+# - bash icecuberun.sh <project_name> ## creates <project_name>.bin
+#
+#
+#
+# Additional notes for installing iCEcube2 on 64 Bit Ubuntu:
+#
+# sudo apt-get install ibc6-i386 zlib1g:i386 libxext6:i386 libpng12-0:i386 libsm6:i386
+# sudo apt-get install libxi6:i386 libxrender1:i386 libxrandr2:i386 libxfixes3:i386
+# sudo apt-get install libxcursor1:i386 libXinerama.so.1:i386 libXinerama1:i386 libfreetype6:i386
+# sudo apt-get install libfontconfig1:i386 libglib2.0-0:i386 libstdc++6:i386 libelf1:i386
+#
+# icecubedir="/opt/lscc/iCEcube2.2014.08"
+# sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/synplify_pro
+# sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/c_hdl
+# sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/syn_nfilter
+# sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/m_generic
+#
+
+scriptdir=${BASH_SOURCE%/*}
+if [ -z "$scriptdir" ]; then scriptdir="."; fi
+
+set -ex
+set -- ${1%.v}
+icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2014.08}"
+export SBT_DIR="$icecubedir/sbt_backend"
+export SYNPLIFY_PATH="$icecubedir/synpbase"
+export LM_LICENSE_FILE="$icecubedir/license.dat"
+export TCL_LIBRARY="$icecubedir/sbt_backend/bin/linux/lib/tcl8.4"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt/synpwrap"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/lib/linux/opt"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/lin"
+
+case "${ICEDEV:-hx1k-tq144}" in
+ hx1k-cb132)
+ iCEPACKAGE="CB132"
+ iCE40DEV="iCE40HX1K"
+ ;;
+ hx1k-vq100)
+ iCEPACKAGE="VQ100"
+ iCE40DEV="iCE40HX1K"
+ ;;
+ hx1k-tq144)
+ iCEPACKAGE="TQ144"
+ iCE40DEV="iCE40HX1K"
+ ;;
+ hx8k-cm225)
+ iCEPACKAGE="CM225"
+ iCE40DEV="iCE40HX8K"
+ ;;
+ hx8k-ct256)
+ iCEPACKAGE="CT256"
+ iCE40DEV="iCE40HX8K"
+ ;;
+ hx8k-cb132)
+ iCEPACKAGE="CB132"
+ iCE40DEV="iCE40HX8K"
+ ;;
+ *)
+ echo "ERROR: Invalid \$ICEDEV device config '$ICEDEV'."
+ exit 1
+esac
+
+case "$iCE40DEV" in
+ iCE40HX1K)
+ libfile="ice40HX1K.lib"
+ devfile="ICE40P01.dev"
+ ;;
+ iCE40HX8K)
+ libfile="ice40HX8K.lib"
+ devfile="ICE40P08.dev"
+ ;;
+esac
+
+(
+rm -rf "$1.tmp"
+mkdir -p "$1.tmp"
+cp "$1.v" "$1.tmp/input.v"
+if test -f "$1.sdc"; then cp "$1.sdc" "$1.tmp/input.sdc"; fi
+if test -f "$1.pcf"; then cp "$1.pcf" "$1.tmp/input.pcf"; fi
+cd "$1.tmp"
+
+touch input.sdc
+touch input.pcf
+
+mkdir -p outputs/packer
+mkdir -p outputs/placer
+mkdir -p outputs/router
+mkdir -p outputs/bitmap
+mkdir -p outputs/netlist
+mkdir -p netlist/Log/bitmap
+
+cat > impl_syn.prj << EOT
+add_file -verilog -lib work input.v
+impl -add impl -type fpga
+
+# implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+# device options
+set_option -technology SBTiCE40
+set_option -part $iCE40DEV
+set_option -package $iCEPACKAGE
+set_option -speed_grade
+set_option -part_companion ""
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+# set result format/file last
+project -result_format edif
+project -result_file impl.edf
+impl -active impl
+project -run synthesis -clean
+EOT
+
+try_rerun() {
+ for i in {0..3}; do
+ if "$@"; then return 0; fi
+ done
+ return 1
+}
+
+# synthesis
+"$icecubedir"/sbt_backend/bin/linux/opt/synpwrap/synpwrap -prj impl_syn.prj -log impl.srr
+
+# convert netlist
+"$icecubedir"/sbt_backend/bin/linux/opt/edifparser "$icecubedir"/sbt_backend/devices/$devfile impl/impl.edf netlist -p$iCEPACKAGE -yinput.pcf -sinput.sdc -c --devicename $iCE40DEV
+
+# run placer
+try_rerun "$icecubedir"/sbt_backend/bin/linux/opt/sbtplacer --des-lib netlist/oadb-top --outdir outputs/placer --device-file "$icecubedir"/sbt_backend/devices/$devfile --package $iCEPACKAGE --deviceMarketName $iCE40DEV --sdc-file netlist/Temp/sbt_temp.sdc --lib-file "$icecubedir"/sbt_backend/devices/$libfile --effort_level std --out-sdc-file outputs/placer/top_pl.sdc
+
+# run packer
+"$icecubedir"/sbt_backend/bin/linux/opt/packer "$icecubedir"/sbt_backend/devices/$devfile netlist/oadb-top --package $iCEPACKAGE --outdir outputs/packer --translator "$icecubedir"/sbt_backend/bin/sdc_translator.tcl --src_sdc_file outputs/placer/top_pl.sdc --dst_sdc_file outputs/packer/top_pk.sdc --devicename $iCE40DEV
+
+# run router
+"$icecubedir"/sbt_backend/bin/linux/opt/sbrouter "$icecubedir"/sbt_backend/devices/$devfile netlist/oadb-top "$icecubedir"/sbt_backend/devices/$libfile outputs/packer/top_pk.sdc --outdir outputs/router --sdf_file outputs/simulation_netlist/top_sbt.sdf --pin_permutation
+
+# run netlister
+"$icecubedir"/sbt_backend/bin/linux/opt/netlister --verilog outputs/netlist/top_sbt.v --vhdl outputs/netlist/top_sbt.vhd --lib netlist/oadb-top --view rt --device "$icecubedir"/sbt_backend/devices/$devfile --splitio --in-sdc-file outputs/packer/top_pk.sdc --out-sdc-file netlister/top_sbt.sdc
+
+# make bitmap
+"$icecubedir"/sbt_backend/bin/linux/opt/bitmap "$icecubedir"/sbt_backend/devices/$devfile --design netlist/oadb-top --device_name $iCE40DEV --package $iCEPACKAGE --outdir outputs/bitmap --debug --low_power on --init_ram on --init_ram_bank 1111 --frequency low --warm_boot on
+)
+
+cp "$1.tmp"/outputs/bitmap/top_bitmap.bin "$1.bin"
+cp "$1.tmp"/outputs/bitmap/top_bitmap_glb.txt "$1.glb"
+cp "$1.tmp"/outputs/placer/top_sbt.pcf "$1.psb"
+cp "$1.tmp"/outputs/netlist/top_sbt.v "$1.vsb"
+$scriptdir/../icepack/iceunpack "$1.bin" "$1.txt"
+
diff --git a/icefuzz/make_binop.py b/icefuzz/make_binop.py
new file mode 100644
index 0000000..ac7740c
--- /dev/null
+++ b/icefuzz/make_binop.py
@@ -0,0 +1,28 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_binop")
+os.mkdir("work_binop")
+
+for idx in range(num):
+ with open("work_binop/binop_%02d.v" % idx, "w") as f:
+ print("module top(input a, b, output y);", file=f)
+ print(" assign y = a%sb;" % np.random.choice([" ^ ", " ^ ~", " & ", " & ~", " | ", " | ~"]), file=f)
+ print("endmodule", file=f)
+ with open("work_binop/binop_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ print("set_io a %s" % p[0], file=f)
+ print("set_io b %s" % p[1], file=f)
+ print("set_io y %s" % p[2], file=f)
+
+with open("work_binop/Makefile", "w") as f:
+ print("all: %s" % " ".join(["binop_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("binop_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh binop_%02d > binop_%02d.log 2>&1 && rm -rf binop_%02d.tmp || tail binop_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_cluster.py b/icefuzz/make_cluster.py
new file mode 100644
index 0000000..a2af710
--- /dev/null
+++ b/icefuzz/make_cluster.py
@@ -0,0 +1,29 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_cluster")
+os.mkdir("work_cluster")
+
+for idx in range(num):
+ with open("work_cluster/cluster_%02d.v" % idx, "w") as f:
+ print("module top(input [3:0] a, output [3:0] y);", file=f)
+ print(" assign y = {|a, &a, ^a, a[3:2] == a[1:0]};", file=f)
+ print("endmodule", file=f)
+ with open("work_cluster/cluster_%02d.pcf" % idx, "w") as f:
+ i = np.random.randint(len(pins))
+ netnames = np.random.permutation(["a[%d]" % i for i in range(4)] + ["y[%d]" % i for i in range(4)])
+ for net in netnames:
+ print("set_io %s %s" % (net, pins[i]), file=f)
+ i = (i + 1) % len(pins)
+
+with open("work_cluster/Makefile", "w") as f:
+ print("all: %s" % " ".join(["cluster_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("cluster_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh cluster_%02d > cluster_%02d.log 2>&1 && rm -rf cluster_%02d.tmp || tail cluster_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_fanout.py b/icefuzz/make_fanout.py
new file mode 100644
index 0000000..aceffe8
--- /dev/null
+++ b/icefuzz/make_fanout.py
@@ -0,0 +1,29 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_fanout")
+os.mkdir("work_fanout")
+
+for idx in range(num):
+ with open("work_fanout/fanout_%02d.v" % idx, "w") as f:
+ print("module top(input [1:0] a, output [63:0] y);", file=f)
+ print(" assign y = {32{a}};", file=f)
+ print("endmodule", file=f)
+ with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ for i in range(64):
+ print("set_io y[%d] %s" % (i, p[i]), file=f)
+ print("set_io a[0] %s" % p[64], file=f)
+ print("set_io a[1] %s" % p[65], file=f)
+
+with open("work_fanout/Makefile", "w") as f:
+ print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("fanout_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh fanout_%02d > fanout_%02d.log 2>&1 && rm -rf fanout_%02d.tmp || tail fanout_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_fflogic.py b/icefuzz/make_fflogic.py
new file mode 100644
index 0000000..9bc2c5d
--- /dev/null
+++ b/icefuzz/make_fflogic.py
@@ -0,0 +1,54 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_fflogic")
+os.mkdir("work_fflogic")
+
+def random_op():
+ return np.random.choice(["+", "-", "*", "^", "&", "|"])
+
+def print_seq_op(dst, src1, src2, op, f):
+ mode = np.random.choice(list("abc"))
+ negreset = np.random.choice(["!", ""])
+ enable = np.random.choice(["if (en) ", ""])
+ if mode == "a":
+ print(" always @(%sedge clk) begin" % np.random.choice(["pos", "neg"]), file=f)
+ print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f)
+ print(" end", file=f)
+ elif mode == "b":
+ print(" always @(%sedge clk) begin" % np.random.choice(["pos", "neg"]), file=f)
+ print(" if (%srst)" % negreset, file=f)
+ print(" %s <= %d;" % (dst, np.random.randint(2**16)), file=f)
+ print(" else", file=f)
+ print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f)
+ print(" end", file=f)
+ elif mode == "c":
+ print(" always @(%sedge clk, %sedge rst) begin" % (np.random.choice(["pos", "neg"]), "neg" if negreset == "!" else "pos"), file=f)
+ print(" if (%srst)" % negreset, file=f)
+ print(" %s <= %d;" % (dst, np.random.randint(2**16)), file=f)
+ print(" else", file=f)
+ print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f)
+ print(" end", file=f)
+ else:
+ assert False
+
+for idx in range(num):
+ with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f:
+ print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f)
+ print(" reg [15:0] p, q;", file=f)
+ print_seq_op("p", "a", "b", random_op(), f)
+ print_seq_op("q", "c", "d", random_op(), f)
+ print(" assign y = p %s q, z = clk ^ rst ^ en;" % random_op(), file=f)
+ print("endmodule", file=f)
+
+with open("work_fflogic/Makefile", "w") as f:
+ print("all: %s" % " ".join(["fflogic_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("fflogic_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh fflogic_%02d > fflogic_%02d.log 2>&1 && rm -rf fflogic_%02d.tmp || tail fflogic_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_gbio.py b/icefuzz/make_gbio.py
new file mode 100644
index 0000000..8f08202
--- /dev/null
+++ b/icefuzz/make_gbio.py
@@ -0,0 +1,84 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_gbio")
+os.mkdir("work_gbio")
+
+for idx in range(num):
+ with open("work_gbio/gbio_%02d.v" % idx, "w") as f:
+ glbs = np.random.permutation(range(8))
+ print("""
+ module top (
+ inout [7:0] pin,
+ input latch_in,
+ input clk_en,
+ input clk_in,
+ input clk_out,
+ input oen,
+ input dout_0,
+ input dout_1,
+ output [7:0] din_0,
+ output [7:0] din_1,
+ output [7:0] globals,
+ output reg q
+ );
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 1100_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) PINS [7:0] (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(%s),
+ .CLOCK_ENABLE(%s),
+ .INPUT_CLK(%s),
+ .OUTPUT_CLK(%s),
+ .OUTPUT_ENABLE(%s),
+ .D_OUT_0(%s),
+ .D_OUT_1(%s),
+ .D_IN_0(%s),
+ .D_IN_1(%s),
+ .GLOBAL_BUFFER_OUTPUT(%s)
+ );
+
+ always @(posedge globals[%d], posedge globals[%d])
+ if (globals[%d])
+ q <= 0;
+ else if (globals[%d])
+ q <= globals[%d];
+ endmodule
+ """ % (
+ np.random.choice(["latch_in", "globals", "din_0+din_1", "din_0^din_1"]),
+ np.random.choice(["clk_en", "globals", "din_0+din_1", "din_0^din_1"]),
+ np.random.choice(["clk_in", "globals", "din_0+din_1", "din_0^din_1"]),
+ np.random.choice(["clk_out", "globals", "din_0+din_1", "din_0^din_1"]),
+ np.random.choice(["oen", "globals", "din_0+din_1", "din_0^din_1"]),
+ np.random.choice(["dout_1", "globals", "globals^dout_0", "din_0+din_1", "~din_0"]),
+ np.random.choice(["dout_0", "globals", "globals^dout_1", "din_0+din_1", "~din_1"]),
+ np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]),
+ np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]),
+ np.random.choice(["globals", "{globals[0], globals[7:1]}"]),
+ glbs[0], glbs[1], glbs[1], glbs[2], glbs[3]
+ ), file=f)
+ with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ for i in range(8):
+ print("set_io pin[%d] %s" % (i, p[i]), file=f)
+ print("set_io din_0[%d] %s" % (i, p[8+i]), file=f)
+ print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f)
+ print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f)
+ for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()):
+ print("set_io %s %s" % (n, p[4*8+i]), file=f)
+ print("set_io q %s" % (p[-1]), file=f)
+
+with open("work_gbio/Makefile", "w") as f:
+ print("all: %s" % " ".join(["gbio_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("gbio_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh gbio_%02d > gbio_%02d.log 2>&1 && rm -rf gbio_%02d.tmp || tail gbio_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_gbio2.py b/icefuzz/make_gbio2.py
new file mode 100644
index 0000000..bd8158a
--- /dev/null
+++ b/icefuzz/make_gbio2.py
@@ -0,0 +1,83 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_gbio2")
+os.mkdir("work_gbio2")
+
+for idx in range(num):
+ with open("work_gbio2/gbio2_%02d.v" % idx, "w") as f:
+ glbs = np.random.permutation(range(8))
+ print("""
+ module top (
+ inout [7:0] pin,
+ input latch_in,
+ input clk_en,
+ input clk_in,
+ input clk_out,
+ input oen,
+ input dout_0,
+ input dout_1,
+ output [7:0] din_0,
+ output [7:0] din_1,
+ output [7:0] globals,
+ output reg q
+ );
+ """, file=f);
+ for k in range(8):
+ print("""
+ SB_GB_IO #(
+ .PIN_TYPE(6'b %s),
+ .PULLUP(1'b %s),
+ .NEG_TRIGGER(1'b %s),
+ .IO_STANDARD("SB_LVCMOS")
+ ) \pin[%d]_gb_io (
+ .PACKAGE_PIN(pin[%d]),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(clk_en),
+ .INPUT_CLK(clk_in),
+ .OUTPUT_CLK(clk_out),
+ .OUTPUT_ENABLE(oen),
+ .D_OUT_0(dout_0),
+ .D_OUT_1(dout_1),
+ .D_IN_0(din_0[%d]),
+ .D_IN_1(din_1[%d]),
+ .GLOBAL_BUFFER_OUTPUT(globals[%d])
+ );
+ """ % (
+ np.random.choice(["1100_00", "1010_10", "1010_00", "0000_11", "1111_00"]),
+ np.random.choice(["0", "1"]),
+ np.random.choice(["0", "1"]),
+ k, k, k, k, k
+ ), file=f)
+ print("""
+ always @(posedge globals[%d], posedge globals[%d])
+ if (globals[%d])
+ q <= 0;
+ else if (globals[%d])
+ q <= globals[%d];
+ endmodule
+ """ % (
+ glbs[0], glbs[1], glbs[1], glbs[2], glbs[3]
+ ), file=f)
+ with open("work_gbio2/gbio2_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ for i in range(8):
+ print("set_io pin[%d] %s" % (i, p[i]), file=f)
+ print("set_io din_0[%d] %s" % (i, p[8+i]), file=f)
+ print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f)
+ print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f)
+ for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()):
+ print("set_io %s %s" % (n, p[4*8+i]), file=f)
+ print("set_io q %s" % (p[-1]), file=f)
+
+with open("work_gbio2/Makefile", "w") as f:
+ print("all: %s" % " ".join(["gbio2_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("gbio2_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh gbio2_%02d > gbio2_%02d.log 2>&1 && rm -rf gbio2_%02d.tmp || tail gbio2_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_io.py b/icefuzz/make_io.py
new file mode 100644
index 0000000..60d967b
--- /dev/null
+++ b/icefuzz/make_io.py
@@ -0,0 +1,61 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_io")
+os.mkdir("work_io")
+
+for idx in range(num):
+ with open("work_io/io_%02d.v" % idx, "w") as f:
+ glbs = np.random.permutation(range(8))
+ print("""
+ module top (
+ inout [3:0] pin,
+ input [3:0] latch_in,
+ input [3:0] clk_en,
+ input [3:0] clk_in,
+ input [3:0] clk_out,
+ input [3:0] oen,
+ input [3:0] dout_0,
+ input [3:0] dout_1,
+ output [3:0] din_0,
+ output [3:0] din_1
+ );
+ SB_IO #(
+ .PIN_TYPE(6'b %s_%s),
+ .PULLUP(1'b %s),
+ .NEG_TRIGGER(1'b %s),
+ .IO_STANDARD("SB_LVCMOS")
+ ) PINS [3:0] (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(clk_en),
+ .INPUT_CLK(clk_in),
+ .OUTPUT_CLK(clk_out),
+ .OUTPUT_ENABLE(oen),
+ .D_OUT_0(dout_0),
+ .D_OUT_1(dout_1),
+ .D_IN_0(din_0),
+ .D_IN_1(din_1)
+ );
+ endmodule
+ """ % (
+ np.random.choice(["0000", "0110", "1010", "1110", "0101", "1001", "1101", "0100", "1000", "1100", "0111", "1111"]),
+ np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"])
+ ), file=f)
+ with open("work_io/io_%02d.pcf" % idx, "w") as f:
+ p = list(np.random.permutation(pins))
+ for k in ["pin", "latch_in", "clk_en", "clk_in", "clk_out", "oen", "dout_0", "dout_1", "din_0", "din_1"]:
+ for i in range(4):
+ print("set_io %s[%d] %s" % (k, i, p.pop()), file=f)
+
+with open("work_io/Makefile", "w") as f:
+ print("all: %s" % " ".join(["io_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("io_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh io_%02d > io_%02d.log 2>&1 && rm -rf io_%02d.tmp || tail io_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_iopack.py b/icefuzz/make_iopack.py
new file mode 100644
index 0000000..1ad41ee
--- /dev/null
+++ b/icefuzz/make_iopack.py
@@ -0,0 +1,59 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+from numpy.random import randint, choice, permutation
+
+num_xor = 8
+num_luts = 8
+num_outputs_range = (5, 20)
+
+os.system("rm -rf work_iopack")
+os.mkdir("work_iopack")
+
+def get_pin_directions():
+ pindirs = ["i" for i in range(len(pins))]
+ for i in range(randint(num_outputs_range[0], num_outputs_range[1])):
+ pindirs[randint(len(pins))] = "o"
+ return pindirs
+
+def get_nearby_inputs(p, n, r):
+ while True:
+ ipins = list()
+ for i in range(-r, +r):
+ ip = (p + i + len(pins)) % len(pins)
+ if pindirs[ip] == "i":
+ ipins.append(ip)
+ if len(ipins) >= n:
+ break
+ r += 4
+ return [choice(ipins) for i in range(n)]
+
+for idx in range(num):
+ with open("work_iopack/iopack_%02d.v" % idx, "w") as f:
+ pindirs = get_pin_directions()
+ print("module top(%s);" % ", ".join(["%sput p%d" % ("in" if pindirs[i] == "i" else "out", i) for i in range(len(pins))]), file=f)
+ for outp in range(len(pins)):
+ if pindirs[outp] == "o":
+ xor_nets = set(["%sp%d" % (choice(["~", ""]), p) for p in get_nearby_inputs(outp, num_xor, 2 + randint(10))])
+ for i in range(num_luts):
+ print(" localparam [15:0] p%d_lut%d = 16'd %d;" % (outp, i, randint(2**16)), file=f)
+ print(" wire p%d_in%d = p%d_lut%d >> {%s};" % (outp, i, outp, i,
+ ", ".join(["p%d" % p for p in get_nearby_inputs(outp + randint(-10, +11), 4, 4)])), file=f)
+ xor_nets.add("%sp%d_in%d" % (choice(["~", ""]), outp, i))
+ print(" assign p%d = ^{%s};" % (outp, ", ".join(sorted(xor_nets))), file=f)
+ print("endmodule", file=f)
+ with open("work_iopack/iopack_%02d.pcf" % idx, "w") as f:
+ for i in range(len(pins)):
+ print("set_io p%d %s" % (i, pins[i]), file=f)
+
+with open("work_iopack/Makefile", "w") as f:
+ print("all: %s" % " ".join(["iopack_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("iopack_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh iopack_%02d > iopack_%02d.log 2>&1 && rm -rf iopack_%02d.tmp || tail iopack_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_logic.py b/icefuzz/make_logic.py
new file mode 100644
index 0000000..69a5641
--- /dev/null
+++ b/icefuzz/make_logic.py
@@ -0,0 +1,34 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_logic")
+os.mkdir("work_logic")
+
+def random_op():
+ return np.random.choice(["+", "-", "^", "&", "|", "&~", "|~"])
+
+for idx in range(num):
+ with open("work_logic/logic_%02d.v" % idx, "w") as f:
+ print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f)
+ print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f)
+ print("endmodule", file=f)
+ with open("work_logic/logic_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ for i in range(16):
+ print("set_io a[%d] %s" % (i, p[i]), file=f)
+ print("set_io b[%d] %s" % (i, p[i+16]), file=f)
+ print("set_io c[%d] %s" % (i, p[i+32]), file=f)
+ print("set_io d[%d] %s" % (i, p[i+48]), file=f)
+ print("set_io y[%d] %s" % (i, p[i+64]), file=f)
+
+with open("work_logic/Makefile", "w") as f:
+ print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("logic_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh logic_%02d > logic_%02d.log 2>&1 && rm -rf logic_%02d.tmp || tail logic_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_mesh.py b/icefuzz/make_mesh.py
new file mode 100644
index 0000000..c3da800
--- /dev/null
+++ b/icefuzz/make_mesh.py
@@ -0,0 +1,29 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_mesh")
+os.mkdir("work_mesh")
+
+for idx in range(num):
+ with open("work_mesh/mesh_%02d.v" % idx, "w") as f:
+ print("module top(input [39:0] a, output [39:0] y);", file=f)
+ print(" assign y = a;", file=f)
+ print("endmodule", file=f)
+ with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ for i in range(40):
+ print("set_io a[%d] %s" % (i, p[i]), file=f)
+ for i in range(40):
+ print("set_io y[%d] %s" % (i, p[40+i]), file=f)
+
+with open("work_mesh/Makefile", "w") as f:
+ print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("mesh_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh mesh_%02d > mesh_%02d.log 2>&1 && rm -rf mesh_%02d.tmp || tail mesh_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_pin2pin.py b/icefuzz/make_pin2pin.py
new file mode 100644
index 0000000..34e40cd
--- /dev/null
+++ b/icefuzz/make_pin2pin.py
@@ -0,0 +1,27 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_pin2pin")
+os.mkdir("work_pin2pin")
+
+for idx in range(num):
+ with open("work_pin2pin/pin2pin_%02d.v" % idx, "w") as f:
+ print("module top(input a, output y);", file=f)
+ print(" assign y = a;", file=f)
+ print("endmodule", file=f)
+ with open("work_pin2pin/pin2pin_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ print("set_io a %s" % p[0], file=f)
+ print("set_io y %s" % p[1], file=f)
+
+with open("work_pin2pin/Makefile", "w") as f:
+ print("all: %s" % " ".join(["pin2pin_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("pin2pin_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh pin2pin_%02d > pin2pin_%02d.log 2>&1 && rm -rf pin2pin_%02d.tmp || tail pin2pin_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_pll.py b/icefuzz/make_pll.py
new file mode 100644
index 0000000..93a168a
--- /dev/null
+++ b/icefuzz/make_pll.py
@@ -0,0 +1,139 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+import numpy as np
+import os
+
+from numpy.random import randint, choice, permutation
+
+def randbin(n):
+ return "".join([choice(["0", "1"]) for i in range(n)])
+
+num = 20
+
+pins = [int(i) for i in """
+ 1 2 3 4 7 8 9 10 11 12 19 20 21 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 39 41 42 43 44 45 47 48 49 50 52 56 58 60 61 62 63 64 67 68 70 71
+ 73 74 75 76 78 79 80 81 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 128 129 134 135 136 137 138 139 141 142 143 144
+""".split()]
+
+pins.remove(49)
+pins.remove(50)
+
+os.system("rm -rf work_pll")
+os.mkdir("work_pll")
+
+for idx in range(num):
+ pin_names = list()
+ vlog_body = list()
+ pll_inst = list()
+
+ pll_type = choice(["SB_PLL40_CORE", "SB_PLL40_2F_CORE", "SB_PLL40_PAD", "SB_PLL40_2_PAD", "SB_PLL40_2F_PAD"])
+
+ pll_inst.append("%s uut (" % pll_type)
+
+ if pll_type.endswith("_PAD"):
+ pin_names.append("packagepin")
+ vlog_body.append("input packagepin;")
+ pll_inst.append(" .PACKAGEPIN(packagepin),")
+ else:
+ pin_names.append("referenceclk")
+ vlog_body.append("input referenceclk;")
+ pll_inst.append(" .REFERENCECLK(referenceclk),")
+
+ for pin in ["a", "b"]:
+ pin_names.append(pin)
+ vlog_body.append("input %s;" % pin)
+
+ for pin in ["w", "x", "y", "z"]:
+ pin_names.append(pin)
+ vlog_body.append("output %s%s;" % ("reg " if pin in ["y", "z"] else "", pin))
+
+ for pin in ["EXTFEEDBACK", "BYPASS", "RESETB", "LOCK", "LATCHINPUTVALUE", "SDI", "SDO", "SCLK"]:
+ pin_names.append(pin.lower())
+ vlog_body.append("%sput %s;" % ("out" if pin in ["LOCK", "SDO"] else "in", pin.lower()))
+ pll_inst.append(" .%s(%s)," % (pin, pin.lower()))
+
+ if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0:
+ for pin in ["PLLOUTCORE", "PLLOUTGLOBAL"]:
+ vlog_body.append("wire %s;" % pin.lower())
+ pll_inst.append(" .%s(%s)," % (pin, pin.lower()))
+ vlog_body.append("assign w = plloutcore ^ a;")
+ vlog_body.append("assign x = plloutcore ^ b;")
+ vlog_body.append("always @(posedge plloutglobal) y <= a;")
+ vlog_body.append("always @(posedge plloutglobal) z <= b;")
+ else:
+ for pin in ["PLLOUTCOREA", "PLLOUTCOREB", "PLLOUTGLOBALA", "PLLOUTGLOBALB"]:
+ vlog_body.append("wire %s;" % pin.lower())
+ pll_inst.append(" .%s(%s)," % (pin, pin.lower()))
+ vlog_body.append("assign w = plloutcorea ^ a;")
+ vlog_body.append("assign x = plloutcoreb ^ b;")
+ vlog_body.append("always @(posedge plloutglobala) y <= a;")
+ vlog_body.append("always @(posedge plloutglobalb) z <= b;")
+
+ for i in range(8):
+ pin_names.append("dynamicdelay_%d" % i)
+ vlog_body.append("input dynamicdelay_%d;" % i)
+ pll_inst.append(" .DYNAMICDELAY({%s})" % ", ".join(["dynamicdelay_%d" % i for i in range(7, -1, -1)]))
+ pll_inst.append(");")
+
+ divq = randbin(3)
+ if divq == "000": divq = "001"
+ if divq == "111": divq = "110"
+ pll_inst.append("defparam uut.DIVR = 4'b%s;" % randbin(4))
+ pll_inst.append("defparam uut.DIVF = 7'b%s;" % randbin(7))
+ pll_inst.append("defparam uut.DIVQ = 3'b%s;" % divq)
+ pll_inst.append("defparam uut.FILTER_RANGE = 3'b%s;" % randbin(3))
+ pll_inst.append("defparam uut.FEEDBACK_PATH = \"%s\";" % choice(["DELAY", "SIMPLE", "PHASE_AND_DELAY", "EXTERNAL"]))
+
+ if choice([True, False]):
+ pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_FEEDBACK = \"FIXED\";")
+ pll_inst.append("defparam uut.FDA_FEEDBACK = 4'b%s;" % randbin(4))
+ else:
+ pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_FEEDBACK = \"DYNAMIC\";")
+ pll_inst.append("defparam uut.FDA_FEEDBACK = 4'b1111;")
+
+ if choice([True, False]):
+ pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_RELATIVE = \"FIXED\";")
+ pll_inst.append("defparam uut.FDA_RELATIVE = 4'b%s;" % randbin(4))
+ else:
+ pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_RELATIVE = \"DYNAMIC\";")
+ pll_inst.append("defparam uut.FDA_RELATIVE = 4'b1111;")
+
+ pll_inst.append("defparam uut.SHIFTREG_DIV_MODE = 1'b%s;" % randbin(1))
+
+ if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0:
+ pll_inst.append("defparam uut.PLLOUT_SELECT = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"]))
+ elif pll_type.find("_2F_") < 0:
+ pll_inst.append("defparam uut.PLLOUT_SELECT_PORTB = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"]))
+ else:
+ pll_inst.append("defparam uut.PLLOUT_SELECT_PORTA = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"]))
+ pll_inst.append("defparam uut.PLLOUT_SELECT_PORTB = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"]))
+
+ if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0:
+ pll_inst.append("defparam uut.ENABLE_ICEGATE = 1'b0;")
+ else:
+ pll_inst.append("defparam uut.ENABLE_ICEGATE_PORTA = 1'b0;")
+ pll_inst.append("defparam uut.ENABLE_ICEGATE_PORTB = 1'b0;")
+
+ pll_inst.append("defparam uut.TEST_MODE = 1'b0;")
+
+ with open("work_pll/pll_%02d.v" % idx, "w") as f:
+ print("module top(%s);" % ", ".join(pin_names), file=f)
+ print("\n".join(vlog_body), file=f)
+ print("\n".join(pll_inst), file=f)
+ print("endmodule", file=f)
+
+ with open("work_pll/pll_%02d.pcf" % idx, "w") as f:
+ for pll_pin, package_pin in zip(pin_names, list(permutation(pins))[0:len(pin_names)]):
+ if pll_pin == "packagepin": package_pin = 49
+ print("set_io %s %d" % (pll_pin, package_pin), file=f)
+
+with open("work_pll/Makefile", "w") as f:
+ print("all: %s" % " ".join(["pll_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("pll_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh pll_%02d > pll_%02d.log 2>&1 && rm -rf pll_%02d.tmp || tail pll_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_prim.py b/icefuzz/make_prim.py
new file mode 100644
index 0000000..54dc538
--- /dev/null
+++ b/icefuzz/make_prim.py
@@ -0,0 +1,51 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_prim")
+os.mkdir("work_prim")
+
+for idx in range(num):
+ with open("work_prim/prim_%02d.v" % idx, "w") as f:
+ clkedge = np.random.choice(["pos", "neg"])
+ print("module top(input clk, input [23:0] a, b, output reg x, output reg [23:0] y);", file=f)
+ print(" reg [23:0] aa, bb;", file=f)
+ print(" always @(%sedge clk) aa <= a;" % clkedge, file=f)
+ print(" always @(%sedge clk) bb <= b;" % clkedge, file=f)
+ if np.random.choice([True, False]):
+ print(" always @(%sedge clk) x <= %s%s;" % (clkedge, np.random.choice(["^", "&", "|", "!"]), np.random.choice(["a", "b", "y"])), file=f)
+ else:
+ print(" always @(%sedge clk) x <= a%sb;" % (clkedge, np.random.choice(["&&", "||"])), file=f)
+ if np.random.choice([True, False]):
+ print(" always @(%sedge clk) y <= a%sb;" % (clkedge, np.random.choice(["+", "-", "&", "|"])), file=f)
+ else:
+ print(" always @(%sedge clk) y <= %s%s;" % (clkedge, np.random.choice(["~", "-", ""]), np.random.choice(["a", "b"])), file=f)
+ print("endmodule", file=f)
+ with open("work_prim/prim_%02d.pcf" % idx, "w") as f:
+ p = np.random.permutation(pins)
+ if np.random.choice([True, False]):
+ for i in range(24):
+ print("set_io a[%d] %s" % (i, p[i]), file=f)
+ if np.random.choice([True, False]):
+ for i in range(24):
+ print("set_io b[%d] %s" % (i, p[24+i]), file=f)
+ if np.random.choice([True, False]):
+ for i in range(24):
+ print("set_io y[%d] %s" % (i, p[2*24+i]), file=f)
+ if np.random.choice([True, False]):
+ print("set_io x %s" % p[3*24], file=f)
+ if np.random.choice([True, False]):
+ print("set_io y %s" % p[3*24+1], file=f)
+ if np.random.choice([True, False]):
+ print("set_io clk %s" % p[3*24+2], file=f)
+
+with open("work_prim/Makefile", "w") as f:
+ print("all: %s" % " ".join(["prim_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("prim_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh prim_%02d > prim_%02d.log 2>&1 && rm -rf prim_%02d.tmp || tail prim_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/make_ram40.py b/icefuzz/make_ram40.py
new file mode 100644
index 0000000..0d3eb32
--- /dev/null
+++ b/icefuzz/make_ram40.py
@@ -0,0 +1,113 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+from fuzzconfig import *
+import numpy as np
+import os
+
+os.system("rm -rf work_ram40")
+os.mkdir("work_ram40")
+
+for idx in range(num):
+ with open("work_ram40/ram40_%02d.v" % idx, "w") as f:
+ glbs = ["glb[%d]" % i for i in range(np.random.randint(9))]
+ glbs_choice = ["wa", "ra", "msk", "wd", "we", "wce", "wc", "re", "rce", "rc"]
+ print("""
+ module top (
+ input [%d:0] glb_pins,
+ input [59:0] in_pins,
+ output [15:0] out_pins
+ );
+ wire [%d:0] glb, glb_pins;
+ SB_GB gbufs [%d:0] (
+ .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins),
+ .GLOBAL_BUFFER_OUTPUT(glb)
+ );
+ """ % (len(glbs)-1, len(glbs)-1, len(glbs)-1), file=f)
+ bits = ["in_pins[%d]" % i for i in range(60)]
+ bits = list(np.random.permutation(bits))
+ for i in range(num_ramb40):
+ tmp = list(np.random.permutation(bits))
+ rmode = np.random.randint(4)
+ if rmode == 3:
+ wmode = np.random.randint(1, 4)
+ else:
+ wmode = np.random.randint(4)
+ raddr_bits = (8, 9, 10, 11)[rmode]
+ waddr_bits = (8, 9, 10, 11)[wmode]
+ rdata_bits = (16, 8, 4, 2)[rmode]
+ wdata_bits = (16, 8, 4, 2)[wmode]
+ bits_waddr = [tmp.pop() for k in range(waddr_bits)]
+ bits_raddr = [tmp.pop() for k in range(raddr_bits)]
+ bits_mask = [tmp.pop() for k in range(16)]
+ bits_wdata = [tmp.pop() for k in range(wdata_bits)]
+ bit_we = tmp.pop()
+ bit_wclke = tmp.pop()
+ bit_wclk = tmp.pop()
+ bit_re = tmp.pop()
+ bit_rclke = tmp.pop()
+ bit_rclk = tmp.pop()
+ if len(glbs) != 0:
+ s = np.random.choice(glbs_choice)
+ glbs_choice.remove(s)
+ if s == "wa": bits_waddr[np.random.randint(len(bits_waddr))] = glbs.pop()
+ if s == "ra": bits_raddr[np.random.randint(len(bits_raddr))] = glbs.pop()
+ if s == "msk": bits_mask [np.random.randint(len(bits_mask ))] = glbs.pop()
+ if s == "wd": bits_wdata[np.random.randint(len(bits_wdata))] = glbs.pop()
+ if s == "we": bit_we = glbs.pop()
+ if s == "wce": bit_wclke = glbs.pop()
+ if s == "wc": bit_wclk = glbs.pop()
+ if s == "re": bit_re = glbs.pop()
+ if s == "rce": bit_rclke = glbs.pop()
+ if s == "rc": bit_rclk = glbs.pop()
+ bits_waddr = "{%s}" % ", ".join(bits_waddr)
+ bits_raddr = "{%s}" % ", ".join(bits_raddr)
+ bits_mask = "{%s}" % ", ".join(bits_mask)
+ bits_wdata = "{%s}" % ", ".join(bits_wdata)
+ if wmode != 0: bits_mask = ""
+ memtype = np.random.choice(["", "NR", "NW", "NRNW"])
+ wclksuffix = "N" if memtype in ["NW", "NRNW"] else ""
+ rclksuffix = "N" if memtype in ["NR", "NRNW"] else ""
+ print("""
+ wire [%d:0] rdata_%d;
+ SB_RAM40_4K%s #(
+ .READ_MODE(%d),
+ .WRITE_MODE(%d)
+ ) ram_%d (
+ .WADDR(%s),
+ .RADDR(%s),
+ .MASK(%s),
+ .WDATA(%s),
+ .RDATA(rdata_%d),
+ .WE(%s),
+ .WCLKE(%s),
+ .WCLK%s(%s),
+ .RE(%s),
+ .RCLKE(%s),
+ .RCLK%s(%s)
+ );
+ """ % (
+ rdata_bits-1, i, memtype, rmode, wmode, i,
+ bits_waddr, bits_raddr, bits_mask, bits_wdata, i,
+ bit_we, bit_wclke, wclksuffix, bit_wclk,
+ bit_re, bit_rclke, rclksuffix, bit_rclk
+ ), file=f)
+ bits = list(np.random.permutation(bits))
+ for k in range(rdata_bits):
+ bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k])
+ print("assign out_pins = rdata_%d;" % i, file=f)
+ print("endmodule", file=f)
+ with open("work_ram40/ram40_%02d.pcf" % idx, "w") as f:
+ p = list(np.random.permutation(pins))
+ for i in range(60):
+ print("set_io in_pins[%d] %s" % (i, p.pop()), file=f)
+ for i in range(16):
+ print("set_io out_pins[%d] %s" % (i, p.pop()), file=f)
+
+with open("work_ram40/Makefile", "w") as f:
+ print("all: %s" % " ".join(["ram40_%02d.bin" % i for i in range(num)]), file=f)
+ for i in range(num):
+ print("ram40_%02d.bin:" % i, file=f)
+ print("\t-bash ../icecube.sh ram40_%02d > ram40_%02d.log 2>&1 && rm -rf ram40_%02d.tmp || tail ram40_%02d.log" % (i, i, i, i), file=f)
+
diff --git a/icefuzz/pinloc/pinloc-1k-tq144.sh b/icefuzz/pinloc/pinloc-1k-tq144.sh
new file mode 100644
index 0000000..64f9f69
--- /dev/null
+++ b/icefuzz/pinloc/pinloc-1k-tq144.sh
@@ -0,0 +1,33 @@
+#!/bin/bash
+
+pins="
+ 1 2 3 4 7 8 9 10 11 12 19 20 21 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 39 41 42 43 44 45 47 48 49 50 52 56 58 60 61 62 63 64 67 68 70 71
+ 73 74 75 76 78 79 80 81 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 128 129 134 135 136 137 138 139 141 142 143 144
+"
+
+{
+ echo -n "all:"
+ for pin in $pins; do
+ id="pinloc-1k-tq144_${pin}"
+ echo -n " ${id}.exp"
+ done
+ echo
+
+ for pin in $pins; do
+ id="pinloc-1k-tq144_${pin}"
+ echo "module top(output y); assign y = 0; endmodule" > ${id}.v
+ echo "set_io y ${pin}" >> ${id}.pcf
+ echo; echo "${id}.exp:"
+ echo " ICEDEV=hx1k-tq144 bash ../icecube.sh ${id} > ${id}.log 2>&1"
+ echo " ../../icebox/icebox_explain.py ${id}.txt > ${id}.exp.new"
+ echo " rm -rf ${id}.tmp"
+ echo " mv ${id}.exp.new ${id}.exp"
+ done
+} > pinloc-1k-tq144.mk
+
+set -ex
+make -f pinloc-1k-tq144.mk -j4
+python pinlocdb.py pinloc-1k-tq144_*.exp > pinloc-1k-tq144.txt
+
diff --git a/icefuzz/pinloc/pinloc-8k-ct256.sh b/icefuzz/pinloc/pinloc-8k-ct256.sh
new file mode 100644
index 0000000..d3cf419
--- /dev/null
+++ b/icefuzz/pinloc/pinloc-8k-ct256.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+
+pins="
+ A1 A2 A5 A6 A7 A9 A10 A11 A15 A16
+ B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
+ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16
+ D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16
+ E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16
+ F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16
+ G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16
+ H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16
+ J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16
+ K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16
+ L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16
+ M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16
+ N2 N3 N4 N5 N6 N7 N9 N10 N12 N16
+ P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
+ R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16
+ T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16
+"
+
+{
+ echo -n "all:"
+ for pin in $pins; do
+ id="pinloc-8k-ct256_${pin}"
+ echo -n " ${id}.exp"
+ done
+ echo
+
+ for pin in $pins; do
+ id="pinloc-8k-ct256_${pin}"
+ echo "module top(output y); assign y = 0; endmodule" > ${id}.v
+ echo "set_io y ${pin}" >> ${id}.pcf
+ echo; echo "${id}.exp:"
+ echo " ICEDEV=hx8k-ct256 bash ../icecube.sh ${id} > ${id}.log 2>&1"
+ echo " ../../icebox/icebox_explain.py ${id}.txt > ${id}.exp.new"
+ echo " rm -rf ${id}.tmp"
+ echo " mv ${id}.exp.new ${id}.exp"
+ done
+} > pinloc-8k-ct256.mk
+
+set -ex
+make -f pinloc-8k-ct256.mk -j4
+python pinlocdb.py pinloc-8k-ct256_*.exp > pinloc-8k-ct256.txt
diff --git a/icefuzz/pinloc/pinlocdb.py b/icefuzz/pinloc/pinlocdb.py
new file mode 100644
index 0000000..31c6476
--- /dev/null
+++ b/icefuzz/pinloc/pinlocdb.py
@@ -0,0 +1,46 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+
+import re
+from sys import argv
+
+ieren_db = [ ]
+pinloc_db = [ ]
+
+for arg in argv[1:]:
+ pin = re.search(r"_([^.]*)", arg).group(1)
+ with open(arg, "r") as f:
+ tile = [0, 0]
+ iob = [0, 0, 0]
+ ioctrl = [0, 0, 0]
+
+ for line in f:
+ match = re.match(r"^\.io_tile (\d+) (\d+)", line)
+ if match:
+ tile = [int(match.group(1)), int(match.group(2))]
+
+ match = re.match(r"^IOB_(\d+)", line)
+ if match:
+ iob = tile + [int(match.group(1))]
+
+ match = re.match(r"^IoCtrl REN_(\d+)", line)
+ if match:
+ ioctrl = tile + [int(match.group(1))]
+
+ ieren_db.append(tuple(iob + ioctrl))
+ pinloc_db.append(tuple(['"' + pin + '"'] + iob))
+
+print()
+print("# ieren_db")
+for entry in sorted(ieren_db):
+ print("(%2d, %2d, %d, %2d, %2d, %d)," % entry)
+
+print()
+print("# pinloc_db")
+for entry in sorted(pinloc_db):
+ print("(%5s, %2d, %2d, %d)," % entry)
+
+print()
+
diff --git a/icefuzz/runloop.sh b/icefuzz/runloop.sh
new file mode 100644
index 0000000..ceb75c9
--- /dev/null
+++ b/icefuzz/runloop.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+i=0
+while true; do
+ echo; svn diff cached_*.txt | diffstat
+ echo; echo -n "[$(date '+%H:%M:%S')] Iteration $(( ++i )) "
+ { echo; echo; echo; echo; echo; echo; echo "Iteration $i"; date; } >> runloop.log
+ if make clean > >( gawk '{ print >> "runloop.log"; printf("x"); fflush(""); }'; ) 2>&1 &&
+ make -j6 > >( gawk '{ print >> "runloop.log"; printf("m"); fflush(""); }'; ) 2>&1 &&
+ make -j6 check > >( gawk '{ print >> "runloop.log"; if (NR % 100 == 0) printf("c"); fflush(""); }'; ) 2>&1
+ then
+ echo -n " OK"
+ else
+ echo " ERROR"; echo
+ tail runloop.log
+ exit 1
+ fi
+done
+
diff --git a/icefuzz/tests/all_luts_ffff.bin b/icefuzz/tests/all_luts_ffff.bin
new file mode 100644
index 0000000..4ccf76a
Binary files /dev/null and b/icefuzz/tests/all_luts_ffff.bin differ
diff --git a/icefuzz/tests/bitop.pcf b/icefuzz/tests/bitop.pcf
new file mode 100644
index 0000000..143632e
--- /dev/null
+++ b/icefuzz/tests/bitop.pcf
@@ -0,0 +1,3 @@
+set_io a 1
+set_io b 10
+set_io y 11
diff --git a/icefuzz/tests/bitop.v b/icefuzz/tests/bitop.v
new file mode 100644
index 0000000..b698cf9
--- /dev/null
+++ b/icefuzz/tests/bitop.v
@@ -0,0 +1,3 @@
+module top (input a, b, output y);
+ assign y = a & b;
+endmodule
diff --git a/icefuzz/tests/bram.pcf b/icefuzz/tests/bram.pcf
new file mode 100644
index 0000000..1d9ac7e
--- /dev/null
+++ b/icefuzz/tests/bram.pcf
@@ -0,0 +1 @@
+set_location ram 3 1
diff --git a/icefuzz/tests/bram.v b/icefuzz/tests/bram.v
new file mode 100644
index 0000000..842fe52
--- /dev/null
+++ b/icefuzz/tests/bram.v
@@ -0,0 +1,40 @@
+module top (
+ input clk,
+ input [15:0] wdata,
+ output [15:0] rdata,
+ input [7:0] addr
+);
+ SB_RAM40_4K #(
+ .WRITE_MODE(0),
+ .READ_MODE(0)
+ ) ram (
+ .RDATA(rdata),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(1'b1),
+ .MASK(16'b0)
+ );
+
+ defparam ram.INIT_0 = 256'h123456789abcdef00000dddd0000eeee00000012483569ac0111044400000001;
+ defparam ram.INIT_1 = 256'h56789abcdef123400000dddd0000eeee00000012483569ac0111044401000002;
+ defparam ram.INIT_2 = 256'habcdef12345678900000dddd0000eeee00000012483569ac0111044402000004;
+ defparam ram.INIT_3 = 256'h00000000000000000000dddd0000eeee00000012483569ac0111044403000008;
+ defparam ram.INIT_4 = 256'hffff000022220000444400006666000088880012483569ac0111044404000010;
+ defparam ram.INIT_5 = 256'hffff000022220000444400006666000088880012483569ac0111044405000020;
+ defparam ram.INIT_6 = 256'hffff000022220000444400006666000088880012483569ac0111044406000040;
+ defparam ram.INIT_7 = 256'hffff000022220000444400006666000088880012483569ac0111044407000080;
+ defparam ram.INIT_8 = 256'h0000111100003333000055550000777700000012483569ac0111044408000100;
+ defparam ram.INIT_9 = 256'h0000111100003333000055550000777700000012483569ac0111044409000200;
+ defparam ram.INIT_A = 256'h0000111100003333000055550000777700000012483569ac011104440a000400;
+ defparam ram.INIT_B = 256'h0000111100003333000055550000777700000012483569ac011104440b000800;
+ defparam ram.INIT_C = 256'h0123000099990000aaaa0000bbbb0000cccc0012483569ac011104440c001000;
+ defparam ram.INIT_D = 256'h4567000099990000aaaa0000bbbb0000cccc0012483569ac011104440d002000;
+ defparam ram.INIT_E = 256'h89ab000099990000aaaa0000bbbb0000cccc0012483569ac011104440e004000;
+ defparam ram.INIT_F = 256'hcdef000099990000aaaa0000bbbb0000cccc0012483569ac011104440f008000;
+endmodule
diff --git a/icefuzz/tests/carry.v b/icefuzz/tests/carry.v
new file mode 100644
index 0000000..42aae86
--- /dev/null
+++ b/icefuzz/tests/carry.v
@@ -0,0 +1,8 @@
+module top (input a, b, ci, output co);
+ SB_CARRY carry_cell (
+ .I0(a),
+ .I1(b),
+ .CI(ci),
+ .CO(co)
+ );
+endmodule
diff --git a/icefuzz/tests/colbuf.py b/icefuzz/tests/colbuf.py
new file mode 100644
index 0000000..7b080b1
--- /dev/null
+++ b/icefuzz/tests/colbuf.py
@@ -0,0 +1,22 @@
+#!/usr/bin/python
+
+import fileinput
+
+colbuf_tile = None
+glbnet_tile = None
+
+for line in fileinput.input():
+ line = line.split()
+ if len(line) == 0:
+ continue
+ if line[0] in [".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile"]:
+ current_tile = (int(line[1]), int(line[2]))
+ if line[0] == "ColBufCtrl":
+ assert colbuf_tile is None
+ colbuf_tile = current_tile
+ if line[0] == "buffer" and line[1].startswith("glb_netwk_"):
+ assert glbnet_tile is None
+ glbnet_tile = current_tile
+
+print("(%2d, %2d, %2d, %2d)," % (colbuf_tile[0], colbuf_tile[1], glbnet_tile[0], glbnet_tile[1]))
+
diff --git a/icefuzz/tests/colbuf.sh b/icefuzz/tests/colbuf.sh
new file mode 100644
index 0000000..61b31cc
--- /dev/null
+++ b/icefuzz/tests/colbuf.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+
+# for f in colbuf_io.work/*.exp colbuf_logic.work/*.exp colbuf_ram.work/*.exp; do
+# python colbuf.py $f
+# done | sort -u > colbuf.txt
+
+get_colbuf_data()
+{
+ # tr -d '(,)' < colbuf.txt
+ for x in {0..2} {4..9} {11..13}; do
+ echo $x 4 $x 0
+ echo $x 5 $x 8
+ echo $x 12 $x 9
+ echo $x 13 $x 17
+ done
+ for x in 3 10; do
+ echo $x 3 $x 0
+ echo $x 3 $x 4
+ echo $x 5 $x 8
+ echo $x 11 $x 9
+ echo $x 11 $x 12
+ echo $x 13 $x 17
+ done
+}
+
+{
+ echo "<svg xmlns=\"http://www.w3.org/2000/svg\" height=\"580\" width=\"460\">"
+ for x in {1..13}; do
+ echo "<line x1=\"$((10+x*30))\" y1=\"10\" x2=\"$((10+x*30))\" y2=\"$((10+18*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
+ done
+ for y in {1..17}; do
+ echo "<line x1=\"10\" y1=\"$((10+y*30))\" x2=\"$((10+14*30))\" y2=\"$((10+y*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
+ done
+ for x in {0..13}; do
+ echo "<text x=\"$((10+$x*30+7))\" y=\"$((10+18*30+15))\" fill=\"black\">$x</text>"
+ done
+ for y in {0..17}; do
+ echo "<text x=\"$((10+14*30+5))\" y=\"$((10+(17-y)*30+20))\" fill=\"black\">$y</text>"
+ done
+ while read x1 y1 x2 y2; do
+ echo "<line x1=\"$((10+x1*30+15))\" y1=\"$((10+(17-y1)*30+15))\" x2=\"$((10+x2*30+15))\" y2=\"$((10+(17-y2)*30+15))\" style=\"stroke:rgb(255,0,0);stroke-width:5\" />"
+ done < <( get_colbuf_data; )
+ while read x1 y1 x2 y2; do
+ echo "<circle cx=\"$((10+x1*30+15))\" cy=\"$((10+(17-y1)*30+15))\" r=\"5\" fill=\"gray\" />"
+ done < <( get_colbuf_data; )
+ echo "</svg>"
+} > colbuf.svg
+
diff --git a/icefuzz/tests/colbuf_8k.sh b/icefuzz/tests/colbuf_8k.sh
new file mode 100644
index 0000000..b333075
--- /dev/null
+++ b/icefuzz/tests/colbuf_8k.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+
+for f in colbuf_io_8k.work/*.exp colbuf_logic_8k.work/*.exp colbuf_ram_8k.work/*.exp; do
+ echo $f >&2
+ python colbuf.py $f
+done | sort -u > colbuf_8k.txt
+
+get_colbuf_data()
+{
+ tr -d '(,)' < colbuf_8k.txt
+ # for x in {0..2} {4..9} {11..13}; do
+ # echo $x 4 $x 0
+ # echo $x 5 $x 8
+ # echo $x 12 $x 9
+ # echo $x 13 $x 17
+ # done
+ # for x in 3 10; do
+ # echo $x 3 $x 0
+ # echo $x 3 $x 4
+ # echo $x 5 $x 8
+ # echo $x 11 $x 9
+ # echo $x 11 $x 12
+ # echo $x 13 $x 17
+ # done
+}
+
+{
+ echo "<svg xmlns=\"http://www.w3.org/2000/svg\" height=\"1050\" width=\"1050\">"
+ for x in {1..33}; do
+ echo "<line x1=\"$((10+x*30))\" y1=\"10\" x2=\"$((10+x*30))\" y2=\"$((10+34*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
+ done
+ for y in {1..33}; do
+ echo "<line x1=\"10\" y1=\"$((10+y*30))\" x2=\"$((10+34*30))\" y2=\"$((10+y*30))\" style=\"stroke:rgb(0,0,0);stroke-width:3\" />"
+ done
+ for x in {0..33}; do
+ echo "<text x=\"$((10+$x*30+7))\" y=\"$((10+34*30+15))\" fill=\"black\">$x</text>"
+ done
+ for y in {0..33}; do
+ echo "<text x=\"$((10+34*30+5))\" y=\"$((10+(33-y)*30+20))\" fill=\"black\">$y</text>"
+ done
+ while read x1 y1 x2 y2; do
+ echo "<line x1=\"$((10+x1*30+15))\" y1=\"$((10+(33-y1)*30+15))\" x2=\"$((10+x2*30+15))\" y2=\"$((10+(33-y2)*30+15))\" style=\"stroke:rgb(255,0,0);stroke-width:5\" />"
+ done < <( get_colbuf_data; )
+ while read x1 y1 x2 y2; do
+ echo "<circle cx=\"$((10+x2*30+15))\" cy=\"$((10+(33-y2)*30+15))\" r=\"4\" fill=\"blue\" />"
+ done < <( get_colbuf_data; )
+ while read x1 y1 x2 y2; do
+ echo "<circle cx=\"$((10+x1*30+15))\" cy=\"$((10+(33-y1)*30+15))\" r=\"5\" fill=\"gray\" />"
+ done < <( get_colbuf_data; )
+ echo "</svg>"
+} > colbuf_8k.svg
+
diff --git a/icefuzz/tests/colbuf_io.sh b/icefuzz/tests/colbuf_io.sh
new file mode 100644
index 0000000..2cc8387
--- /dev/null
+++ b/icefuzz/tests/colbuf_io.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_io.work
+cd colbuf_io.work
+
+glb_pins="93 21 128 50 20 94 49 129"
+
+pins="
+ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64
+ 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144
+"
+pins="$( echo $pins )"
+
+for pin in $pins; do
+ pf="colbuf_io_$pin"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | grep -v $pin | sort -R | head -n1; )
+ cat > ${pf}.v <<- EOT
+ module top (input clk, data, output pin);
+ SB_IO #(
+ .PIN_TYPE(6'b 0101_00)
+ ) pin_obuf (
+ .PACKAGE_PIN(pin),
+ .OUTPUT_CLK(clk),
+ .D_OUT_0(data)
+ );
+ endmodule
+ EOT
+ echo "set_io pin $pin" > ${pf}.pcf
+ echo "set_io clk $gpin" >> ${pf}.pcf
+ bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done
+
diff --git a/icefuzz/tests/colbuf_io_8k.sh b/icefuzz/tests/colbuf_io_8k.sh
new file mode 100644
index 0000000..06d9d1d
--- /dev/null
+++ b/icefuzz/tests/colbuf_io_8k.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_io_8k.work
+cd colbuf_io_8k.work
+
+glb_pins="C8 F7 G1 H11 H16 J3 K9 R9"
+
+pins="
+ A1 A2 A5 A6 A7 A9 A10 A11 A15 A16
+ B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
+ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16
+ D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16
+ E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16
+ F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16
+ G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16
+ H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16
+ J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16
+ K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16
+ L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16
+ M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16
+ N2 N3 N4 N5 N6 N7 N9 N10 N12 N16
+ P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
+ R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16
+ T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16
+"
+pins="$( echo $pins )"
+
+for pin in $pins; do
+ pf="colbuf_io_8k_$pin"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | grep -v $pin | sort -R | head -n1; )
+ cat > ${pf}.v <<- EOT
+ module top (input clk, data, output pin);
+ SB_IO #(
+ .PIN_TYPE(6'b 0101_00)
+ ) pin_obuf (
+ .PACKAGE_PIN(pin),
+ .OUTPUT_CLK(clk),
+ .D_OUT_0(data)
+ );
+ endmodule
+ EOT
+ echo "set_io pin $pin" > ${pf}.pcf
+ echo "set_io clk $gpin" >> ${pf}.pcf
+ ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done
+
diff --git a/icefuzz/tests/colbuf_logic.sh b/icefuzz/tests/colbuf_logic.sh
new file mode 100644
index 0000000..76676a4
--- /dev/null
+++ b/icefuzz/tests/colbuf_logic.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_logic.work
+cd colbuf_logic.work
+
+glb_pins="93 21 128 50 20 94 49 129"
+
+for x in 1 2 {4..9} 11 12; do
+for y in {1..16}; do
+ pf="colbuf_logic_${x}_${y}"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
+ cat > ${pf}.v <<- EOT
+ module top (input c, d, output q);
+ SB_DFF dff (
+ .C(c),
+ .D(d),
+ .Q(q)
+ );
+ endmodule
+ EOT
+ echo "set_location dff $x $y 0" > ${pf}.pcf
+ echo "set_io c $gpin" >> ${pf}.pcf
+ bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done; done
+
diff --git a/icefuzz/tests/colbuf_logic_8k.sh b/icefuzz/tests/colbuf_logic_8k.sh
new file mode 100644
index 0000000..135053b
--- /dev/null
+++ b/icefuzz/tests/colbuf_logic_8k.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_logic_8k.work
+cd colbuf_logic_8k.work
+
+glb_pins="C8 F7 G1 H11 H16 J3 K9 R9"
+
+for x in {1..7} {9..24} {26..32}; do
+for y in {1..32}; do
+ pf="colbuf_logic_8k_${x}_${y}"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
+ cat > ${pf}.v <<- EOT
+ module top (input c, d, output q);
+ SB_DFF dff (
+ .C(c),
+ .D(d),
+ .Q(q)
+ );
+ endmodule
+ EOT
+ echo "set_location dff $x $y 0" > ${pf}.pcf
+ echo "set_io c $gpin" >> ${pf}.pcf
+ ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done; done
+
diff --git a/icefuzz/tests/colbuf_ram.sh b/icefuzz/tests/colbuf_ram.sh
new file mode 100644
index 0000000..7dc2f04
--- /dev/null
+++ b/icefuzz/tests/colbuf_ram.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_ram.work
+cd colbuf_ram.work
+
+glb_pins="93 21 128 50 20 94 49 129"
+
+for x in 3 10; do
+for y in {1..16}; do
+ pf="colbuf_ram_${x}_${y}"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
+ if [ $((y % 2)) == 1 ]; then
+ clkport="WCLK"
+ other_clkport="RCLK"
+ else
+ clkport="RCLK"
+ other_clkport="WCLK"
+ fi
+ cat > ${pf}.v <<- EOT
+ module top (input c, oc, input [1:0] d, output [1:0] q);
+ wire gc;
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 0000_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) gbuf (
+ .PACKAGE_PIN(c),
+ .GLOBAL_BUFFER_OUTPUT(gc)
+ );
+ SB_RAM40_4K #(
+ .READ_MODE(3),
+ .WRITE_MODE(3)
+ ) ram40 (
+ .WADDR(11'b0),
+ .RADDR(11'b0),
+ .$clkport(gc),
+ .$other_clkport(oc),
+ .RDATA(q),
+ .WDATA(d),
+ .WE(1'b1),
+ .WCLKE(1'b1),
+ .RE(1'b1),
+ .RCLKE(1'b1)
+ );
+ endmodule
+ EOT
+ echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf
+ echo "set_io oc 1" >> ${pf}.pcf
+ echo "set_io c $gpin" >> ${pf}.pcf
+ bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done; done
+
diff --git a/icefuzz/tests/colbuf_ram_8k.sh b/icefuzz/tests/colbuf_ram_8k.sh
new file mode 100644
index 0000000..56c5825
--- /dev/null
+++ b/icefuzz/tests/colbuf_ram_8k.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p colbuf_ram_8k.work
+cd colbuf_ram_8k.work
+
+glb_pins="C8 F7 G1 H11 H16 J3 K9 R9"
+
+for x in 8 25; do
+for y in {1..32}; do
+ pf="colbuf_ram_8k_${x}_${y}"
+ gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; )
+ if [ $((y % 2)) == 1 ]; then
+ clkport="WCLK"
+ other_clkport="RCLK"
+ else
+ clkport="RCLK"
+ other_clkport="WCLK"
+ fi
+ cat > ${pf}.v <<- EOT
+ module top (input c, oc, input [1:0] d, output [1:0] q);
+ wire gc;
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 0000_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) gbuf (
+ .PACKAGE_PIN(c),
+ .GLOBAL_BUFFER_OUTPUT(gc)
+ );
+ SB_RAM40_4K #(
+ .READ_MODE(3),
+ .WRITE_MODE(3)
+ ) ram40 (
+ .WADDR(11'b0),
+ .RADDR(11'b0),
+ .$clkport(gc),
+ .$other_clkport(oc),
+ .RDATA(q),
+ .WDATA(d),
+ .WE(1'b1),
+ .WCLKE(1'b1),
+ .RE(1'b1),
+ .RCLKE(1'b1)
+ );
+ endmodule
+ EOT
+ echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf
+ echo "set_io oc 1" >> ${pf}.pcf
+ echo "set_io c $gpin" >> ${pf}.pcf
+ ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+ rm -rf ${pf}.tmp
+done; done
+
diff --git a/icefuzz/tests/cross_0.pcf b/icefuzz/tests/cross_0.pcf
new file mode 100644
index 0000000..35ea96b
--- /dev/null
+++ b/icefuzz/tests/cross_0.pcf
@@ -0,0 +1,17 @@
+
+# row 14, block 0
+set_io in_left 2
+set_io out_right 104
+
+# row 4, block 0
+set_io out_left 29
+set_io in_right 79
+
+# col 4, block 0
+set_io in_bottom 44
+set_io out_top 137
+
+# col 8, block 0
+set_io out_bottom 58
+set_io in_top 121
+
diff --git a/icefuzz/tests/cross_0.v b/icefuzz/tests/cross_0.v
new file mode 100644
index 0000000..515b7ac
--- /dev/null
+++ b/icefuzz/tests/cross_0.v
@@ -0,0 +1,9 @@
+module top (
+ input in_left, in_right, in_top, in_bottom,
+ output out_left, out_right, out_top, out_bottom
+);
+ assign out_left = in_right;
+ assign out_right = in_left;
+ assign out_top = in_bottom;
+ assign out_bottom = in_top;
+endmodule
diff --git a/icefuzz/tests/example_hx8kboard.pcf b/icefuzz/tests/example_hx8kboard.pcf
new file mode 100644
index 0000000..417ca01
--- /dev/null
+++ b/icefuzz/tests/example_hx8kboard.pcf
@@ -0,0 +1,9 @@
+set_io LED0 B5
+set_io LED1 B4
+set_io LED2 A2
+set_io LED3 A1
+set_io LED4 C5
+set_io LED5 C4
+set_io LED6 B3
+set_io LED7 C3
+set_io clk J3
diff --git a/icefuzz/tests/example_hx8kboard.sdc b/icefuzz/tests/example_hx8kboard.sdc
new file mode 100644
index 0000000..c20def1
--- /dev/null
+++ b/icefuzz/tests/example_hx8kboard.sdc
@@ -0,0 +1 @@
+create_clock -period 10.00 -name {top|clk} [get_ports {clk}]
diff --git a/icefuzz/tests/example_hx8kboard.sh b/icefuzz/tests/example_hx8kboard.sh
new file mode 100644
index 0000000..0d1affd
--- /dev/null
+++ b/icefuzz/tests/example_hx8kboard.sh
@@ -0,0 +1,2 @@
+#!/bin/bash
+ICEDEV=hx8k-ct256 bash ../icecube.sh example_hx8kboard.v
diff --git a/icefuzz/tests/example_hx8kboard.v b/icefuzz/tests/example_hx8kboard.v
new file mode 100644
index 0000000..f04203a
--- /dev/null
+++ b/icefuzz/tests/example_hx8kboard.v
@@ -0,0 +1,32 @@
+module top (
+ input clk,
+ output LED0,
+ output LED1,
+ output LED2,
+ output LED3,
+ output LED4,
+ output LED5,
+ output LED6,
+ output LED7
+);
+
+ localparam BITS = 8;
+ localparam LOG2DELAY = 22;
+
+ function [BITS-1:0] bin2gray(input [BITS-1:0] in);
+ integer i;
+ reg [BITS:0] temp;
+ begin
+ temp = in;
+ for (i=0; i<BITS; i=i+1)
+ bin2gray[i] = ^temp[i +: 2];
+ end
+ endfunction
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always@(posedge clk)
+ counter <= counter + 1;
+
+ assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = bin2gray(counter >> LOG2DELAY);
+endmodule
diff --git a/icefuzz/tests/example_icestick.pcf b/icefuzz/tests/example_icestick.pcf
new file mode 100644
index 0000000..a1693eb
--- /dev/null
+++ b/icefuzz/tests/example_icestick.pcf
@@ -0,0 +1,6 @@
+set_io LED1 99
+set_io LED2 98
+set_io LED3 97
+set_io LED4 96
+set_io LED5 95
+set_io clk 21
diff --git a/icefuzz/tests/example_icestick.sdc b/icefuzz/tests/example_icestick.sdc
new file mode 100644
index 0000000..c20def1
--- /dev/null
+++ b/icefuzz/tests/example_icestick.sdc
@@ -0,0 +1 @@
+create_clock -period 10.00 -name {top|clk} [get_ports {clk}]
diff --git a/icefuzz/tests/example_icestick.sh b/icefuzz/tests/example_icestick.sh
new file mode 100644
index 0000000..a438183
--- /dev/null
+++ b/icefuzz/tests/example_icestick.sh
@@ -0,0 +1,2 @@
+#!/bin/bash
+bash ../icecube.sh example_icestick.v
diff --git a/icefuzz/tests/example_icestick.v b/icefuzz/tests/example_icestick.v
new file mode 100644
index 0000000..4635550
--- /dev/null
+++ b/icefuzz/tests/example_icestick.v
@@ -0,0 +1,29 @@
+module top (
+ input clk,
+ output LED1,
+ output LED2,
+ output LED3,
+ output LED4,
+ output LED5
+);
+
+ localparam BITS = 5;
+ localparam LOG2DELAY = 22;
+
+ function [BITS-1:0] bin2gray(input [BITS-1:0] in);
+ integer i;
+ reg [BITS:0] temp;
+ begin
+ temp = in;
+ for (i=0; i<BITS; i=i+1)
+ bin2gray[i] = ^temp[i +: 2];
+ end
+ endfunction
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always@(posedge clk)
+ counter <= counter + 1;
+
+ assign {LED1, LED2, LED3, LED4, LED5} = bin2gray(counter >> LOG2DELAY);
+endmodule
diff --git a/icefuzz/tests/icegate.pcf b/icefuzz/tests/icegate.pcf
new file mode 100644
index 0000000..6c6e2e1
--- /dev/null
+++ b/icefuzz/tests/icegate.pcf
@@ -0,0 +1,4 @@
+set_io din_0 33
+set_io global 97
+set_io latch_in 112
+set_io pin_gb_io 0 9 0
diff --git a/icefuzz/tests/icegate.v b/icefuzz/tests/icegate.v
new file mode 100644
index 0000000..13b7dd5
--- /dev/null
+++ b/icefuzz/tests/icegate.v
@@ -0,0 +1,18 @@
+module top (
+ inout pin,
+ input latch_in,
+ output din_0,
+ output global
+);
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 0000_11),
+ .PULLUP(1'b 0),
+ .NEG_TRIGGER(1'b 0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) \pin_gb_io (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(latch_in),
+ .D_IN_0(din_0),
+ .GLOBAL_BUFFER_OUTPUT(globals)
+ );
+endmodule
diff --git a/icefuzz/tests/io_glb_netwk.pcf b/icefuzz/tests/io_glb_netwk.pcf
new file mode 100644
index 0000000..9abb57d
--- /dev/null
+++ b/icefuzz/tests/io_glb_netwk.pcf
@@ -0,0 +1,10 @@
+set_io in 1
+set_io out 2
+set_io pin[0] 20 # padin_4
+set_io pin[1] 21 # padin_1
+set_io pin[2] 49 # padin_6
+set_io pin[3] 50 # padin_3
+set_io pin[4] 93 # padin_0
+set_io pin[5] 94 # padin_5
+set_io pin[6] 128 # padin_2
+set_io pin[7] 129 # padin_7
diff --git a/icefuzz/tests/io_glb_netwk.v b/icefuzz/tests/io_glb_netwk.v
new file mode 100644
index 0000000..0d94244
--- /dev/null
+++ b/icefuzz/tests/io_glb_netwk.v
@@ -0,0 +1,42 @@
+module top (
+ inout [7:0] pin,
+ input in,
+ output out
+);
+ wire [7:0] glbl, clk;
+ reg [7:0] q;
+
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 0000_11),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) PIO[7:0] (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(1'b1),
+ .CLOCK_ENABLE(),
+ .INPUT_CLK(),
+ .OUTPUT_CLK(),
+ .OUTPUT_ENABLE(),
+ .D_OUT_0(),
+ .D_OUT_1(),
+ .D_IN_0(),
+ .D_IN_1(),
+ .GLOBAL_BUFFER_OUTPUT(glbl)
+ );
+
+ assign clk[0] = glbl[0]; // glb_netwk_4
+ assign clk[1] = glbl[1]; // glb_netwk_1
+ assign clk[2] = glbl[2]; // glb_netwk_6
+ assign clk[3] = glbl[3]; // glb_netwk_3
+ assign clk[4] = glbl[4]; // glb_netwk_0
+ assign clk[5] = glbl[5]; // glb_netwk_5
+ assign clk[6] = glbl[6]; // glb_netwk_2
+ assign clk[7] = glbl[7]; // glb_netwk_7
+
+ genvar i;
+ generate for (i = 0; i < 8; i=i+1) begin
+ always @(posedge clk[i]) q[i] <= in;
+ end endgenerate
+ assign out = ^{q, in};
+endmodule
diff --git a/icefuzz/tests/io_latched.sh b/icefuzz/tests/io_latched.sh
new file mode 100644
index 0000000..7db5268
--- /dev/null
+++ b/icefuzz/tests/io_latched.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p io_latched.work
+cd io_latched.work
+
+pins="
+ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64
+ 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144
+"
+pins="$( echo $pins )"
+
+for pin in $pins; do
+ pf="io_latched_$pin"
+ cp ../io_latched.v ${pf}.v
+ read pin_latch pin_data < <( echo $pins | tr ' ' '\n' | grep -v $pin | sort -R; )
+ {
+ echo "set_io pin $pin"
+ echo "set_io latch_in $pin_latch"
+ echo "set_io data_out $pin_data"
+ } > ${pf}.pcf
+ bash ../../icecube.sh ${pf}.v
+ ../../../icebox/icebox_vlog.py -SP ${pf}.psb ${pf}.txt > ${pf}.ve
+done
+
diff --git a/icefuzz/tests/io_latched.v b/icefuzz/tests/io_latched.v
new file mode 100644
index 0000000..8c0e63e
--- /dev/null
+++ b/icefuzz/tests/io_latched.v
@@ -0,0 +1,23 @@
+module top (
+ inout pin,
+ input latch_in,
+ output data_out
+);
+ SB_IO #(
+ .PIN_TYPE(6'b0000_11),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) pin_ibuf (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(),
+ .INPUT_CLK(),
+ .OUTPUT_CLK(),
+ .OUTPUT_ENABLE(),
+ .D_OUT_0(),
+ .D_OUT_1(),
+ .D_IN_0(data_out),
+ .D_IN_1()
+ );
+endmodule
diff --git a/icefuzz/tests/ioctrl.py b/icefuzz/tests/ioctrl.py
new file mode 100644
index 0000000..6d09bad
--- /dev/null
+++ b/icefuzz/tests/ioctrl.py
@@ -0,0 +1,21 @@
+#!/usr/bin/python
+
+import fileinput
+
+for line in fileinput.input():
+ line = line.split()
+ if len(line) == 0:
+ continue
+ if line[0] == ".io_tile":
+ current_tile = (int(line[1]), int(line[2]))
+ if line[0] == "IoCtrl" and line[1] == "REN_0":
+ ren = (current_tile[0], current_tile[1], 0)
+ if line[0] == "IoCtrl" and line[1] == "REN_1":
+ ren = (current_tile[0], current_tile[1], 1)
+ if line[0] == "IOB_0":
+ iob = (current_tile[0], current_tile[1], 0)
+ if line[0] == "IOB_1":
+ iob = (current_tile[0], current_tile[1], 1)
+
+print("(%2d, %2d, %2d, %2d, %2d, %2d)," % (iob[0], iob[1], iob[2], ren[0], ren[1], ren[2]))
+
diff --git a/icefuzz/tests/ioctrl.sh b/icefuzz/tests/ioctrl.sh
new file mode 100644
index 0000000..77fdccf
--- /dev/null
+++ b/icefuzz/tests/ioctrl.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p ioctrl.work
+cd ioctrl.work
+
+pins="
+ 1 2 3 4 7 8 9 10 11 12 19 20 21 22 23 24 25 26 28 29 31 32 33 34
+ 37 38 39 41 42 43 44 45 47 48 49 50 52 56 58 60 61 62 63 64 67 68 70 71
+ 73 74 75 76 78 79 80 81 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107
+ 112 113 114 115 116 117 118 119 120 121 122 128 129 134 135 136 137 138 139 141 142 143 144
+"
+pins="$( echo $pins )"
+
+for pin in $pins; do
+ pf="ioctrl_$pin"
+ echo "module top (output pin); assign pin = 1; endmodule" > ${pf}.v
+ echo "set_io pin $pin" > ${pf}.pcf
+ bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ ../../../icebox/icebox_explain.py ${pf}.txt > ${pf}.exp
+done
+
+set +x
+echo "--snip--"
+for pin in $pins; do
+ python ../ioctrl.py ioctrl_${pin}.exp
+done | tee ioctrl_db.txt
+echo "--snap--"
+
diff --git a/icefuzz/tests/lut_cascade.pcf b/icefuzz/tests/lut_cascade.pcf
new file mode 100644
index 0000000..d66d858
--- /dev/null
+++ b/icefuzz/tests/lut_cascade.pcf
@@ -0,0 +1,2 @@
+set_location dst_lut 6 8 2 # SB_LUT4 (LogicCell: dst_lut_LC_0)
+set_location src_lut 6 8 1 # SB_LUT4 (LogicCell: src_lut_LC_1)
diff --git a/icefuzz/tests/lut_cascade.v b/icefuzz/tests/lut_cascade.v
new file mode 100644
index 0000000..fed55ba
--- /dev/null
+++ b/icefuzz/tests/lut_cascade.v
@@ -0,0 +1,23 @@
+module top (input a, b, c, d, e, f, g, output y);
+ wire cascade;
+
+ SB_LUT4 #(
+ .LUT_INIT(16'b 1100_1100_1100_1010)
+ ) src_lut (
+ .O(cascade),
+ .I0(a),
+ .I1(b),
+ .I2(c),
+ .I3(d)
+ );
+
+ SB_LUT4 #(
+ .LUT_INIT(16'b 1000_0100_0010_0001)
+ ) dst_lut (
+ .O(y),
+ .I0(e),
+ .I1(f),
+ .I2(cascade),
+ .I3(g)
+ );
+endmodule
diff --git a/icefuzz/tests/raminits.pcf b/icefuzz/tests/raminits.pcf
new file mode 100644
index 0000000..6d9d1c7
--- /dev/null
+++ b/icefuzz/tests/raminits.pcf
@@ -0,0 +1,16 @@
+set_location ram_0301 3 1
+set_location ram_0303 3 3
+set_location ram_0305 3 5
+set_location ram_0307 3 7
+set_location ram_0309 3 9
+set_location ram_0311 3 11
+set_location ram_0313 3 13
+set_location ram_0315 3 15
+set_location ram_1001 10 1
+set_location ram_1003 10 3
+set_location ram_1005 10 5
+set_location ram_1007 10 7
+set_location ram_1009 10 9
+set_location ram_1011 10 11
+set_location ram_1013 10 13
+set_location ram_1015 10 15
diff --git a/icefuzz/tests/raminits.v b/icefuzz/tests/raminits.v
new file mode 100644
index 0000000..10d2f86
--- /dev/null
+++ b/icefuzz/tests/raminits.v
@@ -0,0 +1,490 @@
+// tmpfiles/ex_00.v
+module top (
+ input clk,
+ input [7:0] sel,
+ input [15:0] wdata,
+ output [15:0] rdata,
+ input [7:0] addr
+);
+ wire [15:0] rdata_0301;
+ SB_RAM256x16 ram_0301 (
+ .RDATA(rdata_0301),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 0),
+ .MASK(16'b0)
+ );
+defparam ram_0301.INIT_0 = 256'heee7d4195b1ee583e83766c47c4279255c36fac37ffa2db1c7978834c0a7b756;
+defparam ram_0301.INIT_1 = 256'haf36df1852690a6f4bd5a70c8cdc7ace32570591bdc9da916fdfebbf250ee920;
+defparam ram_0301.INIT_2 = 256'h062ec86b566ae81511bdb1c797b09358fd7b8b55a4033809181a8590636ebc4a;
+defparam ram_0301.INIT_3 = 256'he5647bccd28fcd7e1175dd08c07eee22b5f7a76ce80b814acc913a8bf6272489;
+defparam ram_0301.INIT_4 = 256'h847367636b8515d939efbb8e215509b3639c2d42650023fde29a300331ea02dd;
+defparam ram_0301.INIT_5 = 256'h1bfed331fc20e7d3855f6f57b704e77098ad9921daa03a251a0d4750cfdb8c5c;
+defparam ram_0301.INIT_6 = 256'h5796d45e174c10a14c1c6296d8e71d33a2601b790ac8ace68483a4095b8b2f2c;
+defparam ram_0301.INIT_7 = 256'h5c02f2a5a09d26529a93bdc1c3b2dad1edbdba8729e3ba1447b96a823b5e6ddb;
+defparam ram_0301.INIT_8 = 256'he6c0da7b269cb3b8213608a7c38a5eb224f7d37981f337e1b1f4e4aa13a330bc;
+defparam ram_0301.INIT_9 = 256'hd8aab74a136340b43c44e69b99233b7657c1faf8795e6e6513e399eccf835d64;
+defparam ram_0301.INIT_A = 256'h76da9bfa7def43d27b289046765ebad19bd9853133aa79e7a4c53b489266b78b;
+defparam ram_0301.INIT_B = 256'hd0be66fe7f334ca37b5cfa6fcfb84f2b5d7b556e3b179da25cb20a4bcf285dbc;
+defparam ram_0301.INIT_C = 256'he36823bd57f798408173ee4e1a138496a319039e28f783015ad938818b1ffeef;
+defparam ram_0301.INIT_D = 256'h19ad3217524d84a9eed19f6a88a3e6f6f3e27c256534dcefe6721a2eaf27e104;
+defparam ram_0301.INIT_E = 256'hbb5e5ef9246e61ee24121f2169dc1d755429486f030b7ae134f83c35915a2f44;
+defparam ram_0301.INIT_F = 256'hf0b5e781fb75db80882e0641026b6c4df0e61dd31d84c2f44bbe7073ccad1d01;
+ wire [15:0] rdata_0303;
+ SB_RAM256x16 ram_0303 (
+ .RDATA(rdata_0303),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 1),
+ .MASK(16'b0)
+ );
+defparam ram_0303.INIT_0 = 256'h2b668f5787aef8f5025f79512dcefc91d4bebc46513598e42c93d37c931d8923;
+defparam ram_0303.INIT_1 = 256'h7b9a84f2d5f65df84d4157495ab21e01e152dd7a886c33cb614e382e7fed9eab;
+defparam ram_0303.INIT_2 = 256'h878bdd512303597de1345a1cc680af906dabb3a7ad0ff50221288bce8af64881;
+defparam ram_0303.INIT_3 = 256'he36b5511c45aec1bba20d1791c3ccfa39cf93bde842f184cc1a93d70520529d6;
+defparam ram_0303.INIT_4 = 256'haf4b39a9fdfb42ccae9f2eea59845f5a8c2fb07035d64d71722f4d656b703c69;
+defparam ram_0303.INIT_5 = 256'h4c0cacce82085c0931587d9e7f4e6d074746cca6744b4a3b0ab1b54ec03fc84e;
+defparam ram_0303.INIT_6 = 256'he937cdb315288fbfdcaf1d77b698da022e5f6cf1b4fa3249d0d50eaf876466ae;
+defparam ram_0303.INIT_7 = 256'h1bd6d490c00964563d3f8438a32966a8f5de9447eae7b0e63dbf930d2dad4faa;
+defparam ram_0303.INIT_8 = 256'h55f0e909449d025ca05f81ffe6a71641b98694281522061a7d60fc84447395af;
+defparam ram_0303.INIT_9 = 256'h03cbdbbb3afb93d1360dc27ee9bc65b9dd407010717a2e5d5a2e6d7195875aef;
+defparam ram_0303.INIT_A = 256'hc8f9ceb334e4c22b1bfbd0321ab6762af2d10f9e67282aa4b3c0b4784c061708;
+defparam ram_0303.INIT_B = 256'h4a49021a4cf723dca9d9dba93f8ae9f3d5be64f54d61b5b40646bc8f11418390;
+defparam ram_0303.INIT_C = 256'hd579caee533c14990f0ef6e2307cbfd1252414b9384802fa7b434e40cc8b1f21;
+defparam ram_0303.INIT_D = 256'h17ff7be7f32b4e90a04b999795a68ecf923fd605ae58d82f9ddf78adfff85572;
+defparam ram_0303.INIT_E = 256'h41f8121524de634c0801dc5f8c04c8dec086b1f63d3e3a769c9cd63fd8132a72;
+defparam ram_0303.INIT_F = 256'h32d4549b468eba9a49fb496ff2d11b8e43d138b24a800e49853a6aba5bb5c5a2;
+ wire [15:0] rdata_0305;
+ SB_RAM256x16 ram_0305 (
+ .RDATA(rdata_0305),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 2),
+ .MASK(16'b0)
+ );
+defparam ram_0305.INIT_0 = 256'h172521cfcd66a4e54fdd281bea4e877d13357371970a607c4f1ec21bb92550c1;
+defparam ram_0305.INIT_1 = 256'h570a6f1ceb613a885a738b85084a55cf2e1d619a5392390c972d53e0b3c11f5d;
+defparam ram_0305.INIT_2 = 256'hb630e33faca35036486f0b8f94f0a4b21f804a2d82799ab121141b3ab1ba8df4;
+defparam ram_0305.INIT_3 = 256'haf7d9e3eb70911e8af4f2a1aad6cbfaa69248b89b36c222f7b1a5c32aa3844a4;
+defparam ram_0305.INIT_4 = 256'h273c5c3dcea0d9942168d6181aaaa30efbc3efd5fff73c7f30de4bdacd018779;
+defparam ram_0305.INIT_5 = 256'h559c7a4af1d4c9204d935d10817727b1ca5c554580e8b28dfc9e2fd6f2c71e77;
+defparam ram_0305.INIT_6 = 256'h418602bdff1e69af57af6a198e57a59c68443f3934fdd09ee68e630304166940;
+defparam ram_0305.INIT_7 = 256'h54aac47c7be964002b6c71aec829d69dc6ef2ee6f3640279b8c7f7947b4a2e61;
+defparam ram_0305.INIT_8 = 256'h32b50c21a7bdbdfac5909853b9d0fa8915dadc18f087070e30fba834d6eab209;
+defparam ram_0305.INIT_9 = 256'h02742ea4a2b626738ce04c7f6b4472739f981a7dd37413214228c9446ab320cb;
+defparam ram_0305.INIT_A = 256'h5c70fe89a21724eb2d36ded6fd01f47da78a97db0666e038cc5284ffaf5e66e1;
+defparam ram_0305.INIT_B = 256'h7ffdc072c4f7abc5888f3d30aa097195aa54f18635ad8308e08d3cda939db459;
+defparam ram_0305.INIT_C = 256'h159a2eaace991c51eb3c61abe9fe74af235d51f04ebabf0b2c0f0dfe6e3bb4e6;
+defparam ram_0305.INIT_D = 256'h460ded1b0a7f120b23cd292508e5a575fa8fd66f3033b69ab189e110fae0d668;
+defparam ram_0305.INIT_E = 256'hc72b4562d113f6f9c58ba44a7edf53b39b664357e12296fc389bd05d098311ee;
+defparam ram_0305.INIT_F = 256'h69bb7c5e08c96718f7ad092ba30a40c3b4347572251976ab0d1cae6bbac50333;
+ wire [15:0] rdata_0307;
+ SB_RAM256x16 ram_0307 (
+ .RDATA(rdata_0307),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 3),
+ .MASK(16'b0)
+ );
+defparam ram_0307.INIT_0 = 256'hf59c43dc52bc3d2b7bd85cd8c56aabb48969aae3721d16db0ff0524dabde709b;
+defparam ram_0307.INIT_1 = 256'heff0fb7181e53b6512b080104e27b8e18c62780045a8106caf69951ca6173db4;
+defparam ram_0307.INIT_2 = 256'hbfcb9c012c6c74f22b40ebe0369f994c9e409a65cd018bacb6dc6c3da36a6652;
+defparam ram_0307.INIT_3 = 256'h7ea21da12871042efd405fe9998f635050a02f99e9b802cfec48d38fe984f30a;
+defparam ram_0307.INIT_4 = 256'h5b659e0511fe236eb30e9fe92c5d69a637a10ab807a98eb567c2e914431a96fe;
+defparam ram_0307.INIT_5 = 256'h6a7816f542396924307d31d55501a35849b2531f4ca596a29e84cb3c650b4062;
+defparam ram_0307.INIT_6 = 256'he278bbc6ce05e58f6d15b005337aa2abdc6866ce8fc74cda53e9393909662f49;
+defparam ram_0307.INIT_7 = 256'h353257b35760e5d107ec73be367dbcef8e9d6f4c227f436758f569bc325ac59f;
+defparam ram_0307.INIT_8 = 256'h83609202f72286d35700331a86c68f0b1f20d8c0dd39bf0e7652cda584bec453;
+defparam ram_0307.INIT_9 = 256'hf24f9f1dca3539dcc73bd15a1c3b12e4f27d864325c1eb2f5f7c5e9ab0c6ec68;
+defparam ram_0307.INIT_A = 256'h2f41690287a95877a8637624974e1d779aa82daa7f1439733a7bcd7ee6a7d6df;
+defparam ram_0307.INIT_B = 256'h4d3e73056bebe5184c7fbacd65b2862c66c425d3b82ac573ab4b325035a9cff1;
+defparam ram_0307.INIT_C = 256'hf2dd4cf5279f86c413dc082dfc3b8e1dd913b59118dac6c99cde6e4a487316a2;
+defparam ram_0307.INIT_D = 256'haa901c2b6d47194f2157465b276bc2cb30c8af04f6372384f969e26235a1fc6b;
+defparam ram_0307.INIT_E = 256'h7cacd0b5a31ca17fdf94837ffa560342e9aa8ec69626dfd0b33b4df263d1fb88;
+defparam ram_0307.INIT_F = 256'h0da63678ff1980428f183ce9f9317dd0f2e0ad40f9c55b89342db6e18b832977;
+ wire [15:0] rdata_0309;
+ SB_RAM256x16 ram_0309 (
+ .RDATA(rdata_0309),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 4),
+ .MASK(16'b0)
+ );
+defparam ram_0309.INIT_0 = 256'h07a51489176ecf26b26ba3d3f4acb14b927e4f80c1a3333e79f52b87d0052eba;
+defparam ram_0309.INIT_1 = 256'he542c4ed986aef41e2c1f1f1e0eff957f5f7fe3c1a956f1b7e73f6c12c3e7b35;
+defparam ram_0309.INIT_2 = 256'h08e0d0315d86c998bfce1650d75c4cba11db471ff568d0ad39078ee3ad2dd5ae;
+defparam ram_0309.INIT_3 = 256'h0624c556f3b27168ca874071a2c037eba979cb6738a8983c26017669cd44f3f9;
+defparam ram_0309.INIT_4 = 256'h8f3727f57d00cdfdb0766c85a68bb59c52691d4b154bc2017cb2f0cf9deac2de;
+defparam ram_0309.INIT_5 = 256'he2d9ad2f0193ddb2ca738bed9d69fff0c4e181c5f6534a986fcb65d1756b0f5d;
+defparam ram_0309.INIT_6 = 256'hd28fc8443c5006206c35efd0fb2e0504f8d08f788e276b9f642d6837897906bc;
+defparam ram_0309.INIT_7 = 256'h9d25639c0a8e04cdb1fd5e02583734811a349e6ebfb3913e775e5fc09dbd8536;
+defparam ram_0309.INIT_8 = 256'h845c59e1f7c470abce8fa54120e38a9ff002c46c0eb2b651d3120627df47fa65;
+defparam ram_0309.INIT_9 = 256'h709ef0f92579008ec26a7bb4aa70870557693cc59c4e16347e23574429b1acaa;
+defparam ram_0309.INIT_A = 256'hd3553eac767b972d7cbec91901fdf203768c337577e599929a02788bab131ba2;
+defparam ram_0309.INIT_B = 256'hbcb398877ab4e802f93de666ee53147b4104a883e8fc58f704764bb0377457aa;
+defparam ram_0309.INIT_C = 256'hcb6bcd60cbeec7d69627cb56da8e829171c72a8f9ae075ca73146cb3bb33895f;
+defparam ram_0309.INIT_D = 256'hec0a7b61ca77b184a5da828074adee07b0bdaf9d3a75f0b4e496228906882c96;
+defparam ram_0309.INIT_E = 256'h4fcaff83f49c993e1344167d32660a6693a730fa2f29d5d4cab9063853bd7bbe;
+defparam ram_0309.INIT_F = 256'h0238e69d220727869654edd6fa05d2e9f17b82827fdf7e151d0078147fe5bdff;
+ wire [15:0] rdata_0311;
+ SB_RAM256x16 ram_0311 (
+ .RDATA(rdata_0311),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 5),
+ .MASK(16'b0)
+ );
+defparam ram_0311.INIT_0 = 256'h1e29fa340abb28a034d044905ef2b7aa08b76a1dafc7e743bdfc4fe88d77bb02;
+defparam ram_0311.INIT_1 = 256'h2fed2793ab9de32ba8d11df985a68371bdfb9564ccb8c12c63aa9c968b95b348;
+defparam ram_0311.INIT_2 = 256'hc3603ba144d8f2e8273b7762172a862f179e043fc755912fe840c60eb0aafc5f;
+defparam ram_0311.INIT_3 = 256'hbe3c00c259e270eec9ab5ca99a40653662bdc9ba0b0742eddc9da27441c29907;
+defparam ram_0311.INIT_4 = 256'h2effdb8a2a1ad09741d463bafe42d24e684e5c271cb64911f33651abb2554217;
+defparam ram_0311.INIT_5 = 256'h3d12ab8b32a2f8e90e616ba6136747522f6ef4b3ef3231750a6a6da587c46544;
+defparam ram_0311.INIT_6 = 256'hb9b1d4f05a71ca7bc92e7ef599655af7ca4abdc9a6bdb0ca6c9a1b2de1b67e6f;
+defparam ram_0311.INIT_7 = 256'ha2601f9d00bcab3ca1ec26151124156e6cf0f2c45f4761bdfb4f3ea6d0b9789c;
+defparam ram_0311.INIT_8 = 256'h16012927b00b193efde7ca215c88573280cea742d31623de3e0ed88b5a08e23c;
+defparam ram_0311.INIT_9 = 256'h5b1657e14902f7c08b6c154f96e04192d52439983d0a5c8810d0462f45d1c091;
+defparam ram_0311.INIT_A = 256'hdc67eaa704ff2aa09386be4dc9448074c427139cbb5118273a954a53838ffecf;
+defparam ram_0311.INIT_B = 256'h347c2253402c45890e871a1dbe53cd91e98b3cb4c1884c349e9536fcc1e5b53f;
+defparam ram_0311.INIT_C = 256'hc22e14b25ffdfb89a0556700e8171d0dfc84eb865898e6280cdbf0dbf51ec78c;
+defparam ram_0311.INIT_D = 256'h9fc88e0a32800fcb117c996b5dc252ec0256ccf1cecfccb0f2bfd5870219878c;
+defparam ram_0311.INIT_E = 256'h69df52b9aa92b8f75eb961cb77e1753ce5da5400f412bd36bc5c274a58fe17c2;
+defparam ram_0311.INIT_F = 256'h96dda78bb769a16e24ad1d9c34604b35c450c79d6fd2e51b28320a1bdd2408b0;
+ wire [15:0] rdata_0313;
+ SB_RAM256x16 ram_0313 (
+ .RDATA(rdata_0313),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 6),
+ .MASK(16'b0)
+ );
+defparam ram_0313.INIT_0 = 256'hd9559cc61e3f4571d58b14ea4740e577d14c30ebdf4f73b8c782f46f3b6c08d1;
+defparam ram_0313.INIT_1 = 256'h6f4efcd9b858d443ac63f0fd9225592fdba22f66c1eccb3714aa800ed71412ba;
+defparam ram_0313.INIT_2 = 256'h0ab1107b6d650fdf66add2cc2a7e488108161e3e651486f00ad50b3c070e68c3;
+defparam ram_0313.INIT_3 = 256'h37ffb1dc247db3f4b69ca946e62587246b0806f819735c9261c4cbfd46769b71;
+defparam ram_0313.INIT_4 = 256'hb436465a2f3a75b373c8a2013106750d96cd433c935988591a46c2cf947a4fc0;
+defparam ram_0313.INIT_5 = 256'h97752e46f2a5658b7a242904bbe1e26748ba95bf6f7e9a6ff72373e9a3f5dcc0;
+defparam ram_0313.INIT_6 = 256'h2f25d930c7bea790540df0b90418e26c86c58cba0f3cfd2e20c1adfafc8b58b9;
+defparam ram_0313.INIT_7 = 256'hf67a98264a755ad033da5a3f4f7bb0563a24c65f9e379e7ea24398ff770a1569;
+defparam ram_0313.INIT_8 = 256'h1a9d43cfcd1ae2142b2f35e8eb1f961e20f3488685a817ea0f7147abefe92821;
+defparam ram_0313.INIT_9 = 256'hb3c30dcac4dccdad0c7e14a9fa41edd57fb93a1560cfad9fffe812b476a66bcf;
+defparam ram_0313.INIT_A = 256'hda6c916c9a250420b9470d5bb5f4895bc65f83f3418d7872734951b3c89f8157;
+defparam ram_0313.INIT_B = 256'ha09ff972ebcbd082333bc97a4687b5b5f7b3a7939d7f4a6d3728cfa5a6599e93;
+defparam ram_0313.INIT_C = 256'h38eb42c565b9f9ebe0596a1fa9f9fc33836fca4058e1e20f60069ecbde0a1a05;
+defparam ram_0313.INIT_D = 256'h4beeab82252f2569fb56ffad4478db381e6b0d96b7f6d712c7073d8a118a5892;
+defparam ram_0313.INIT_E = 256'h0b48f12af2ff6febee038a01ae79d93cac9f09ac76501e43bb4817d39f1d043d;
+defparam ram_0313.INIT_F = 256'hdfbaa596a11d2248f849620d20cf3a6f856302c5bcc74dd6bfb3a756f59446c3;
+ wire [15:0] rdata_0315;
+ SB_RAM256x16 ram_0315 (
+ .RDATA(rdata_0315),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 7),
+ .MASK(16'b0)
+ );
+defparam ram_0315.INIT_0 = 256'h2af31f7e9493844389075cf4a347ad1ded317b44870c068432d89047eeca2b37;
+defparam ram_0315.INIT_1 = 256'hf51a6444eba4fb0b4baef416aa19593cf6ab473fe46255e53550cc8523ccb1fc;
+defparam ram_0315.INIT_2 = 256'h09f3a52d859af19ba525a62fccf0b64d03a86be72316ce8f38acb5959db215f5;
+defparam ram_0315.INIT_3 = 256'hfe309f2ae03cb8f724c01818371d5456ff5c9ef029f4806597554044d23fca5c;
+defparam ram_0315.INIT_4 = 256'h13bbbf3bb5e83b3200dde2fa4ef0566f4fcb2bee140ab81acf351cfad0a9d1cb;
+defparam ram_0315.INIT_5 = 256'h73b9f5bff710c59328c47ff675d8b68cdd2cfc07aa71d66b29ff98500b70e063;
+defparam ram_0315.INIT_6 = 256'h24d0607d548133d0f4e50d79b643fc604de016ca3d849c9e1fa5d70357f443c7;
+defparam ram_0315.INIT_7 = 256'hab53d6af5f0b3c6d7710bb402e21438013f3ac830c6405e219b3f114ad5b4db2;
+defparam ram_0315.INIT_8 = 256'h268b8fc89f948592c8e2fb38912dbd2bc88e67e820d03f5b4cf494491ac36816;
+defparam ram_0315.INIT_9 = 256'h846a486f199955e0852705305a805d5cece1647e839d3cd811a7a9d197f84815;
+defparam ram_0315.INIT_A = 256'h09007c4a495b836c16a082cd2418b2962059924230aa7729d1bb2be706283998;
+defparam ram_0315.INIT_B = 256'h336ee10a1530f40a98d338e2dceb777d8f6b456431c2267dcfda449bf5d28ed4;
+defparam ram_0315.INIT_C = 256'h1b16770684b88454ab9db7e40b07802b36d741eeacebc9d1648723b857f2ba4b;
+defparam ram_0315.INIT_D = 256'h9ccb7b57c9d5f4ac9eb293df84b6a124d1dde80bc7f262e38af79177e6520243;
+defparam ram_0315.INIT_E = 256'hab117e08b2b8ddcd7f68311478c2e018799685480835f1dc30b9159377ff2d69;
+defparam ram_0315.INIT_F = 256'hb05b0092e8d80ea1ff04a52f94d9b7f147f5651e8b624c1d800ce228e9db35e4;
+ wire [15:0] rdata_1001;
+ SB_RAM256x16 ram_1001 (
+ .RDATA(rdata_1001),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 8),
+ .MASK(16'b0)
+ );
+defparam ram_1001.INIT_0 = 256'h9c7c41b50768a605cf8152a411317da39cf38541b53e6cab1f59fd2ff79f1b29;
+defparam ram_1001.INIT_1 = 256'h2cb583fde53060648977748557fe9480afb7e331806f1955e4cb348795a15d4a;
+defparam ram_1001.INIT_2 = 256'hfc57e12bed42aa24b833f3f2e8a254f8d17dbaefde4ef4fa78f14f96bb248b1d;
+defparam ram_1001.INIT_3 = 256'h6fa44ad672bb75f06d5e00fe4d735e528400897f0eaec902ec089786e9e0968d;
+defparam ram_1001.INIT_4 = 256'h1ce5e5112b8ab585513bcb8ef393e593ddd5d0e76af31aaa4e815e680eea7d1d;
+defparam ram_1001.INIT_5 = 256'hc338e533ee20665b272c18f0b85424e41745d7649fad5736f68677b92feaba2c;
+defparam ram_1001.INIT_6 = 256'hf1ba42579571926ee12e8abbd287acf12d22a10caecce7b310dd7e75dde1bb7d;
+defparam ram_1001.INIT_7 = 256'hf4b97664ff2e90cb650c33d660c8e03898a7c0f608c58667867bb9f0c4042b77;
+defparam ram_1001.INIT_8 = 256'h03c5c843009d4ce9457a900cc6c45ca871bcf29e8c206b85bc1f7637e5afddd2;
+defparam ram_1001.INIT_9 = 256'hae78d5d9491ce25d1c833158e72dc0b440f91d1acce4bc33cddcf8a63885b8a6;
+defparam ram_1001.INIT_A = 256'hff813a16814de988dd1d99c902ccba4c070623d63935bc59ca9a54f8811d97b8;
+defparam ram_1001.INIT_B = 256'h0644e9960a194d65fed04e16f0f45d6ddf1aa911f13da01696dce1e5fdff6a9a;
+defparam ram_1001.INIT_C = 256'h93aa1fbc2c2f92dbec99d4e59741569b7a5fef853715af2e069b19fb50a1b934;
+defparam ram_1001.INIT_D = 256'hbdfc5a6a699eb6c6a6857c6b2ff4ef867084d4db40cdc5babd878ec8a5b9f0ea;
+defparam ram_1001.INIT_E = 256'h0d3751acaa17328f1e52fd4443755392bc4d20b626185b200c87677191df6259;
+defparam ram_1001.INIT_F = 256'h7772f629fcb9aff2a3318a98b9e4e58f44fd902bf544239968d748796577ca6a;
+ wire [15:0] rdata_1003;
+ SB_RAM256x16 ram_1003 (
+ .RDATA(rdata_1003),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 9),
+ .MASK(16'b0)
+ );
+defparam ram_1003.INIT_0 = 256'h52f7a59fb8d848aad51bd38121e11d5175b3239b971a8bcbd270d276e4f21f90;
+defparam ram_1003.INIT_1 = 256'h19a6611c09a950d1045425ecee7977d0f3bd3b70cce0ade0aa10f5fe3f15b1d3;
+defparam ram_1003.INIT_2 = 256'hff16259d190b5d0dd4453df81d9375dc1768e22673be4905fcc51f0f975e2cd1;
+defparam ram_1003.INIT_3 = 256'ha32a34f06674fd42bc1c9533c378d01b65cbce95a7200b64f9dde478cbb754b7;
+defparam ram_1003.INIT_4 = 256'hf6d4f68fd768de9aa637f5755cc3f64248d0f9866c5fcb00bd79be9d247243f8;
+defparam ram_1003.INIT_5 = 256'hb2411f4b8b21802fbce0082920a96856c9902897538f7068c10ebe6dca1ff7d6;
+defparam ram_1003.INIT_6 = 256'h2b3b94e10d954bc10b97e227f5b2c1c629e62166ed06c2347bfb2fa4a44010ea;
+defparam ram_1003.INIT_7 = 256'hff82fa877fbf9802434a2f8f8eff7a18e6b9ad444f736c1592db47627146289e;
+defparam ram_1003.INIT_8 = 256'hfced2cd513690efbd52ded9fe01bb809a8d2b048326d0e7559d8c181cf6d075f;
+defparam ram_1003.INIT_9 = 256'hba7672c199d70b9d2b3d5c980aad280086feeacbe16077b94941ac9ebe9c7aa4;
+defparam ram_1003.INIT_A = 256'heb9d91de7a2ffabce82eead39a8ee44eb1b65a7274ead34013422c9f7cb0bcd7;
+defparam ram_1003.INIT_B = 256'h2fbc5beec9c515ca4d0186e649eb7475e5170e7ea4b6e0e3de09f96b98a4216c;
+defparam ram_1003.INIT_C = 256'hd146f604f32aea162557efc77e070a9edbbad0d276024acf16d1a5dd4629d48d;
+defparam ram_1003.INIT_D = 256'h445080680263cbe9b1dec849f5dba0449c1a105981a3ad167e346303742edf2f;
+defparam ram_1003.INIT_E = 256'h0527a9fbf0a68e910b8589e3bb1efa281615e6857d5cdb78ece71aeb9f69de3d;
+defparam ram_1003.INIT_F = 256'h9282f9309931634a765f52b8eec225c309549d9a1045a9b700831ab3468223de;
+ wire [15:0] rdata_1005;
+ SB_RAM256x16 ram_1005 (
+ .RDATA(rdata_1005),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 10),
+ .MASK(16'b0)
+ );
+defparam ram_1005.INIT_0 = 256'h0776006ec4d03f7a5c73c6057f7bbb99f7edd3d8a12be2e3861cd69aa1bc525c;
+defparam ram_1005.INIT_1 = 256'hf24b4a0303bece261707dd7962cd9ab47513d64b793224f15562b4c4d72ec72c;
+defparam ram_1005.INIT_2 = 256'hd30dbc4325341cdd5dcfb3d5f9410e1519c20e4b16d74676e855324ccd67af40;
+defparam ram_1005.INIT_3 = 256'h4a60c84b1172429d7d8a0b7bbefc3e626e25187906cd7e14e1c316ac7e9ed288;
+defparam ram_1005.INIT_4 = 256'h9d1c20f207820f24ba23a74a0da804ec13f8a1b7ed61e5a644c79e5932782489;
+defparam ram_1005.INIT_5 = 256'ha2f4c117c4d10358b1b04ab329706816dce90617ee78102870d29889a7660488;
+defparam ram_1005.INIT_6 = 256'h22b667287f6fed4bfee9b16292dc9c8123a2ab5dcfa8fefdfcedfe2cb1869519;
+defparam ram_1005.INIT_7 = 256'hddfb1d4815eaa10a75bde6c4799ef3e1d4c0812fa1d808083bc054d21b3655f0;
+defparam ram_1005.INIT_8 = 256'h6bebae5c4efe1bdf465dda9e4ca89a3a78d985462f017150b8f9d36783fc27d3;
+defparam ram_1005.INIT_9 = 256'hde7dd3ae6e92319591c5d8647f2e51d38d1b0cad7683fd870d63f55fca8a1524;
+defparam ram_1005.INIT_A = 256'hd27e172a81e83608bbc9ea610f3801d47a54d14a5309a4847f14abceda8fecb9;
+defparam ram_1005.INIT_B = 256'ha151d1f63317c4515c9f5773a7e5812a3906738b26b9a9447ec9aceb93fe5636;
+defparam ram_1005.INIT_C = 256'ha43c9e64daef57c028270e426fa141aa96209263021ae9d0c78fd98f9c148954;
+defparam ram_1005.INIT_D = 256'h40d7f09924ea37080c9b7243c18c25243eeef757b2ddf45cd90f1552f2dc67f4;
+defparam ram_1005.INIT_E = 256'hf09c320f602b1fa8d8321d0554a8a6613a67f43747362b7f5e2881a27d943bec;
+defparam ram_1005.INIT_F = 256'h86a034c22751bb658bb02c3d653e7f3af4f1d23807a5d0850342092825c678d7;
+ wire [15:0] rdata_1007;
+ SB_RAM256x16 ram_1007 (
+ .RDATA(rdata_1007),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 11),
+ .MASK(16'b0)
+ );
+defparam ram_1007.INIT_0 = 256'h4e39bcdedc4225f725553e52a5ac856ffce7ec677b03371f5cfcbdc088d25d3e;
+defparam ram_1007.INIT_1 = 256'h3ae63a363e292263c3767b69693f590967b4a51b7545ef66197a9e81340625f4;
+defparam ram_1007.INIT_2 = 256'hd143d96571dcf7c28197a18318537b93c8fcf207cbc9c28b02e6891faa1d2060;
+defparam ram_1007.INIT_3 = 256'hd4cccc72f0bc14361256a0860cf83c4036056951417bd9e9c36bb443da137a45;
+defparam ram_1007.INIT_4 = 256'h19fdfb40c38ba5c327ec0e928aa904b3c82003e48245d6665ea30e6de59d95b5;
+defparam ram_1007.INIT_5 = 256'h1955f4d9c2eb2e65e772a58e15b472caa748bcdfe36ff847d6b40e3144fbeec3;
+defparam ram_1007.INIT_6 = 256'h1731ac85d13545f4d691a4c6b53833936ba7bf84be95a37682d3d7e8f46105ae;
+defparam ram_1007.INIT_7 = 256'hff2e1b21202bc8d4e6d0924ec4f3d650c383ddecef63c838ec35fdcdbfff217a;
+defparam ram_1007.INIT_8 = 256'h6cba3ae658a500c33b92d92896b897b356daf59a114db811c6386201d9933a04;
+defparam ram_1007.INIT_9 = 256'hfc3a2543ec498d95e4d91a702c848c7ac8bbd9a2e427f73c9103bf231eed364f;
+defparam ram_1007.INIT_A = 256'h93e1884aeb0366366c841e1f542598c2bd8b2cf31f73055007bc12d74164191b;
+defparam ram_1007.INIT_B = 256'hec77a7c083657e4af9e587b26a41f9951cbc47a4998066a06fbef31e4c703a84;
+defparam ram_1007.INIT_C = 256'h2fe468d39c8459102279bb9b4ee58b644a36bf6473591f8ef3cbba2a994869ba;
+defparam ram_1007.INIT_D = 256'h83776c239ddd7de3a1578433608dc6a4469bf2d56f488f12b726d8ce919ea9d2;
+defparam ram_1007.INIT_E = 256'h3fdc7c39c3d78e24f206100c593ae13f3504e3fdb51d0c1e0ee8deb94c2e56f8;
+defparam ram_1007.INIT_F = 256'h0cf5c0b04f44cb998f2666e53fb0821fce4cd86a56cf0d9294c63badae74ea58;
+ wire [15:0] rdata_1009;
+ SB_RAM256x16 ram_1009 (
+ .RDATA(rdata_1009),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 12),
+ .MASK(16'b0)
+ );
+defparam ram_1009.INIT_0 = 256'h00dd22ab72977ee266ff25412fb075db016baeca9f13968d4616a585eee3090a;
+defparam ram_1009.INIT_1 = 256'h13e38c740dfa42a0dd7630edf82bec6afc3e4444a24e308b45899e5c2179aa53;
+defparam ram_1009.INIT_2 = 256'h46074c8da907cd884cf6a0d6c8f42c68d5aaeade7159ac472a3846993f283607;
+defparam ram_1009.INIT_3 = 256'h6e9a5cdcc076f56aea6b66f2423f485b78289ed5c6192a7b88de6b149a0bcc77;
+defparam ram_1009.INIT_4 = 256'hba3d1385e32eab4b82370495b8d90f5751a6dc1da47d33e82fef50b08904afa8;
+defparam ram_1009.INIT_5 = 256'h070b3ab69f1e5ff13022fd403e3197f363bcf4b926a12265e8e7143b9ce57bff;
+defparam ram_1009.INIT_6 = 256'h54e43106537fc4a6ee059ca2e4608f1ddf4c225a60c46b4b8c5aad9c0140e6e3;
+defparam ram_1009.INIT_7 = 256'hf54a84ac1112cce38092c8ab9dc372da803fb1043313a44bc09e0ae9870882de;
+defparam ram_1009.INIT_8 = 256'h7bea9c49dfce264c2887a4d75f8401384d3ecd8f4126ba767b0f559e9bc27589;
+defparam ram_1009.INIT_9 = 256'hd83372f53ac2c6174a64540ebc7c0a604d6d739f6f7ec5c7c217b0f42ff28ce4;
+defparam ram_1009.INIT_A = 256'h225c6c8d155ddc900609375ff62e940face07ecd4700b9a58e31f79ad4177031;
+defparam ram_1009.INIT_B = 256'h6f3934aeb7cb9b817f7a1e742cd2b64c077f7b394ac65fcc5d67f2b13ef402ef;
+defparam ram_1009.INIT_C = 256'h4634285a3fe505d87689ddd607abe8942354d1ff1ab96bbda0e3992cc51827f2;
+defparam ram_1009.INIT_D = 256'h8f5ba84568337a4c48dd650d26e7774062012636b6be06c3d084e9e69505669d;
+defparam ram_1009.INIT_E = 256'h9c8362ebbd6cdb77941d8dcc2cd9975ecf45bdab9cd5c6c6d96cd12439ba3416;
+defparam ram_1009.INIT_F = 256'h6ac567c655b53b93d3dd0718c2bed6419eff6bb310b4865c1115d7d6a18dbe39;
+ wire [15:0] rdata_1011;
+ SB_RAM256x16 ram_1011 (
+ .RDATA(rdata_1011),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 13),
+ .MASK(16'b0)
+ );
+defparam ram_1011.INIT_0 = 256'h362c2d793cc2cbefa8f0856599ae3092fc9d1899af1176c56cf4af5204ceff43;
+defparam ram_1011.INIT_1 = 256'h24a47c459b500efbdbade11495dc1563d0eb10d855e616d158903f42c85f9d7f;
+defparam ram_1011.INIT_2 = 256'h22dcae4b4ea436cfcfab001745d46d018985b37ca8967cfa1acd8092b04b8f54;
+defparam ram_1011.INIT_3 = 256'hafc84dc99ccba1a754e8891edcd82ef3bb3b2c3ae1cb1ec0a14f572c60d12f08;
+defparam ram_1011.INIT_4 = 256'h904aa0e37fa6c8da80ef6a8494b730ce7e422c4cf13aa527573671d153cf7ce1;
+defparam ram_1011.INIT_5 = 256'h03f03529f73ed23835562295897065dee7cf99f593ccef4c545193d867ac7e08;
+defparam ram_1011.INIT_6 = 256'h5d2fd0e50390eccf5322efa530c77ef20d5807ae44138ca9d55c7eb221c4a3ed;
+defparam ram_1011.INIT_7 = 256'h5ecf2c470973a0d8a192a9aebb1fc0634a2bc4ad471a81a56dbef77148acc224;
+defparam ram_1011.INIT_8 = 256'hb729ece2b3ebf4a36f769a6fa20a6e78f448a15ae707f593097b6d2aecaa6948;
+defparam ram_1011.INIT_9 = 256'h0af41c521d3c94c64b76a424110a8d95fba2b51dbf72b0b34806cb2a1088fd7e;
+defparam ram_1011.INIT_A = 256'h65f51a767a25bcf8c8b922d2291a81cb43d8fd14c4f28e3f6211e685cf6bf659;
+defparam ram_1011.INIT_B = 256'h525643b65c204fbc4784701c8d27bc7272d622ce3b95f6cfc3dd99df69cb3b8e;
+defparam ram_1011.INIT_C = 256'ha60853f8e9d0e538e106184173fdc70b496cc3048e65f3378e0b740b76bf594f;
+defparam ram_1011.INIT_D = 256'h8359c3bc1e7be748e9e74c42b2ac4ff44fa6e1a5cd485e18bf2f1674d76fc7ad;
+defparam ram_1011.INIT_E = 256'h19868c5139623b8823c1f62d69ba80469415a6766cb8c4e5827ada6e7b2c107c;
+defparam ram_1011.INIT_F = 256'h1c7f1dd62f29a97250327ce5d9909876004e17f1532a2d218a67980a03ded845;
+ wire [15:0] rdata_1013;
+ SB_RAM256x16 ram_1013 (
+ .RDATA(rdata_1013),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 14),
+ .MASK(16'b0)
+ );
+defparam ram_1013.INIT_0 = 256'h1c9b05f5062cf4c25ddeeac8024576874c7989e717a11770dca3747f29ae514a;
+defparam ram_1013.INIT_1 = 256'h13cfb7cc84ef05f07fc8f83085878e6aab399c88815116dc4ad2f7c4cea680e2;
+defparam ram_1013.INIT_2 = 256'h50b45abe6c1f167f5bccf97db6d7251da4321990172d4897804947f434e79b1c;
+defparam ram_1013.INIT_3 = 256'hb2a152c418006c4a0e7bcc961cacaf37eedbb38830633b7fe3a124f7795f58e6;
+defparam ram_1013.INIT_4 = 256'hc8b596be79c27aa527c94de1cee75f50e13465f1031d4f6e88866f2adb61806f;
+defparam ram_1013.INIT_5 = 256'hcb2b6636db3b635aadfd796a226f128ff3d2005b501abee63f9caa1116367044;
+defparam ram_1013.INIT_6 = 256'hfd2255e9d120bfd3df10e0dd1f3488243e58bf85058a960d9767ae3176090494;
+defparam ram_1013.INIT_7 = 256'hdc0aec0de8936cc5843863a55f7d60326be11898381a27151ee3ba699a4e8d6d;
+defparam ram_1013.INIT_8 = 256'h5219e84d5be7ff41723580327bf1d2931ebff70ac32a3219066af7ebe5b6d1d2;
+defparam ram_1013.INIT_9 = 256'hcb5029f958e66f0e3d1b1b9df273b9131bc1d10abe226c03de9b15ff5ff9e282;
+defparam ram_1013.INIT_A = 256'h02637bb03a384463fee3a500ca6b4614e19db03d8eec5214540767a13f4218d1;
+defparam ram_1013.INIT_B = 256'h1d83eee108d925f34f15f03269d685d1132a5aa102f8a49ba0d216d4a2de5858;
+defparam ram_1013.INIT_C = 256'h5b354f004e9a7d40dd6f4b38b9d258c6718a6db339eb23d591e96b31b4ffed14;
+defparam ram_1013.INIT_D = 256'hc1c1c526ea60690e3bbf2bce2989a12e3deb4dcafc2818b37a591a15bc6fe402;
+defparam ram_1013.INIT_E = 256'hc08c14e42ac9e3175d2c2ae617d71f3aac4c18ab51f4827f491bd8c7109c3db0;
+defparam ram_1013.INIT_F = 256'h50929c51c7d605a973c3f518850e9ecc133cffd13a9942a69317b566dba8e78e;
+ wire [15:0] rdata_1015;
+ SB_RAM256x16 ram_1015 (
+ .RDATA(rdata_1015),
+ .RADDR(addr),
+ .RCLK(clk),
+ .RCLKE(1'b1),
+ .RE(1'b1),
+ .WADDR(addr),
+ .WCLK(clk),
+ .WCLKE(1'b1),
+ .WDATA(wdata),
+ .WE(sel == 15),
+ .MASK(16'b0)
+ );
+defparam ram_1015.INIT_0 = 256'h12be2212ed14b2640338f81dff4108d4ac3bf1e6a03d7a29cac03cfe50e1bff8;
+defparam ram_1015.INIT_1 = 256'hf485c1d5ad53c47a71709a5fb8cfcbc329f0e18b7178c13872b52c7c6a285ce4;
+defparam ram_1015.INIT_2 = 256'h0f7b97d175c184936b7626f2402e106ec7a53b31b97f05b87b224270da05e334;
+defparam ram_1015.INIT_3 = 256'heb2844df6eb99634216dfe81c6287f7c55d047b08034e4c32b1d824d10c64fe0;
+defparam ram_1015.INIT_4 = 256'ha28fff103cf00d3a51939c8eb633d49ed059a79bb70253ef6a145fa0fba30636;
+defparam ram_1015.INIT_5 = 256'he8ac62e181b16da21e581e88f0a9faf89d14e1e2e1013d7522705f7dd64d2de4;
+defparam ram_1015.INIT_6 = 256'h7b90b08c103dd63a3c5423a7ee83d6a144fbf40c6fb04befa7e116b1b8a5d6b6;
+defparam ram_1015.INIT_7 = 256'h6d5eae0464fff912dcde27536baa0ce0831c559a90f63df5d7dc9c2ac9cd82a2;
+defparam ram_1015.INIT_8 = 256'hff802d46b492cf02aff2dc259541586414f67b86fc8c4114969f39702d29830e;
+defparam ram_1015.INIT_9 = 256'h7078b25fbb5914cd4dfc3c391beb54a2c47baabae73f3ee4da1b64cf7767be72;
+defparam ram_1015.INIT_A = 256'hfc517c45f85fb461e326f7a886cebeb6c977d0b285b42d1ca35042cafadee9e3;
+defparam ram_1015.INIT_B = 256'h5519034f258fa5c885ea5cf8d67b379a55859ae6b38f12236e559c4b19972731;
+defparam ram_1015.INIT_C = 256'hcf4251d73f1054d3986f2ac746ac44d4e0e9a0b4f179126262ffef39f4ba1756;
+defparam ram_1015.INIT_D = 256'h3cd68370c54a6b68802813bb1a3181ad13166a324cf1c3eba85f8651664dde8a;
+defparam ram_1015.INIT_E = 256'h8a0896ac480c525a1c702b9856da6163328b36a3ec5c2e13bc07656b71bd1575;
+defparam ram_1015.INIT_F = 256'hdbccace4967a5bbacc70d66dd227a1fbd11062e04cc1cb91d6d0dcd9750fd1b7;
+assign rdata = sel == 0 ? rdata_0301 : sel == 1 ? rdata_0303 : sel == 2 ? rdata_0305 : sel == 3 ? rdata_0307 : sel == 4 ? rdata_0309 : sel == 5 ? rdata_0311 : sel == 6 ? rdata_0313 : sel == 7 ? rdata_0315 : sel == 8 ? rdata_1001 : sel == 9 ? rdata_1003 : sel == 10 ? rdata_1005 : sel == 11 ? rdata_1007 : sel == 12 ? rdata_1009 : sel == 13 ? rdata_1011 : sel == 14 ? rdata_1013 : sel == 15 ? rdata_1015 : 0;
+endmodule
diff --git a/icefuzz/tests/sb_dff.v b/icefuzz/tests/sb_dff.v
new file mode 100644
index 0000000..4a680b1
--- /dev/null
+++ b/icefuzz/tests/sb_dff.v
@@ -0,0 +1,3 @@
+module top (input C, D, output Q);
+ SB_DFF ff (.C(C), .D(D), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffe.v b/icefuzz/tests/sb_dffe.v
new file mode 100644
index 0000000..b707d77
--- /dev/null
+++ b/icefuzz/tests/sb_dffe.v
@@ -0,0 +1,3 @@
+module top (input C, D, E, output Q);
+ SB_DFFE ff (.C(C), .D(D), .E(E), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffer.v b/icefuzz/tests/sb_dffer.v
new file mode 100644
index 0000000..6d05c7e
--- /dev/null
+++ b/icefuzz/tests/sb_dffer.v
@@ -0,0 +1,3 @@
+module top (input C, D, E, R, output Q);
+ SB_DFFER ff (.C(C), .D(D), .E(E), .R(R), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffes.v b/icefuzz/tests/sb_dffes.v
new file mode 100644
index 0000000..e1d7a13
--- /dev/null
+++ b/icefuzz/tests/sb_dffes.v
@@ -0,0 +1,3 @@
+module top (input C, D, E, S, output Q);
+ SB_DFFES ff (.C(C), .D(D), .E(E), .S(S), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffesr.v b/icefuzz/tests/sb_dffesr.v
new file mode 100644
index 0000000..51acc95
--- /dev/null
+++ b/icefuzz/tests/sb_dffesr.v
@@ -0,0 +1,3 @@
+module top (input C, D, E, R, output Q);
+ SB_DFFESR ff (.C(C), .D(D), .E(E), .R(R), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffess.v b/icefuzz/tests/sb_dffess.v
new file mode 100644
index 0000000..de78c28
--- /dev/null
+++ b/icefuzz/tests/sb_dffess.v
@@ -0,0 +1,3 @@
+module top (input C, D, E, S, output Q);
+ SB_DFFESS ff (.C(C), .D(D), .E(E), .S(S), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffr.v b/icefuzz/tests/sb_dffr.v
new file mode 100644
index 0000000..aa3ccc4
--- /dev/null
+++ b/icefuzz/tests/sb_dffr.v
@@ -0,0 +1,3 @@
+module top (input C, D, R, output Q);
+ SB_DFFR ff (.C(C), .D(D), .R(R), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffs.v b/icefuzz/tests/sb_dffs.v
new file mode 100644
index 0000000..e81b920
--- /dev/null
+++ b/icefuzz/tests/sb_dffs.v
@@ -0,0 +1,3 @@
+module top (input C, D, S, output Q);
+ SB_DFFS ff (.C(C), .D(D), .S(S), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffsr.v b/icefuzz/tests/sb_dffsr.v
new file mode 100644
index 0000000..48cc7f2
--- /dev/null
+++ b/icefuzz/tests/sb_dffsr.v
@@ -0,0 +1,3 @@
+module top (input C, D, R, output Q);
+ SB_DFFSR ff (.C(C), .D(D), .R(R), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_dffss.v b/icefuzz/tests/sb_dffss.v
new file mode 100644
index 0000000..fb797bc
--- /dev/null
+++ b/icefuzz/tests/sb_dffss.v
@@ -0,0 +1,3 @@
+module top (input C, D, S, output Q);
+ SB_DFFSS ff (.C(C), .D(D), .S(S), .Q(Q));
+endmodule
diff --git a/icefuzz/tests/sb_gb.v b/icefuzz/tests/sb_gb.v
new file mode 100644
index 0000000..f71e594
--- /dev/null
+++ b/icefuzz/tests/sb_gb.v
@@ -0,0 +1,9 @@
+module top (
+ input [7:0] a,
+ output [7:0] y
+);
+ SB_GB gbufs [7:0] (
+ .USER_SIGNAL_TO_GLOBAL_BUFFER(a),
+ .GLOBAL_BUFFER_OUTPUT(y)
+ );
+endmodule
diff --git a/icefuzz/tests/sb_gb_io.v b/icefuzz/tests/sb_gb_io.v
new file mode 100644
index 0000000..ed78e6e
--- /dev/null
+++ b/icefuzz/tests/sb_gb_io.v
@@ -0,0 +1,32 @@
+module top (
+ inout [7:0] pin,
+ input latch_in,
+ input clk_en,
+ input clk_in,
+ input clk_out,
+ input oen,
+ input dout_0,
+ input dout_1,
+ output [7:0] din_0,
+ output [7:0] din_1,
+ output [7:0] globals
+);
+ SB_GB_IO #(
+ .PIN_TYPE(6'b 1100_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) PINS [7:0] (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(clk_en),
+ .INPUT_CLK(clk_in),
+ .OUTPUT_CLK(clk_out),
+ .OUTPUT_ENABLE(oen),
+ .D_OUT_0(dout_0),
+ .D_OUT_1(dout_1),
+ .D_IN_0(din_0),
+ .D_IN_1(din_1),
+ .GLOBAL_BUFFER_OUTPUT(globals)
+ );
+endmodule
diff --git a/icefuzz/tests/sb_io.pcf b/icefuzz/tests/sb_io.pcf
new file mode 100644
index 0000000..a050b00
--- /dev/null
+++ b/icefuzz/tests/sb_io.pcf
@@ -0,0 +1,12 @@
+# set_io pin 1
+set_io pin 2
+
+# set_io pin
+# set_io latch_in
+# set_io clk_in
+# set_io clk_out
+# set_io oen
+# set_io dout_0
+# set_io dout_1
+# set_io din_0
+# set_io din_1
diff --git a/icefuzz/tests/sb_io.v b/icefuzz/tests/sb_io.v
new file mode 100644
index 0000000..83a56cf
--- /dev/null
+++ b/icefuzz/tests/sb_io.v
@@ -0,0 +1,64 @@
+`define CONN_INTERNAL_BITS
+
+`define PINTYPE 6'b010000
+// `define IOSTANDARD "SB_LVCMOS"
+`define IOSTANDARD "SB_LVDS_INPUT"
+
+// The following IO standards are just aliases for SB_LVCMOS
+// `define IOSTANDARD "SB_LVCMOS25_16"
+// `define IOSTANDARD "SB_LVCMOS25_12"
+// `define IOSTANDARD "SB_LVCMOS25_8"
+// `define IOSTANDARD "SB_LVCMOS25_4"
+// `define IOSTANDARD "SB_LVCMOS18_10"
+// `define IOSTANDARD "SB_LVCMOS18_8"
+// `define IOSTANDARD "SB_LVCMOS18_4"
+// `define IOSTANDARD "SB_LVCMOS18_2"
+// `define IOSTANDARD "SB_LVCMOS15_4"
+// `define IOSTANDARD "SB_LVCMOS15_2"
+// `define IOSTANDARD "SB_MDDR10"
+// `define IOSTANDARD "SB_MDDR8"
+// `define IOSTANDARD "SB_MDDR4"
+// `define IOSTANDARD "SB_MDDR2"
+
+`ifdef CONN_INTERNAL_BITS
+module top (
+ inout pin,
+ input latch_in,
+ input clk_in,
+ input clk_out,
+ input oen,
+ input dout_0,
+ input dout_1,
+ output din_0,
+ output din_1
+);
+`else
+module top(pin);
+ inout pin;
+ wire latch_in = 0;
+ wire clk_in = 0;
+ wire clk_out = 0;
+ wire oen = 0;
+ wire dout_0 = 0;
+ wire dout_1 = 0;
+ wire din_0;
+ wire din_1;
+`endif
+ SB_IO #(
+ .PIN_TYPE(`PINTYPE),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD(`IOSTANDARD)
+ ) IO_PIN_I (
+ .PACKAGE_PIN(pin),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(clk_en),
+ .INPUT_CLK(clk_in),
+ .OUTPUT_CLK(clk_out),
+ .OUTPUT_ENABLE(oen),
+ .D_OUT_0(dout_0),
+ .D_OUT_1(dout_1),
+ .D_IN_0(din_0),
+ .D_IN_1(din_1)
+ );
+endmodule
diff --git a/icefuzz/tests/sb_io_negclk.pcf b/icefuzz/tests/sb_io_negclk.pcf
new file mode 100644
index 0000000..00df4f0
--- /dev/null
+++ b/icefuzz/tests/sb_io_negclk.pcf
@@ -0,0 +1,2 @@
+set_io pin1 1
+set_io pin2 2
diff --git a/icefuzz/tests/sb_io_negclk.v b/icefuzz/tests/sb_io_negclk.v
new file mode 100644
index 0000000..f37f9d2
--- /dev/null
+++ b/icefuzz/tests/sb_io_negclk.v
@@ -0,0 +1,39 @@
+module top(input clk, inout pin1, inout pin2);
+ wire w;
+
+ SB_IO #(
+ .PIN_TYPE(6'b 0101_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b1),
+ .IO_STANDARD("SB_LVCMOS")
+ ) IO_PIN_1 (
+ .PACKAGE_PIN(pin1),
+ .LATCH_INPUT_VALUE(),
+ .CLOCK_ENABLE(),
+ .INPUT_CLK(clk),
+ .OUTPUT_CLK(clk),
+ .OUTPUT_ENABLE(),
+ .D_OUT_0(1'b0),
+ .D_OUT_1(1'b0),
+ .D_IN_0(w),
+ .D_IN_1()
+ );
+
+ SB_IO #(
+ .PIN_TYPE(6'b 0101_00),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b1),
+ .IO_STANDARD("SB_LVCMOS")
+ ) IO_PIN_2 (
+ .PACKAGE_PIN(pin2),
+ .LATCH_INPUT_VALUE(),
+ .CLOCK_ENABLE(),
+ .INPUT_CLK(clk),
+ .OUTPUT_CLK(clk),
+ .OUTPUT_ENABLE(),
+ .D_OUT_0(w),
+ .D_OUT_1(1'b0),
+ .D_IN_0(),
+ .D_IN_1()
+ );
+endmodule
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_core.v
new file mode 100644
index 0000000..298fb73
--- /dev/null
+++ b/icefuzz/tests/sb_pll40_core.v
@@ -0,0 +1,67 @@
+module top(
+ input REFERENCECLK,
+ output [1:0] PLLOUTCORE,
+ output [1:0] PLLOUTGLOBAL,
+ input EXTFEEDBACK,
+ input [7:0] DYNAMICDELAY,
+ output LOCK,
+ input BYPASS,
+ input RESETB,
+ input LATCHINPUTVALUE,
+
+ //Test Pins
+ output SDO,
+ input SDI,
+ input SCLK
+);
+ SB_PLL40_2F_CORE #(
+ .FEEDBACK_PATH("DELAY"),
+ // .FEEDBACK_PATH("SIMPLE"),
+ // .FEEDBACK_PATH("PHASE_AND_DELAY"),
+ // .FEEDBACK_PATH("EXTERNAL"),
+
+ .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
+
+ .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
+ // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
+
+ .PLLOUT_SELECT_PORTA("GENCLK"),
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+
+ // .PLLOUT_SELECT("GENCLK"),
+ // .PLLOUT_SELECT("GENCLK_HALF"),
+ // .PLLOUT_SELECT("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT("SHIFTREG_0deg"),
+
+ .SHIFTREG_DIV_MODE(1'b0),
+ .FDA_FEEDBACK(4'b1111),
+ .FDA_RELATIVE(4'b1111),
+ .DIVR(4'b0000),
+ .DIVF(7'b0000000),
+ .DIVQ(3'b001),
+ .FILTER_RANGE(3'b000),
+ // .ENABLE_ICEGATE(1'b0),
+ .ENABLE_ICEGATE_PORTA(1'b0),
+ .ENABLE_ICEGATE_PORTB(1'b0),
+ .TEST_MODE(1'b0)
+ ) uut (
+ .REFERENCECLK (REFERENCECLK ),
+ // .PACKAGEPIN (REFERENCECLK ),
+ // .PLLOUTCORE (PLLOUTCORE ),
+ // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
+ .PLLOUTCOREA (PLLOUTCORE [0]),
+ .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
+ .PLLOUTCOREB (PLLOUTCORE [1]),
+ .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .EXTFEEDBACK (EXTFEEDBACK ),
+ .DYNAMICDELAY (DYNAMICDELAY ),
+ .LOCK (LOCK ),
+ .BYPASS (BYPASS ),
+ .RESETB (RESETB ),
+ .LATCHINPUTVALUE(LATCHINPUTVALUE),
+ .SDO (SDO ),
+ .SDI (SDI ),
+ .SCLK (SCLK )
+ );
+endmodule
diff --git a/icefuzz/tests/sb_ram40.pcf b/icefuzz/tests/sb_ram40.pcf
new file mode 100644
index 0000000..f6f4d20
--- /dev/null
+++ b/icefuzz/tests/sb_ram40.pcf
@@ -0,0 +1,4 @@
+set_location lut 7 21 0
+set_location ram40_00 8 21 0
+set_location ram40_12 8 19 0
+set_location ram40_33 8 17 0
diff --git a/icefuzz/tests/sb_ram40.v b/icefuzz/tests/sb_ram40.v
new file mode 100644
index 0000000..3516593
--- /dev/null
+++ b/icefuzz/tests/sb_ram40.v
@@ -0,0 +1,80 @@
+// ICEDEV=hx8k-ct256 bash ../icecube.sh sb_ram40.v
+// ../../icebox/icebox_vlog.py -P sb_ram40.psb sb_ram40.txt
+// ../../icebox/icebox_explain.py -t '7 21' sb_ram40.txt
+
+module top (
+ input [10:0] WADDR,
+ input [10:0] RADDR,
+ input [15:0] MASK,
+ input [15:0] WDATA,
+ output [15:0] RDATA_0,
+ output [ 7:0] RDATA_1,
+ output [ 1:0] RDATA_3,
+ input WE, WCLKE, WCLK,
+ input RE, RCLKE, RCLK,
+ output X
+);
+ // Write Mode 0: 8 Bit ADDR, 16 Bit DATA, MASK
+ // Write Mode 1: 9 Bit ADDR, 8 Bit DATA, NO MASK
+ // Write Mode 2: 10 Bit ADDR, 4 Bit DATA, NO MASK
+ // Write Mode 3: 11 Bit ADDR, 2 Bit DATA, NO MASK
+
+ SB_RAM40_4K #(
+ .READ_MODE(0),
+ .WRITE_MODE(0)
+ ) ram40_00 (
+ .WADDR(WADDR[7:0]),
+ .RADDR(RADDR[7:0]),
+ .MASK(MASK),
+ .WDATA(WDATA),
+ .RDATA(RDATA_0),
+ .WE(WE),
+ .WCLKE(WCLKE),
+ .WCLK(WCLK),
+ .RE(RE),
+ .RCLKE(RCLKE),
+ .RCLK(RCLK)
+ );
+
+ SB_RAM40_4K #(
+ .READ_MODE(1),
+ .WRITE_MODE(2)
+ ) ram40_12 (
+ .WADDR(WADDR[9:0]),
+ .RADDR(RADDR[8:0]),
+ .WDATA(WDATA[3:0]),
+ .RDATA(RDATA_1),
+ .WE(WE),
+ .WCLKE(WCLKE),
+ .WCLK(WCLK),
+ .RE(RE),
+ .RCLKE(RCLKE),
+ .RCLK(RCLK)
+ );
+
+ SB_RAM40_4K #(
+ .READ_MODE(3),
+ .WRITE_MODE(3)
+ ) ram40_33 (
+ .WADDR(WADDR),
+ .RADDR(RADDR),
+ .WDATA(WDATA[1:0]),
+ .RDATA(RDATA_3),
+ .WE(WE),
+ .WCLKE(WCLKE),
+ .WCLK(WCLK),
+ .RE(RE),
+ .RCLKE(RCLKE),
+ .RCLK(RCLK)
+ );
+
+ SB_LUT4 #(
+ .LUT_INIT(16'b 1000_0000_0000_0000)
+ ) lut (
+ .O(X),
+ .I0(RDATA_0[0]),
+ .I1(RDATA_0[6]),
+ .I2(RDATA_0[8]),
+ .I3(RDATA_0[14])
+ );
+endmodule
diff --git a/icefuzz/tests/sb_warmboot.v b/icefuzz/tests/sb_warmboot.v
new file mode 100644
index 0000000..9b632ba
--- /dev/null
+++ b/icefuzz/tests/sb_warmboot.v
@@ -0,0 +1,7 @@
+module top(input boot, s0, s1);
+ SB_WARMBOOT warmboot (
+ .BOOT(boot),
+ .S0(s0),
+ .S1(s1)
+ );
+endmodule
diff --git a/icefuzz/tests/test_pio.sh b/icefuzz/tests/test_pio.sh
new file mode 100644
index 0000000..4987259
--- /dev/null
+++ b/icefuzz/tests/test_pio.sh
@@ -0,0 +1,60 @@
+#!/bin/bash
+
+set -e
+lattice_simlib="/opt/lscc/iCEcube2.2014.12/verilog/sb_ice_syn.v"
+
+mkdir -p test_pio.work
+cd test_pio.work
+
+for NEGTRIG in 0 1; do
+for INTYPE in 00 01 10 11; do
+for OUTTYPE in 0000 0110 1010 1110 0101 1001 1101 \
+ 0100 1000 1100 0111 1011 1111; do
+ pf="test_pio_${OUTTYPE}${INTYPE}${NEGTRIG}"
+ echo "Testing ${pf}..."
+ if ! test -f ${pf}.bin; then
+ cat > ${pf}.v <<- EOT
+ module top (
+ inout pin,
+ input latch_in,
+ input clk_en,
+ input clk_in,
+ input clk_out,
+ input oen,
+ input dout_0,
+ input dout_1,
+ output din_0,
+ output din_1,
+ output global
+ );
+ SB_GB_IO #(
+ .PIN_TYPE(6'b${OUTTYPE}${INTYPE}),
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b${NEGTRIG}),
+ .IO_STANDARD("SB_LVCMOS")
+ ) pin_gb_io (
+ .PACKAGE_PIN(pin),
+ .GLOBAL_BUFFER_OUTPUT(global),
+ .LATCH_INPUT_VALUE(latch_in),
+ .CLOCK_ENABLE(clk_en),
+ .INPUT_CLK(clk_in),
+ .OUTPUT_CLK(clk_out),
+ .OUTPUT_ENABLE(oen),
+ .D_OUT_0(dout_0),
+ .D_OUT_1(dout_1),
+ .D_IN_0(din_0),
+ .D_IN_1(din_1)
+ );
+ endmodule
+ EOT
+ bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1
+ fi
+ python ../../../icebox/icebox_vlog.py -P ${pf}.psb ${pf}.txt > ${pf}_out.v
+ iverilog -D"VCDFILE=\"${pf}_tb.vcd\"" -DINTYPE=${INTYPE} -o ${pf}_tb \
+ -s testbench ../test_pio_tb.v ${pf}.v ${pf}_out.v $lattice_simlib 2> /dev/null
+ ./${pf}_tb > ${pf}_tb.txt
+ if grep ERROR ${pf}_tb.txt; then exit 1; fi
+done; done; done
+
+echo "All tests passed."
+
diff --git a/icefuzz/tests/test_pio_tb.v b/icefuzz/tests/test_pio_tb.v
new file mode 100644
index 0000000..14c15a5
--- /dev/null
+++ b/icefuzz/tests/test_pio_tb.v
@@ -0,0 +1,126 @@
+module testbench;
+ reg pin_reg;
+ reg latch_in;
+ reg clk_en;
+ reg clk_in;
+ reg clk_out;
+ reg oen;
+ reg dout_0;
+ reg dout_1;
+
+ wire gold_pin;
+ wire gold_global;
+ wire gold_din_0;
+ wire gold_din_1;
+
+ wire gate_pin;
+ wire gate_global;
+ wire gate_din_0;
+ wire gate_din_1;
+
+ top gold (
+ .pin (gold_pin ),
+ .global (gold_global),
+ .latch_in(latch_in ),
+ .clk_en (clk_en ),
+ .clk_in (clk_in ),
+ .clk_out (clk_out ),
+ .oen (oen ),
+ .dout_0 (dout_0 ),
+ .dout_1 (dout_1 ),
+ .din_0 (gold_din_0 ),
+ .din_1 (gold_din_1 )
+ );
+
+ chip gate (
+ .pin (gate_pin ),
+ .global (gate_global),
+ .latch_in(latch_in ),
+ .clk_en (clk_en ),
+ .clk_in (clk_in ),
+ .clk_out (clk_out ),
+ .oen (oen ),
+ .dout_0 (dout_0 ),
+ .dout_1 (dout_1 ),
+ .din_0 (gate_din_0 ),
+ .din_1 (gate_din_1 )
+ );
+
+ assign gold_pin = pin_reg;
+ assign gate_pin = pin_reg;
+
+ reg [63:0] xorshift64_state = 64'd88172645463325252;
+
+ task xorshift64_next;
+ begin
+ // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
+ xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
+ xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
+ xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
+ end
+ endtask
+
+ reg error = 0;
+ integer rndval;
+
+ initial begin
+ `ifdef VCDFILE
+ $dumpfile(`VCDFILE);
+ $dumpvars(0, testbench);
+ `endif
+
+ pin_reg <= 0;
+ latch_in <= 0;
+ clk_en <= 1;
+ clk_in <= 0;
+ clk_out <= 0;
+ oen <= 0;
+ dout_0 <= 0;
+ dout_1 <= 0;
+
+ pin_reg <= 0;
+ repeat (5) #10 clk_in <= ~clk_in;
+ repeat (5) #10 clk_out <= ~clk_out;
+
+ pin_reg <= 1;
+ repeat (5) #10 clk_in <= ~clk_in;
+ repeat (5) #10 clk_out <= ~clk_out;
+
+ pin_reg <= 'bz;
+ repeat (5) #10 clk_in <= ~clk_in;
+ repeat (5) #10 clk_out <= ~clk_out;
+
+ repeat (1000) begin
+ if ('b `INTYPE == 0) begin
+ error = {gold_pin, gold_global, gold_din_0, gate_din_1} !== {gate_pin, gate_global, gate_din_0, gate_din_1};
+ $display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ",
+ "oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b, din_1=%b%b %s"},
+ gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out,
+ oen, dout_0, dout_1, gold_din_0, gate_din_0, gold_din_1, gate_din_1, error ? "ERROR" : "OK");
+ end else begin
+ error = {gold_pin, gold_global, gold_din_0} !== {gate_pin, gate_global, gate_din_0};
+ $display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ",
+ "oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b %s"},
+ gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out,
+ oen, dout_0, dout_1, gold_din_0, gate_din_0, error ? "ERROR" : "OK");
+ end
+ xorshift64_next;
+ rndval = (xorshift64_state >> 16) & 'hffff;
+ case (xorshift64_state % 5)
+ 0: pin_reg <= 1'bz;
+ 1: pin_reg <= 1'b0;
+ 2: pin_reg <= 1'b1;
+ `ifdef DISABLED
+ // Lattice SB_IO clk_en model is b0rken
+ // IceBox latch_in routing is non-existing
+ default: {latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} <=
+ {latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 7));
+ `else
+ default: {latch_in, clk_in, clk_out, oen, dout_0, dout_1} <=
+ {latch_in, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 6));
+ `endif
+ endcase
+ #10;
+ end
+ end
+endmodule
diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index 85531b1..3e0f109 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -379,12 +379,10 @@ void FpgaConfig::read_bits(std::istream &ifs)
}
}
- if (this->cram_width == 182 && this->cram_height == 80)
- this->device = "384";
- else if (this->cram_width == 332 && this->cram_height == 144)
+ if (this->cram_width == 332 && this->cram_height == 144)
this->device = "1k";
else if (this->cram_width == 872 && this->cram_height == 272)
- this->device = "4k8k";
+ this->device = "8k";
else
error("Failed to detect chip type.\n");
@@ -595,6 +593,12 @@ void FpgaConfig::read_ascii(std::istream &ifs)
this->bram_width = 64;
this->bram_height = 2 * 128;
} else
+ if (this->device == "8k") {
+ this->cram_width = 872;
+ this->cram_height = 272;
+ this->bram_width = 128;
+ this->bram_height = 2 * 128;
+ } else
error("Unsupported chip type '%s'.\n", this->device.c_str());
this->cram.resize(4);
@@ -842,36 +846,40 @@ void FpgaConfig::write_bram_pbm(std::ostream &ofs, int bank_num) const
int FpgaConfig::chip_width() const
{
- if (this->device == "384") return 6;
- if (this->device == "1k") return 12;
- if (this->device == "4k8k") return 32;
+ if (this->device == "1k") return 12;
+ if (this->device == "8k") return 32;
panic("Unkown chip type '%s'.\n", this->device.c_str());
}
int FpgaConfig::chip_height() const
{
- if (this->device == "384") return 8;
- if (this->device == "1k") return 16;
- if (this->device == "4k8k") return 32;
+ if (this->device == "1k") return 16;
+ if (this->device == "8k") return 32;
panic("Unkown chip type '%s'.\n", this->device.c_str());
}
vector<int> FpgaConfig::chip_cols() const
{
- if (this->device == "384") return vector<int>({18, 54, 54, 54});
- if (this->device == "1k") return vector<int>({18, 54, 54, 42, 54, 54, 54});
- if (this->device == "4k8k") return vector<int>({18, 2, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54});
+ if (this->device == "1k") return vector<int>({18, 54, 54, 42, 54, 54, 54});
+ if (this->device == "8k") return vector<int>({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54});
panic("Unkown chip type '%s'.\n", this->device.c_str());
}
string FpgaConfig::tile_type(int x, int y) const
{
+ if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
+ if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io";
+
if (this->device == "1k") {
- if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
- if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io";
if (x == 3 || x == 10) return y % 2 == 1 ? "ramb" : "ramt";
return "logic";
}
+
+ if (this->device == "8k") {
+ if (x == 8 || x == 25) return y % 2 == 1 ? "ramb" : "ramt";
+ return "logic";
+ }
+
panic("Unkown chip type '%s'.\n", this->device.c_str());
}
diff --git a/iceprog/iceprog.c b/iceprog/iceprog.c
index 5d03dc9..1288fe3 100644
--- a/iceprog/iceprog.c
+++ b/iceprog/iceprog.c
@@ -31,6 +31,8 @@
#include <unistd.h>
#include <string.h>
#include <errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
struct ftdi_context ftdic;
bool ftdic_open = false;
@@ -148,7 +150,7 @@ void flash_read_id()
{
// printf("read flash ID..\n");
- uint8_t data[21] = { 0x9E };
+ uint8_t data[21] = { 0x9F };
set_gpio(0, 0);
xfer_spi(data, 21);
set_gpio(1, 0);
@@ -159,6 +161,22 @@ void flash_read_id()
printf("\n");
}
+void flash_power_up()
+{
+ uint8_t data[1] = { 0xAB };
+ set_gpio(0, 0);
+ xfer_spi(data, 1);
+ set_gpio(1, 0);
+}
+
+void flash_power_down()
+{
+ uint8_t data[1] = { 0xB9 };
+ set_gpio(0, 0);
+ xfer_spi(data, 1);
+ set_gpio(1, 0);
+}
+
void flash_write_enable()
{
if (verbose)
@@ -180,9 +198,9 @@ void flash_bulk_erase()
set_gpio(1, 0);
}
-void flash_sector_erase(int addr)
+void flash_64kB_sector_erase(int addr)
{
- printf("sector erase 0x%06X..\n", addr);
+ printf("erase 64kB sector at 0x%06X..\n", addr);
uint8_t command[4] = { 0xd8, addr >> 16, addr >> 8, addr };
set_gpio(0, 0);
@@ -279,6 +297,9 @@ void help(const char *progname)
fprintf(stderr, " i:<vendor>:<product>:<index> (e.g. i:0x0403:0x6010:0)\n");
fprintf(stderr, " s:<vendor>:<product>:<serial-string>\n");
fprintf(stderr, "\n");
+ fprintf(stderr, " -I [ABCD]\n");
+ fprintf(stderr, " connect to the specified interface on the FTDI chip\n");
+ fprintf(stderr, "\n");
fprintf(stderr, " -r\n");
fprintf(stderr, " read entire flash (32Mb / 4MB) and write to file\n");
fprintf(stderr, "\n");
@@ -297,6 +318,9 @@ void help(const char *progname)
fprintf(stderr, " -S\n");
fprintf(stderr, " perform SRAM programming\n");
fprintf(stderr, "\n");
+ fprintf(stderr, " -t\n");
+ fprintf(stderr, " just read the flash ID sequence\n");
+ fprintf(stderr, "\n");
fprintf(stderr, " -v\n");
fprintf(stderr, " verbose output\n");
fprintf(stderr, "\n");
@@ -311,17 +335,26 @@ int main(int argc, char **argv)
bool bulk_erase = false;
bool dont_erase = false;
bool prog_sram = false;
+ bool test_mode = false;
const char *filename = NULL;
const char *devstr = NULL;
+ int ifnum = INTERFACE_A;
int opt;
- while ((opt = getopt(argc, argv, "d:rRcbnSv")) != -1)
+ while ((opt = getopt(argc, argv, "d:I:rRcbnStv")) != -1)
{
switch (opt)
{
case 'd':
devstr = optarg;
break;
+ case 'I':
+ if (!strcmp(optarg, "A")) ifnum = INTERFACE_A;
+ else if (!strcmp(optarg, "B")) ifnum = INTERFACE_B;
+ else if (!strcmp(optarg, "C")) ifnum = INTERFACE_C;
+ else if (!strcmp(optarg, "D")) ifnum = INTERFACE_D;
+ else help(argv[0]);
+ break;
case 'r':
read_mode = true;
break;
@@ -341,6 +374,9 @@ int main(int argc, char **argv)
case 'S':
prog_sram = true;
break;
+ case 't':
+ test_mode = true;
+ break;
case 'v':
verbose = true;
break;
@@ -349,13 +385,13 @@ int main(int argc, char **argv)
}
}
- if (read_mode && check_mode)
+ if (read_mode + check_mode + prog_sram + test_mode > 1)
help(argv[0]);
if (bulk_erase && dont_erase)
help(argv[0]);
- if (optind+1 != argc)
+ if (optind+1 != argc && !test_mode)
help(argv[0]);
filename = argv[optind];
@@ -367,7 +403,7 @@ int main(int argc, char **argv)
printf("init..\n");
ftdi_init(&ftdic);
- ftdi_set_interface(&ftdic, INTERFACE_A);
+ ftdi_set_interface(&ftdic, ifnum);
if (devstr != NULL) {
if (ftdi_usb_open_string(&ftdic, devstr)) {
@@ -412,7 +448,27 @@ int main(int argc, char **argv)
usleep(100000);
- if (prog_sram)
+ if (test_mode)
+ {
+ printf("reset..\n");
+
+ set_gpio(1, 0);
+ usleep(250000);
+
+ printf("cdone: %s\n", get_cdone() ? "high" : "low");
+
+ flash_power_up();
+
+ flash_read_id();
+
+ flash_power_down();
+
+ set_gpio(1, 1);
+ usleep(250000);
+
+ printf("cdone: %s\n", get_cdone() ? "high" : "low");
+ }
+ else if (prog_sram)
{
// ---------------------------------------------------------
// Reset
@@ -476,6 +532,8 @@ int main(int argc, char **argv)
printf("cdone: %s\n", get_cdone() ? "high" : "low");
+ flash_power_up();
+
flash_read_id();
@@ -501,13 +559,16 @@ int main(int argc, char **argv)
}
else
{
- fseek(f, SEEK_END, 0);
- int file_size = ftell(f);
- rewind(f);
+ struct stat st_buf;
+ if (stat(filename, &st_buf)) {
+ fprintf(stderr, "Error: Can't stat '%s': %s\n", filename, strerror(errno));
+ error();
+ }
- for (int addr = 0; addr < file_size; addr += 0x1000) {
+ printf("file size: %d\n", (int)st_buf.st_size);
+ for (int addr = 0; addr < st_buf.st_size; addr += 0x10000) {
flash_write_enable();
- flash_sector_erase(addr);
+ flash_64kB_sector_erase(addr);
flash_wait();
}
}
@@ -578,6 +639,8 @@ int main(int argc, char **argv)
// Reset
// ---------------------------------------------------------
+ flash_power_down();
+
set_gpio(1, 1);
usleep(250000);
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/debian-science/packages/icestorm.git
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