[icestorm] 09/75: Updated documentation

[Ruben Undheim]

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rubund-guest pushed a commit to branch master
in repository icestorm.

commit f696bb7a92aff4ddd6a1f07cbd73f9ebd2032a3d
Author: Clifford Wolf <clifford at clifford.at>
Date:   Sun Jul 19 09:50:39 2015 +0200

    Updated documentation
---
 README          |  9 +++------
 docs/index.html | 56 ++++++++++++++++++++++++++++++++++++--------------------
 2 files changed, 39 insertions(+), 26 deletions(-)

diff --git a/README b/README
index 7f433f5..1446e00 100644
--- a/README
+++ b/README
@@ -1,7 +1,4 @@
-See http://www.clifford.at/icestorm/ for more information.
-
-Note: This is a development snapshot. This version of
-icestorm will not work with any release of arachne-pnr.
+Project IceStorm aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
 
-Download "icestorm-snapshot-150526.zip" from the website
-for the last "stable" version of project icestorm.
+See http://www.clifford.at/icestorm/ for more information.
diff --git a/docs/index.html b/docs/index.html
index dbd8ba6..4b96aa3 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -34,13 +34,7 @@ for all kinds of projects.
 
 <p>
 We have enough bits mapped that we can create a functional verilog model for almost all 
-bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144, as long as no
-block memories or PLLs are used. (Both are fully documented, but the
-<tt>icebox_vlog.py</tt> script does not create verilog models for them yet.)
-</p>
-
-<p>
-Next on the TODO list: PLLs, Timing Analysis, support for HX8K chips.
+bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256.
 </p>
 
 <h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
@@ -58,23 +52,36 @@ arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.txt
 icepack rot.txt rot.bin
 iceprog rot.bin</pre>
 
-<h2>Where are the Tools?</h2>
+<h2>Where are the Tools? How to install?</h2>
 
 <p>
-Here is the current snapshot of our toolchain: <a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a><br/>
-<i>This is work under construction and highly experimental! Use at your own risk!</i>
+Installing the <a hreaf="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a> (icepack, icebox, iceprog):
 </p>
 
-<p style="margin-bottom: 0.5em;">
-All snapshots in reverse chronological order:
+<pre style="padding-left: 3em">git clone https://github.com/cliffordwolf/icestorm.git icestorm
+cd icestorm
+make -j$(nproc)
+sudo make install</pre>
+
+<p>
+Installing <a href="https://github.com/cseed/arachne-pnr">Arachne-PNR</a> (the place&route tool):
 </p>
 
-<ul style="margin-top: 0.5em;">
-<li><a href="icestorm-snapshot-150526.zip">icestorm-snapshot-150526.zip</a></li>
-<li><a href="icestorm-snapshot-150413.zip">icestorm-snapshot-150413.zip</a></li>
-<li><a href="icestorm-snapshot-150401.zip">icestorm-snapshot-150401.zip</a></li>
-<li><a href="icestorm-snapshot-150322.zip">icestorm-snapshot-150322.zip</a></li>
-</ul>
+<pre style="padding-left: 3em">git clone https://github.com/cseed/arachne-pnr.git arachne-pnr
+cd arachne-pnr
+make -j$(nproc)
+sudo make install</pre>
+
+<p>
+Installing <a href="http://www.clifford.at/yosys/">Yosys</a> (Verilog synthesis):
+</p>
+
+<pre style="padding-left: 3em">git clone https://github.com/cliffordwolf/yosys.git yosys
+cd yosys
+make -j$(nproc)
+sudo make install</pre>
+
+<h2>What are the IceStorm Tools?</h2>
 
 <h3>IcePack/IceUnpack</h3>
 
@@ -98,8 +105,16 @@ dump of a bitstream into a verilog file that implements an equivalent circuit.
 A small driver programm for the FTDI-based programmer used on the iCEstick and HX8K development boards.
 </p>
 
+<h3>ChipDB</h3>
+
+<p>
+The IceStorm Makefile builds and installs two files: <tt>chipdb-1k.txt</tt> and <tt>chipdb-8k.txt</tt>.
+This files contain all the relevant information for arachne-pnr to place&route a design and
+create an IceBox ASCII file for the placed and routed design.
+</p>
+
 <p>
-<i>The tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser.</i>
+<i>The IceStorm tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser.</i>
 </p>
 
 <h2>Where is the Documentation?</h2>
@@ -121,7 +136,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
 <li><a href="io_tile.html">IO Tile Documentation</a></li>
 <li><a href="ram_tile.html">RAM Tile Documentation</a></li>
 <li><a href="format.html">The Bitstream File Format</a></li>
-<li><a href="bitdocs/">Tile Bits Reference Docs</a></li>
+<li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li>
+<li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li>
 </ul>
 
 <p>

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