[icestorm] 40/75: Fixed SBTICETechnologyLibrary links
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 15:52:07 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository icestorm.
commit 235ff955e3f857a8b4353a64d5b18dd3da91f1f5
Author: Clifford Wolf <clifford at clifford.at>
Date: Sat Aug 15 10:07:30 2015 +0200
Fixed SBTICETechnologyLibrary links
---
docs/index.html | 2 +-
docs/io_tile.html | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/index.html b/docs/index.html
index 7fcec8d..17b99a7 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -144,7 +144,7 @@ create an IceBox ASCII file for the placed and routed design.
<p>
Recommended reading:
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf">Lattice iCE40 LP/HX Family Datasheet</a>,
-<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201412.pdf">Lattice iCE Technology Library</a>
+<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201504.pdf">Lattice iCE Technology Library</a>
(Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in
the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)
</p>
diff --git a/docs/io_tile.html b/docs/io_tile.html
index e92ce21..3cbc045 100644
--- a/docs/io_tile.html
+++ b/docs/io_tile.html
@@ -46,7 +46,7 @@ connecting IO tiles to each other are not pairwise crossed out.
<p>
Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt>
-primitive from the <a href="http://www.latticesemi.com/~/media/Documents/TechnicalBriefs/iCETechnologyLibrary.PDF">Lattice iCE Technology Library</a>.
+primitive from the Lattice iCE Technology Library.
Some inputs are shared between the two IO blocks. The following table lists how the
wires in the logic tile map to the <tt>SB_IO</tt> primitive ports:
</p>
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