[icestorm] 58/75: Added test-cases for all sb_pll40 primitives
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 15:52:09 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository icestorm.
commit 4af8569777fe3aea19ce4e03543441734d6c4272
Author: Clifford Wolf <clifford at clifford.at>
Date: Sun Aug 30 21:45:11 2015 +0200
Added test-cases for all sb_pll40 primitives
---
.../tests/{sb_pll40_core.v => sb_pll40_2_pad.v} | 19 +++++----------
.../tests/{sb_pll40_core.v => sb_pll40_2f_core.v} | 16 ++++++-------
.../tests/{sb_pll40_core.v => sb_pll40_2f_pad.v} | 22 ++++++++---------
icefuzz/tests/sb_pll40_core.v | 24 ++++++-------------
icefuzz/tests/{sb_pll40_core.v => sb_pll40_pad.v} | 28 +++++++---------------
5 files changed, 39 insertions(+), 70 deletions(-)
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_2_pad.v
similarity index 76%
copy from icefuzz/tests/sb_pll40_core.v
copy to icefuzz/tests/sb_pll40_2_pad.v
index 298fb73..4137a22 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_2_pad.v
@@ -1,5 +1,5 @@
module top(
- input REFERENCECLK,
+ input PACKAGEPIN,
output [1:0] PLLOUTCORE,
output [1:0] PLLOUTGLOBAL,
input EXTFEEDBACK,
@@ -14,7 +14,7 @@ module top(
input SDI,
input SCLK
);
- SB_PLL40_2F_CORE #(
+ SB_PLL40_2_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
@@ -26,13 +26,10 @@ module top(
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
- .PLLOUT_SELECT_PORTA("GENCLK"),
.PLLOUT_SELECT_PORTB("GENCLK"),
-
- // .PLLOUT_SELECT("GENCLK"),
- // .PLLOUT_SELECT("GENCLK_HALF"),
- // .PLLOUT_SELECT("SHIFTREG_90deg"),
- // .PLLOUT_SELECT("SHIFTREG_0deg"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
@@ -41,15 +38,11 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
- .REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
+ .PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_2f_core.v
similarity index 83%
copy from icefuzz/tests/sb_pll40_core.v
copy to icefuzz/tests/sb_pll40_2f_core.v
index 298fb73..8055e12 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_2f_core.v
@@ -27,12 +27,14 @@ module top(
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT_PORTA("GENCLK"),
- .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTA("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
- // .PLLOUT_SELECT("GENCLK"),
- // .PLLOUT_SELECT("GENCLK_HALF"),
- // .PLLOUT_SELECT("SHIFTREG_90deg"),
- // .PLLOUT_SELECT("SHIFTREG_0deg"),
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
@@ -41,15 +43,11 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
.REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_2f_pad.v
similarity index 78%
copy from icefuzz/tests/sb_pll40_core.v
copy to icefuzz/tests/sb_pll40_2f_pad.v
index 298fb73..65bfad4 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_2f_pad.v
@@ -1,5 +1,5 @@
module top(
- input REFERENCECLK,
+ input PACKAGEPIN,
output [1:0] PLLOUTCORE,
output [1:0] PLLOUTGLOBAL,
input EXTFEEDBACK,
@@ -14,7 +14,7 @@ module top(
input SDI,
input SCLK
);
- SB_PLL40_2F_CORE #(
+ SB_PLL40_2F_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
@@ -27,12 +27,14 @@ module top(
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT_PORTA("GENCLK"),
- .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTA("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
- // .PLLOUT_SELECT("GENCLK"),
- // .PLLOUT_SELECT("GENCLK_HALF"),
- // .PLLOUT_SELECT("SHIFTREG_90deg"),
- // .PLLOUT_SELECT("SHIFTREG_0deg"),
+ .PLLOUT_SELECT_PORTB("GENCLK"),
+ // .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
+ // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
@@ -41,15 +43,11 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
- .REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
+ .PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_core.v
index 298fb73..9954eca 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_core.v
@@ -1,7 +1,7 @@
module top(
input REFERENCECLK,
- output [1:0] PLLOUTCORE,
- output [1:0] PLLOUTGLOBAL,
+ output PLLOUTCORE,
+ output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
@@ -14,7 +14,7 @@ module top(
input SDI,
input SCLK
);
- SB_PLL40_2F_CORE #(
+ SB_PLL40_CORE #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
@@ -26,10 +26,7 @@ module top(
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
- .PLLOUT_SELECT_PORTA("GENCLK"),
- .PLLOUT_SELECT_PORTB("GENCLK"),
-
- // .PLLOUT_SELECT("GENCLK"),
+ .PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
@@ -41,19 +38,12 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
- .ENABLE_ICEGATE_PORTA(1'b0),
- .ENABLE_ICEGATE_PORTB(1'b0),
+ .ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
.REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
- .PLLOUTCOREA (PLLOUTCORE [0]),
- .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
- .PLLOUTCOREB (PLLOUTCORE [1]),
- .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .PLLOUTCORE (PLLOUTCORE ),
+ .PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_pad.v
similarity index 66%
copy from icefuzz/tests/sb_pll40_core.v
copy to icefuzz/tests/sb_pll40_pad.v
index 298fb73..180d04b 100644
--- a/icefuzz/tests/sb_pll40_core.v
+++ b/icefuzz/tests/sb_pll40_pad.v
@@ -1,7 +1,7 @@
module top(
- input REFERENCECLK,
- output [1:0] PLLOUTCORE,
- output [1:0] PLLOUTGLOBAL,
+ input PACKAGEPIN,
+ output PLLOUTCORE,
+ output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
@@ -14,7 +14,7 @@ module top(
input SDI,
input SCLK
);
- SB_PLL40_2F_CORE #(
+ SB_PLL40_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
@@ -26,10 +26,7 @@ module top(
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
- .PLLOUT_SELECT_PORTA("GENCLK"),
- .PLLOUT_SELECT_PORTB("GENCLK"),
-
- // .PLLOUT_SELECT("GENCLK"),
+ .PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
@@ -41,19 +38,12 @@ module top(
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
- // .ENABLE_ICEGATE(1'b0),
- .ENABLE_ICEGATE_PORTA(1'b0),
- .ENABLE_ICEGATE_PORTB(1'b0),
+ .ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
- .REFERENCECLK (REFERENCECLK ),
- // .PACKAGEPIN (REFERENCECLK ),
- // .PLLOUTCORE (PLLOUTCORE ),
- // .PLLOUTGLOBAL (PLLOUTGLOBAL ),
- .PLLOUTCOREA (PLLOUTCORE [0]),
- .PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
- .PLLOUTCOREB (PLLOUTCORE [1]),
- .PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
+ .PACKAGEPIN (PACKAGEPIN ),
+ .PLLOUTCORE (PLLOUTCORE ),
+ .PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
--
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