[icestorm] 70/75: Converted docs to proper HTML5
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 15:52:11 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository icestorm.
commit d1e16d54ad7dd6bb7334494450917107615d0ef2
Author: Clifford Wolf <clifford at clifford.at>
Date: Fri Oct 2 14:06:54 2015 +0200
Converted docs to proper HTML5
---
docs/format.html | 34 +++-
docs/index.html | 39 ++--
docs/io_tile.html | 561 ++++++++++++++++++++++++++-------------------------
docs/logic_tile.html | 315 ++++++++++++++---------------
docs/ram_tile.html | 79 ++++----
5 files changed, 528 insertions(+), 500 deletions(-)
diff --git a/docs/format.html b/docs/format.html
index 75397e0..8c21c00 100644
--- a/docs/format.html
+++ b/docs/format.html
@@ -1,4 +1,18 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
+<style>
+.ctab {
+ margin-left: auto;
+ margin-right: auto;
+ border: 1px solid gray;
+}
+.ctab td, .ctab th {
+ padding: 3px;
+ border: 1px solid gray;
+}
+</style>
<title>Project IceStorm – Bitstream File Format Documentation</title>
+</head><body>
<h1>Project IceStorm – Bitstream File Format Documentation</h1>
<p>
@@ -31,8 +45,7 @@ follows the command in case of the CRAM and BRAM commands.
The following commands are known:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Opcode</th><th>Description</th></tr>
<tr><td>0</td><td>payload=0: CRAM Data<br/>
payload=3: BRAM Data<br/>
@@ -53,10 +66,9 @@ The following commands are known:
payload=16: Enable cold boot<br/>
payload=32: Enable warm boot</td></tr>
</table>
-</p>
<p>
-Use <tt>iceunpack -vv</tt> to display the commands as they are interpreted by the tool.
+Use <span style="font-family:monospace">iceunpack -vv</span> to display the commands as they are interpreted by the tool.
</p>
<p>
@@ -72,7 +84,7 @@ Most bytes in the bitstream are SRAM data bytes that should be written to the va
in the FPGA. The following sequence is used to program an SRAM cell:
</p>
-<p><ul>
+<ul>
<li>Set bank width (opcode 6)</li>
<li>Set bank height (opcode 7)</li>
<li>Set bank offset (opcode 8)</li>
@@ -80,7 +92,7 @@ in the FPGA. The following sequence is used to program an SRAM cell:
<li>CRAM or BRAM Data Command</li>
<li>(width * height / 8) data bytes</li>
<li>two zero bytes</li>
-</ul></p>
+</ul>
<p>
The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can
@@ -104,7 +116,8 @@ The ordering of the data bits is in MSB first row-major order.
<h2>Organization of the CRAM</h2>
-<p><a href="checkerboard.png"><img style="float:right; padding:1em; padding-top:0" height="200" src="checkerboard.png" border="0"></a></p>
+<p><a href="checkerboard.png"><img alt="Mapping of tile config bits to 2D CRAM"
+style="float:right; padding:1em; padding-top:0; border:0" height="200" src="checkerboard.png"></a></p>
<p>
The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant.
@@ -129,14 +142,14 @@ RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM
<p>
The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that
their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit
-positions are vertically permuted as well. The <tt>CramIndexConverter</tt> class in <tt>icepack.cc</tt> encapsulates the calculations
+positions are vertically permuted as well. The <span style="font-family:monospace">CramIndexConverter</span> class in <span style="font-family:monospace">icepack.cc</span> encapsulates the calculations
that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.
</p>
<p>
The black pixels in the image correspond to CRAM bits that are not associated with any IO, LOGIC or RAM tile.
-Some of them are unused, others are used by hard IPs or other global resources. The <tt>iceunpack</tt> tool reports
-such bits, when set, with the "<tt>.extra_bit <i>bank x y</i></tt>" statement in the ASCII output format.
+Some of them are unused, others are used by hard IPs or other global resources. The <span style="font-family:monospace">iceunpack</span> tool reports
+such bits, when set, with the "<span style="font-family:monospace">.extra_bit <i>bank x y</i></span>" statement in the ASCII output format.
</p>
<h2>Organization of the BRAM</h2>
@@ -152,3 +165,4 @@ The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). Th
the CRC to 0xFFFF. No zero padding is performed.
</p>
+</body></html>
diff --git a/docs/index.html b/docs/index.html
index 17b99a7..a400fef 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -1,4 +1,7 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
<title>Project IceStorm</title>
+</head><body>
<h1>Project IceStorm</h1>
<p>
@@ -102,16 +105,16 @@ after updating your IceStorm installation.
<h3>IcePack/IceUnpack</h3>
<p>
-The <tt>iceunpack</tt> program converts an iCE40 <tt>.bin</tt> file into the IceBox ASCII format
-that has blocks of <tt>0</tt> and <tt>1</tt> for the config bits for each tile in the chip. The
-<tt>icepack</tt> program converts such an ASCII file back to an iCE40 <tt>.bin</tt> file.
+The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceBox ASCII format
+that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The
+<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file.
</p>
<h3>IceBox</h3>
<p>
A python library and various tools for working with IceBox ASCII files and accessing
-the device database. For example <tt>icebox_vlog</tt> converts our ASCII file
+the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file
dump of a bitstream into a Verilog file that implements an equivalent circuit.
</p>
@@ -130,7 +133,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.
<h3>ChipDB</h3>
<p>
-The IceStorm Makefile builds and installs two files: <tt>chipdb-1k.txt</tt> and <tt>chipdb-8k.txt</tt>.
+The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>.
This files contain all the relevant information for arachne-pnr to place&route a design and
create an IceBox ASCII file for the placed and routed design.
</p>
@@ -163,8 +166,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
</ul>
<p>
-The <tt>iceunpack</tt> program can be used to convert the bitstream into an ASCII file
-that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For example:
+The <span style="font-family:monospace">iceunpack</span> program can be used to convert the bitstream into an ASCII file
+that has a block of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> characters for each tile. For example:
</p>
<pre style="padding-left: 3em">.logic_tile 12 12
@@ -186,12 +189,12 @@ that has a block of <tt>0</tt> and <tt>1</tt> characters for each tile. For exam
000000000000000000000000000101010000101010100000000000</pre>
<p>
-This bits are referred to as <tt>B<i>y</i>[<i>x</i>]</tt> in the documentation. For example, <tt>B0</tt> is the first
-line, <tt>B0[0]</tt> the first bit in the first line, and <tt>B15[53]</tt> the last bit in the last line.
+This bits are referred to as <span style="font-family:monospace">B<i>y</i>[<i>x</i>]</span> in the documentation. For example, <span style="font-family:monospace">B0</span> is the first
+line, <span style="font-family:monospace">B0[0]</span> the first bit in the first line, and <span style="font-family:monospace">B15[53]</span> the last bit in the last line.
</p>
<p>
-The <tt>icebox_explain</tt> program can be used to turn this block of config bits into a description of the cell
+The <span style="font-family:monospace">icebox_explain</span> program can be used to turn this block of config bits into a description of the cell
configuration:
</p>
@@ -205,16 +208,16 @@ buffer sp12_h_r_20 local_g1_4</pre>
<p>
IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed
via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API
-to export this database into a format that fits the target application. See <tt>icebox_chipdb</tt> for
+to export this database into a format that fits the target application. See <span style="font-family:monospace">icebox_chipdb</span> for
an example program that does that.
</p>
<p>
The recommended approach for learning how to use this documentation is to
synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm
-tool <tt>icebox_explain</tt> on the resulting bitstream files, and analyze the
+tool <span style="font-family:monospace">icebox_explain</span> on the resulting bitstream files, and analyze the
results using the HTML export of the database mentioned above.
-<tt>icebox_vlog</tt> can be used to convert the bitstream to Verilog. The
+<span style="font-family:monospace">icebox_vlog</span> can be used to convert the bitstream to Verilog. The
output file of this tool will also outline the signal paths in comments added
to the generated Verilog code.
</p>
@@ -243,7 +246,7 @@ $ icepack example.txt example.bin
</pre>
<p>
-We would get something like the following <tt>icebox_explain</tt> output:
+We would get something like the following <span style="font-family:monospace">icebox_explain</span> output:
</p>
<pre style="padding-left: 3em">$ icebox_explain example.txt
@@ -280,7 +283,7 @@ buffer neigh_op_lft_0 local_g0_0
buffer sp4_h_r_24 local_g3_0</pre>
<p>
-And something like the following <tt>icebox_vlog</tt> output:
+And something like the following <span style="font-family:monospace">icebox_vlog</span> output:
</p>
<pre style="padding-left: 3em">$ icebox_vlog -p example.pcf example.txt
@@ -353,9 +356,7 @@ Links to related projects. Contact me at clifford at clifford.at if you have an int
<li><a href="https://hackaday.io/project/6636-iced-an-arduino-style-board-with-ice-fpga">ICEd = an Arduino Style Board, with ICE FPGA</a>
</ul>
-<p>
<hr>
-</p>
<p>
In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
@@ -368,11 +369,11 @@ e.g. using the following BibTeX code:
howpublished = "\url{http://www.clifford.at/icestorm/}"
}</pre>
-<p>
<hr>
-</p>
<p>
<i>Documentation mostly by Clifford Wolf <clifford at clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here. Buy a few because you might break some..</i>
</p>
+
+</body></html>
diff --git a/docs/io_tile.html b/docs/io_tile.html
index 53ee497..8c1555f 100644
--- a/docs/io_tile.html
+++ b/docs/io_tile.html
@@ -1,4 +1,27 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
+<style>
+.xtab {
+ margin-left: auto;
+ margin-right: auto;
+}
+.xtab td, .xtab th {
+ padding: 10px;
+ vertical-align: top;
+}
+.ctab {
+ margin-left: auto;
+ margin-right: auto;
+ border: 1px solid gray;
+}
+.ctab td, .ctab th {
+ padding: 3px;
+ border: 1px solid gray;
+ vertical-align: baseline;
+}
+</style>
<title>Project IceStorm – IO Tile Documentation</title>
+</head><body>
<h1>Project IceStorm – IO Tile Documentation</h1>
<p>
@@ -9,31 +32,31 @@ This is work in progress.</i>
<h2>Span-4 and Span-12 Wires</h2>
-<p><a href="iosp.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="iosp.svg" border="0"></a></p>
+<p><a href="iosp.svg"><img alt="IO Tile Span-Wires" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="iosp.svg"></a></p>
<p>
The image on the right shows the span-wires of a left (or right) io cell (click to enlarge).
</p>
<p>
-A left/right io cell has 16 connections named <tt>span4_vert_t_0</tt> to <tt>span4_vert_t_15</tt> on its top edge and
-16 connections named <tt>span4_vert_b_0</tt> to <tt>span4_vert_b_15</tt> on its bottom edge. The nets <tt>span4_vert_t_0</tt>
-to <tt>span4_vert_t_11</tt> are connected to <tt>span4_vert_b_4</tt> to <tt>span4_vert_b_15</tt>. The span-4 and span-12 wires
-of the adjacent logic cell are connected to the nets <tt>span4_horz_0</tt> to <tt>span4_horz_47</tt> and <tt>span12_horz_0</tt>
-to <tt>span12_horz_23</tt>.
+A left/right io cell has 16 connections named <span style="font-family:monospace">span4_vert_t_0</span> to <span style="font-family:monospace">span4_vert_t_15</span> on its top edge and
+16 connections named <span style="font-family:monospace">span4_vert_b_0</span> to <span style="font-family:monospace">span4_vert_b_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_t_0</span>
+to <span style="font-family:monospace">span4_vert_t_11</span> are connected to <span style="font-family:monospace">span4_vert_b_4</span> to <span style="font-family:monospace">span4_vert_b_15</span>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_horz_0</span> to <span style="font-family:monospace">span4_horz_47</span> and <span style="font-family:monospace">span12_horz_0</span>
+to <span style="font-family:monospace">span12_horz_23</span>.
</p>
<p>
-A top/bottom io cell has 16 connections named <tt>span4_vert_l_0</tt> to <tt>span4_vert_l_15</tt> on its top edge and
-16 connections named <tt>span4_vert_r_0</tt> to <tt>span4_vert_r_15</tt> on its bottom edge. The nets <tt>span4_vert_l_0</tt>
-to <tt>span4_vert_l_11</tt> are connected to <tt>span4_vert_r_4</tt> to <tt>span4_vert_r_15</tt>. The span-4 and span-12 wires
-of the adjacent logic cell are connected to the nets <tt>span4_vert_0</tt> to <tt>span4_vert_47</tt> and <tt>span12_vert_0</tt>
-to <tt>span12_vert_23</tt>.
+A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_vert_l_0</span> to <span style="font-family:monospace">span4_vert_l_15</span> on its top edge and
+16 connections named <span style="font-family:monospace">span4_vert_r_0</span> to <span style="font-family:monospace">span4_vert_r_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_l_0</span>
+to <span style="font-family:monospace">span4_vert_l_11</span> are connected to <span style="font-family:monospace">span4_vert_r_4</span> to <span style="font-family:monospace">span4_vert_r_15</span>. The span-4 and span-12 wires
+of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_vert_0</span> to <span style="font-family:monospace">span4_vert_47</span> and <span style="font-family:monospace">span12_vert_0</span>
+to <span style="font-family:monospace">span12_vert_23</span>.
</p>
<p>
The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom
-io cells. For example <tt>span4_vert_b_0</tt> of IO cell (0 1) is connected to <tt>span4_horz_l_0</tt> (<tt>span4_horz_r_4</tt>)
+io cells. For example <span style="font-family:monospace">span4_vert_b_0</span> of IO cell (0 1) is connected to <span style="font-family:monospace">span4_horz_l_0</span> (<span style="font-family:monospace">span4_horz_r_4</span>)
of IO cell (1 0).
</p>
@@ -45,26 +68,24 @@ connecting IO tiles to each other are not pairwise crossed out.
<h2>IO Blocks</h2>
<p>
-Each IO tile contains two IO blocks. Each IO block essentially implements the <tt>SB_IO</tt>
+Each IO tile contains two IO blocks. Each IO block essentially implements the <span style="font-family:monospace">SB_IO</span>
primitive from the Lattice iCE Technology Library.
Some inputs are shared between the two IO blocks. The following table lists how the
-wires in the logic tile map to the <tt>SB_IO</tt> primitive ports:
+wires in the logic tile map to the <span style="font-family:monospace">SB_IO</span> primitive ports:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>SB_IO Port</th><th>IO Block 0</th><th>IO Block 1</th></tr>
-<tr><td>D_IN_0</td><td><tt>io_0/D_IN_0</tt></td><td><tt>io_1/D_IN_0</tt></td></tr>
-<tr><td>D_IN_1</td><td><tt>io_0/D_IN_1</tt></td><td><tt>io_1/D_IN_1</tt></td></tr>
-<tr><td>D_OUT_0</td><td><tt>io_0/D_OUT_0</tt></td><td><tt>io_1/D_OUT_0</tt></td></tr>
-<tr><td>D_OUT_1</td><td><tt>io_0/D_OUT_1</tt></td><td><tt>io_1/D_OUT_1</tt></td></tr>
-<tr><td>OUTPUT_ENABLE</td><td><tt>io_0/OUT_ENB</tt></td><td><tt>io_1/OUT_ENB</tt></td></tr>
-<tr><td>CLOCK_ENABLE</td><td colspan="2"><tt>io_global/cen</tt></td></tr>
-<tr><td>INPUT_CLK</td><td colspan="2"><tt>io_global/inclk</tt></td></tr>
-<tr><td>OUTPUT_CLK</td><td colspan="2"><tt>io_global/outclk</tt></td></tr>
-<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><tt>io_global/latch</tt></td></tr>
+<tr><td>D_IN_0</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr>
+<tr><td>D_IN_1</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr>
+<tr><td>D_OUT_0</td><td><span style="font-family:monospace">io_0/D_OUT_0</span></td><td><span style="font-family:monospace">io_1/D_OUT_0</span></td></tr>
+<tr><td>D_OUT_1</td><td><span style="font-family:monospace">io_0/D_OUT_1</span></td><td><span style="font-family:monospace">io_1/D_OUT_1</span></td></tr>
+<tr><td>OUTPUT_ENABLE</td><td><span style="font-family:monospace">io_0/OUT_ENB</span></td><td><span style="font-family:monospace">io_1/OUT_ENB</span></td></tr>
+<tr><td>CLOCK_ENABLE</td><td colspan="2"><span style="font-family:monospace">io_global/cen</span></td></tr>
+<tr><td>INPUT_CLK</td><td colspan="2"><span style="font-family:monospace">io_global/inclk</span></td></tr>
+<tr><td>OUTPUT_CLK</td><td colspan="2"><span style="font-family:monospace">io_global/outclk</span></td></tr>
+<tr><td>LATCH_INPUT_VALUE</td><td colspan="2"><span style="font-family:monospace">io_global/latch</span></td></tr>
</table>
-</p>
<p>
Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal
@@ -72,36 +93,34 @@ is first routed to one of 16 local tracks in the IO tile and then from the local
</p>
<p>
-The <tt>io_global/latch</tt> signal is shared among all IO tiles on an edge of the chip and is driven by <tt>fabout</tt>
-from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <tt>io_global/latch</tt> signal are:
+The <span style="font-family:monospace">io_global/latch</span> signal is shared among all IO tiles on an edge of the chip and is driven by <span style="font-family:monospace">fabout</span>
+from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the <span style="font-family:monospace">io_global/latch</span> signal are:
(0, 7), (13, 10), (5, 0), and (8, 17)
</p>
<p>
-A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <tt>D_IN</tt>
-signals created by its two IO blocks. The <tt>D_IN</tt> signals map to logic function indices as follows:
+A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four <span style="font-family:monospace">D_IN</span>
+signals created by its two IO blocks. The <span style="font-family:monospace">D_IN</span> signals map to logic function indices as follows:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Function Index</th><th>D_IN Wire</th></tr>
-<tr><td>0</td><td><tt>io_0/D_IN_0</tt></td></tr>
-<tr><td>1</td><td><tt>io_0/D_IN_1</tt></td></tr>
-<tr><td>2</td><td><tt>io_1/D_IN_0</tt></td></tr>
-<tr><td>3</td><td><tt>io_1/D_IN_1</tt></td></tr>
-<tr><td>4</td><td><tt>io_0/D_IN_0</tt></td></tr>
-<tr><td>5</td><td><tt>io_0/D_IN_1</tt></td></tr>
-<tr><td>6</td><td><tt>io_1/D_IN_0</tt></td></tr>
-<tr><td>7</td><td><tt>io_1/D_IN_1</tt></td></tr>
+<tr><td>0</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td></tr>
+<tr><td>1</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td></tr>
+<tr><td>2</td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr>
+<tr><td>3</td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr>
+<tr><td>4</td><td><span style="font-family:monospace">io_0/D_IN_0</span></td></tr>
+<tr><td>5</td><td><span style="font-family:monospace">io_0/D_IN_1</span></td></tr>
+<tr><td>6</td><td><span style="font-family:monospace">io_1/D_IN_0</span></td></tr>
+<tr><td>7</td><td><span style="font-family:monospace">io_1/D_IN_1</span></td></tr>
</table>
-</p>
<p>
-For example the signal <tt>io_1/D_IN_0</tt> in IO tile (0, 5) can be seen as <tt>neigh_op_lft_2</tt> and <tt>neigh_op_lft_6</tt> in LOGIC tile (1, 5).
+For example the signal <span style="font-family:monospace">io_1/D_IN_0</span> in IO tile (0, 5) can be seen as <span style="font-family:monospace">neigh_op_lft_2</span> and <span style="font-family:monospace">neigh_op_lft_6</span> in LOGIC tile (1, 5).
</p>
<p>
-Each IO Tile has 2 <tt>NegClk</tt> configuration bits, suggesting that the
+Each IO Tile has 2 <span style="font-family:monospace">NegClk</span> configuration bits, suggesting that the
clock signals can be inverted independently for the the two IO blocks in the
tile. However, the Lattice tools refuse to pack to IO blocks with different block
polarity into the same IO tile. In our tests we only managed to either set or clear
@@ -109,159 +128,157 @@ both NegClk bits.
</p>
<p>
-Each IO block has two <tt>IoCtrl IE</tt> bits that enable the input buffers and
-two <tt>IoCtrl REN</tt> bits that enable the pull up resistors. Both bits are active
+Each IO block has two <span style="font-family:monospace">IoCtrl IE</span> bits that enable the input buffers and
+two <span style="font-family:monospace">IoCtrl REN</span> bits that enable the pull up resistors. Both bits are active
low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the
default behavior is to enable pullup resistors on all unused pins). Note that
-<tt>icebox_explain.py</tt> will ignore all IO tiles that only have the two <tt>IoCtrl
-IE</tt> bits set.
+<span style="font-family:monospace">icebox_explain.py</span> will ignore all IO tiles that only have the two <span style="font-family:monospace">IoCtrl
+IE</span> bits set.
</p>
<p>
-However, the <tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> do not
+However, the <span style="font-family:monospace">IoCtrl IE_0/IE_1</span> and <span style="font-family:monospace">IoCtrl REN_0/REN_1</span> do not
necessarily configure the IO PIN that are connected to the IO block in the same tile,
and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins
on the right and bottom side of the chips match up with the IO blocks and for the pins
on the left and top side the numbers must be swapped. But in some cases the IO block
-and the set of <tt>IE/REN</tt> are not even located in the same tile. The following
-table lists the correlation between IO blocks and <tt>IE/REN</tt> bits for the
+and the set of <span style="font-family:monospace">IE/REN</span> are not even located in the same tile. The following
+table lists the correlation between IO blocks and <span style="font-family:monospace">IE/REN</span> bits for the
1K chip:
</p>
-<p align="center">
-<table cellpadding="10">
-<tr><td valign="top">
+<table class="xtab">
+<tr><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Block</th><th>IE/REN Block</th></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 1</td><td align="center">0 14 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 14 0</td><td align="center">0 14 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 1</td><td align="center">0 13 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 13 0</td><td align="center">0 13 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 1</td><td align="center">0 12 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 12 0</td><td align="center">0 12 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 1</td><td align="center">0 11 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 11 0</td><td align="center">0 11 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 1</td><td align="center">0 10 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 10 0</td><td align="center">0 10 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 1</td><td align="center">0 9 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 9 0</td><td align="center">0 9 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 1</td><td align="center">0 8 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 8 0</td><td align="center">0 8 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 1</td><td align="center">0 6 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 6 0</td><td align="center">0 6 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 1</td><td align="center">0 5 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 5 0</td><td align="center">0 5 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 1</td><td align="center">0 4 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 4 0</td><td align="center">0 4 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 1</td><td align="center">0 3 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 3 0</td><td align="center">0 3 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 1</td><td align="center">0 2 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0 2 0</td><td align="center">0 2 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 14 1</td><td style="text-align:center">0 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 14 0</td><td style="text-align:center">0 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 13 1</td><td style="text-align:center">0 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 13 0</td><td style="text-align:center">0 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 12 1</td><td style="text-align:center">0 12 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 12 0</td><td style="text-align:center">0 12 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 11 1</td><td style="text-align:center">0 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 11 0</td><td style="text-align:center">0 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 10 1</td><td style="text-align:center">0 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 10 0</td><td style="text-align:center">0 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 9 1</td><td style="text-align:center">0 9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 9 0</td><td style="text-align:center">0 9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 8 1</td><td style="text-align:center">0 8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 8 0</td><td style="text-align:center">0 8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 6 1</td><td style="text-align:center">0 6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 6 0</td><td style="text-align:center">0 6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 5 1</td><td style="text-align:center">0 5 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 5 0</td><td style="text-align:center">0 5 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 4 1</td><td style="text-align:center">0 4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 4 0</td><td style="text-align:center">0 4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 3 1</td><td style="text-align:center">0 3 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 3 0</td><td style="text-align:center">0 3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 2 1</td><td style="text-align:center">0 2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0 2 0</td><td style="text-align:center">0 2 1</td></tr>
</table>
-</td><td valign="top">
+</td><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Block</th><th>IE/REN Block</th></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 0</td><td align="center"> 1 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 0 1</td><td align="center"> 1 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 0</td><td align="center"> 2 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 0 1</td><td align="center"> 2 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 0</td><td align="center"> 3 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 0 1</td><td align="center"> 3 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 0</td><td align="center"> 4 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 0 1</td><td align="center"> 4 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 0</td><td align="center"> 5 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 0 1</td><td align="center"> 5 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 1</td><td align="center"> 6 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 0</td><td align="center"> 6 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 0 0</td><td align="center"> 7 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 0 1</td><td align="center"> 7 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 0</td><td align="center"> 8 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 0 1</td><td align="center"> 8 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 0</td><td align="center"> 9 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 0 1</td><td align="center"> 9 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 0</td><td align="center">10 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">10 0 1</td><td align="center">10 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 0</td><td align="center">11 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">11 0 1</td><td align="center">11 0 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 0</td><td align="center">12 0 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">12 0 1</td><td align="center">12 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 0 0</td><td style="text-align:center"> 1 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 0 1</td><td style="text-align:center"> 1 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 0 0</td><td style="text-align:center"> 2 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 0 1</td><td style="text-align:center"> 2 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 0 0</td><td style="text-align:center"> 3 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 0 1</td><td style="text-align:center"> 3 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 0 0</td><td style="text-align:center"> 4 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 0 1</td><td style="text-align:center"> 4 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 0 0</td><td style="text-align:center"> 5 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 0 1</td><td style="text-align:center"> 5 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 0 1</td><td style="text-align:center"> 6 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 0 0</td><td style="text-align:center"> 6 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 0 0</td><td style="text-align:center"> 7 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 0 1</td><td style="text-align:center"> 7 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 0 0</td><td style="text-align:center"> 8 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 0 1</td><td style="text-align:center"> 8 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 0 0</td><td style="text-align:center"> 9 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 0 1</td><td style="text-align:center"> 9 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 0 0</td><td style="text-align:center">10 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 0 1</td><td style="text-align:center">10 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 0 0</td><td style="text-align:center">11 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 0 1</td><td style="text-align:center">11 0 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 0 0</td><td style="text-align:center">12 0 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 0 1</td><td style="text-align:center">12 0 1</td></tr>
</table>
-</td><td valign="top">
+</td><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Block</th><th>IE/REN Block</th></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 0</td><td align="center">13 1 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 1 1</td><td align="center">13 1 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 0</td><td align="center">13 2 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 2 1</td><td align="center">13 2 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 3 1</td><td align="center">13 3 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 0</td><td align="center">13 4 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 4 1</td><td align="center">13 4 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 0</td><td align="center">13 6 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 6 1</td><td align="center">13 6 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 0</td><td align="center">13 7 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 7 1</td><td align="center">13 7 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 0</td><td align="center">13 8 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 8 1</td><td align="center">13 8 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 0</td><td align="center">13 9 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 9 1</td><td align="center">13 9 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 0</td><td align="center">13 10 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 11 1</td><td align="center">13 10 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 0</td><td align="center">13 11 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 12 1</td><td align="center">13 11 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 0</td><td align="center">13 13 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 13 1</td><td align="center">13 13 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 0</td><td align="center">13 14 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 14 1</td><td align="center">13 14 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 0</td><td align="center">13 15 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">13 15 1</td><td align="center">13 15 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 1 0</td><td style="text-align:center">13 1 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 1 1</td><td style="text-align:center">13 1 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 2 0</td><td style="text-align:center">13 2 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 2 1</td><td style="text-align:center">13 2 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 3 1</td><td style="text-align:center">13 3 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 4 0</td><td style="text-align:center">13 4 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 4 1</td><td style="text-align:center">13 4 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 6 0</td><td style="text-align:center">13 6 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 6 1</td><td style="text-align:center">13 6 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 7 0</td><td style="text-align:center">13 7 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 7 1</td><td style="text-align:center">13 7 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 8 0</td><td style="text-align:center">13 8 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 8 1</td><td style="text-align:center">13 8 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 9 0</td><td style="text-align:center">13 9 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 9 1</td><td style="text-align:center">13 9 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 11 0</td><td style="text-align:center">13 10 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 11 1</td><td style="text-align:center">13 10 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 12 0</td><td style="text-align:center">13 11 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 12 1</td><td style="text-align:center">13 11 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 13 0</td><td style="text-align:center">13 13 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 13 1</td><td style="text-align:center">13 13 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 14 0</td><td style="text-align:center">13 14 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 14 1</td><td style="text-align:center">13 14 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 15 0</td><td style="text-align:center">13 15 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">13 15 1</td><td style="text-align:center">13 15 1</td></tr>
</table>
-</td><td valign="top">
+</td><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Block</th><th>IE/REN Block</th></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 1</td><td align="center">12 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">12 17 0</td><td align="center">12 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 1</td><td align="center">11 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">11 17 0</td><td align="center">11 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 1</td><td align="center"> 9 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">10 17 0</td><td align="center"> 9 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 1</td><td align="center">10 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 9 17 0</td><td align="center">10 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 1</td><td align="center"> 8 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 8 17 0</td><td align="center"> 8 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 1</td><td align="center"> 7 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 7 17 0</td><td align="center"> 7 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 6 17 1</td><td align="center"> 6 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 1</td><td align="center"> 5 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 5 17 0</td><td align="center"> 5 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 1</td><td align="center"> 4 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 4 17 0</td><td align="center"> 4 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 1</td><td align="center"> 3 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 3 17 0</td><td align="center"> 3 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 1</td><td align="center"> 2 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 2 17 0</td><td align="center"> 2 17 0</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 1</td><td align="center"> 1 17 1</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center"> 1 17 0</td><td align="center"> 1 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 17 1</td><td style="text-align:center">12 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">12 17 0</td><td style="text-align:center">12 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 17 1</td><td style="text-align:center">11 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">11 17 0</td><td style="text-align:center">11 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 17 1</td><td style="text-align:center"> 9 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">10 17 0</td><td style="text-align:center"> 9 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 17 1</td><td style="text-align:center">10 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 9 17 0</td><td style="text-align:center">10 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 17 1</td><td style="text-align:center"> 8 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 8 17 0</td><td style="text-align:center"> 8 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 17 1</td><td style="text-align:center"> 7 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 7 17 0</td><td style="text-align:center"> 7 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 6 17 1</td><td style="text-align:center"> 6 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 17 1</td><td style="text-align:center"> 5 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 5 17 0</td><td style="text-align:center"> 5 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 17 1</td><td style="text-align:center"> 4 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 4 17 0</td><td style="text-align:center"> 4 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 17 1</td><td style="text-align:center"> 3 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 3 17 0</td><td style="text-align:center"> 3 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 17 1</td><td style="text-align:center"> 2 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 2 17 0</td><td style="text-align:center"> 2 17 0</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 17 1</td><td style="text-align:center"> 1 17 1</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center"> 1 17 0</td><td style="text-align:center"> 1 17 0</td></tr>
</table>
</table>
-</p>
<p>
When an input pin pair is used as LVDS pair (IO standard
-<tt>SB_LVDS_INPUT</tt>, bank 3 / left edge only), then the four bits
-<tt>IoCtrl IE_0/IE_1</tt> and <tt>IoCtrl REN_0/REN_1</tt> are all set, as well
-as the <tt>IoCtrl LVDS</tt> bit.
+<span style="font-family:monospace">SB_LVDS_INPUT</span>, bank 3 / left edge only), then the four bits
+<span style="font-family:monospace">IoCtrl IE_0/IE_1</span> and <span style="font-family:monospace">IoCtrl REN_0/REN_1</span> are all set, as well
+as the <span style="font-family:monospace">IoCtrl LVDS</span> bit.
</p>
<p>
-In the iCE 8k devices the <tt>IoCtrl IE</tt> bits are active high. So an unused
+In the iCE 8k devices the <span style="font-family:monospace">IoCtrl IE</span> bits are active high. So an unused
IO tile on an 8k chip has all bits cleared.
</p>
@@ -276,55 +293,51 @@ tile are used. In IceBox nomenclature such bits are called "extra bits".
<p>
The following table lists which pins / IO blocks may be used to drive
-which global net, and what <tt>.extra</tt> statements in the IceBox ASCII file
+which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceBox ASCII file
format to represent the corresponding configuration bits:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Glb Net</th><th>Pin<br/>(HX1K-TQ144)</th><th>IO Tile +<br/>Block #</th><th>IceBox Statement</th></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">0</td><td align="center"> 93</td><td align="center">13 8 1</td><td align="center">.extra_bit 0 330 142</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">1</td><td align="center"> 21</td><td align="center"> 0 8 1</td><td align="center">.extra_bit 0 331 142</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">2</td><td align="center">128</td><td align="center"> 7 17 0</td><td align="center">.extra_bit 1 330 143</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">3</td><td align="center"> 50</td><td align="center"> 7 0 0</td><td align="center">.extra_bit 1 331 143</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">4</td><td align="center"> 20</td><td align="center"> 0 9 0</td><td align="center">.extra_bit 1 330 142</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">5</td><td align="center"> 94</td><td align="center">13 9 0</td><td align="center">.extra_bit 1 331 142</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">6</td><td align="center"> 49</td><td align="center"> 6 0 1</td><td align="center">.extra_bit 0 330 143</td></tr>
-<tr style="white-space: pre; font-family: monospace"><td align="center">7</td><td align="center">129</td><td align="center"> 6 17 1</td><td align="center">.extra_bit 0 331 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">0</td><td style="text-align:center"> 93</td><td style="text-align:center">13 8 1</td><td style="text-align:center">.extra_bit 0 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">1</td><td style="text-align:center"> 21</td><td style="text-align:center"> 0 8 1</td><td style="text-align:center">.extra_bit 0 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">2</td><td style="text-align:center">128</td><td style="text-align:center"> 7 17 0</td><td style="text-align:center">.extra_bit 1 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">3</td><td style="text-align:center"> 50</td><td style="text-align:center"> 7 0 0</td><td style="text-align:center">.extra_bit 1 331 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">4</td><td style="text-align:center"> 20</td><td style="text-align:center"> 0 9 0</td><td style="text-align:center">.extra_bit 1 330 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">5</td><td style="text-align:center"> 94</td><td style="text-align:center">13 9 0</td><td style="text-align:center">.extra_bit 1 331 142</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">6</td><td style="text-align:center"> 49</td><td style="text-align:center"> 6 0 1</td><td style="text-align:center">.extra_bit 0 330 143</td></tr>
+<tr style="white-space: pre; font-family: monospace"><td style="text-align:center">7</td><td style="text-align:center">129</td><td style="text-align:center"> 6 17 1</td><td style="text-align:center">.extra_bit 0 331 143</td></tr>
</table>
-</p>
<p>
Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal
-to the <tt>fabout</tt> net on an IO tile. The same set of I/O tiles is used for this, but in this
+to the <span style="font-family:monospace">fabout</span> net on an IO tile. The same set of I/O tiles is used for this, but in this
case each of the I/O tiles corresponds to a different global net:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Glb Net</th>
-<td align="center">0</td>
-<td align="center">1</td>
-<td align="center">2</td>
-<td align="center">3</td>
-<td align="center">4</td>
-<td align="center">5</td>
-<td align="center">6</td>
-<td align="center">7</td></tr>
+<td style="text-align:center">0</td>
+<td style="text-align:center">1</td>
+<td style="text-align:center">2</td>
+<td style="text-align:center">3</td>
+<td style="text-align:center">4</td>
+<td style="text-align:center">5</td>
+<td style="text-align:center">6</td>
+<td style="text-align:center">7</td></tr>
<tr><th>IO Tile</th>
-<td style="white-space: pre; font-family: monospace" align="center"> 7 0</td>
-<td style="white-space: pre; font-family: monospace" align="center"> 7 17</td>
-<td style="white-space: pre; font-family: monospace" align="center">13 9</td>
-<td style="white-space: pre; font-family: monospace" align="center"> 0 9</td>
-<td style="white-space: pre; font-family: monospace" align="center"> 6 17</td>
-<td style="white-space: pre; font-family: monospace" align="center"> 6 0</td>
-<td style="white-space: pre; font-family: monospace" align="center"> 0 8</td>
-<td style="white-space: pre; font-family: monospace" align="center">13 8</td></tr>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 7 0</td>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 7 17</td>
+<td style="white-space: pre; font-family: monospace; text-align:center">13 9</td>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 0 9</td>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 6 17</td>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 6 0</td>
+<td style="white-space: pre; font-family: monospace; text-align:center"> 0 8</td>
+<td style="white-space: pre; font-family: monospace; text-align:center">13 8</td></tr>
</table>
-</p>
-<p><a href="colbuf.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="colbuf.svg" border="0"></a></p>
+<p><a href="colbuf.svg"><img alt="Column Buffers" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="colbuf.svg"></a></p>
<h3>Column Buffer Control Bits</h3>
@@ -344,147 +357,142 @@ IO columns.
<h2>Warmboot</h2>
<p>
-The <tt>SB_WARMBOOT</tt> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell
-are driven by the <tt>fabout</tt> signal from three IO tiles. In HX1K chips the tiles connected to the
-<tt>SB_WARMBOOT</tt> primitive are:
+The <span style="font-family:monospace">SB_WARMBOOT</span> primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell
+are driven by the <span style="font-family:monospace">fabout</span> signal from three IO tiles. In HX1K chips the tiles connected to the
+<span style="font-family:monospace">SB_WARMBOOT</span> primitive are:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Warmboot Pin</th><th>IO Tile</th></tr>
-<tr><td>BOOT</td><td><tt>12 0</tt></td></tr>
-<tr><td>S0</td><td><tt>13 1</tt></td></tr>
-<tr><td>S1</td><td><tt>13 2</tt></td></tr>
+<tr><td>BOOT</td><td><span style="font-family:monospace">12 0</span></td></tr>
+<tr><td>S0</td><td><span style="font-family:monospace">13 1</span></td></tr>
+<tr><td>S1</td><td><span style="font-family:monospace">13 2</span></td></tr>
</table>
-</p>
<h2>PLL Cores</h2>
<p>
-The PLL primitives in iCE40 FPGAs are configured using the <tt>PLLCONFIG_*</tt>
+The PLL primitives in iCE40 FPGAs are configured using the <span style="font-family:monospace">PLLCONFIG_*</span>
bits in the IO tiles. The configuration for a single PLL cell is spread out
over many IO tiles. For example, the PLL cell in the 1K chip are configured as
follows (bits listed from LSB to MSB):
</p>
-<p align="center">
-<table cellpadding="10"><tr><td valign="top">
+<table class="xtab">
+<tr><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3">Select PLL Type:<br/>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="3">Select PLL Type:<br/>
000 = DISABLED<br/>
010 = SB_PLL40_PAD<br/>
100 = SB_PLL40_2_PAD<br/>
110 = SB_PLL40_2F_PAD<br/>
011 = SB_PLL40_CORE<br/>
111 = SB_PLL40_2F_CORE</td></tr>
-<tr><td>0 5</td><td><tt>PLLCONFIG_1</tt></td></tr>
-<tr><td>0 5</td><td><tt>PLLCONFIG_3</tt></td></tr>
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr>
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr>
-<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="3"><tt>FEEDBACK_PATH</tt><br/>
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="3"><span style="font-family:monospace">FEEDBACK_PATH</span><br/>
000 = "DELAY"<br/>
001 = "SIMPLE"<br/>
010 = "PHASE_AND_DELAY"<br/>
110 = "EXTERNAL"</td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_9</tt></td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_1</tt></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_FEEDBACK</tt><br/>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td><td rowspan="1"><span style="font-family:monospace">DELAY_ADJUSTMENT_MODE_FEEDBACK</span><br/>
0 = "FIXED"<br/>
1 = "DYNAMIC"</td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="1"><tt>DELAY_ADJUSTMENT_MODE_RELATIVE</tt><br/>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td><td rowspan="1"><span style="font-family:monospace">DELAY_ADJUSTMENT_MODE_RELATIVE</span><br/>
0 = "FIXED"<br/>
1 = "DYNAMIC"</td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="2"><tt>PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</tt><br/>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td><td rowspan="2"><span style="font-family:monospace">PLLOUT_SELECT<br/>PLLOUT_SELECT_PORTA</span><br/>
00 = "GENCLK"<br/>
01 = "GENCLK_HALF"<br/>
10 = "SHIFTREG_90deg"<br/>
11 = "SHIFTREG_0deg"</td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_7</tt></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_2</tt></td><td rowspan="2"><tt>PLLOUT_SELECT_PORTB</tt><br/>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td><td rowspan="2"><span style="font-family:monospace">PLLOUT_SELECT_PORTB</span><br/>
00 = "GENCLK"<br/>
01 = "GENCLK_HALF"<br/>
10 = "SHIFTREG_90deg"<br/>
11 = "SHIFTREG_0deg"</td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_3</tt></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_4</tt></td><td rowspan="1"><tt>SHIFTREG_DIV_MODE</tt></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td><td rowspan="1"><span style="font-family:monospace">SHIFTREG_DIV_MODE</span></td></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_8</tt></td><td rowspan="1"><tt>TEST_MODE</tt></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td><td rowspan="1"><span style="font-family:monospace">TEST_MODE</span></td></tr>
-</table></td><td valign="top">
+</table></td><td>
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>IO Tile</th><th>Config Bit</th><th>SB_PLL40_* Parameter</th></tr>
-<tr><td>0 3</td><td><tt>PLLCONFIG_9</tt></td><td rowspan="4"><tt>FDA_FEEDBACK</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_1</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_2</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_3</tt></td></tr>
-
-<tr><td>0 5</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="4"><tt>FDA_RELATIVE</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_6</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_7</tt></td></tr>
-<tr><td>0 4</td><td><tt>PLLCONFIG_8</tt></td></tr>
-
-<tr><td>0 1</td><td><tt>PLLCONFIG_1</tt></td><td rowspan="4"><tt>DIVR</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_2</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_3</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_4</tt></td></tr>
-
-<tr><td>0 1</td><td><tt>PLLCONFIG_5</tt></td><td rowspan="7"><tt>DIVF</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_6</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_7</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_8</tt></td></tr>
-<tr><td>0 1</td><td><tt>PLLCONFIG_9</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_1</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_2</tt></td></tr>
-
-<tr><td>0 2</td><td><tt>PLLCONFIG_3</tt></td><td rowspan="3"><tt>DIVQ</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_4</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_5</tt></td></tr>
-
-<tr><td>0 2</td><td><tt>PLLCONFIG_6</tt></td><td rowspan="3"><tt>FILTER_RANGE</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_7</tt></td></tr>
-<tr><td>0 2</td><td><tt>PLLCONFIG_8</tt></td></tr>
+<tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td><td rowspan="4"><span style="font-family:monospace">FDA_FEEDBACK</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr>
+
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="4"><span style="font-family:monospace">FDA_RELATIVE</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr>
+
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td><td rowspan="4"><span style="font-family:monospace">DIVR</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td></tr>
+
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td><td rowspan="7"><span style="font-family:monospace">DIVF</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">PLLCONFIG_9</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_1</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td></tr>
+
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_3</span></td><td rowspan="3"><span style="font-family:monospace">DIVQ</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_5</span></td></tr>
+
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_6</span></td><td rowspan="3"><span style="font-family:monospace">FILTER_RANGE</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_7</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td></tr>
</table>
</table>
-</p>
<p>
-The PLL inputs are routed to the PLL via the <tt>fabout</tt> signal from various IO tiles. The non-clock
-PLL outputs are routed via otherwise unused <tt>neigh_op_*</tt> signals in fabric corners. For example in case
+The PLL inputs are routed to the PLL via the <span style="font-family:monospace">fabout</span> signal from various IO tiles. The non-clock
+PLL outputs are routed via otherwise unused <span style="font-family:monospace">neigh_op_*</span> signals in fabric corners. For example in case
of the 1k chip:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Tile</th><th>Net-Segment</th><th>SB_PLL40_* Port Name</th></tr>
-<tr><td>0 1</td><td><tt>fabout</tt></td><td rowspan="1"><tt>REFERENCECLK</tt></td></tr>
-<tr><td>0 2</td><td><tt>fabout</tt></td><td rowspan="1"><tt>EXTFEEDBACK</tt></td></tr>
-<tr><td>0 4</td><td><tt>fabout</tt></td><td rowspan="8"><tt>DYNAMICDELAY</tt></td></tr>
-<tr><td>0 5</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 6</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 10</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 11</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 12</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 13</td><td><tt>fabout</tt></td></tr>
-<tr><td>0 14</td><td><tt>fabout</tt></td></tr>
-<tr><td>1 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>LOCK</tt></td></tr>
-<tr><td>1 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>BYPASS</tt></td></tr>
-<tr><td>2 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>RESETB</tt></td></tr>
-<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>LATCHINPUTVALUE</tt></td></tr>
-<tr><td>12 1</td><td><tt>neigh_op_bnl_1</tt></td><td rowspan="1"><tt>SDO</tt></td></tr>
-<tr><td>4 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SDI</tt></td></tr>
-<tr><td>5 0</td><td><tt>fabout</tt></td><td rowspan="1"><tt>SCLK</tt></td></tr>
+<tr><td>0 1</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">REFERENCECLK</span></td></tr>
+<tr><td>0 2</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">EXTFEEDBACK</span></td></tr>
+<tr><td>0 4</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="8"><span style="font-family:monospace">DYNAMICDELAY</span></td></tr>
+<tr><td>0 5</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 6</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 10</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 11</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 12</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 13</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>0 14</td><td><span style="font-family:monospace">fabout</span></td></tr>
+<tr><td>1 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">LOCK</span></td></tr>
+<tr><td>1 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">BYPASS</span></td></tr>
+<tr><td>2 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">RESETB</span></td></tr>
+<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">LATCHINPUTVALUE</span></td></tr>
+<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr>
+<tr><td>4 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SDI</span></td></tr>
+<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr>
</table>
-</p>
<p>
The PLL clock outputs are fed directly into the input path of certain IO tiles.
@@ -494,3 +502,4 @@ PIOs can only be used as output Pins by the FPGA fabric when the PLL ports
are being used.
</p>
+</body></html>
diff --git a/docs/logic_tile.html b/docs/logic_tile.html
index 6404a80..67524bb 100644
--- a/docs/logic_tile.html
+++ b/docs/logic_tile.html
@@ -1,4 +1,18 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
+<style>
+.ctab {
+ margin-left: auto;
+ margin-right: auto;
+ border: 1px solid gray;
+}
+.ctab td, .ctab th {
+ padding: 3px;
+ border: 1px solid gray;
+}
+</style>
<title>Project IceStorm – LOGIC Tile Documentation</title>
+</head><body>
<h1>Project IceStorm – LOGIC Tile Documentation</h1>
<p>
@@ -15,9 +29,9 @@ The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in
</p>
<p>
-The bits marked <tt>routing</tt> in the bitstream do enable switches (transfer gates) that can
+The bits marked <span style="font-family:monospace">routing</span> in the bitstream do enable switches (transfer gates) that can
be used to connect wire segments bidirectionally to each other in order to create larger
-segments. The bits marked <tt>buffer</tt> in the bitstream enable tristate buffers that drive
+segments. The bits marked <span style="font-family:monospace">buffer</span> in the bitstream enable tristate buffers that drive
the signal in one direction from one wire to another. Both types of bits exist for routing between
span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
</p>
@@ -28,21 +42,21 @@ Only directional tristate buffers are used to route signals between the span-wir
<h3 style="clear:both">Span-4 Horizontal</h3>
-<p><a href="sp4h.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4h.svg" border="0"></a></p>
+<p><a href="sp4h.svg"><img alt="Span-4 Horizontal" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="sp4h.svg"></a></p>
<p>
The image on the right shows the <i>horizontal span-4</i> wires of a logic or ram cell (click to enlarge).
</p>
<p>
-On the left side of the cell there are 48 connections named <tt>sp4_h_l_0</tt> to <tt>sp4_h_l_47</tt>. The lower 36 of those
-wires are connected to <tt>sp4_h_r_12</tt> to <tt>sp4_h_r_47</tt> on the right side of the cell. (IceStorm normalizes this
-wire names to <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_35</tt>. Note: the Lattice tools use a different normalization scheme
+On the left side of the cell there are 48 connections named <span style="font-family:monospace">sp4_h_l_0</span> to <span style="font-family:monospace">sp4_h_l_47</span>. The lower 36 of those
+wires are connected to <span style="font-family:monospace">sp4_h_r_12</span> to <span style="font-family:monospace">sp4_h_r_47</span> on the right side of the cell. (IceStorm normalizes this
+wire names to <span style="font-family:monospace">sp4_h_r_0</span> to <span style="font-family:monospace">sp4_h_r_35</span>. Note: the Lattice tools use a different normalization scheme
for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.
</p>
<p>
-The wires <tt>sp4_h_l_36</tt> to <tt>sp4_h_l_47</tt> terminate in the cell, so do the wires <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_11</tt>.
+The wires <span style="font-family:monospace">sp4_h_l_36</span> to <span style="font-family:monospace">sp4_h_l_47</span> terminate in the cell, so do the wires <span style="font-family:monospace">sp4_h_r_0</span> to <span style="font-family:monospace">sp4_h_r_11</span>.
</p>
<p>
@@ -51,55 +65,51 @@ both ends of the wire.
</p>
<p>
-For example, the wire <tt>sp4_h_r_0</tt> in cell (x, y) has the following names:
+For example, the wire <span style="font-family:monospace">sp4_h_r_0</span> in cell (x, y) has the following names:
</p>
-<p align="center">
-<table border>
+<table class="ctab">
<tr><th>Cell Coordinates</th><th>sp4_h_l_* wire name</th><th>sp4_h_r_* wire name</th></tr>
-<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_h_r_0</tt></td></tr>
-<tr><td>x+1, y</td><td><tt>sp4_h_l_0</tt></td><td><tt>sp4_h_r_13</tt></td></tr>
-<tr><td>x+2, y</td><td><tt>sp4_h_l_13</tt></td><td><tt>sp4_h_r_24</tt></td></tr>
-<tr><td>x+3, y</td><td><tt>sp4_h_l_24</tt></td><td><tt>sp4_h_r_37</tt></td></tr>
-<tr><td>x+4, y</td><td><tt>sp4_h_l_37</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_h_r_0</span></td></tr>
+<tr><td>x+1, y</td><td><span style="font-family:monospace">sp4_h_l_0</span></td><td><span style="font-family:monospace">sp4_h_r_13</span></td></tr>
+<tr><td>x+2, y</td><td><span style="font-family:monospace">sp4_h_l_13</span></td><td><span style="font-family:monospace">sp4_h_r_24</span></td></tr>
+<tr><td>x+3, y</td><td><span style="font-family:monospace">sp4_h_l_24</span></td><td><span style="font-family:monospace">sp4_h_r_37</span></td></tr>
+<tr><td>x+4, y</td><td><span style="font-family:monospace">sp4_h_l_37</span></td><td><span style="font-family:monospace">-</span></td></tr>
</table>
-</p>
<h3 style="clear:both">Span-4 Vertical</h3>
-<p><a href="sp4v.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4v.svg" border="0"></a></p>
+<p><a href="sp4v.svg"><img alt="Span-4 Vertical" style="float:right; padding:1em; padding-top:0; border:0" height="200" src="sp4v.svg"></a></p>
<p>
The image on the right shows the <i>vertical span-4</i> wires of a logic or ram cell (click to enlarge).
</p>
<p>
-Similar to the horizontal span-4 wires there are 48 connections on the top (<tt>sp4_v_t_0</tt> to <tt>sp4_v_t_47</tt>) and
-48 connections on the bottom (<tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt>). The wires <tt>sp4_v_t_0</tt> to <tt>sp4_v_t_35</tt>
-are connected to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt> (with pairwise crossing out). Wire names are normalized
-to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt>.
+Similar to the horizontal span-4 wires there are 48 connections on the top (<span style="font-family:monospace">sp4_v_t_0</span> to <span style="font-family:monospace">sp4_v_t_47</span>) and
+48 connections on the bottom (<span style="font-family:monospace">sp4_v_b_0</span> to <span style="font-family:monospace">sp4_v_b_47</span>). The wires <span style="font-family:monospace">sp4_v_t_0</span> to <span style="font-family:monospace">sp4_v_t_35</span>
+are connected to <span style="font-family:monospace">sp4_v_b_12</span> to <span style="font-family:monospace">sp4_v_b_47</span> (with pairwise crossing out). Wire names are normalized
+to <span style="font-family:monospace">sp4_v_b_12</span> to <span style="font-family:monospace">sp4_v_b_47</span>.
</p>
<p>
-But in addition to that, each cell also has access to <tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt> of its right neighbour.
-This are the wires <tt>sp4_r_v_b_0</tt> to <tt>sp4_r_v_b_47</tt>. So over all a single vertical span-4 wire
-connects 9 cells. For example, the wire <tt>sp4_v_b_0</tt> in cell (x, y) has the following names:
+But in addition to that, each cell also has access to <span style="font-family:monospace">sp4_v_b_0</span> to <span style="font-family:monospace">sp4_v_b_47</span> of its right neighbour.
+This are the wires <span style="font-family:monospace">sp4_r_v_b_0</span> to <span style="font-family:monospace">sp4_r_v_b_47</span>. So over all a single vertical span-4 wire
+connects 9 cells. For example, the wire <span style="font-family:monospace">sp4_v_b_0</span> in cell (x, y) has the following names:
</p>
-<p align="center">
-<table border>
+<table class="ctab">
<tr><th>Cell Coordinates</th><th>sp4_v_t_* wire name</th><th>sp4_v_b_* wire name</th><th>sp4_r_v_b_* wire name</th></tr>
-<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_v_b_0</tt></td><td><tt>-</tt></td></tr>
-<tr><td>x, y-1</td><td><tt>sp4_v_t_0</tt></td><td><tt>sp4_v_b_13</tt></td><td><tt>-</tt></td></tr>
-<tr><td>x, y-2</td><td><tt>sp4_v_t_13</tt></td><td><tt>sp4_v_b_24</tt></td><td><tt>-</tt></td></tr>
-<tr><td>x, y-3</td><td><tt>sp4_v_t_24</tt></td><td><tt>sp4_v_b_37</tt></td><td><tt>-</tt></td></tr>
-<tr><td>x, y-4</td><td><tt>sp4_v_t_37</tt></td><td><tt>-</tt></td><td><tt>-</tt></td></tr>
-<tr><td>x-1, y</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_0</tt></td></tr>
-<tr><td>x-1, y-1</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_13</tt></td></tr>
-<tr><td>x-1, y-2</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_24</tt></td></tr>
-<tr><td>x-1, y-3</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_37</tt></td></tr>
+<tr><td>x, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_v_b_0</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td>x, y-1</td><td><span style="font-family:monospace">sp4_v_t_0</span></td><td><span style="font-family:monospace">sp4_v_b_13</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td>x, y-2</td><td><span style="font-family:monospace">sp4_v_t_13</span></td><td><span style="font-family:monospace">sp4_v_b_24</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td>x, y-3</td><td><span style="font-family:monospace">sp4_v_t_24</span></td><td><span style="font-family:monospace">sp4_v_b_37</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td>x, y-4</td><td><span style="font-family:monospace">sp4_v_t_37</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td>x-1, y</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_0</span></td></tr>
+<tr><td>x-1, y-1</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_13</span></td></tr>
+<tr><td>x-1, y-2</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_24</span></td></tr>
+<tr><td>x-1, y-3</td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">sp4_r_v_b_37</span></td></tr>
</table>
-</p>
<h3 style="clear:both">Span-12 Horizontal and Vertical</h3>
@@ -108,21 +118,21 @@ Similar to the span-4 wires there are also longer horizontal and vertical span-1
</p>
<p>
-There are 24 connections <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_23</tt> on the top of the
-cell and 24 connections <tt>sp12_v_b_0</tt> to <tt>sp12_v_b_23</tt> on the bottom of the
-cell. The wires <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_21</tt> are connected to
-<tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt> (with pairwise crossing out). The connections
-<tt>sp12_v_b_0</tt>, <tt>sp12_v_b_1</tt>, <tt>sp12_v_t_22</tt>, and <tt>sp12_v_t_23</tt>
-terminate in the cell. Wire names are normalized to <tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt>.
+There are 24 connections <span style="font-family:monospace">sp12_v_t_0</span> to <span style="font-family:monospace">sp12_v_t_23</span> on the top of the
+cell and 24 connections <span style="font-family:monospace">sp12_v_b_0</span> to <span style="font-family:monospace">sp12_v_b_23</span> on the bottom of the
+cell. The wires <span style="font-family:monospace">sp12_v_t_0</span> to <span style="font-family:monospace">sp12_v_t_21</span> are connected to
+<span style="font-family:monospace">sp12_v_b_2</span> to <span style="font-family:monospace">sp12_v_b_23</span> (with pairwise crossing out). The connections
+<span style="font-family:monospace">sp12_v_b_0</span>, <span style="font-family:monospace">sp12_v_b_1</span>, <span style="font-family:monospace">sp12_v_t_22</span>, and <span style="font-family:monospace">sp12_v_t_23</span>
+terminate in the cell. Wire names are normalized to <span style="font-family:monospace">sp12_v_b_2</span> to <span style="font-family:monospace">sp12_v_b_23</span>.
</p>
<p>
-There are also 24 connections <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_23</tt> on the left of the
-cell and 24 connections <tt>sp12_h_r_0</tt> to <tt>sp12_h_r_23</tt> on the right of the
-cell. The wires <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_21</tt> are connected to
-<tt>sp12_h_r_2</tt> to <tt>sp12_h_r_23</tt> (with pairwise crossing out). The connections
-<tt>sp12_h_r_0</tt>, <tt>sp12_h_r_1</tt>, <tt>sp12_h_l_22</tt>, and <tt>sp12_h_l_23</tt>
-terminate in the cell. Wire names are normalized to <tt>sp12_v_r_2</tt> to <tt>sp12_h_r_23</tt>.
+There are also 24 connections <span style="font-family:monospace">sp12_h_l_0</span> to <span style="font-family:monospace">sp12_h_l_23</span> on the left of the
+cell and 24 connections <span style="font-family:monospace">sp12_h_r_0</span> to <span style="font-family:monospace">sp12_h_r_23</span> on the right of the
+cell. The wires <span style="font-family:monospace">sp12_h_l_0</span> to <span style="font-family:monospace">sp12_h_l_21</span> are connected to
+<span style="font-family:monospace">sp12_h_r_2</span> to <span style="font-family:monospace">sp12_h_r_23</span> (with pairwise crossing out). The connections
+<span style="font-family:monospace">sp12_h_r_0</span>, <span style="font-family:monospace">sp12_h_r_1</span>, <span style="font-family:monospace">sp12_h_l_22</span>, and <span style="font-family:monospace">sp12_h_l_23</span>
+terminate in the cell. Wire names are normalized to <span style="font-family:monospace">sp12_v_r_2</span> to <span style="font-family:monospace">sp12_h_r_23</span>.
</p>
<h2>Local Tracks</h2>
@@ -135,7 +145,7 @@ signals from the local tracks can be routed to the logic cell inputs.
<p>
Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each:
-<tt>local_g0_0</tt> to <tt>local_g3_7</tt>.
+<span style="font-family:monospace">local_g0_0</span> to <span style="font-family:monospace">local_g3_7</span>.
</p>
<p>
@@ -146,71 +156,59 @@ mix of 16 signals for each local track.
<p>
The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select
-the input wire. For example for <tt>local_g0_0</tt> (copy&paste from the bitstream doku):
+the input wire. For example for <span style="font-family:monospace">local_g0_0</span> (copy&paste from the bitstream doku):
</p>
-<p align="center">
-<table border=""><tbody><tr>
-<th style="width:5em"><a name="B.0.14">B0[14]</a></th>
-<th style="width:5em"><a name="B.1.14">B1[14]</a></th>
-<th style="width:5em"><a name="B.1.15">B1[15]</a></th>
-<th style="width:5em"><a name="B.1.16">B1[16]</a></th>
-<th style="width:5em"><a name="B.1.17">B1[17]</a></th>
+<table class="ctab">
+<tr><th style="width:5em">B0[14]</th><th style="width:5em">B1[14]</th><th style="width:5em">B1[15]</th><th style="width:5em">B1[16]</th> <th style="width:5em">B1[17]</th>
<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_24</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bot_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_16</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_35</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_top_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>lutff_0/out</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_lft_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bnr_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_8</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
-</tbody></table>
-</p>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_r_v_b_24</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp12_h_r_8</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_bot_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_v_b_16</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_r_v_b_35</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp12_h_r_16</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_top_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">lutff_0/out</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_v_b_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_lft_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_8</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">neigh_op_bnr_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_v_b_8</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp12_h_r_0</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">sp4_h_r_16</span></td><td><span style="font-family:monospace">local_g0_0</span></td></tr>
+</table>
<p>
Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before,
not every local track can be routed to every logic cell input pin. Instead there is a different mix
-of 16 local track for each logic cell input. For example for <tt>lutff_0/in_0</tt>:
+of 16 local track for each logic cell input. For example for <span style="font-family:monospace">lutff_0/in_0</span>:
</p>
-<p align="center">
-<table border=""><tbody><tr>
-<th style="width:5em"><a name="B.0.26">B0[26]</a></th>
-<th style="width:5em"><a name="B.1.26">B1[26]</a></th>
-<th style="width:5em"><a name="B.1.27">B1[27]</a></th>
-<th style="width:5em"><a name="B.1.28">B1[28]</a></th>
-<th style="width:5em"><a name="B.1.29">B1[29]</a></th>
+<table class="ctab">
+<tr><th style="width:5em">B0[26]</th><th style="width:5em">B1[26]</th><th style="width:5em">B1[27]</th><th style="width:5em">B1[28]</th><th style="width:5em">B1[29]</th>
<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
-</tbody></table>
-</p>
-
-<p>
-The 8 global nets on the iCE40 can be routed to the local track via the <tt>glb2local_0</tt> to <tt>glb2local_3</tt>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_0</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_0</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_1</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_1</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_2</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_2</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_3</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_3</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_4</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_4</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_5</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_5</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g0_6</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g2_6</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g1_7</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">buffer</td><td><span style="font-family:monospace">local_g3_7</span></td><td><span style="font-family:monospace">lutff_0/in_0</span></td></tr>
+</table>
+
+<p>
+The 8 global nets on the iCE40 can be routed to the local track via the <span style="font-family:monospace">glb2local_0</span> to <span style="font-family:monospace">glb2local_3</span>
nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven
directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven
from any of the global nets and from a few local tracks. See the bitstream documentation for details.
@@ -227,97 +225,93 @@ or asynchronous exist for each logic cell individually.
</p>
<p>
-Each LUT <i>i</i> has four input wires <tt>lutff_<i>i</i>/in_0</tt> to <tt>lutff_<i>i</i>/in_3</tt>. Input
-<tt>lutff_<i>i</i>/in_3</tt> can be configured to be driven by the carry output of the previous logic cell,
-or by <tt>carry_in_mux</tt> in case of <i>i</i>=0. Input <tt>lutff_<i>i</i>/in_2</tt> can be configured to
+Each LUT <i>i</i> has four input wires <span style="font-family:monospace">lutff_<i>i</i>/in_0</span> to <span style="font-family:monospace">lutff_<i>i</i>/in_3</span>. Input
+<span style="font-family:monospace">lutff_<i>i</i>/in_3</span> can be configured to be driven by the carry output of the previous logic cell,
+or by <span style="font-family:monospace">carry_in_mux</span> in case of <i>i</i>=0. Input <span style="font-family:monospace">lutff_<i>i</i>/in_2</span> can be configured to
be driven by the output of the previous LUT for <i>i</i>>0. The LUT uses its 4 input signals to
-calculate <tt>lutff_<i>i</i>/out</tt>.
+calculate <span style="font-family:monospace">lutff_<i>i</i>/out</span>.
</p>
<p>
-The carry unit calculates <tt>lutff_<i>i</i>/cout</tt> = <tt>lutff_<i>i</i>/in_1</tt> + <tt>lutff_<i>i</i>/in_2</tt> + <tt>lutff_<i>(i-1)</i>/cout</tt> > 1</tt>. In case of <i>i</i>=0, <tt>carry_in_mux</tt> is used as third input. <tt>carry_in_mux</tt> can be configured to be constant 0, 1 or the <tt>lutff_7/cout</tt> signal from the logic tile below.
+The carry unit calculates <span style="font-family:monospace">lutff_<i>i</i>/cout</span> = <span style="font-family:monospace">lutff_<i>i</i>/in_1</span> + <span style="font-family:monospace">lutff_<i>i</i>/in_2</span> + <span style="font-family:monospace">lutff_<i>(i-1)</i>/cout</span> > 1. In case of <i>i</i>=0, <span style="font-family:monospace">carry_in_mux</span> is used as third input. <span style="font-family:monospace">carry_in_mux</span> can be configured to be constant 0, 1 [...]
</p>
<p>
Part of the functionality described above is documented as part of the routing
-bitstream documentation (see the buffers for <tt>lutff_</tt> inputs). The <tt>NegClk</tt>
-bit switches all 8 FFs in the tile to negative edge mode. The <tt>CarryInSet</tt>
-bit drives the <tt>carry_in_mux</tt> high (it defaults to low when not driven via the buffer from
-<tt>carry_in</tt>).
+bitstream documentation (see the buffers for <span style="font-family:monospace">lutff_</span> inputs). The <span style="font-family:monospace">NegClk</span>
+bit switches all 8 FFs in the tile to negative edge mode. The <span style="font-family:monospace">CarryInSet</span>
+bit drives the <span style="font-family:monospace">carry_in_mux</span> high (it defaults to low when not driven via the buffer from
+<span style="font-family:monospace">carry_in</span>).
</p>
<p>
-The remaining functions of the logic cell are configured via the <tt>LC_<i>i</i></tt> bits. This
+The remaining functions of the logic cell are configured via the <span style="font-family:monospace">LC_<i>i</i></span> bits. This
are 20 bit per logic cell. We have arbitrarily labeled those bits as follows:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>Label</th><th>LC_0</th><th>LC_1</th><th>LC_2</th><th>LC_3</th><th>LC_4</th><th>LC_5</th><th>LC_6</th><th>LC_7</th></tr>
-<tr><td>LC_<i>i</i>[0]</tt></td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr>
-<tr><td>LC_<i>i</i>[1]</tt></td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr>
-<tr><td>LC_<i>i</i>[2]</tt></td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr>
-<tr><td>LC_<i>i</i>[3]</tt></td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr>
-<tr><td>LC_<i>i</i>[4]</tt></td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr>
-<tr><td>LC_<i>i</i>[5]</tt></td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr>
-<tr><td>LC_<i>i</i>[6]</tt></td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr>
-<tr><td>LC_<i>i</i>[7]</tt></td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr>
-<tr><td>LC_<i>i</i>[8]</tt></td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr>
-<tr><td>LC_<i>i</i>[9]</tt></td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr>
-<tr><td>LC_<i>i</i>[10]</tt></td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr>
-<tr><td>LC_<i>i</i>[11]</tt></td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr>
-<tr><td>LC_<i>i</i>[12]</tt></td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr>
-<tr><td>LC_<i>i</i>[13]</tt></td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr>
-<tr><td>LC_<i>i</i>[14]</tt></td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr>
-<tr><td>LC_<i>i</i>[15]</tt></td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr>
-<tr><td>LC_<i>i</i>[16]</tt></td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr>
-<tr><td>LC_<i>i</i>[17]</tt></td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr>
-<tr><td>LC_<i>i</i>[18]</tt></td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr>
-<tr><td>LC_<i>i</i>[19]</tt></td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr>
+<tr><td>LC_<i>i</i>[0]</td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr>
+<tr><td>LC_<i>i</i>[1]</td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr>
+<tr><td>LC_<i>i</i>[2]</td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr>
+<tr><td>LC_<i>i</i>[3]</td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr>
+<tr><td>LC_<i>i</i>[4]</td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr>
+<tr><td>LC_<i>i</i>[5]</td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr>
+<tr><td>LC_<i>i</i>[6]</td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr>
+<tr><td>LC_<i>i</i>[7]</td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr>
+<tr><td>LC_<i>i</i>[8]</td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr>
+<tr><td>LC_<i>i</i>[9]</td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr>
+<tr><td>LC_<i>i</i>[10]</td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr>
+<tr><td>LC_<i>i</i>[11]</td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr>
+<tr><td>LC_<i>i</i>[12]</td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr>
+<tr><td>LC_<i>i</i>[13]</td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr>
+<tr><td>LC_<i>i</i>[14]</td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr>
+<tr><td>LC_<i>i</i>[15]</td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr>
+<tr><td>LC_<i>i</i>[16]</td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr>
+<tr><td>LC_<i>i</i>[17]</td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr>
+<tr><td>LC_<i>i</i>[18]</td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr>
+<tr><td>LC_<i>i</i>[19]</td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr>
</table>
-</p>
<p>
-<tt>LC_<i>i</i>[8]</tt> is the <tt>CarryEnable</tt> bit. This bit must be set if the carry logic is used.
+<span style="font-family:monospace">LC_<i>i</i>[8]</span> is the <span style="font-family:monospace">CarryEnable</span> bit. This bit must be set if the carry logic is used.
</p>
<p>
-<tt>LC_<i>i</i>[9]</tt> is the <tt>DffEnable</tt> bit. It enables the output flip-flop for the LUT.
+<span style="font-family:monospace">LC_<i>i</i>[9]</span> is the <span style="font-family:monospace">DffEnable</span> bit. It enables the output flip-flop for the LUT.
</p>
<p>
-<tt>LC_<i>i</i>[18]</tt> is the <tt>Set_NoReset</tt> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.
+<span style="font-family:monospace">LC_<i>i</i>[18]</span> is the <span style="font-family:monospace">Set_NoReset</span> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.
</p>
<p>
-<tt>LC_<i>i</i>[19]</tt> is the <tt>AsyncSetReset</tt> bit. When this bit is set then the set/reset signal is asynchronous to the clock.
+<span style="font-family:monospace">LC_<i>i</i>[19]</span> is the <span style="font-family:monospace">AsyncSetReset</span> bit. When this bit is set then the set/reset signal is asynchronous to the clock.
</p>
<p>
The LUT implements the following truth table:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>in_3</th><th>in_2</th><th>in_1</th><th>in_0</th><th>out</th></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[4]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[14]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[15]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[5]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[6]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[16]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[17]</tt></td></tr>
-<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[7]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[3]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[13]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[12]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[2]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[1]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[11]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[10]</tt></td></tr>
-<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[0]</tt></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[4]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[14]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[15]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[5]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[6]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[16]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[17]</span></td></tr>
+<tr><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[7]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[3]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[13]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[12]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[2]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[1]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[11]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">0</td><td><span style="font-family:monospace">LC_<i>i</i>[10]</span></td></tr>
+<tr><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td style="text-align:center">1</td><td><span style="font-family:monospace">LC_<i>i</i>[0]</span></td></tr>
</table>
-</p>
<p>
LUT inputs that are not connected to anything are driven low. The set/reset
@@ -325,3 +319,4 @@ signal is also driven low if not connected to any other driver, and the clock
enable signal is driven high when left unconnected.
</p>
+</body></html>
diff --git a/docs/ram_tile.html b/docs/ram_tile.html
index 3121f57..73bda8d 100644
--- a/docs/ram_tile.html
+++ b/docs/ram_tile.html
@@ -1,4 +1,18 @@
+<!DOCTYPE html>
+<html><head><meta charset="UTF-8">
+<style>
+.ctab {
+ margin-left: auto;
+ margin-right: auto;
+ border: 1px solid gray;
+}
+.ctab td, .ctab th {
+ padding: 3px;
+ border: 1px solid gray;
+}
+</style>
<title>Project IceStorm – RAM Tile Documentation</title>
+</head><body>
<h1>Project IceStorm – RAM Tile Documentation</h1>
<p>
@@ -21,75 +35,70 @@ tiles without logic cells in them.
A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with
LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram
inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates
-are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <tt>SB_RAM40_4K</tt> cell. The
+are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a <span style="font-family:monospace">SB_RAM40_4K</span> cell. The
cell ports are spread out over the two tiles as follows:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>SB_RAM40_4K</th><th>RAMB Tile</th><th>RAMT Tile</th></tr>
-<tr><td><tt>RDATA[15:0]</tt></td><td><tt>RDATA[7:0]</tt></td><td><tt>RDATA[15:8]</tt></td></tr>
-<tr><td><tt>RADDR[10:0]</tt></td><td><tt>-</tt></td><td><tt>RADDR[10:0]</tt></td></tr>
-<tr><td><tt>WADDR[10:0]</tt></td><td><tt>WADDR[10:0]</tt></td><td><tt>-</tt></td></tr>
-<tr><td><tt>MASK[15:0]</tt></td><td><tt>MASK[7:0]</tt></td><td><tt>MASK[15:8]</tt></td></tr>
-<tr><td><tt>WDATA[15:0]</tt></td><td><tt>WDATA[7:0]</tt></td><td><tt>WDATA[15:8]</tt></td></tr>
-<tr><td><tt>RCLKE</tt></td><td><tt>-</tt></td><td><tt>RCLKE</tt></td></tr>
-<tr><td><tt>RCLK</tt></td><td><tt>-</tt></td><td><tt>RCLK</tt></td></tr>
-<tr><td><tt>RE</tt></td><td><tt>-</tt></td><td><tt>RE</tt></td></tr>
-<tr><td><tt>WCLKE</tt></td><td><tt>WCLKE</tt></td><td><tt>-</tt></td></tr>
-<tr><td><tt>WCLK</tt></td><td><tt>WCLK</tt></td><td><tt>-</tt></td></tr>
-<tr><td><tt>WE</tt></td><td><tt>WE</tt></td><td><tt>-</tt></td></tr>
+<tr><td><span style="font-family:monospace">RDATA[15:0]</span></td><td><span style="font-family:monospace">RDATA[7:0]</span></td><td><span style="font-family:monospace">RDATA[15:8]</span></td></tr>
+<tr><td><span style="font-family:monospace">RADDR[10:0]</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RADDR[10:0]</span></td></tr>
+<tr><td><span style="font-family:monospace">WADDR[10:0]</span></td><td><span style="font-family:monospace">WADDR[10:0]</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td><span style="font-family:monospace">MASK[15:0]</span></td><td><span style="font-family:monospace">MASK[7:0]</span></td><td><span style="font-family:monospace">MASK[15:8]</span></td></tr>
+<tr><td><span style="font-family:monospace">WDATA[15:0]</span></td><td><span style="font-family:monospace">WDATA[7:0]</span></td><td><span style="font-family:monospace">WDATA[15:8]</span></td></tr>
+<tr><td><span style="font-family:monospace">RCLKE</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RCLKE</span></td></tr>
+<tr><td><span style="font-family:monospace">RCLK</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RCLK</span></td></tr>
+<tr><td><span style="font-family:monospace">RE</span></td><td><span style="font-family:monospace">-</span></td><td><span style="font-family:monospace">RE</span></td></tr>
+<tr><td><span style="font-family:monospace">WCLKE</span></td><td><span style="font-family:monospace">WCLKE</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td><span style="font-family:monospace">WCLK</span></td><td><span style="font-family:monospace">WCLK</span></td><td><span style="font-family:monospace">-</span></td></tr>
+<tr><td><span style="font-family:monospace">WE</span></td><td><span style="font-family:monospace">WE</span></td><td><span style="font-family:monospace">-</span></td></tr>
</table>
-</p>
<p>
-The configuration bit <tt>RamConfig PowerUp</tt> in the RAMB tile enables the memory. This bit
-is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <tt>icebox_explain.py</tt>
-will ignore all RAMB tiles that only have the <tt>RamConfig PowerUp</tt> bit set.
+The configuration bit <span style="font-family:monospace">RamConfig PowerUp</span> in the RAMB tile enables the memory. This bit
+is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that <span style="font-family:monospace">icebox_explain.py</span>
+will ignore all RAMB tiles that only have the <span style="font-family:monospace">RamConfig PowerUp</span> bit set.
</p>
<p>
-In 8k chips the <tt>RamConfig PowerUp</tt> bit is active-high. So an unused RAM block has all bits cleared
+In 8k chips the <span style="font-family:monospace">RamConfig PowerUp</span> bit is active-high. So an unused RAM block has all bits cleared
in the 8k config bitstream.
</p>
<p>
-The <tt>RamConfig CBIT_*</tt> bits in the RAMT tile configure the read/write width of the
-memory. Those bits map to the <tt>SB_RAM40_4K</tt> cell parameters as follows:
+The <span style="font-family:monospace">RamConfig CBIT_*</span> bits in the RAMT tile configure the read/write width of the
+memory. Those bits map to the <span style="font-family:monospace">SB_RAM40_4K</span> cell parameters as follows:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>SB_RAM40_4K</th><th>RAMT Config Bit</th></tr>
-<tr><td><tt>WRITE_MODE[0]</tt></td><td><tt>RamConfig CBIT_0</tt></td></tr>
-<tr><td><tt>WRITE_MODE[1]</tt></td><td><tt>RamConfig CBIT_1</tt></td></tr>
-<tr><td><tt>READ_MODE[0]</tt></td><td><tt>RamConfig CBIT_2</tt></td></tr>
-<tr><td><tt>READ_MODE[1]</tt></td><td><tt>RamConfig CBIT_3</tt></td></tr>
+<tr><td><span style="font-family:monospace">WRITE_MODE[0]</span></td><td><span style="font-family:monospace">RamConfig CBIT_0</span></td></tr>
+<tr><td><span style="font-family:monospace">WRITE_MODE[1]</span></td><td><span style="font-family:monospace">RamConfig CBIT_1</span></td></tr>
+<tr><td><span style="font-family:monospace">READ_MODE[0]</span></td><td><span style="font-family:monospace">RamConfig CBIT_2</span></td></tr>
+<tr><td><span style="font-family:monospace">READ_MODE[1]</span></td><td><span style="font-family:monospace">RamConfig CBIT_3</span></td></tr>
</table>
-</p>
<p>
The read/write mode selects the width of the read/write port:
</p>
-<p align="center">
-<table cellpadding="3" border>
+<table class="ctab">
<tr><th>MODE</th><th>DATA Width</th><th>Used WDATA/RDATA Bits</th></tr>
<tr><td>0</td><td>16</td><td>15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0</td></tr>
<tr><td>1</td><td>8</td><td>14, 12, 10, 8, 6, 4, 2, 0</td></tr>
<tr><td>2</td><td>4</td><td>13, 9, 5, 1</td></tr>
<tr><td>3</td><td>2</td><td>11, 3</td></tr>
</table>
-</p>
<p>
-The <tt>NegClk</tt> bit in the RAMB tile negates the polarity of the <tt>WCLK</tt> port,
-and the <tt>NegClk</tt> bit in the RAMT tile negates the polarity of the <tt>RCLK</tt> port.
+The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
+and the <span style="font-family:monospace">NegClk</span> bit in the RAMT tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
</p>
<p>
A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing
-with the <tt>RDATA</tt> outputs. Each RAMB tile exports its <tt>RDATA[7:0]</tt> outputs and each RAMT tile
-exports its <tt>RDATA[15:8]</tt> outputs via this mechanism.
+with the <span style="font-family:monospace">RDATA</span> outputs. Each RAMB tile exports its <span style="font-family:monospace">RDATA[7:0]</span> outputs and each RAMT tile
+exports its <span style="font-family:monospace">RDATA[15:8]</span> outputs via this mechanism.
</p>
+</body></html>
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