[clblas] 01/75: Fixing issue with beta == 0 in AutoGemm kernels

[Ghislain Vaillant]

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ghisvail-guest pushed a commit to branch debian/master
in repository clblas.

commit 1af16a8bdf3ef3b356054a9038afd2f0b94b0627
Author: Pavan Yalamanchili <pavan at arrayfire.com>
Date:   Thu Dec 17 14:10:23 2015 -0500

    Fixing issue with beta == 0 in AutoGemm kernels
---
 src/library/blas/AutoGemm/KernelOpenCL.py | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/library/blas/AutoGemm/KernelOpenCL.py b/src/library/blas/AutoGemm/KernelOpenCL.py
index ccf266f..d8b3871 100644
--- a/src/library/blas/AutoGemm/KernelOpenCL.py
+++ b/src/library/blas/AutoGemm/KernelOpenCL.py
@@ -162,12 +162,6 @@ def makeOpenCLKernelString(kernel):
         "  REG.s0 = mad( -ALPHA.s1, REG.s1, REG.s0 ); \\\\" + endLine +
         "  REG.s1 *= ALPHA.s0; \\\\" + endLine +
         "  REG.s1 = mad(  ALPHA.s1, type_mad_tmp, REG.s1 ); \\\\" + endLine +
-        "  /* (2) */ \\\\" + endLine +
-        "  REG.s0 = mad(  BETA.s0, DST.s0, REG.s0 ); \\\\" + endLine +
-        "  REG.s0 = mad( -BETA.s1, DST.s1, REG.s0 ); \\\\" + endLine +
-        "  REG.s1 = mad(  BETA.s1, DST.s0, REG.s1 ); \\\\" + endLine +
-        "  REG.s1 = mad(  BETA.s0, DST.s1, REG.s1 ); \\\\" + endLine +
-        "  /* (3) */ \\\\" + endLine +
         "  DST = REG;" + endLine )
 
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