[Glibc-bsd-commits] r3569 - branches/squeeze/kfreebsd-8/debian/patches

Robert Millan rmh at alioth.debian.org
Mon Jul 11 16:28:45 UTC 2011


Author: rmh
Date: 2011-07-11 16:28:45 +0000 (Mon, 11 Jul 2011)
New Revision: 3569

Modified:
   branches/squeeze/kfreebsd-8/debian/patches/000_msk_backport.diff
Log:
diff 000_msk_backport.diff against 8.1, not 8.2.

Modified: branches/squeeze/kfreebsd-8/debian/patches/000_msk_backport.diff
===================================================================
--- branches/squeeze/kfreebsd-8/debian/patches/000_msk_backport.diff	2011-07-11 16:16:04 UTC (rev 3568)
+++ branches/squeeze/kfreebsd-8/debian/patches/000_msk_backport.diff	2011-07-11 16:28:45 UTC (rev 3569)
@@ -3,7 +3,7 @@
 
 Patch obtained from 8-STABLE using:
 
-  svn diff http://svn.freebsd.org/base/release/8.2.0/sys/dev/msk \
+  svn diff http://svn.freebsd.org/base/release/8.1.0/sys/dev/msk \
     http://svn.freebsd.org/base/stable/8/sys/dev/msk
 
 --- a/sys/dev/msk/if_mskreg.h
@@ -83,7 +83,53 @@
  static int msk_init_rx_ring(struct msk_if_softc *);
  static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
  static void msk_init_tx_ring(struct msk_if_softc *);
-@@ -565,7 +571,7 @@
+@@ -399,9 +405,6 @@
+ {
+ 	struct msk_if_softc *sc_if;
+ 
+-	if (phy != PHY_ADDR_MARV)
+-		return (0);
+-
+ 	sc_if = device_get_softc(dev);
+ 
+ 	return (msk_phy_readreg(sc_if, phy, reg));
+@@ -440,9 +443,6 @@
+ {
+ 	struct msk_if_softc *sc_if;
+ 
+-	if (phy != PHY_ADDR_MARV)
+-		return (0);
+-
+ 	sc_if = device_get_softc(dev);
+ 
+ 	return (msk_phy_writereg(sc_if, phy, reg, val));
+@@ -533,11 +533,11 @@
+ 			break;
+ 		}
+ 
+-		/* Disable Rx flow control. */
+-		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0)
++		if ((IFM_OPTIONS(mii->mii_media_active) &
++		    IFM_ETH_RXPAUSE) == 0)
+ 			gmac |= GM_GPCR_FC_RX_DIS;
+-		/* Disable Tx flow control. */
+-		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0)
++		if ((IFM_OPTIONS(mii->mii_media_active) &
++		     IFM_ETH_TXPAUSE) == 0)
+ 			gmac |= GM_GPCR_FC_TX_DIS;
+ 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
+ 			gmac |= GM_GPCR_DUP_FULL;
+@@ -549,7 +549,8 @@
+ 		GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
+ 		gmac = GMC_PAUSE_OFF;
+ 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
+-			if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0)
++			if ((IFM_OPTIONS(mii->mii_media_active) &
++			    IFM_ETH_RXPAUSE) != 0)
+ 				gmac = GMC_PAUSE_ON;
+ 		}
+ 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
+@@ -565,7 +566,7 @@
  		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
  		/* Disable Rx/Tx MAC. */
  		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
@@ -92,7 +138,7 @@
  			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
  			/* Read again to ensure writing. */
-@@ -647,6 +653,54 @@
+@@ -647,6 +648,54 @@
  }
  
  static int
@@ -147,7 +193,7 @@
  msk_init_rx_ring(struct msk_if_softc *sc_if)
  {
  	struct msk_ring_data *rd;
-@@ -662,7 +716,21 @@
+@@ -662,7 +711,21 @@
  	rd = &sc_if->msk_rdata;
  	bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
  	prod = sc_if->msk_cdata.msk_rx_prod;
@@ -170,7 +216,7 @@
  		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
  		rxd->rx_m = NULL;
  		rxd->rx_le = &rd->msk_rx_ring[prod];
-@@ -680,7 +748,8 @@
+@@ -680,7 +743,8 @@
  	CSR_WRITE_2(sc_if->msk_softc,
  	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
  	    sc_if->msk_cdata.msk_rx_prod);
@@ -180,7 +226,7 @@
  	return (0);
  }
  
-@@ -701,7 +770,21 @@
+@@ -701,7 +765,21 @@
  	bzero(rd->msk_jumbo_rx_ring,
  	    sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
  	prod = sc_if->msk_cdata.msk_rx_prod;
@@ -203,7 +249,7 @@
  		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
  		rxd->rx_m = NULL;
  		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
-@@ -718,7 +801,8 @@
+@@ -718,7 +796,8 @@
  	CSR_WRITE_2(sc_if->msk_softc,
  	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
  	    sc_if->msk_cdata.msk_rx_prod);
@@ -213,7 +259,7 @@
  	return (0);
  }
  
-@@ -927,7 +1011,7 @@
+@@ -927,7 +1006,7 @@
  	struct msk_if_softc *sc_if;
  	struct ifreq *ifr;
  	struct mii_data	*mii;
@@ -222,7 +268,7 @@
  
  	sc_if = ifp->if_softc;
  	ifr = (struct ifreq *)data;
-@@ -939,7 +1023,7 @@
+@@ -939,7 +1018,7 @@
  		if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
  			error = EINVAL;
  		else if (ifp->if_mtu != ifr->ifr_mtu) {
@@ -231,7 +277,7 @@
  				if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
  					error = EINVAL;
  					MSK_IF_UNLOCK(sc_if);
-@@ -955,7 +1039,10 @@
+@@ -955,7 +1034,10 @@
  				}
  			}
  			ifp->if_mtu = ifr->ifr_mtu;
@@ -243,7 +289,7 @@
  		}
  		MSK_IF_UNLOCK(sc_if);
  		break;
-@@ -986,6 +1073,7 @@
+@@ -986,6 +1068,7 @@
  		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
  		break;
  	case SIOCSIFCAP:
@@ -251,7 +297,7 @@
  		MSK_IF_LOCK(sc_if);
  		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
  		if ((mask & IFCAP_TXCSUM) != 0 &&
-@@ -997,8 +1085,11 @@
+@@ -997,8 +1080,11 @@
  				ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
  		}
  		if ((mask & IFCAP_RXCSUM) != 0 &&
@@ -264,7 +310,7 @@
  		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
  		    (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0)
  			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
-@@ -1026,8 +1117,11 @@
+@@ -1026,8 +1112,11 @@
  			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
  			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
  		}
@@ -277,7 +323,16 @@
  		MSK_IF_UNLOCK(sc_if);
  		break;
  	default:
-@@ -1130,37 +1224,30 @@
+@@ -1076,7 +1165,7 @@
+ 	sc->msk_pflags |= MSK_FLAG_RAMBUF;
+ 	/*
+ 	 * Give receiver 2/3 of memory and round down to the multiple
+-	 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
++	 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
+ 	 * of 1024.
+ 	 */
+ 	sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
+@@ -1130,37 +1219,30 @@
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
@@ -331,7 +386,7 @@
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
-@@ -1169,10 +1256,10 @@
+@@ -1169,10 +1251,10 @@
  			val |= GLB_GPIO_STAT_RACE_DIS;
  			CSR_WRITE_4(sc, B2_GP_IO, val);
  			CSR_READ_4(sc, B2_GP_IO);
@@ -345,7 +400,7 @@
  		for (i = 0; i < sc->msk_num_port; i++) {
  			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
  			    GMLC_RST_SET);
-@@ -1218,28 +1305,33 @@
+@@ -1218,28 +1300,33 @@
  	bus_addr_t addr;
  	uint16_t status;
  	uint32_t val;
@@ -399,7 +454,7 @@
  
  	/* Clear all error bits in the PCI status register. */
  	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
-@@ -1280,17 +1372,22 @@
+@@ -1280,17 +1367,22 @@
  	/* Reset GPHY/GMAC Control */
  	for (i = 0; i < sc->msk_num_port; i++) {
  		/* GPHY Control reset. */
@@ -425,7 +480,7 @@
  	if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
  		/* Disable PCIe PHY powerdown(reg 0x80, bit7). */
  		CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
-@@ -1314,8 +1411,14 @@
+@@ -1314,8 +1406,14 @@
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  
@@ -441,7 +496,7 @@
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
-@@ -1490,23 +1593,14 @@
+@@ -1490,23 +1588,14 @@
  	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  	ifp->if_mtu = ETHERMTU;
  	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
@@ -470,16 +525,34 @@
  	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
  	    (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
  		ifp->if_capabilities |= IFCAP_RXCSUM;
-@@ -1549,7 +1643,7 @@
+@@ -1549,9 +1638,9 @@
  		 * this workaround does not work so disable checksum offload
  		 * for VLAN interface.
  		 */
 -        	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
 +		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
  		/*
- 		 * Enable Rx checksum offloading for VLAN taggedd frames
+-		 * Enable Rx checksum offloading for VLAN taggedd frames
++		 * Enable Rx checksum offloading for VLAN tagged frames
  		 * if controller support new descriptor format.
-@@ -1634,13 +1728,15 @@
+ 		 */
+ 		if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
+@@ -1571,10 +1660,11 @@
+ 	 * Do miibus setup.
+ 	 */
+ 	MSK_IF_UNLOCK(sc_if);
+-	error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange,
+-	    msk_mediastatus);
++	error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
++	    msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
++	    mmd->mii_flags);
+ 	if (error != 0) {
+-		device_printf(sc_if->msk_if_dev, "no PHY found!\n");
++		device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
+ 		ether_ifdetach(ifp);
+ 		error = ENXIO;
+ 		goto fail;
+@@ -1634,13 +1724,15 @@
  		}
  	}
  
@@ -496,7 +569,7 @@
  	    sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
  		device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
  		    sc->msk_hw_id, sc->msk_hw_rev);
-@@ -1674,9 +1770,6 @@
+@@ -1674,9 +1766,6 @@
  	resource_int_value(device_get_name(dev), device_get_unit(dev),
  	    "int_holdoff", &sc->msk_int_holdoff);
  
@@ -506,7 +579,16 @@
  	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
  	/* Check number of MACs. */
  	sc->msk_num_port = 1;
-@@ -1750,6 +1843,11 @@
+@@ -1738,7 +1827,7 @@
+ 			 * does not rely on status word of received frame
+ 			 * in msk_rxeof() which in turn disables all
+ 			 * hardware assistance bits reported by the status
+-			 * word as well as validity of the recevied frame.
++			 * word as well as validity of the received frame.
+ 			 * Just pass received frames to upper stack with
+ 			 * minimal test and let upper stack handle them.
+ 			 */
+@@ -1750,6 +1839,11 @@
  		sc->msk_clock = 156;	/* 156 MHz */
  		sc->msk_pflags |= MSK_FLAG_JUMBO;
  		break;
@@ -518,7 +600,20 @@
  	case CHIP_ID_YUKON_UL_2:
  		sc->msk_clock = 125;	/* 125 MHz */
  		sc->msk_pflags |= MSK_FLAG_JUMBO;
-@@ -1826,7 +1924,8 @@
+@@ -1815,8 +1909,11 @@
+ 	}
+ 	mmd->port = MSK_PORT_A;
+ 	mmd->pmd = sc->msk_pmd;
+-	 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P')
++	mmd->mii_flags |= MIIF_DOPAUSE | MIIF_FORCEPAUSE;
++	if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
+ 		mmd->mii_flags |= MIIF_HAVEFIBER;
++	if (sc->msk_pmd == 'P')
++		mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
+ 	device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
+ 
+ 	if (sc->msk_num_port > 1) {
+@@ -1826,7 +1923,8 @@
  			error = ENXIO;
  			goto fail;
  		}
@@ -528,15 +623,58 @@
  		if (mmd == NULL) {
  			device_printf(dev, "failed to allocate memory for "
  			    "ivars of PORT_B\n");
-@@ -2885,6 +2984,7 @@
+@@ -1835,8 +1933,10 @@
+ 		}
+ 		mmd->port = MSK_PORT_B;
+ 		mmd->pmd = sc->msk_pmd;
+-	 	if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P')
++		if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
+ 			mmd->mii_flags |= MIIF_HAVEFIBER;
++		if (sc->msk_pmd == 'P')
++			mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
+ 		device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
+ 	}
  
+@@ -2068,10 +2168,10 @@
+ 	 * what DMA address is used and chain another descriptor for the
+ 	 * 64bits DMA operation. This also means descriptor ring size is
+ 	 * variable. Limiting DMA address to be in 32bit address space greatly
+-	 * simplyfies descriptor handling and possibly would increase
++	 * simplifies descriptor handling and possibly would increase
+ 	 * performance a bit due to efficient handling of descriptors.
+ 	 * Apart from harassing checksum offloading mechanisms, it seems
+-	 * it's really bad idea to use a seperate descriptor for 64bit
++	 * it's really bad idea to use a separate descriptor for 64bit
+ 	 * DMA operation to save small descriptor memory. Anyway, I've
+ 	 * never seen these exotic scheme on ethernet interface hardware.
+ 	 */
+@@ -2568,7 +2668,7 @@
+ 			 * Short UDP packets appear to be handled correctly by
+ 			 * Yukon II. Also I assume this bug does not happen on
+ 			 * controllers that use newer descriptor format or
+-			 * automatic Tx checksum calaulcation.
++			 * automatic Tx checksum calculation.
+ 			 */
+ 			m = m_pullup(m, offset + sizeof(struct tcphdr));
+ 			if (m == NULL) {
+@@ -2705,7 +2805,7 @@
+ 	/* Update producer index. */
+ 	sc_if->msk_cdata.msk_tx_prod = prod;
+ 
+-	/* Set EOP on the last desciptor. */
++	/* Set EOP on the last descriptor. */
+ 	prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
+ 	tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
+ 	tx_le->msk_control |= htole32(EOP);
+@@ -2885,6 +2985,7 @@
+ 
  	MSK_LOCK(sc);
  
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
  	mskc_reset(sc);
  	for (i = 0; i < sc->msk_num_port; i++) {
  		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
-@@ -2918,6 +3018,96 @@
+@@ -2918,6 +3019,96 @@
  }
  #endif
  
@@ -633,7 +771,7 @@
  static void
  msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
      int len)
-@@ -2972,18 +3162,8 @@
+@@ -2972,18 +3163,8 @@
  			msk_fixup_rx(m);
  #endif
  		ifp->if_ipackets++;
@@ -654,7 +792,7 @@
  		/* Check for VLAN tagged packets. */
  		if ((status & GMR_FS_VLAN) != 0 &&
  		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
-@@ -3042,18 +3222,8 @@
+@@ -3042,18 +3223,8 @@
  			msk_fixup_rx(m);
  #endif
  		ifp->if_ipackets++;
@@ -675,7 +813,16 @@
  		/* Check for VLAN tagged packets. */
  		if ((status & GMR_FS_VLAN) != 0 &&
  		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
-@@ -3370,6 +3540,9 @@
+@@ -3176,7 +3347,7 @@
+ 		 * XXX
+ 		 * In case of Tx underrun, we may need to flush/reset
+ 		 * Tx MAC but that would also require resynchronization
+-		 * with status LEs. Reintializing status LEs would
++		 * with status LEs. Reinitializing status LEs would
+ 		 * affect other port in dual MAC configuration so it
+ 		 * should be avoided as possible as we can.
+ 		 * Due to lack of documentation it's all vague guess but
+@@ -3370,6 +3541,9 @@
  			break;
  		case OP_RXCHKSVLAN:
  			sc_if->msk_vtag = ntohs(len);
@@ -685,7 +832,7 @@
  			break;
  		case OP_RXSTAT:
  			if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING))
-@@ -3503,37 +3676,24 @@
+@@ -3503,37 +3677,24 @@
  
  	ifp = sc_if->msk_ifp;
  	sc = sc_if->msk_softc;
@@ -733,7 +880,7 @@
  	}
  }
  
-@@ -3582,11 +3742,12 @@
+@@ -3582,11 +3743,12 @@
  		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
  	}
  
@@ -751,7 +898,16 @@
  		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
  		    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
  		    GMC_BYP_RETR_ON);
-@@ -3694,13 +3855,13 @@
+@@ -3685,7 +3847,7 @@
+ 	msk_setvlan(sc_if, ifp);
+ 
+ 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
+-		/* Set Rx Pause threshould. */
++		/* Set Rx Pause threshold. */
+ 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
+ 		    MSK_ECU_LLPP);
+ 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
+@@ -3694,13 +3856,13 @@
  		msk_set_tx_stfwd(sc_if);
  	}
  
@@ -772,7 +928,7 @@
  
  	/*
  	 * Disable Force Sync bit and Alloc bit in Tx RAM interface
-@@ -3757,8 +3918,13 @@
+@@ -3757,8 +3919,13 @@
  	msk_init_tx_ring(sc_if);
  
  	/* Disable Rx checksum offload and RSS hash. */
@@ -788,7 +944,7 @@
  	if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
  		msk_set_prefetch(sc, sc_if->msk_rxq,
  		    sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
-@@ -3776,7 +3942,8 @@
+@@ -3776,7 +3943,8 @@
  		msk_stop(sc_if);
  		return;
  	}




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