[Glibc-bsd-commits] r5680 - trunk/kfreebsd-10/debian/patches
stevenc-guest at alioth.debian.org
stevenc-guest at alioth.debian.org
Mon Nov 3 22:06:55 UTC 2014
Author: stevenc-guest
Date: 2014-11-03 22:06:55 +0000 (Mon, 03 Nov 2014)
New Revision: 5680
Modified:
trunk/kfreebsd-10/debian/patches/ath9k-linux.diff
Log:
* Rename entry guards to FreeBSD style, based on filename
* Identify manufacturer of chipsets, with abbreviations
* Whitespace fixes
Modified: trunk/kfreebsd-10/debian/patches/ath9k-linux.diff
===================================================================
--- trunk/kfreebsd-10/debian/patches/ath9k-linux.diff 2014-11-03 21:58:50 UTC (rev 5679)
+++ trunk/kfreebsd-10/debian/patches/ath9k-linux.diff 2014-11-03 22:06:55 UTC (rev 5680)
@@ -1,10 +1,10 @@
From: Steven Chamberlain <steven at pyro.eu.org>
Date: Mon, 03 Nov 2014 21:57:57 +0000
-Subject: import part of Linux drivers/net/wireless/ath/ath9k/reg.h
+Subject: import Linux drivers/net/wireless/ath/ath9k/reg.h and modify
--- /dev/null
+++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_devid.h
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ *
@@ -21,67 +21,70 @@
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
-+#ifndef REG_H
-+#define REG_H
++#ifndef __AR9300_DEVID_H__
++#define __AR9300_DEVID_H__
+
-+#define AR_SREV_VERSION_5416_PCI 0xD
-+#define AR_SREV_VERSION_5416_PCIE 0xC
-+#define AR_SREV_REVISION_5416_10 0
-+#define AR_SREV_REVISION_5416_20 1
-+#define AR_SREV_REVISION_5416_22 2
-+#define AR_SREV_VERSION_9100 0x14
-+#define AR_SREV_VERSION_9160 0x40
-+#define AR_SREV_REVISION_9160_10 0
-+#define AR_SREV_REVISION_9160_11 1
-+#define AR_SREV_VERSION_9280 0x80
-+#define AR_SREV_REVISION_9280_10 0
-+#define AR_SREV_REVISION_9280_20 1
-+#define AR_SREV_REVISION_9280_21 2
-+#define AR_SREV_VERSION_9285 0xC0
-+#define AR_SREV_REVISION_9285_10 0
-+#define AR_SREV_REVISION_9285_11 1
-+#define AR_SREV_REVISION_9285_12 2
-+#define AR_SREV_VERSION_9287 0x180
-+#define AR_SREV_REVISION_9287_10 0
-+#define AR_SREV_REVISION_9287_11 1
-+#define AR_SREV_REVISION_9287_12 2
-+#define AR_SREV_REVISION_9287_13 3
-+#define AR_SREV_VERSION_9271 0x140
-+#define AR_SREV_REVISION_9271_10 0
-+#define AR_SREV_REVISION_9271_11 1
-+#define AR_SREV_VERSION_9300 0x1c0
-+#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
-+#define AR_SREV_REVISION_9300_22 3
-+#define AR_SREV_VERSION_9330 0x200
-+#define AR_SREV_REVISION_9330_10 0
-+#define AR_SREV_REVISION_9330_11 1
-+#define AR_SREV_REVISION_9330_12 2
-+#define AR_SREV_VERSION_9485 0x240
-+#define AR_SREV_REVISION_9485_10 0
-+#define AR_SREV_REVISION_9485_11 1
-+#define AR_SREV_VERSION_9340 0x300
-+#define AR_SREV_REVISION_9340_10 0
-+#define AR_SREV_REVISION_9340_11 1
-+#define AR_SREV_REVISION_9340_12 2
-+#define AR_SREV_REVISION_9340_13 3
-+#define AR_SREV_VERSION_9580 0x1C0
-+#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
-+#define AR_SREV_VERSION_9462 0x280
-+#define AR_SREV_REVISION_9462_20 2
-+#define AR_SREV_REVISION_9462_21 3
-+#define AR_SREV_VERSION_9565 0x2C0
-+#define AR_SREV_REVISION_9565_10 0
-+#define AR_SREV_REVISION_9565_101 1
-+#define AR_SREV_REVISION_9565_11 2
-+#define AR_SREV_VERSION_9550 0x400
-+#define AR_SREV_VERSION_9531 0x500
-+#define AR_SREV_REVISION_9531_10 0
-+#define AR_SREV_REVISION_9531_11 1
++/* Atheros chipsets */
++#define AR_SREV_VERSION_AR5416_PCI 0xD
++#define AR_SREV_VERSION_AR5416_PCIE 0xC
++#define AR_SREV_REVISION_AR5416_10 0
++#define AR_SREV_REVISION_AR5416_20 1
++#define AR_SREV_REVISION_AR5416_22 2
++#define AR_SREV_VERSION_AR9100 0x14
++#define AR_SREV_VERSION_AR9160 0x40
++#define AR_SREV_REVISION_AR9160_10 0
++#define AR_SREV_REVISION_AR9160_11 1
++#define AR_SREV_VERSION_AR9280 0x80
++#define AR_SREV_REVISION_AR9280_10 0
++#define AR_SREV_REVISION_AR9280_20 1
++#define AR_SREV_REVISION_AR9280_21 2
++#define AR_SREV_VERSION_AR9285 0xC0
++#define AR_SREV_REVISION_AR9285_10 0
++#define AR_SREV_REVISION_AR9285_11 1
++#define AR_SREV_REVISION_AR9285_12 2
++#define AR_SREV_VERSION_AR9287 0x180
++#define AR_SREV_REVISION_AR9287_10 0
++#define AR_SREV_REVISION_AR9287_11 1
++#define AR_SREV_REVISION_AR9287_12 2
++#define AR_SREV_REVISION_AR9287_13 3
++#define AR_SREV_VERSION_AR9271 0x140
++#define AR_SREV_REVISION_AR9271_10 0
++#define AR_SREV_REVISION_AR9271_11 1
++#define AR_SREV_VERSION_AR9300 0x1c0
++#define AR_SREV_REVISION_AR9300_20 2 /* 2.0 and 2.1 */
++#define AR_SREV_REVISION_AR9300_22 3
++#define AR_SREV_VERSION_AR9330 0x200
++#define AR_SREV_REVISION_AR9330_10 0
++#define AR_SREV_REVISION_AR9330_11 1
++#define AR_SREV_REVISION_AR9330_12 2
++#define AR_SREV_VERSION_AR9485 0x240
++#define AR_SREV_REVISION_AR9485_10 0
++#define AR_SREV_REVISION_AR9485_11 1
++#define AR_SREV_VERSION_AR9340 0x300
++#define AR_SREV_REVISION_AR9340_10 0
++#define AR_SREV_REVISION_AR9340_11 1
++#define AR_SREV_REVISION_AR9340_12 2
++#define AR_SREV_REVISION_AR9340_13 3
++#define AR_SREV_VERSION_AR9580 0x1C0
++#define AR_SREV_REVISION_AR9580_10 4 /* AR9580 1.0 */
++#define AR_SREV_VERSION_AR9462 0x280
++#define AR_SREV_REVISION_AR9462_20 2
++#define AR_SREV_REVISION_AR9462_21 3
+
++/* Qualcomm Atheros chipsets */
++#define AR_SREV_VERSION_AR9565 0x2C0
++#define AR_SREV_REVISION_AR9565_10 0
++#define AR_SREV_REVISION_AR9565_101 1
++#define AR_SREV_REVISION_AR9565_11 2
++#define AR_SREV_VERSION_AR9550 0x400
++#define AR_SREV_VERSION_AR9531 0x500
++#define AR_SREV_REVISION_AR9531_10 0
++#define AR_SREV_REVISION_AR9531_11 1
++
+#endif
--- /dev/null
+++ b/sys/dev/ath/ath_hal/ar9003/ar9300_devid.h
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ *
@@ -98,61 +101,64 @@
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
-+#ifndef REG_H
-+#define REG_H
++#ifndef __AR9300_DEVID_H__
++#define __AR9300_DEVID_H__
+
-+#define AR_SREV_VERSION_5416_PCI 0xD
-+#define AR_SREV_VERSION_5416_PCIE 0xC
-+#define AR_SREV_REVISION_5416_10 0
-+#define AR_SREV_REVISION_5416_20 1
-+#define AR_SREV_REVISION_5416_22 2
-+#define AR_SREV_VERSION_9100 0x14
-+#define AR_SREV_VERSION_9160 0x40
-+#define AR_SREV_REVISION_9160_10 0
-+#define AR_SREV_REVISION_9160_11 1
-+#define AR_SREV_VERSION_9280 0x80
-+#define AR_SREV_REVISION_9280_10 0
-+#define AR_SREV_REVISION_9280_20 1
-+#define AR_SREV_REVISION_9280_21 2
-+#define AR_SREV_VERSION_9285 0xC0
-+#define AR_SREV_REVISION_9285_10 0
-+#define AR_SREV_REVISION_9285_11 1
-+#define AR_SREV_REVISION_9285_12 2
-+#define AR_SREV_VERSION_9287 0x180
-+#define AR_SREV_REVISION_9287_10 0
-+#define AR_SREV_REVISION_9287_11 1
-+#define AR_SREV_REVISION_9287_12 2
-+#define AR_SREV_REVISION_9287_13 3
-+#define AR_SREV_VERSION_9271 0x140
-+#define AR_SREV_REVISION_9271_10 0
-+#define AR_SREV_REVISION_9271_11 1
-+#define AR_SREV_VERSION_9300 0x1c0
-+#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
-+#define AR_SREV_REVISION_9300_22 3
-+#define AR_SREV_VERSION_9330 0x200
-+#define AR_SREV_REVISION_9330_10 0
-+#define AR_SREV_REVISION_9330_11 1
-+#define AR_SREV_REVISION_9330_12 2
-+#define AR_SREV_VERSION_9485 0x240
-+#define AR_SREV_REVISION_9485_10 0
-+#define AR_SREV_REVISION_9485_11 1
-+#define AR_SREV_VERSION_9340 0x300
-+#define AR_SREV_REVISION_9340_10 0
-+#define AR_SREV_REVISION_9340_11 1
-+#define AR_SREV_REVISION_9340_12 2
-+#define AR_SREV_REVISION_9340_13 3
-+#define AR_SREV_VERSION_9580 0x1C0
-+#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
-+#define AR_SREV_VERSION_9462 0x280
-+#define AR_SREV_REVISION_9462_20 2
-+#define AR_SREV_REVISION_9462_21 3
-+#define AR_SREV_VERSION_9565 0x2C0
-+#define AR_SREV_REVISION_9565_10 0
-+#define AR_SREV_REVISION_9565_101 1
-+#define AR_SREV_REVISION_9565_11 2
-+#define AR_SREV_VERSION_9550 0x400
-+#define AR_SREV_VERSION_9531 0x500
-+#define AR_SREV_REVISION_9531_10 0
-+#define AR_SREV_REVISION_9531_11 1
++/* Atheros chipsets */
++#define AR_SREV_VERSION_AR5416_PCI 0xD
++#define AR_SREV_VERSION_AR5416_PCIE 0xC
++#define AR_SREV_REVISION_AR5416_10 0
++#define AR_SREV_REVISION_AR5416_20 1
++#define AR_SREV_REVISION_AR5416_22 2
++#define AR_SREV_VERSION_AR9100 0x14
++#define AR_SREV_VERSION_AR9160 0x40
++#define AR_SREV_REVISION_AR9160_10 0
++#define AR_SREV_REVISION_AR9160_11 1
++#define AR_SREV_VERSION_AR9280 0x80
++#define AR_SREV_REVISION_AR9280_10 0
++#define AR_SREV_REVISION_AR9280_20 1
++#define AR_SREV_REVISION_AR9280_21 2
++#define AR_SREV_VERSION_AR9285 0xC0
++#define AR_SREV_REVISION_AR9285_10 0
++#define AR_SREV_REVISION_AR9285_11 1
++#define AR_SREV_REVISION_AR9285_12 2
++#define AR_SREV_VERSION_AR9287 0x180
++#define AR_SREV_REVISION_AR9287_10 0
++#define AR_SREV_REVISION_AR9287_11 1
++#define AR_SREV_REVISION_AR9287_12 2
++#define AR_SREV_REVISION_AR9287_13 3
++#define AR_SREV_VERSION_AR9271 0x140
++#define AR_SREV_REVISION_AR9271_10 0
++#define AR_SREV_REVISION_AR9271_11 1
++#define AR_SREV_VERSION_AR9300 0x1c0
++#define AR_SREV_REVISION_AR9300_20 2 /* 2.0 and 2.1 */
++#define AR_SREV_REVISION_AR9300_22 3
++#define AR_SREV_VERSION_AR9330 0x200
++#define AR_SREV_REVISION_AR9330_10 0
++#define AR_SREV_REVISION_AR9330_11 1
++#define AR_SREV_REVISION_AR9330_12 2
++#define AR_SREV_VERSION_AR9485 0x240
++#define AR_SREV_REVISION_AR9485_10 0
++#define AR_SREV_REVISION_AR9485_11 1
++#define AR_SREV_VERSION_AR9340 0x300
++#define AR_SREV_REVISION_AR9340_10 0
++#define AR_SREV_REVISION_AR9340_11 1
++#define AR_SREV_REVISION_AR9340_12 2
++#define AR_SREV_REVISION_AR9340_13 3
++#define AR_SREV_VERSION_AR9580 0x1C0
++#define AR_SREV_REVISION_AR9580_10 4 /* AR9580 1.0 */
++#define AR_SREV_VERSION_AR9462 0x280
++#define AR_SREV_REVISION_AR9462_20 2
++#define AR_SREV_REVISION_AR9462_21 3
+
++/* Qualcomm Atheros chipsets */
++#define AR_SREV_VERSION_AR9565 0x2C0
++#define AR_SREV_REVISION_AR9565_10 0
++#define AR_SREV_REVISION_AR9565_101 1
++#define AR_SREV_REVISION_AR9565_11 2
++#define AR_SREV_VERSION_AR9550 0x400
++#define AR_SREV_VERSION_AR9531 0x500
++#define AR_SREV_REVISION_AR9531_10 0
++#define AR_SREV_REVISION_AR9531_11 1
++
+#endif
More information about the Glibc-bsd-commits
mailing list