[Gnuk-users] Answer to Will you support gnuk on STM32F4Discovery?

Kaz Kojima kkojima at rr.iij4u.or.jp
Tue Nov 8 13:00:33 UTC 2016


Hi Bastien,

>> IIRC, Kaz Kojima did some work for porting Chopstx to a chip with
>> Cortex-M4 and another chip of Cortex-A9.  For the latter (multi
>> cores), we once tried to merge, but the merge had not finished.  Only
>> some parts were merged.  Meanwhile Chopstx introduced new API.  We
>> need to resume porting work again (for multiple cores, or more portable
>> Chopstx).
> 
> Do you have some pointer ?

FYI, I've attached an old patch and some related files for my trial
which was on NUCLEO-64 STM32F446 with chopstx.  Hope that it helps,
though it's for the ancient chopstx and not completed.

Regards,
	kaz
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/* Simple STM32F446 definitions.  Not complete. */

/* Cotex-M4 system controll block definition. */

struct SCB
{
  volatile uint32_t CPUID;
  volatile uint32_t ICSR;
  volatile uint32_t VTOR;
  volatile uint32_t AIRCR;
  volatile uint32_t SCR;
  volatile uint32_t CCR;
  volatile uint8_t  SHP[12];
  volatile uint32_t SHCSR;
  volatile uint32_t CFSR;
  volatile uint32_t HFSR;
  volatile uint32_t DFSR;
  volatile uint32_t MMFAR;
  volatile uint32_t BFAR;
  volatile uint32_t AFSR;
  volatile uint32_t PFR[2];
  volatile uint32_t DFR;
  volatile uint32_t ADR;
  volatile uint32_t MMFR[4];
  volatile uint32_t ISAR[5];
  uint32_t dummy0[5];
  volatile uint32_t CPACR;
};

#define SCS_BASE	(0xE000E000)
#define SCB_BASE	(SCS_BASE +  0x0D00)
static struct SCB *const SCB = ((struct SCB *const) SCB_BASE);

struct FPU
{
  uint32_t dummy0[1];
  volatile uint32_t FPCCR;
  volatile uint32_t FPCAR;
  volatile uint32_t FPDSCR;
  volatile uint32_t MVFR0;
  volatile uint32_t MVFR1;
};

#define FPU_BASE	(SCS_BASE + 0x0F30)
static struct FPU *const FPU = ((struct FPU *const) FPU_BASE);

/* Some STM32F446 peripheral definitions.  */

#define PERIPH_BASE		0x40000000
#define APB1PERIPH_BASE  	PERIPH_BASE
#define APB2PERIPH_BASE		(PERIPH_BASE + 0x10000)
#define AHB1PERIPH_BASE		(PERIPH_BASE + 0x20000)
#define AHB2PERIPH_BASE		(PERIPH_BASE + 0x10000000)

/* RCC */
struct RCC {
  volatile uint32_t CR;
  volatile uint32_t PLLCFGR;
  volatile uint32_t CFGR;
  volatile uint32_t CIR;
  volatile uint32_t AHB1RSTR;
  volatile uint32_t AHB2RSTR;
  volatile uint32_t AHB3RSTR;
  uint32_t dummy0[1];
  volatile uint32_t APB1RSTR;
  volatile uint32_t APB2RSTR;
  uint32_t dummy1[2];
  volatile uint32_t AHB1ENR;
  volatile uint32_t AHB2ENR;
  volatile uint32_t AHB3ENR;
  uint32_t dummy2[1];
  volatile uint32_t APB1ENR;
  volatile uint32_t APB2ENR;
  uint32_t dummy3[2];
  volatile uint32_t AHB1LPENR;
  volatile uint32_t AHB2LPENR;
  volatile uint32_t AHB3LPENR;
  uint32_t dummy4[1];
  volatile uint32_t APB1LPENR;
  volatile uint32_t APB2LPENR;
  uint32_t dummy5[2];
  volatile uint32_t BDCR;
  volatile uint32_t CSR;
  uint32_t dummy6[2];
  volatile uint32_t SSCGR;
  volatile uint32_t PLLI2SCFGR;
  volatile uint32_t PLLSAICFGR;
  volatile uint32_t DCKCFGR;
  volatile uint32_t CKGATENR;
  volatile uint32_t DCKCFGR2;
};

#define RCC_CR_HSION		0x00000001
#define RCC_CR_HSIRDY		0x00000002
#define RCC_CR_HSITRIM		0x000000F8
#define RCC_CR_HSEON		0x00010000
#define RCC_CR_HSERDY		0x00020000
#define RCC_CR_HSEBYP		0x00040000
#define RCC_CR_CSSON		0x00080000
#define RCC_CR_PLLON		0x01000000
#define RCC_CR_PLLRDY		0x02000000
#define RCC_CR_PLLI2SON		0x04000000
#define RCC_CR_PLLI2SRDY	0x08000000
#define RCC_CR_PLLSAION		0x10000000
#define RCC_CR_PLLSAIRDY	0x20000000

#define RCC_PLLCFGR_PLLM	0x0000003F
#define RCC_PLLCFGR_PLLN	0x00007FC0
#define RCC_PLLCFGR_PLLP	0x00030000
#define RCC_PLLCFGR_PLLSRC	0x00400000
#define RCC_PLLCFGR_PLLSRC_HSE	0x00400000
#define RCC_PLLCFGR_PLLQ	0x0F000000
#define RCC_PLLCFGR_PLLR	0x70000000

#define RCC_CFGR_SW		0x00000003
#define RCC_CFGR_SW_PLL		0x00000002
#define RCC_CFGR_SWS		0x0000000C
#define RCC_CFGR_SWS_HSI	0x00000000
#define RCC_CFGR_HPRE		0x000000F0
#define RCC_CFGR_PPRE1		0x00001C00
#define RCC_CFGR_PPRE1_DIV4	0x00001400
#define RCC_CFGR_PPRE2		0x0000E000
#define RCC_CFGR_PPRE2_DIV2	0x00008000
#define RCC_CFGR_RTCPRE		0x001F0000
#define RCC_CFGR_MCO1		0x00600000
#define RCC_CFGR_I2SSRC		0x00800000
#define RCC_CFGR_MCO1PRE	0x07000000
#define RCC_CFGR_MCO2PRE	0x38000000
#define RCC_CFGR_MCO2		0xC0000000

#define RCC_AHB1RSTR_GPIOARST	0x00000001
#define RCC_AHB1RSTR_GPIOBRST	0x00000002
#define RCC_AHB1RSTR_GPIOCRST	0x00000004
#define RCC_AHB1RSTR_GPIODRST	0x00000008
#define RCC_AHB1RSTR_GPIOERST	0x00000010
#define RCC_AHB1RSTR_GPIOFRST	0x00000020
#define RCC_AHB1RSTR_GPIOGRST	0x00000040
#define RCC_AHB1RSTR_GPIOHRST	0x00000080
#define RCC_AHB1RSTR_CRCRST	0x00001000
#define RCC_AHB1RSTR_DMA1RST	0x00200000
#define RCC_AHB1RSTR_DMA2RST	0x00400000
#define RCC_AHB1RSTR_OTGHRST	0x20000000

#define RCC_APB1RSTR_TIM2RST	0x00000001
#define RCC_APB1RSTR_TIM3RST	0x00000002
#define RCC_APB1RSTR_TIM4RST	0x00000004
#define RCC_APB1RSTR_TIM5RST	0x00000008
#define RCC_APB1RSTR_TIM6RST	0x00000010
#define RCC_APB1RSTR_TIM7RST	0x00000020
#define RCC_APB1RSTR_TIM12RST	0x00000040
#define RCC_APB1RSTR_TIM13RST	0x00000080
#define RCC_APB1RSTR_TIM14RST	0x00000100
#define RCC_APB1RSTR_WWDGRST	0x00000800
#define RCC_APB1RSTR_SPI2RST	0x00004000
#define RCC_APB1RSTR_SPI3RST	0x00008000
#define RCC_APB1RSTR_SPDIFRXRST	0x00010000
#define RCC_APB1RSTR_USART2RST	0x00020000
#define RCC_APB1RSTR_USART3RST	0x00040000
#define RCC_APB1RSTR_UART4RST	0x00080000
#define RCC_APB1RSTR_UART5RST	0x00100000
#define RCC_APB1RSTR_I2C1RST	0x00200000
#define RCC_APB1RSTR_I2C2RST	0x00400000
#define RCC_APB1RSTR_I2C3RST	0x00800000
#define RCC_APB1RSTR_FMPI2C1RST	0x01000000
#define RCC_APB1RSTR_CAN1RST	0x02000000
#define RCC_APB1RSTR_CAN2RST	0x04000000
#define RCC_APB1RSTR_CECRST	0x08000000
#define RCC_APB1RSTR_PWRRST	0x10000000
#define RCC_APB1RSTR_DACRST	0x20000000

#define RCC_APB2RSTR_TIM1RST	0x00000001
#define RCC_APB2RSTR_TIM8RST	0x00000002
#define RCC_APB2RSTR_USART1RST	0x00000010
#define RCC_APB2RSTR_USART6RST	0x00000020
#define RCC_APB2RSTR_ADCRST	0x00000100
#define RCC_APB2RSTR_SDIORST	0x00000800
#define RCC_APB2RSTR_SPI1RST	0x00001000
#define RCC_APB2RSTR_SPI4RST	0x00002000
#define RCC_APB2RSTR_SYSCFGRST	0x00004000
#define RCC_APB2RSTR_TIM9RST	0x00010000
#define RCC_APB2RSTR_TIM10RST	0x00020000
#define RCC_APB2RSTR_TIM11RST	0x00040000
#define RCC_APB2RSTR_SAI1RST	0x00400000
#define RCC_APB2RSTR_SAI2RST	0x00800000
#define RCC_AHB1ENR_GPIOAEN	0x00000001
#define RCC_AHB1ENR_GPIOBEN	0x00000002
#define RCC_AHB1ENR_GPIOCEN	0x00000004
#define RCC_AHB1ENR_GPIODEN	0x00000008
#define RCC_AHB1ENR_GPIOEEN	0x00000010
#define RCC_AHB1ENR_GPIOFEN	0x00000020
#define RCC_AHB1ENR_GPIOGEN	0x00000040
#define RCC_AHB1ENR_GPIOHEN	0x00000080

#define RCC_AHB1ENR_CRCEN	0x00001000
#define RCC_AHB1ENR_BKPSRAMEN	0x00040000
#define RCC_AHB1ENR_DMA1EN	0x00200000
#define RCC_AHB1ENR_DMA2EN	0x00400000

#define RCC_AHB1ENR_OTGHSEN	0x20000000
#define RCC_AHB1ENR_OTGHSULPIEN	0x40000000
#define RCC_APB1ENR_TIM2EN	0x00000001
#define RCC_APB1ENR_TIM3EN	0x00000002
#define RCC_APB1ENR_TIM4EN	0x00000004
#define RCC_APB1ENR_TIM5EN	0x00000008
#define RCC_APB1ENR_TIM6EN	0x00000010
#define RCC_APB1ENR_TIM7EN	0x00000020
#define RCC_APB1ENR_TIM12EN	0x00000040
#define RCC_APB1ENR_TIM13EN	0x00000080
#define RCC_APB1ENR_TIM14EN	0x00000100
#define RCC_APB1ENR_WWDGEN	0x00000800
#define RCC_APB1ENR_SPI2EN	0x00004000
#define RCC_APB1ENR_SPI3EN	0x00008000
#define RCC_APB1ENR_SPDIFRXEN	0x00010000
#define RCC_APB1ENR_USART2EN	0x00020000
#define RCC_APB1ENR_USART3EN	0x00040000
#define RCC_APB1ENR_UART4EN	0x00080000
#define RCC_APB1ENR_UART5EN	0x00100000
#define RCC_APB1ENR_I2C1EN	0x00200000
#define RCC_APB1ENR_I2C2EN	0x00400000
#define RCC_APB1ENR_I2C3EN	0x00800000
#define RCC_APB1ENR_FMPI2C1EN	0x01000000
#define RCC_APB1ENR_CAN1EN	0x02000000
#define RCC_APB1ENR_CAN2EN	0x04000000
#define RCC_APB1ENR_CECEN	0x08000000
#define RCC_APB1ENR_PWREN	0x10000000
#define RCC_APB1ENR_DACEN	0x20000000

#define RCC_APB2ENR_TIM1EN	0x00000001
#define RCC_APB2ENR_TIM8EN	0x00000002
#define RCC_APB2ENR_USART1EN	0x00000010
#define RCC_APB2ENR_USART6EN	0x00000020
#define RCC_APB2ENR_ADC1EN	0x00000100
#define RCC_APB2ENR_ADC2EN	0x00000200
#define RCC_APB2ENR_ADC3EN	0x00000400
#define RCC_APB2ENR_SDIOEN	0x00000800
#define RCC_APB2ENR_SPI1EN	0x00001000
#define RCC_APB2ENR_SPI4EN	0x00002000
#define RCC_APB2ENR_SYSCFGEN	0x00004000
#define RCC_APB2ENR_TIM9EN	0x00010000
#define RCC_APB2ENR_TIM10EN	0x00020000
#define RCC_APB2ENR_TIM11EN	0x00040000
#define RCC_APB2ENR_SAI1EN	0x00400000
#define RCC_APB2ENR_SAI2EN	0x00800000

/* SYSCFG */
struct SYSCFG {
  volatile uint32_t MEMRMP;
  volatile uint32_t PMC;
  volatile uint32_t EXTICR[4];
  uint32_t dummy0[2];
  volatile uint32_t CMPCR;
  uint32_t dummy1[2];
  volatile uint32_t CFGR;
};

#define SYSCFG_MEMRMP_MEM_MODE 0x07

/* FLASH */
struct FLASH {
  volatile uint32_t ACR;
  volatile uint32_t KEYR;
  volatile uint32_t OPTKEYR;
  volatile uint32_t SR;
  volatile uint32_t CR;
  volatile uint32_t AR;
  volatile uint32_t RESERVED;
  volatile uint32_t OBR;
  volatile uint32_t WRPR;
};

#define FLASH_ACR_LATENCY_5WS	0x00000005
#define FLASH_ACR_PRFTEN	0x00000100
#define FLASH_ACR_ICEN		0x00000200
#define FLASH_ACR_DCEN		0x00000400

/* GPIO */
struct GPIO {
  volatile uint32_t MODER;
  volatile uint32_t OTYPER;
  volatile uint32_t OSPEEDR;
  volatile uint32_t PUPDR;
  volatile uint32_t IDR;
  volatile uint32_t ODR;
  volatile uint32_t BSRR;
  volatile uint32_t LCKR;
  volatile uint32_t AFR[2];
};

/* Timer */
struct TIM
{
  volatile uint32_t CR1;
  volatile uint32_t CR2;
  volatile uint32_t SMCR;
  volatile uint32_t DIER;
  volatile uint32_t SR;
  volatile uint32_t EGR;
  volatile uint32_t CCMR1;
  volatile uint32_t CCMR2;
  volatile uint32_t CCER;
  volatile uint32_t CNT;
  volatile uint32_t PSC;
  volatile uint32_t ARR;
  volatile uint32_t RCR;
  volatile uint32_t CCR1;
  volatile uint32_t CCR2;
  volatile uint32_t CCR3;
  volatile uint32_t CCR4;
  volatile uint32_t BDTR;
  volatile uint32_t DCR;
  volatile uint32_t DMAR;
  volatile uint32_t OR;
};

/* USART */
struct USART
{
  volatile uint32_t SR;
  volatile uint32_t DR;
  volatile uint32_t BRR;
  volatile uint32_t CR1;
  volatile uint32_t CR2;
  volatile uint32_t CR3;
  volatile uint32_t GTPR;
};

/* bxCAN */
struct TXMB
{
  volatile uint32_t TIR;
  volatile uint32_t TDTR;
  volatile uint32_t TDLR;
  volatile uint32_t TDHR;
};

struct RXMB
{
  volatile uint32_t RIR;
  volatile uint32_t RDTR;
  volatile uint32_t RDLR;
  volatile uint32_t RDHR;
};

struct FILT
{
  volatile uint32_t FR1;
  volatile uint32_t FR2;
};

struct CAN
{
  volatile uint32_t MCR;
  volatile uint32_t MSR;
  volatile uint32_t TSR;
  volatile uint32_t RF0R;
  volatile uint32_t RF1R;
  volatile uint32_t IER;
  volatile uint32_t ESR;
  volatile uint32_t BTR;
  uint32_t dummy0[88];
  struct TXMB TXMB[3];
  struct RXMB RXMB[2];
  uint32_t dummy1[12];
  volatile uint32_t FMR;
  volatile uint32_t FM1R;
  uint32_t dummy2;
  volatile uint32_t FS1R;
  uint32_t dummy3;
  volatile uint32_t FFA1R;
  uint32_t dummy4;
  volatile uint32_t FA1R;
  uint32_t dummy5[8];
  struct FILT BANK[28];
};

/* SPI/I2S */
struct SPI
{
  volatile uint32_t CR1;
  volatile uint32_t CR2;
  volatile uint32_t SR;
  volatile uint32_t DR;
  volatile uint32_t CRCPR;
  volatile uint32_t RXCRCR;
  volatile uint32_t TXCRCR;
  volatile uint32_t I2SCFGR;
  volatile uint32_t I2SPR;
};

/* I2C */

struct I2C
{
  volatile uint32_t CR1;
  volatile uint32_t CR2;
  volatile uint32_t OAR1;
  volatile uint32_t OAR2;
  volatile uint32_t DR;
  volatile uint32_t SR1;
  volatile uint32_t SR2;
  volatile uint32_t CCR;
  volatile uint32_t TRISE;
  volatile uint32_t FLTR;
};

/* ADC */

struct ADC
{
  volatile uint32_t SR;
  volatile uint32_t CR1;
  volatile uint32_t CR2;
  volatile uint32_t SMPR1;
  volatile uint32_t SMPR2;
  volatile uint32_t JOFR1;
  volatile uint32_t JOFR2;
  volatile uint32_t JOFR3;
  volatile uint32_t JOFR4;
  volatile uint32_t HTR;
  volatile uint32_t LTR;
  volatile uint32_t SQR1;
  volatile uint32_t SQR2;
  volatile uint32_t SQR3;
  volatile uint32_t JSQR;
  volatile uint32_t JDR1;
  volatile uint32_t JDR2;
  volatile uint32_t JDR3;
  volatile uint32_t JDR4;
  volatile uint32_t DR;
};

/* common ADC registers */

struct ADCC
{
  volatile uint32_t CSR;
  volatile uint32_t CCR;
  volatile uint32_t CDR;
};

/* DMA */

struct DMA
{
  volatile uint32_t LISR;
  volatile uint32_t HISR;
  volatile uint32_t LIFCR;
  volatile uint32_t HIFCR;
};

#define DMA_TCIF3		(1 << 27)
#define DMA_HTIF3		(1 << 26)
#define DMA_TEIF3		(1 << 25)
#define DMA_DMEIF3		(1 << 24)
#define DMA_FEIF3		(1 << 22)
#define DMA_TCIF2		(1 << 21)
#define DMA_HTIF2		(1 << 20)
#define DMA_TEIF2		(1 << 19)
#define DMA_DMEIF2		(1 << 18)
#define DMA_FEIF2		(1 << 16)
#define DMA_TCIF1		(1 << 11)
#define DMA_HTIF1		(1 << 10)
#define DMA_TEIF1		(1 << 9)
#define DMA_DMEIF1		(1 << 8)
#define DMA_FEIF1		(1 << 6)
#define DMA_TCIF0		(1 << 5)
#define DMA_HTIF0		(1 << 4)
#define DMA_TEIF0		(1 << 3)
#define DMA_DMEIF0		(1 << 2)
#define DMA_FEIF0		(1 << 0)

#define DMA_TCIF7		(1 << 27)
#define DMA_HTIF7		(1 << 26)
#define DMA_TEIF7		(1 << 25)
#define DMA_DMEIF7		(1 << 24)
#define DMA_FEIF7		(1 << 22)
#define DMA_TCIF6		(1 << 21)
#define DMA_HTIF6		(1 << 20)
#define DMA_TEIF6		(1 << 19)
#define DMA_DMEIF6		(1 << 18)
#define DMA_FEIF6		(1 << 16)
#define DMA_TCIF5		(1 << 11)
#define DMA_HTIF5		(1 << 10)
#define DMA_TEIF5		(1 << 9)
#define DMA_DMEIF5		(1 << 8)
#define DMA_FEIF5		(1 << 6)
#define DMA_TCIF4		(1 << 5)
#define DMA_HTIF4		(1 << 4)
#define DMA_TEIF4		(1 << 3)
#define DMA_DMEIF4		(1 << 2)
#define DMA_FEIF4		(1 << 0)

/* DMA stream */
struct DMA_Stream
{
  volatile uint32_t CR;
  volatile uint32_t NDTR;
  volatile uint32_t PAR;
  volatile uint32_t M0AR;
  volatile uint32_t M1AR;
  volatile uint32_t FCR;
};

#define DMA_SxCR_CHSEL_shift	25
#define DMA_SxCR_MBURST_shift	23
#define DMA_SxCR_PBURST_shift	21
#define DMA_SxCR_BURST_SINGLE	0
#define DMA_SxCR_BURST_INCR4	1
#define DMA_SxCR_BURST_INCR8	2
#define DMA_SxCR_BURST_INCR16	3
#define DMA_SxCR_CT		(1 << 19)
#define DMA_SxCR_DBM		(1 << 18)
#define DMA_SxCR_PL_shift	16
#define DMA_SxCR_PL_LOW		0
#define DMA_SxCR_PL_MEDIUM	1
#define DMA_SxCR_PL_HIGH	2
#define DMA_SxCR_PL_VHIGH	3
#define DMA_SxCR_PINCOS		(1 << 15)
#define DMA_SxCR_MSIZE_shift	13
#define DMA_SxCR_PSIZE_shift	11
#define DMA_SxCR_SIZE_BYTE	0
#define DMA_SxCR_SIZE_HALF	1
#define DMA_SxCR_SIZE_WORD	2
#define DMA_SxCR_MINC		(1 << 10)
#define DMA_SxCR_PINC		(1 << 9)
#define DMA_SxCR_CIRC		(1 << 8)
#define DMA_SxCR_DIR_shift	6
#define DMA_SxCR_DIR_P2M	0
#define DMA_SxCR_DIR_M2P	1
#define DMA_SxCR_DIR_M2M	2
#define DMA_SxCR_PFCTRL		(1 << 5)
#define DMA_SxCR_TCIE		(1 << 4)
#define DMA_SxCR_HTIE		(1 << 3)
#define DMA_SxCR_TEIE		(1 << 2)
#define DMA_SxCR_DMEIE		(1 << 1)
#define DMA_SxCR_EN		(1 << 0)

#define DMA_SxFCR_FEIE		(1 << 7)
#define DMA_SxFCR_FS_shift	3
#define DMA_SxFCR_FS_1BY4	0
#define DMA_SxFCR_FS_1BY2	1
#define DMA_SxFCR_FS_3BY4	2
#define DMA_SxFCR_FS_ALMOST	3
#define DMA_SxFCR_FS_ENMPT	4
#define DMA_SxFCR_FS_FULL	5
#define DMA_SxFCR_DMDIS		(1 << 2)
#define DMA_SxFCR_FTH_shift	0
#define DMA_SxFCR_FTH_1BY4	0
#define DMA_SxFCR_FTH_1BY2	1
#define DMA_SxFCR_FTH_3BY4	2
#define DMA_SxFCR_FTH_FULL	3

/* Physical addresses */
#define RCC_BASE		(AHB1PERIPH_BASE + 0x3800)
#define SYSCFG_BASE		(APB2PERIPH_BASE + 0x3800)
#define FLASH_R_BASE		(AHB1PERIPH_BASE + 0x3C00)
#define GPIOA_BASE		(AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE		(AHB1PERIPH_BASE + 0x0400)
#define GPIOC_BASE		(AHB1PERIPH_BASE + 0x0800)
#define GPIOD_BASE		(AHB1PERIPH_BASE + 0x0C00)
#define TIM2_BASE		(APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE		(APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE		(APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE		(APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE		(APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE		(APB1PERIPH_BASE + 0x1400)
#define USART1_BASE		(APB2PERIPH_BASE + 0x1000)
#define USART2_BASE		(APB1PERIPH_BASE + 0x4400)
#define USART3_BASE		(APB1PERIPH_BASE + 0x4800)
#define UART4_BASE		(APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE		(APB1PERIPH_BASE + 0x5000)
#define USART6_BASE		(APB2PERIPH_BASE + 0x1400)
#define CAN1_BASE		(APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE		(APB1PERIPH_BASE + 0x6800)
#define SPI1_BASE		(APB2PERIPH_BASE + 0x3000)
#define SPI2_BASE		(APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE		(APB1PERIPH_BASE + 0x3C00)
#define I2C1_BASE		(APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE		(APB1PERIPH_BASE + 0x5800)
#define I2C3_BASE		(APB1PERIPH_BASE + 0x5C00)
#define ADC1_BASE		(APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE		(APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE		(APB2PERIPH_BASE + 0x2200)
#define ADCC_BASE		(APB2PERIPH_BASE + 0x2300)
#define DMA1_BASE		(AHB1PERIPH_BASE + 0x6000)
#define DMA2_BASE		(AHB1PERIPH_BASE + 0x6400)

static struct RCC *const RCC = ((struct RCC *const)RCC_BASE);
static struct SYSCFG *const SYSCFG = ((struct SYSCFG *const) SYSCFG_BASE);
static struct FLASH *const FLASH = ((struct FLASH *const) FLASH_R_BASE);
static struct GPIO *const GPIOA = ((struct GPIO *const) GPIOA_BASE);
static struct GPIO *const GPIOB = ((struct GPIO *const) GPIOB_BASE);
static struct GPIO *const GPIOC = ((struct GPIO *const) GPIOC_BASE);
static struct GPIO *const GPIOD = ((struct GPIO *const) GPIOD_BASE);
static struct TIM *const TIM2 = ((struct TIM *const) TIM2_BASE);
static struct TIM *const TIM3 = ((struct TIM *const) TIM3_BASE);
static struct TIM *const TIM4 = ((struct TIM *const) TIM4_BASE);
static struct TIM *const TIM5 = ((struct TIM *const) TIM5_BASE);
static struct TIM *const TIM6 = ((struct TIM *const) TIM6_BASE);
static struct TIM *const TIM7 = ((struct TIM *const) TIM7_BASE);
static struct USART *const USART1 = ((struct USART *const) USART1_BASE);
static struct USART *const USART2 = ((struct USART *const) USART2_BASE);
static struct USART *const USART3 = ((struct USART *const) USART3_BASE);
static struct USART *const UART4 = ((struct USART *const) UART4_BASE);
static struct USART *const UART5 = ((struct USART *const) UART5_BASE);
static struct USART *const USART6 = ((struct USART *const) USART6_BASE);
static struct CAN *const CAN1 = ((struct CAN *const) CAN1_BASE);
static struct CAN *const CAN2 = ((struct CAN *const) CAN2_BASE);
static struct SPI *const I2S1 = ((struct SPI *const) SPI1_BASE);
static struct SPI *const I2S2 = ((struct SPI *const) SPI2_BASE);
static struct SPI *const I2S3 = ((struct SPI *const) SPI3_BASE);
static struct I2C *const I2C1 = ((struct I2C *const) I2C1_BASE);
static struct I2C *const I2C2 = ((struct I2C *const) I2C2_BASE);
static struct I2C *const I2C3 = ((struct I2C *const) I2C3_BASE);
static struct ADC *const ADC1 = ((struct ADC *const) ADC1_BASE);
static struct ADC *const ADC2 = ((struct ADC *const) ADC2_BASE);
static struct ADC *const ADC3 = ((struct ADC *const) ADC3_BASE);
static struct ADCC *const ADCC = ((struct ADCC *const) ADCC_BASE);
static struct DMA *const DMA1 = ((struct DMA *const) DMA1_BASE);
static struct DMA *const DMA2 = ((struct DMA *const) DMA2_BASE);
static struct DMA_Stream *const DMA1_Stream =
  ((struct DMA_Stream *const) (DMA1_BASE + sizeof (struct DMA)));
static struct DMA_Stream *const DMA2_Stream =
  ((struct DMA_Stream *const) (DMA2_BASE + sizeof (struct DMA)));
-------------- next part --------------
extern const uint8_t sys_version[8];
extern const uint32_t sys_board_id;
extern const uint8_t sys_board_name[];

typedef void (*handler)(void);
extern handler vector[16];

static inline const uint8_t *
unique_device_id (void)
{
  /* STM32F103 has 96-bit unique device identifier */
  const uint8_t *addr = (const uint8_t *)0x1ffff7e8;

  return addr;
}

static inline void
set_led (int on)
{
  void (*func) (int) = (void (*)(int))vector[2];

  return (*func) (on);
}

static inline void
flash_unlock (void)
{
  (*vector[3]) ();
}

static inline int
flash_program_halfword (uint32_t addr, uint16_t data)
{
  int (*func) (uint32_t, uint16_t) = (int (*)(uint32_t, uint16_t))vector[4];

  return (*func) (addr, data);
}

static inline int
flash_erase_page (uint32_t addr)
{
  int (*func) (uint32_t) = (int (*)(uint32_t))vector[5];

  return (*func) (addr);
}

static inline int
flash_check_blank (const uint8_t *p_start, size_t size)
{
  int (*func) (const uint8_t *, int) = (int (*)(const uint8_t *, int))vector[6];

  return (*func) (p_start, size);
}

static inline int
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
{
  int (*func) (uint32_t, const uint8_t *, size_t)
    = (int (*)(uint32_t, const uint8_t *, size_t))vector[7];

  return (*func) (dst_addr, src, len);
}

static inline int
flash_protect (void)
{
  int (*func) (void) = (int (*)(void))vector[8];

  return (*func) ();
}

static inline void __attribute__((noreturn))
flash_erase_all_and_exec (void (*entry)(void))
{
  void (*func) (void (*)(void)) = (void (*)(void (*)(void)))vector[9];

  (*func) (entry);
  for (;;);
}

static inline void
usb_lld_sys_init (void)
{
  (*vector[10]) ();
}

static inline void
usb_lld_sys_shutdown (void)
{
  (*vector[11]) ();
}

static inline void
nvic_system_reset (void)
{
  (*vector[12]) ();
}

/*
 * Users can override INLINE by 'attribute((used))' to have an
 * implementation defined.
 */
#if !defined(INLINE)
#define INLINE __inline__
#endif

static INLINE void
clock_init (void)
{
  (*vector[13]) ();
}

static INLINE void
gpio_init (void)
{
  (*vector[14]) ();
}
-------------- next part --------------
/*
 * sys.c - system routines for the initial page for STM32F446
 *
 * Copyright (C) 2013-2016 Flying Stone Technology
 * Author: NIIBE Yutaka <gniibe at fsij.org>
 *
 * Copying and distribution of this file, with or without modification,
 * are permitted in any medium without royalty provided the copyright
 * notice and this notice are preserved.  This file is offered as-is,
 * without any warranty.
 *
 * When the flash ROM is protected, we cannot modify the initial page.
 * We put some system routines (which is useful for any program) here.
 */

#include <stdint.h>
#include <stdlib.h>
#include "board.h"
#include "stm32f446.h"

static void __attribute__((used))
clock_init (void)
{
  /* This is NOT clock setting but perhaps good time for it.  */
  SCB->CPACR |= (0xf << 20);
  asm volatile ("dsb\n\t"
		"isb" : : : "memory");
#if defined(USE_FPU_AUTO_SAVE)
  /* Auto save/restore fp context on exceptions.  */
  FPU->FPCCR = (1 << 31);
#else
  /* No auto save/restore.  */
  FPU->FPCCR = 0;
#endif

  /* HSI setup */
  RCC->CR |= RCC_CR_HSION;
  while (!(RCC->CR & RCC_CR_HSIRDY))
    ;
  /* Reset CR */
  RCC->CR = 0x83;
  RCC->CFGR = 0;
  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
    ;
  /* Reset PLLCFGR */
  RCC->PLLCFGR = 0x24003010;
  /* Reset PLLI2SCFGR */
  RCC->PLLSAICFGR = 0x24003010;
  /* Reset PLLSAICFGR */
  RCC->PLLSAICFGR = 0x24003000;
  
  /* Disable all interrupts */
  RCC->CIR = 0;

  /* HSE setup */
  RCC->CR |= RCC_CR_HSEON;
  while (!(RCC->CR & RCC_CR_HSERDY))
    ;

  /* PLL setup */
  RCC->PLLCFGR = (RCC_PLLCFGR_PLLSRC_HSE
		  | (8 << 0)	/* PLLM=8 */
		  | (360 << 6)	/* PLLN=360 */
		  | (0 << 16)	/* PLLP=DIV2 0:DIV2 1:DIV4 2:DIV6 3:DIV8 */
		  | (6 << 24)	/* PLLQ=6 */
		  | (2 << 28)); /* PLLR=2 */
  RCC->CR |= RCC_CR_PLLON;
  while (!(RCC->CR & RCC_CR_PLLRDY))
    ;

  /* PLLI2S setup */
  RCC->PLLI2SCFGR = ((8 << 0)	    /* PLLM=8 */
		     | (192 << 6)   /* PLLN=192 */
		     | (0 << 16)    /* PLLP=DIV2 0:DIV2 1:DIV4 2:DIV6 3:DIV8 */
		     | (6 << 24)    /* PLLQ=6 */
		     | (2 << 28));  /* PLLR=2 */
  RCC->CR |= RCC_CR_PLLI2SON;
  while (!(RCC->CR & RCC_CR_PLLI2SRDY))
    ;

  /* PLLSAI setup */
  RCC->PLLSAICFGR = ((8 << 0)	    /* PLLM=8 */
		     | (384 << 6)   /* PLLN=384 */
		     | (3 << 16)    /* PLLP=DIV2 0:DIV2 1:DIV4 2:DIV6 3:DIV8 */
		     | (6 << 24)    /* PLLQ=6 */
		     | (2 << 28));  /* must be Reset value */
  RCC->CR |= RCC_CR_PLLSAION;
  while (!(RCC->CR & RCC_CR_PLLSAIRDY))
    ;

  /* Clock settings */
  RCC->CFGR = ((0 << 30)	/* MCO2 0:SYS 1:PLLI2S 2:HSE 3:PLL */
	       | (6 << 27)	/* MCO2PRE 4:DIV2 5:DIV3 6:DIV4 7:DIV5 */
	       | (4 << 24)	/* MCO1PRE 4:DIV2 5:DIV3 6:DIV4 7:DIV5 */
	       | (0 << 23)	/* I2SSRC 0:PLLI2S 1:I2S_CKIN */
	       | (0 << 21)	/* MCO1 0:HSI 1:LSE 2:HSE 3:PLL */
	       | (0 << 16)	/* RTCPRE HSE division factor */
	       | RCC_CFGR_PPRE2_DIV2	/* 4:DIV2 5:DIV4 6:DIV8 7:DIV16 */
	       | RCC_CFGR_PPRE1_DIV4
	       | (0 << 4)	/* HPRE 0xxx:DIV1 4:DIV2 ... 15:DIV512 */
	       | (0 << 2)	/* SWS read only bits */
	       | (0 << 0));	/* SW 0:HSI 1:HSE 2:PLL */

  /*
   * We don't touch RCC->CR2, RCC->CFGR2, RCC->CFGR3, and RCC->CIR.
   */

  /* Flash setup */
  FLASH->ACR = (FLASH_ACR_LATENCY_5WS /* 6 CPU cycle wait */
		| FLASH_ACR_PRFTEN
		| FLASH_ACR_ICEN
		| FLASH_ACR_DCEN);

  /* CRC */
  RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN;

  /* Switching on the configured clock source. */
  RCC->CFGR &= ~RCC_CFGR_SW;
  RCC->CFGR |= RCC_CFGR_SW_PLL;
  while ((RCC->CFGR & RCC_CFGR_SW_PLL) != RCC_CFGR_SW_PLL)
    ;

  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
  RCC->APB2RSTR = RCC_APB2RSTR_SYSCFGRST;
  RCC->APB2RSTR = 0;

  RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
  RCC->APB1RSTR = RCC_AHB1RSTR_DMA2RST;
  RCC->APB1RSTR = 0;

#if defined(HAVE_SYS_H)
  /* Use vectors on RAM */
  SYSCFG->MEMRMP = (SYSCFG->MEMRMP & ~SYSCFG_MEMRMP_MEM_MODE) | 0x3;
#endif
}

/*
 * Port A setup.
 * PA2  - USART2_TX (AF7)
 * PA3  - USART2_RX (AF7)
 * PA5  - LED (LED 1:ON 0:OFF)
 * PA13, PA14 - SWD(AF0)
 * PA11 - CAN1_RX (AF9)
 * PA12 - CAN1_TX (AF9)
 * PA15  - I2S1_WS (AF5)
 */
#define GPIOA_MODER   0xaa8004a0 /* AF Pin 15,14,13,12,11,3,2 Output Pin5 */
#define GPIOA_OTYPER  0x00000000 /* Push-Pull */
#define GPIOA_OSPEEDR 0x03c00c00 /* High speed: Pin12,11,5 */
#define GPIOA_PUPDR   0x00000000 /* No pull-up/pull-down */
#define GPIOA_AFR0    0x00007700 /* AF7 Pin3,2 */
#define GPIOA_AFR1    0x50099000 /* AF9 Pin12,11 */

/*
 * Port B setup.
 * PB3  - I2S1_CK (AF5)
 * PB5  - I2S1_SD (AF5)
 * PB8  - I2C1_SCL(AF4)
 * PB9  - I2C1_SDA(AF4)
 */
#define GPIOB_MODER   0x000a0880 /* AF4 Pin9,8 AF5 Pin5,3 */
#define GPIOB_OTYPER  0x00000300 /* Open-drain Pin9,8 otherwise Push-Pull */
#define GPIOB_OSPEEDR 0x000f0cc0 /* High speed: Pin9,8,5,3 */
#define GPIOB_PUPDR   0x00050000 /* Pin9,8 pull-up otherwise no pull-up/down */
#define GPIOB_AFR0    0x00505000 /* AF5 Pin5,3 */
#define GPIOB_AFR1    0x00000044 /* AF4 Pin9,8 */

/*
 * Port C setup.
 * PC13  - USER Button
 */
#define GPIOC_MODER   0x000000ff /* Input Pin13 Analog input Pin3,2,1,0 */
#define GPIOC_OTYPER  0x00000000 /* Push-Pull */
#define GPIOC_OSPEEDR 0x00000000
#define GPIOC_PUPDR   0x00000000 /* No pull-up/pull-down */

#define GPIO_LED GPIOA
#define GPIO_LED_SET_TO_EMIT    5

static void __attribute__((used))
gpio_init (void)
{
  /* Enable GPIO clock. */
  RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN
		   | RCC_AHB1ENR_GPIOBEN
		   | RCC_AHB1ENR_GPIOCEN);
  RCC->AHB1RSTR = (RCC_AHB1RSTR_GPIOARST
		   | RCC_AHB1RSTR_GPIOBRST
		   | RCC_AHB1RSTR_GPIOCRST);
  RCC->AHB1RSTR = 0;

  GPIOA->AFR[0]  = GPIOA_AFR0;
  GPIOA->AFR[1]  = GPIOA_AFR1;
  GPIOA->OSPEEDR = GPIOA_OSPEEDR;
  GPIOA->OTYPER  = GPIOA_OTYPER;
  GPIOA->MODER   = GPIOA_MODER;
  GPIOA->PUPDR   = GPIOA_PUPDR;

  GPIOB->AFR[0]  = GPIOB_AFR0;
  GPIOB->AFR[1]  = GPIOB_AFR1;
  GPIOB->OSPEEDR = GPIOB_OSPEEDR;
  GPIOB->OTYPER  = GPIOB_OTYPER;
  GPIOB->MODER   = GPIOB_MODER;
  GPIOB->PUPDR   = GPIOB_PUPDR;

  GPIOC->OSPEEDR = GPIOC_OSPEEDR;
  GPIOC->OTYPER  = GPIOC_OTYPER;
  GPIOC->MODER   = GPIOC_MODER;
  GPIOC->PUPDR   = GPIOC_PUPDR;
}

#define CORTEX_PRIORITY_BITS    4
#define CORTEX_PRIORITY_MASK(n)  ((n) << (8 - CORTEX_PRIORITY_BITS))
#define USB_LP_CAN1_RX0_IRQn	 20
#define STM32_USB_IRQ_PRIORITY   11

struct NVIC {
  uint32_t ISER[8];
  uint32_t unused1[24];
  uint32_t ICER[8];
  uint32_t unused2[24];
  uint32_t ISPR[8];
  uint32_t unused3[24];
  uint32_t ICPR[8];
  uint32_t unused4[24];
  uint32_t IABR[8];
  uint32_t unused5[56];
  uint32_t IPR[60];
};

static struct NVIC *const NVICBase = ((struct NVIC *const)0xE000E100);
#define NVIC_ISER(n)	(NVICBase->ISER[n >> 5])
#define NVIC_ICPR(n)	(NVICBase->ICPR[n >> 5])
#define NVIC_IPR(n)	(NVICBase->IPR[n >> 2])

static void
nvic_enable_vector (uint32_t n, uint32_t prio)
{
  unsigned int sh = (n & 3) << 3;

  NVIC_IPR (n) = (NVIC_IPR(n) & ~(0xFF << sh)) | (prio << sh);
  NVIC_ICPR (n) = 1 << (n & 0x1F);
  NVIC_ISER (n) = 1 << (n & 0x1F);
}

static void
usb_cable_config (int enable)
{
#if defined(GPIO_USB_SET_TO_ENABLE)
  if (enable)
    GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE);
  else
    GPIO_USB->BSRR = (1 << GPIO_USB_SET_TO_ENABLE) << 16;
#elif defined(GPIO_USB_CLEAR_TO_ENABLE)
  if (enable)
    GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE) << 16;
  else
    GPIO_USB->BSRR = (1 << GPIO_USB_CLEAR_TO_ENABLE);
#else
  (void)enable;
#endif
}

void
set_led (int on)
{
#if defined(GPIO_LED_CLEAR_TO_EMIT)
  if (on)
    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT) << 16;
  else
    GPIO_LED->BSRR = (1 << GPIO_LED_CLEAR_TO_EMIT);
#else
  if (on)
    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT);
  else
    GPIO_LED->BSRR = (1 << GPIO_LED_SET_TO_EMIT) << 16;
#endif
}

static void wait (int count)
{
  int i;

  for (i = 0; i < count; i++)
    asm volatile ("" : : "r" (i) : "memory");
}

#if 0
static void
usb_lld_sys_shutdown (void)
{
  RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
  usb_cable_config (0);
}

static void
usb_lld_sys_init (void)
{
  if ((RCC->APB1ENR & RCC_APB1ENR_USBEN)
      && (RCC->APB1RSTR & RCC_APB1RSTR_USBRST) == 0)
    /* Make sure the device is disconnected, even after core reset.  */
    {
      usb_lld_sys_shutdown ();
      /* Disconnect requires SE0 (>= 2.5uS).  */
      wait (300);
    }

  usb_cable_config (1);
  RCC->APB1ENR |= RCC_APB1ENR_USBEN;
  nvic_enable_vector (USB_LP_CAN1_RX0_IRQn,
		      CORTEX_PRIORITY_MASK (STM32_USB_IRQ_PRIORITY));
  /*
   * Note that we also have other IRQ(s):
   * 	USB_HP_CAN1_TX_IRQn (for double-buffered or isochronous)
   * 	USBWakeUp_IRQn (suspend/resume)
   */
  RCC->APB1RSTR = RCC_APB1RSTR_USBRST;
  RCC->APB1RSTR = 0;
}

#define FLASH_KEY1               0x08192A3BUL
#define FLASH_KEY2               0x4C5D6E7FL

enum flash_status
{
  FLASH_BUSY = 1,
  FLASH_ERROR_PG,
  FLASH_ERROR_WRP,
  FLASH_COMPLETE,
  FLASH_TIMEOUT
};

static void __attribute__ ((used))
flash_unlock (void)
{
  FLASH->KEYR = FLASH_KEY1;
  FLASH->KEYR = FLASH_KEY2;
}


#define intr_disable()  asm volatile ("cpsid   i" : : : "memory")
#define intr_enable()  asm volatile ("cpsie   i" : : : "memory")

#define FLASH_SR_BSY		0x01
#define FLASH_SR_PGERR		0x04
#define FLASH_SR_WRPRTERR	0x10
#define FLASH_SR_EOP		0x20

#define FLASH_CR_PG	0x0001
#define FLASH_CR_PER	0x0002
#define FLASH_CR_MER	0x0004
#define FLASH_CR_OPTPG	0x0010
#define FLASH_CR_OPTER	0x0020
#define FLASH_CR_STRT	0x0040
#define FLASH_CR_LOCK	0x0080
#define FLASH_CR_OPTWRE	0x0200
#define FLASH_CR_ERRIE	0x0400
#define FLASH_CR_EOPIE	0x1000

static int
flash_wait_for_last_operation (uint32_t timeout)
{
  int status;

  do
    {
      status = FLASH->SR;
      if (--timeout == 0)
	break;
    }
  while ((status & FLASH_SR_BSY) != 0);

  return status & (FLASH_SR_BSY|FLASH_SR_PGERR|FLASH_SR_WRPRTERR);
}

#define FLASH_PROGRAM_TIMEOUT 0x00010000
#define FLASH_ERASE_TIMEOUT   0x01000000

static int
flash_program_halfword (uint32_t addr, uint16_t data)
{
  int status;

  status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);

  intr_disable ();
  if (status == 0)
    {
      FLASH->CR |= FLASH_CR_PG;

      *(volatile uint16_t *)addr = data;

      status = flash_wait_for_last_operation (FLASH_PROGRAM_TIMEOUT);
      FLASH->CR &= ~FLASH_CR_PG;
    }
  intr_enable ();

  return status;
}

static int
flash_erase_page (uint32_t addr)
{
  int status;

  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);

  intr_disable ();
  if (status == 0)
    {
      FLASH->CR |= FLASH_CR_PER;
      FLASH->AR = addr;
      FLASH->CR |= FLASH_CR_STRT;

      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
      FLASH->CR &= ~FLASH_CR_PER;
    }
  intr_enable ();

  return status;
}

static int
flash_check_blank (const uint8_t *p_start, size_t size)
{
  const uint8_t *p;

  for (p = p_start; p < p_start + size; p++)
    if (*p != 0xff)
      return 0;

  return 1;
}

#define FLASH_START_ADDR 0x08000000
#define FLASH_END	 0x0807FFFF
#define FLASH_OFFSET     0x1000     /* First pages are not-writable
				       when protected.  */
#define FLASH_SIZE_REG   ((uint16_t *)0x1fff7a22)
#define CHIP_ID_REG      ((uint32_t *)0xe0042000)

#define FLASH_START      (FLASH_START_ADDR+FLASH_OFFSET)

static int
flash_write (uint32_t dst_addr, const uint8_t *src, size_t len)
{
  int status;
  uint32_t flash_end = FLASH_END;

  if (dst_addr < FLASH_START || dst_addr + len > flash_end)
    return 0;

  while (len)
    {
      uint16_t hw = *src++;

      hw |= (*src++ << 8);
      status = flash_program_halfword (dst_addr, hw);
      if (status != 0)
	return 0;		/* error return */

      dst_addr += 2;
      len -= 2;
    }

  return 1;
}

#define OPTION_BYTES_ADDR 0x1fffc008

static int
flash_protect (void)
{
  int status;
  uint16_t option_bytes_value;

  status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);

  intr_disable ();
  if (status == 0)
    {
      FLASH->OPTKEYR = FLASH_KEY1;
      FLASH->OPTKEYR = FLASH_KEY2;

      FLASH->CR |= FLASH_CR_OPTER;
      FLASH->CR |= FLASH_CR_STRT;

      status = flash_wait_for_last_operation (FLASH_ERASE_TIMEOUT);
      FLASH->CR &= ~FLASH_CR_OPTER;
    }
  intr_enable ();

  if (status != 0)
    return 0;

  option_bytes_value = *(uint16_t *)OPTION_BYTES_ADDR;
  return (option_bytes_value & 0xff) == 0xff ? 1 : 0;
}

static void __attribute__((naked))
flash_erase_all_and_exec (void (*entry)(void))
{
  uint32_t addr = FLASH_START;
  uint32_t end = FLASH_START_ADDR + (*FLASH_SIZE_REG)*1024;
  uint32_t page_size = 1024;
  int r;

  if (((*CHIP_ID_REG) & 0xfff) == 0x0414)
    page_size = 2048;

  while (addr < end)
    {
      r = flash_erase_page (addr);
      if (r != 0)
	break;

      addr += page_size;
    }

  if (addr >= end)
    (*entry) ();

  for (;;);
}
#else
static int
noop (void)
{
  return 0;
}
#endif


#define SYSRESETREQ 0x04
static void
nvic_system_reset (void)
{
  SCB->AIRCR = (0x05FA0000 | (SCB->AIRCR & 0x70) | SYSRESETREQ);
  asm volatile ("dsb");
  for (;;);
}

static void __attribute__ ((naked))
reset (void)
{
  /*
   * This code may not be at the start of flash ROM, because of DFU.
   * So, we take the address from PC.
   */
#if defined(__ARM_ARCH_6M__)
  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
		"ldr	r0, 1f\n\t"     /* r0 = RAM start */
		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
		"mov	r2, #0x10\n\t"
		"lsl	r2, #8\n\t"
		"add	r1, r1, r2\n\t"
		"sub	r2, r2, #1\n\t"
		"bic	r1, r1, r2\n\t"
		"mov	r2, #188\n"
	"2:\n\t" /* Copy vectors.  It will be enabled later by clock_init.  */
		"ldr	r3, [r1, r2]\n\t"
		"str	r3, [r0, r2]\n\t"
		"sub	r2, #4\n\t"
		"bcs	2b\n\t"
		"msr	MSP, r3\n\t"	/* Main (exception handler) stack. */
		"ldr	r0, [r1, #4]\n\t" /* Reset handler.                */
		"bx	r0\n\t"
		".align	2\n"
	"1:	.word	0x20000000"
		: /* no output */ : /* no input */ : "memory");
#else
  asm volatile ("cpsid	i\n\t"		/* Mask all interrupts. */
		"ldr	r0, 1f\n\t"     /* r0 = SCR */
		"mov	r1, pc\n\t"	/* r1 = (PC + 0x1000) & ~0x0fff */
		"mov	r2, #0x1000\n\t"
		"add	r1, r1, r2\n\t"
		"sub	r2, r2, #1\n\t"
		"bic	r1, r1, r2\n\t"
		"str	r1, [r0, #8]\n\t"	/* Set SCR->VCR */
		"ldr	r0, [r1], #4\n\t"
		"msr	MSP, r0\n\t"	/* Main (exception handler) stack. */
		"ldr	r0, [r1]\n\t"	/* Reset handler.                  */
		"bx	r0\n\t"
		".align	2\n"
	"1:	.word	0xe000ed00"
		: /* no output */ : /* no input */ : "memory");
#endif
  /* Never reach here. */
}

typedef void (*handler)(void);
extern uint8_t __ram_end__;

handler vector[] __attribute__ ((section(".vectors"))) = {
  (handler)&__ram_end__,
  reset,
  (handler)set_led,
#if 0
  flash_unlock,
  (handler)flash_program_halfword,
  (handler)flash_erase_page,
  (handler)flash_check_blank,
  (handler)flash_write,
  (handler)flash_protect,
  (handler)flash_erase_all_and_exec,
  usb_lld_sys_init,
  usb_lld_sys_shutdown,
#else
  noop,
  noop,
  noop,
  noop,
  noop,
  noop,
  noop,
  noop,
  noop,
#endif
  nvic_system_reset,
  clock_init,
  gpio_init,
  NULL,
};

const uint8_t sys_version[8] __attribute__((section(".sys.version"))) = {
  3*2+2,	     /* bLength */
  0x03,		     /* bDescriptorType = USB_STRING_DESCRIPTOR_TYPE */
  /* sys version: "2.1" */
  '2', 0, '.', 0, '1', 0,
};

const uint32_t __attribute__((section(".sys.board_id")))
sys_board_id = BOARD_ID;

const uint8_t __attribute__((section(".sys.board_name")))
sys_board_name[] = BOARD_NAME;
-------------- next part --------------
/*
 * ST32F446 memory setup.
 */
__main_stack_size__     = 0x0400;  /* Exception handlers     */
__process0_stack_size__  = 0x1000; /* Main program           */
__process1_stack_size__  = 0x0100; /* first thread program */
__process2_stack_size__  = 0x0100; /* second thread program */
__process3_stack_size__  = 0x0100; /* third thread program */
__process4_stack_size__  = 0x0100; /* 4-th thread program */
__process5_stack_size__  = 0x0100; /* 5-th thread program */
__process6_stack_size__  = 0x0100; /* 6-th thread program */
__process7_stack_size__  = 0x0100; /* 7-th thread program */
__process_stack_heap_size__ = 0x800;

MEMORY
{
    flash0 : org = 0x08000000, len = 4k
    flash  : org = 0x08000000+0x1000, len = 508k
    ram : org = 0x20000000, len = 128k
}

__ram_start__           = ORIGIN(ram);
__ram_size__            = 128k;
__ram_end__             = __ram_start__ + __ram_size__;

SECTIONS
{
    . = 0;

    .sys : ALIGN(4) SUBALIGN(4)
    {
	_sys = .;
	KEEP(*(.vectors))
	. = ALIGN(16);
	KEEP(*(.sys.version))
	KEEP(*(.sys.board_id))
	KEEP(*(.sys.board_name))
	build/sys.o(.text)
	build/sys.o(.text.*)
	build/sys.o(.rodata)
	build/sys.o(.rodata.*)
	. = ALIGN(1024);
/*
	*(.sys.0)
	*(.sys.1)
	*(.sys.2)
*/
    } > flash0 =0xffffffff

    _text = .;

    .startup : ALIGN(128) SUBALIGN(128)
    {
        KEEP(*(.startup.vectors))
        . = ALIGN (16);
    } > flash =0xffffffff

    .text : ALIGN(16) SUBALIGN(16)
    {
        *(.text.startup.*)
        *(.text)
        *(.text.*)
        *(.rodata)
        *(.rodata.*)
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
	. = ALIGN(8);
    } > flash

    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} > flash

    .ARM.exidx : {
        PROVIDE(__exidx_start = .);
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
        PROVIDE(__exidx_end = .);
     } > flash

    .eh_frame_hdr : {*(.eh_frame_hdr)} > flash

    .eh_frame : ONLY_IF_RO {*(.eh_frame)} > flash

    .textalign : ONLY_IF_RO { . = ALIGN(8); } > flash

    _etext = .;
    _textdata = _etext;

    .vectors_in_ram :
    {
        . = ALIGN(8);
        __vector_ram_addr__ = .;
	KEEP(*(.bss.startup.*))
    } > ram

    .process_stack :
    {
        . = ALIGN(8);
        __process_stack_heap_base__ = .;
        . += __process_stack_heap_size__;
        . = ALIGN(8);
        __process7_stack_base__ = .;
        . += __process7_stack_size__;
        . = ALIGN(8);
        __process7_stack_end__ = .;
        __process6_stack_base__ = .;
        . += __process6_stack_size__;
        . = ALIGN(8);
        __process6_stack_end__ = .;
        __process5_stack_base__ = .;
        . += __process5_stack_size__;
        . = ALIGN(8);
        __process5_stack_end__ = .;
        __process4_stack_base__ = .;
        . += __process4_stack_size__;
        . = ALIGN(8);
        __process4_stack_end__ = .;
        . = ALIGN(8);
        __process3_stack_base__ = .;
        . += __process3_stack_size__;
        . = ALIGN(8);
        __process3_stack_end__ = .;
        __process2_stack_base__ = .;
        . += __process2_stack_size__;
        . = ALIGN(8);
        __process2_stack_end__ = .;
        __process1_stack_base__ = .;
        . += __process1_stack_size__;
        . = ALIGN(8);
        __process1_stack_end__ = .;
        __process0_stack_base__ = .;
        . += __process0_stack_size__;
        . = ALIGN(8);
        __process0_stack_end__ = .;
    } > ram

    .main_stack :
    {
        . = ALIGN(8);
        __main_stack_base__ = .;
        . += __main_stack_size__;
        . = ALIGN(8);
        __main_stack_end__ = .;
    } > ram

    .data :
    {
        . = ALIGN(4);
        PROVIDE(_data = .);
        *(.data)
        . = ALIGN(4);
        *(.data.*)
        . = ALIGN(4);
        *(.ramtext)
        . = ALIGN(4);
        PROVIDE(_edata = .);
    } > ram AT > flash

    .bss :
    {
        . = ALIGN(4);
        PROVIDE(_bss_start = .);
        *(.bss)
        . = ALIGN(4);
        *(.bss.*)
        . = ALIGN(4);
        *(COMMON)
        . = ALIGN(4);
        PROVIDE(_bss_end = .);
    } > ram

    PROVIDE(end = .);
    _end            = .;
}

__heap_base__   = _end;
__heap_end__    = __ram_end__;


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