r3552 - in trunk/kernel/source/linux-2.6-2.6.12/debian: .
patches-debian patches-debian/series
Sven Luther
luther at costa.debian.org
Sat Jul 16 12:16:21 UTC 2005
Author: luther
Date: 2005-07-16 12:16:20 +0000 (Sat, 16 Jul 2005)
New Revision: 3552
Added:
trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/powerpc-g4-l2-flush-errata.patch
Modified:
trunk/kernel/source/linux-2.6-2.6.12/debian/changelog
trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/series/2.6.12-1
Log:
Readded powerpc-g4-l2-flush-errata.patch after cleanup.
Modified: trunk/kernel/source/linux-2.6-2.6.12/debian/changelog
===================================================================
--- trunk/kernel/source/linux-2.6-2.6.12/debian/changelog 2005-07-16 10:42:19 UTC (rev 3551)
+++ trunk/kernel/source/linux-2.6-2.6.12/debian/changelog 2005-07-16 12:16:20 UTC (rev 3552)
@@ -100,6 +100,7 @@
it and thinks it is not needed.
- Disabled swim3 on powerpc-smp, FTBFS.
- Disabled software-suspend on powerpc-smp, FTBFS, amd64/i386 only smp code.
+ - Rediffed and readded the G4 L2 hardware flush assist patch from Jacob Pan.
(Sven Luther)
-- Joshua Kwan <joshk at triplehelix.org> Sat, 16 Jul 2005 05:54:16 +0300
Added: trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/powerpc-g4-l2-flush-errata.patch
===================================================================
--- trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/powerpc-g4-l2-flush-errata.patch 2005-07-16 10:42:19 UTC (rev 3551)
+++ trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/powerpc-g4-l2-flush-errata.patch 2005-07-16 12:16:20 UTC (rev 3552)
@@ -0,0 +1,243 @@
+# Description: Fixes g4 l2 cache flush and MSR erratas.
+# Patch author: Jacob Pan.
+# Rediffed for 2.6.12 by Sven Luther <luther at debian.org>
+# Upstream status: under review by benh.
+
+. $(dirname $0)/DPATCH
+
+ at DPATCH@
+--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/cputable.c.orig 2005-06-17 19:48:29.000000000 +0000
++++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/cputable.c 2005-07-16 12:09:33.000000000 +0000
+@@ -380,7 +380,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -397,7 +397,7 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -413,7 +413,8 @@
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -428,7 +429,8 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -445,7 +447,8 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -462,7 +465,7 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -479,7 +482,8 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -496,7 +500,8 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -513,7 +518,7 @@
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -529,7 +534,8 @@
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+ CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+@@ -537,7 +543,7 @@
+ .cpu_setup = __setup_cpu_745x
+ },
+ { /* 82xx (8240, 8245, 8260 are all 603e cores) */
+- .pvr_mask = 0x7fff0000,
++ .pvr_mask = 0x7fff0000,
+ .pvr_value = 0x00810000,
+ .cpu_name = "82xx",
+ .cpu_features = CPU_FTR_COMMON |
+--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/l2cr.S.orig 2005-06-17 19:48:29.000000000 +0000
++++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/l2cr.S 2005-07-16 11:50:39.000000000 +0000
+@@ -36,7 +36,9 @@
+ several months. The L2CR is similar, but I'm going
+ to assume the user of this functions knows what they
+ are doing.
+-
++ June 17, 2004.
++ - JPAN: Fixed 745X L3 cache enablement routine, also use HW flush assist.
++
+ Author: Terry Greeniaus (tgree at phys.ualberta.ca)
+ Please e-mail updates to this file to me, thanks!
+ */
+@@ -155,9 +157,7 @@
+ Don't do this unless you accomodate all processor variations.
+ The bit moved on the 7450.....
+ ****/
+-
+- /* TODO: use HW flush assist when available */
+-
++BEGIN_FTR_SECTION
+ lis r4,0x0002
+ mtctr r4
+ li r4,0
+@@ -176,7 +176,23 @@
+ dcbf 0,r4
+ addi r4,r4,32 /* Go to start of next cache line */
+ bdnz 1b
++END_FTR_SECTION_IFCLR(CPU_FTR_HWFLUSH_L2_CACHE)
+
++BEGIN_FTR_SECTION
++ /* Use HW flush assist, MPC7447A errata #3 */
++ oris r4,r4,0x0010 /* Set L2CR[IONLY/11] = 1 */
++ oris r4,r4,0x0001 /* Set L2CR[DONLY/15] = 1 */
++ mtspr L2CR,r4 /* Lock the L2 */
++ sync
++ ori r4,r4,0x0800 /* Set L2CR[L2HWF/20] = 1 */
++ mtspr L2CR,r4 /* Flush the L2 */
++1:
++ mfspr r4,L2CR
++ andi. r4,r4,0x0800 /* L2HWF still set? */
++ bne 1b
++ sync /* sync to clear the store queues before L3 flush (UM step 5)*/
++END_FTR_SECTION_IFSET(CPU_FTR_HWFLUSH_L2_CACHE)
++
+ 2:
+ /* Set up the L2CR configuration bits (and switch L2 off) */
+ /* CPU errata: Make sure the mtspr below is already in the
+@@ -293,17 +309,18 @@
+
+ /* Flush the cache.
+ */
+-
+- /* TODO: use HW flush assist */
+-
+- lis r4,0x0008
+- mtctr r4
+- li r4,0
+-1:
+- lwzx r0,r0,r4
+- dcbf 0,r4
+- addi r4,r4,32 /* Go to start of next cache line */
+- bdnz 1b
++ /* use HW flush assist. (UM 3.6.3.1.5) */
++ mfspr r4, SPRN_L3CR
++ oris r4,r4,0x0040 /* Set L3CR[L3IO/9] = 1. */
++ ori r4,r4,0x0040 /* Set L3CR[L3DO/29] = 1.*/
++ mtspr 1018,r4 /* Lock the L3 by making IONLY and DONLY */
++ ori r4,r4,0x0800 /* Set L3CR[L3HWF/20] for hardware flush */
++ mtspr SPRN_L3CR,r4
++flush_745x_L3_poll:
++ mfspr r4,SPRN_L3CR
++ rlwinm. r4,r4,0,20,20
++ bne flush_745x_L3_poll
++ sync /* Clear the store queues per procedure (UM step 8) */
+
+ 2:
+ /* Set up the L3CR configuration bits (and switch L3 off) */
+@@ -349,8 +366,8 @@
+ cmplwi r5,0
+ beq 4f
+
+- /* Enable the cache */
+- oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
++ /* enable L3 clock */
++ oris r3,r3,(L3CR_L3CLKEN)@h
+ mtspr SPRN_L3CR,r3
+ sync
+
+@@ -358,6 +375,15 @@
+ li r0,256
+ mtctr r0
+ 1: bdnz 1b
++
++ /* Clear MSSSR0 which may cause parity error */
++ xor r5,r5,r5
++ mtspr 1015, r5
++
++ /* Enable L3 cache */
++ oris r3,r3,(L3CR_L3E)@h
++ mtspr SPRN_L3CR,r3
++ sync
+
+ /* Restore MSR (restores EE and DR bits to original state) */
+ 4: SYNC
+--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/traps.c.orig 2005-06-17 19:48:29.000000000 +0000
++++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/traps.c 2005-07-16 11:50:39.000000000 +0000
+@@ -307,7 +307,9 @@
+ case 0x80000:
+ printk("Machine check signal\n");
+ break;
+- case 0: /* for 601 */
++ case 0: /* for 601 and 744x */
++ printk("Transfer error ack signal if 601, or MCP if 744x \n");
++ break;
+ case 0x40000:
+ case 0x140000: /* 7450 MSS error and TEA */
+ printk("Transfer error ack signal\n");
+--- linux-kernel-2.6.12-2.6.12/./include/asm-ppc/cputable.h.orig 2005-06-17 19:48:29.000000000 +0000
++++ linux-kernel-2.6.12-2.6.12/./include/asm-ppc/cputable.h 2005-07-16 11:52:01.000000000 +0000
+@@ -89,6 +89,7 @@
+ #define CPU_FTR_NEED_COHERENT 0x00020000
+ #define CPU_FTR_NO_BTIC 0x00040000
+ #define CPU_FTR_BIG_PHYS 0x00080000
++#define CPU_FTR_HWFLUSH_L2_CACHE 0x00100000
+
+ #ifdef __ASSEMBLY__
+
Modified: trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/series/2.6.12-1
===================================================================
--- trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/series/2.6.12-1 2005-07-16 10:42:19 UTC (rev 3551)
+++ trunk/kernel/source/linux-2.6-2.6.12/debian/patches-debian/series/2.6.12-1 2005-07-16 12:16:20 UTC (rev 3552)
@@ -24,3 +24,4 @@
+ powerpc-mkvmlinuz-support.patch
+ patch-2.6.12.3
+ sparc64-hme-lockup.patch
++ powerpc-g4-l2-flush-errata.dpatch
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