r2633 - trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches
Sven Luther
luther@costa.debian.org
Mon, 07 Mar 2005 16:36:25 +0100
Author: luther
Date: 2005-03-07 16:36:24 +0100 (Mon, 07 Mar 2005)
New Revision: 2633
Modified:
trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch
Log:
Had used the wrong patch here.
Modified: trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch
===================================================================
--- trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch 2005-03-07 13:57:28 UTC (rev 2632)
+++ trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch 2005-03-07 15:36:24 UTC (rev 2633)
@@ -9,481 +9,233 @@
. $(dirname $0)/DPATCH
@DPATCH@
---- /home/sven/debian/kernel/test/kernel-patch-powerpc-2.6.11-2.6.11/tmp/kernel-source-2.6.11-powerpc/include/linux/mv643xx.h 2005-03-05 19:42:47.000000000 +0100
-+++ include/linux/mv643xx.h 2005-03-05 21:23:35.000000000 +0100
-@@ -1,5 +1,5 @@
- /*
-- * mv64340.h - MV-64340 Internal registers definition file.
-+ * mv643xx.h - MV-643XX Internal registers definition file.
- *
- * Copyright 2002 Momentum Computer, Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
-@@ -10,8 +10,8 @@
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
--#ifndef __ASM_MV64340_H
--#define __ASM_MV64340_H
-+#ifndef __ASM_MV643XX_H
-+#define __ASM_MV643XX_H
+--- kernel-source-2.6.11/arch/ppc/boot/simple/Makefile 2005-03-02 08:37:30.000000000 +0100
++++ kernel-source-2.6.11-marvell/arch/ppc/boot/simple/Makefile 2005-03-07 14:13:14.000000000 +0100
+@@ -162,7 +162,7 @@
+ boot-$(CONFIG_8260) += embed_config.o
+ boot-$(CONFIG_BSEIP) += iic.o
+ boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o
+-boot-$(CONFIG_MV64X60) += misc-mv64x60.o
++boot-$(CONFIG_MV64X60) += misc-mv64x60.o mv64x60_stub.o
+ boot-$(CONFIG_RPXCLASSIC) += iic.o pci.o qspan_pci.o
+ boot-$(CONFIG_RPXLITE) += iic.o
+ # Different boards need different serial implementations.
+--- kernel-source-2.6.11/arch/ppc/platforms/chrp_setup.c 2005-03-02 08:38:25.000000000 +0100
++++ kernel-source-2.6.11-marvell/arch/ppc/platforms/chrp_setup.c 2005-03-07 14:13:14.000000000 +0100
+@@ -217,8 +217,13 @@
+ }
+ }
- #ifdef __MIPS__
- #include <asm/addrspace.h>
-@@ -662,116 +662,119 @@
- /* Ethernet Unit Registers */
- /****************************************/
++#ifdef CONFIG_MV64X60
++#include <linux/mv643xx.h>
++#include <asm/mv64x60.h>
++#endif
++
--#define MV64340_ETH_PHY_ADDR_REG 0x2000
--#define MV64340_ETH_SMI_REG 0x2004
--#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
--#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c
--#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
--#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
--#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc
--#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094
--#define MV64340_ETH_BAR_0 0x2200
--#define MV64340_ETH_BAR_1 0x2208
--#define MV64340_ETH_BAR_2 0x2210
--#define MV64340_ETH_BAR_3 0x2218
--#define MV64340_ETH_BAR_4 0x2220
--#define MV64340_ETH_BAR_5 0x2228
--#define MV64340_ETH_SIZE_REG_0 0x2204
--#define MV64340_ETH_SIZE_REG_1 0x220c
--#define MV64340_ETH_SIZE_REG_2 0x2214
--#define MV64340_ETH_SIZE_REG_3 0x221c
--#define MV64340_ETH_SIZE_REG_4 0x2224
--#define MV64340_ETH_SIZE_REG_5 0x222c
--#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230
--#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
--#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
--#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
--#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
--#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
--#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290
--#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
--#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
--#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
--#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
--#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
--#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
--#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
--#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
--#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
--#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
--#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10))
--#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10))
--#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10))
--#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10))
--#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10))
--#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10))
--#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10))
--#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
--#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
--#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
--#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
--#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
--#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
--#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
--#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
--#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
--#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
--#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
--#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
--#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
--#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
--#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
--#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
--#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
--#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
--#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
--#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
--#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
--#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
--#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
--#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
--#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
--#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
--#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
--#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
--#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-+#define MV643XX_ETH_SHARED_REGS 0x2000
-+#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
+-static void __init pegasos_set_l2cr(void)
++static void __init pegasos_stuff(void)
+ {
+ struct device_node *np;
+
+@@ -242,6 +247,19 @@
+ _set_L2CR((*l2cr) | 0x80000000);
+ }
+ }
+
-+#define MV643XX_ETH_PHY_ADDR_REG 0x2000
-+#define MV643XX_ETH_SMI_REG 0x2004
-+#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-+#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
-+#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-+#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-+#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
-+#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
-+#define MV643XX_ETH_BAR_0 0x2200
-+#define MV643XX_ETH_BAR_1 0x2208
-+#define MV643XX_ETH_BAR_2 0x2210
-+#define MV643XX_ETH_BAR_3 0x2218
-+#define MV643XX_ETH_BAR_4 0x2220
-+#define MV643XX_ETH_BAR_5 0x2228
-+#define MV643XX_ETH_SIZE_REG_0 0x2204
-+#define MV643XX_ETH_SIZE_REG_1 0x220c
-+#define MV643XX_ETH_SIZE_REG_2 0x2214
-+#define MV643XX_ETH_SIZE_REG_3 0x221c
-+#define MV643XX_ETH_SIZE_REG_4 0x2224
-+#define MV643XX_ETH_SIZE_REG_5 0x222c
-+#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
-+#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-+#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-+#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-+#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-+#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-+#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
-+#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-+#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-+#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-+#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-+#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-+#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-+#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-+#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-+#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-+#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-+#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
-+#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
-+#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
-+#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
-+#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
-+#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
-+#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
-+#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-+#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-+#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-+#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-+#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-+#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-+#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-+#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-+#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-+#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-+#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-+#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-+#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-+#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-+#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-+#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-+#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-+#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-+#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-+#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-+#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-+#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-+#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-+#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-+#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-+#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
++#ifdef CONFIG_MV64X60
++ // Pegasos II (MV64361)
++ // We have to call mv64x60_init() in arch/ppc/syslib/mv64x60.c
++ // This call will do NOTHING but set the correct value for IRQ & reg base...
++ // This is needed because new Marvell ethernet driver get theses info from
++ // there
++ {
++ static struct mv64x60_handle bh;
++ static struct mv64x60_setup_info si;
++ mv64x60_init(&bh, &si);
++ }
++#endif
+ }
- /*******************************************/
- /* CUNIT Registers */
-@@ -1085,4 +1088,221 @@
- u32 brg_clk_freq;
- };
+ void __init chrp_setup_arch(void)
+@@ -262,7 +280,7 @@
+ ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
--#endif /* __ASM_MV64340_H */
-+/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
-+#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
-+#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
-+#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
-+#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
-+#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
-+#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
-+#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
-+#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
-+#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
-+#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
-+#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
-+#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
-+#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
-+#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
-+#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
-+#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
-+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
-+#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
+ /* On pegasos, enable the L2 cache if not already done by OF */
+- pegasos_set_l2cr();
++ pegasos_stuff();
+
+ /* Lookup PCI host bridges */
+ chrp_find_bridges();
+--- kernel-source-2.6.11/arch/ppc/syslib/Makefile 2005-03-02 08:37:48.000000000 +0100
++++ kernel-source-2.6.11-marvell/arch/ppc/syslib/Makefile 2005-03-07 14:13:14.000000000 +0100
+@@ -59,8 +59,8 @@
+ open_pic.o i8259.o hawk_common.o
+ obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \
+ pci_auto.o indirect_pci.o
+-obj-$(CONFIG_MV64360) += mv64360_pic.o
+-obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o indirect_pci.o
++obj-$(CONFIG_MV64360) +=
++obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o indirect_pci.o mv64360_pic.o
+ obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \
+ pci_auto.o hawk_common.o
+ obj-$(CONFIG_MVME5100_IPMC761_PRESENT) += i8259.o
+--- kernel-source-2.6.11/arch/ppc/syslib/mv64360_pic.c 2005-03-02 08:37:30.000000000 +0100
++++ kernel-source-2.6.11-marvell/arch/ppc/syslib/mv64360_pic.c 2005-03-07 14:13:14.000000000 +0100
+@@ -369,6 +369,10 @@
+ u32 mask;
+ int rc;
+
++ if ( mv64360_ispegasos2() ) return 0;
+
-+#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
-+ MV643XX_ETH_UNICAST_NORMAL_MODE | \
-+ MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
-+ MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
-+ MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
-+ MV643XX_ETH_RECEIVE_BC_IF_IP | \
-+ MV643XX_ETH_RECEIVE_BC_IF_ARP | \
-+ MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
-+ MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
-+ MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
-+ MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
-+ MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
++ printk("not pegasos\n");
+
-+/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
-+#define MV643XX_ETH_CLASSIFY_EN (1<<0)
-+#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
-+#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
-+#define MV643XX_ETH_PARTITION_DISABLE 0
-+#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
+ /* Clear old errors and register CPU interface error intr handler */
+ mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
+ if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
+--- kernel-source-2.6.11/arch/ppc/syslib/mv64x60.c 2005-03-02 08:37:52.000000000 +0100
++++ kernel-source-2.6.11-marvell/arch/ppc/syslib/mv64x60.c 2005-03-07 14:21:04.000000000 +0100
+@@ -314,15 +314,15 @@
+ static struct resource mv64x60_eth_shared_resources[] = {
+ [0] = {
+ .name = "ethernet shared base",
+- .start = MV64340_ETH_SHARED_REGS,
+- .end = MV64340_ETH_SHARED_REGS +
+- MV64340_ETH_SHARED_REGS_SIZE - 1,
++ .start = MV643XX_ETH_SHARED_REGS,
++ .end = MV643XX_ETH_SHARED_REGS +
++ MV643XX_ETH_SHARED_REGS_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ static struct platform_device mv64x60_eth_shared_device = {
+- .name = MV64XXX_ETH_SHARED_NAME,
++ .name = MV643XX_ETH_SHARED_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
+ .resource = mv64x60_eth_shared_resources,
+@@ -341,7 +341,7 @@
+ static struct mv64xxx_eth_platform_data eth0_pd;
+
+ static struct platform_device eth0_device = {
+- .name = MV64XXX_ETH_NAME,
++ .name = MV643XX_ETH_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
+ .resource = mv64x60_eth0_resources,
+@@ -361,10 +361,10 @@
+ },
+ };
+
+-static struct mv64xxx_eth_platform_data eth1_pd;
++static struct mv643xx_eth_platform_data eth1_pd;
+
+ static struct platform_device eth1_device = {
+- .name = MV64XXX_ETH_NAME,
++ .name = MV643XX_ETH_NAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
+ .resource = mv64x60_eth1_resources,
+@@ -475,17 +475,58 @@
+ {
+ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
+
+- if (ppc_md.progress)
+- ppc_md.progress("mv64x60 initialization", 0x0);
++ if (ppc_md.progress) ppc_md.progress("mv64x60 initialization", 0x0);
+
-+#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
-+ MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
-+ MV643XX_ETH_PARTITION_DISABLE
++#if defined(CONFIG_PPC_MULTIPLATFORM)
++ if (mv64360_ispegasos2())
++ {
++ // Pegasos II stuff
+
-+/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
-+#define MV643XX_ETH_RIFB (1<<0)
-+#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
-+#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
-+#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
-+#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
-+#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
-+#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
-+#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
-+#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
-+#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
-+#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
-+#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
-+#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
-+#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
-+#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
-+#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
-+#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
++ if (ppc_md.progress)
++ ppc_md.progress("mv64x60: Pegasos II Detected, skiping most of the init code & patching the ressources tables", 0x0);
+
-+#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
++ spin_lock_init(&mv64x60_lock);
+
-+#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
-+ MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
-+ MV643XX_ETH_IPG_INT_RX(0) | \
-+ MV643XX_ETH_TX_BURST_SIZE_4_64BIT
++ if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh))
++ {
++ if (ppc_md.progress) ppc_md.progress("mv64x60_init: Init error", 0x0);
++ return -1;
++ }
+
-+/* These macros describe Ethernet Port serial control reg (PSCR) bits */
-+#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
-+#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
-+#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
-+#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
-+#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
-+#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
-+#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
-+#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
-+#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
-+#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
-+#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-+#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
-+#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
-+#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
-+#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
-+#define MV643XX_ETH_FORCE_LINK_FAIL 0
-+#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
-+#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
-+#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
-+#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
-+#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
-+#define MV643XX_ETH_DTE_ADV_0 0
-+#define MV643XX_ETH_DTE_ADV_1 (1<<14)
-+#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
-+#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
-+#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
-+#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
-+#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
-+#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
-+#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
-+#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
-+#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
-+#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
-+#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
-+#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
-+#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
-+#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
-+#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
-+#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-+#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
-+#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
-+#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
-+#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
++ // Pegasos II use IRQ 9 for every port
++ // Also notice that the ethernet driver (& others) have to
++ // use SA_SHIRQ instead of SA_INTERRUPT
++ // Also the Pegasos II has only port 0 & 1 available (MV64361)
++
++#ifdef CONFIG_MV643XX_ETH_0
++ mv64x60_eth0_resources[0].start = 9;
++ mv64x60_eth0_resources[0].end = 9;
++#endif
+
++#ifdef CONFIG_MV643XX_ETH_1
++ mv64x60_eth1_resources[0].start = 9;
++ mv64x60_eth1_resources[0].end = 9;
++#endif
+
-+#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
-+ MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
-+ MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
-+ MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
-+ MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
-+ MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
-+ MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
-+ (1<<9) /* reserved */ | \
-+ MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
-+ MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
-+ MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
-+ MV643XX_ETH_DTE_ADV_0 | \
-+ MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
-+ MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
-+ MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
-+ MV643XX_ETH_CLR_EXT_LOOPBACK | \
-+ MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
-+ MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
++ // Marvell register is at 0xf1000000 on Pegasos II
++ mv64x60_eth_shared_resources[0].start = 0xf1000000 + MV643XX_ETH_SHARED_REGS;
++ mv64x60_eth_shared_resources[0].end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + MV643XX_ETH_SHARED_REGS_SIZE - 1;
++
++ // For Pegasos II, we stop here
++ // Indeed, we only need the resources info for
++ // the ethernet driver ATM
++ if (ppc_md.progress) ppc_md.progress("mv64x60: End", 0x0);
++ return 0;
++ }
++#endif
++
+ spin_lock_init(&mv64x60_lock);
+ mv64x60_early_init(bh, si);
+
+ if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
+ iounmap(bh->v_base);
+ bh->v_base = 0;
+- if (ppc_md.progress)
+- ppc_md.progress("mv64x60_init: Can't determine chip",0);
++ if (ppc_md.progress) ppc_md.progress("mv64x60_init: Can't determine chip",0);
+ return -1;
+ }
+
+@@ -823,6 +864,18 @@
+ u16 val;
+ u8 save_exclude;
+
++#if defined(CONFIG_PPC_MULTIPLATFORM)
++ if (mv64360_ispegasos2())
++ {
++ // we could use the OF pci stuff
++ // but we know Pegasos II use the MV64361 chipset
++ // If people think it's not nice enough I could add some PCI code
++ // to detect that using OF
++ bh->type = MV64x60_TYPE_MV64360;
++ return 0;
++ }
++#endif
+
-+/* These macros describe Ethernet Serial Status reg (PSR) bits */
-+#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
-+#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
-+#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
-+#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
-+#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
-+#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
-+/* PSR bit 6 is undocumented */
-+#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
-+#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
-+#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
-+#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
-+/* PSR bits 11-31 are reserved */
-+
-+#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
-+#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
-+
-+#define MV643XX_ETH_DESC_SIZE 64
-+
-+#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
-+#define MV643XX_ETH_NAME "mv643xx_eth"
-+
-+struct mv643xx_eth_platform_data {
-+ /*
-+ * Non-values for mac_addr, phy_addr, port_config, etc.
-+ * override the default value. Setting the corresponding
-+ * force_* field, causes the default value to be overridden
-+ * even when zero.
-+ */
-+ unsigned int force_phy_addr:1;
-+ unsigned int force_port_config:1;
-+ unsigned int force_port_config_extend:1;
-+ unsigned int force_port_sdma_config:1;
-+ unsigned int force_port_serial_control:1;
-+ int phy_addr;
-+ char *mac_addr; /* pointer to mac address */
-+ u32 port_config;
-+ u32 port_config_extend;
-+ u32 port_sdma_config;
-+ u32 port_serial_control;
-+ u32 tx_queue_size;
-+ u32 rx_queue_size;
-+ u32 tx_sram_addr;
-+ u32 tx_sram_size;
-+ u32 rx_sram_addr;
-+ u32 rx_sram_size;
-+};
-+
-+#endif /* __ASM_MV643XX_H */
---- /home/sven/debian/kernel/test/kernel-patch-powerpc-2.6.11-2.6.11/tmp/kernel-source-2.6.11-powerpc/drivers/net/mv643xx_eth.c 2005-03-02 08:38:01.000000000 +0100
-+++ drivers/net/mv643xx_eth.c 2005-03-05 21:23:35.000000000 +0100
+ memset(&hose, 0, sizeof(hose));
+ setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
+ bh->v_base + MV64x60_PCI0_CONFIG_DATA);
+--- kernel-source-2.6.11/drivers/net/Kconfig 2005-03-02 08:38:25.000000000 +0100
++++ kernel-source-2.6.11-marvell/drivers/net/Kconfig 2005-03-07 14:13:14.000000000 +0100
+@@ -2094,10 +2094,11 @@
+
+ config MV643XX_ETH
+ tristate "MV-643XX Ethernet support"
+- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX
++ depends on MOMENCO_OCELOT_CA || MOMENCO_JAGUAR_ATX || MV64X60
+ help
+ This driver supports the gigabit Ethernet on the Marvell MV643XX
+- chipset which is used in the Momenco Ocelot C and Jaguar ATX.
++ chipset which is used in the Momenco Ocelot C, Jaguar ATX and
++ bPlan Pegasos II computer.
+
+ config MV643XX_ETH_0
+ bool "MV-643XX Port 0"
+--- kernel-source-2.6.11/drivers/net/mv643xx_eth.c 2005-03-02 08:38:01.000000000 +0100
++++ kernel-source-2.6.11-marvell/drivers/net/mv643xx_eth.c 2005-03-07 14:25:38.000000000 +0100
@@ -1,5 +1,5 @@
/*
- * drivers/net/mv64340_eth.c - Driver for MV64340X ethernet ports
@@ -504,7 +256,7 @@
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
-@@ -24,80 +30,100 @@
+@@ -24,80 +30,101 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
@@ -543,6 +295,7 @@
#include <asm/pgtable.h>
#include <asm/system.h>
+#include <asm/delay.h>
++#include <asm/mv64x60.h>
#include "mv643xx_eth.h"
/*
@@ -647,7 +400,7 @@
unsigned long flags;
spin_lock_irqsave(&mp->lock, flags);
-@@ -108,21 +134,21 @@
+@@ -108,21 +135,21 @@
}
dev->mtu = new_mtu;
@@ -676,7 +429,7 @@
}
spin_unlock_irqrestore(&mp->lock, flags);
-@@ -130,17 +156,17 @@
+@@ -130,17 +157,17 @@
}
/*
@@ -701,7 +454,7 @@
struct pkt_info pkt_info;
struct sk_buff *skb;
-@@ -148,28 +174,18 @@
+@@ -148,28 +175,18 @@
panic("%s: Error in test_set_bit / clear_bit", dev->name);
while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
@@ -735,7 +488,7 @@
break;
}
skb_reserve(skb, 2);
-@@ -186,46 +202,45 @@
+@@ -186,46 +203,45 @@
add_timer(&mp->timeout);
mp->rx_timer_flag = 1;
}
@@ -799,7 +552,7 @@
unsigned int port_num = mp->port_num;
eth_port_init_mac_tables(port_num);
-@@ -234,64 +249,59 @@
+@@ -234,64 +250,59 @@
}
/*
@@ -891,7 +644,7 @@
printk(KERN_INFO "%s: TX timeout ", dev->name);
-@@ -300,31 +310,31 @@
+@@ -300,31 +311,31 @@
}
/*
@@ -936,7 +689,7 @@
struct net_device_stats *stats = &mp->stats;
struct pkt_info pkt_info;
int released = 1;
-@@ -341,33 +351,36 @@
+@@ -341,33 +352,36 @@
stats->tx_errors++;
}
@@ -991,7 +744,7 @@
}
spin_unlock(&mp->lock);
-@@ -376,60 +389,59 @@
+@@ -376,60 +390,59 @@
}
/*
@@ -1072,7 +825,7 @@
}
if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
stats->rx_errors++;
-@@ -445,11 +457,11 @@
+@@ -445,11 +458,11 @@
if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
@@ -1087,7 +840,7 @@
netif_receive_skb(skb);
#else
netif_rx(skb);
-@@ -461,74 +473,74 @@
+@@ -461,74 +474,74 @@
}
/*
@@ -1195,7 +948,7 @@
queue_task(&mp->rx_task, &tq_immediate);
mark_bh(IMMEDIATE_BH);
#else
-@@ -538,25 +550,15 @@
+@@ -538,25 +551,15 @@
}
/* PHY status changed */
if (eth_int_cause_ext & (BIT16 | BIT20)) {
@@ -1229,7 +982,7 @@
}
}
-@@ -570,7 +572,7 @@
+@@ -570,7 +573,7 @@
return IRQ_HANDLED;
}
@@ -1238,7 +991,7 @@
/*
* eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
-@@ -584,9 +586,9 @@
+@@ -584,9 +587,9 @@
* , and the required delay of the interrupt in usec.
*
* INPUT:
@@ -1251,7 +1004,7 @@
*
* OUTPUT:
* Interrupt coalescing mechanism value is set in MV-643xx chip.
-@@ -596,15 +598,15 @@
+@@ -596,15 +599,15 @@
*
*/
static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
@@ -1272,7 +1025,7 @@
return coal;
}
-@@ -618,13 +620,13 @@
+@@ -618,13 +621,13 @@
* This parameter is a timeout counter, that counts in 64 t_clk
* chunks ; that when timeout event occurs a maskable interrupt
* occurs.
@@ -1290,7 +1043,7 @@
*
* OUTPUT:
* Interrupt coalescing mechanism value is set in MV-643xx chip.
-@@ -634,48 +636,48 @@
+@@ -634,48 +637,53 @@
*
*/
static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
@@ -1330,14 +1083,20 @@
+ struct mv643xx_private *mp = netdev_priv(dev);
unsigned int port_num = mp->port_num;
- int err = err;
+-
+ int err;
-
++#if defined(CONFIG_PPC_MULTIPLATFORM)
++ int IRQ_Flags = mv64360_ispegasos2() ? SA_SHIRQ : SA_INTERRUPT;
++#else
++ int IRQ_Flags = SA_INTERRUPT;
++#endif
++
spin_lock_irq(&mp->lock);
- err = request_irq(dev->irq, mv64340_eth_int_handler,
- SA_INTERRUPT | SA_SAMPLE_RANDOM, dev->name, dev);
+ err = request_irq(dev->irq, mv643xx_eth_int_handler,
-+ SA_INTERRUPT | SA_SAMPLE_RANDOM, dev->name, dev);
++ IRQ_Flags | SA_SAMPLE_RANDOM, dev->name, dev);
if (err) {
- printk(KERN_ERR "Can not assign IRQ number to MV64340_eth%d\n",
@@ -1353,7 +1112,7 @@
printk("%s: Error opening interface\n", dev->name);
err = -EBUSY;
goto out_free;
-@@ -698,66 +700,35 @@
+@@ -698,66 +706,35 @@
* ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*
* DESCRIPTION:
@@ -1434,7 +1193,7 @@
}
/* Save Rx desc pointer to driver struct. */
-@@ -766,293 +737,288 @@
+@@ -766,293 +743,288 @@
mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
@@ -1858,7 +1617,7 @@
free_irq(dev->irq, dev);
spin_unlock_irq(&mp->lock);
-@@ -1060,59 +1026,64 @@
+@@ -1060,59 +1032,64 @@
return 0;
}
@@ -1949,7 +1708,7 @@
mp->rx_task.func(dev);
*budget -= work_done;
dev->quota -= work_done;
-@@ -1123,12 +1094,12 @@
+@@ -1123,12 +1100,12 @@
if (done) {
spin_lock_irqsave(&mp->lock, flags);
__netif_rx_complete(dev);
@@ -1967,7 +1726,7 @@
spin_unlock_irqrestore(&mp->lock, flags);
}
-@@ -1137,19 +1108,19 @@
+@@ -1137,19 +1114,19 @@
#endif
/*
@@ -1994,7 +1753,7 @@
struct net_device_stats *stats = &mp->stats;
ETH_FUNC_RET_STATUS status;
unsigned long flags;
-@@ -1157,119 +1128,195 @@
+@@ -1157,119 +1134,195 @@
if (netif_queue_stopped(dev)) {
printk(KERN_ERR
@@ -2263,7 +2022,7 @@
* Stop getting skb's from upper layers.
* Getting skb's from upper layers will be enabled again after
* packets are released.
-@@ -1277,7 +1324,6 @@
+@@ -1277,7 +1330,6 @@
netif_stop_queue(dev);
/* Update statistics and start of transmittion time */
@@ -2271,7 +2030,7 @@
stats->tx_packets++;
dev->trans_start = jiffies;
-@@ -1287,214 +1333,304 @@
+@@ -1287,214 +1339,308 @@
}
/*
@@ -2344,6 +2103,8 @@
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ BUG_ON(!res);
+ dev->irq = res->start;
++
++ printk(KERN_INFO "%s: Using IRQ %d\n", __func__, dev->irq);
- dev->open = mv64340_eth_open;
- dev->stop = mv64340_eth_stop;
@@ -2619,6 +2380,8 @@
}
-#endif
- return 0;
++
++ printk("%s: return %d\n", __func__, rc);
+ return rc;
}
@@ -2684,7 +2447,7 @@
* - This low level driver is OS independent. Allocating memory for
* the descriptor rings and buffers are not within the scope of
* this driver.
-@@ -1511,12 +1647,12 @@
+@@ -1511,12 +1657,12 @@
* - PHY access and control API.
* - Port control register configuration API.
* - Full control over Unicast and Multicast MAC configurations.
@@ -2700,7 +2463,7 @@
* User information regarding port configuration has to be set
* prior to calling the port initialization routine.
*
-@@ -1525,7 +1661,7 @@
+@@ -1525,7 +1671,7 @@
* access to DRAM and internal SRAM memory spaces.
*
* Driver ring initialization
@@ -2709,7 +2472,7 @@
* within the scope of this driver. Thus, the user is required to
* allocate memory for the descriptors ring and buffers. Those
* memory parameters are used by the Rx and Tx ring initialization
-@@ -1533,49 +1669,50 @@
+@@ -1533,49 +1679,50 @@
* of a ring.
* Note: Pay special attention to alignment issues when using
* cached descriptors/buffers. In this phase the driver store
@@ -2780,7 +2543,7 @@
* It is the user responsibility to return this resource back
* to the Rx descriptor ring to enable the reuse of this source.
* Return Rx resource is done using the eth_rx_return_buff API.
-@@ -1596,27 +1733,21 @@
+@@ -1596,27 +1743,21 @@
*
* EXTERNAL INTERFACE
*
@@ -2818,7 +2581,7 @@
* cmd_sts Tx/Rx descriptor command status.
* buf_ptr Tx/Rx descriptor buffer pointer.
* return_info Tx/Rx user resource return information.
-@@ -1625,70 +1756,44 @@
+@@ -1625,70 +1766,44 @@
/* defines */
/* SDMA command macros */
#define ETH_ENABLE_TX_QUEUE(eth_port) \
@@ -2906,7 +2669,7 @@
mp->port_rx_queue_command = 0;
mp->port_tx_queue_command = 0;
-@@ -1706,77 +1811,73 @@
+@@ -1706,77 +1821,73 @@
* eth_port_start - Start the Ethernet port activity.
*
* DESCRIPTION:
@@ -3024,7 +2787,7 @@
}
/*
-@@ -1786,29 +1887,29 @@
+@@ -1786,29 +1897,29 @@
* This function Set the port Ethernet MAC address.
*
* INPUT:
@@ -3063,7 +2826,7 @@
/* Accept frames of this address */
eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
-@@ -1817,29 +1918,64 @@
+@@ -1817,29 +1928,64 @@
}
/*
@@ -3136,7 +2899,7 @@
{
unsigned int unicast_reg;
unsigned int tbl_offset;
-@@ -1852,29 +1988,26 @@
+@@ -1852,29 +1998,26 @@
switch (option) {
case REJECT_MAC_ADDR:
@@ -3175,7 +2938,7 @@
break;
-@@ -1889,17 +2022,17 @@
+@@ -1889,17 +2032,17 @@
* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
*
* DESCRIPTION:
@@ -3198,7 +2961,7 @@
*/
static void eth_port_init_mac_tables(unsigned int eth_port_num)
{
-@@ -1907,18 +2040,16 @@
+@@ -1907,18 +2050,16 @@
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index <= 0xC; table_index += 4)
@@ -3223,7 +2986,7 @@
}
}
-@@ -1926,17 +2057,17 @@
+@@ -1926,17 +2067,17 @@
* eth_clear_mib_counters - Clear all MIB counters
*
* DESCRIPTION:
@@ -3246,7 +3009,7 @@
*
*/
static void eth_clear_mib_counters(unsigned int eth_port_num)
-@@ -1944,72 +2075,155 @@
+@@ -1944,72 +2085,155 @@
int i;
/* Perform dummy reads from MIB counters */
@@ -3260,8 +3023,8 @@
+static inline u32 read_mib(struct mv643xx_private *mp, int offset)
+{
+ return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
- }
-
++}
++
+static void eth_update_mib_counters(struct mv643xx_private *mp)
+{
+ struct mv643xx_mib_counters *p = &mp->mib_counters;
@@ -3285,8 +3048,8 @@
+ offset <= ETH_MIB_LATE_COLLISION;
+ offset += 4)
+ *(u32 *)((char *)p + offset) = read_mib(mp, offset);
-+}
-+
+ }
+
+/*
+ * ethernet_phy_detect - Detect whether a phy is present
+ *
@@ -3426,7 +3189,7 @@
}
/*
-@@ -2017,381 +2231,358 @@
+@@ -2017,381 +2241,358 @@
*
* DESCRIPTION:
* This routine resets the chip by aborting any SDMA engine activity and
@@ -3999,7 +3762,7 @@
unsigned int command_status;
/* Do not process Tx ring in case of Tx ring resource error */
-@@ -2403,39 +2594,24 @@
+@@ -2403,39 +2604,24 @@
tx_desc_used = mp->tx_used_desc_q;
current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
@@ -4044,7 +3807,7 @@
/* Check for ring index overlap in the Tx desc ring */
if (tx_desc_curr == tx_desc_used) {
-@@ -2452,62 +2628,55 @@
+@@ -2452,62 +2638,55 @@
*
* DESCRIPTION:
* This routine returns the transmitted packet information to the caller.
@@ -4130,7 +3893,7 @@
/* Pass the packet information to the caller */
p_pkt_info->cmd_sts = command_status;
-@@ -2515,7 +2684,7 @@
+@@ -2515,7 +2694,7 @@
mp->tx_skb[tx_desc_used] = NULL;
/* Update the next descriptor to release. */
@@ -4139,7 +3902,7 @@
/* Any Tx return cancels the Tx resource error status */
mp->tx_resource_err = 0;
-@@ -2527,30 +2696,30 @@
+@@ -2527,30 +2706,30 @@
* eth_port_receive - Get received information from Rx ring.
*
* DESCRIPTION:
@@ -4182,7 +3945,7 @@
unsigned int command_status;
/* Do not process Rx ring in case of Rx ring resource error */
-@@ -2565,6 +2734,7 @@
+@@ -2565,6 +2744,7 @@
/* The following parameters are used to save readings from memory */
command_status = p_rx_desc->cmd_sts;
@@ -4190,7 +3953,7 @@
/* Nothing to receive... */
if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
-@@ -2577,18 +2747,17 @@
+@@ -2577,18 +2757,17 @@
p_pkt_info->l4i_chk = p_rx_desc->buf_size;
/* Clean the return info field to indicate that the packet has been */
@@ -4211,7 +3974,7 @@
return ETH_OK;
}
-@@ -2596,27 +2765,27 @@
+@@ -2596,27 +2775,27 @@
* eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
*
* DESCRIPTION:
@@ -4249,7 +4012,7 @@
/* Get 'used' Rx descriptor */
used_rx_desc = mp->rx_used_desc_q;
-@@ -2627,20 +2796,240 @@
+@@ -2627,20 +2806,240 @@
mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
/* Flush the write pipe */
@@ -4496,8 +4259,8 @@
+};
+
+/************* End ethtool support *************************/
---- /home/sven/debian/kernel/test/kernel-patch-powerpc-2.6.11-2.6.11/tmp/kernel-source-2.6.11-powerpc/drivers/net/mv643xx_eth.h 2005-03-02 08:38:09.000000000 +0100
-+++ drivers/net/mv643xx_eth.h 2005-03-05 21:23:35.000000000 +0100
+--- kernel-source-2.6.11/drivers/net/mv643xx_eth.h 2005-03-02 08:38:09.000000000 +0100
++++ kernel-source-2.6.11-marvell/drivers/net/mv643xx_eth.h 2005-03-07 14:13:14.000000000 +0100
@@ -1,5 +1,5 @@
-#ifndef __MV64340_ETH_H__
-#define __MV64340_ETH_H__
@@ -5278,19 +5041,498 @@
-#endif /* __MV64340_ETH_H__ */
+#endif /* __MV643XX_ETH_H__ */
---- /home/sven/debian/kernel/test/kernel-patch-powerpc-2.6.11-2.6.11/tmp/kernel-source-2.6.11-powerpc/drivers/net/Kconfig 2005-03-02 08:38:25.000000000 +0100
-+++ drivers/net/Kconfig 2005-03-05 20:57:01.000000000 +0100
-@@ -2094,10 +2094,11 @@
+--- kernel-source-2.6.11/include/asm-ppc/mv64x60.h 2005-03-02 08:38:17.000000000 +0100
++++ kernel-source-2.6.11-marvell/include/asm-ppc/mv64x60.h 2005-03-07 14:18:27.000000000 +0100
+@@ -27,6 +27,19 @@
+ #include <asm/pci-bridge.h>
+ #include <asm/mv64x60_defs.h>
- config MV643XX_ETH
- tristate "MV-643XX Ethernet support"
-- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX
-+ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || PPC_CHRP
- help
- This driver supports the gigabit Ethernet on the Marvell MV643XX
-- chipset which is used in the Momenco Ocelot C and Jaguar ATX.
-+ chipset which is used in the Momenco Ocelot C and Jaguar ATX and
-+ Pegasos II, amongst other PPC and MIPS boards.
++/*
++ * return 1 if you are on a Pegasos II, 0 otherwise
++ * this code is useful to execute the correct code
++ * on the correct machine
++ *
++*/
++#if defined(CONFIG_PPC_MULTIPLATFORM)
++extern inline int mv64360_ispegasos2(void)
++{
++ return ((_machine == _MACH_chrp) && (_chrp_type == _CHRP_Pegasos)) ? 1 : 0;
++}
++#endif
++
+ extern u8 mv64x60_pci_exclude_bridge;
- config MV643XX_ETH_0
- bool "MV-643XX Port 0"
+ extern spinlock_t mv64x60_lock;
+--- kernel-source-2.6.11/include/linux/mv643xx.h 2005-03-02 08:38:18.000000000 +0100
++++ kernel-source-2.6.11-marvell/include/linux/mv643xx.h 2005-03-07 14:13:14.000000000 +0100
+@@ -1,5 +1,5 @@
+ /*
+- * mv64340.h - MV-64340 Internal registers definition file.
++ * mv643xx.h - MV-643XX Internal registers definition file.
+ *
+ * Copyright 2002 Momentum Computer, Inc.
+ * Author: Matthew Dharm <mdharm@momenco.com>
+@@ -10,8 +10,8 @@
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+-#ifndef __ASM_MV64340_H
+-#define __ASM_MV64340_H
++#ifndef __ASM_MV643XX_H
++#define __ASM_MV643XX_H
+
+ #ifdef __MIPS__
+ #include <asm/addrspace.h>
+@@ -662,116 +662,119 @@
+ /* Ethernet Unit Registers */
+ /****************************************/
+
+-#define MV64340_ETH_PHY_ADDR_REG 0x2000
+-#define MV64340_ETH_SMI_REG 0x2004
+-#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
+-#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c
+-#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
+-#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
+-#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc
+-#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094
+-#define MV64340_ETH_BAR_0 0x2200
+-#define MV64340_ETH_BAR_1 0x2208
+-#define MV64340_ETH_BAR_2 0x2210
+-#define MV64340_ETH_BAR_3 0x2218
+-#define MV64340_ETH_BAR_4 0x2220
+-#define MV64340_ETH_BAR_5 0x2228
+-#define MV64340_ETH_SIZE_REG_0 0x2204
+-#define MV64340_ETH_SIZE_REG_1 0x220c
+-#define MV64340_ETH_SIZE_REG_2 0x2214
+-#define MV64340_ETH_SIZE_REG_3 0x221c
+-#define MV64340_ETH_SIZE_REG_4 0x2224
+-#define MV64340_ETH_SIZE_REG_5 0x222c
+-#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230
+-#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
+-#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290
+-#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
+-#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
+-#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
+-#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
+-#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
+-#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
+-#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
+-#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
+-#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10))
+-#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10))
+-#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10))
+-#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10))
+-#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10))
+-#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10))
+-#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10))
+-#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
+-#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
+-#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
+-#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
+-#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
+-#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
+-#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
+-#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
+-#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
+-#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
+-#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
+-#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
+-#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
+-#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
+-#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
+-#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
++#define MV643XX_ETH_SHARED_REGS 0x2000
++#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
++
++#define MV643XX_ETH_PHY_ADDR_REG 0x2000
++#define MV643XX_ETH_SMI_REG 0x2004
++#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
++#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
++#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
++#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
++#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
++#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
++#define MV643XX_ETH_BAR_0 0x2200
++#define MV643XX_ETH_BAR_1 0x2208
++#define MV643XX_ETH_BAR_2 0x2210
++#define MV643XX_ETH_BAR_3 0x2218
++#define MV643XX_ETH_BAR_4 0x2220
++#define MV643XX_ETH_BAR_5 0x2228
++#define MV643XX_ETH_SIZE_REG_0 0x2204
++#define MV643XX_ETH_SIZE_REG_1 0x220c
++#define MV643XX_ETH_SIZE_REG_2 0x2214
++#define MV643XX_ETH_SIZE_REG_3 0x221c
++#define MV643XX_ETH_SIZE_REG_4 0x2224
++#define MV643XX_ETH_SIZE_REG_5 0x222c
++#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
++#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
++#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
++#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
++#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
++#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
++#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
++#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
++#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
++#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
++#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
++#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
++#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
++#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
++#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
++#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
++#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
++#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
++#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
++#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
++#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
++#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
++#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
++#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
++#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
++#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
++#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
++#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
++#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
++#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
++#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
++#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
+
+ /*******************************************/
+ /* CUNIT Registers */
+@@ -1085,4 +1088,221 @@
+ u32 brg_clk_freq;
+ };
+
+-#endif /* __ASM_MV64340_H */
++/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
++#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
++#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
++#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
++#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
++#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
++#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
++#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
++
++#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_UNICAST_NORMAL_MODE | \
++ MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
++ MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
++ MV643XX_ETH_RECEIVE_BC_IF_IP | \
++ MV643XX_ETH_RECEIVE_BC_IF_ARP | \
++ MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
++ MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
++ MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
++
++/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
++#define MV643XX_ETH_CLASSIFY_EN (1<<0)
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
++#define MV643XX_ETH_PARTITION_DISABLE 0
++#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
++
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
++ MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
++ MV643XX_ETH_PARTITION_DISABLE
++
++/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
++#define MV643XX_ETH_RIFB (1<<0)
++#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
++#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
++#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
++#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
++#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
++#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
++#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
++#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
++#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
++#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
++#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
++#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
++#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
++#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
++
++#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
++
++#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
++ MV643XX_ETH_IPG_INT_RX(0) | \
++ MV643XX_ETH_TX_BURST_SIZE_4_64BIT
++
++/* These macros describe Ethernet Port serial control reg (PSCR) bits */
++#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
++#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
++#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
++#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
++#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
++#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
++#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
++#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
++#define MV643XX_ETH_FORCE_LINK_FAIL 0
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
++#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
++#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
++#define MV643XX_ETH_DTE_ADV_0 0
++#define MV643XX_ETH_DTE_ADV_1 (1<<14)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
++#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
++#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
++#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
++#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
++#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
++#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
++#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
++#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
++#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
++#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
++#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
++#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
++#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
++#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
++#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
++#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
++
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
++ MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
++ MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
++ MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
++ (1<<9) /* reserved */ | \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
++ MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
++ MV643XX_ETH_DTE_ADV_0 | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
++ MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
++ MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
++ MV643XX_ETH_CLR_EXT_LOOPBACK | \
++ MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
++ MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
++
++/* These macros describe Ethernet Serial Status reg (PSR) bits */
++#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
++#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
++#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
++#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
++#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
++#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
++/* PSR bit 6 is undocumented */
++#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
++#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
++#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
++#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
++/* PSR bits 11-31 are reserved */
++
++#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
++#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
++
++#define MV643XX_ETH_DESC_SIZE 64
++
++#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
++#define MV643XX_ETH_NAME "mv643xx_eth"
++
++struct mv643xx_eth_platform_data {
++ /*
++ * Non-values for mac_addr, phy_addr, port_config, etc.
++ * override the default value. Setting the corresponding
++ * force_* field, causes the default value to be overridden
++ * even when zero.
++ */
++ unsigned int force_phy_addr:1;
++ unsigned int force_port_config:1;
++ unsigned int force_port_config_extend:1;
++ unsigned int force_port_sdma_config:1;
++ unsigned int force_port_serial_control:1;
++ int phy_addr;
++ char *mac_addr; /* pointer to mac address */
++ u32 port_config;
++ u32 port_config_extend;
++ u32 port_sdma_config;
++ u32 port_serial_control;
++ u32 tx_queue_size;
++ u32 rx_queue_size;
++ u32 tx_sram_addr;
++ u32 tx_sram_size;
++ u32 rx_sram_addr;
++ u32 rx_sram_size;
++};
++
++#endif /* __ASM_MV643XX_H */