r2724 - in trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian: . patches patches/series
Sven Luther
luther@costa.debian.org
Wed, 16 Mar 2005 11:23:02 +0100
Author: luther
Date: 2005-03-16 11:22:58 +0100 (Wed, 16 Mar 2005)
New Revision: 2724
Added:
trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-enet.dpatch
trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-eth-pegasos.dpatch
trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/series/2.6.10-7
Modified:
trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/changelog
Log:
Replaced the marvell gigabit ethernet driver with the backported version.
Modified: trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/changelog
===================================================================
--- trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/changelog 2005-03-16 06:46:06 UTC (rev 2723)
+++ trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/changelog 2005-03-16 10:22:58 UTC (rev 2724)
@@ -1,3 +1,10 @@
+kernel-source-2.6.10 (2.6.10-7) UNRELEASED; urgency=low
+
+ * [powerpc] replaced pegasos marvell gigabit ethernet driver by the backported
+ version (Sven Luther)
+
+ -- Sven Luther <luther@debian.org> Wed, 16 Mar 2005 11:20:00 +0100
+
kernel-source-2.6.10 (2.6.10-6) unstable; urgency=low
* Updated kernel-tree description from Martin F Krafft
Copied: trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-enet.dpatch (from rev 2710, trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-mv643xx-enet.dpatch)
===================================================================
--- trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-mv643xx-enet.dpatch 2005-03-14 13:20:53 UTC (rev 2710)
+++ trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-enet.dpatch 2005-03-16 10:22:58 UTC (rev 2724)
@@ -0,0 +1,6634 @@
+#! /bin/sh -e
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Description: Cleans arch-dependency of mv643xx_eth driver.
+## DP: Patch authors: Dale Farnsworth <dale@farnsworth.org>
+## DP: Upstream status: planned for 2.6.12.
+## DP: BK URL: bk://dfarnsworth.bkbits.net/linux-2.5-mv643xx-enet
+
+. $(dirname $0)/DPATCH
+
+@DPATCH@
+diff -urN linux-2.6.10/drivers/net/Kconfig linux-2.6.10-marvell/drivers/net/Kconfig
+--- linux-2.6.10/drivers/net/Kconfig 2004-12-24 22:35:25.000000000 +0100
++++ linux-2.6.10-marvell/drivers/net/Kconfig 2005-03-16 09:23:27.824605048 +0100
+@@ -2092,10 +2092,11 @@
+
+ config MV643XX_ETH
+ tristate "MV-643XX Ethernet support"
+- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX
++ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || PPC_MULTIPLATFORM
+ help
+ This driver supports the gigabit Ethernet on the Marvell MV643XX
+- chipset which is used in the Momenco Ocelot C and Jaguar ATX.
++ chipset which is used in the Momenco Ocelot C and Jaguar ATX and
++ Pegasos II, amongst other PPC and MIPS boards.
+
+ config MV643XX_ETH_0
+ bool "MV-643XX Port 0"
+diff -urN linux-2.6.10/drivers/net/mv643xx_eth.c linux-2.6.10-marvell/drivers/net/mv643xx_eth.c
+--- linux-2.6.10/drivers/net/mv643xx_eth.c 2004-12-24 22:34:31.000000000 +0100
++++ linux-2.6.10-marvell/drivers/net/mv643xx_eth.c 2005-03-16 09:23:27.000000000 +0100
+@@ -1,5 +1,5 @@
+ /*
+- * drivers/net/mv64340_eth.c - Driver for MV64340X ethernet ports
++ * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
+ * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
+ *
+ * Based on the 64360 driver from:
+@@ -10,6 +10,12 @@
+ *
+ * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
+ *
++ * Copyright (C) 2004-2005 MontaVista Software, Inc.
++ * Dale Farnsworth <dale@farnsworth.org>
++ *
++ * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
++ * <sjhill@realitydiluted.com>
++ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+@@ -24,80 +30,100 @@
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+-#include <linux/config.h>
+-#include <linux/version.h>
+-#include <linux/module.h>
+-#include <linux/kernel.h>
+-#include <linux/config.h>
+-#include <linux/sched.h>
+-#include <linux/ptrace.h>
+-#include <linux/fcntl.h>
+-#include <linux/ioport.h>
+-#include <linux/interrupt.h>
+-#include <linux/slab.h>
+-#include <linux/string.h>
+-#include <linux/errno.h>
+-#include <linux/ip.h>
+ #include <linux/init.h>
+-#include <linux/in.h>
+-#include <linux/pci.h>
+-#include <linux/workqueue.h>
+-#include <asm/smp.h>
+-#include <linux/skbuff.h>
++#include <linux/dma-mapping.h>
+ #include <linux/tcp.h>
+-#include <linux/netdevice.h>
++#include <linux/udp.h>
+ #include <linux/etherdevice.h>
+-#include <net/ip.h>
+
+ #include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/ethtool.h>
+ #include <asm/io.h>
+ #include <asm/types.h>
+ #include <asm/pgtable.h>
+ #include <asm/system.h>
++#include <asm/delay.h>
+ #include "mv643xx_eth.h"
+
+ /*
+- * The first part is the high level driver of the gigE ethernet ports.
++ * The first part is the high level driver of the gigE ethernet ports.
+ */
+
+-/* Definition for configuring driver */
+-#undef MV64340_RX_QUEUE_FILL_ON_TASK
+-
+ /* Constants */
+-#define EXTRA_BYTES 32
+-#define WRAP ETH_HLEN + 2 + 4 + 16
+-#define BUFFER_MTU dev->mtu + WRAP
++#define VLAN_HLEN 4
++#define FCS_LEN 4
++#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
++#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
++
+ #define INT_CAUSE_UNMASK_ALL 0x0007ffff
+ #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
+-#ifdef MV64340_RX_FILL_ON_TASK
++#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
+ #define INT_CAUSE_MASK_ALL 0x00000000
+ #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
+ #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
+ #endif
+
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
++#else
++#define MAX_DESCS_PER_SKB 1
++#endif
++
++#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
++#define PHY_WAIT_MICRO_SECONDS 10
++
+ /* Static function declarations */
+-static int mv64340_eth_real_open(struct net_device *);
+-static int mv64340_eth_real_stop(struct net_device *);
+-static int mv64340_eth_change_mtu(struct net_device *, int);
+-static struct net_device_stats *mv64340_eth_get_stats(struct net_device *);
++static int eth_port_link_is_up(unsigned int eth_port_num);
++static void eth_port_uc_addr_get(struct net_device *dev,
++ unsigned char *MacAddr);
++static int mv643xx_eth_real_open(struct net_device *);
++static int mv643xx_eth_real_stop(struct net_device *);
++static int mv643xx_eth_change_mtu(struct net_device *, int);
++static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
+ static void eth_port_init_mac_tables(unsigned int eth_port_num);
+-#ifdef MV64340_NAPI
+-static int mv64340_poll(struct net_device *dev, int *budget);
++#ifdef MV643XX_NAPI
++static int mv643xx_poll(struct net_device *dev, int *budget);
+ #endif
++static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
++static int ethernet_phy_detect(unsigned int eth_port_num);
++static struct ethtool_ops mv643xx_ethtool_ops;
++
++static char mv643xx_driver_name[] = "mv643xx_eth";
++static char mv643xx_driver_version[] = "1.0";
++
++static void __iomem *mv643xx_eth_shared_base;
++
++/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
++static spinlock_t mv643xx_eth_phy_lock = SPIN_LOCK_UNLOCKED;
++
++static inline u32 mv_read(int offset)
++{
++ void *__iomem reg_base;
++
++ reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
++
++ return readl(reg_base + offset);
++}
++
++static inline void mv_write(int offset, u32 data)
++{
++ void * __iomem reg_base;
+
+-unsigned char prom_mac_addr_base[6];
+-unsigned long mv64340_sram_base;
++ reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
++ writel(data, reg_base + offset);
++}
+
+ /*
+ * Changes MTU (maximum transfer unit) of the gigabit ethenret port
+ *
+- * Input : pointer to ethernet interface network device structure
+- * new mtu size
+- * Output : 0 upon success, -EINVAL upon failure
++ * Input : pointer to ethernet interface network device structure
++ * new mtu size
++ * Output : 0 upon success, -EINVAL upon failure
+ */
+-static int mv64340_eth_change_mtu(struct net_device *dev, int new_mtu)
++static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&mp->lock, flags);
+@@ -108,21 +134,21 @@
+ }
+
+ dev->mtu = new_mtu;
+- /*
++ /*
+ * Stop then re-open the interface. This will allocate RX skb's with
+ * the new MTU.
+ * There is a possible danger that the open will not successed, due
+ * to memory is full, which might fail the open function.
+ */
+ if (netif_running(dev)) {
+- if (mv64340_eth_real_stop(dev))
++ if (mv643xx_eth_real_stop(dev))
+ printk(KERN_ERR
+- "%s: Fatal error on stopping device\n",
+- dev->name);
+- if (mv64340_eth_real_open(dev))
++ "%s: Fatal error on stopping device\n",
++ dev->name);
++ if (mv643xx_eth_real_open(dev))
+ printk(KERN_ERR
+- "%s: Fatal error on opening device\n",
+- dev->name);
++ "%s: Fatal error on opening device\n",
++ dev->name);
+ }
+
+ spin_unlock_irqrestore(&mp->lock, flags);
+@@ -130,17 +156,17 @@
+ }
+
+ /*
+- * mv64340_eth_rx_task
+- *
++ * mv643xx_eth_rx_task
++ *
+ * Fills / refills RX queue on a certain gigabit ethernet port
+ *
+- * Input : pointer to ethernet interface network device structure
+- * Output : N/A
++ * Input : pointer to ethernet interface network device structure
++ * Output : N/A
+ */
+-static void mv64340_eth_rx_task(void *data)
++static void mv643xx_eth_rx_task(void *data)
+ {
+- struct net_device *dev = (struct net_device *) data;
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct net_device *dev = (struct net_device *)data;
++ struct mv643xx_private *mp = netdev_priv(dev);
+ struct pkt_info pkt_info;
+ struct sk_buff *skb;
+
+@@ -148,28 +174,18 @@
+ panic("%s: Error in test_set_bit / clear_bit", dev->name);
+
+ while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
+- /* The +8 for buffer allignment and another 32 byte extra */
+-
+- skb = dev_alloc_skb(BUFFER_MTU + 8 + EXTRA_BYTES);
++ skb = dev_alloc_skb(RX_SKB_SIZE);
+ if (!skb)
+- /* Better luck next time */
+ break;
+ mp->rx_ring_skbs++;
+ pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
+- pkt_info.byte_cnt = dev->mtu + ETH_HLEN + 4 + 2 + EXTRA_BYTES;
+- /* Allign buffer to 8 bytes */
+- if (pkt_info.byte_cnt & ~0x7) {
+- pkt_info.byte_cnt &= ~0x7;
+- pkt_info.byte_cnt += 8;
+- }
+- pkt_info.buf_ptr =
+- pci_map_single(0, skb->data,
+- dev->mtu + ETH_HLEN + 4 + 2 + EXTRA_BYTES,
+- PCI_DMA_FROMDEVICE);
++ pkt_info.byte_cnt = RX_SKB_SIZE;
++ pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
++ DMA_FROM_DEVICE);
+ pkt_info.return_info = skb;
+ if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
+ printk(KERN_ERR
+- "%s: Error allocating RX Ring\n", dev->name);
++ "%s: Error allocating RX Ring\n", dev->name);
+ break;
+ }
+ skb_reserve(skb, 2);
+@@ -186,46 +202,45 @@
+ add_timer(&mp->timeout);
+ mp->rx_timer_flag = 1;
+ }
+-#if MV64340_RX_QUEUE_FILL_ON_TASK
++#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
+ else {
+ /* Return interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(mp->port_num),
+- INT_CAUSE_UNMASK_ALL);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
++ INT_CAUSE_UNMASK_ALL);
+ }
+ #endif
+ }
+
+ /*
+- * mv64340_eth_rx_task_timer_wrapper
+- *
++ * mv643xx_eth_rx_task_timer_wrapper
++ *
+ * Timer routine to wake up RX queue filling task. This function is
+ * used only in case the RX queue is empty, and all alloc_skb has
+ * failed (due to out of memory event).
+ *
+- * Input : pointer to ethernet interface network device structure
+- * Output : N/A
++ * Input : pointer to ethernet interface network device structure
++ * Output : N/A
+ */
+-static void mv64340_eth_rx_task_timer_wrapper(unsigned long data)
++static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
+ {
+- struct net_device *dev = (struct net_device *) data;
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct net_device *dev = (struct net_device *)data;
++ struct mv643xx_private *mp = netdev_priv(dev);
+
+ mp->rx_timer_flag = 0;
+- mv64340_eth_rx_task((void *) data);
++ mv643xx_eth_rx_task((void *)data);
+ }
+
+-
+ /*
+- * mv64340_eth_update_mac_address
+- *
++ * mv643xx_eth_update_mac_address
++ *
+ * Update the MAC address of the port in the address table
+ *
+- * Input : pointer to ethernet interface network device structure
+- * Output : N/A
++ * Input : pointer to ethernet interface network device structure
++ * Output : N/A
+ */
+-static void mv64340_eth_update_mac_address(struct net_device *dev)
++static void mv643xx_eth_update_mac_address(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+
+ eth_port_init_mac_tables(port_num);
+@@ -234,64 +249,59 @@
+ }
+
+ /*
+- * mv64340_eth_set_rx_mode
+- *
++ * mv643xx_eth_set_rx_mode
++ *
+ * Change from promiscuos to regular rx mode
+ *
+- * Input : pointer to ethernet interface network device structure
+- * Output : N/A
++ * Input : pointer to ethernet interface network device structure
++ * Output : N/A
+ */
+-static void mv64340_eth_set_rx_mode(struct net_device *dev)
++static void mv643xx_eth_set_rx_mode(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
++ u32 config_reg;
+
+- if (dev->flags & IFF_PROMISC) {
+- ethernet_set_config_reg
+- (mp->port_num,
+- ethernet_get_config_reg(mp->port_num) |
+- ETH_UNICAST_PROMISCUOUS_MODE);
+- } else {
+- ethernet_set_config_reg
+- (mp->port_num,
+- ethernet_get_config_reg(mp->port_num) &
+- ~(unsigned int) ETH_UNICAST_PROMISCUOUS_MODE);
+- }
++ config_reg = ethernet_get_config_reg(mp->port_num);
++ if (dev->flags & IFF_PROMISC)
++ config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
++ else
++ config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
++ ethernet_set_config_reg(mp->port_num, config_reg);
+ }
+
+-
+ /*
+- * mv64340_eth_set_mac_address
+- *
++ * mv643xx_eth_set_mac_address
++ *
+ * Change the interface's mac address.
+ * No special hardware thing should be done because interface is always
+ * put in promiscuous mode.
+ *
+- * Input : pointer to ethernet interface network device structure and
+- * a pointer to the designated entry to be added to the cache.
+- * Output : zero upon success, negative upon failure
++ * Input : pointer to ethernet interface network device structure and
++ * a pointer to the designated entry to be added to the cache.
++ * Output : zero upon success, negative upon failure
+ */
+-static int mv64340_eth_set_mac_address(struct net_device *dev, void *addr)
++static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
+ {
+ int i;
+
+ for (i = 0; i < 6; i++)
+ /* +2 is for the offset of the HW addr type */
+- dev->dev_addr[i] = ((unsigned char *) addr)[i + 2];
+- mv64340_eth_update_mac_address(dev);
++ dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
++ mv643xx_eth_update_mac_address(dev);
+ return 0;
+ }
+
+ /*
+- * mv64340_eth_tx_timeout
+- *
++ * mv643xx_eth_tx_timeout
++ *
+ * Called upon a timeout on transmitting a packet
+ *
+- * Input : pointer to ethernet interface network device structure.
+- * Output : N/A
++ * Input : pointer to ethernet interface network device structure.
++ * Output : N/A
+ */
+-static void mv64340_eth_tx_timeout(struct net_device *dev)
++static void mv643xx_eth_tx_timeout(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+
+ printk(KERN_INFO "%s: TX timeout ", dev->name);
+
+@@ -300,31 +310,31 @@
+ }
+
+ /*
+- * mv64340_eth_tx_timeout_task
++ * mv643xx_eth_tx_timeout_task
+ *
+ * Actual routine to reset the adapter when a timeout on Tx has occurred
+ */
+-static void mv64340_eth_tx_timeout_task(struct net_device *dev)
++static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+
+- netif_device_detach(dev);
+- eth_port_reset(mp->port_num);
+- eth_port_start(mp);
+- netif_device_attach(dev);
++ netif_device_detach(dev);
++ eth_port_reset(mp->port_num);
++ eth_port_start(mp);
++ netif_device_attach(dev);
+ }
+
+ /*
+- * mv64340_eth_free_tx_queue
++ * mv643xx_eth_free_tx_queue
+ *
+- * Input : dev - a pointer to the required interface
++ * Input : dev - a pointer to the required interface
+ *
+- * Output : 0 if was able to release skb , nonzero otherwise
++ * Output : 0 if was able to release skb , nonzero otherwise
+ */
+-static int mv64340_eth_free_tx_queue(struct net_device *dev,
+- unsigned int eth_int_cause_ext)
++static int mv643xx_eth_free_tx_queue(struct net_device *dev,
++ unsigned int eth_int_cause_ext)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ struct pkt_info pkt_info;
+ int released = 1;
+@@ -341,33 +351,36 @@
+ stats->tx_errors++;
+ }
+
+- /*
++ /*
+ * If return_info is different than 0, release the skb.
+ * The case where return_info is not 0 is only in case
+ * when transmitted a scatter/gather packet, where only
+ * last skb releases the whole chain.
+ */
+ if (pkt_info.return_info) {
+- dev_kfree_skb_irq((struct sk_buff *)
+- pkt_info.return_info);
+- released = 0;
+ if (skb_shinfo(pkt_info.return_info)->nr_frags)
+- pci_unmap_page(NULL, pkt_info.buf_ptr,
+- pkt_info.byte_cnt, PCI_DMA_TODEVICE);
++ dma_unmap_page(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt,
++ DMA_TO_DEVICE);
++ else
++ dma_unmap_single(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt,
++ DMA_TO_DEVICE);
+
+- if (mp->tx_ring_skbs != 1)
+- mp->tx_ring_skbs--;
+- } else
+- pci_unmap_page(NULL, pkt_info.buf_ptr,
+- pkt_info.byte_cnt, PCI_DMA_TODEVICE);
+-
+- /*
+- * Decrement the number of outstanding skbs counter on
+- * the TX queue.
+- */
+- if (mp->tx_ring_skbs == 0)
+- panic("ERROR - TX outstanding SKBs counter is corrupted");
++ dev_kfree_skb_irq(pkt_info.return_info);
++ released = 0;
+
++ /*
++ * Decrement the number of outstanding skbs counter on
++ * the TX queue.
++ */
++ if (mp->tx_ring_skbs == 0)
++ panic("ERROR - TX outstanding SKBs"
++ " counter is corrupted");
++ mp->tx_ring_skbs--;
++ } else
++ dma_unmap_page(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt, DMA_TO_DEVICE);
+ }
+
+ spin_unlock(&mp->lock);
+@@ -376,60 +389,59 @@
+ }
+
+ /*
+- * mv64340_eth_receive
++ * mv643xx_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+- * Input : dev - a pointer to the required interface
+- * max - maximum number to receive (0 means unlimted)
++ * Input : dev - a pointer to the required interface
++ * max - maximum number to receive (0 means unlimted)
+ *
+- * Output : number of served packets
++ * Output : number of served packets
+ */
+-#ifdef MV64340_NAPI
+-static int mv64340_eth_receive_queue(struct net_device *dev, unsigned int max,
+- int budget)
++#ifdef MV643XX_NAPI
++static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
+ #else
+-static int mv64340_eth_receive_queue(struct net_device *dev, unsigned int max)
++static int mv643xx_eth_receive_queue(struct net_device *dev)
+ #endif
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ unsigned int received_packets = 0;
+ struct sk_buff *skb;
+ struct pkt_info pkt_info;
+
+-#ifdef MV64340_NAPI
++#ifdef MV643XX_NAPI
+ while (eth_port_receive(mp, &pkt_info) == ETH_OK && budget > 0) {
+ #else
+- while ((--max) && eth_port_receive(mp, &pkt_info) == ETH_OK) {
++ while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
+ #endif
+ mp->rx_ring_skbs--;
+ received_packets++;
+-#ifdef MV64340_NAPI
++#ifdef MV643XX_NAPI
+ budget--;
+ #endif
+ /* Update statistics. Note byte count includes 4 byte CRC count */
+ stats->rx_packets++;
+ stats->rx_bytes += pkt_info.byte_cnt;
+- skb = (struct sk_buff *) pkt_info.return_info;
++ skb = pkt_info.return_info;
+ /*
+ * In case received a packet without first / last bits on OR
+ * the error summary bit is on, the packets needs to be dropeed.
+ */
+ if (((pkt_info.cmd_sts
+- & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
++ & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
++ (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
++ || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+ stats->rx_dropped++;
+ if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
+- ETH_RX_LAST_DESC)) !=
+- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
++ ETH_RX_LAST_DESC)) !=
++ (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
+ if (net_ratelimit())
+ printk(KERN_ERR
+- "%s: Received packet spread on multiple"
+- " descriptors\n",
+- dev->name);
++ "%s: Received packet spread "
++ "on multiple descriptors\n",
++ dev->name);
+ }
+ if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
+ stats->rx_errors++;
+@@ -445,11 +457,11 @@
+
+ if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+- skb->csum = htons((pkt_info.cmd_sts
+- & 0x0007fff8) >> 3);
++ skb->csum = htons(
++ (pkt_info.cmd_sts & 0x0007fff8) >> 3);
+ }
+ skb->protocol = eth_type_trans(skb, dev);
+-#ifdef MV64340_NAPI
++#ifdef MV643XX_NAPI
+ netif_receive_skb(skb);
+ #else
+ netif_rx(skb);
+@@ -461,74 +473,74 @@
+ }
+
+ /*
+- * mv64340_eth_int_handler
++ * mv643xx_eth_int_handler
+ *
+ * Main interrupt handler for the gigbit ethernet ports
+ *
+- * Input : irq - irq number (not used)
+- * dev_id - a pointer to the required interface's data structure
+- * regs - not used
+- * Output : N/A
++ * Input : irq - irq number (not used)
++ * dev_id - a pointer to the required interface's data structure
++ * regs - not used
++ * Output : N/A
+ */
+
+-static irqreturn_t mv64340_eth_int_handler(int irq, void *dev_id,
+- struct pt_regs *regs)
++static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
++ struct pt_regs *regs)
+ {
+- struct net_device *dev = (struct net_device *) dev_id;
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct net_device *dev = (struct net_device *)dev_id;
++ struct mv643xx_private *mp = netdev_priv(dev);
+ u32 eth_int_cause, eth_int_cause_ext = 0;
+ unsigned int port_num = mp->port_num;
+
+ /* Read interrupt cause registers */
+- eth_int_cause = MV_READ(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num)) &
+- INT_CAUSE_UNMASK_ALL;
++ eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
++ INT_CAUSE_UNMASK_ALL;
+
+ if (eth_int_cause & BIT1)
+- eth_int_cause_ext =
+- MV_READ(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
+- INT_CAUSE_UNMASK_ALL_EXT;
++ eth_int_cause_ext = mv_read(
++ MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
++ INT_CAUSE_UNMASK_ALL_EXT;
+
+-#ifdef MV64340_NAPI
++#ifdef MV643XX_NAPI
+ if (!(eth_int_cause & 0x0007fffd)) {
+- /* Dont ack the Rx interrupt */
++ /* Dont ack the Rx interrupt */
+ #endif
+ /*
+- * Clear specific ethernet port intrerrupt registers by
++ * Clear specific ethernet port intrerrupt registers by
+ * acknowleding relevant bits.
+ */
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num),
+- ~eth_int_cause);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
++ ~eth_int_cause);
+ if (eth_int_cause_ext != 0x0)
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
+- ~eth_int_cause_ext);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
++ (port_num), ~eth_int_cause_ext);
+
+ /* UDP change : We may need this */
+ if ((eth_int_cause_ext & 0x0000ffff) &&
+- (mv64340_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
+- (MV64340_TX_QUEUE_SIZE > mp->tx_ring_skbs + 1))
+- netif_wake_queue(dev);
+-#ifdef MV64340_NAPI
++ (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
++ (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
++ netif_wake_queue(dev);
++#ifdef MV643XX_NAPI
+ } else {
+ if (netif_rx_schedule_prep(dev)) {
+ /* Mask all the interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),0);
+- MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
++ (port_num), 0);
+ __netif_rx_schedule(dev);
+ }
+ #else
+- {
+ if (eth_int_cause & (BIT2 | BIT11))
+- mv64340_eth_receive_queue(dev, 0);
++ mv643xx_eth_receive_queue(dev, 0);
+
+ /*
+- * After forwarded received packets to upper layer, add a task
++ * After forwarded received packets to upper layer, add a task
+ * in an interrupts enabled context that refills the RX ring
+ * with skb's.
+ */
+-#if MV64340_RX_QUEUE_FILL_ON_TASK
++#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
+ /* Unmask all interrupts on ethernet port */
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
+- INT_CAUSE_MASK_ALL);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
++ INT_CAUSE_MASK_ALL);
+ queue_task(&mp->rx_task, &tq_immediate);
+ mark_bh(IMMEDIATE_BH);
+ #else
+@@ -538,25 +550,15 @@
+ }
+ /* PHY status changed */
+ if (eth_int_cause_ext & (BIT16 | BIT20)) {
+- unsigned int phy_reg_data;
+-
+- /* Check Link status on ethernet port */
+- eth_port_read_smi_reg(port_num, 1, &phy_reg_data);
+- if (!(phy_reg_data & 0x20)) {
+- netif_stop_queue(dev);
+- } else {
++ if (eth_port_link_is_up(port_num)) {
++ netif_carrier_on(dev);
+ netif_wake_queue(dev);
+-
+- /*
+- * Start all TX queues on ethernet port. This is good in
+- * case of previous packets where not transmitted, due
+- * to link down and this command re-enables all TX
+- * queues.
+- * Note that it is possible to get a TX resource error
+- * interrupt after issuing this, since not all TX queues
+- * are enabled, or has anything to send.
+- */
+- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 1);
++ /* Start TX queue */
++ mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
++ (port_num), 1);
++ } else {
++ netif_carrier_off(dev);
++ netif_stop_queue(dev);
+ }
+ }
+
+@@ -570,7 +572,7 @@
+ return IRQ_HANDLED;
+ }
+
+-#ifdef MV64340_COAL
++#ifdef MV643XX_COAL
+
+ /*
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+@@ -584,9 +586,9 @@
+ * , and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet port number
+- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
+- * unsigned int delay Delay in usec
++ * unsigned int eth_port_num Ethernet port number
++ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
++ * unsigned int delay Delay in usec
+ *
+ * OUTPUT:
+ * Interrupt coalescing mechanism value is set in MV-643xx chip.
+@@ -596,15 +598,15 @@
+ *
+ */
+ static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
+- unsigned int t_clk, unsigned int delay)
++ unsigned int t_clk, unsigned int delay)
+ {
+ unsigned int coal = ((t_clk / 1000000) * delay) / 64;
+
+ /* Set RX Coalescing mechanism */
+- MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num),
+- ((coal & 0x3fff) << 8) |
+- (MV_READ(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num))
+- & 0xffc000ff));
++ mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
++ ((coal & 0x3fff) << 8) |
++ (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
++ & 0xffc000ff));
+
+ return coal;
+ }
+@@ -618,13 +620,13 @@
+ * This parameter is a timeout counter, that counts in 64 t_clk
+ * chunks ; that when timeout event occurs a maskable interrupt
+ * occurs.
+- * The parameter is calculated using the t_cLK frequency of the
++ * The parameter is calculated using the t_cLK frequency of the
+ * MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet port number
+- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
+- * unsigned int delay Delay in uSeconds
++ * unsigned int eth_port_num Ethernet port number
++ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
++ * unsigned int delay Delay in uSeconds
+ *
+ * OUTPUT:
+ * Interrupt coalescing mechanism value is set in MV-643xx chip.
+@@ -634,48 +636,48 @@
+ *
+ */
+ static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
+- unsigned int t_clk, unsigned int delay)
++ unsigned int t_clk, unsigned int delay)
+ {
+ unsigned int coal;
+ coal = ((t_clk / 1000000) * delay) / 64;
+ /* Set TX Coalescing mechanism */
+- MV_WRITE(MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
+- coal << 4);
++ mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
++ coal << 4);
+ return coal;
+ }
+
+ /*
+- * mv64340_eth_open
++ * mv643xx_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+- * Input : a pointer to the network device structure
++ * Input : a pointer to the network device structure
+ *
+- * Output : zero of success , nonzero if fails.
++ * Output : zero of success , nonzero if fails.
+ */
+
+-static int mv64340_eth_open(struct net_device *dev)
++static int mv643xx_eth_open(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+- int err = err;
++ int err;
+
+ spin_lock_irq(&mp->lock);
+
+- err = request_irq(dev->irq, mv64340_eth_int_handler,
+- SA_INTERRUPT | SA_SAMPLE_RANDOM, dev->name, dev);
++ err = request_irq(dev->irq, mv643xx_eth_int_handler,
++ SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
+
+ if (err) {
+- printk(KERN_ERR "Can not assign IRQ number to MV64340_eth%d\n",
+- port_num);
++ printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
++ port_num);
+ err = -EAGAIN;
+ goto out;
+ }
+
+- if (mv64340_eth_real_open(dev)) {
++ if (mv643xx_eth_real_open(dev)) {
+ printk("%s: Error opening interface\n", dev->name);
+ err = -EBUSY;
+ goto out_free;
+@@ -698,66 +700,35 @@
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+- * This function prepares a Rx chained list of descriptors and packet
+- * buffers in a form of a ring. The routine must be called after port
+- * initialization routine and before port start routine.
+- * The Ethernet SDMA engine uses CPU bus addresses to access the various
+- * devices in the system (i.e. DRAM). This function uses the ethernet
+- * struct 'virtual to physical' routine (set by the user) to set the ring
+- * with physical addresses.
++ * This function prepares a Rx chained list of descriptors and packet
++ * buffers in a form of a ring. The routine must be called after port
++ * initialization routine and before port start routine.
++ * The Ethernet SDMA engine uses CPU bus addresses to access the various
++ * devices in the system (i.e. DRAM). This function uses the ethernet
++ * struct 'virtual to physical' routine (set by the user) to set the ring
++ * with physical addresses.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * int rx_desc_num Number of Rx descriptors
+- * int rx_buff_size Size of Rx buffer
+- * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
+- * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
+ *
+ * OUTPUT:
+- * The routine updates the Ethernet port control struct with information
+- * regarding the Rx descriptors and buffers.
++ * The routine updates the Ethernet port control struct with information
++ * regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+- * false if the given descriptors memory area is not aligned according to
+- * Ethernet SDMA specifications.
+- * true otherwise.
++ * None.
+ */
+-static int ether_init_rx_desc_ring(struct mv64340_private * mp,
+- unsigned long rx_buff_base_addr)
++static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
+ {
+- unsigned long buffer_addr = rx_buff_base_addr;
+ volatile struct eth_rx_desc *p_rx_desc;
+ int rx_desc_num = mp->rx_ring_size;
+- unsigned long rx_desc_base_addr = (unsigned long) mp->p_rx_desc_area;
+- int rx_buff_size = 1536; /* Dummy, will be replaced later */
+ int i;
+
+- p_rx_desc = (struct eth_rx_desc *) rx_desc_base_addr;
+-
+- /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+- if (rx_buff_base_addr & 0xf)
+- return 0;
+-
+- /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
+- if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+- return 0;
+-
+- /* Rx buffers must be 64-bit aligned. */
+- if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+- return 0;
+-
+- /* initialize the Rx descriptors ring */
++ /* initialize the next_desc_ptr links in the Rx descriptors ring */
++ p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
+ for (i = 0; i < rx_desc_num; i++) {
+- p_rx_desc[i].buf_size = rx_buff_size;
+- p_rx_desc[i].byte_cnt = 0x0000;
+- p_rx_desc[i].cmd_sts =
+- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+ p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
+ ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
+- p_rx_desc[i].buf_ptr = buffer_addr;
+-
+- mp->rx_skb[i] = NULL;
+- buffer_addr += rx_buff_size;
+ }
+
+ /* Save Rx desc pointer to driver struct. */
+@@ -766,293 +737,288 @@
+
+ mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
+
++ /* Add the queue to the list of RX queues of this port */
+ mp->port_rx_queue_command |= 1;
+-
+- return 1;
+ }
+
+ /*
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+- * This function prepares a Tx chained list of descriptors and packet
+- * buffers in a form of a ring. The routine must be called after port
+- * initialization routine and before port start routine.
+- * The Ethernet SDMA engine uses CPU bus addresses to access the various
+- * devices in the system (i.e. DRAM). This function uses the ethernet
+- * struct 'virtual to physical' routine (set by the user) to set the ring
+- * with physical addresses.
++ * This function prepares a Tx chained list of descriptors and packet
++ * buffers in a form of a ring. The routine must be called after port
++ * initialization routine and before port start routine.
++ * The Ethernet SDMA engine uses CPU bus addresses to access the various
++ * devices in the system (i.e. DRAM). This function uses the ethernet
++ * struct 'virtual to physical' routine (set by the user) to set the ring
++ * with physical addresses.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * int tx_desc_num Number of Tx descriptors
+- * int tx_buff_size Size of Tx buffer
+- * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
+ *
+ * OUTPUT:
+- * The routine updates the Ethernet port control struct with information
+- * regarding the Tx descriptors and buffers.
++ * The routine updates the Ethernet port control struct with information
++ * regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+- * false if the given descriptors memory area is not aligned according to
+- * Ethernet SDMA specifications.
+- * true otherwise.
++ * None.
+ */
+-static int ether_init_tx_desc_ring(struct mv64340_private *mp)
++static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
+ {
+- unsigned long tx_desc_base_addr = (unsigned long) mp->p_tx_desc_area;
+ int tx_desc_num = mp->tx_ring_size;
+ struct eth_tx_desc *p_tx_desc;
+ int i;
+
+- /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+- if (tx_desc_base_addr & 0xf)
+- return 0;
+-
+- /* save the first desc pointer to link with the last descriptor */
+- p_tx_desc = (struct eth_tx_desc *) tx_desc_base_addr;
+-
+- /* Initialize the Tx descriptors ring */
++ /* Initialize the next_desc_ptr links in the Tx descriptors ring */
++ p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
+ for (i = 0; i < tx_desc_num; i++) {
+- p_tx_desc[i].byte_cnt = 0x0000;
+- p_tx_desc[i].l4i_chk = 0x0000;
+- p_tx_desc[i].cmd_sts = 0x00000000;
+ p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
+ ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
+- p_tx_desc[i].buf_ptr = 0x00000000;
+- mp->tx_skb[i] = NULL;
+ }
+
+- /* Set Tx desc pointer in driver struct. */
+ mp->tx_curr_desc_q = 0;
+ mp->tx_used_desc_q = 0;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- mp->tx_first_desc_q = 0;
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ mp->tx_first_desc_q = 0;
+ #endif
+- /* Init Tx ring base and size parameters */
+- mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
++
++ mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
+
+ /* Add the queue to the list of Tx queues of this port */
+ mp->port_tx_queue_command |= 1;
+-
+- return 1;
+ }
+
+-/* Helper function for mv64340_eth_open */
+-static int mv64340_eth_real_open(struct net_device *dev)
++/* Helper function for mv643xx_eth_open */
++static int mv643xx_eth_real_open(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+- u32 phy_reg_data;
+ unsigned int size;
+
+ /* Stop RX Queues */
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
+- 0x0000ff00);
++ mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
+
+ /* Clear the ethernet port interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+
+ /* Unmask RX buffer and TX end interrupt */
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
+- INT_CAUSE_UNMASK_ALL);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
++ INT_CAUSE_UNMASK_ALL);
+
+ /* Unmask phy and link status changes interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
+- INT_CAUSE_UNMASK_ALL_EXT);
++ mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
++ INT_CAUSE_UNMASK_ALL_EXT);
+
+ /* Set the MAC Address */
+ memcpy(mp->port_mac_addr, dev->dev_addr, 6);
+
+ eth_port_init(mp);
+
+- INIT_WORK(&mp->rx_task, (void (*)(void *)) mv64340_eth_rx_task, dev);
++ INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
+
+ memset(&mp->timeout, 0, sizeof(struct timer_list));
+- mp->timeout.function = mv64340_eth_rx_task_timer_wrapper;
+- mp->timeout.data = (unsigned long) dev;
++ mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
++ mp->timeout.data = (unsigned long)dev;
+
+ mp->rx_task_busy = 0;
+ mp->rx_timer_flag = 0;
+
++ /* Allocate RX and TX skb rings */
++ mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
++ GFP_KERNEL);
++ if (!mp->rx_skb) {
++ printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
++ return -ENOMEM;
++ }
++ mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
++ GFP_KERNEL);
++ if (!mp->tx_skb) {
++ printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
++ kfree(mp->rx_skb);
++ return -ENOMEM;
++ }
++
+ /* Allocate TX ring */
+ mp->tx_ring_skbs = 0;
+- mp->tx_ring_size = MV64340_TX_QUEUE_SIZE;
+ size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
+ mp->tx_desc_area_size = size;
+
+- /* Assumes allocated ring is 16 bytes alligned */
+- mp->p_tx_desc_area = pci_alloc_consistent(NULL, size, &mp->tx_desc_dma);
++ if (mp->tx_sram_size) {
++ mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
++ mp->tx_sram_size);
++ mp->tx_desc_dma = mp->tx_sram_addr;
++ } else
++ mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
++ &mp->tx_desc_dma,
++ GFP_KERNEL);
++
+ if (!mp->p_tx_desc_area) {
+ printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
+- dev->name, size);
++ dev->name, size);
++ kfree(mp->rx_skb);
++ kfree(mp->tx_skb);
+ return -ENOMEM;
+ }
+- memset((void *) mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
++ BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
++ memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
+
+- /* Dummy will be replaced upon real tx */
+ ether_init_tx_desc_ring(mp);
+
+ /* Allocate RX ring */
+- /* Meantime RX Ring are fixed - but must be configurable by user */
+- mp->rx_ring_size = MV64340_RX_QUEUE_SIZE;
+ mp->rx_ring_skbs = 0;
+ size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
+ mp->rx_desc_area_size = size;
+
+- /* Assumes allocated ring is 16 bytes aligned */
+-
+- mp->p_rx_desc_area = pci_alloc_consistent(NULL, size, &mp->rx_desc_dma);
++ if (mp->rx_sram_size) {
++ mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
++ mp->rx_sram_size);
++ mp->rx_desc_dma = mp->rx_sram_addr;
++ } else
++ mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
++ &mp->rx_desc_dma,
++ GFP_KERNEL);
+
+ if (!mp->p_rx_desc_area) {
+ printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
+- dev->name, size);
++ dev->name, size);
+ printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
+- dev->name);
+- pci_free_consistent(0, mp->tx_desc_area_size,
+- (void *) mp->p_tx_desc_area,
+- mp->tx_desc_dma);
++ dev->name);
++ if (mp->rx_sram_size)
++ iounmap(mp->p_rx_desc_area);
++ else
++ dma_free_coherent(NULL, mp->tx_desc_area_size,
++ mp->p_tx_desc_area, mp->tx_desc_dma);
++ kfree(mp->rx_skb);
++ kfree(mp->tx_skb);
+ return -ENOMEM;
+ }
+- memset(mp->p_rx_desc_area, 0, size);
++ memset((void *)mp->p_rx_desc_area, 0, size);
+
+- if (!(ether_init_rx_desc_ring(mp, 0)))
+- panic("%s: Error initializing RX Ring", dev->name);
++ ether_init_rx_desc_ring(mp);
+
+- mv64340_eth_rx_task(dev); /* Fill RX ring with skb's */
++ mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
+
+ eth_port_start(mp);
+
+ /* Interrupt Coalescing */
+
+-#ifdef MV64340_COAL
++#ifdef MV643XX_COAL
+ mp->rx_int_coal =
+- eth_port_set_rx_coal(port_num, 133000000, MV64340_RX_COAL);
++ eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
+ #endif
+
+ mp->tx_int_coal =
+- eth_port_set_tx_coal (port_num, 133000000, MV64340_TX_COAL);
++ eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
+
+- /* Increase the Rx side buffer size */
+-
+- MV_WRITE (MV64340_ETH_PORT_SERIAL_CONTROL_REG(port_num), (0x5 << 17) |
+- (MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(port_num))
+- & 0xfff1ffff));
+-
+- /* Check Link status on phy */
+- eth_port_read_smi_reg(port_num, 1, &phy_reg_data);
+- if (!(phy_reg_data & 0x20))
+- netif_stop_queue(dev);
+- else
+- netif_start_queue(dev);
++ netif_start_queue(dev);
+
+ return 0;
+ }
+
+-static void mv64340_eth_free_tx_rings(struct net_device *dev)
++static void mv643xx_eth_free_tx_rings(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ unsigned int curr;
+
+ /* Stop Tx Queues */
+- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
+- 0x0000ff00);
++ mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
+
+- /* Free TX rings */
+ /* Free outstanding skb's on TX rings */
+- for (curr = 0;
+- (mp->tx_ring_skbs) && (curr < MV64340_TX_QUEUE_SIZE);
+- curr++) {
++ for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
+ if (mp->tx_skb[curr]) {
+ dev_kfree_skb(mp->tx_skb[curr]);
+ mp->tx_ring_skbs--;
+ }
+ }
+- if (mp->tx_ring_skbs != 0)
++ if (mp->tx_ring_skbs)
+ printk("%s: Error on Tx descriptor free - could not free %d"
+- " descriptors\n", dev->name,
+- mp->tx_ring_skbs);
+- pci_free_consistent(0, mp->tx_desc_area_size,
+- (void *) mp->p_tx_desc_area, mp->tx_desc_dma);
++ " descriptors\n", dev->name, mp->tx_ring_skbs);
++
++ /* Free TX ring */
++ if (mp->tx_sram_size)
++ iounmap(mp->p_tx_desc_area);
++ else
++ dma_free_coherent(NULL, mp->tx_desc_area_size,
++ mp->p_tx_desc_area, mp->tx_desc_dma);
+ }
+
+-static void mv64340_eth_free_rx_rings(struct net_device *dev)
++static void mv643xx_eth_free_rx_rings(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+ int curr;
+
+ /* Stop RX Queues */
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
+- 0x0000ff00);
++ mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
+
+- /* Free RX rings */
+ /* Free preallocated skb's on RX rings */
+- for (curr = 0;
+- mp->rx_ring_skbs && (curr < MV64340_RX_QUEUE_SIZE);
+- curr++) {
++ for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
+ if (mp->rx_skb[curr]) {
+ dev_kfree_skb(mp->rx_skb[curr]);
+ mp->rx_ring_skbs--;
+ }
+ }
+
+- if (mp->rx_ring_skbs != 0)
++ if (mp->rx_ring_skbs)
+ printk(KERN_ERR
+- "%s: Error in freeing Rx Ring. %d skb's still"
+- " stuck in RX Ring - ignoring them\n", dev->name,
+- mp->rx_ring_skbs);
+- pci_free_consistent(0, mp->rx_desc_area_size,
+- (void *) mp->p_rx_desc_area,
+- mp->rx_desc_dma);
++ "%s: Error in freeing Rx Ring. %d skb's still"
++ " stuck in RX Ring - ignoring them\n", dev->name,
++ mp->rx_ring_skbs);
++ /* Free RX ring */
++ if (mp->rx_sram_size)
++ iounmap(mp->p_rx_desc_area);
++ else
++ dma_free_coherent(NULL, mp->rx_desc_area_size,
++ mp->p_rx_desc_area, mp->rx_desc_dma);
+ }
+
+ /*
+- * mv64340_eth_stop
++ * mv643xx_eth_stop
+ *
+- * This function is used when closing the network device.
+- * It updates the hardware,
++ * This function is used when closing the network device.
++ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+- * Input : a pointer to the device structure
+- * Output : zero if success , nonzero if fails
++ * Input : a pointer to the device structure
++ * Output : zero if success , nonzero if fails
+ */
+
+-/* Helper function for mv64340_eth_stop */
++/* Helper function for mv643xx_eth_stop */
+
+-static int mv64340_eth_real_stop(struct net_device *dev)
++static int mv643xx_eth_real_stop(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ unsigned int port_num = mp->port_num;
+
++ netif_carrier_off(dev);
+ netif_stop_queue(dev);
+
+- mv64340_eth_free_tx_rings(dev);
+- mv64340_eth_free_rx_rings(dev);
++ mv643xx_eth_free_tx_rings(dev);
++ mv643xx_eth_free_rx_rings(dev);
+
+ eth_port_reset(mp->port_num);
+
+ /* Disable ethernet port interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+
+ /* Mask RX buffer and TX end interrupt */
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
+
+ /* Mask phy and link status changes interrupts */
+- MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
+
+ return 0;
+ }
+
+-static int mv64340_eth_stop(struct net_device *dev)
++static int mv643xx_eth_stop(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+
+ spin_lock_irq(&mp->lock);
+
+- mv64340_eth_real_stop(dev);
++ mv643xx_eth_real_stop(dev);
+
+ free_irq(dev->irq, dev);
+ spin_unlock_irq(&mp->lock);
+@@ -1060,59 +1026,64 @@
+ return 0;
+ }
+
+-#ifdef MV64340_NAPI
+-static void mv64340_tx(struct net_device *dev)
++#ifdef MV643XX_NAPI
++static void mv643xx_tx(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
+- struct pkt_info pkt_info;
++ struct mv643xx_private *mp = netdev_priv(dev);
++ struct pkt_info pkt_info;
+
+ while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
+ if (pkt_info.return_info) {
+- dev_kfree_skb_irq((struct sk_buff *)
+- pkt_info.return_info);
+- if (skb_shinfo(pkt_info.return_info)->nr_frags)
+- pci_unmap_page(NULL, pkt_info.buf_ptr,
+- pkt_info.byte_cnt,
+- PCI_DMA_TODEVICE);
+-
+- if (mp->tx_ring_skbs != 1)
+- mp->tx_ring_skbs--;
+- } else
+- pci_unmap_page(NULL, pkt_info.buf_ptr, pkt_info.byte_cnt,
+- PCI_DMA_TODEVICE);
++ if (skb_shinfo(pkt_info.return_info)->nr_frags)
++ dma_unmap_page(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt,
++ DMA_TO_DEVICE);
++ else
++ dma_unmap_single(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt,
++ DMA_TO_DEVICE);
++
++ dev_kfree_skb_irq(pkt_info.return_info);
++
++ if (mp->tx_ring_skbs)
++ mp->tx_ring_skbs--;
++ } else
++ dma_unmap_page(NULL, pkt_info.buf_ptr,
++ pkt_info.byte_cnt, DMA_TO_DEVICE);
+ }
+
+ if (netif_queue_stopped(dev) &&
+- MV64340_TX_QUEUE_SIZE > mp->tx_ring_skbs + 1)
+- netif_wake_queue(dev);
++ mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
++ netif_wake_queue(dev);
+ }
+
+ /*
+- * mv64340_poll
++ * mv643xx_poll
+ *
+ * This function is used in case of NAPI
+ */
+-static int mv64340_poll(struct net_device *dev, int *budget)
++static int mv643xx_poll(struct net_device *dev, int *budget)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
+- int done = 1, orig_budget, work_done;
++ struct mv643xx_private *mp = netdev_priv(dev);
++ int done = 1, orig_budget, work_done;
+ unsigned int port_num = mp->port_num;
+ unsigned long flags;
+
+-#ifdef MV64340_TX_FAST_REFILL
++#ifdef MV643XX_TX_FAST_REFILL
+ if (++mp->tx_clean_threshold > 5) {
+ spin_lock_irqsave(&mp->lock, flags);
+- mv64340_tx(dev);
++ mv643xx_tx(dev);
+ mp->tx_clean_threshold = 0;
+ spin_unlock_irqrestore(&mp->lock, flags);
+ }
+ #endif
+
+- if ((u32)(MV_READ(MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) != (u32)mp->rx_used_desc_q) {
++ if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
++ != (u32) mp->rx_used_desc_q) {
+ orig_budget = *budget;
+ if (orig_budget > dev->quota)
+ orig_budget = dev->quota;
+- work_done = mv64340_eth_receive_queue(dev, 0, orig_budget);
++ work_done = mv643xx_eth_receive_queue(dev, orig_budget);
+ mp->rx_task.func(dev);
+ *budget -= work_done;
+ dev->quota -= work_done;
+@@ -1123,12 +1094,12 @@
+ if (done) {
+ spin_lock_irqsave(&mp->lock, flags);
+ __netif_rx_complete(dev);
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_REG(port_num),0);
+- MV_WRITE(MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),0);
+- MV_WRITE(MV64340_ETH_INTERRUPT_MASK_REG(port_num),
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
++ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
+ INT_CAUSE_UNMASK_ALL);
+- MV_WRITE(MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
+- INT_CAUSE_UNMASK_ALL_EXT);
++ mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
++ INT_CAUSE_UNMASK_ALL_EXT);
+ spin_unlock_irqrestore(&mp->lock, flags);
+ }
+
+@@ -1137,19 +1108,19 @@
+ #endif
+
+ /*
+- * mv64340_eth_start_xmit
++ * mv643xx_eth_start_xmit
+ *
+- * This function is queues a packet in the Tx descriptor for
++ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+- * Input : skb - a pointer to socket buffer
+- * dev - a pointer to the required port
++ * Input : skb - a pointer to socket buffer
++ * dev - a pointer to the required port
+ *
+- * Output : zero upon success
++ * Output : zero upon success
+ */
+-static int mv64340_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
++static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &mp->stats;
+ ETH_FUNC_RET_STATUS status;
+ unsigned long flags;
+@@ -1157,119 +1128,195 @@
+
+ if (netif_queue_stopped(dev)) {
+ printk(KERN_ERR
+- "%s: Tried sending packet when interface is stopped\n",
+- dev->name);
++ "%s: Tried sending packet when interface is stopped\n",
++ dev->name);
+ return 1;
+ }
+
+ /* This is a hard error, log it. */
+- if ((MV64340_TX_QUEUE_SIZE - mp->tx_ring_skbs) <=
+- (skb_shinfo(skb)->nr_frags + 1)) {
++ if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
++ (skb_shinfo(skb)->nr_frags + 1)) {
+ netif_stop_queue(dev);
+ printk(KERN_ERR
+- "%s: Bug in mv64340_eth - Trying to transmit when"
+- " queue full !\n", dev->name);
++ "%s: Bug in mv643xx_eth - Trying to transmit when"
++ " queue full !\n", dev->name);
+ return 1;
+ }
+
+ /* Paranoid check - this shouldn't happen */
+ if (skb == NULL) {
+ stats->tx_dropped++;
++ printk(KERN_ERR "mv64320_eth paranoid check failed\n");
+ return 1;
+ }
+
+ spin_lock_irqsave(&mp->lock, flags);
+
+ /* Update packet info data structure -- DMA owned, first last */
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- if (!skb_shinfo(skb)->nr_frags || (skb_shinfo(skb)->nr_frags > 3)) {
+-#endif
+- pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
+- ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ if (!skb_shinfo(skb)->nr_frags) {
++linear:
++ if (skb->ip_summed != CHECKSUM_HW) {
++ pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
++ ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;
++ pkt_info.l4i_chk = 0;
++ } else {
++ u32 ipheader = skb->nh.iph->ihl << 11;
+
++ pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
++ ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC |
++ ETH_GEN_TCP_UDP_CHECKSUM |
++ ETH_GEN_IP_V_4_CHECKSUM | ipheader;
++ /* CPU already calculated pseudo header checksum. */
++ if (skb->nh.iph->protocol == IPPROTO_UDP) {
++ pkt_info.cmd_sts |= ETH_UDP_FRAME;
++ pkt_info.l4i_chk = skb->h.uh->check;
++ } else if (skb->nh.iph->protocol == IPPROTO_TCP)
++ pkt_info.l4i_chk = skb->h.th->check;
++ else {
++ printk(KERN_ERR
++ "%s: chksum proto != TCP or UDP\n",
++ dev->name);
++ spin_unlock_irqrestore(&mp->lock, flags);
++ return 1;
++ }
++ }
+ pkt_info.byte_cnt = skb->len;
+- pkt_info.buf_ptr = pci_map_single(0, skb->data, skb->len,
+- PCI_DMA_TODEVICE);
+-
+-
++ pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
++ DMA_TO_DEVICE);
+ pkt_info.return_info = skb;
++ mp->tx_ring_skbs++;
+ status = eth_port_send(mp, &pkt_info);
+ if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
+ printk(KERN_ERR "%s: Error on transmitting packet\n",
+- dev->name);
+- mp->tx_ring_skbs++;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
++ dev->name);
++ stats->tx_bytes += pkt_info.byte_cnt;
+ } else {
+- unsigned int frag;
+- u32 ipheader;
++ unsigned int frag;
++ u32 ipheader;
+
+- /* first frag which is skb header */
+- pkt_info.byte_cnt = skb_headlen(skb);
+- pkt_info.buf_ptr = pci_map_single(0, skb->data,
+- skb_headlen(skb), PCI_DMA_TODEVICE);
+- pkt_info.return_info = 0;
+- ipheader = skb->nh.iph->ihl << 11;
+- pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
+- ETH_GEN_TCP_UDP_CHECKSUM |
+- ETH_GEN_IP_V_4_CHECKSUM |
+- ipheader;
+- /* CPU already calculated pseudo header checksum. So, use it */
+- pkt_info.l4i_chk = skb->h.th->check;
+- status = eth_port_send(mp, &pkt_info);
++ /* Since hardware can't handle unaligned fragments smaller
++ * than 9 bytes, if we find any, we linearize the skb
++ * and start again. When I've seen it, it's always been
++ * the first frag (probably near the end of the page),
++ * but we check all frags to be safe.
++ */
++ for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
++ skb_frag_t *fragp;
++
++ fragp = &skb_shinfo(skb)->frags[frag];
++ if (fragp->size <= 8 && fragp->page_offset & 0x7) {
++ skb_linearize(skb, GFP_ATOMIC);
++ printk(KERN_DEBUG "%s: unaligned tiny fragment"
++ "%d of %d, fixed\n",
++ dev->name, frag,
++ skb_shinfo(skb)->nr_frags);
++ goto linear;
++ }
++ }
++
++ /* first frag which is skb header */
++ pkt_info.byte_cnt = skb_headlen(skb);
++ pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
++ skb_headlen(skb),
++ DMA_TO_DEVICE);
++ pkt_info.l4i_chk = 0;
++ pkt_info.return_info = 0;
++ pkt_info.cmd_sts = ETH_TX_FIRST_DESC;
++
++ if (skb->ip_summed == CHECKSUM_HW) {
++ ipheader = skb->nh.iph->ihl << 11;
++ pkt_info.cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
++ ETH_GEN_IP_V_4_CHECKSUM | ipheader;
++ /* CPU already calculated pseudo header checksum. */
++ if (skb->nh.iph->protocol == IPPROTO_UDP) {
++ pkt_info.cmd_sts |= ETH_UDP_FRAME;
++ pkt_info.l4i_chk = skb->h.uh->check;
++ } else if (skb->nh.iph->protocol == IPPROTO_TCP)
++ pkt_info.l4i_chk = skb->h.th->check;
++ else {
++ printk(KERN_ERR
++ "%s: chksum proto != TCP or UDP\n",
++ dev->name);
++ spin_unlock_irqrestore(&mp->lock, flags);
++ return 1;
++ }
++ }
++
++ status = eth_port_send(mp, &pkt_info);
+ if (status != ETH_OK) {
+- if ((status == ETH_ERROR))
+- printk(KERN_ERR "%s: Error on transmitting packet\n", dev->name);
+- if (status == ETH_QUEUE_FULL)
+- printk("Error on Queue Full \n");
+- if (status == ETH_QUEUE_LAST_RESOURCE)
+- printk("Tx resource error \n");
++ if ((status == ETH_ERROR))
++ printk(KERN_ERR
++ "%s: Error on transmitting packet\n",
++ dev->name);
++ if (status == ETH_QUEUE_FULL)
++ printk("Error on Queue Full \n");
++ if (status == ETH_QUEUE_LAST_RESOURCE)
++ printk("Tx resource error \n");
+ }
++ stats->tx_bytes += pkt_info.byte_cnt;
++
++ /* Check for the remaining frags */
++ for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
++ skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
++ pkt_info.l4i_chk = 0x0000;
++ pkt_info.cmd_sts = 0x00000000;
++
++ /* Last Frag enables interrupt and frees the skb */
++ if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
++ pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
++ ETH_TX_LAST_DESC;
++ pkt_info.return_info = skb;
++ mp->tx_ring_skbs++;
++ } else {
++ pkt_info.return_info = 0;
++ }
++ pkt_info.l4i_chk = 0;
++ pkt_info.byte_cnt = this_frag->size;
+
+- /* Check for the remaining frags */
+- for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
+- skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
+- pkt_info.l4i_chk = 0x0000;
+- pkt_info.cmd_sts = 0x00000000;
+-
+- /* Last Frag enables interrupt and frees the skb */
+- if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
+- pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
+- ETH_TX_LAST_DESC;
+- pkt_info.return_info = skb;
+- mp->tx_ring_skbs++;
+- }
+- else {
+- pkt_info.return_info = 0;
+- }
+- pkt_info.byte_cnt = this_frag->size;
+- if (this_frag->size < 8)
+- printk("%d : \n", skb_shinfo(skb)->nr_frags);
+-
+- pkt_info.buf_ptr = pci_map_page(NULL, this_frag->page,
+- this_frag->page_offset,
+- this_frag->size, PCI_DMA_TODEVICE);
++ pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
++ this_frag->page_offset,
++ this_frag->size,
++ DMA_TO_DEVICE);
+
+- status = eth_port_send(mp, &pkt_info);
++ status = eth_port_send(mp, &pkt_info);
+
+ if (status != ETH_OK) {
+- if ((status == ETH_ERROR))
+- printk(KERN_ERR "%s: Error on transmitting packet\n", dev->name);
++ if ((status == ETH_ERROR))
++ printk(KERN_ERR "%s: Error on "
++ "transmitting packet\n",
++ dev->name);
+
+- if (status == ETH_QUEUE_LAST_RESOURCE)
+- printk("Tx resource error \n");
++ if (status == ETH_QUEUE_LAST_RESOURCE)
++ printk("Tx resource error \n");
+
+- if (status == ETH_QUEUE_FULL)
+- printk("Queue is full \n");
++ if (status == ETH_QUEUE_FULL)
++ printk("Queue is full \n");
+ }
+- }
+- }
++ stats->tx_bytes += pkt_info.byte_cnt;
++ }
++ }
++#else
++ pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
++ ETH_TX_LAST_DESC;
++ pkt_info.l4i_chk = 0;
++ pkt_info.byte_cnt = skb->len;
++ pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
++ DMA_TO_DEVICE);
++ pkt_info.return_info = skb;
++ mp->tx_ring_skbs++;
++ status = eth_port_send(mp, &pkt_info);
++ if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
++ printk(KERN_ERR "%s: Error on transmitting packet\n",
++ dev->name);
++ stats->tx_bytes += pkt_info.byte_cnt;
+ #endif
+
+ /* Check if TX queue can handle another skb. If not, then
+ * signal higher layers to stop requesting TX
+ */
+- if (MV64340_TX_QUEUE_SIZE <= (mp->tx_ring_skbs + 1))
+- /*
++ if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
++ /*
+ * Stop getting skb's from upper layers.
+ * Getting skb's from upper layers will be enabled again after
+ * packets are released.
+@@ -1277,7 +1324,6 @@
+ netif_stop_queue(dev);
+
+ /* Update statistics and start of transmittion time */
+- stats->tx_bytes += skb->len;
+ stats->tx_packets++;
+ dev->trans_start = jiffies;
+
+@@ -1287,214 +1333,304 @@
+ }
+
+ /*
+- * mv64340_eth_get_stats
++ * mv643xx_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+- * Input : dev - a pointer to the required interface
++ * Input : dev - a pointer to the required interface
+ *
+- * Output : a pointer to the interface's statistics
++ * Output : a pointer to the interface's statistics
+ */
+
+-static struct net_device_stats *mv64340_eth_get_stats(struct net_device *dev)
++static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct mv643xx_private *mp = netdev_priv(dev);
+
+ return &mp->stats;
+ }
+
+ /*/
+- * mv64340_eth_init
+- *
+- * First function called after registering the network device.
+- * It's purpose is to initialize the device as an ethernet device,
+- * fill the structure that was given in registration with pointers
+- * to functions, and setting the MAC address of the interface
++ * mv643xx_eth_probe
+ *
+- * Input : number of port to initialize
+- * Output : -ENONMEM if failed , 0 if success
+- */
+-static struct net_device *mv64340_eth_init(int port_num)
+-{
+- struct mv64340_private *mp;
++ * First function called after registering the network device.
++ * It's purpose is to initialize the device as an ethernet device,
++ * fill the ethernet device structure with pointers * to functions,
++ * and set the MAC address of the interface
++ *
++ * Input : struct device *
++ * Output : -ENOMEM if failed , 0 if success
++ */
++static int mv643xx_eth_probe(struct device *ddev)
++{
++ struct platform_device *pdev = to_platform_device(ddev);
++ struct mv643xx_eth_platform_data *pd;
++ int port_num = pdev->id;
++ struct mv643xx_private *mp;
+ struct net_device *dev;
++ u8 *p;
++ struct resource *res;
+ int err;
+
+- dev = alloc_etherdev(sizeof(struct mv64340_private));
++ dev = alloc_etherdev(sizeof(struct mv643xx_private));
+ if (!dev)
+- return NULL;
++ return -ENOMEM;
++
++ dev_set_drvdata(ddev, dev);
+
+ mp = netdev_priv(dev);
+
+- dev->irq = ETH_PORT0_IRQ_NUM + port_num;
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ BUG_ON(!res);
++ dev->irq = res->start;
+
+- dev->open = mv64340_eth_open;
+- dev->stop = mv64340_eth_stop;
+- dev->hard_start_xmit = mv64340_eth_start_xmit;
+- dev->get_stats = mv64340_eth_get_stats;
+- dev->set_mac_address = mv64340_eth_set_mac_address;
+- dev->set_multicast_list = mv64340_eth_set_rx_mode;
++ mp->port_num = port_num;
++
++ dev->open = mv643xx_eth_open;
++ dev->stop = mv643xx_eth_stop;
++ dev->hard_start_xmit = mv643xx_eth_start_xmit;
++ dev->get_stats = mv643xx_eth_get_stats;
++ dev->set_mac_address = mv643xx_eth_set_mac_address;
++ dev->set_multicast_list = mv643xx_eth_set_rx_mode;
+
+ /* No need to Tx Timeout */
+- dev->tx_timeout = mv64340_eth_tx_timeout;
+-#ifdef MV64340_NAPI
+- dev->poll = mv64340_poll;
+- dev->weight = 64;
++ dev->tx_timeout = mv643xx_eth_tx_timeout;
++#ifdef MV643XX_NAPI
++ dev->poll = mv643xx_poll;
++ dev->weight = 64;
+ #endif
+
+ dev->watchdog_timeo = 2 * HZ;
+- dev->tx_queue_len = MV64340_TX_QUEUE_SIZE;
++ dev->tx_queue_len = mp->tx_ring_size;
+ dev->base_addr = 0;
+- dev->change_mtu = mv64340_eth_change_mtu;
++ dev->change_mtu = mv643xx_eth_change_mtu;
++ SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
+
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
+ #ifdef MAX_SKB_FRAGS
+ #ifndef CONFIG_JAGUAR_DMALOW
+- /*
+- * Zero copy can only work if we use Discovery II memory. Else, we will
+- * have to map the buffers to ISA memory which is only 16 MB
+- */
+- dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
++ /*
++ * Zero copy can only work if we use Discovery II memory. Else, we will
++ * have to map the buffers to ISA memory which is only 16 MB
++ */
++ dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
+ #endif
+ #endif
+ #endif
+
+- mp->port_num = port_num;
+-
+ /* Configure the timeout task */
+- INIT_WORK(&mp->tx_timeout_task,
+- (void (*)(void *))mv64340_eth_tx_timeout_task, dev);
++ INIT_WORK(&mp->tx_timeout_task,
++ (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
+
+ spin_lock_init(&mp->lock);
+
+- /* set MAC addresses */
+- memcpy(dev->dev_addr, prom_mac_addr_base, 6);
+- dev->dev_addr[5] += port_num;
++ /* set default config values */
++ eth_port_uc_addr_get(dev, dev->dev_addr);
++ mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
++ mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
++ mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
++ mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
++ mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
++ mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
++
++ pd = pdev->dev.platform_data;
++ if (pd) {
++ if (pd->mac_addr != NULL)
++ memcpy(dev->dev_addr, pd->mac_addr, 6);
++
++ if (pd->phy_addr || pd->force_phy_addr)
++ ethernet_phy_set(port_num, pd->phy_addr);
++
++ if (pd->port_config || pd->force_port_config)
++ mp->port_config = pd->port_config;
++
++ if (pd->port_config_extend || pd->force_port_config_extend)
++ mp->port_config_extend = pd->port_config_extend;
++
++ if (pd->port_sdma_config || pd->force_port_sdma_config)
++ mp->port_sdma_config = pd->port_sdma_config;
++
++ if (pd->port_serial_control || pd->force_port_serial_control)
++ mp->port_serial_control = pd->port_serial_control;
++
++ if (pd->rx_queue_size)
++ mp->rx_ring_size = pd->rx_queue_size;
++
++ if (pd->tx_queue_size)
++ mp->tx_ring_size = pd->tx_queue_size;
++
++ if (pd->tx_sram_size) {
++ mp->tx_sram_size = pd->tx_sram_size;
++ mp->tx_sram_addr = pd->tx_sram_addr;
++ }
++
++ if (pd->rx_sram_size) {
++ mp->rx_sram_size = pd->rx_sram_size;
++ mp->rx_sram_addr = pd->rx_sram_addr;
++ }
++ }
++
++ err = ethernet_phy_detect(port_num);
++ if (err) {
++ pr_debug("MV643xx ethernet port %d: "
++ "No PHY detected at addr %d\n",
++ port_num, ethernet_phy_get(port_num));
++ return err;
++ }
+
+ err = register_netdev(dev);
+ if (err)
+- goto out_free_dev;
++ goto out;
+
+- printk(KERN_NOTICE "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
+- dev->name, port_num,
+- dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
+- dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
++ p = dev->dev_addr;
++ printk(KERN_NOTICE
++ "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
++ dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ if (dev->features & NETIF_F_SG)
+- printk("Scatter Gather Enabled ");
++ printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
+
+ if (dev->features & NETIF_F_IP_CSUM)
+- printk("TX TCP/IP Checksumming Supported \n");
++ printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
++ dev->name);
++
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
++#endif
+
+- printk("RX TCP/UDP Checksum Offload ON, \n");
+- printk("TX and RX Interrupt Coalescing ON \n");
++#ifdef MV643XX_COAL
++ printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
++ dev->name);
++#endif
+
+-#ifdef MV64340_NAPI
+- printk("RX NAPI Enabled \n");
++#ifdef MV643XX_NAPI
++ printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
+ #endif
+
+- return dev;
++ return 0;
+
+-out_free_dev:
++out:
+ free_netdev(dev);
+
+- return NULL;
++ return err;
+ }
+
+-static void mv64340_eth_remove(struct net_device *dev)
++static int mv643xx_eth_remove(struct device *ddev)
+ {
+- struct mv64340_private *mp = netdev_priv(dev);
++ struct net_device *dev = dev_get_drvdata(ddev);
+
+ unregister_netdev(dev);
+ flush_scheduled_work();
++
+ free_netdev(dev);
++ dev_set_drvdata(ddev, NULL);
++ return 0;
++}
++
++static int mv643xx_eth_shared_probe(struct device *ddev)
++{
++ struct platform_device *pdev = to_platform_device(ddev);
++ struct resource *res;
++
++ printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL)
++ return -ENODEV;
++
++ mv643xx_eth_shared_base = ioremap(res->start,
++ MV643XX_ETH_SHARED_REGS_SIZE);
++ if (mv643xx_eth_shared_base == NULL)
++ return -ENOMEM;
++
++ return 0;
++
++}
++
++static int mv643xx_eth_shared_remove(struct device *ddev)
++{
++ iounmap(mv643xx_eth_shared_base);
++ mv643xx_eth_shared_base = NULL;
++
++ return 0;
+ }
+
+-static struct net_device *mv64340_dev0;
+-static struct net_device *mv64340_dev1;
+-static struct net_device *mv64340_dev2;
++static struct device_driver mv643xx_eth_driver = {
++ .name = MV643XX_ETH_NAME,
++ .bus = &platform_bus_type,
++ .probe = mv643xx_eth_probe,
++ .remove = mv643xx_eth_remove,
++};
++
++static struct device_driver mv643xx_eth_shared_driver = {
++ .name = MV643XX_ETH_SHARED_NAME,
++ .bus = &platform_bus_type,
++ .probe = mv643xx_eth_shared_probe,
++ .remove = mv643xx_eth_shared_remove,
++};
+
+ /*
+- * mv64340_init_module
++ * mv643xx_init_module
+ *
+ * Registers the network drivers into the Linux kernel
+ *
+- * Input : N/A
++ * Input : N/A
+ *
+- * Output : N/A
++ * Output : N/A
+ */
+-static int __init mv64340_init_module(void)
++static int __init mv643xx_init_module(void)
+ {
+- printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
++ int rc;
+
+-#ifdef CONFIG_MV643XX_ETH_0
+- mv64340_dev0 = mv64340_eth_init(0);
+- if (!mv64340_dev0) {
+- printk(KERN_ERR
+- "Error registering MV-64360 ethernet port 0\n");
+- }
+-#endif
+-#ifdef CONFIG_MV643XX_ETH_1
+- mv64340_dev1 = mv64340_eth_init(1);
+- if (!mv64340_dev1) {
+- printk(KERN_ERR
+- "Error registering MV-64360 ethernet port 1\n");
+- }
+-#endif
+-#ifdef CONFIG_MV643XX_ETH_2
+- mv64340_dev2 = mv64340_eth_init(2);
+- if (!mv64340_dev2) {
+- printk(KERN_ERR
+- "Error registering MV-64360 ethernet port 2\n");
++ rc = driver_register(&mv643xx_eth_shared_driver);
++ if (!rc) {
++ rc = driver_register(&mv643xx_eth_driver);
++ if (rc)
++ driver_unregister(&mv643xx_eth_shared_driver);
+ }
+-#endif
+- return 0;
++ return rc;
+ }
+
+ /*
+- * mv64340_cleanup_module
++ * mv643xx_cleanup_module
+ *
+ * Registers the network drivers into the Linux kernel
+ *
+- * Input : N/A
++ * Input : N/A
+ *
+- * Output : N/A
++ * Output : N/A
+ */
+-static void __exit mv64340_cleanup_module(void)
++static void __exit mv643xx_cleanup_module(void)
+ {
+- if (mv64340_dev2)
+- mv64340_eth_remove(mv64340_dev2);
+- if (mv64340_dev1)
+- mv64340_eth_remove(mv64340_dev1);
+- if (mv64340_dev0)
+- mv64340_eth_remove(mv64340_dev0);
++ driver_unregister(&mv643xx_eth_driver);
++ driver_unregister(&mv643xx_eth_shared_driver);
+ }
+
+-module_init(mv64340_init_module);
+-module_exit(mv64340_cleanup_module);
++module_init(mv643xx_init_module);
++module_exit(mv643xx_cleanup_module);
+
+ MODULE_LICENSE("GPL");
+-MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm and Manish Lachwani");
+-MODULE_DESCRIPTION("Ethernet driver for Marvell MV64340");
++MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
++ " and Dale Farnsworth");
++MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
+
+ /*
+- * The second part is the low level driver of the gigE ethernet ports.
++ * The second part is the low level driver of the gigE ethernet ports.
+ */
+
+ /*
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+- * This file introduce low level API to Marvell's Gigabit Ethernet
++ * This file introduce low level API to Marvell's Gigabit Ethernet
+ * controller. This Gigabit Ethernet Controller driver API controls
+ * 1) Operations (i.e. port init, start, reset etc').
+ * 2) Data flow (i.e. port send, receive etc').
+ * Each Gigabit Ethernet port is controlled via
+- * struct mv64340_private.
++ * struct mv643xx_private.
+ * This struct includes user configuration information as well as
+ * driver internal data needed for its operations.
+ *
+- * Supported Features:
++ * Supported Features:
+ * - This low level driver is OS independent. Allocating memory for
+ * the descriptor rings and buffers are not within the scope of
+ * this driver.
+@@ -1511,12 +1647,12 @@
+ * - PHY access and control API.
+ * - Port control register configuration API.
+ * - Full control over Unicast and Multicast MAC configurations.
+- *
++ *
+ * Operation flow:
+ *
+ * Initialization phase
+- * This phase complete the initialization of the the mv64340_private
+- * struct.
++ * This phase complete the initialization of the the
++ * mv643xx_private struct.
+ * User information regarding port configuration has to be set
+ * prior to calling the port initialization routine.
+ *
+@@ -1525,7 +1661,7 @@
+ * access to DRAM and internal SRAM memory spaces.
+ *
+ * Driver ring initialization
+- * Allocating memory for the descriptor rings and buffers is not
++ * Allocating memory for the descriptor rings and buffers is not
+ * within the scope of this driver. Thus, the user is required to
+ * allocate memory for the descriptors ring and buffers. Those
+ * memory parameters are used by the Rx and Tx ring initialization
+@@ -1533,49 +1669,50 @@
+ * of a ring.
+ * Note: Pay special attention to alignment issues when using
+ * cached descriptors/buffers. In this phase the driver store
+- * information in the mv64340_private struct regarding each queue
++ * information in the mv643xx_private struct regarding each queue
+ * ring.
+ *
+- * Driver start
++ * Driver start
+ * This phase prepares the Ethernet port for Rx and Tx activity.
+- * It uses the information stored in the mv64340_private struct to
++ * It uses the information stored in the mv643xx_private struct to
+ * initialize the various port registers.
+ *
+ * Data flow:
+ * All packet references to/from the driver are done using
+- * struct pkt_info.
+- * This struct is a unified struct used with Rx and Tx operations.
++ * struct pkt_info.
++ * This struct is a unified struct used with Rx and Tx operations.
+ * This way the user is not required to be familiar with neither
+ * Tx nor Rx descriptors structures.
+ * The driver's descriptors rings are management by indexes.
+ * Those indexes controls the ring resources and used to indicate
+ * a SW resource error:
+- * 'current'
+- * This index points to the current available resource for use. For
+- * example in Rx process this index will point to the descriptor
+- * that will be passed to the user upon calling the receive routine.
+- * In Tx process, this index will point to the descriptor
++ * 'current'
++ * This index points to the current available resource for use. For
++ * example in Rx process this index will point to the descriptor
++ * that will be passed to the user upon calling the receive
++ * routine. In Tx process, this index will point to the descriptor
+ * that will be assigned with the user packet info and transmitted.
+- * 'used'
+- * This index points to the descriptor that need to restore its
++ * 'used'
++ * This index points to the descriptor that need to restore its
+ * resources. For example in Rx process, using the Rx buffer return
+ * API will attach the buffer returned in packet info to the
+ * descriptor pointed by 'used'. In Tx process, using the Tx
+ * descriptor return will merely return the user packet info with
+- * the command status of the transmitted buffer pointed by the
++ * the command status of the transmitted buffer pointed by the
+ * 'used' index. Nevertheless, it is essential to use this routine
+ * to update the 'used' index.
+ * 'first'
+- * This index supports Tx Scatter-Gather. It points to the first
+- * descriptor of a packet assembled of multiple buffers. For example
+- * when in middle of Such packet we have a Tx resource error the
+- * 'curr' index get the value of 'first' to indicate that the ring
+- * returned to its state before trying to transmit this packet.
++ * This index supports Tx Scatter-Gather. It points to the first
++ * descriptor of a packet assembled of multiple buffers. For
++ * example when in middle of Such packet we have a Tx resource
++ * error the 'curr' index get the value of 'first' to indicate
++ * that the ring returned to its state before trying to transmit
++ * this packet.
+ *
+ * Receive operation:
+ * The eth_port_receive API set the packet information struct,
+- * passed by the caller, with received information from the
+- * 'current' SDMA descriptor.
++ * passed by the caller, with received information from the
++ * 'current' SDMA descriptor.
+ * It is the user responsibility to return this resource back
+ * to the Rx descriptor ring to enable the reuse of this source.
+ * Return Rx resource is done using the eth_rx_return_buff API.
+@@ -1596,27 +1733,21 @@
+ *
+ * EXTERNAL INTERFACE
+ *
+- * Prior to calling the initialization routine eth_port_init() the user
+- * must set the following fields under mv64340_private struct:
+- * port_num User Ethernet port number.
+- * port_mac_addr[6] User defined port MAC address.
+- * port_config User port configuration value.
+- * port_config_extend User port config extend value.
+- * port_sdma_config User port SDMA config value.
+- * port_serial_control User port serial control value.
+- *
+- * This driver introduce a set of default values:
+- * PORT_CONFIG_VALUE Default port configuration value
+- * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
+- * PORT_SDMA_CONFIG_VALUE Default sdma control value
+- * PORT_SERIAL_CONTROL_VALUE Default port serial control value
++ * Prior to calling the initialization routine eth_port_init() the user
++ * must set the following fields under mv643xx_private struct:
++ * port_num User Ethernet port number.
++ * port_mac_addr[6] User defined port MAC address.
++ * port_config User port configuration value.
++ * port_config_extend User port config extend value.
++ * port_sdma_config User port SDMA config value.
++ * port_serial_control User port serial control value.
+ *
+ * This driver data flow is done using the struct pkt_info which
+- * is a unified struct for Rx and Tx operations:
++ * is a unified struct for Rx and Tx operations:
+ *
+ * byte_cnt Tx/Rx descriptor buffer byte count.
+ * l4i_chk CPU provided TCP Checksum. For Tx operation
+- * only.
++ * only.
+ * cmd_sts Tx/Rx descriptor command status.
+ * buf_ptr Tx/Rx descriptor buffer pointer.
+ * return_info Tx/Rx user resource return information.
+@@ -1625,70 +1756,44 @@
+ /* defines */
+ /* SDMA command macros */
+ #define ETH_ENABLE_TX_QUEUE(eth_port) \
+- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
+-
+-#define ETH_DISABLE_TX_QUEUE(eth_port) \
+- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), \
+- (1 << 8))
+-
+-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), \
+- (1 << rx_queue))
+-
+-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), \
+- (1 << (8 + rx_queue)))
+-
+-#define LINK_UP_TIMEOUT 100000
+-#define PHY_BUSY_TIMEOUT 10000000
++ mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
+
+ /* locals */
+
+ /* PHY routines */
+ static int ethernet_phy_get(unsigned int eth_port_num);
++static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
+
+ /* Ethernet Port routines */
+ static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
+- int option);
++ int option);
+
+ /*
+ * eth_port_init - Initialize the Ethernet port driver
+ *
+ * DESCRIPTION:
+- * This function prepares the ethernet port to start its activity:
+- * 1) Completes the ethernet port driver struct initialization toward port
+- * start routine.
+- * 2) Resets the device to a quiescent state in case of warm reboot.
+- * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+- * 4) Clean MAC tables. The reset status of those tables is unknown.
+- * 5) Set PHY address.
+- * Note: Call this routine prior to eth_port_start routine and after
+- * setting user values in the user fields of Ethernet port control
+- * struct.
++ * This function prepares the ethernet port to start its activity:
++ * 1) Completes the ethernet port driver struct initialization toward port
++ * start routine.
++ * 2) Resets the device to a quiescent state in case of warm reboot.
++ * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
++ * 4) Clean MAC tables. The reset status of those tables is unknown.
++ * 5) Set PHY address.
++ * Note: Call this routine prior to eth_port_start routine and after
++ * setting user values in the user fields of Ethernet port control
++ * struct.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet port control struct
++ * struct mv643xx_private *mp Ethernet port control struct
+ *
+ * OUTPUT:
+- * See description.
++ * See description.
+ *
+ * RETURN:
+- * None.
++ * None.
+ */
+-static void eth_port_init(struct mv64340_private * mp)
++static void eth_port_init(struct mv643xx_private *mp)
+ {
+- mp->port_config = PORT_CONFIG_VALUE;
+- mp->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+-#if defined(__BIG_ENDIAN)
+- mp->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+-#elif defined(__LITTLE_ENDIAN)
+- mp->port_sdma_config = PORT_SDMA_CONFIG_VALUE |
+- ETH_BLM_RX_NO_SWAP | ETH_BLM_TX_NO_SWAP;
+-#else
+-#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be defined!
+-#endif
+- mp->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+-
+ mp->port_rx_queue_command = 0;
+ mp->port_tx_queue_command = 0;
+
+@@ -1706,77 +1811,73 @@
+ * eth_port_start - Start the Ethernet port activity.
+ *
+ * DESCRIPTION:
+- * This routine prepares the Ethernet port for Rx and Tx activity:
+- * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+- * has been initialized a descriptor's ring (using
+- * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
+- * 2. Initialize and enable the Ethernet configuration port by writing to
+- * the port's configuration and command registers.
+- * 3. Initialize and enable the SDMA by writing to the SDMA's
+- * configuration and command registers. After completing these steps,
+- * the ethernet port SDMA can starts to perform Rx and Tx activities.
++ * This routine prepares the Ethernet port for Rx and Tx activity:
++ * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
++ * has been initialized a descriptor's ring (using
++ * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
++ * 2. Initialize and enable the Ethernet configuration port by writing to
++ * the port's configuration and command registers.
++ * 3. Initialize and enable the SDMA by writing to the SDMA's
++ * configuration and command registers. After completing these steps,
++ * the ethernet port SDMA can starts to perform Rx and Tx activities.
+ *
+- * Note: Each Rx and Tx queue descriptor's list must be initialized prior
+- * to calling this function (use ether_init_tx_desc_ring for Tx queues
+- * and ether_init_rx_desc_ring for Rx queues).
++ * Note: Each Rx and Tx queue descriptor's list must be initialized prior
++ * to calling this function (use ether_init_tx_desc_ring for Tx queues
++ * and ether_init_rx_desc_ring for Rx queues).
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet port control struct
++ * struct mv643xx_private *mp Ethernet port control struct
+ *
+ * OUTPUT:
+- * Ethernet port is ready to receive and transmit.
++ * Ethernet port is ready to receive and transmit.
+ *
+ * RETURN:
+- * false if the port PHY is not up.
+- * true otherwise.
++ * None.
+ */
+-static int eth_port_start(struct mv64340_private *mp)
++static void eth_port_start(struct mv643xx_private *mp)
+ {
+- unsigned int eth_port_num = mp->port_num;
++ unsigned int port_num = mp->port_num;
+ int tx_curr_desc, rx_curr_desc;
+- unsigned int phy_reg_data;
+
+ /* Assignment of Tx CTRP of given queue */
+ tx_curr_desc = mp->tx_curr_desc_q;
+- MV_WRITE(MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(eth_port_num),
+- (struct eth_tx_desc *) mp->tx_desc_dma + tx_curr_desc);
++ mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
++ (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
+
+ /* Assignment of Rx CRDP of given queue */
+ rx_curr_desc = mp->rx_curr_desc_q;
+- MV_WRITE(MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(eth_port_num),
+- (struct eth_rx_desc *) mp->rx_desc_dma + rx_curr_desc);
++ mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
++ (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
+
+ /* Add the assigned Ethernet address to the port's address table */
+- eth_port_uc_addr_set(mp->port_num, mp->port_mac_addr);
++ eth_port_uc_addr_set(port_num, mp->port_mac_addr);
+
+ /* Assign port configuration and command. */
+- MV_WRITE(MV64340_ETH_PORT_CONFIG_REG(eth_port_num),
+- mp->port_config);
++ mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
+
+- MV_WRITE(MV64340_ETH_PORT_CONFIG_EXTEND_REG(eth_port_num),
+- mp->port_config_extend);
++ mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
++ mp->port_config_extend);
+
+- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num),
+- mp->port_serial_control);
+
+- MV_SET_REG_BITS(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num),
+- ETH_SERIAL_PORT_ENABLE);
++ /* Increase the Rx side buffer size if supporting GigE */
++ if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
++ mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
++ (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
++ else
++ mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
++ mp->port_serial_control);
++
++ mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
++ mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
++ MV643XX_ETH_SERIAL_PORT_ENABLE);
+
+ /* Assign port SDMA configuration */
+- MV_WRITE(MV64340_ETH_SDMA_CONFIG_REG(eth_port_num),
+- mp->port_sdma_config);
++ mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
++ mp->port_sdma_config);
+
+ /* Enable port Rx. */
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port_num),
+- mp->port_rx_queue_command);
+-
+- /* Check if link is up */
+- eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data);
+-
+- if (!(phy_reg_data & 0x20))
+- return 0;
+-
+- return 1;
++ mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
++ mp->port_rx_queue_command);
+ }
+
+ /*
+@@ -1786,29 +1887,29 @@
+ * This function Set the port Ethernet MAC address.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Port number.
+- * char * p_addr Address to be set
++ * unsigned int eth_port_num Port number.
++ * char * p_addr Address to be set
+ *
+ * OUTPUT:
+- * Set MAC address low and high registers. also calls eth_port_uc_addr()
+- * To set the unicast table with the proper information.
++ * Set MAC address low and high registers. also calls eth_port_uc_addr()
++ * To set the unicast table with the proper information.
+ *
+ * RETURN:
+ * N/A.
+ *
+ */
+ static void eth_port_uc_addr_set(unsigned int eth_port_num,
+- unsigned char *p_addr)
++ unsigned char *p_addr)
+ {
+ unsigned int mac_h;
+ unsigned int mac_l;
+
+ mac_l = (p_addr[4] << 8) | (p_addr[5]);
+- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+- (p_addr[2] << 8) | (p_addr[3] << 0);
++ mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
++ (p_addr[3] << 0);
+
+- MV_WRITE(MV64340_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
+- MV_WRITE(MV64340_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
++ mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
++ mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
+
+ /* Accept frames of this address */
+ eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
+@@ -1817,29 +1918,64 @@
+ }
+
+ /*
++ * eth_port_uc_addr_get - This function retrieves the port Unicast address
++ * (MAC address) from the ethernet hw registers.
++ *
++ * DESCRIPTION:
++ * This function retrieves the port Ethernet MAC address.
++ *
++ * INPUT:
++ * unsigned int eth_port_num Port number.
++ * char *MacAddr pointer where the MAC address is stored
++ *
++ * OUTPUT:
++ * Copy the MAC address to the location pointed to by MacAddr
++ *
++ * RETURN:
++ * N/A.
++ *
++ */
++static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
++{
++ struct mv643xx_private *mp = netdev_priv(dev);
++ unsigned int mac_h;
++ unsigned int mac_l;
++
++ mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
++ mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
++
++ p_addr[0] = (mac_h >> 24) & 0xff;
++ p_addr[1] = (mac_h >> 16) & 0xff;
++ p_addr[2] = (mac_h >> 8) & 0xff;
++ p_addr[3] = mac_h & 0xff;
++ p_addr[4] = (mac_l >> 8) & 0xff;
++ p_addr[5] = mac_l & 0xff;
++}
++
++/*
+ * eth_port_uc_addr - This function Set the port unicast address table
+ *
+ * DESCRIPTION:
+- * This function locates the proper entry in the Unicast table for the
+- * specified MAC nibble and sets its properties according to function
++ * This function locates the proper entry in the Unicast table for the
++ * specified MAC nibble and sets its properties according to function
+ * parameters.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Port number.
+- * unsigned char uc_nibble Unicast MAC Address last nibble.
+- * int option 0 = Add, 1 = remove address.
++ * unsigned int eth_port_num Port number.
++ * unsigned char uc_nibble Unicast MAC Address last nibble.
++ * int option 0 = Add, 1 = remove address.
+ *
+ * OUTPUT:
+ * This function add/removes MAC addresses from the port unicast address
+- * table.
++ * table.
+ *
+ * RETURN:
+ * true is output succeeded.
+ * false if option parameter is invalid.
+ *
+ */
+-static int eth_port_uc_addr(unsigned int eth_port_num,
+- unsigned char uc_nibble, int option)
++static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
++ int option)
+ {
+ unsigned int unicast_reg;
+ unsigned int tbl_offset;
+@@ -1852,29 +1988,26 @@
+
+ switch (option) {
+ case REJECT_MAC_ADDR:
+- /* Clear accepts frame bit at specified unicast DA table entry */
+- unicast_reg = MV_READ((MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+- (eth_port_num) + tbl_offset));
++ /* Clear accepts frame bit at given unicast DA table entry */
++ unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
++ (eth_port_num) + tbl_offset));
+
+ unicast_reg &= (0x0E << (8 * reg_offset));
+
+- MV_WRITE(
+- (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+- (eth_port_num) + tbl_offset), unicast_reg);
++ mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
++ (eth_port_num) + tbl_offset), unicast_reg);
+ break;
+
+ case ACCEPT_MAC_ADDR:
+ /* Set accepts frame bit at unicast DA filter table entry */
+ unicast_reg =
+- MV_READ(
+- (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+- (eth_port_num) + tbl_offset));
++ mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
++ (eth_port_num) + tbl_offset));
+
+ unicast_reg |= (0x01 << (8 * reg_offset));
+
+- MV_WRITE(
+- (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+- (eth_port_num) + tbl_offset), unicast_reg);
++ mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
++ (eth_port_num) + tbl_offset), unicast_reg);
+
+ break;
+
+@@ -1889,17 +2022,17 @@
+ * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+ *
+ * DESCRIPTION:
+- * Go through all the DA filter tables (Unicast, Special Multicast &
+- * Other Multicast) and set each entry to 0.
++ * Go through all the DA filter tables (Unicast, Special Multicast &
++ * Other Multicast) and set each entry to 0.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * Multicast and Unicast packets are rejected.
++ * Multicast and Unicast packets are rejected.
+ *
+ * RETURN:
+- * None.
++ * None.
+ */
+ static void eth_port_init_mac_tables(unsigned int eth_port_num)
+ {
+@@ -1907,18 +2040,16 @@
+
+ /* Clear DA filter unicast table (Ex_dFUT) */
+ for (table_index = 0; table_index <= 0xC; table_index += 4)
+- MV_WRITE(
+- (MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE
+- (eth_port_num) + table_index), 0);
++ mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
++ (eth_port_num) + table_index), 0);
+
+ for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+ /* Clear DA filter special multicast table (Ex_dFSMT) */
+- MV_WRITE(
+- (MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
+- (eth_port_num) + table_index), 0);
++ mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
++ (eth_port_num) + table_index), 0);
+ /* Clear DA filter other multicast table (Ex_dFOMT) */
+- MV_WRITE((MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
+- (eth_port_num) + table_index), 0);
++ mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
++ (eth_port_num) + table_index), 0);
+ }
+ }
+
+@@ -1926,17 +2057,17 @@
+ * eth_clear_mib_counters - Clear all MIB counters
+ *
+ * DESCRIPTION:
+- * This function clears all MIB counters of a specific ethernet port.
+- * A read from the MIB counter will reset the counter.
++ * This function clears all MIB counters of a specific ethernet port.
++ * A read from the MIB counter will reset the counter.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * After reading all MIB counters, the counters resets.
++ * After reading all MIB counters, the counters resets.
+ *
+ * RETURN:
+- * MIB counter value.
++ * MIB counter value.
+ *
+ */
+ static void eth_clear_mib_counters(unsigned int eth_port_num)
+@@ -1944,72 +2075,155 @@
+ int i;
+
+ /* Perform dummy reads from MIB counters */
+- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4)
+- MV_READ(MV64340_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
++ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
++ i += 4)
++ mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
++}
++
++static inline u32 read_mib(struct mv643xx_private *mp, int offset)
++{
++ return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
+ }
+
++static void eth_update_mib_counters(struct mv643xx_private *mp)
++{
++ struct mv643xx_mib_counters *p = &mp->mib_counters;
++ int offset;
++
++ p->good_octets_received +=
++ read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
++ p->good_octets_received +=
++ (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
++
++ for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
++ offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
++ offset += 4)
++ *(u32 *)((char *)p + offset) = read_mib(mp, offset);
++
++ p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
++ p->good_octets_sent +=
++ (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
++
++ for (offset = ETH_MIB_GOOD_FRAMES_SENT;
++ offset <= ETH_MIB_LATE_COLLISION;
++ offset += 4)
++ *(u32 *)((char *)p + offset) = read_mib(mp, offset);
++}
++
++/*
++ * ethernet_phy_detect - Detect whether a phy is present
++ *
++ * DESCRIPTION:
++ * This function tests whether there is a PHY present on
++ * the specified port.
++ *
++ * INPUT:
++ * unsigned int eth_port_num Ethernet Port number.
++ *
++ * OUTPUT:
++ * None
++ *
++ * RETURN:
++ * 0 on success
++ * -ENODEV on failure
++ *
++ */
++static int ethernet_phy_detect(unsigned int port_num)
++{
++ unsigned int phy_reg_data0;
++ int auto_neg;
++
++ eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
++ auto_neg = phy_reg_data0 & 0x1000;
++ phy_reg_data0 ^= 0x1000; /* invert auto_neg */
++ eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
++
++ eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
++ if ((phy_reg_data0 & 0x1000) == auto_neg)
++ return -ENODEV; /* change didn't take */
++
++ phy_reg_data0 ^= 0x1000;
++ eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
++ return 0;
++}
+
+ /*
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+- * This routine returns the given ethernet port PHY address.
++ * This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * None.
++ * None.
+ *
+ * RETURN:
+- * PHY address.
++ * PHY address.
+ *
+ */
+ static int ethernet_phy_get(unsigned int eth_port_num)
+ {
+ unsigned int reg_data;
+
+- reg_data = MV_READ(MV64340_ETH_PHY_ADDR_REG);
++ reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
+
+ return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+ }
+
+ /*
++ * ethernet_phy_set - Set the ethernet port PHY address.
++ *
++ * DESCRIPTION:
++ * This routine sets the given ethernet port PHY address.
++ *
++ * INPUT:
++ * unsigned int eth_port_num Ethernet Port number.
++ * int phy_addr PHY address.
++ *
++ * OUTPUT:
++ * None.
++ *
++ * RETURN:
++ * None.
++ *
++ */
++static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
++{
++ u32 reg_data;
++ int addr_shift = 5 * eth_port_num;
++
++ reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
++ reg_data &= ~(0x1f << addr_shift);
++ reg_data |= (phy_addr & 0x1f) << addr_shift;
++ mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
++}
++
++/*
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+- * This routine utilize the SMI interface to reset the ethernet port PHY.
+- * The routine waits until the link is up again or link up is timeout.
++ * This routine utilizes the SMI interface to reset the ethernet port PHY.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * The ethernet port PHY renew its link.
++ * The PHY is reset.
+ *
+ * RETURN:
+- * None.
++ * None.
+ *
+ */
+-static int ethernet_phy_reset(unsigned int eth_port_num)
++static void ethernet_phy_reset(unsigned int eth_port_num)
+ {
+- unsigned int time_out = 50;
+ unsigned int phy_reg_data;
+
+ /* Reset the PHY */
+ eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
+ phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
+ eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
+-
+- /* Poll on the PHY LINK */
+- do {
+- eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data);
+-
+- if (time_out-- == 0)
+- return 0;
+- } while (!(phy_reg_data & 0x20));
+-
+- return 1;
+ }
+
+ /*
+@@ -2017,381 +2231,358 @@
+ *
+ * DESCRIPTION:
+ * This routine resets the chip by aborting any SDMA engine activity and
+- * clearing the MIB counters. The Receiver and the Transmit unit are in
+- * idle state after this command is performed and the port is disabled.
++ * clearing the MIB counters. The Receiver and the Transmit unit are in
++ * idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * Channel activity is halted.
++ * Channel activity is halted.
+ *
+ * RETURN:
+- * None.
++ * None.
+ *
+ */
+-static void eth_port_reset(unsigned int eth_port_num)
++static void eth_port_reset(unsigned int port_num)
+ {
+ unsigned int reg_data;
+
+ /* Stop Tx port activity. Check port Tx activity. */
+- reg_data =
+- MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port_num));
++ reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG
+- (eth_port_num), (reg_data << 8));
++ mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
++ (reg_data << 8));
+
+ /* Wait for all Tx activity to terminate. */
+- do {
+- /* Check port cause register that all Tx queues are stopped */
+- reg_data =
+- MV_READ
+- (MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG
+- (eth_port_num));
+- }
+- while (reg_data & 0xFF);
++ /* Check port cause register that all Tx queues are stopped */
++ while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
++ & 0xFF)
++ udelay(10);
+ }
+
+ /* Stop Rx port activity. Check port Rx activity. */
+- reg_data =
+- MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+- (eth_port_num));
++ reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+- (eth_port_num), (reg_data << 8));
++ mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
++ (reg_data << 8));
+
+ /* Wait for all Rx activity to terminate. */
+- do {
+- /* Check port cause register that all Rx queues are stopped */
+- reg_data =
+- MV_READ
+- (MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG
+- (eth_port_num));
+- }
+- while (reg_data & 0xFF);
++ /* Check port cause register that all Rx queues are stopped */
++ while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
++ & 0xFF)
++ udelay(10);
+ }
+
+-
+ /* Clear all MIB counters */
+- eth_clear_mib_counters(eth_port_num);
++ eth_clear_mib_counters(port_num);
+
+ /* Reset the Enable bit in the Configuration Register */
+- reg_data =
+- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num));
+- reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(eth_port_num), reg_data);
+-
+- return;
++ reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
++ reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
++ mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
+ }
+
+ /*
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+- * This function sets specified bits in the given ethernet
+- * configuration register.
++ * This function sets specified bits in the given ethernet
++ * configuration register.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
+- * unsigned int value 32 bit value.
++ * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int value 32 bit value.
+ *
+ * OUTPUT:
+- * The set bits in the value parameter are set in the configuration
+- * register.
++ * The set bits in the value parameter are set in the configuration
++ * register.
+ *
+ * RETURN:
+- * None.
++ * None.
+ *
+ */
+ static void ethernet_set_config_reg(unsigned int eth_port_num,
+- unsigned int value)
++ unsigned int value)
+ {
+ unsigned int eth_config_reg;
+
+- eth_config_reg =
+- MV_READ(MV64340_ETH_PORT_CONFIG_REG(eth_port_num));
++ eth_config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(eth_port_num));
+ eth_config_reg |= value;
+- MV_WRITE(MV64340_ETH_PORT_CONFIG_REG(eth_port_num),
+- eth_config_reg);
++ mv_write(MV643XX_ETH_PORT_CONFIG_REG(eth_port_num), eth_config_reg);
++}
++
++static int eth_port_autoneg_supported(unsigned int eth_port_num)
++{
++ unsigned int phy_reg_data0;
++
++ eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
++
++ return phy_reg_data0 & 0x1000;
++}
++
++static int eth_port_link_is_up(unsigned int eth_port_num)
++{
++ unsigned int phy_reg_data1;
++
++ eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
++
++ if (eth_port_autoneg_supported(eth_port_num)) {
++ if (phy_reg_data1 & 0x20) /* auto-neg complete */
++ return 1;
++ } else if (phy_reg_data1 & 0x4) /* link up */
++ return 1;
++
++ return 0;
+ }
+
+ /*
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+- * This function returns the configuration register value of the given
+- * ethernet port.
++ * This function returns the configuration register value of the given
++ * ethernet port.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int eth_port_num Ethernet Port number.
+ *
+ * OUTPUT:
+- * None.
++ * None.
+ *
+ * RETURN:
+- * Port configuration register value.
++ * Port configuration register value.
+ */
+ static unsigned int ethernet_get_config_reg(unsigned int eth_port_num)
+ {
+ unsigned int eth_config_reg;
+
+- eth_config_reg = MV_READ(MV64340_ETH_PORT_CONFIG_EXTEND_REG
+- (eth_port_num));
++ eth_config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_EXTEND_REG
++ (eth_port_num));
+ return eth_config_reg;
+ }
+
+-
+ /*
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+- * This routine utilize the SMI interface to interact with the PHY in
+- * order to perform PHY register read.
++ * This routine utilize the SMI interface to interact with the PHY in
++ * order to perform PHY register read.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
+- * unsigned int phy_reg PHY register address offset.
+- * unsigned int *value Register value buffer.
++ * unsigned int port_num Ethernet Port number.
++ * unsigned int phy_reg PHY register address offset.
++ * unsigned int *value Register value buffer.
+ *
+ * OUTPUT:
+- * Write the value of a specified PHY register into given buffer.
++ * Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+- * false if the PHY is busy or read data is not in valid state.
+- * true otherwise.
++ * false if the PHY is busy or read data is not in valid state.
++ * true otherwise.
+ *
+ */
+-static int eth_port_read_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg, unsigned int *value)
++static void eth_port_read_smi_reg(unsigned int port_num,
++ unsigned int phy_reg, unsigned int *value)
+ {
+- int phy_addr = ethernet_phy_get(eth_port_num);
+- unsigned int time_out = PHY_BUSY_TIMEOUT;
+- unsigned int reg_value;
+-
+- /* first check that it is not busy */
+- do {
+- reg_value = MV_READ(MV64340_ETH_SMI_REG);
+- if (time_out-- == 0)
+- return 0;
+- } while (reg_value & ETH_SMI_BUSY);
+-
+- /* not busy */
+-
+- MV_WRITE(MV64340_ETH_SMI_REG,
+- (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
+-
+- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
++ int phy_addr = ethernet_phy_get(port_num);
++ unsigned long flags;
++ int i;
+
+- do {
+- reg_value = MV_READ(MV64340_ETH_SMI_REG);
+- if (time_out-- == 0)
+- return 0;
+- } while (reg_value & ETH_SMI_READ_VALID);
++ /* the SMI register is a shared resource */
++ spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
+
+- /* Wait for the data to update in the SMI register */
+- for (time_out = 0; time_out < PHY_BUSY_TIMEOUT; time_out++);
++ /* wait for the SMI register to become available */
++ for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
++ if (i == PHY_WAIT_ITERATIONS) {
++ printk("mv643xx PHY busy timeout, port %d\n", port_num);
++ goto out;
++ }
++ udelay(PHY_WAIT_MICRO_SECONDS);
++ }
+
+- reg_value = MV_READ(MV64340_ETH_SMI_REG);
++ mv_write(MV643XX_ETH_SMI_REG,
++ (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
+
+- *value = reg_value & 0xffff;
++ /* now wait for the data to be valid */
++ for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
++ if (i == PHY_WAIT_ITERATIONS) {
++ printk("mv643xx PHY read timeout, port %d\n", port_num);
++ goto out;
++ }
++ udelay(PHY_WAIT_MICRO_SECONDS);
++ }
+
+- return 1;
++ *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
++out:
++ spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
+ }
+
+ /*
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+- * This routine utilize the SMI interface to interact with the PHY in
+- * order to perform writes to PHY registers.
++ * This routine utilize the SMI interface to interact with the PHY in
++ * order to perform writes to PHY registers.
+ *
+ * INPUT:
+- * unsigned int eth_port_num Ethernet Port number.
+- * unsigned int phy_reg PHY register address offset.
+- * unsigned int value Register value.
++ * unsigned int eth_port_num Ethernet Port number.
++ * unsigned int phy_reg PHY register address offset.
++ * unsigned int value Register value.
+ *
+ * OUTPUT:
+- * Write the given value to the specified PHY register.
++ * Write the given value to the specified PHY register.
+ *
+ * RETURN:
+- * false if the PHY is busy.
+- * true otherwise.
++ * false if the PHY is busy.
++ * true otherwise.
+ *
+ */
+-static int eth_port_write_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg, unsigned int value)
++static void eth_port_write_smi_reg(unsigned int eth_port_num,
++ unsigned int phy_reg, unsigned int value)
+ {
+- unsigned int time_out = PHY_BUSY_TIMEOUT;
+- unsigned int reg_value;
+ int phy_addr;
++ int i;
++ unsigned long flags;
+
+ phy_addr = ethernet_phy_get(eth_port_num);
+
+- /* first check that it is not busy */
+- do {
+- reg_value = MV_READ(MV64340_ETH_SMI_REG);
+- if (time_out-- == 0)
+- return 0;
+- } while (reg_value & ETH_SMI_BUSY);
+-
+- /* not busy */
+- MV_WRITE(MV64340_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
+- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
++ /* the SMI register is a shared resource */
++ spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
+
+- return 1;
++ /* wait for the SMI register to become available */
++ for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
++ if (i == PHY_WAIT_ITERATIONS) {
++ printk("mv643xx PHY busy timeout, port %d\n",
++ eth_port_num);
++ goto out;
++ }
++ udelay(PHY_WAIT_MICRO_SECONDS);
++ }
++
++ mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
++ ETH_SMI_OPCODE_WRITE | (value & 0xffff));
++out:
++ spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
+ }
+
+ /*
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+- * This routine send a given packet described by p_pktinfo parameter. It
+- * supports transmitting of a packet spaned over multiple buffers. The
+- * routine updates 'curr' and 'first' indexes according to the packet
+- * segment passed to the routine. In case the packet segment is first,
+- * the 'first' index is update. In any case, the 'curr' index is updated.
+- * If the routine get into Tx resource error it assigns 'curr' index as
+- * 'first'. This way the function can abort Tx process of multiple
+- * descriptors per packet.
++ * This routine send a given packet described by p_pktinfo parameter. It
++ * supports transmitting of a packet spaned over multiple buffers. The
++ * routine updates 'curr' and 'first' indexes according to the packet
++ * segment passed to the routine. In case the packet segment is first,
++ * the 'first' index is update. In any case, the 'curr' index is updated.
++ * If the routine get into Tx resource error it assigns 'curr' index as
++ * 'first'. This way the function can abort Tx process of multiple
++ * descriptors per packet.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * struct pkt_info *p_pkt_info User packet buffer.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
++ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+- * Tx ring 'curr' and 'first' indexes are updated.
++ * Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+- * ETH_QUEUE_FULL in case of Tx resource error.
++ * ETH_QUEUE_FULL in case of Tx resource error.
+ * ETH_ERROR in case the routine can not access Tx desc ring.
+ * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+- * ETH_OK otherwise.
++ * ETH_OK otherwise.
+ *
+ */
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
+ /*
+ * Modified to include the first descriptor pointer in case of SG
+ */
+-static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private * mp,
+- struct pkt_info * p_pkt_info)
++static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info)
+ {
+ int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
+- volatile struct eth_tx_desc *current_descriptor;
+- volatile struct eth_tx_desc *first_descriptor;
+- u32 command_status, first_chip_ptr;
++ struct eth_tx_desc *current_descriptor;
++ struct eth_tx_desc *first_descriptor;
++ u32 command;
+
+ /* Do not process Tx ring in case of Tx ring resource error */
+ if (mp->tx_resource_err)
+ return ETH_QUEUE_FULL;
+
++ /*
++ * The hardware requires that each buffer that is <= 8 bytes
++ * in length must be aligned on an 8 byte boundary.
++ */
++ if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
++ printk(KERN_ERR
++ "mv643xx_eth port %d: packet size <= 8 problem\n",
++ mp->port_num);
++ return ETH_ERROR;
++ }
++
+ /* Get the Tx Desc ring indexes */
+ tx_desc_curr = mp->tx_curr_desc_q;
+ tx_desc_used = mp->tx_used_desc_q;
+
+ current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+- if (current_descriptor == NULL)
+- return ETH_ERROR;
+
+- tx_next_desc = (tx_desc_curr + 1) % MV64340_TX_QUEUE_SIZE;
+- command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
++ tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
++
++ current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
++ current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
++ current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
++ mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
+
+- if (command_status & ETH_TX_FIRST_DESC) {
++ command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
++ ETH_BUFFER_OWNED_BY_DMA;
++ if (command & ETH_TX_FIRST_DESC) {
+ tx_first_desc = tx_desc_curr;
+ mp->tx_first_desc_q = tx_first_desc;
++ first_descriptor = current_descriptor;
++ mp->tx_first_command = command;
++ } else {
++ tx_first_desc = mp->tx_first_desc_q;
++ first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
++ BUG_ON(first_descriptor == NULL);
++ current_descriptor->cmd_sts = command;
++ }
+
+- /* fill first descriptor */
+- first_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+- first_descriptor->l4i_chk = p_pkt_info->l4i_chk;
+- first_descriptor->cmd_sts = command_status;
+- first_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+- first_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+- first_descriptor->next_desc_ptr = mp->tx_desc_dma +
+- tx_next_desc * sizeof(struct eth_tx_desc);
++ if (command & ETH_TX_LAST_DESC) {
+ wmb();
+- } else {
+- tx_first_desc = mp->tx_first_desc_q;
+- first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
+- if (first_descriptor == NULL) {
+- printk("First desc is NULL !!\n");
+- return ETH_ERROR;
+- }
+- if (command_status & ETH_TX_LAST_DESC)
+- current_descriptor->next_desc_ptr = 0x00000000;
+- else {
+- command_status |= ETH_BUFFER_OWNED_BY_DMA;
+- current_descriptor->next_desc_ptr = mp->tx_desc_dma +
+- tx_next_desc * sizeof(struct eth_tx_desc);
+- }
+- }
+-
+- if (p_pkt_info->byte_cnt < 8) {
+- printk(" < 8 problem \n");
+- return ETH_ERROR;
+- }
+-
+- current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+- current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+- current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
+- current_descriptor->cmd_sts = command_status;
+-
+- mp->tx_skb[tx_desc_curr] = (struct sk_buff*) p_pkt_info->return_info;
+-
+- wmb();
+-
+- /* Set last desc with DMA ownership and interrupt enable. */
+- if (command_status & ETH_TX_LAST_DESC) {
+- current_descriptor->cmd_sts = command_status |
+- ETH_TX_ENABLE_INTERRUPT |
+- ETH_BUFFER_OWNED_BY_DMA;
++ first_descriptor->cmd_sts = mp->tx_first_command;
+
+- if (!(command_status & ETH_TX_FIRST_DESC))
+- first_descriptor->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+ wmb();
+-
+- first_chip_ptr = MV_READ(MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(mp->port_num));
+-
+- /* Apply send command */
+- if (first_chip_ptr == 0x00000000)
+- MV_WRITE(MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(mp->port_num), (struct eth_tx_desc *) mp->tx_desc_dma + tx_first_desc);
+-
+- ETH_ENABLE_TX_QUEUE(mp->port_num);
++ ETH_ENABLE_TX_QUEUE(mp->port_num);
+
+ /*
+ * Finish Tx packet. Update first desc in case of Tx resource
+ * error */
+- tx_first_desc = tx_next_desc;
+- mp->tx_first_desc_q = tx_first_desc;
+- } else {
+- if (! (command_status & ETH_TX_FIRST_DESC) ) {
+- current_descriptor->cmd_sts = command_status;
+- wmb();
+- }
++ tx_first_desc = tx_next_desc;
++ mp->tx_first_desc_q = tx_first_desc;
+ }
+
+- /* Check for ring index overlap in the Tx desc ring */
+- if (tx_next_desc == tx_desc_used) {
+- mp->tx_resource_err = 1;
+- mp->tx_curr_desc_q = tx_first_desc;
++ /* Check for ring index overlap in the Tx desc ring */
++ if (tx_next_desc == tx_desc_used) {
++ mp->tx_resource_err = 1;
++ mp->tx_curr_desc_q = tx_first_desc;
+
+- return ETH_QUEUE_LAST_RESOURCE;
++ return ETH_QUEUE_LAST_RESOURCE;
+ }
+
+- mp->tx_curr_desc_q = tx_next_desc;
+- wmb();
++ mp->tx_curr_desc_q = tx_next_desc;
+
+- return ETH_OK;
++ return ETH_OK;
+ }
+ #else
+-static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private * mp,
+- struct pkt_info * p_pkt_info)
++static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info)
+ {
+ int tx_desc_curr;
+ int tx_desc_used;
+- volatile struct eth_tx_desc* current_descriptor;
++ struct eth_tx_desc *current_descriptor;
+ unsigned int command_status;
+
+ /* Do not process Tx ring in case of Tx ring resource error */
+@@ -2403,39 +2594,24 @@
+ tx_desc_used = mp->tx_used_desc_q;
+ current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
+
+- if (current_descriptor == NULL)
+- return ETH_ERROR;
+-
+ command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+-
+-/* XXX Is this for real ?!?!? */
+- /* Buffers with a payload smaller than 8 bytes must be aligned to a
+- * 64-bit boundary. We use the memory allocated for Tx descriptor.
+- * This memory is located in TX_BUF_OFFSET_IN_DESC offset within the
+- * Tx descriptor. */
+- if (p_pkt_info->byte_cnt <= 8) {
+- printk(KERN_ERR
+- "You have failed in the < 8 bytes errata - fixme\n");
+- return ETH_ERROR;
+- }
+ current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
+ current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
+- mp->tx_skb[tx_desc_curr] = (struct sk_buff *) p_pkt_info->return_info;
+-
+- mb();
++ mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
+
+ /* Set last desc with DMA ownership and interrupt enable. */
++ wmb();
+ current_descriptor->cmd_sts = command_status |
+ ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+- /* Apply send command */
++ wmb();
+ ETH_ENABLE_TX_QUEUE(mp->port_num);
+
+ /* Finish Tx packet. Update first desc in case of Tx resource error */
+- tx_desc_curr = (tx_desc_curr + 1) % MV64340_TX_QUEUE_SIZE;
++ tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
+
+ /* Update the current descriptor */
+- mp->tx_curr_desc_q = tx_desc_curr;
++ mp->tx_curr_desc_q = tx_desc_curr;
+
+ /* Check for ring index overlap in the Tx desc ring */
+ if (tx_desc_curr == tx_desc_used) {
+@@ -2452,62 +2628,55 @@
+ *
+ * DESCRIPTION:
+ * This routine returns the transmitted packet information to the caller.
+- * It uses the 'first' index to support Tx desc return in case a transmit
+- * of a packet spanned over multiple buffer still in process.
+- * In case the Tx queue was in "resource error" condition, where there are
+- * no available Tx resources, the function resets the resource error flag.
++ * It uses the 'first' index to support Tx desc return in case a transmit
++ * of a packet spanned over multiple buffer still in process.
++ * In case the Tx queue was in "resource error" condition, where there are
++ * no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * struct pkt_info *p_pkt_info User packet buffer.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
++ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+- * Tx ring 'first' and 'used' indexes are updated.
++ * Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Tx desc ring.
+- * ETH_RETRY in case there is transmission in process.
++ * ETH_RETRY in case there is transmission in process.
+ * ETH_END_OF_JOB if the routine has nothing to release.
+- * ETH_OK otherwise.
++ * ETH_OK otherwise.
+ *
+ */
+-static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private * mp,
+- struct pkt_info * p_pkt_info)
++static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info)
+ {
+- int tx_desc_used, tx_desc_curr;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- int tx_first_desc;
++ int tx_desc_used;
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ int tx_busy_desc = mp->tx_first_desc_q;
++#else
++ int tx_busy_desc = mp->tx_curr_desc_q;
+ #endif
+- volatile struct eth_tx_desc *p_tx_desc_used;
++ struct eth_tx_desc *p_tx_desc_used;
+ unsigned int command_status;
+
+ /* Get the Tx Desc ring indexes */
+- tx_desc_curr = mp->tx_curr_desc_q;
+ tx_desc_used = mp->tx_used_desc_q;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- tx_first_desc = mp->tx_first_desc_q;
+-#endif
++
+ p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
+
+- /* XXX Sanity check */
++ /* Sanity check */
+ if (p_tx_desc_used == NULL)
+ return ETH_ERROR;
+
++ /* Stop release. About to overlap the current available Tx descriptor */
++ if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
++ return ETH_END_OF_JOB;
++
+ command_status = p_tx_desc_used->cmd_sts;
+
+ /* Still transmitting... */
+-#ifndef MV64340_CHECKSUM_OFFLOAD_TX
+ if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
+ return ETH_RETRY;
+-#endif
+- /* Stop release. About to overlap the current available Tx descriptor */
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- if (tx_desc_used == tx_first_desc && !mp->tx_resource_err)
+- return ETH_END_OF_JOB;
+-#else
+- if (tx_desc_used == tx_desc_curr && !mp->tx_resource_err)
+- return ETH_END_OF_JOB;
+-#endif
+
+ /* Pass the packet information to the caller */
+ p_pkt_info->cmd_sts = command_status;
+@@ -2515,7 +2684,7 @@
+ mp->tx_skb[tx_desc_used] = NULL;
+
+ /* Update the next descriptor to release. */
+- mp->tx_used_desc_q = (tx_desc_used + 1) % MV64340_TX_QUEUE_SIZE;
++ mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
+
+ /* Any Tx return cancels the Tx resource error status */
+ mp->tx_resource_err = 0;
+@@ -2527,30 +2696,30 @@
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+- * This routine returns the received data to the caller. There is no
+- * data copying during routine operation. All information is returned
+- * using pointer to packet information struct passed from the caller.
+- * If the routine exhausts Rx ring resources then the resource error flag
+- * is set.
++ * This routine returns the received data to the caller. There is no
++ * data copying during routine operation. All information is returned
++ * using pointer to packet information struct passed from the caller.
++ * If the routine exhausts Rx ring resources then the resource error flag
++ * is set.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * struct pkt_info *p_pkt_info User packet buffer.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
++ * struct pkt_info *p_pkt_info User packet buffer.
+ *
+ * OUTPUT:
+- * Rx ring current and used indexes are updated.
++ * Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Rx desc ring.
+ * ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ * ETH_END_OF_JOB if there is no received data.
+- * ETH_OK otherwise.
++ * ETH_OK otherwise.
+ */
+-static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private * mp,
+- struct pkt_info * p_pkt_info)
++static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info)
+ {
+ int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
+- volatile struct eth_rx_desc * p_rx_desc;
++ volatile struct eth_rx_desc *p_rx_desc;
+ unsigned int command_status;
+
+ /* Do not process Rx ring in case of Rx ring resource error */
+@@ -2565,6 +2734,7 @@
+
+ /* The following parameters are used to save readings from memory */
+ command_status = p_rx_desc->cmd_sts;
++ rmb();
+
+ /* Nothing to receive... */
+ if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
+@@ -2577,18 +2747,17 @@
+ p_pkt_info->l4i_chk = p_rx_desc->buf_size;
+
+ /* Clean the return info field to indicate that the packet has been */
+- /* moved to the upper layers */
++ /* moved to the upper layers */
+ mp->rx_skb[rx_curr_desc] = NULL;
+
+ /* Update current index in data structure */
+- rx_next_curr_desc = (rx_curr_desc + 1) % MV64340_RX_QUEUE_SIZE;
++ rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
+ mp->rx_curr_desc_q = rx_next_curr_desc;
+
+ /* Rx descriptors exhausted. Set the Rx ring resource error flag */
+ if (rx_next_curr_desc == rx_used_desc)
+ mp->rx_resource_err = 1;
+
+- mb();
+ return ETH_OK;
+ }
+
+@@ -2596,27 +2765,27 @@
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+- * This routine returns a Rx buffer back to the Rx ring. It retrieves the
+- * next 'used' descriptor and attached the returned buffer to it.
+- * In case the Rx ring was in "resource error" condition, where there are
+- * no available Rx resources, the function resets the resource error flag.
++ * This routine returns a Rx buffer back to the Rx ring. It retrieves the
++ * next 'used' descriptor and attached the returned buffer to it.
++ * In case the Rx ring was in "resource error" condition, where there are
++ * no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+- * struct mv64340_private *mp Ethernet Port Control srtuct.
+- * struct pkt_info *p_pkt_info Information on the returned buffer.
++ * struct mv643xx_private *mp Ethernet Port Control srtuct.
++ * struct pkt_info *p_pkt_info Information on returned buffer.
+ *
+ * OUTPUT:
+ * New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ * ETH_ERROR in case the routine can not access Rx desc ring.
+- * ETH_OK otherwise.
++ * ETH_OK otherwise.
+ */
+-static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private * mp,
+- struct pkt_info * p_pkt_info)
++static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info)
+ {
+ int used_rx_desc; /* Where to return Rx resource */
+- volatile struct eth_rx_desc* p_used_rx_desc;
++ volatile struct eth_rx_desc *p_used_rx_desc;
+
+ /* Get 'used' Rx descriptor */
+ used_rx_desc = mp->rx_used_desc_q;
+@@ -2627,20 +2796,240 @@
+ mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
+
+ /* Flush the write pipe */
+- mb();
+
+ /* Return the descriptor to DMA ownership */
++ wmb();
+ p_used_rx_desc->cmd_sts =
+- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+-
+- /* Flush descriptor and CPU pipe */
+- mb();
++ ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
++ wmb();
+
+ /* Move the used descriptor pointer to the next descriptor */
+- mp->rx_used_desc_q = (used_rx_desc + 1) % MV64340_RX_QUEUE_SIZE;
++ mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
+
+ /* Any Rx return cancels the Rx resource error status */
+ mp->rx_resource_err = 0;
+
+ return ETH_OK;
+ }
++
++/************* Begin ethtool support *************************/
++
++struct mv643xx_stats {
++ char stat_string[ETH_GSTRING_LEN];
++ int sizeof_stat;
++ int stat_offset;
++};
++
++#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
++ offsetof(struct mv643xx_private, m)
++
++static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
++ { "rx_packets", MV643XX_STAT(stats.rx_packets) },
++ { "tx_packets", MV643XX_STAT(stats.tx_packets) },
++ { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
++ { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
++ { "rx_errors", MV643XX_STAT(stats.rx_errors) },
++ { "tx_errors", MV643XX_STAT(stats.tx_errors) },
++ { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
++ { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
++ { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
++ { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
++ { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
++ { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
++ { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
++ { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
++ { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
++ { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
++ { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
++ { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
++ { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
++ { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
++ { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
++ { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
++ { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
++ { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
++ { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
++ { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
++ { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
++ { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
++ { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
++ { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
++ { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
++ { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
++ { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
++ { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
++ { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
++ { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
++ { "collision", MV643XX_STAT(mib_counters.collision) },
++ { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
++};
++
++#define MV643XX_STATS_LEN \
++ sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
++
++static int
++mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
++{
++ struct mv643xx_private *mp = netdev->priv;
++ int port_num = mp->port_num;
++ int autoneg = eth_port_autoneg_supported(port_num);
++ int mode_10_bit;
++ int auto_duplex;
++ int half_duplex = 0;
++ int full_duplex = 0;
++ int auto_speed;
++ int speed_10 = 0;
++ int speed_100 = 0;
++ int speed_1000 = 0;
++
++ u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
++ u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
++
++ mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
++
++ if (mode_10_bit) {
++ ecmd->supported = SUPPORTED_10baseT_Half;
++ } else {
++ ecmd->supported = (SUPPORTED_10baseT_Half |
++ SUPPORTED_10baseT_Full |
++ SUPPORTED_100baseT_Half |
++ SUPPORTED_100baseT_Full |
++ SUPPORTED_1000baseT_Full |
++ (autoneg ? SUPPORTED_Autoneg : 0) |
++ SUPPORTED_TP);
++
++ auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
++ auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
++
++ ecmd->advertising = ADVERTISED_TP;
++
++ if (autoneg) {
++ ecmd->advertising |= ADVERTISED_Autoneg;
++
++ if (auto_duplex) {
++ half_duplex = 1;
++ full_duplex = 1;
++ } else {
++ if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
++ full_duplex = 1;
++ else
++ half_duplex = 1;
++ }
++
++ if (auto_speed) {
++ speed_10 = 1;
++ speed_100 = 1;
++ speed_1000 = 1;
++ } else {
++ if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
++ speed_1000 = 1;
++ else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
++ speed_100 = 1;
++ else
++ speed_10 = 1;
++ }
++
++ if (speed_10 & half_duplex)
++ ecmd->advertising |= ADVERTISED_10baseT_Half;
++ if (speed_10 & full_duplex)
++ ecmd->advertising |= ADVERTISED_10baseT_Full;
++ if (speed_100 & half_duplex)
++ ecmd->advertising |= ADVERTISED_100baseT_Half;
++ if (speed_100 & full_duplex)
++ ecmd->advertising |= ADVERTISED_100baseT_Full;
++ if (speed_1000)
++ ecmd->advertising |= ADVERTISED_1000baseT_Full;
++ }
++ }
++
++ ecmd->port = PORT_TP;
++ ecmd->phy_address = ethernet_phy_get(port_num);
++
++ ecmd->transceiver = XCVR_EXTERNAL;
++
++ if (netif_carrier_ok(netdev)) {
++ if (mode_10_bit)
++ ecmd->speed = SPEED_10;
++ else {
++ if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
++ ecmd->speed = SPEED_1000;
++ else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
++ ecmd->speed = SPEED_100;
++ else
++ ecmd->speed = SPEED_10;
++ }
++
++ if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
++ ecmd->duplex = DUPLEX_FULL;
++ else
++ ecmd->duplex = DUPLEX_HALF;
++ } else {
++ ecmd->speed = -1;
++ ecmd->duplex = -1;
++ }
++
++ ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
++ return 0;
++}
++
++static void
++mv643xx_get_drvinfo(struct net_device *netdev,
++ struct ethtool_drvinfo *drvinfo)
++{
++ strncpy(drvinfo->driver, mv643xx_driver_name, 32);
++ strncpy(drvinfo->version, mv643xx_driver_version, 32);
++ strncpy(drvinfo->fw_version, "N/A", 32);
++ strncpy(drvinfo->bus_info, "mv643xx", 32);
++ drvinfo->n_stats = MV643XX_STATS_LEN;
++}
++
++static int
++mv643xx_get_stats_count(struct net_device *netdev)
++{
++ return MV643XX_STATS_LEN;
++}
++
++static void
++mv643xx_get_ethtool_stats(struct net_device *netdev,
++ struct ethtool_stats *stats, uint64_t *data)
++{
++ struct mv643xx_private *mp = netdev->priv;
++ int i;
++
++ eth_update_mib_counters(mp);
++
++ for(i = 0; i < MV643XX_STATS_LEN; i++) {
++ char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
++ data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
++ sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
++ }
++}
++
++static void
++mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
++{
++ int i;
++
++ switch(stringset) {
++ case ETH_SS_STATS:
++ for (i=0; i < MV643XX_STATS_LEN; i++) {
++ memcpy(data + i * ETH_GSTRING_LEN,
++ mv643xx_gstrings_stats[i].stat_string,
++ ETH_GSTRING_LEN);
++ }
++ break;
++ }
++}
++
++static struct ethtool_ops mv643xx_ethtool_ops = {
++ .get_settings = mv643xx_get_settings,
++ .get_drvinfo = mv643xx_get_drvinfo,
++ .get_link = ethtool_op_get_link,
++ .get_sg = ethtool_op_get_sg,
++ .set_sg = ethtool_op_set_sg,
++ .get_strings = mv643xx_get_strings,
++ .get_stats_count = mv643xx_get_stats_count,
++ .get_ethtool_stats = mv643xx_get_ethtool_stats,
++};
++
++/************* End ethtool support *************************/
+diff -urN linux-2.6.10/drivers/net/mv643xx_eth.h linux-2.6.10-marvell/drivers/net/mv643xx_eth.h
+--- linux-2.6.10/drivers/net/mv643xx_eth.h 2004-12-24 22:34:45.000000000 +0100
++++ linux-2.6.10-marvell/drivers/net/mv643xx_eth.h 2005-03-16 09:23:28.000000000 +0100
+@@ -1,5 +1,5 @@
+-#ifndef __MV64340_ETH_H__
+-#define __MV64340_ETH_H__
++#ifndef __MV643XX_ETH_H__
++#define __MV643XX_ETH_H__
+
+ #include <linux/version.h>
+ #include <linux/module.h>
+@@ -46,17 +46,16 @@
+ * The first part is the high level driver of the gigE ethernet ports.
+ */
+
+-#define ETH_PORT0_IRQ_NUM 48 /* main high register, bit0 */
+-#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1 /* main high register, bit1 */
+-#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2 /* main high register, bit1 */
+-
+-/* Checksum offload for Tx works */
+-#define MV64340_CHECKSUM_OFFLOAD_TX
+-#define MV64340_NAPI
+-#define MV64340_TX_FAST_REFILL
+-#undef MV64340_COAL
++/* Checksum offload for Tx works for most packets, but
++ * fails if previous packet sent did not use hw csum
++ */
++#undef MV643XX_CHECKSUM_OFFLOAD_TX
++#define MV643XX_NAPI
++#define MV643XX_TX_FAST_REFILL
++#undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */
++#undef MV643XX_COAL
+
+-/*
++/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+@@ -65,89 +64,35 @@
+ */
+
+ /* Default TX ring size is 1000 descriptors */
+-#define MV64340_TX_QUEUE_SIZE 1000
++#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
+
+ /* Default RX ring size is 400 descriptors */
+-#define MV64340_RX_QUEUE_SIZE 400
++#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
+
+-#define MV64340_TX_COAL 100
+-#ifdef MV64340_COAL
+-#define MV64340_RX_COAL 100
++#define MV643XX_TX_COAL 100
++#ifdef MV643XX_COAL
++#define MV643XX_RX_COAL 100
+ #endif
+
+-
+ /*
+- * The second part is the low level driver of the gigE ethernet ports. *
++ * The second part is the low level driver of the gigE ethernet ports.
+ */
+
+-
+ /*
+- * Header File for : MV-643xx network interface header
++ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+- * This header file contains macros typedefs and function declaration for
+- * the Marvell Gig Bit Ethernet Controller.
++ * This header file contains macros typedefs and function declaration for
++ * the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+- * None.
++ * None.
+ *
+ */
+
+-/* Default port configuration value */
+-#define PORT_CONFIG_VALUE \
+- ETH_UNICAST_NORMAL_MODE | \
+- ETH_DEFAULT_RX_QUEUE_0 | \
+- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
+- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
+- ETH_RECEIVE_BC_IF_IP | \
+- ETH_RECEIVE_BC_IF_ARP | \
+- ETH_CAPTURE_TCP_FRAMES_DIS | \
+- ETH_CAPTURE_UDP_FRAMES_DIS | \
+- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
+- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
+- ETH_DEFAULT_RX_BPDU_QUEUE_0
+-
+-/* Default port extend configuration value */
+-#define PORT_CONFIG_EXTEND_VALUE \
+- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
+- ETH_PARTITION_DISABLE
+-
+-
+-/* Default sdma control value */
+-#define PORT_SDMA_CONFIG_VALUE \
+- ETH_RX_BURST_SIZE_16_64BIT | \
+- GT_ETH_IPG_INT_RX(0) | \
+- ETH_TX_BURST_SIZE_16_64BIT;
+-
+-#define GT_ETH_IPG_INT_RX(value) \
+- ((value & 0x3fff) << 8)
+-
+-/* Default port serial control value */
+-#define PORT_SERIAL_CONTROL_VALUE \
+- ETH_FORCE_LINK_PASS | \
+- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
+- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
+- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
+- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+- ETH_FORCE_BP_MODE_NO_JAM | \
+- BIT9 | \
+- ETH_DO_NOT_FORCE_LINK_FAIL | \
+- ETH_RETRANSMIT_16_ATTEMPTS | \
+- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
+- ETH_DTE_ADV_0 | \
+- ETH_DISABLE_AUTO_NEG_BYPASS | \
+- ETH_AUTO_NEG_NO_CHANGE | \
+- ETH_MAX_RX_PACKET_9700BYTE | \
+- ETH_CLR_EXT_LOOPBACK | \
+- ETH_SET_FULL_DUPLEX_MODE | \
+- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
+-
+-#define RX_BUFFER_MAX_SIZE 0x4000000
+-#define TX_BUFFER_MAX_SIZE 0x4000000
+-
+ /* MAC accepet/reject macros */
+-#define ACCEPT_MAC_ADDR 0
+-#define REJECT_MAC_ADDR 1
++#define ACCEPT_MAC_ADDR 0
++#define REJECT_MAC_ADDR 1
+
+ /* Buffer offset from buffer pointer */
+ #define RX_BUF_OFFSET 0x2
+@@ -155,277 +100,132 @@
+ /* Gigabit Ethernet Unit Global Registers */
+
+ /* MIB Counters register definitions */
+-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
+-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
+-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
+-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
+-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
+-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
+-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
+-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
+-#define ETH_MIB_FRAMES_64_OCTETS 0x20
+-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
+-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
+-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
+-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
+-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
+-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
+-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
+-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
+-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
+-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
+-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
+-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+-#define ETH_MIB_FC_SENT 0x54
+-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
+-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
+-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
+-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
+-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
+-#define ETH_MIB_JABBER_RECEIVED 0x6c
+-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
+-#define ETH_MIB_BAD_CRC_EVENT 0x74
+-#define ETH_MIB_COLLISION 0x78
+-#define ETH_MIB_LATE_COLLISION 0x7c
++#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
++#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
++#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
++#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
++#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
++#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
++#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
++#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
++#define ETH_MIB_FRAMES_64_OCTETS 0x20
++#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
++#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
++#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
++#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
++#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
++#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
++#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
++#define ETH_MIB_GOOD_FRAMES_SENT 0x40
++#define ETH_MIB_EXCESSIVE_COLLISION 0x44
++#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
++#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
++#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
++#define ETH_MIB_FC_SENT 0x54
++#define ETH_MIB_GOOD_FC_RECEIVED 0x58
++#define ETH_MIB_BAD_FC_RECEIVED 0x5c
++#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
++#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
++#define ETH_MIB_OVERSIZE_RECEIVED 0x68
++#define ETH_MIB_JABBER_RECEIVED 0x6c
++#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
++#define ETH_MIB_BAD_CRC_EVENT 0x74
++#define ETH_MIB_COLLISION 0x78
++#define ETH_MIB_LATE_COLLISION 0x7c
+
+ /* Port serial status reg (PSR) */
+-#define ETH_INTERFACE_GMII_MII 0
+-#define ETH_INTERFACE_PCM BIT0
+-#define ETH_LINK_IS_DOWN 0
+-#define ETH_LINK_IS_UP BIT1
+-#define ETH_PORT_AT_HALF_DUPLEX 0
+-#define ETH_PORT_AT_FULL_DUPLEX BIT2
+-#define ETH_RX_FLOW_CTRL_DISABLED 0
+-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
+-#define ETH_GMII_SPEED_100_10 0
+-#define ETH_GMII_SPEED_1000 BIT4
+-#define ETH_MII_SPEED_10 0
+-#define ETH_MII_SPEED_100 BIT5
+-#define ETH_NO_TX 0
+-#define ETH_TX_IN_PROGRESS BIT7
+-#define ETH_BYPASS_NO_ACTIVE 0
+-#define ETH_BYPASS_ACTIVE BIT8
+-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
+-#define ETH_PORT_AT_PARTITION_STATE BIT9
+-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
+-#define ETH_PORT_TX_FIFO_EMPTY BIT10
+-
+-
+-/* These macros describes the Port configuration reg (Px_cR) bits */
+-#define ETH_UNICAST_NORMAL_MODE 0
+-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
+-#define ETH_DEFAULT_RX_QUEUE_0 0
+-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
+-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
+-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
+-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
+-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
+-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
+-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
+-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
+-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
+-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
+-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
+-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
+-#define ETH_RECEIVE_BC_IF_IP 0
+-#define ETH_REJECT_BC_IF_IP BIT8
+-#define ETH_RECEIVE_BC_IF_ARP 0
+-#define ETH_REJECT_BC_IF_ARP BIT9
+-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
+-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
+-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
+-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
+-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
+-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
+-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
+-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
+-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
+-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
+-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
+-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
+-
+-
+-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+-#define ETH_CLASSIFY_EN BIT0
+-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
+-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
+-#define ETH_PARTITION_DISABLE 0
+-#define ETH_PARTITION_ENABLE BIT2
+-
+-
+-/* Tx/Rx queue command reg (RQCR/TQCR)*/
+-#define ETH_QUEUE_0_ENABLE BIT0
+-#define ETH_QUEUE_1_ENABLE BIT1
+-#define ETH_QUEUE_2_ENABLE BIT2
+-#define ETH_QUEUE_3_ENABLE BIT3
+-#define ETH_QUEUE_4_ENABLE BIT4
+-#define ETH_QUEUE_5_ENABLE BIT5
+-#define ETH_QUEUE_6_ENABLE BIT6
+-#define ETH_QUEUE_7_ENABLE BIT7
+-#define ETH_QUEUE_0_DISABLE BIT8
+-#define ETH_QUEUE_1_DISABLE BIT9
+-#define ETH_QUEUE_2_DISABLE BIT10
+-#define ETH_QUEUE_3_DISABLE BIT11
+-#define ETH_QUEUE_4_DISABLE BIT12
+-#define ETH_QUEUE_5_DISABLE BIT13
+-#define ETH_QUEUE_6_DISABLE BIT14
+-#define ETH_QUEUE_7_DISABLE BIT15
+-
+-
+-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+-#define ETH_RIFB BIT0
+-#define ETH_RX_BURST_SIZE_1_64BIT 0
+-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
+-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
+-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
+-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
+-#define ETH_BLM_RX_NO_SWAP BIT4
+-#define ETH_BLM_RX_BYTE_SWAP 0
+-#define ETH_BLM_TX_NO_SWAP BIT5
+-#define ETH_BLM_TX_BYTE_SWAP 0
+-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
+-#define ETH_DESCRIPTORS_NO_SWAP 0
+-#define ETH_TX_BURST_SIZE_1_64BIT 0
+-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
+-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
+-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
+-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
+-
+-
+-
+-/* These macros describes the Port serial control reg (PSCR) bits */
+-#define ETH_SERIAL_PORT_DISABLE 0
+-#define ETH_SERIAL_PORT_ENABLE BIT0
+-#define ETH_FORCE_LINK_PASS BIT1
+-#define ETH_DO_NOT_FORCE_LINK_PASS 0
+-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
+-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
+-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
+-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
+-#define ETH_ADV_NO_FLOW_CTRL 0
+-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
+-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
+-#define ETH_FORCE_BP_MODE_NO_JAM 0
+-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
+-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
+-#define ETH_FORCE_LINK_FAIL 0
+-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
+-#define ETH_RETRANSMIT_16_ATTEMPTS 0
+-#define ETH_RETRANSMIT_FOREVER BIT11
+-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
+-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
+-#define ETH_DTE_ADV_0 0
+-#define ETH_DTE_ADV_1 BIT14
+-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
+-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
+-#define ETH_AUTO_NEG_NO_CHANGE 0
+-#define ETH_RESTART_AUTO_NEG BIT16
+-#define ETH_MAX_RX_PACKET_1518BYTE 0
+-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
+-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
+-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
+-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
+-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
+-#define ETH_SET_EXT_LOOPBACK BIT20
+-#define ETH_CLR_EXT_LOOPBACK 0
+-#define ETH_SET_FULL_DUPLEX_MODE BIT21
+-#define ETH_SET_HALF_DUPLEX_MODE 0
+-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
+-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+-#define ETH_SET_GMII_SPEED_TO_10_100 0
+-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
+-#define ETH_SET_MII_SPEED_TO_10 0
+-#define ETH_SET_MII_SPEED_TO_100 BIT24
+-
++#define ETH_INTERFACE_GMII_MII 0
++#define ETH_INTERFACE_PCM BIT0
++#define ETH_LINK_IS_DOWN 0
++#define ETH_LINK_IS_UP BIT1
++#define ETH_PORT_AT_HALF_DUPLEX 0
++#define ETH_PORT_AT_FULL_DUPLEX BIT2
++#define ETH_RX_FLOW_CTRL_DISABLED 0
++#define ETH_RX_FLOW_CTRL_ENBALED BIT3
++#define ETH_GMII_SPEED_100_10 0
++#define ETH_GMII_SPEED_1000 BIT4
++#define ETH_MII_SPEED_10 0
++#define ETH_MII_SPEED_100 BIT5
++#define ETH_NO_TX 0
++#define ETH_TX_IN_PROGRESS BIT7
++#define ETH_BYPASS_NO_ACTIVE 0
++#define ETH_BYPASS_ACTIVE BIT8
++#define ETH_PORT_NOT_AT_PARTITION_STATE 0
++#define ETH_PORT_AT_PARTITION_STATE BIT9
++#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
++#define ETH_PORT_TX_FIFO_EMPTY BIT10
++
++#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
++#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
+
+ /* SMI reg */
+-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
+-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
++#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
++#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
+ #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
+-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
++#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
+
+ /* SDMA command status fields macros */
+
+ /* Tx & Rx descriptors status */
+-#define ETH_ERROR_SUMMARY (BIT0)
++#define ETH_ERROR_SUMMARY (BIT0)
+
+ /* Tx & Rx descriptors command */
+-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
++#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
+
+ /* Tx descriptors status */
+-#define ETH_LC_ERROR (0 )
+-#define ETH_UR_ERROR (BIT1 )
+-#define ETH_RL_ERROR (BIT2 )
+-#define ETH_LLC_SNAP_FORMAT (BIT9 )
++#define ETH_LC_ERROR (0 )
++#define ETH_UR_ERROR (BIT1 )
++#define ETH_RL_ERROR (BIT2 )
++#define ETH_LLC_SNAP_FORMAT (BIT9 )
+
+ /* Rx descriptors status */
+-#define ETH_CRC_ERROR (0 )
+-#define ETH_OVERRUN_ERROR (BIT1 )
+-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
+-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
+-#define ETH_VLAN_TAGGED (BIT19)
+-#define ETH_BPDU_FRAME (BIT20)
+-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
+-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
+-#define ETH_OTHER_FRAME_TYPE (BIT22)
+-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
+-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
+-#define ETH_FRAME_HEADER_OK (BIT25)
+-#define ETH_RX_LAST_DESC (BIT26)
+-#define ETH_RX_FIRST_DESC (BIT27)
+-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
+-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
+-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
++#define ETH_CRC_ERROR (0 )
++#define ETH_OVERRUN_ERROR (BIT1 )
++#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
++#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
++#define ETH_VLAN_TAGGED (BIT19)
++#define ETH_BPDU_FRAME (BIT20)
++#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
++#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
++#define ETH_OTHER_FRAME_TYPE (BIT22)
++#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
++#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
++#define ETH_FRAME_HEADER_OK (BIT25)
++#define ETH_RX_LAST_DESC (BIT26)
++#define ETH_RX_FIRST_DESC (BIT27)
++#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
++#define ETH_RX_ENABLE_INTERRUPT (BIT29)
++#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
+
+ /* Rx descriptors byte count */
+-#define ETH_FRAME_FRAGMENTED (BIT2)
++#define ETH_FRAME_FRAGMENTED (BIT2)
+
+ /* Tx descriptors command */
+ #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
+-#define ETH_FRAME_SET_TO_VLAN (BIT15)
+-#define ETH_TCP_FRAME (0 )
+-#define ETH_UDP_FRAME (BIT16)
+-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
+-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
+-#define ETH_ZERO_PADDING (BIT19)
+-#define ETH_TX_LAST_DESC (BIT20)
+-#define ETH_TX_FIRST_DESC (BIT21)
+-#define ETH_GEN_CRC (BIT22)
+-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
+-#define ETH_AUTO_MODE (BIT30)
++#define ETH_FRAME_SET_TO_VLAN (BIT15)
++#define ETH_TCP_FRAME (0 )
++#define ETH_UDP_FRAME (BIT16)
++#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
++#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
++#define ETH_ZERO_PADDING (BIT19)
++#define ETH_TX_LAST_DESC (BIT20)
++#define ETH_TX_FIRST_DESC (BIT21)
++#define ETH_GEN_CRC (BIT22)
++#define ETH_TX_ENABLE_INTERRUPT (BIT23)
++#define ETH_AUTO_MODE (BIT30)
+
+ /* typedefs */
+
+ typedef enum _eth_func_ret_status {
+- ETH_OK, /* Returned as expected. */
+- ETH_ERROR, /* Fundamental error. */
+- ETH_RETRY, /* Could not process request. Try later. */
+- ETH_END_OF_JOB, /* Ring has nothing to process. */
+- ETH_QUEUE_FULL, /* Ring resource error. */
+- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
++ ETH_OK, /* Returned as expected. */
++ ETH_ERROR, /* Fundamental error. */
++ ETH_RETRY, /* Could not process request. Try later.*/
++ ETH_END_OF_JOB, /* Ring has nothing to process. */
++ ETH_QUEUE_FULL, /* Ring resource error. */
++ ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
+ } ETH_FUNC_RET_STATUS;
+
+ typedef enum _eth_target {
+@@ -441,66 +241,103 @@
+ */
+ #if defined(__BIG_ENDIAN)
+ struct eth_rx_desc {
+- u16 byte_cnt; /* Descriptor buffer byte count */
+- u16 buf_size; /* Buffer size */
+- u32 cmd_sts; /* Descriptor command status */
+- u32 next_desc_ptr; /* Next descriptor pointer */
+- u32 buf_ptr; /* Descriptor buffer pointer */
++ u16 byte_cnt; /* Descriptor buffer byte count */
++ u16 buf_size; /* Buffer size */
++ u32 cmd_sts; /* Descriptor command status */
++ u32 next_desc_ptr; /* Next descriptor pointer */
++ u32 buf_ptr; /* Descriptor buffer pointer */
+ };
+
+ struct eth_tx_desc {
+- u16 byte_cnt; /* buffer byte count */
+- u16 l4i_chk; /* CPU provided TCP checksum */
+- u32 cmd_sts; /* Command/status field */
+- u32 next_desc_ptr; /* Pointer to next descriptor */
+- u32 buf_ptr; /* pointer to buffer for this descriptor */
++ u16 byte_cnt; /* buffer byte count */
++ u16 l4i_chk; /* CPU provided TCP checksum */
++ u32 cmd_sts; /* Command/status field */
++ u32 next_desc_ptr; /* Pointer to next descriptor */
++ u32 buf_ptr; /* pointer to buffer for this descriptor*/
+ };
+
+ #elif defined(__LITTLE_ENDIAN)
+ struct eth_rx_desc {
+- u32 cmd_sts; /* Descriptor command status */
+- u16 buf_size; /* Buffer size */
+- u16 byte_cnt; /* Descriptor buffer byte count */
+- u32 buf_ptr; /* Descriptor buffer pointer */
+- u32 next_desc_ptr; /* Next descriptor pointer */
++ u32 cmd_sts; /* Descriptor command status */
++ u16 buf_size; /* Buffer size */
++ u16 byte_cnt; /* Descriptor buffer byte count */
++ u32 buf_ptr; /* Descriptor buffer pointer */
++ u32 next_desc_ptr; /* Next descriptor pointer */
+ };
+
+ struct eth_tx_desc {
+- u32 cmd_sts; /* Command/status field */
+- u16 l4i_chk; /* CPU provided TCP checksum */
+- u16 byte_cnt; /* buffer byte count */
+- u32 buf_ptr; /* pointer to buffer for this descriptor */
+- u32 next_desc_ptr; /* Pointer to next descriptor */
++ u32 cmd_sts; /* Command/status field */
++ u16 l4i_chk; /* CPU provided TCP checksum */
++ u16 byte_cnt; /* buffer byte count */
++ u32 buf_ptr; /* pointer to buffer for this descriptor*/
++ u32 next_desc_ptr; /* Pointer to next descriptor */
+ };
+ #else
+ #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
+ #endif
+
+-/* Unified struct for Rx and Tx operations. The user is not required to */
+-/* be familier with neither Tx nor Rx descriptors. */
++/* Unified struct for Rx and Tx operations. The user is not required to */
++/* be familier with neither Tx nor Rx descriptors. */
+ struct pkt_info {
+- unsigned short byte_cnt; /* Descriptor buffer byte count */
+- unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
+- unsigned int cmd_sts; /* Descriptor command status */
+- dma_addr_t buf_ptr; /* Descriptor buffer pointer */
+- struct sk_buff * return_info; /* User resource return information */
++ unsigned short byte_cnt; /* Descriptor buffer byte count */
++ unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
++ unsigned int cmd_sts; /* Descriptor command status */
++ dma_addr_t buf_ptr; /* Descriptor buffer pointer */
++ struct sk_buff *return_info; /* User resource return information */
+ };
+
+-
+ /* Ethernet port specific infomation */
+
+-struct mv64340_private {
+- int port_num; /* User Ethernet port number */
+- u8 port_mac_addr[6]; /* User defined port MAC address. */
+- u32 port_config; /* User port configuration value */
+- u32 port_config_extend; /* User port config extend value */
+- u32 port_sdma_config; /* User port SDMA config value */
+- u32 port_serial_control; /* User port serial control value */
+- u32 port_tx_queue_command; /* Port active Tx queues summary */
+- u32 port_rx_queue_command; /* Port active Rx queues summary */
++struct mv643xx_mib_counters {
++ u64 good_octets_received;
++ u32 bad_octets_received;
++ u32 internal_mac_transmit_err;
++ u32 good_frames_received;
++ u32 bad_frames_received;
++ u32 broadcast_frames_received;
++ u32 multicast_frames_received;
++ u32 frames_64_octets;
++ u32 frames_65_to_127_octets;
++ u32 frames_128_to_255_octets;
++ u32 frames_256_to_511_octets;
++ u32 frames_512_to_1023_octets;
++ u32 frames_1024_to_max_octets;
++ u64 good_octets_sent;
++ u32 good_frames_sent;
++ u32 excessive_collision;
++ u32 multicast_frames_sent;
++ u32 broadcast_frames_sent;
++ u32 unrec_mac_control_received;
++ u32 fc_sent;
++ u32 good_fc_received;
++ u32 bad_fc_received;
++ u32 undersize_received;
++ u32 fragments_received;
++ u32 oversize_received;
++ u32 jabber_received;
++ u32 mac_receive_error;
++ u32 bad_crc_event;
++ u32 collision;
++ u32 late_collision;
++};
++
++struct mv643xx_private {
++ int port_num; /* User Ethernet port number */
++ u8 port_mac_addr[6]; /* User defined port MAC address.*/
++ u32 port_config; /* User port configuration value*/
++ u32 port_config_extend; /* User port config extend value*/
++ u32 port_sdma_config; /* User port SDMA config value */
++ u32 port_serial_control; /* User port serial control value */
++ u32 port_tx_queue_command; /* Port active Tx queues summary*/
++ u32 port_rx_queue_command; /* Port active Rx queues summary*/
++
++ u32 rx_sram_addr; /* Base address of rx sram area */
++ u32 rx_sram_size; /* Size of rx sram area */
++ u32 tx_sram_addr; /* Base address of tx sram area */
++ u32 tx_sram_size; /* Size of tx sram area */
+
+- int rx_resource_err; /* Rx ring resource error flag */
+- int tx_resource_err; /* Tx ring resource error flag */
++ int rx_resource_err; /* Rx ring resource error flag */
++ int tx_resource_err; /* Tx ring resource error flag */
+
+ /* Tx/Rx rings managment indexes fields. For driver use */
+
+@@ -509,30 +346,32 @@
+
+ /* Next available and first returning Tx resource */
+ int tx_curr_desc_q, tx_used_desc_q;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- int tx_first_desc_q;
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ int tx_first_desc_q;
++ u32 tx_first_command;
+ #endif
+
+-#ifdef MV64340_TX_FAST_REFILL
+- u32 tx_clean_threshold;
++#ifdef MV643XX_TX_FAST_REFILL
++ u32 tx_clean_threshold;
+ #endif
+
+- volatile struct eth_rx_desc * p_rx_desc_area;
+- dma_addr_t rx_desc_dma;
+- unsigned int rx_desc_area_size;
+- struct sk_buff * rx_skb[MV64340_RX_QUEUE_SIZE];
+-
+- volatile struct eth_tx_desc * p_tx_desc_area;
+- dma_addr_t tx_desc_dma;
+- unsigned int tx_desc_area_size;
+- struct sk_buff * tx_skb[MV64340_TX_QUEUE_SIZE];
++ struct eth_rx_desc *p_rx_desc_area;
++ dma_addr_t rx_desc_dma;
++ unsigned int rx_desc_area_size;
++ struct sk_buff **rx_skb;
++
++ struct eth_tx_desc *p_tx_desc_area;
++ dma_addr_t tx_desc_dma;
++ unsigned int tx_desc_area_size;
++ struct sk_buff **tx_skb;
+
+- struct work_struct tx_timeout_task;
++ struct work_struct tx_timeout_task;
+
+ /*
+- * Former struct mv64340_eth_priv members start here
++ * Former struct mv643xx_eth_priv members start here
+ */
+ struct net_device_stats stats;
++ struct mv643xx_mib_counters mib_counters;
+ spinlock_t lock;
+ /* Size of Tx Ring per queue */
+ unsigned int tx_ring_size;
+@@ -544,13 +383,13 @@
+ unsigned int rx_ring_skbs;
+
+ /*
+- * rx_task used to fill RX ring out of bottom half context
++ * rx_task used to fill RX ring out of bottom half context
+ */
+ struct work_struct rx_task;
+
+- /*
+- * Used in case RX Ring is empty, which can be caused when
+- * system does not have resources (skb's)
++ /*
++ * Used in case RX Ring is empty, which can be caused when
++ * system does not have resources (skb's)
+ */
+ struct timer_list timeout;
+ long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
+@@ -563,9 +402,9 @@
+ /* ethernet.h API list */
+
+ /* Port operation control routines */
+-static void eth_port_init(struct mv64340_private *mp);
++static void eth_port_init(struct mv643xx_private *mp);
+ static void eth_port_reset(unsigned int eth_port_num);
+-static int eth_port_start(struct mv64340_private *mp);
++static void eth_port_start(struct mv643xx_private *mp);
+
+ static void ethernet_set_config_reg(unsigned int eth_port_num,
+ unsigned int value);
+@@ -576,26 +415,24 @@
+ unsigned char *p_addr);
+
+ /* PHY and MIB routines */
+-static int ethernet_phy_reset(unsigned int eth_port_num);
++static void ethernet_phy_reset(unsigned int eth_port_num);
++
++static void eth_port_write_smi_reg(unsigned int eth_port_num,
++ unsigned int phy_reg, unsigned int value);
+
+-static int eth_port_write_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg,
+- unsigned int value);
+-
+-static int eth_port_read_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg,
+- unsigned int *value);
++static void eth_port_read_smi_reg(unsigned int eth_port_num,
++ unsigned int phy_reg, unsigned int *value);
+
+ static void eth_clear_mib_counters(unsigned int eth_port_num);
+
+ /* Port data flow control routines */
+-static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
+
+-#endif /* __MV64340_ETH_H__ */
++#endif /* __MV643XX_ETH_H__ */
+diff -urN linux-2.6.10/include/asm-ppc/mv64x60_defs.h linux-2.6.10-marvell/include/asm-ppc/mv64x60_defs.h
+--- linux-2.6.10/include/asm-ppc/mv64x60_defs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.10-marvell/include/asm-ppc/mv64x60_defs.h 2005-03-16 09:23:16.000000000 +0100
+@@ -0,0 +1,929 @@
++/*
++ * include/asm-ppc/gt64260_defs.h
++ *
++ * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
++ * host bridges.
++ *
++ * Author: Mark A. Greer <mgreer@mvista.com>
++ *
++ * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
++ * the terms of the GNU General Public License version 2. This program
++ * is licensed "as is" without any warranty of any kind, whether express
++ * or implied.
++ */
++#ifndef __ASMPPC_MV64x60_DEFS_H
++#define __ASMPPC_MV64x60_DEFS_H
++
++/*
++ * Define the Marvell bridges that are supported
++ */
++#define MV64x60_TYPE_INVALID 0
++#define MV64x60_TYPE_GT64260A 1
++#define MV64x60_TYPE_GT64260B 2
++#define MV64x60_TYPE_MV64360 3
++#define MV64x60_TYPE_MV64361 4
++#define MV64x60_TYPE_MV64362 5
++#define MV64x60_TYPE_MV64460 6
++
++
++/* Revisions of each supported chip */
++#define GT64260_REV_A 0x10
++#define GT64260_REV_B 0x20
++#define MV64360 0x01
++#define MV64460 0x01
++
++/* Minimum window size supported by 64260 is 1MB */
++#define GT64260_WINDOW_SIZE_MIN 0x00100000
++#define MV64360_WINDOW_SIZE_MIN 0x00010000
++
++/* IRQ's for embedded controllers */
++#define MV64x60_IRQ_DEV 1
++#define MV64x60_IRQ_CPU_ERR 3
++#define MV64x60_IRQ_TIMER_0_1 8
++#define MV64x60_IRQ_TIMER_2_3 9
++#define MV64x60_IRQ_TIMER_4_5 10
++#define MV64x60_IRQ_TIMER_6_7 11
++#define MV64x60_IRQ_ETH_0 32
++#define MV64x60_IRQ_ETH_1 33
++#define MV64x60_IRQ_ETH_2 34
++#define MV64x60_IRQ_SDMA_0 36
++#define MV64x60_IRQ_I2C 37
++#define MV64x60_IRQ_BRG 39
++#define MV64x60_IRQ_MPSC_0 40
++#define MV64x60_IRQ_MPSC_1 42
++#define MV64x60_IRQ_COMM 43
++
++#define MV64360_IRQ_PCI0 12
++#define MV64360_IRQ_SRAM_PAR_ERR 13
++#define MV64360_IRQ_PCI1 16
++#define MV64360_IRQ_SDMA_1 38
++
++/* Offsets for register blocks */
++#define GT64260_ENET_PHY_ADDR 0x2000
++#define GT64260_ENET_ESMIR 0x2010
++#define GT64260_ENET_0_OFFSET 0x2400
++#define GT64260_ENET_1_OFFSET 0x2800
++#define GT64260_ENET_2_OFFSET 0x2c00
++#define MV64x60_SDMA_0_OFFSET 0x4000
++#define MV64x60_SDMA_1_OFFSET 0x6000
++#define MV64x60_MPSC_0_OFFSET 0x8000
++#define MV64x60_MPSC_1_OFFSET 0x9000
++#define MV64x60_MPSC_ROUTING_OFFSET 0xb400
++#define MV64x60_SDMA_INTR_OFFSET 0xb800
++#define MV64x60_BRG_0_OFFSET 0xb200
++#define MV64x60_BRG_1_OFFSET 0xb208
++
++/*
++ *****************************************************************************
++ *
++ * CPU Interface Registers
++ *
++ *****************************************************************************
++ */
++
++/* CPU physical address of bridge's registers */
++#define MV64x60_INTERNAL_SPACE_DECODE 0x0068
++#define MV64x60_INTERNAL_SPACE_SIZE 0x10000
++#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000
++
++#define MV64360_CPU_BAR_ENABLE 0x0278
++
++/* CPU Memory Controller Window Registers (4 windows) */
++#define MV64x60_CPU2MEM_WINDOWS 4
++
++#define MV64x60_CPU2MEM_0_BASE 0x0008
++#define MV64x60_CPU2MEM_0_SIZE 0x0010
++#define MV64x60_CPU2MEM_1_BASE 0x0208
++#define MV64x60_CPU2MEM_1_SIZE 0x0210
++#define MV64x60_CPU2MEM_2_BASE 0x0018
++#define MV64x60_CPU2MEM_2_SIZE 0x0020
++#define MV64x60_CPU2MEM_3_BASE 0x0218
++#define MV64x60_CPU2MEM_3_SIZE 0x0220
++
++/* CPU Device Controller Window Registers (4 windows) */
++#define MV64x60_CPU2DEV_WINDOWS 4
++
++#define MV64x60_CPU2DEV_0_BASE 0x0028
++#define MV64x60_CPU2DEV_0_SIZE 0x0030
++#define MV64x60_CPU2DEV_1_BASE 0x0228
++#define MV64x60_CPU2DEV_1_SIZE 0x0230
++#define MV64x60_CPU2DEV_2_BASE 0x0248
++#define MV64x60_CPU2DEV_2_SIZE 0x0250
++#define MV64x60_CPU2DEV_3_BASE 0x0038
++#define MV64x60_CPU2DEV_3_SIZE 0x0040
++
++#define MV64x60_CPU2BOOT_0_BASE 0x0238
++#define MV64x60_CPU2BOOT_0_SIZE 0x0240
++
++#define MV64360_CPU2SRAM_BASE 0x0268
++
++/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
++#define MV64x60_PCI_BUSES 2
++#define MV64x60_PCI_IO_WINDOWS_PER_BUS 1
++#define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4
++
++#define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000
++#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
++#define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000
++#define MV64x60_CPU2PCI_SWAP_WORD 0x03000000
++
++#define MV64x60_CPU2PCI_MEM_REQ64 (1<<27)
++
++#define MV64x60_CPU2PCI0_IO_BASE 0x0048
++#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
++#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
++#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
++#define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080
++#define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088
++#define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258
++#define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260
++#define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280
++#define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288
++
++#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
++#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
++#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
++#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100
++#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328
++#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8
++#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330
++#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300
++#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338
++
++#define MV64x60_CPU2PCI1_IO_BASE 0x0090
++#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
++#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
++#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
++#define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0
++#define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8
++#define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0
++#define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8
++#define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0
++#define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8
++
++#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
++#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
++#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
++#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118
++#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348
++#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310
++#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350
++#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318
++#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358
++
++/* CPU Control Registers */
++#define MV64x60_CPU_CONFIG 0x0000
++#define MV64x60_CPU_MODE 0x0120
++#define MV64x60_CPU_MASTER_CNTL 0x0160
++#define MV64x60_CPU_XBAR_CNTL_LO 0x0150
++#define MV64x60_CPU_XBAR_CNTL_HI 0x0158
++#define MV64x60_CPU_XBAR_TO 0x0168
++
++#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170
++#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178
++
++#define MV64360_CPU_PADS_CALIBRATION 0x03b4
++#define MV64360_CPU_RESET_SAMPLE_LO 0x03c4
++#define MV64360_CPU_RESET_SAMPLE_HI 0x03d4
++
++/* SMP Register Map */
++#define MV64360_WHO_AM_I 0x0200
++#define MV64360_CPU0_DOORBELL 0x0214
++#define MV64360_CPU0_DOORBELL_CLR 0x021c
++#define MV64360_CPU0_DOORBELL_MASK 0x0234
++#define MV64360_CPU1_DOORBELL 0x0224
++#define MV64360_CPU1_DOORBELL_CLR 0x022c
++#define MV64360_CPU1_DOORBELL_MASK 0x023c
++#define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10))
++#define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10))
++#define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08))
++#define MV64360_SEMAPHORE_0 0x0244
++#define MV64360_SEMAPHORE_1 0x024c
++#define MV64360_SEMAPHORE_2 0x0254
++#define MV64360_SEMAPHORE_3 0x025c
++#define MV64360_SEMAPHORE_4 0x0264
++#define MV64360_SEMAPHORE_5 0x026c
++#define MV64360_SEMAPHORE_6 0x0274
++#define MV64360_SEMAPHORE_7 0x027c
++
++/* CPU Sync Barrier Registers */
++#define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0
++#define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8
++
++#define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0
++#define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8
++#define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0
++#define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8
++
++/* CPU Deadlock and Ordering registers (Rev B part only) */
++#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
++#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
++#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
++
++/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
++#define MV64x260_CPU_PROT_WINDOWS 4
++
++#define GT64260_CPU_PROT_ACCPROTECT (1<<16)
++#define GT64260_CPU_PROT_WRPROTECT (1<<17)
++#define GT64260_CPU_PROT_CACHEPROTECT (1<<18)
++
++#define MV64360_CPU_PROT_ACCPROTECT (1<<20)
++#define MV64360_CPU_PROT_WRPROTECT (1<<21)
++#define MV64360_CPU_PROT_CACHEPROTECT (1<<22)
++#define MV64360_CPU_PROT_WIN_ENABLE (1<<31)
++
++#define MV64x60_CPU_PROT_BASE_0 0x0180
++#define MV64x60_CPU_PROT_SIZE_0 0x0188
++#define MV64x60_CPU_PROT_BASE_1 0x0190
++#define MV64x60_CPU_PROT_SIZE_1 0x0198
++#define MV64x60_CPU_PROT_BASE_2 0x01a0
++#define MV64x60_CPU_PROT_SIZE_2 0x01a8
++#define MV64x60_CPU_PROT_BASE_3 0x01b0
++#define MV64x60_CPU_PROT_SIZE_3 0x01b8
++
++#define GT64260_CPU_PROT_BASE_4 0x01c0
++#define GT64260_CPU_PROT_SIZE_4 0x01c8
++#define GT64260_CPU_PROT_BASE_5 0x01d0
++#define GT64260_CPU_PROT_SIZE_5 0x01d8
++#define GT64260_CPU_PROT_BASE_6 0x01e0
++#define GT64260_CPU_PROT_SIZE_6 0x01e8
++#define GT64260_CPU_PROT_BASE_7 0x01f0
++#define GT64260_CPU_PROT_SIZE_7 0x01f8
++
++/* CPU Snoop Control Registers (64260 only) */
++#define GT64260_CPU_SNOOP_WINDOWS 4
++
++#define GT64260_CPU_SNOOP_NONE 0x00000000
++#define GT64260_CPU_SNOOP_WT 0x00010000
++#define GT64260_CPU_SNOOP_WB 0x00020000
++#define GT64260_CPU_SNOOP_MASK 0x00030000
++#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK
++
++#define GT64260_CPU_SNOOP_BASE_0 0x0380
++#define GT64260_CPU_SNOOP_SIZE_0 0x0388
++#define GT64260_CPU_SNOOP_BASE_1 0x0390
++#define GT64260_CPU_SNOOP_SIZE_1 0x0398
++#define GT64260_CPU_SNOOP_BASE_2 0x03a0
++#define GT64260_CPU_SNOOP_SIZE_2 0x03a8
++#define GT64260_CPU_SNOOP_BASE_3 0x03b0
++#define GT64260_CPU_SNOOP_SIZE_3 0x03b8
++
++/* CPU Snoop Control Registers (64360 only) */
++#define MV64360_CPU_SNOOP_WINDOWS 4
++#define MV64360_CPU_SNOOP_NONE 0x00000000
++#define MV64360_CPU_SNOOP_WT 0x00010000
++#define MV64360_CPU_SNOOP_WB 0x00020000
++#define MV64360_CPU_SNOOP_MASK 0x00030000
++#define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK
++
++
++/* CPU Error Report Registers */
++#define MV64x60_CPU_ERR_ADDR_LO 0x0070
++#define MV64x60_CPU_ERR_ADDR_HI 0x0078
++#define MV64x60_CPU_ERR_DATA_LO 0x0128
++#define MV64x60_CPU_ERR_DATA_HI 0x0130
++#define MV64x60_CPU_ERR_PARITY 0x0138
++#define MV64x60_CPU_ERR_CAUSE 0x0140
++#define MV64x60_CPU_ERR_MASK 0x0148
++
++/*
++ *****************************************************************************
++ *
++ * SRAM Cotnroller Registers
++ *
++ *****************************************************************************
++ */
++
++#define MV64360_SRAM_CONFIG 0x0380
++#define MV64360_SRAM_TEST_MODE 0x03f4
++#define MV64360_SRAM_ERR_CAUSE 0x0388
++#define MV64360_SRAM_ERR_ADDR_LO 0x0390
++#define MV64360_SRAM_ERR_ADDR_HI 0x03f8
++#define MV64360_SRAM_ERR_DATA_LO 0x0398
++#define MV64360_SRAM_ERR_DATA_HI 0x03a0
++#define MV64360_SRAM_ERR_PARITY 0x03a8
++
++#define MV64360_SRAM_SIZE 0x00040000 /* 256 KB of SRAM */
++
++/*
++ *****************************************************************************
++ *
++ * SDRAM/MEM Cotnroller Registers
++ *
++ *****************************************************************************
++ */
++
++/* SDRAM Config Registers (64260) */
++#define GT64260_SDRAM_CONFIG 0x0448
++
++/* SDRAM Error Report Registers (64260) */
++#define GT64260_SDRAM_ERR_DATA_LO 0x0484
++#define GT64260_SDRAM_ERR_DATA_HI 0x0480
++#define GT64260_SDRAM_ERR_ADDR 0x0490
++#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488
++#define GT64260_SDRAM_ERR_ECC_CALC 0x048c
++#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494
++#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498
++
++/* SDRAM Config Registers (64360) */
++#define MV64360_SDRAM_CONFIG 0x1400
++
++/* SDRAM Control Registers */
++#define MV64360_D_UNIT_CONTROL_LOW 0x1404
++#define MV64360_D_UNIT_CONTROL_HIGH 0x1424
++
++/* SDRAM Error Report Registers (64360) */
++#define MV64360_SDRAM_ERR_DATA_LO 0x1444
++#define MV64360_SDRAM_ERR_DATA_HI 0x1440
++#define MV64360_SDRAM_ERR_ADDR 0x1450
++#define MV64360_SDRAM_ERR_ECC_RCVD 0x1448
++#define MV64360_SDRAM_ERR_ECC_CALC 0x144c
++#define MV64360_SDRAM_ERR_ECC_CNTL 0x1454
++#define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458
++
++/*
++ *****************************************************************************
++ *
++ * Device/BOOT Cotnroller Registers
++ *
++ *****************************************************************************
++ */
++
++/* Device Control Registers */
++#define MV64x60_DEV_BANK_PARAMS_0 0x045c
++#define MV64x60_DEV_BANK_PARAMS_1 0x0460
++#define MV64x60_DEV_BANK_PARAMS_2 0x0464
++#define MV64x60_DEV_BANK_PARAMS_3 0x0468
++#define MV64x60_DEV_BOOT_PARAMS 0x046c
++#define MV64x60_DEV_IF_CNTL 0x04c0
++#define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8
++#define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc
++#define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4
++
++/* Device Interrupt Registers */
++#define MV64x60_DEV_INTR_CAUSE 0x04d0
++#define MV64x60_DEV_INTR_MASK 0x04d4
++#define MV64x60_DEV_INTR_ERR_ADDR 0x04d8
++
++#define MV64360_DEV_INTR_ERR_DATA 0x04dc
++#define MV64360_DEV_INTR_ERR_PAR 0x04e0
++
++/*
++ *****************************************************************************
++ *
++ * PCI Bridge Interface Registers
++ *
++ *****************************************************************************
++ */
++
++/* PCI Configuration Access Registers */
++#define MV64x60_PCI0_CONFIG_ADDR 0x0cf8
++#define MV64x60_PCI0_CONFIG_DATA 0x0cfc
++#define MV64x60_PCI0_IACK 0x0c34
++
++#define MV64x60_PCI1_CONFIG_ADDR 0x0c78
++#define MV64x60_PCI1_CONFIG_DATA 0x0c7c
++#define MV64x60_PCI1_IACK 0x0cb4
++
++/* PCI Control Registers */
++#define MV64x60_PCI0_CMD 0x0c00
++#define MV64x60_PCI0_MODE 0x0d00
++#define MV64x60_PCI0_TO_RETRY 0x0c04
++#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04
++#define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38
++#define MV64x60_PCI0_ARBITER_CNTL 0x1d00
++#define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08
++#define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c
++#define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04
++#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18
++#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c
++#define MV64x60_PCI0_SYNC_BARRIER 0x1d10
++#define MV64x60_PCI0_P2P_CONFIG 0x1d14
++#define MV64x60_PCI0_INTR_MASK
++
++#define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54
++
++#define MV64x60_PCI1_CMD 0x0c80
++#define MV64x60_PCI1_MODE 0x0d80
++#define MV64x60_PCI1_TO_RETRY 0x0c84
++#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84
++#define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8
++#define MV64x60_PCI1_ARBITER_CNTL 0x1d80
++#define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88
++#define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c
++#define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84
++#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98
++#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c
++#define MV64x60_PCI1_SYNC_BARRIER 0x1d90
++#define MV64x60_PCI1_P2P_CONFIG 0x1d94
++
++#define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4
++
++/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
++#define MV64x60_PCIMODE_CONVENTIONAL 0
++#define MV64x60_PCIMODE_PCIX_66 (1 << 4)
++#define MV64x60_PCIMODE_PCIX_100 (2 << 4)
++#define MV64x60_PCIMODE_PCIX_133 (3 << 4)
++#define MV64x60_PCIMODE_MASK (0x3 << 4)
++
++/* PCI Access Control Regions Registers */
++#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12)
++#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13)
++#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16)
++#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17)
++#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18)
++#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000
++#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000
++#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000
++#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000
++#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
++#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000
++#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000
++#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000
++#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000
++#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28)
++#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29)
++
++#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \
++ GT64260_PCI_ACC_CNTL_DREADEN | \
++ GT64260_PCI_ACC_CNTL_RDPREFETCH | \
++ GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
++ GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
++ GT64260_PCI_ACC_CNTL_MBURST_MASK | \
++ GT64260_PCI_ACC_CNTL_SWAP_MASK | \
++ GT64260_PCI_ACC_CNTL_ACCPROT| \
++ GT64260_PCI_ACC_CNTL_WRPROT)
++
++#define MV64360_PCI_ACC_CNTL_ENABLE (1<<0)
++#define MV64360_PCI_ACC_CNTL_REQ64 (1<<1)
++#define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
++#define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004
++#define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008
++#define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
++#define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4)
++#define MV64360_PCI_ACC_CNTL_WRPROT (1<<5)
++#define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
++#define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040
++#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
++#define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
++#define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
++#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
++#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
++#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
++#define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300
++#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
++#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
++#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
++#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
++#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
++
++#define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \
++ MV64360_PCI_ACC_CNTL_REQ64 | \
++ MV64360_PCI_ACC_CNTL_SNOOP_MASK | \
++ MV64360_PCI_ACC_CNTL_ACCPROT | \
++ MV64360_PCI_ACC_CNTL_WRPROT | \
++ MV64360_PCI_ACC_CNTL_SWAP_MASK | \
++ MV64360_PCI_ACC_CNTL_MBURST_MASK | \
++ MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
++
++#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
++#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
++#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
++#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
++#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
++#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
++#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
++#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
++#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
++#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
++#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
++#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
++#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
++#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
++#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
++#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
++#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
++#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
++
++#define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60
++#define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64
++#define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68
++#define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70
++#define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74
++#define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78
++
++#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
++#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
++#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
++#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
++#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
++#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
++#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
++#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
++#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
++#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
++#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
++#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
++#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
++#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
++#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
++#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
++#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
++#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
++
++#define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0
++#define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4
++#define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8
++#define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0
++#define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4
++#define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8
++
++/* PCI Snoop Control Registers (64260 only) */
++#define GT64260_PCI_SNOOP_NONE 0x00000000
++#define GT64260_PCI_SNOOP_WT 0x00001000
++#define GT64260_PCI_SNOOP_WB 0x00002000
++
++#define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00
++#define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04
++#define GT64260_PCI0_SNOOP_0_SIZE 0x1f08
++#define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10
++#define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14
++#define GT64260_PCI0_SNOOP_1_SIZE 0x1f18
++#define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20
++#define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24
++#define GT64260_PCI0_SNOOP_2_SIZE 0x1f28
++#define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30
++#define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34
++#define GT64260_PCI0_SNOOP_3_SIZE 0x1f38
++
++#define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80
++#define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84
++#define GT64260_PCI1_SNOOP_0_SIZE 0x1f88
++#define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90
++#define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94
++#define GT64260_PCI1_SNOOP_1_SIZE 0x1f98
++#define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0
++#define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4
++#define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8
++#define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0
++#define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4
++#define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8
++
++/* PCI Error Report Registers */
++#define MV64x60_PCI0_ERR_SERR_MASK 0x0c28
++#define MV64x60_PCI0_ERR_ADDR_LO 0x1d40
++#define MV64x60_PCI0_ERR_ADDR_HI 0x1d44
++#define MV64x60_PCI0_ERR_DATA_LO 0x1d48
++#define MV64x60_PCI0_ERR_DATA_HI 0x1d4c
++#define MV64x60_PCI0_ERR_CMD 0x1d50
++#define MV64x60_PCI0_ERR_CAUSE 0x1d58
++#define MV64x60_PCI0_ERR_MASK 0x1d5c
++
++#define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8
++#define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0
++#define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4
++#define MV64x60_PCI1_ERR_DATA_LO 0x1dc8
++#define MV64x60_PCI1_ERR_DATA_HI 0x1dcc
++#define MV64x60_PCI1_ERR_CMD 0x1dd0
++#define MV64x60_PCI1_ERR_CAUSE 0x1dd8
++#define MV64x60_PCI1_ERR_MASK 0x1ddc
++
++/* PCI Slave Address Decoding Registers */
++#define MV64x60_PCI0_MEM_0_SIZE 0x0c08
++#define MV64x60_PCI0_MEM_1_SIZE 0x0d08
++#define MV64x60_PCI0_MEM_2_SIZE 0x0c0c
++#define MV64x60_PCI0_MEM_3_SIZE 0x0d0c
++#define MV64x60_PCI1_MEM_0_SIZE 0x0c88
++#define MV64x60_PCI1_MEM_1_SIZE 0x0d88
++#define MV64x60_PCI1_MEM_2_SIZE 0x0c8c
++#define MV64x60_PCI1_MEM_3_SIZE 0x0d8c
++
++#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
++#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
++
++#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
++#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
++
++#define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48
++#define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48
++#define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c
++#define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c
++#define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50
++#define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50
++#define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58
++#define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54
++#define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54
++#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c
++#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60
++#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64
++#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68
++#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c
++#define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70
++
++#define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8
++#define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8
++#define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc
++#define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc
++#define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0
++#define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0
++#define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8
++#define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4
++#define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4
++#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc
++#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0
++#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4
++#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8
++#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec
++#define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0
++
++/*
++ *****************************************************************************
++ *
++ * ENET Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++/* ENET Controller Window Registers (6 windows) */
++#define MV64360_ENET2MEM_WINDOWS 6
++
++#define MV64360_ENET2MEM_0_BASE 0x2200
++#define MV64360_ENET2MEM_0_SIZE 0x2204
++#define MV64360_ENET2MEM_1_BASE 0x2208
++#define MV64360_ENET2MEM_1_SIZE 0x220c
++#define MV64360_ENET2MEM_2_BASE 0x2210
++#define MV64360_ENET2MEM_2_SIZE 0x2214
++#define MV64360_ENET2MEM_3_BASE 0x2218
++#define MV64360_ENET2MEM_3_SIZE 0x221c
++#define MV64360_ENET2MEM_4_BASE 0x2220
++#define MV64360_ENET2MEM_4_SIZE 0x2224
++#define MV64360_ENET2MEM_5_BASE 0x2228
++#define MV64360_ENET2MEM_5_SIZE 0x222c
++
++#define MV64360_ENET2MEM_SNOOP_NONE 0x00000000
++#define MV64360_ENET2MEM_SNOOP_WT 0x00001000
++#define MV64360_ENET2MEM_SNOOP_WB 0x00002000
++
++#define MV64360_ENET2MEM_BAR_ENABLE 0x2290
++
++#define MV64360_ENET2MEM_ACC_PROT_0 0x2294
++#define MV64360_ENET2MEM_ACC_PROT_1 0x2298
++#define MV64360_ENET2MEM_ACC_PROT_2 0x229c
++
++/*
++ *****************************************************************************
++ *
++ * MPSC Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++/* MPSC Controller Window Registers (4 windows) */
++#define MV64360_MPSC2MEM_WINDOWS 4
++
++#define MV64360_MPSC2MEM_0_BASE 0xf200
++#define MV64360_MPSC2MEM_0_SIZE 0xf204
++#define MV64360_MPSC2MEM_1_BASE 0xf208
++#define MV64360_MPSC2MEM_1_SIZE 0xf20c
++#define MV64360_MPSC2MEM_2_BASE 0xf210
++#define MV64360_MPSC2MEM_2_SIZE 0xf214
++#define MV64360_MPSC2MEM_3_BASE 0xf218
++#define MV64360_MPSC2MEM_3_SIZE 0xf21c
++
++#define MV64360_MPSC_0_REMAP 0xf240
++#define MV64360_MPSC_1_REMAP 0xf244
++
++#define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000
++#define MV64360_MPSC2MEM_SNOOP_WT 0x00001000
++#define MV64360_MPSC2MEM_SNOOP_WB 0x00002000
++
++#define MV64360_MPSC2MEM_BAR_ENABLE 0xf250
++
++#define MV64360_MPSC2MEM_ACC_PROT_0 0xf254
++#define MV64360_MPSC2MEM_ACC_PROT_1 0xf258
++
++#define MV64360_MPSC2REGS_BASE 0xf25c
++
++/*
++ *****************************************************************************
++ *
++ * Timer/Counter Interface Registers
++ *
++ *****************************************************************************
++ */
++
++#define MV64x60_TIMR_CNTR_0 0x0850
++#define MV64x60_TIMR_CNTR_1 0x0854
++#define MV64x60_TIMR_CNTR_2 0x0858
++#define MV64x60_TIMR_CNTR_3 0x085c
++#define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864
++#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868
++#define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c
++
++#define GT64260_TIMR_CNTR_4 0x0950
++#define GT64260_TIMR_CNTR_5 0x0954
++#define GT64260_TIMR_CNTR_6 0x0958
++#define GT64260_TIMR_CNTR_7 0x095c
++#define GT64260_TIMR_CNTR_4_7_CNTL 0x0964
++#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968
++#define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c
++
++/*
++ *****************************************************************************
++ *
++ * Communications Controller
++ *
++ *****************************************************************************
++ */
++
++#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320
++#define GT64260_SER_INIT_LAST_DATA 0xf324
++#define GT64260_SER_INIT_CONTROL 0xf328
++#define GT64260_SER_INIT_STATUS 0xf32c
++
++#define MV64x60_COMM_ARBITER_CNTL 0xf300
++#define MV64x60_COMM_CONFIG 0xb40c
++#define MV64x60_COMM_XBAR_TO 0xf304
++#define MV64x60_COMM_INTR_CAUSE 0xf310
++#define MV64x60_COMM_INTR_MASK 0xf314
++#define MV64x60_COMM_ERR_ADDR 0xf318
++
++#define MV64360_COMM_ARBITER_CNTL 0xf300
++
++/*
++ *****************************************************************************
++ *
++ * IDMA Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++/* IDMA Controller Window Registers (8 windows) */
++#define MV64360_IDMA2MEM_WINDOWS 8
++
++#define MV64360_IDMA2MEM_0_BASE 0x0a00
++#define MV64360_IDMA2MEM_0_SIZE 0x0a04
++#define MV64360_IDMA2MEM_1_BASE 0x0a08
++#define MV64360_IDMA2MEM_1_SIZE 0x0a0c
++#define MV64360_IDMA2MEM_2_BASE 0x0a10
++#define MV64360_IDMA2MEM_2_SIZE 0x0a14
++#define MV64360_IDMA2MEM_3_BASE 0x0a18
++#define MV64360_IDMA2MEM_3_SIZE 0x0a1c
++#define MV64360_IDMA2MEM_4_BASE 0x0a20
++#define MV64360_IDMA2MEM_4_SIZE 0x0a24
++#define MV64360_IDMA2MEM_5_BASE 0x0a28
++#define MV64360_IDMA2MEM_5_SIZE 0x0a2c
++#define MV64360_IDMA2MEM_6_BASE 0x0a30
++#define MV64360_IDMA2MEM_6_SIZE 0x0a34
++#define MV64360_IDMA2MEM_7_BASE 0x0a38
++#define MV64360_IDMA2MEM_7_SIZE 0x0a3c
++
++#define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000
++#define MV64360_IDMA2MEM_SNOOP_WT 0x00001000
++#define MV64360_IDMA2MEM_SNOOP_WB 0x00002000
++
++#define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80
++
++#define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70
++#define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74
++#define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78
++#define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c
++
++#define MV64x60_IDMA_0_OFFSET 0x0800
++#define MV64x60_IDMA_1_OFFSET 0x0804
++#define MV64x60_IDMA_2_OFFSET 0x0808
++#define MV64x60_IDMA_3_OFFSET 0x080c
++#define MV64x60_IDMA_4_OFFSET 0x0900
++#define MV64x60_IDMA_5_OFFSET 0x0904
++#define MV64x60_IDMA_6_OFFSET 0x0908
++#define MV64x60_IDMA_7_OFFSET 0x090c
++
++#define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET)
++#define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET)
++
++#define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860
++#define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960
++
++#define MV64x60_IDMA_0_3_XBAR_TO 0x08d0
++#define MV64x60_IDMA_4_7_XBAR_TO 0x09d0
++
++#define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0
++#define MV64x60_IDMA_0_3_INTR_MASK 0x08c4
++#define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8
++#define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc
++#define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0
++#define MV64x60_IDMA_4_7_INTR_MASK 0x09c4
++#define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8
++#define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc
++
++/*
++ *****************************************************************************
++ *
++ * Watchdog Timer Interface Registers
++ *
++ *****************************************************************************
++ */
++
++#define MV64x60_WDT_WDC 0xb410
++#define MV64x60_WDT_WDV 0xb414
++
++
++/*
++ *****************************************************************************
++ *
++ * General Purpose Pins Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++#define MV64x60_GPP_IO_CNTL 0xf100
++#define MV64x60_GPP_LEVEL_CNTL 0xf110
++#define MV64x60_GPP_VALUE 0xf104
++#define MV64x60_GPP_INTR_CAUSE 0xf108
++#define MV64x60_GPP_INTR_MASK 0xf10c
++#define MV64x60_GPP_VALUE_SET 0xf118
++#define MV64x60_GPP_VALUE_CLR 0xf11c
++
++
++/*
++ *****************************************************************************
++ *
++ * Multi-Purpose Pins Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++#define MV64x60_MPP_CNTL_0 0xf000
++#define MV64x60_MPP_CNTL_1 0xf004
++#define MV64x60_MPP_CNTL_2 0xf008
++#define MV64x60_MPP_CNTL_3 0xf00c
++#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010
++
++#define MV64x60_ETH_BAR_GAP 0x8
++#define MV64x60_ETH_SIZE_REG_GAP 0x8
++#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
++#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4
++
++#define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00
++#define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00
++#define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00
++#define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700
++
++#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
++#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
++#define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000
++#define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800
++
++
++/*
++ *****************************************************************************
++ *
++ * Interrupt Controller Interface Registers
++ *
++ *****************************************************************************
++ */
++
++#define GT64260_IC_OFFSET 0x0c18
++
++#define GT64260_IC_MAIN_CAUSE_LO 0x0c18
++#define GT64260_IC_MAIN_CAUSE_HI 0x0c68
++#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c
++#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c
++#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70
++#define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24
++#define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64
++#define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74
++#define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4
++#define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4
++#define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4
++#define GT64260_IC_CPU_INT_0_MASK 0x0e60
++#define GT64260_IC_CPU_INT_1_MASK 0x0e64
++#define GT64260_IC_CPU_INT_2_MASK 0x0e68
++#define GT64260_IC_CPU_INT_3_MASK 0x0e6c
++
++#define MV64360_IC_OFFSET 0x0000
++
++#define MV64360_IC_MAIN_CAUSE_LO 0x0004
++#define MV64360_IC_MAIN_CAUSE_HI 0x000c
++#define MV64360_IC_CPU0_INTR_MASK_LO 0x0014
++#define MV64360_IC_CPU0_INTR_MASK_HI 0x001c
++#define MV64360_IC_CPU0_SELECT_CAUSE 0x0024
++#define MV64360_IC_CPU1_INTR_MASK_LO 0x0034
++#define MV64360_IC_CPU1_INTR_MASK_HI 0x003c
++#define MV64360_IC_CPU1_SELECT_CAUSE 0x0044
++#define MV64360_IC_INT0_MASK_LO 0x0054
++#define MV64360_IC_INT0_MASK_HI 0x005c
++#define MV64360_IC_INT0_SELECT_CAUSE 0x0064
++#define MV64360_IC_INT1_MASK_LO 0x0074
++#define MV64360_IC_INT1_MASK_HI 0x007c
++#define MV64360_IC_INT1_SELECT_CAUSE 0x0084
++
++#endif /* __ASMPPC_MV64x60_DEFS_H */
+diff -urN linux-2.6.10/include/asm-ppc/mv64x60.h linux-2.6.10-marvell/include/asm-ppc/mv64x60.h
+--- linux-2.6.10/include/asm-ppc/mv64x60.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.10-marvell/include/asm-ppc/mv64x60.h 2005-03-16 09:23:16.000000000 +0100
+@@ -0,0 +1,345 @@
++/*
++ * include/asm-ppc/mv64x60.h
++ *
++ * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
++ *
++ * Author: Mark A. Greer <mgreer@mvista.com>
++ *
++ * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
++ * the terms of the GNU General Public License version 2. This program
++ * is licensed "as is" without any warranty of any kind, whether express
++ * or implied.
++ */
++#ifndef __ASMPPC_MV64x60_H
++#define __ASMPPC_MV64x60_H
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/pci.h>
++#include <linux/slab.h>
++#include <linux/config.h>
++
++#include <asm/byteorder.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++#include <asm/machdep.h>
++#include <asm/pci-bridge.h>
++#include <asm/mv64x60_defs.h>
++
++extern u8 mv64x60_pci_exclude_bridge;
++
++extern spinlock_t mv64x60_lock;
++
++/* 32-bit Window table entry defines */
++#define MV64x60_CPU2MEM_0_WIN 0
++#define MV64x60_CPU2MEM_1_WIN 1
++#define MV64x60_CPU2MEM_2_WIN 2
++#define MV64x60_CPU2MEM_3_WIN 3
++#define MV64x60_CPU2DEV_0_WIN 4
++#define MV64x60_CPU2DEV_1_WIN 5
++#define MV64x60_CPU2DEV_2_WIN 6
++#define MV64x60_CPU2DEV_3_WIN 7
++#define MV64x60_CPU2BOOT_WIN 8
++#define MV64x60_CPU2PCI0_IO_WIN 9
++#define MV64x60_CPU2PCI0_MEM_0_WIN 10
++#define MV64x60_CPU2PCI0_MEM_1_WIN 11
++#define MV64x60_CPU2PCI0_MEM_2_WIN 12
++#define MV64x60_CPU2PCI0_MEM_3_WIN 13
++#define MV64x60_CPU2PCI1_IO_WIN 14
++#define MV64x60_CPU2PCI1_MEM_0_WIN 15
++#define MV64x60_CPU2PCI1_MEM_1_WIN 16
++#define MV64x60_CPU2PCI1_MEM_2_WIN 17
++#define MV64x60_CPU2PCI1_MEM_3_WIN 18
++#define MV64x60_CPU2SRAM_WIN 19
++#define MV64x60_CPU2PCI0_IO_REMAP_WIN 20
++#define MV64x60_CPU2PCI1_IO_REMAP_WIN 21
++#define MV64x60_CPU_PROT_0_WIN 22
++#define MV64x60_CPU_PROT_1_WIN 23
++#define MV64x60_CPU_PROT_2_WIN 24
++#define MV64x60_CPU_PROT_3_WIN 25
++#define MV64x60_CPU_SNOOP_0_WIN 26
++#define MV64x60_CPU_SNOOP_1_WIN 27
++#define MV64x60_CPU_SNOOP_2_WIN 28
++#define MV64x60_CPU_SNOOP_3_WIN 29
++#define MV64x60_PCI02MEM_REMAP_0_WIN 30
++#define MV64x60_PCI02MEM_REMAP_1_WIN 31
++#define MV64x60_PCI02MEM_REMAP_2_WIN 32
++#define MV64x60_PCI02MEM_REMAP_3_WIN 33
++#define MV64x60_PCI12MEM_REMAP_0_WIN 34
++#define MV64x60_PCI12MEM_REMAP_1_WIN 35
++#define MV64x60_PCI12MEM_REMAP_2_WIN 36
++#define MV64x60_PCI12MEM_REMAP_3_WIN 37
++#define MV64x60_ENET2MEM_0_WIN 38
++#define MV64x60_ENET2MEM_1_WIN 39
++#define MV64x60_ENET2MEM_2_WIN 40
++#define MV64x60_ENET2MEM_3_WIN 41
++#define MV64x60_ENET2MEM_4_WIN 42
++#define MV64x60_ENET2MEM_5_WIN 43
++#define MV64x60_MPSC2MEM_0_WIN 44
++#define MV64x60_MPSC2MEM_1_WIN 45
++#define MV64x60_MPSC2MEM_2_WIN 46
++#define MV64x60_MPSC2MEM_3_WIN 47
++#define MV64x60_IDMA2MEM_0_WIN 48
++#define MV64x60_IDMA2MEM_1_WIN 49
++#define MV64x60_IDMA2MEM_2_WIN 50
++#define MV64x60_IDMA2MEM_3_WIN 51
++#define MV64x60_IDMA2MEM_4_WIN 52
++#define MV64x60_IDMA2MEM_5_WIN 53
++#define MV64x60_IDMA2MEM_6_WIN 54
++#define MV64x60_IDMA2MEM_7_WIN 55
++
++#define MV64x60_32BIT_WIN_COUNT 56
++
++/* 64-bit Window table entry defines */
++#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0
++#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1
++#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2
++#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3
++#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4
++#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5
++#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6
++#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7
++#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8
++#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9
++#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10
++#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11
++#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12
++#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13
++#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14
++#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15
++#define MV64x60_PCI02MEM_SNOOP_0_WIN 16
++#define MV64x60_PCI02MEM_SNOOP_1_WIN 17
++#define MV64x60_PCI02MEM_SNOOP_2_WIN 18
++#define MV64x60_PCI02MEM_SNOOP_3_WIN 19
++#define MV64x60_PCI12MEM_SNOOP_0_WIN 20
++#define MV64x60_PCI12MEM_SNOOP_1_WIN 21
++#define MV64x60_PCI12MEM_SNOOP_2_WIN 22
++#define MV64x60_PCI12MEM_SNOOP_3_WIN 23
++
++#define MV64x60_64BIT_WIN_COUNT 24
++
++/*
++ * Define a structure that's used to pass in config information to the
++ * core routines.
++ */
++struct mv64x60_pci_window {
++ u32 cpu_base;
++ u32 pci_base_hi;
++ u32 pci_base_lo;
++ u32 size;
++ u32 swap;
++};
++
++struct mv64x60_pci_info {
++ u8 enable_bus; /* allow access to this PCI bus? */
++
++ struct mv64x60_pci_window pci_io;
++ struct mv64x60_pci_window pci_mem[3];
++
++ u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
++ u32 snoop_options[MV64x60_CPU2MEM_WINDOWS];
++ u16 pci_cmd_bits;
++ u16 latency_timer;
++};
++
++struct mv64x60_setup_info {
++ u32 phys_reg_base;
++ u32 window_preserve_mask_32_hi;
++ u32 window_preserve_mask_32_lo;
++ u32 window_preserve_mask_64;
++
++ u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
++ u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
++ u32 enet_options[MV64x60_CPU2MEM_WINDOWS];
++ u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS];
++ u32 idma_options[MV64x60_CPU2MEM_WINDOWS];
++
++ struct mv64x60_pci_info pci_0;
++ struct mv64x60_pci_info pci_1;
++};
++
++/* Define what the top bits in the extra member of a window entry means. */
++#define MV64x60_EXTRA_INVALID 0x00000000
++#define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000
++#define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000
++#define MV64x60_EXTRA_ENET_ENAB 0x30000000
++#define MV64x60_EXTRA_MPSC_ENAB 0x40000000
++#define MV64x60_EXTRA_IDMA_ENAB 0x50000000
++#define MV64x60_EXTRA_PCIACC_ENAB 0x60000000
++
++#define MV64x60_EXTRA_MASK 0xf0000000
++
++/*
++ * Define the 'handle' struct that will be passed between the 64x60 core
++ * code and the platform-specific code that will use it. The handle
++ * will contain pointers to chip-specific routines & information.
++ */
++struct mv64x60_32bit_window {
++ u32 base_reg;
++ u32 size_reg;
++ u8 base_bits;
++ u8 size_bits;
++ u32 (*get_from_field)(u32 val, u32 num_bits);
++ u32 (*map_to_field)(u32 val, u32 num_bits);
++ u32 extra;
++};
++
++struct mv64x60_64bit_window {
++ u32 base_hi_reg;
++ u32 base_lo_reg;
++ u32 size_reg;
++ u8 base_lo_bits;
++ u8 size_bits;
++ u32 (*get_from_field)(u32 val, u32 num_bits);
++ u32 (*map_to_field)(u32 val, u32 num_bits);
++ u32 extra;
++};
++
++typedef struct mv64x60_handle mv64x60_handle_t;
++struct mv64x60_chip_info {
++ u32 (*translate_size)(u32 base, u32 size, u32 num_bits);
++ u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits);
++ void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
++ u32 window, u32 base);
++ void (*set_pci2regs_window)(struct mv64x60_handle *bh,
++ struct pci_controller *hose, u32 bus, u32 base);
++ u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
++ void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
++ void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
++ void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
++ void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
++ void (*disable_all_windows)(mv64x60_handle_t *bh,
++ struct mv64x60_setup_info *si);
++ void (*config_io2mem_windows)(mv64x60_handle_t *bh,
++ struct mv64x60_setup_info *si,
++ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
++ void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
++ void (*chip_specific_init)(mv64x60_handle_t *bh,
++ struct mv64x60_setup_info *si);
++
++ struct mv64x60_32bit_window *window_tab_32bit;
++ struct mv64x60_64bit_window *window_tab_64bit;
++};
++
++struct mv64x60_handle {
++ u32 type; /* type of bridge */
++ u32 rev; /* revision of bridge */
++ void *v_base; /* virtual base addr of bridge regs */
++ phys_addr_t p_base; /* physical base addr of bridge regs */
++
++ u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/
++ u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/
++
++ u32 io_base_a; /* vaddr of pci 0's I/O space */
++ u32 io_base_b; /* vaddr of pci 1's I/O space */
++
++ struct pci_controller *hose_a;
++ struct pci_controller *hose_b;
++
++ struct mv64x60_chip_info *ci; /* chip/bridge-specific info */
++};
++
++
++/* Define I/O routines for accessing registers on the 64x60 bridge. */
++extern inline void
++mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
++ ulong flags;
++
++ spin_lock_irqsave(&mv64x60_lock, flags);
++ out_le32(bh->v_base + offset, val);
++ spin_unlock_irqrestore(&mv64x60_lock, flags);
++}
++
++extern inline u32
++mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
++ ulong flags;
++ u32 reg;
++
++ spin_lock_irqsave(&mv64x60_lock, flags);
++ reg = in_le32(bh->v_base + offset);
++ spin_unlock_irqrestore(&mv64x60_lock, flags);
++ return reg;
++}
++
++extern inline void
++mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
++{
++ u32 reg;
++ ulong flags;
++
++ spin_lock_irqsave(&mv64x60_lock, flags);
++ reg = in_le32(bh->v_base + offs) & (~mask);
++ reg |= data & mask;
++ out_le32(bh->v_base + offs, reg);
++ spin_unlock_irqrestore(&mv64x60_lock, flags);
++}
++
++#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
++#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
++
++
++/* Externally visible function prototypes */
++int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
++u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
++void mv64x60_early_init(struct mv64x60_handle *bh,
++ struct mv64x60_setup_info *si);
++void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
++ u32 cfg_data, struct pci_controller **hose);
++int mv64x60_get_type(struct mv64x60_handle *bh);
++int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
++void *mv64x60_get_bridge_vbase(void);
++u32 mv64x60_get_bridge_type(void);
++u32 mv64x60_get_bridge_rev(void);
++void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
++ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
++void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
++ struct mv64x60_setup_info *si,
++ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
++void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
++ struct mv64x60_pci_info *pi, u32 bus);
++void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
++ struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
++ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
++void mv64x60_config_resources(struct pci_controller *hose,
++ struct mv64x60_pci_info *pi, u32 io_base);
++void mv64x60_config_pci_params(struct pci_controller *hose,
++ struct mv64x60_pci_info *pi);
++void mv64x60_pd_fixup(struct mv64x60_handle *bh,
++ struct platform_device *pd_devs[], u32 entries);
++void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
++ u32 *base, u32 *size);
++void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
++ u32 size, u32 other_bits);
++void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
++ u32 *base_hi, u32 *base_lo, u32 *size);
++void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
++ u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
++void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
++int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
++
++
++void gt64260_init_irq(void);
++int gt64260_get_irq(struct pt_regs *regs);
++void mv64360_init_irq(void);
++int mv64360_get_irq(struct pt_regs *regs);
++
++u32 mv64x60_mask(u32 val, u32 num_bits);
++u32 mv64x60_shift_left(u32 val, u32 num_bits);
++u32 mv64x60_shift_right(u32 val, u32 num_bits);
++u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
++ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
++
++void mv64x60_progress_init(u32 base);
++void mv64x60_mpsc_progress(char *s, unsigned short hex);
++
++extern struct mv64x60_32bit_window
++ gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
++extern struct mv64x60_64bit_window
++ gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
++extern struct mv64x60_32bit_window
++ mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
++extern struct mv64x60_64bit_window
++ mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
++
++#endif /* __ASMPPC_MV64x60_H */
+diff -urN linux-2.6.10/include/linux/mv643xx.h linux-2.6.10-marvell/include/linux/mv643xx.h
+--- linux-2.6.10/include/linux/mv643xx.h 2004-12-24 22:35:24.000000000 +0100
++++ linux-2.6.10-marvell/include/linux/mv643xx.h 2005-03-16 09:23:28.000000000 +0100
+@@ -1,5 +1,5 @@
+ /*
+- * mv64340.h - MV-64340 Internal registers definition file.
++ * mv643xx.h - MV-643XX Internal registers definition file.
+ *
+ * Copyright 2002 Momentum Computer, Inc.
+ * Author: Matthew Dharm <mdharm@momenco.com>
+@@ -10,11 +10,14 @@
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+-#ifndef __ASM_MV64340_H
+-#define __ASM_MV64340_H
++#ifndef __ASM_MV643XX_H
++#define __ASM_MV643XX_H
+
++#ifdef __MIPS__
+ #include <asm/addrspace.h>
+ #include <asm/marvell.h>
++#endif
++#include <asm/types.h>
+
+ /****************************************/
+ /* Processor Address Space */
+@@ -659,116 +662,119 @@
+ /* Ethernet Unit Registers */
+ /****************************************/
+
+-#define MV64340_ETH_PHY_ADDR_REG 0x2000
+-#define MV64340_ETH_SMI_REG 0x2004
+-#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
+-#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c
+-#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
+-#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
+-#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc
+-#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094
+-#define MV64340_ETH_BAR_0 0x2200
+-#define MV64340_ETH_BAR_1 0x2208
+-#define MV64340_ETH_BAR_2 0x2210
+-#define MV64340_ETH_BAR_3 0x2218
+-#define MV64340_ETH_BAR_4 0x2220
+-#define MV64340_ETH_BAR_5 0x2228
+-#define MV64340_ETH_SIZE_REG_0 0x2204
+-#define MV64340_ETH_SIZE_REG_1 0x220c
+-#define MV64340_ETH_SIZE_REG_2 0x2214
+-#define MV64340_ETH_SIZE_REG_3 0x221c
+-#define MV64340_ETH_SIZE_REG_4 0x2224
+-#define MV64340_ETH_SIZE_REG_5 0x222c
+-#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230
+-#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
+-#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290
+-#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
+-#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
+-#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
+-#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
+-#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
+-#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
+-#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
+-#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
+-#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10))
+-#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10))
+-#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10))
+-#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10))
+-#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10))
+-#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10))
+-#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10))
+-#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
+-#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
+-#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
+-#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
+-#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
+-#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
+-#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
+-#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
+-#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
+-#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
+-#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
+-#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
+-#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
+-#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
+-#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
+-#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
++#define MV643XX_ETH_SHARED_REGS 0x2000
++#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
++
++#define MV643XX_ETH_PHY_ADDR_REG 0x2000
++#define MV643XX_ETH_SMI_REG 0x2004
++#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
++#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
++#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
++#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
++#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
++#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
++#define MV643XX_ETH_BAR_0 0x2200
++#define MV643XX_ETH_BAR_1 0x2208
++#define MV643XX_ETH_BAR_2 0x2210
++#define MV643XX_ETH_BAR_3 0x2218
++#define MV643XX_ETH_BAR_4 0x2220
++#define MV643XX_ETH_BAR_5 0x2228
++#define MV643XX_ETH_SIZE_REG_0 0x2204
++#define MV643XX_ETH_SIZE_REG_1 0x220c
++#define MV643XX_ETH_SIZE_REG_2 0x2214
++#define MV643XX_ETH_SIZE_REG_3 0x221c
++#define MV643XX_ETH_SIZE_REG_4 0x2224
++#define MV643XX_ETH_SIZE_REG_5 0x222c
++#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
++#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
++#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
++#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
++#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
++#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
++#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
++#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
++#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
++#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
++#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
++#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
++#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
++#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
++#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
++#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
++#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
++#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
++#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
++#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
++#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
++#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
++#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
++#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
++#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
++#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
++#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
++#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
++#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
++#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
++#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
++#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
+
+ /*******************************************/
+ /* CUNIT Registers */
+@@ -1036,4 +1042,267 @@
+
+ extern void mv64340_irq_init(unsigned int base);
+
+-#endif /* __ASM_MV64340_H */
++/* MPSC Platform Device, Driver Data (Shared register regions) */
++#define MPSC_SHARED_NAME "mpsc_shared"
++
++#define MPSC_ROUTING_BASE_ORDER 0
++#define MPSC_SDMA_INTR_BASE_ORDER 1
++
++#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
++#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
++
++struct mpsc_shared_pdata {
++ u32 mrr_val;
++ u32 rcrr_val;
++ u32 tcrr_val;
++ u32 intr_cause_val;
++ u32 intr_mask_val;
++};
++
++/* MPSC Platform Device, Driver Data */
++#define MPSC_CTLR_NAME "mpsc"
++
++#define MPSC_BASE_ORDER 0
++#define MPSC_SDMA_BASE_ORDER 1
++#define MPSC_BRG_BASE_ORDER 2
++
++#define MPSC_REG_BLOCK_SIZE 0x0038
++#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
++#define MPSC_BRG_REG_BLOCK_SIZE 0x0008
++
++struct mpsc_pdata {
++ u8 mirror_regs;
++ u8 cache_mgmt;
++ u8 max_idle;
++ int default_baud;
++ int default_bits;
++ int default_parity;
++ int default_flow;
++ u32 chr_1_val;
++ u32 chr_2_val;
++ u32 chr_10_val;
++ u32 mpcr_val;
++ u32 bcr_val;
++ u8 brg_can_tune;
++ u8 brg_clk_src;
++ u32 brg_clk_freq;
++};
++
++/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
++#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
++#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
++#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
++#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
++#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
++#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
++#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
++
++#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_UNICAST_NORMAL_MODE | \
++ MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
++ MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
++ MV643XX_ETH_RECEIVE_BC_IF_IP | \
++ MV643XX_ETH_RECEIVE_BC_IF_ARP | \
++ MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
++ MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
++ MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
++
++/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
++#define MV643XX_ETH_CLASSIFY_EN (1<<0)
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
++#define MV643XX_ETH_PARTITION_DISABLE 0
++#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
++
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
++ MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
++ MV643XX_ETH_PARTITION_DISABLE
++
++/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
++#define MV643XX_ETH_RIFB (1<<0)
++#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
++#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
++#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
++#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
++#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
++#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
++#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
++#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
++#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
++#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
++#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
++#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
++#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
++#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
++
++#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
++
++#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
++ MV643XX_ETH_IPG_INT_RX(0) | \
++ MV643XX_ETH_TX_BURST_SIZE_4_64BIT
++
++/* These macros describe Ethernet Port serial control reg (PSCR) bits */
++#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
++#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
++#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
++#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
++#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
++#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
++#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
++#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
++#define MV643XX_ETH_FORCE_LINK_FAIL 0
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
++#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
++#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
++#define MV643XX_ETH_DTE_ADV_0 0
++#define MV643XX_ETH_DTE_ADV_1 (1<<14)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
++#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
++#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
++#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
++#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
++#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
++#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
++#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
++#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
++#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
++#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
++#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
++#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
++#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
++#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
++#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
++#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
++
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
++ MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
++ MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
++ MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
++ (1<<9) /* reserved */ | \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
++ MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
++ MV643XX_ETH_DTE_ADV_0 | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
++ MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
++ MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
++ MV643XX_ETH_CLR_EXT_LOOPBACK | \
++ MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
++ MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
++
++/* These macros describe Ethernet Serial Status reg (PSR) bits */
++#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
++#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
++#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
++#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
++#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
++#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
++/* PSR bit 6 is undocumented */
++#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
++#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
++#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
++#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
++/* PSR bits 11-31 are reserved */
++
++#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
++#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
++
++#define MV643XX_ETH_DESC_SIZE 64
++
++#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
++#define MV643XX_ETH_NAME "mv643xx_eth"
++
++struct mv643xx_eth_platform_data {
++ /*
++ * Non-values for mac_addr, phy_addr, port_config, etc.
++ * override the default value. Setting the corresponding
++ * force_* field, causes the default value to be overridden
++ * even when zero.
++ */
++ unsigned int force_phy_addr:1;
++ unsigned int force_port_config:1;
++ unsigned int force_port_config_extend:1;
++ unsigned int force_port_sdma_config:1;
++ unsigned int force_port_serial_control:1;
++ int phy_addr;
++ char *mac_addr; /* pointer to mac address */
++ u32 port_config;
++ u32 port_config_extend;
++ u32 port_sdma_config;
++ u32 port_serial_control;
++ u32 tx_queue_size;
++ u32 rx_queue_size;
++ u32 tx_sram_addr;
++ u32 tx_sram_size;
++ u32 rx_sram_addr;
++ u32 rx_sram_size;
++};
++
++#endif /* __ASM_MV643XX_H */
Copied: trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-eth-pegasos.dpatch (from rev 2654, trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-mv643xx-eth-pegasos.dpatch)
===================================================================
--- trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-mv643xx-eth-pegasos.dpatch 2005-03-08 19:53:02 UTC (rev 2654)
+++ trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/powerpc-mv643xx-eth-pegasos.dpatch 2005-03-16 10:22:58 UTC (rev 2724)
@@ -0,0 +1,176 @@
+#! /bin/sh -e
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Description: Powerpc/pegasos platform suport for mv643xx_eth gigabit ethernet driver.
+## DP: Patch authors: Dale Farnsworth <dale@farnsworth.org>, Sven Luther <sl@bplan-gmbh.de>
+## DP: Upstream status: submitted, planned for 2.6.12
+
+. $(dirname $0)/DPATCH
+
+@DPATCH@
+diff -urN linux-2.6.10-pegasos/arch/ppc/platforms/chrp_pci.c linux-2.6.10-pegasos-marvell/arch/ppc/platforms/chrp_pci.c
+--- linux-2.6.10-pegasos/arch/ppc/platforms/chrp_pci.c 2005-03-16 10:52:31.499243024 +0100
++++ linux-2.6.10-pegasos-marvell/arch/ppc/platforms/chrp_pci.c 2005-03-16 11:01:12.267074280 +0100
+@@ -153,19 +153,25 @@
+ return 1;
+ }
+
++extern int __init mv643xx_eth_add_pds(void);
++
+ void __init
+ chrp_pcibios_fixup(void)
+ {
+ struct pci_dev *dev = NULL;
+ struct device_node *np;
+
+- /* PCI interrupts are controlled by the OpenPIC */
+- for_each_pci_dev(dev) {
+- np = pci_device_to_OF_node(dev);
+- if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
+- dev->irq = np->intrs[0].line;
+- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+- }
++ if (_chrp_type != _CHRP_Pegasos) {
++ /* PCI interrupts are controlled by the OpenPIC */
++ for_each_pci_dev(dev) {
++ np = pci_device_to_OF_node(dev);
++ if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
++ dev->irq = np->intrs[0].line;
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++ }
++
++ /* Let's search for marvel 643xx northbridges and do presetup if found */
++ mv643xx_eth_add_pds();
+ }
+
+ #define PRG_CL_RESET_VALID 0x00010000
+@@ -303,8 +309,5 @@
+ }
+ }
+
+- if (is_pegasos)
+- ppc_md.pcibios_fixup = NULL;
+- else
+- ppc_md.pcibios_fixup = chrp_pcibios_fixup;
++ ppc_md.pcibios_fixup = chrp_pcibios_fixup;
+ }
+diff -urN linux-2.6.10-pegasos/arch/ppc/platforms/Makefile linux-2.6.10-pegasos-marvell/arch/ppc/platforms/Makefile
+--- linux-2.6.10-pegasos/arch/ppc/platforms/Makefile 2004-12-24 22:35:49.000000000 +0100
++++ linux-2.6.10-pegasos-marvell/arch/ppc/platforms/Makefile 2005-03-16 10:53:30.681245992 +0100
+@@ -12,7 +12,8 @@
+ obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \
+ pmac_feature.o pmac_pci.o pmac_sleep.o \
+ pmac_low_i2c.o
+-obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o
++obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \
++ mv643xx_eth_pegasos.o
+ obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
+ ifeq ($(CONFIG_PPC_PMAC),y)
+ obj-$(CONFIG_NVRAM) += pmac_nvram.o
+diff -urN linux-2.6.10-pegasos/arch/ppc/platforms/mv643xx_eth_pegasos.c linux-2.6.10-pegasos-marvell/arch/ppc/platforms/mv643xx_eth_pegasos.c
+--- linux-2.6.10-pegasos/arch/ppc/platforms/mv643xx_eth_pegasos.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.10-pegasos-marvell/arch/ppc/platforms/mv643xx_eth_pegasos.c 2005-03-16 10:46:45.000000000 +0100
+@@ -0,0 +1,103 @@
++/*
++ * arch/ppc/platforms/mv643xx_eth_pegasos.c
++ *
++ * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
++ * Thanks to :
++ * Dale Farnsworth <dale@farnsworth.org>
++ * Mark A. Greer <mgreer@mvista.com>
++ * Nicolas DET <nd@bplan-gmbh.de>
++ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
++ * And anyone else who helped me on this.
++ */
++
++#include <linux/types.h>
++#include <asm/prom.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/device.h>
++#include <linux/mv643xx.h>
++#include <linux/pci_ids.h>
++
++/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
++static struct resource mv643xx_eth_shared_resources[] = {
++ [0] = {
++ .name = "ethernet shared base",
++ .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
++ .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
++ MV643XX_ETH_SHARED_REGS_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device mv643xx_eth_shared_device = {
++ .name = MV643XX_ETH_SHARED_NAME,
++ .id = 0,
++ .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
++ .resource = mv643xx_eth_shared_resources,
++};
++
++#ifdef CONFIG_MV643XX_ETH_0
++static struct resource mv643xx_eth0_resources[] = {
++ [0] = {
++ .name = "eth0 irq",
++ .start = 9,
++ .end = 9,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct mv643xx_eth_platform_data eth0_pd;
++
++static struct platform_device eth0_device = {
++ .name = MV643XX_ETH_NAME,
++ .id = 0,
++ .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
++ .resource = mv643xx_eth0_resources,
++ .dev = {
++ .platform_data = ð0_pd,
++ },
++};
++#endif
++
++#ifdef CONFIG_MV643XX_ETH_1
++static struct resource mv643xx_eth1_resources[] = {
++ [0] = {
++ .name = "eth1 irq",
++ .start = 9,
++ .end = 9,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct mv643xx_eth_platform_data eth1_pd;
++
++static struct platform_device eth1_device = {
++ .name = MV643XX_ETH_NAME,
++ .id = 1,
++ .num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
++ .resource = mv643xx_eth1_resources,
++ .dev = {
++ .platform_data = ð1_pd,
++ },
++};
++#endif
++
++static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
++ &mv643xx_eth_shared_device,
++#ifdef CONFIG_MV643XX_ETH_0
++ ð0_device,
++#endif
++#ifdef CONFIG_MV643XX_ETH_1
++ ð1_device,
++#endif
++};
++
++static int __init
++mv643xx_eth_add_pds(void)
++{
++ int ret = 0;
++
++ if ((ret = pci_find_device(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360, NULL))) {
++ ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
++ }
++}
Added: trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/series/2.6.10-7
===================================================================
--- trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/series/2.6.10-7 2005-03-16 06:46:06 UTC (rev 2723)
+++ trunk/kernel/source/kernel-source-2.6.10-2.6.10/debian/patches/series/2.6.10-7 2005-03-16 10:22:58 UTC (rev 2724)
@@ -0,0 +1,3 @@
+- marvell-pegasos.dpatch
++ powerpc-mv643xx-enet.dpatch
++ powerpc-mv643xx-eth-pegasos.dpatch