[kernel] r5919 -
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches
Martin Michlmayr
tbm at costa.debian.org
Fri Feb 17 19:15:29 UTC 2006
Author: tbm
Date: Fri Feb 17 19:15:29 2006
New Revision: 5919
Modified:
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/27_cobalt-def_fix.dpatch
Log:
proper fix
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/27_cobalt-def_fix.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/27_cobalt-def_fix.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/27_cobalt-def_fix.dpatch Fri Feb 17 19:15:29 2006
@@ -1,15 +1,23 @@
#! /bin/sh -e
## 27_cobalt-def_fix.dpatch by Martin Michlmayr <tbm at cyrius.com>
-## DP: Workaround a bug in Cobalt that'll cause a crash on boot
-## DP: Upstream status: is only a workaround, real solution in work
+## DP: Initialize scache flushing functions when CPU has no scache
+## DP: Upstream status: submitted to linux-mips
+
+# [PATCH] Initialize scache flushing functions when CPU has no scache
+
+# When a CPU has no scache, the scache flushing functions currently
+# aren't getting initialized and the NULL pointer is eventually called
+# as a function. Initialize the scache flushing functions as a noop
+# when there's no scache.
+
+# Signed-off-by: Martin Michlmayr <tbm at cyrius.com>
+
+# ---
+
+# c-r4k.c | 16 +++++++++++-----
+# 1 file changed, 11 insertions(+), 5 deletions(-)
-# Ralf Baechle writes:
-# > If cpu_icache_snoops_remote_store is not set, Cobalt will crash
-# > immediately when starting the kernel.
-# That's papering over the actual bug. The CPU has no scache, so the
-# scache flushing functions aren't getting initialized and the NULL
-# pointer is eventually called as a function.
if [ $# -lt 1 ]; then
@@ -30,15 +38,59 @@
exit 0
---- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h~ 2006-01-19 19:21:35.000000000 +0000
-+++ b/include/asm-mips/cobalt/cpu-feature-overrides.h 2006-01-19 19:21:41.000000000 +0000
-@@ -45,7 +45,7 @@
- #define cpu_has_smartmips 0
- #define cpu_has_vtag_icache 0
- #define cpu_has_ic_fills_f_dc 0
--#define cpu_icache_snoops_remote_store 0
-+#define cpu_icache_snoops_remote_store 1
- #define cpu_has_dsp 0
+diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
+index 1b71d91..0668e9b 100644
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+- if (sc_lsize == 16)
++ if (scache_size == 0)
++ r4k_blast_scache_page = (void *)no_sc_noop;
++ else if (sc_lsize == 16)
+ r4k_blast_scache_page = blast_scache16_page;
+ else if (sc_lsize == 32)
+ r4k_blast_scache_page = blast_scache32_page;
+@@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+- if (sc_lsize == 16)
++ if (scache_size == 0)
++ r4k_blast_scache_page_indexed = (void *)no_sc_noop;
++ else if (sc_lsize == 16)
+ r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
+ else if (sc_lsize == 32)
+ r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
+@@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setu
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+- if (sc_lsize == 16)
++ if (scache_size == 0)
++ r4k_blast_scache = (void *)no_sc_noop;
++ else if (sc_lsize == 16)
+ r4k_blast_scache = blast_scache16;
+ else if (sc_lsize == 32)
+ r4k_blast_scache = blast_scache32;
+@@ -482,7 +488,7 @@ static inline void local_r4k_flush_icach
+ protected_blast_dcache_range(start, end);
+ }
+
+- if (!cpu_icache_snoops_remote_store) {
++ if (!cpu_icache_snoops_remote_store && scache_size) {
+ if (end - start > scache_size)
+ r4k_blast_scache();
+ else
+@@ -651,7 +657,7 @@ static void local_r4k_flush_cache_sigtra
- #define cpu_has_mips32r1 0
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+- if (!cpu_icache_snoops_remote_store)
++ if (!cpu_icache_snoops_remote_store && scache_size)
+ protected_writeback_scache_line(addr & ~(sc_lsize - 1));
+ protected_flush_icache_line(addr & ~(ic_lsize - 1));
+ if (MIPS4K_ICACHE_REFILL_WAR) {
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