[kernel] r5520 -
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches
Martin Michlmayr
tbm at costa.debian.org
Thu Jan 19 16:40:55 UTC 2006
Author: tbm
Date: Thu Jan 19 16:40:54 2006
New Revision: 5520
Modified:
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/26_cobalt-ll-sc.dpatch
Log:
replace with patch from upstream
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/26_cobalt-ll-sc.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/26_cobalt-ll-sc.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/26_cobalt-ll-sc.dpatch Thu Jan 19 16:40:54 2006
@@ -1,8 +1,20 @@
#! /bin/sh -e
-## 26_cobalt-ll-sc.dpatch by Peter Horton <pdh at colonel-panic.org>
-##
-## All lines beginning with `## DP:' are a description of the patch.
-## DP: Work around broken ll/sc of some 64bit cobalt boxen.
+## 26_cobalt-ll-sc.dpatch by Ralf Baechle <ralf at linux-mips.org>
+
+# DP: CPU definitions for Cobalt.
+# DP: Upstream status: in mips-linux git
+
+# author Ralf Baechle <ralf at linux-mips.org>
+# Thu, 19 Jan 2006 00:49:32 +0000 (00:49 +0000)
+# committer Ralf Baechle <ralf at linux-mips.org>
+# Thu, 19 Jan 2006 00:49:32 +0000 (00:49 +0000)
+# commit d0a76bb142a666e4e5127d38d01c666080a2ed7b
+# tree ec2447ebb67f5bd97312bcb099ad5dd81f5e3bf1 tree
+# parent ebb830b34a1d5b6ec0dcace48d4878aeabb26444 commit | commitdiff
+
+# CPU definitions for Cobalt.
+#
+# Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
if [ $# -lt 1 ]; then
echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
@@ -22,79 +34,64 @@
exit 0
-This patch adds detection of broken 64-bit mode LL/SC on Cobalt units.
-With this patch my Qube2700 boots a 64-bit build fine. The later units
-have some problems with the Tulip driver.
-
---- linux-source-2.6.12/arch/mips/kernel/cpu-bugs64.c~ 2005-06-17 21:48:29.000000000 +0200
-+++ linux-source-2.6.12/arch/mips/kernel/cpu-bugs64.c 2005-09-13 23:11:41.000000000 +0200
-@@ -313,9 +313,69 @@ static inline void check_daddiu(void)
- );
- }
-
-+/*
-+ * On R5000/RM5230/RM5231 all accesses to XKPHYS by LL(D) are forced
-+ * to be uncached, bits 61-59 of the address are ignored.
-+ *
-+ * Apparently fixed on RM5230A/5231A.
-+ */
-+static void check_lld(void)
-+{
-+ struct cpuinfo_mips *c = ¤t_cpu_data;
-+ unsigned long flags, value, match, phys, *addr;
-+
-+ switch (c->cputype) {
-+ case CPU_R5000:
-+ case CPU_NEVADA:
-+ break;
-+
-+ default:
-+ return;
-+ }
-+
-+ printk("Checking for lld bug... ");
-+
-+ /* hope the stack is in the low 512MB */
-+ phys = CPHYSADDR((unsigned long) &value);
-+
-+ /* write value to memory */
-+ value = 0xfedcba9876543210;
-+ addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_UNCACHED, phys);
-+ *addr = value;
-+
-+ /* stop spurious flushes */
-+ local_irq_save(flags);
-+
-+ /* flip cached value */
-+ value = ~value;
-+
-+ /* read value, supposedly from cache */
-+ addr = (unsigned long *) PHYS_TO_XKPHYS(K_CALG_NONCOHERENT, phys);
-+ __asm__ __volatile__("lld %0, %1" : "=r" (match) : "m" (*addr));
-+
-+ local_irq_restore(flags);
-+
-+ match ^= value;
-+
-+ switch ((long) match) {
-+ case 0:
-+ printk("no.\n");
-+ break;
-+ case -1:
-+ printk("yes.\n");
-+ break;
-+ default:
-+ printk("yikes yes! (%lx/%lx@%p)\nPlease report to <linux-mips at linux-mips.org>.", value, match, &value);
-+ }
-+
-+ if (!match)
-+ c->options &= ~MIPS_CPU_LLSC;
-+}
-+
- void __init check_bugs64(void)
- {
- check_mult_sh();
- check_daddi();
- check_daddiu();
-+ check_lld();
- }
+
+
+--- /dev/null
++++ b/include/asm-mips/mach/cpu-feature-overrides.h
+@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Ralf Baechle (ralf at linux-mips.org)
+ */
+#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/config.h>
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 1
+#define cpu_has_32fpr 1
+#define cpu_has_counter 1
+#define cpu_has_watch 0
+#define cpu_has_divec 1
+#define cpu_has_vce 0
+#define cpu_has_cache_cdex_p 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_prefetch 0
+#define cpu_has_mcheck 0
+#define cpu_has_ejtag 0
+
+#define cpu_has_subset_pcaches 0
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+#define cpu_scache_line_size() 0
+
+#ifdef CONFIG_64BIT
+#define cpu_has_llsc 0
+#else
+#define cpu_has_llsc 1
+#endif
+
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_ic_fills_f_dc 0
+#define cpu_icache_snoops_remote_store 0
+#define cpu_has_dsp 0
+
+#define cpu_has_mips32r1 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
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