[kernel] r5570 - dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches

[Martin Michlmayr]

Author: tbm
Date: Mon Jan 23 11:10:14 2006
New Revision: 5570

Modified:
   dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/28_cobalt_ide.dpatch
Log:
commit new version of the fix


Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/28_cobalt_ide.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/28_cobalt_ide.dpatch	(original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/28_cobalt_ide.dpatch	Mon Jan 23 11:10:14 2006
@@ -1,12 +1,8 @@
 #! /bin/sh -e
 ## 28_cobalt_ide.dpatch by Peter Horton
 
-## DP: Make IDE work faster on Cobalt...
-## DP: Upstream status: Peter will check if this is still the preferred
-## solution
-
-## Without this patch it takes a Cobalt in 64bit mode over 2 minute to
-## probe for IDE disks.
+## DP: Fix long IDE detection delay by not scanning non-existent channels.
+## DP: Not quite the right fix according to Alan Cox but it works(tm).
 
 
 if [ $# -lt 1 ]; then
@@ -27,90 +23,18 @@
 
 exit 0
 
---- /dev/null	2005-11-10 20:12:48.000000000 +0000
-+++ b/include/asm-mips/cobalt/ide.h	2006-01-20 16:06:11.000000000 +0000
-@@ -0,0 +1,83 @@
-+
-+/*
-+ * PIO "in" transfers can cause D-cache lines to be allocated
-+ * to the data being read. If the target is the page cache then
-+ * the kernel can create a user space mapping of the same page
-+ * without flushing it from the D-cache. This has large potential
-+ * to create cache aliases. The Cobalts seem to trigger this
-+ * problem easily.
-+ *
-+ * MIPS doesn't have a flush_dcache_range() so we roll
-+ * our own.
-+ *
-+ * -- pdh
-+ */
-+
-+#define MAX_HWIFS			2
-+
-+#include <asm/r4kcache.h>
-+
-+static inline void __flush_dcache(void)
-+{
-+	unsigned long dc_size, dc_line, addr, end;
-+
-+	dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
-+	dc_line = current_cpu_data.dcache.linesz;
-+
-+	addr = CKSEG0;
-+	end = addr + dc_size;
-+
-+	for (; addr < end; addr += dc_line)
-+		flush_dcache_line_indexed(addr);
-+}
-+
-+static inline void __flush_dcache_range(unsigned long start, unsigned long end)
-+{
-+	unsigned long dc_size, dc_line, addr;
-+
-+	dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
-+	dc_line = current_cpu_data.dcache.linesz;
-+
-+	addr = start & ~(dc_line - 1);
-+	end += dc_line - 1;
-+
-+	if (end - addr < dc_size)
-+		for (; addr < end; addr += dc_line)
-+			flush_dcache_line(addr);
-+	else
-+		__flush_dcache();
-+}
-+
-+static inline void __ide_insw(unsigned long port, void *addr, unsigned int count)
-+{
-+	insw(port, addr, count);
-+
-+	__flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
-+}
-+
-+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
-+{
-+	insl(port, addr, count);
-+
-+	__flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
-+}
-+
-+static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count)
-+{
-+	readsw(port, addr, count);
-+
-+	__flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
-+}
-+
-+static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count)
-+{
-+	readsl(port, addr, count);
+
+Index: linux.git/include/asm-mips/mach-cobalt/ide.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux.git/include/asm-mips/cobalt/ide.h	2006-01-22 23:17:03.000000000 +0000
+@@ -0,0 +1,8 @@
++#ifndef __ASM_COBALT_IDE_H
++#define __ASM_COBALT_IDE_H
 +
-+	__flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
-+}
++#define MAX_HWIFS		2
 +
-+#define insw			__ide_insw
-+#define insl			__ide_insl
++#include <asm/mach-generic/ide.h>
 +
-+#define __ide_mm_outsw		writesw
-+#define __ide_mm_outsl		writesl
++#endif