[kernel] r5453 - dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches
Martin Michlmayr
tbm at costa.debian.org
Mon Jan 16 17:34:34 UTC 2006
Author: tbm
Date: Mon Jan 16 17:33:25 2006
New Revision: 5453
Added:
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/15_interrupt.dpatch (contents, props changed)
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/18_gettimeofday.dpatch (contents, props changed)
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/25_cobalt-network.dpatch (contents, props changed)
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/36_sb1-addrspace.dpatch (contents, props changed)
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/56_corefile-o32.dpatch (contents, props changed)
Modified:
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00_linux-mips.dpatch
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/20_ioc3.dpatch
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/21_ip30.dpatch
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/51_iomap.dpatch
Log:
update patches from 2.6.12 to 2.6.15
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00_linux-mips.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00_linux-mips.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00_linux-mips.dpatch Mon Jan 16 17:33:25 2006
@@ -2,8 +2,8 @@
## 00_linux-mips.dpatch by Thiemo Seufer <ths at debian.org>
##
## All lines beginning with `## DP:' are a description of the patch.
-## DP: Diff between kernel.org 2.6.12 and linux-mips.org, CVS HEAD,
-## DP: taken at 2005-07-10.
+## DP: Diff between kernel.org 2.6.15 and linux-mips.org git 2.6.15
+## DP: taken at 2006-01-10
if [ $# -lt 1 ]; then
echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
@@ -23,61212 +23,3366 @@
exit 0
-diff -urpNX dontdiff linux-2.6.12/arch/mips/Kconfig linux_HEAD/arch/mips/Kconfig
---- linux-2.6.12/arch/mips/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/Kconfig 2005-07-10 12:16:37.000000000 +0200
-@@ -4,176 +4,131 @@ config MIPS
- # Horrible source of confusion. Die, die, die ...
- select EMBEDDED
+diff -urN --ignore-space-change kernel.org/Documentation/mips/AU1xxx_IDE.README linux-mips/Documentation/mips/AU1xxx_IDE.README
+--- kernel.org/Documentation/mips/AU1xxx_IDE.README 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/Documentation/mips/AU1xxx_IDE.README 2006-01-10 11:21:08.000000000 +0000
+@@ -95,11 +95,13 @@
+ CONFIG_IDEDMA_PCI_AUTO=y
+ CONFIG_BLK_DEV_IDE_AU1XXX=y
+ CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
+-CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON=y
+ CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
+ CONFIG_BLK_DEV_IDEDMA=y
+ CONFIG_IDEDMA_AUTO=y
--config MIPS64
-- bool "64-bit kernel"
-- help
-- Select this option if you want to build a 64-bit kernel. You should
-- only select this option if you have hardware that actually has a
-- 64-bit processor and if your application will actually benefit from
-- 64-bit processing, otherwise say N. You must say Y for kernels for
-- SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2). If in doubt say N.
--
--config 64BIT
-- def_bool MIPS64
--
--config MIPS32
-- bool
-- depends on MIPS64 = 'n'
-- default y
--
- mainmenu "Linux/MIPS Kernel Configuration"
++Also define 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to enable
++the burst support on DBDMA controller.
++
+ If the used system need the USB support enable the following kernel configs for
+ high IDE to USB throughput.
- source "init/Kconfig"
+@@ -115,6 +117,8 @@
+ CONFIG_BLK_DEV_IDEDMA=y
+ CONFIG_IDEDMA_AUTO=y
+
++Also undefine 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to
++disable the burst support on DBDMA controller.
+
+ ADD NEW HARD DISC TO WHITE OR BLACK LIST
+ ----------------------------------------
+diff -urN --ignore-space-change kernel.org/Makefile linux-mips/Makefile
+--- kernel.org/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/Makefile 2006-01-10 11:30:59.000000000 +0000
+@@ -166,10 +166,7 @@
+ # then ARCH is assigned, getting whatever value it gets normally, and
+ # SUBARCH is subsequently ignored.
+
+-SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
+- -e s/arm.*/arm/ -e s/sa110/arm/ \
+- -e s/s390x/s390/ -e s/parisc64/parisc/ \
+- -e s/ppc64/powerpc/ )
++SUBARCH := mips
+
+ # Cross compiling and selecting different set of gcc/bin-utils
+ # ---------------------------------------------------------------------------
+@@ -536,7 +533,7 @@
+ CHECKFLAGS += $(NOSTDINC_FLAGS)
+
+ # warn about C99 declaration after statement
+-CFLAGS += $(call cc-option,-Wdeclaration-after-statement,)
++#CFLAGS += $(call cc-option,-Wdeclaration-after-statement,)
+
+ # disable pointer signedness warnings in gcc 4.0
+ CFLAGS += $(call cc-option,-Wno-pointer-sign,)
+diff -urN --ignore-space-change kernel.org/arch/mips/Kconfig linux-mips/arch/mips/Kconfig
+--- kernel.org/arch/mips/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/Kconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -503,10 +503,7 @@
+ ether port USB, AC97, PCI, etc.
- menu "Machine selection"
+ config MACH_VR41XX
+- bool "Support for NEC VR4100 series based machines"
+- select SYS_HAS_CPU_VR41XX
+- select SYS_SUPPORTS_32BIT_KERNEL
+- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
++ bool "Support for NEC VR41XX-based machines"
--config MACH_JAZZ
-- bool "Support for the Jazz family of machines"
-- select ARC
-- select ARC32
-- select GENERIC_ISA_DMA
-- select I8259
-- select ISA
-- help
-- This a family of machines based on the MIPS R4030 chipset which was
-- used by several vendors to build RISC/os and Windows NT workstations.
-- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
-- Olivetti M700-10 workstations.
-+choice
-+ prompt "System type"
-+ default SGI_IP22
-
--config ACER_PICA_61
-- bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
-- depends on MACH_JAZZ && EXPERIMENTAL
-+config MIPS_MTX1
-+ bool "Support for 4G Systems MTX-1 board"
- select DMA_NONCOHERENT
-- help
-- This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
-- kernel that runs on these, say Y here. For details about Linux on
-- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-- <http://www.linux-mips.org/>.
-+ select HW_HAS_PCI
-+ select SOC_AU1500
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ config PMC_YOSEMITE
+ bool "Support for PMC-Sierra Yosemite eval board"
+@@ -1018,6 +1015,9 @@
+ config HAVE_STD_PC_SERIAL_PORT
+ bool
--config MIPS_MAGNUM_4000
-- bool "Support for MIPS Magnum 4000"
-- depends on MACH_JAZZ
-+config MIPS_BOSPORUS
-+ bool "AMD Alchemy Bosporus board"
-+ select SOC_AU1500
- select DMA_NONCOHERENT
-- help
-- This is a machine with a R4000 100 MHz CPU. To compile a Linux
-- kernel that runs on these, say Y here. For details about Linux on
-- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-- <http://www.linux-mips.org/>.
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
++config VR4181
++ bool
++
+ config ARC_CONSOLE
+ bool "ARC console support"
+ depends on SGI_IP22 || SNI_RM200_PCI
+@@ -1129,7 +1129,7 @@
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
+ help
+- The options selects support for the NEC VR4100 series of processors.
++ The options selects support for the NEC VR41xx series of processors.
+ Only choose this option if you have one of these processors as a
+ kernel built with this option will not run on any other type of
+ processor or vice versa.
+@@ -1471,7 +1471,7 @@
--config OLIVETTI_M700
-- bool "Support for Olivetti M700-10"
-- depends on MACH_JAZZ
-+config MIPS_PB1000
-+ bool "AMD Alchemy PB1000 board"
-+ select SOC_AU1000
- select DMA_NONCOHERENT
+ config 64BIT_PHYS_ADDR
+ bool "Support for 64-bit physical address space"
+- depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
++ depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
+
+ config CPU_ADVANCED
+ bool "Override CPU Options"
+@@ -1492,14 +1492,6 @@
+ for better performance, N if you don't know. You must say Y here
+ for multiprocessor machines.
+
+-config CPU_HAS_LLDSCD
+- bool "lld/scd Instructions available" if CPU_ADVANCED
+- default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
- help
-- This is a machine with a R4000 100 MHz CPU. To compile a Linux
-- kernel that runs on these, say Y here. For details about Linux on
-- the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-- <http://www.linux-mips.org/>.
--
--config MACH_VR41XX
-- bool "Support for NEC VR41XX-based machines"
-+ select HW_HAS_PCI
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+- Say Y here if your CPU has the lld and scd instructions, the 64-bit
+- equivalents of ll and sc. Say Y here for better performance, N if
+- you don't know. You must say Y here for multiprocessor machines.
+-
+ config CPU_HAS_WB
+ bool "Writeback Buffer available" if CPU_ADVANCED
+ default y if !CPU_ADVANCED && CPU_R3000 && MACH_DECSTATION
+diff -urN --ignore-space-change kernel.org/arch/mips/Makefile linux-mips/arch/mips/Makefile
+--- kernel.org/arch/mips/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/Makefile 2006-01-10 11:30:59.000000000 +0000
+@@ -93,7 +93,6 @@
+ #
+ cflags-y += -I $(TOPDIR)/include/asm/gcc
+ cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
+-cflags-y += $(call cc-option, -finline-limit=100000)
+ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
+ MODFLAGS += -mlong-calls
--config NEC_CMBVR4133
-- bool "Support for NEC CMB-VR4133"
-- depends on MACH_VR41XX
-- select CPU_VR41XX
-+config MIPS_PB1100
-+ bool "AMD Alchemy PB1100 board"
-+ select SOC_AU1100
- select DMA_NONCOHERENT
-- select IRQ_CPU
- select HW_HAS_PCI
-- select PCI_VR41XX
--
--config ROCKHOPPER
-- bool "Support for Rockhopper baseboard"
-- depends on NEC_CMBVR4133
-- select I8259
-- select HAVE_STD_PC_SERIAL_PORT
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -106,7 +105,8 @@
+ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
+ cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
--config CASIO_E55
-- bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
-- depends on MACH_VR41XX
-+config MIPS_PB1500
-+ bool "AMD Alchemy PB1500 board"
-+ select SOC_AU1500
- select DMA_NONCOHERENT
-- select IRQ_CPU
-- select ISA
-+ select HW_HAS_PCI
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+-cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
++cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
++ -fno-omit-frame-pointer
--config IBM_WORKPAD
-- bool "Support for IBM WorkPad z50"
-- depends on MACH_VR41XX
-+config MIPS_PB1550
-+ bool "AMD Alchemy PB1550 board"
-+ select SOC_AU1550
- select DMA_NONCOHERENT
-- select IRQ_CPU
-- select ISA
-+ select HW_HAS_PCI
-+ select MIPS_DISABLE_OBSOLETE_IDE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
+@@ -478,6 +478,7 @@
+ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite
+ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
--config TANBAC_TB0226
-- bool "Support for TANBAC TB0226 (Mbase)"
-- depends on MACH_VR41XX
-+config MIPS_PB1200
-+ bool "AMD Alchemy PB1200 board"
-+ select SOC_AU1200
- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select IRQ_CPU
-- help
-- The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC.
-- Please refer to <http://www.tanbac.co.jp/> about Mbase.
-+ select MIPS_DISABLE_OBSOLETE_IDE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
++#
+ # Qemu simulating MIPS32 4Kc
+ #
+ core-$(CONFIG_QEMU) += arch/mips/qemu/
+@@ -564,7 +565,7 @@
+ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
--config TANBAC_TB0229
-- bool "Support for TANBAC TB0229 (VR4131DIMM)"
-- depends on MACH_VR41XX
-+config MIPS_DB1000
-+ bool "AMD Alchemy DB1000 board"
-+ select SOC_AU1000
- select DMA_NONCOHERENT
- select HW_HAS_PCI
-- select IRQ_CPU
-- help
-- The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC.
-- Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM.
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+-# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
++# TANBAC TB0225 VR4131 Multi-chip module/TB0229 VR4131DIMM (VR4131)
+ #
+ load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
--config VICTOR_MPC30X
-- bool "Support for Victor MP-C303/304"
-+config MIPS_DB1100
-+ bool "AMD Alchemy DB1100 board"
-+ select SOC_AU1100
- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select IRQ_CPU
-- depends on MACH_VR41XX
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -762,7 +763,7 @@
--config ZAO_CAPCELLA
-- bool "Support for ZAO Networks Capcella"
-- depends on MACH_VR41XX
-+config MIPS_DB1500
-+ bool "AMD Alchemy DB1500 board"
-+ select SOC_AU1500
- select DMA_NONCOHERENT
- select HW_HAS_PCI
-- select IRQ_CPU
-+ select MIPS_DISABLE_OBSOLETE_IDE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ ifdef CONFIG_LASAT
+ rom.bin rom.sw: vmlinux
+- $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
++ $(call descend,arch/mips/lasat/image,$@)
+ endif
--config PCI_VR41XX
-- bool "Add PCI control unit support of NEC VR4100 series"
-- depends on MACH_VR41XX && PCI
--
--config VRC4171
-- tristate "Add NEC VRC4171 companion chip support"
-- depends on MACH_VR41XX && ISA
-- ---help---
-- The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121.
-+config MIPS_DB1550
-+ bool "AMD Alchemy DB1550 board"
-+ select SOC_AU1550
-+ select HW_HAS_PCI
-+ select DMA_NONCOHERENT
-+ select MIPS_DISABLE_OBSOLETE_IDE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/atlas_defconfig linux-mips/arch/mips/configs/atlas_defconfig
+--- kernel.org/arch/mips/configs/atlas_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/atlas_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:52 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:16 2005
+ #
+ CONFIG_MIPS=y
--config VRC4173
-- tristate "Add NEC VRC4173 companion chip support"
-- depends on MACH_VR41XX && PCI_VR41XX
-- ---help---
-- The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
-+config MIPS_DB1200
-+ bool "AMD Alchemy DB1200 board"
-+ select SOC_AU1200
-+ select DMA_NONCOHERENT
-+ select MIPS_DISABLE_OBSOLETE_IDE
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -168,6 +168,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -176,7 +177,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -553,7 +553,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
--config TOSHIBA_JMR3927
-- bool "Support for Toshiba JMR-TX3927 board"
-- depends on MIPS32
-+config MIPS_MIRAGE
-+ bool "AMD Alchemy Mirage board"
- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select SWAP_IO_SPACE
-+ select SOC_AU1500
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/bigsur_defconfig linux-mips/arch/mips/configs/bigsur_defconfig
+--- kernel.org/arch/mips/configs/bigsur_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/bigsur_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:54 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:20 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_COBALT
-- bool "Support for Cobalt Server (EXPERIMENTAL)"
-- depends on EXPERIMENTAL
-+ bool "Support for Cobalt Server"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select I8259
- select IRQ_CPU
-+ select MIPS_GT64111
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -130,7 +130,6 @@
+ # CONFIG_SIBYTE_DMA_PAGEOPS is not set
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -176,6 +175,7 @@
+ CONFIG_IKCONFIG_PROC=y
+ # CONFIG_CPUSETS is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_ALL is not set
+@@ -185,7 +185,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/capcella_defconfig linux-mips/arch/mips/configs/capcella_defconfig
+--- kernel.org/arch/mips/configs/capcella_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/capcella_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:55 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:23 2005
+ #
+ CONFIG_MIPS=y
- config MACH_DECSTATION
- bool "Support for DECstations"
- select BOOT_ELF32
- select DMA_NONCOHERENT
-+ select EARLY_PRINTK
- select IRQ_CPU
-- depends on MIPS32 || EXPERIMENTAL
-- ---help---
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
- This enables support for DEC's MIPS based workstations. For details
- see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
- DECstation porting pages on <http://decstation.unix-ag.org/>.
-@@ -194,6 +149,9 @@ config MIPS_EV64120
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select MIPS_GT64120
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- This is an evaluation board based on the Galileo GT-64120
- single-chip system controller that contains a MIPS R5000 compatible
-@@ -201,10 +159,6 @@ config MIPS_EV64120
- <http://www.marvell.com/>. Say Y here if you wish to build a
- kernel for this platform.
-
--config EVB_PCI1
-- bool "Enable Second PCI (PCI1)"
-- depends on MIPS_EV64120
--
- config MIPS_EV96100
- bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
- depends on EXPERIMENTAL
-@@ -214,6 +168,9 @@ config MIPS_EV96100
- select MIPS_GT96100
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- This is an evaluation board based on the Galileo GT-96100 LAN/WAN
- communications controllers containing a MIPS R5000 compatible core
-@@ -224,6 +181,10 @@ config MIPS_IVR
- bool "Support for Globespan IVR board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
-+ select ITE_BOARD_GEN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This is an evaluation board built by Globespan to showcase thir
- iVR (Internet Video Recorder) design. It utilizes a QED RM5231
-@@ -231,33 +192,14 @@ config MIPS_IVR
- located at <http://www.globespan.net/>. Say Y here if you wish to
- build a kernel for this platform.
+@@ -159,6 +159,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -167,7 +168,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -306,7 +306,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
--config LASAT
-- bool "Support for LASAT Networks platforms"
-- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select MIPS_GT64120
-- select R5000_CPU_SCACHE
--
--config PICVUE
-- tristate "PICVUE LCD display driver"
-- depends on LASAT
--
--config PICVUE_PROC
-- tristate "PICVUE LCD display driver /proc interface"
-- depends on PICVUE
--
--config DS1603
-- bool "DS1603 RTC driver"
-- depends on LASAT
--
--config LASAT_SYSCTL
-- bool "LASAT sysctl interface"
-- depends on LASAT
--
- config MIPS_ITE8172
- bool "Support for ITE 8172G board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
-+ select ITE_BOARD_GEN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
- with ATX form factor that utilizes a MIPS R5000 to work with its
-@@ -265,24 +207,49 @@ config MIPS_ITE8172
- either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
- a kernel for this platform.
-
--config IT8172_REVC
-- bool "Support for older IT8172 (Rev C)"
-- depends on MIPS_ITE8172
-+config MACH_JAZZ
-+ bool "Support for the Jazz family of machines"
-+ select ARC
-+ select ARC32
-+ select GENERIC_ISA_DMA
-+ select I8259
-+ select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
- help
-- Say Y here to support the older, Revision C version of the Integrated
-- Technology Express, Inc. ITE8172 SBC. Vendor page at
-- <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
-- board at <http://www.mvista.com/partners/semiconductor/ite.html>.
-+ This a family of machines based on the MIPS R4030 chipset which was
-+ used by several vendors to build RISC/os and Windows NT workstations.
-+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
-+ Olivetti M700-10 workstations.
-+
-+config LASAT
-+ bool "Support for LASAT Networks platforms"
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select MIPS_GT64120
-+ select MIPS_NILE4
-+ select R5000_CPU_SCACHE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/cobalt_defconfig linux-mips/arch/mips/configs/cobalt_defconfig
+--- kernel.org/arch/mips/configs/cobalt_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/cobalt_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:57 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:25 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_ATLAS
- bool "Support for MIPS Atlas board"
- select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
-+ select MIPS_BOARDS_GEN
-+ select MIPS_BONITO64
- select MIPS_GT64120
-+ select MIPS_MSC
-+ select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
-- This enables support for the QED R5231-based MIPS Atlas evaluation
-+ This enables support for the MIPS Technologies Atlas evaluation
- board.
-
- config MIPS_MALTA
-@@ -293,10 +260,17 @@ config MIPS_MALTA
- select GENERIC_ISA_DMA
- select HW_HAS_PCI
- select I8259
-+ select MIPS_BOARDS_GEN
-+ select MIPS_BONITO64
- select MIPS_GT64120
-+ select MIPS_MSC
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
-- This enables support for the VR5000-based MIPS Malta evaluation
-+ This enables support for the MIPS Technologies Malta evaluation
- board.
-
- config MIPS_SEAD
-@@ -304,42 +278,46 @@ config MIPS_SEAD
- depends on EXPERIMENTAL
- select IRQ_CPU
- select DMA_NONCOHERENT
--
--config MOMENCO_OCELOT
-- bool "Support for Momentum Ocelot board"
-- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select IRQ_CPU
-- select IRQ_CPU_RM7K
-- select MIPS_GT64120
-- select RM7000_CPU_SCACHE
-- select SWAP_IO_SPACE
-+ select MIPS_BOARDS_GEN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
-- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
-- Momentum Computer <http://www.momenco.com/>.
-+ This enables support for the MIPS Technologies SEAD evaluation
-+ board.
-
--config MOMENCO_OCELOT_G
-- bool "Support for Momentum Ocelot-G board"
-+config MOMENCO_JAGUAR_ATX
-+ bool "Support for Momentum Jaguar board"
-+ select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_CPU_RM7K
-+ select IRQ_MV64340
-+ select LIMITED_DMA
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
-- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
-+ The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-
--config MOMENCO_OCELOT_C
-- bool "Support for Momentum Ocelot-C board"
-+config MOMENCO_OCELOT
-+ bool "Support for Momentum Ocelot board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
-- select IRQ_MV64340
-- select PCI_MARVELL
-+ select IRQ_CPU_RM7K
-+ select MIPS_GT64120
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-@@ -355,70 +333,80 @@ config MOMENCO_OCELOT_3
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Ocelot-3 is based off Discovery III System Controller and
- PMC-Sierra Rm79000 core.
+@@ -115,7 +115,6 @@
+ # CONFIG_MIPS_MT is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -155,6 +154,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -163,7 +163,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -292,7 +291,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
--config MOMENCO_JAGUAR_ATX
-- bool "Support for Momentum Jaguar board"
-- select BOOT_ELF32
-+config MOMENCO_OCELOT_C
-+ bool "Support for Momentum Ocelot-C board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
-- select IRQ_CPU_RM7K
- select IRQ_MV64340
-- select LIMITED_DMA
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
-- The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
-+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-
--config JAGUAR_DMALOW
-- bool "Low DMA Mode"
-- depends on MOMENCO_JAGUAR_ATX
-- help
-- Select to Y if jump JP5 is set on your board, N otherwise. Normally
-- the jumper is set, so if you feel unsafe, just say Y.
--
--config PMC_YOSEMITE
-- bool "Support for PMC-Sierra Yosemite eval board"
-- select DMA_COHERENT
-+config MOMENCO_OCELOT_G
-+ bool "Support for Momentum Ocelot-G board"
-+ select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_CPU_RM7K
-- select IRQ_CPU_RM9K
-+ select PCI_MARVELL
-+ select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
-- Yosemite is an evaluation board for the RM9000x2 processor
-- manufactured by PMC-Sierra
-+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by
-+ Momentum Computer <http://www.momenco.com/>.
-
--config HYPERTRANSPORT
-- bool "Hypertransport Support for PMC-Sierra Yosemite"
-- depends on PMC_YOSEMITE
-+config MIPS_XXS1500
-+ bool "Support for MyCable XXS1500 board"
-+ select DMA_NONCOHERENT
-+ select SOC_AU1500
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/db1000_defconfig linux-mips/arch/mips/configs/db1000_defconfig
+--- kernel.org/arch/mips/configs/db1000_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/db1000_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:59 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:27 2005
+ #
+ CONFIG_MIPS=y
- config DDB5074
- bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
- depends on EXPERIMENTAL
-+ select DDB5XXX_COMMON
- select DMA_NONCOHERENT
- select HAVE_STD_PC_SERIAL_PORT
- select HW_HAS_PCI
- select IRQ_CPU
- select I8259
- select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the VR5000-based NEC DDB Vrc-5074
- evaluation board.
+@@ -155,6 +155,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -163,7 +164,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -332,7 +332,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config DDB5476
- bool "Support for NEC DDB Vrc-5476"
-+ select DDB5XXX_COMMON
- select DMA_NONCOHERENT
- select HAVE_STD_PC_SERIAL_PORT
- select HW_HAS_PCI
- select IRQ_CPU
- select I8259
- select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the R5432-based NEC DDB Vrc-5476
- evaluation board.
-@@ -429,10 +417,14 @@ config DDB5476
-
- config DDB5477
- bool "Support for NEC DDB Vrc-5477"
-+ select DDB5XXX_COMMON
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select I8259
- select IRQ_CPU
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the R5432-based NEC DDB Vrc-5477,
- or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
-@@ -440,15 +432,23 @@ config DDB5477
- Features : kernel debugging, serial terminal, NFS root fs, on-board
- ether port USB, AC97, PCI, etc.
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/db1100_defconfig linux-mips/arch/mips/configs/db1100_defconfig
+--- kernel.org/arch/mips/configs/db1100_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/db1100_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:00 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:30 2005
+ #
+ CONFIG_MIPS=y
--config DDB5477_BUS_FREQUENCY
-- int "bus frequency (in kHZ, 0 for auto-detect)"
-- depends on DDB5477
-- default 0
-+config MACH_VR41XX
-+ bool "Support for NEC VR41XX-based machines"
+@@ -155,6 +155,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -163,7 +164,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -321,7 +321,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
--config NEC_OSPREY
-- bool "Support for NEC Osprey board"
-- select DMA_NONCOHERENT
-+config PMC_YOSEMITE
-+ bool "Support for PMC-Sierra Yosemite eval board"
-+ select DMA_COHERENT
-+ select HW_HAS_PCI
- select IRQ_CPU
-+ select IRQ_CPU_RM7K
-+ select IRQ_CPU_RM9K
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ help
-+ Yosemite is an evaluation board for the RM9000x2 processor
-+ manufactured by PMC-Sierra.
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/db1200_defconfig linux-mips/arch/mips/configs/db1200_defconfig
+--- kernel.org/arch/mips/configs/db1200_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/db1200_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:03 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:32 2005
+ #
+ CONFIG_MIPS=y
- config SGI_IP22
- bool "Support for SGI IP22 (Indy/Indigo2)"
-@@ -456,9 +456,13 @@ config SGI_IP22
- select ARC32
- select BOOT_ELF32
- select DMA_NONCOHERENT
-+ select HW_HAS_EISA
- select IP22_CPU_SCACHE
- select IRQ_CPU
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- This are the SGI Indy, Challenge S and Indigo2, as well as certain
- OEM variants like the Tandem CMN B006S. To compile a Linux kernel
-@@ -466,75 +470,23 @@ config SGI_IP22
-
- config SGI_IP27
- bool "Support for SGI IP27 (Origin200/2000)"
-- depends on MIPS64
- select ARC
- select ARC64
-+ select BOOT_ELF64
- select DMA_IP27
- select HW_HAS_PCI
- select PCI_DOMAINS
-+ select QL_ISP_A64
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
- workstations. To compile a Linux kernel that runs on these, say Y
- here.
-
--#config SGI_SN0_XXL
--# bool "IP27 XXL"
--# depends on SGI_IP27
--# This options adds support for userspace processes upto 16TB size.
--# Normally the limit is just .5TB.
--
--config SGI_SN0_N_MODE
-- bool "IP27 N-Mode"
-- depends on SGI_IP27
-- help
-- The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
-- configured in either N-Modes which allows for more nodes or M-Mode
-- which allows for more memory. Your system is most probably
-- running in M-Mode, so you should say N here.
--
--config DISCONTIGMEM
-- bool
-- default y if SGI_IP27
-- help
-- Say Y to upport efficient handling of discontiguous physical memory,
-- for architectures which are either NUMA (Non-Uniform Memory Access)
-- or have huge holes in the physical address space for other reasons.
-- See <file:Documentation/vm/numa> for more.
--
--config NUMA
-- bool "NUMA Support"
-- depends on SGI_IP27
-- help
-- Say Y to compile the kernel to support NUMA (Non-Uniform Memory
-- Access). This option is for configuring high-end multiprocessor
-- server machines. If in doubt, say N.
--
--config MAPPED_KERNEL
-- bool "Mapped kernel support"
-- depends on SGI_IP27
-- help
-- Change the way a Linux kernel is loaded into memory on a MIPS64
-- machine. This is required in order to support text replication and
-- NUMA. If you need to understand it, read the source code.
--
--config REPLICATE_KTEXT
-- bool "Kernel text replication support"
-- depends on SGI_IP27
-- help
-- Say Y here to enable replicating the kernel text across multiple
-- nodes in a NUMA cluster. This trades memory for speed.
--
--config REPLICATE_EXHANDLERS
-- bool "Exception handler replication support"
-- depends on SGI_IP27
-- help
-- Say Y here to enable replicating the kernel exception handlers
-- across multiple nodes in a NUMA cluster. This trades memory for
-- speed.
--
- config SGI_IP32
- bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
-- depends on MIPS64 && EXPERIMENTAL
-+ depends on EXPERIMENTAL
- select ARC
- select ARC32
- select BOOT_ELF32
-@@ -544,330 +496,89 @@ config SGI_IP32
- select HW_HAS_PCI
- select R5000_CPU_SCACHE
- select RM7000_CPU_SCACHE
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
- help
- If you want this kernel to run on SGI O2 workstation, say Y here.
+@@ -156,6 +156,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +165,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/db1500_defconfig linux-mips/arch/mips/configs/db1500_defconfig
+--- kernel.org/arch/mips/configs/db1500_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/db1500_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:05 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:35 2005
+ #
+ CONFIG_MIPS=y
--config SOC_AU1X00
-- depends on MIPS32
-- bool "Support for AMD/Alchemy Au1X00 SOCs"
--
--choice
-- prompt "Au1X00 SOC Type"
-- depends on SOC_AU1X00
-- help
-- Say Y here to enable support for one of three AMD/Alchemy
-- SOCs. For additional documentation see www.amd.com.
--
--config SOC_AU1000
-- bool "SOC_AU1000"
--config SOC_AU1100
-- bool "SOC_AU1100"
--config SOC_AU1500
-- bool "SOC_AU1500"
--config SOC_AU1550
-- bool "SOC_AU1550"
--
--endchoice
--
--choice
-- prompt "AMD/Alchemy Au1x00 board support"
-- depends on SOC_AU1X00
-- help
-- These are evaluation boards built by AMD/Alchemy to
-- showcase their Au1X00 Internet Edge Processors. The SOC design
-- is based on the MIPS32 architecture running at 266/400/500MHz
-- with many integrated peripherals. Further information can be
-- found at their website, <http://www.amd.com/>. Say Y here if you
-- wish to build a kernel for this platform.
--
--config MIPS_PB1000
-- bool "PB1000 board"
-- depends on SOC_AU1000
-- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select SWAP_IO_SPACE
--
--config MIPS_PB1100
-- bool "PB1100 board"
-- depends on SOC_AU1100
-- select DMA_NONCOHERENT
-- select HW_HAS_PCI
-- select SWAP_IO_SPACE
--
--config MIPS_PB1500
-- bool "PB1500 board"
-- depends on SOC_AU1500
-- select DMA_COHERENT
-- select HW_HAS_PCI
--
--config MIPS_PB1550
-- bool "PB1550 board"
-- depends on SOC_AU1550
-- select DMA_COHERENT
-- select HW_HAS_PCI
-- select MIPS_DISABLE_OBSOLETE_IDE
--
--config MIPS_DB1000
-- bool "DB1000 board"
-- depends on SOC_AU1000
-- select DMA_NONCOHERENT
-- select HW_HAS_PCI
--
--config MIPS_DB1100
-- bool "DB1100 board"
-- depends on SOC_AU1100
-- select DMA_NONCOHERENT
--
--config MIPS_DB1500
-- bool "DB1500 board"
-- depends on SOC_AU1500
-- select DMA_COHERENT
-- select HW_HAS_PCI
-- select MIPS_DISABLE_OBSOLETE_IDE
--
--config MIPS_DB1550
-- bool "DB1550 board"
-- depends on SOC_AU1550
-- select HW_HAS_PCI
-- select DMA_COHERENT
-- select MIPS_DISABLE_OBSOLETE_IDE
--
--config MIPS_BOSPORUS
-- bool "Bosporus board"
-- depends on SOC_AU1500
-- select DMA_NONCOHERENT
--
--config MIPS_MIRAGE
-- bool "Mirage board"
-- depends on SOC_AU1500
-- select DMA_NONCOHERENT
--
--config MIPS_XXS1500
-- bool "MyCable XXS1500 board"
-- depends on SOC_AU1500
-- select DMA_NONCOHERENT
--
--config MIPS_MTX1
-- bool "4G Systems MTX-1 board"
-- depends on SOC_AU1500
-- select HW_HAS_PCI
-- select DMA_NONCOHERENT
--
--endchoice
--
--config SIBYTE_SB1xxx_SOC
-- bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
-- depends on EXPERIMENTAL
-+config SIBYTE_SWARM
-+ bool "Support for Sibyte BCM91250A-SWARM"
- select BOOT_ELF32
- select DMA_COHERENT
-- select SWAP_IO_SPACE
--
--choice
-- prompt "BCM1xxx SOC-based board"
-- depends on SIBYTE_SB1xxx_SOC
-- default SIBYTE_SWARM
-- help
-- Enable support for boards based on the SiByte line of SOCs
-- from Broadcom. There are configurations for the known
-- evaluation boards, or you can choose "Other" and add your
-- own board support code.
--
--config SIBYTE_SWARM
-- bool "BCM91250A-SWARM"
- select SIBYTE_SB1250
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -157,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -165,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -340,7 +340,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config SIBYTE_SENTOSA
-- bool "BCM91250E-Sentosa"
-+ bool "Support for Sibyte BCM91250E-Sentosa"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_SB1250
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/db1550_defconfig linux-mips/arch/mips/configs/db1550_defconfig
+--- kernel.org/arch/mips/configs/db1550_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/db1550_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:07 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:38 2005
+ #
+ CONFIG_MIPS=y
- config SIBYTE_RHONE
-- bool "BCM91125E-Rhone"
-+ bool "Support for Sibyte BCM91125E-Rhone"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_BCM1125H
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -156,6 +156,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +165,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -339,7 +339,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config SIBYTE_CARMEL
-- bool "BCM91120x-Carmel"
-+ bool "Support for Sibyte BCM91120x-Carmel"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_BCM1120
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ddb5476_defconfig linux-mips/arch/mips/configs/ddb5476_defconfig
+--- kernel.org/arch/mips/configs/ddb5476_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ddb5476_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:09 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:40 2005
+ #
+ CONFIG_MIPS=y
- config SIBYTE_PTSWARM
-- bool "BCM91250PT-PTSWARM"
-+ bool "Support for Sibyte BCM91250PT-PTSWARM"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_SB1250
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -116,7 +116,6 @@
+ # CONFIG_MIPS_MT is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -156,6 +155,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +164,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -297,7 +296,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config SIBYTE_LITTLESUR
-- bool "BCM91250C2-LittleSur"
-+ bool "Support for Sibyte BCM91250C2-LittleSur"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_SB1250
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ddb5477_defconfig linux-mips/arch/mips/configs/ddb5477_defconfig
+--- kernel.org/arch/mips/configs/ddb5477_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ddb5477_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:11 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:42 2005
+ #
+ CONFIG_MIPS=y
- config SIBYTE_CRHINE
-- bool "BCM91120C-CRhine"
-+ bool "Support for Sibyte BCM91120C-CRhine"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_BCM1120
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+@@ -116,7 +116,6 @@
+ # CONFIG_MIPS_MT is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -156,6 +155,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +164,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -296,7 +295,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config SIBYTE_CRHONE
-- bool "BCM91125C-CRhone"
-- select SIBYTE_BCM1125
--
--config SIBYTE_UNKNOWN
-- bool "Other"
--
--endchoice
--
--config SIBYTE_BOARD
-- bool
-- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
-- default y
--
--choice
-- prompt "BCM1xxx SOC Type"
-- depends on SIBYTE_UNKNOWN
-- default SIBYTE_UNK_BCM1250
-- help
-- Since you haven't chosen a known evaluation board from
-- Broadcom, you must explicitly pick the SOC this kernel is
-- targetted for.
--
--config SIBYTE_UNK_BCM1250
-- bool "BCM1250"
-- select SIBYTE_SB1250
--
--config SIBYTE_UNK_BCM1120
-- bool "BCM1120"
-- select SIBYTE_BCM1120
--
--config SIBYTE_UNK_BCM1125
-- bool "BCM1125"
-+ bool "Support for Sibyte BCM91125C-CRhone"
-+ depends on EXPERIMENTAL
-+ select BOOT_ELF32
-+ select DMA_COHERENT
- select SIBYTE_BCM1125
--
--config SIBYTE_UNK_BCM1125H
-- bool "BCM1125H"
-- select SIBYTE_BCM1125H
--
--endchoice
--
--config SIBYTE_SB1250
-- bool
-- select HW_HAS_PCI
--
--config SIBYTE_BCM1120
-- bool
-- select SIBYTE_BCM112X
--
--config SIBYTE_BCM1125
-- bool
-- select HW_HAS_PCI
-- select SIBYTE_BCM112X
--
--config SIBYTE_BCM1125H
-- bool
-- select HW_HAS_PCI
-- select SIBYTE_BCM112X
--
--config SIBYTE_BCM112X
-- bool
--
--choice
-- prompt "SiByte SOC Stepping"
-- depends on SIBYTE_SB1xxx_SOC
--
--config CPU_SB1_PASS_1
-- bool "1250 Pass1"
-- depends on SIBYTE_SB1250
-- select CPU_HAS_PREFETCH
--
--config CPU_SB1_PASS_2_1250
-- bool "1250 An"
-- depends on SIBYTE_SB1250
-- select CPU_SB1_PASS_2
-- help
-- Also called BCM1250 Pass 2
--
--config CPU_SB1_PASS_2_2
-- bool "1250 Bn"
-- depends on SIBYTE_SB1250
-- select CPU_HAS_PREFETCH
-- help
-- Also called BCM1250 Pass 2.2
--
--config CPU_SB1_PASS_4
-- bool "1250 Cn"
-- depends on SIBYTE_SB1250
-- select CPU_HAS_PREFETCH
-- help
-- Also called BCM1250 Pass 3
--
--config CPU_SB1_PASS_2_112x
-- bool "112x Hybrid"
-- depends on SIBYTE_BCM112X
-- select CPU_SB1_PASS_2
--
--config CPU_SB1_PASS_3
-- bool "112x An"
-- depends on SIBYTE_BCM112X
-- select CPU_HAS_PREFETCH
--
--endchoice
--
--config CPU_SB1_PASS_2
-- bool
--
--config SIBYTE_HAS_LDT
-- bool
-- depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
-- default y
--
--config SIMULATION
-- bool "Running under simulation"
-- depends on SIBYTE_SB1xxx_SOC
-- help
-- Build a kernel suitable for running under the GDB simulator.
-- Primarily adjusts the kernel's notion of time.
--
--config SIBYTE_CFE
-- bool "Booting from CFE"
-- depends on SIBYTE_SB1xxx_SOC
-- help
-- Make use of the CFE API for enumerating available memory,
-- controlling secondary CPUs, and possibly console output.
--
--config SIBYTE_CFE_CONSOLE
-- bool "Use firmware console"
-- depends on SIBYTE_CFE
-- help
-- Use the CFE API's console write routines during boot. Other console
-- options (VT console, sb1250 duart console, etc.) should not be
-- configured.
--
--config SIBYTE_STANDALONE
-- bool
-- depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
-- default y
--
--config SIBYTE_STANDALONE_RAM_SIZE
-- int "Memory size (in megabytes)"
-- depends on SIBYTE_STANDALONE
-- default "32"
--
--config SIBYTE_BUS_WATCHER
-- bool "Support for Bus Watcher statistics"
-- depends on SIBYTE_SB1xxx_SOC
-- help
-- Handle and keep statistics on the bus error interrupts (COR_ECC,
-- BAD_ECC, IO_BUS).
--
--config SIBYTE_BW_TRACE
-- bool "Capture bus trace before bus error"
-- depends on SIBYTE_BUS_WATCHER
-- help
-- Run a continuous bus trace, dumping the raw data as soon as
-- a ZBbus error is detected. Cannot work if ZBbus profiling
-- is turned on, and also will interfere with JTAG-based trace
-- buffer activity. Raw buffer data is dumped to console, and
-- must be processed off-line.
--
--config SIBYTE_SB1250_PROF
-- bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
-- depends on SIBYTE_SB1xxx_SOC
--
--config SIBYTE_TBPROF
-- bool "Support for ZBbus profiling"
-- depends on SIBYTE_SB1xxx_SOC
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/decstation_defconfig linux-mips/arch/mips/configs/decstation_defconfig
+--- kernel.org/arch/mips/configs/decstation_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/decstation_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:13 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:44 2005
+ #
+ CONFIG_MIPS=y
- config SNI_RM200_PCI
- bool "Support for SNI RM200 PCI"
-@@ -877,31 +588,61 @@ config SNI_RM200_PCI
- select DMA_NONCOHERENT
- select GENERIC_ISA_DMA
- select HAVE_STD_PC_SERIAL_PORT
-+ select HW_HAS_EISA
- select HW_HAS_PCI
- select I8259
- select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
- Nixdorf Informationssysteme (SNI), parent company of Pyramid
- Technology and now in turn merged with Fujitsu. Say Y here to
- support this machine type.
+@@ -154,6 +154,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_ALL is not set
+@@ -163,7 +164,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -298,7 +298,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-+config TOSHIBA_JMR3927
-+ bool "Support for Toshiba JMR-TX3927 board"
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select MIPS_TX3927
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select TOSHIBA_BOARDS
-+
- config TOSHIBA_RBTX4927
- bool "Support for Toshiba TBTX49[23]7 board"
-- depends on MIPS32
- select DMA_NONCOHERENT
- select HAS_TXX9_SERIAL
- select HW_HAS_PCI
- select I8259
- select ISA
- select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select TOSHIBA_BOARDS
- help
- This Toshiba board is based on the TX4927 processor. Say Y here to
- support this machine type
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/e55_defconfig linux-mips/arch/mips/configs/e55_defconfig
+--- kernel.org/arch/mips/configs/e55_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/e55_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:14 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:46 2005
+ #
+ CONFIG_MIPS=y
--config TOSHIBA_FPCIB0
-- bool "FPCIB0 Backplane Support"
-- depends on TOSHIBA_RBTX4927
-+endchoice
-+
-+source "arch/mips/ddb5xxx/Kconfig"
-+source "arch/mips/gt64120/ev64120/Kconfig"
-+source "arch/mips/jazz/Kconfig"
-+source "arch/mips/ite-boards/Kconfig"
-+source "arch/mips/lasat/Kconfig"
-+source "arch/mips/momentum/Kconfig"
-+source "arch/mips/pmc-sierra/Kconfig"
-+source "arch/mips/sgi-ip27/Kconfig"
-+source "arch/mips/sibyte/Kconfig"
-+source "arch/mips/tx4927/Kconfig"
-+source "arch/mips/vr41xx/Kconfig"
-+
-+endmenu
+@@ -157,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -165,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -298,7 +298,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config RWSEM_GENERIC_SPINLOCK
- bool
-@@ -923,32 +664,30 @@ config HAVE_DEC_LOCK
#
- config ARC
- bool
-- depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
-- default y
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ev64120_defconfig linux-mips/arch/mips/configs/ev64120_defconfig
+--- kernel.org/arch/mips/configs/ev64120_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ev64120_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:16 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:48 2005
+ #
+ CONFIG_MIPS=y
--config DMA_COHERENT
-+config DMA_COHERENT
-+ bool
-+
-+config DMA_IP27
-+ bool
-+
-+config DMA_IP32
- bool
+@@ -118,7 +118,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -158,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -166,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -303,7 +302,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
--config DMA_IP27
-+config OWN_DMA
- bool
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ev96100_defconfig linux-mips/arch/mips/configs/ev96100_defconfig
+--- kernel.org/arch/mips/configs/ev96100_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ev96100_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:18 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:50 2005
+ #
+ CONFIG_MIPS=y
--config DMA_NONCOHERENT
-+config DMA_NONCOHERENT
- bool
+@@ -121,7 +121,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -162,6 +161,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -170,7 +170,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -305,7 +304,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config EARLY_PRINTK
- bool
-- depends on MACH_DECSTATION
-- default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ip22_defconfig linux-mips/arch/mips/configs/ip22_defconfig
+--- kernel.org/arch/mips/configs/ip22_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ip22_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:20 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:11 2005
+ #
+ CONFIG_MIPS=y
- config GENERIC_ISA_DMA
- bool
-- depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA
-- default y
+@@ -123,7 +123,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -164,6 +163,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -172,7 +172,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -505,7 +504,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config I8259
- bool
-- depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT
-- default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ip27_defconfig linux-mips/arch/mips/configs/ip27_defconfig
+--- kernel.org/arch/mips/configs/ip27_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ip27_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:21 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:55 2005
+ #
+ CONFIG_MIPS=y
- config LIMITED_DMA
- bool
-@@ -956,30 +695,46 @@ config LIMITED_DMA
+@@ -119,7 +119,6 @@
+ CONFIG_CPU_HAS_PREFETCH=y
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -166,6 +165,7 @@
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_CPUSETS=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -174,7 +174,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -357,7 +356,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config MIPS_BONITO64
- bool
-- depends on MIPS_ATLAS || MIPS_MALTA
-- default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ip32_defconfig linux-mips/arch/mips/configs/ip32_defconfig
+--- kernel.org/arch/mips/configs/ip32_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ip32_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:24 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:57 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_MSC
- bool
-- depends on MIPS_ATLAS || MIPS_MALTA
-- default y
+@@ -121,7 +121,6 @@
+ CONFIG_RM7000_CPU_SCACHE=y
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -162,6 +161,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -170,7 +170,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -306,7 +305,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config MIPS_NILE4
- bool
-- depends on LASAT
-- default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/it8172_defconfig linux-mips/arch/mips/configs/it8172_defconfig
+--- kernel.org/arch/mips/configs/it8172_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/it8172_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:26 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:59 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_DISABLE_OBSOLETE_IDE
- bool
+@@ -117,7 +117,6 @@
+ # CONFIG_MIPS_MT is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -158,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -166,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -302,7 +301,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
--config CPU_LITTLE_ENDIAN
-- bool "Generate little endian code"
-- default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
-- default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
-+#
-+# Endianess selection. Suffiently obscure so many users don't know what to
-+# answer,so we try hard to limit the available choices. Also the use of a
-+# choice statement should be more obvious to the user.
-+#
-+choice
-+ prompt "Endianess selection"
- help
- Some MIPS machines can be configured for either little or big endian
-- byte order. These modes require different kernels. Say Y if your
-- machine is little endian, N if it's a big endian machine.
-+ byte order. These modes require different kernels and a different
-+ Linux distribution. In general there is one prefered byteorder for a
-+ particular system but some systems are just as commonly used in the
-+ one or the other endianess.
-+
-+config CPU_BIG_ENDIAN
-+ bool "Big endian"
-+ depends on SYS_SUPPORTS_BIG_ENDIAN
-+
-+config CPU_LITTLE_ENDIAN
-+ bool "Little endian"
-+ depends on SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+
-+endchoice
-+
-+config SYS_SUPPORTS_BIG_ENDIAN
-+ bool
-+
-+config SYS_SUPPORTS_LITTLE_ENDIAN
-+ bool
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ivr_defconfig linux-mips/arch/mips/configs/ivr_defconfig
+--- kernel.org/arch/mips/configs/ivr_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ivr_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:27 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:01 2005
+ #
+ CONFIG_MIPS=y
- config IRQ_CPU
- bool
-@@ -987,42 +742,57 @@ config IRQ_CPU
- config IRQ_CPU_RM7K
- bool
+@@ -114,7 +114,6 @@
+ # CONFIG_MIPS_MT is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -155,6 +154,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -163,7 +163,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -301,7 +300,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-+config IRQ_CPU_RM9K
-+ bool
-+
- config IRQ_MV64340
- bool
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/jaguar-atx_defconfig linux-mips/arch/mips/configs/jaguar-atx_defconfig
+--- kernel.org/arch/mips/configs/jaguar-atx_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/jaguar-atx_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:29 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:03 2005
+ #
+ CONFIG_MIPS=y
- config DDB5XXX_COMMON
- bool
-- depends on DDB5074 || DDB5476 || DDB5477
-- default y
+@@ -124,7 +124,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -172,7 +171,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -295,7 +293,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config MIPS_BOARDS_GEN
- bool
-- depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
-- default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/jmr3927_defconfig linux-mips/arch/mips/configs/jmr3927_defconfig
+--- kernel.org/arch/mips/configs/jmr3927_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/jmr3927_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:31 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:05 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_GT64111
- bool
-- depends on MIPS_COBALT
-- default y
-
- config MIPS_GT64120
- bool
-- depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT
-- default y
-
- config MIPS_TX3927
- bool
-- depends on TOSHIBA_JMR3927
- select HAS_TXX9_SERIAL
-- default y
+@@ -152,6 +152,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -160,7 +161,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -292,7 +292,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config PCI_MARVELL
- bool
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/lasat200_defconfig linux-mips/arch/mips/configs/lasat200_defconfig
+--- kernel.org/arch/mips/configs/lasat200_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/lasat200_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:33 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:07 2005
+ #
+ CONFIG_MIPS=y
- config ITE_BOARD_GEN
- bool
-- depends on MIPS_IVR || MIPS_ITE8172
-- default y
-+
-+config SOC_AU1000
-+ bool
-+ select SOC_AU1X00
-+
-+config SOC_AU1100
-+ bool
-+ select SOC_AU1X00
-+
-+config SOC_AU1500
-+ bool
-+ select SOC_AU1X00
-+
-+config SOC_AU1550
-+ bool
-+ select SOC_AU1X00
-+
-+config SOC_AU1200
-+ bool
-+ select SOC_AU1X00
-+
-+config SOC_AU1X00
-+ bool
-+ select SYS_SUPPORTS_32BIT_KERNEL
+@@ -121,7 +121,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -161,6 +160,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -169,7 +169,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -303,7 +302,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config SWAP_IO_SPACE
- bool
-@@ -1049,6 +819,9 @@ config SYSCLK_100
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/malta_defconfig linux-mips/arch/mips/configs/malta_defconfig
+--- kernel.org/arch/mips/configs/malta_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/malta_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:35 2005
++# Linux kernel version: 2.6.15-rc5
++# Fri Dec 23 02:21:03 2005
+ #
+ CONFIG_MIPS=y
- endchoice
+@@ -87,8 +87,8 @@
+ #
+ # CPU selection
+ #
+-CONFIG_CPU_MIPS32_R1=y
+-# CONFIG_CPU_MIPS32_R2 is not set
++# CONFIG_CPU_MIPS32_R1 is not set
++CONFIG_CPU_MIPS32_R2=y
+ # CONFIG_CPU_MIPS64_R1 is not set
+ # CONFIG_CPU_MIPS64_R2 is not set
+ # CONFIG_CPU_R3000 is not set
+@@ -112,7 +112,7 @@
+ CONFIG_SYS_HAS_CPU_NEVADA=y
+ CONFIG_SYS_HAS_CPU_RM7000=y
+ CONFIG_CPU_MIPS32=y
+-CONFIG_CPU_MIPSR1=y
++CONFIG_CPU_MIPSR2=y
+ CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+ CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+ CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+@@ -174,6 +174,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -182,7 +183,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -559,7 +559,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-+config ARC32
-+ bool
-+
- config AU1X00_USB_DEVICE
- bool
- depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
-@@ -1056,11 +829,7 @@ config AU1X00_USB_DEVICE
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/mipssim_defconfig linux-mips/arch/mips/configs/mipssim_defconfig
+--- kernel.org/arch/mips/configs/mipssim_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/mipssim_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:37 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:13 2005
+ #
+ CONFIG_MIPS=y
- config MIPS_GT96100
- bool
-- depends on MIPS_EV96100
-- default y
-- help
-- Say Y here to support the Galileo Technology GT96100 communications
-- controller card. There is a web page at <http://www.galileot.com/>.
-+ select MIPS_GT64120
+@@ -160,6 +160,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_ALL is not set
+@@ -169,7 +170,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/mpc30x_defconfig linux-mips/arch/mips/configs/mpc30x_defconfig
+--- kernel.org/arch/mips/configs/mpc30x_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/mpc30x_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:39 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:15 2005
+ #
+ CONFIG_MIPS=y
- config IT8172_CIR
- bool
-@@ -1074,8 +843,6 @@ config IT8712
+@@ -159,6 +159,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -167,7 +168,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ocelot_3_defconfig linux-mips/arch/mips/configs/ocelot_3_defconfig
+--- kernel.org/arch/mips/configs/ocelot_3_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ocelot_3_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:41 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:18 2005
+ #
+ CONFIG_MIPS=y
- config BOOT_ELF32
- bool
-- depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
-- default y
+@@ -122,7 +122,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -165,6 +164,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -173,7 +173,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -345,7 +344,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config MIPS_L1_CACHE_SHIFT
- int
-@@ -1083,53 +850,11 @@ config MIPS_L1_CACHE_SHIFT
- default "7" if SGI_IP27
- default "5"
-
--config ARC32
-- bool
-- depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
-- default y
--
--config FB
-- bool
-- depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
-- default y
-- ---help---
-- The frame buffer device provides an abstraction for the graphics
-- hardware. It represents the frame buffer of some video hardware and
-- allows application software to access the graphics hardware through
-- a well-defined interface, so the software doesn't need to know
-- anything about the low-level (hardware register) stuff.
--
-- Frame buffer devices work identically across the different
-- architectures supported by Linux and make the implementation of
-- application programs easier and more portable; at this point, an X
-- server exists which uses the frame buffer device exclusively.
-- On several non-X86 architectures, the frame buffer device is the
-- only way to use the graphics hardware.
--
-- The device is accessed through special device nodes, usually located
-- in the /dev directory, i.e. /dev/fb*.
--
-- You need an utility program called fbset to make full use of frame
-- buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
-- and the Framebuffer-HOWTO at <http://www.tldp.org/docs.html#howto>
-- for more information.
--
-- Say Y here and to the driver for your graphics board below if you
-- are compiling a kernel for a non-x86 architecture.
--
-- If you are compiling for the x86 architecture, you can say Y if you
-- want to play with it, but it is not essential. Please note that
-- running graphical applications that directly touch the hardware
-- (e.g. an accelerated X server) and that are not frame buffer
-- device-aware may cause unexpected results. If unsure, say N.
--
- config HAVE_STD_PC_SERIAL_PORT
- bool
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ocelot_c_defconfig linux-mips/arch/mips/configs/ocelot_c_defconfig
+--- kernel.org/arch/mips/configs/ocelot_c_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ocelot_c_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:43 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:19 2005
+ #
+ CONFIG_MIPS=y
- config VR4181
- bool
-- depends on NEC_OSPREY
-- default y
+@@ -118,7 +118,6 @@
+ CONFIG_CPU_HAS_PREFETCH=y
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -159,6 +158,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -167,7 +167,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -302,7 +301,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config ARC_CONSOLE
- bool "ARC console support"
-@@ -1147,30 +872,15 @@ config ARC_PROMLIB
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ocelot_defconfig linux-mips/arch/mips/configs/ocelot_defconfig
+--- kernel.org/arch/mips/configs/ocelot_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ocelot_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:44 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:21 2005
+ #
+ CONFIG_MIPS=y
- config ARC64
- bool
-- depends on SGI_IP27
-- default y
+@@ -123,7 +123,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -164,6 +163,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -172,7 +172,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -301,7 +300,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config BOOT_ELF64
- bool
-- depends on SGI_IP27
-- default y
--
--#config MAPPED_PCI_IO y
--# bool
--# depends on SGI_IP27
--# default y
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/ocelot_g_defconfig linux-mips/arch/mips/configs/ocelot_g_defconfig
+--- kernel.org/arch/mips/configs/ocelot_g_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/ocelot_g_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:46 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:23 2005
+ #
+ CONFIG_MIPS=y
- config QL_ISP_A64
- bool
-- depends on SGI_IP27
-- default y
+@@ -121,7 +121,6 @@
+ CONFIG_CPU_HAS_PREFETCH=y
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -162,6 +161,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -170,7 +170,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -305,7 +304,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- config TOSHIBA_BOARDS
- bool
-- depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
-- default y
--
--endmenu
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/pb1100_defconfig linux-mips/arch/mips/configs/pb1100_defconfig
+--- kernel.org/arch/mips/configs/pb1100_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/pb1100_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:48 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:25 2005
+ #
+ CONFIG_MIPS=y
- menu "CPU selection"
+@@ -157,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -165,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -334,7 +334,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-@@ -1178,15 +888,32 @@ choice
- prompt "CPU type"
- default CPU_R4X00
-
--config CPU_MIPS32
-- bool "MIPS32"
--
--config CPU_MIPS64
-- bool "MIPS64"
-+config CPU_MIPS32_R1
-+ bool "MIPS32 Release 1"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_HAS_PREFETCH
-+ help
-+ Choose this option to build a kernel for release 1 or later of the
-+ MIPS32 architecture. Most modern embedded systems with a 32-bit
-+ MIPS processor are based on a MIPS32 processor. If you know the
-+ specific type of processor in your system, choose those that one
-+ otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
-+
-+config CPU_MIPS64_R1
-+ bool "MIPS64 Release 1"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-+ select CPU_HAS_PREFETCH
-+ help
-+ Choose this option to build a kernel for release 1 or later of the
-+ MIPS64 architecture. Many modern embedded systems with a 64-bit
-+ MIPS processor are based on a MIPS64 processor. If you know the
-+ specific type of processor in your system, choose those that one
-+ otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
-
- config CPU_R3000
- bool "R3000"
-- depends on MIPS32
-+ select CPU_SUPPORTS_32BIT_KERNEL
- help
- Please make sure to pick the right CPU type. Linux/MIPS is not
- designed to be generic, i.e. Kernels compiled for R3000 CPUs will
-@@ -1197,10 +924,12 @@ config CPU_R3000
-
- config CPU_TX39XX
- bool "R39XX"
-- depends on MIPS32
-+ select CPU_SUPPORTS_32BIT_KERNEL
-
- config CPU_VR41XX
- bool "R41xx"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- The options selects support for the NEC VR41xx series of processors.
- Only choose this option if you have one of these processors as a
-@@ -1209,61 +938,126 @@ config CPU_VR41XX
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/pb1500_defconfig linux-mips/arch/mips/configs/pb1500_defconfig
+--- kernel.org/arch/mips/configs/pb1500_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/pb1500_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:50 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:28 2005
+ #
+ CONFIG_MIPS=y
- config CPU_R4300
- bool "R4300"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- MIPS Technologies R4300-series processors.
+@@ -156,6 +156,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +165,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -340,7 +340,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config CPU_R4X00
- bool "R4x00"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- MIPS Technologies R4000-series processors other than 4300, including
- the R4000, R4400, R4600, and 4700.
-
- config CPU_TX49XX
- bool "R49XX"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-
- config CPU_R5000
- bool "R5000"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- MIPS Technologies R5000-series processors other than the Nevada.
-
- config CPU_R5432
- bool "R5432"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-
- config CPU_R6000
- bool "R6000"
-- depends on MIPS32 && EXPERIMENTAL
-+ depends on EXPERIMENTAL
-+ select CPU_SUPPORTS_32BIT_KERNEL
- help
- MIPS Technologies R6000 and R6000A series processors. Note these
- processors are extremly rare and the support for them is incomplete.
-
- config CPU_NEVADA
- bool "RM52xx"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- QED / PMC-Sierra RM52xx-series ("Nevada") processors.
-
- config CPU_R8000
- bool "R8000"
-- depends on MIPS64 && EXPERIMENTAL
-+ depends on EXPERIMENTAL
-+ select CPU_HAS_PREFETCH
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- MIPS Technologies R8000 processors. Note these processors are
- uncommon and the support for them is incomplete.
-
- config CPU_R10000
- bool "R10000"
-+ select CPU_HAS_PREFETCH
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
- help
- MIPS Technologies R10000-series processors.
-
- config CPU_RM7000
- bool "RM7000"
-+ select CPU_HAS_PREFETCH
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-
- config CPU_RM9000
- bool "RM9000"
-+ select CPU_HAS_PREFETCH
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-
- config CPU_SB1
- bool "SB1"
-+ select CPU_SUPPORTS_32BIT_KERNEL
-+ select CPU_SUPPORTS_64BIT_KERNEL
-+
-+endchoice
-+
-+endmenu
-+
-+config SYS_SUPPORTS_32BIT_KERNEL
-+ bool
-+config SYS_SUPPORTS_64BIT_KERNEL
-+ bool
-+config CPU_SUPPORTS_32BIT_KERNEL
-+ bool
-+config CPU_SUPPORTS_64BIT_KERNEL
-+ bool
-+
-+menu "Kernel type"
-+
-+choice
-+
-+ prompt "Kernel code model"
-+ help
-+ You should only select this option if you have a workload that
-+ actually benefits from 64-bit processing or if your machine has
-+ large memory. You will only be presented a single option in this
-+ menu if your system does not support both 32-bit and 64-bit kernels.
-+
-+config MIPS32
-+ bool "32-bit kernel"
-+ depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
-+ select TRAD_SIGNALS
-+ help
-+ Select this option if you want to build a 32-bit kernel.
-+config MIPS64
-+ bool "64-bit kernel"
-+ depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
-+ help
-+ Select this option if you want to build a 64-bit kernel.
-
- endchoice
-
-+config 64BIT
-+ def_bool MIPS64
-+
- choice
- prompt "Kernel page size"
- default PAGE_SIZE_4KB
-@@ -1332,12 +1126,7 @@ config SIBYTE_DMA_PAGEOPS
- SiByte Linux port. Seems to give a small performance benefit.
-
- config CPU_HAS_PREFETCH
-- bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
-- default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000
--
--config VTAG_ICACHE
-- bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
-- default y if CPU_SB1
-+ bool
-
- config SB1_PASS_1_WORKAROUNDS
- bool
-@@ -1356,7 +1145,7 @@ config SB1_PASS_2_1_WORKAROUNDS
-
- config 64BIT_PHYS_ADDR
- bool "Support for 64-bit physical address space"
-- depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32
-+ depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && MIPS32
-
- config CPU_ADVANCED
- bool "Override CPU Options"
-@@ -1379,7 +1168,7 @@ config CPU_HAS_LLSC
-
- config CPU_HAS_LLDSCD
- bool "lld/scd Instructions available" if CPU_ADVANCED
-- default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
-+ default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
- help
- Say Y here if your CPU has the lld and scd instructions, the 64-bit
- equivalents of ll and sc. Say Y here for better performance, N if
-@@ -1462,6 +1251,17 @@ config PREEMPT
- This allows applications to run more reliably even when the system is
- under load.
-
-+config PREEMPT_BKL
-+ bool "Preempt The Big Kernel Lock"
-+ depends on PREEMPT
-+ default y
-+ help
-+ This option reduces the latency of the kernel by making the
-+ big kernel lock preemptible.
-+
-+ Say Y here if you are building a kernel for a desktop system.
-+ Say N if you are unsure.
-+
- config RTC_DS1742
- bool "DS1742 BRAM/RTC support"
- depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
-@@ -1476,14 +1276,16 @@ config MIPS_INSANE_LARGE
- This will result in additional memory usage, so it is not
- recommended for normal users.
-
-+endmenu
-+
- config RWSEM_GENERIC_SPINLOCK
- bool
- default y
-
--endmenu
--
- menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
-
-+config HW_HAS_EISA
-+ bool
- config HW_HAS_PCI
- bool
-
-@@ -1517,7 +1319,7 @@ config ISA
-
- config EISA
- bool "EISA support"
-- depends on SGI_IP22 || SNI_RM200_PCI
-+ depends on HW_HAS_EISA
- select ISA
- ---help---
- The Extended Industry Standard Architecture (EISA) bus was
-@@ -1551,12 +1353,6 @@ config MMU
- bool
- default y
-
--config MCA
-- bool
--
--config SBUS
-- bool
--
- source "drivers/pcmcia/Kconfig"
-
- source "drivers/pci/hotplug/Kconfig"
-@@ -1569,7 +1365,6 @@ source "fs/Kconfig.binfmt"
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/pb1550_defconfig linux-mips/arch/mips/configs/pb1550_defconfig
+--- kernel.org/arch/mips/configs/pb1550_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/pb1550_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:52 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:31 2005
+ #
+ CONFIG_MIPS=y
- config TRAD_SIGNALS
- bool
-- default y if MIPS32
+@@ -156,6 +156,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +165,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -340,7 +340,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- config BUILD_ELF64
- bool "Use 64-bit ELF format for building"
-@@ -1588,7 +1383,7 @@ config BUILD_ELF64
-
- config BINFMT_IRIX
- bool "Include IRIX binary compatibility"
-- depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN
-+ depends on CPU_BIG_ENDIAN && MIPS32 && BROKEN
-
- config MIPS32_COMPAT
- bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
-@@ -1628,9 +1423,26 @@ config BINFMT_ELF32
- bool
- default y if MIPS32_O32 || MIPS32_N32
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/pnx8550-jbs_defconfig linux-mips/arch/mips/configs/pnx8550-jbs_defconfig
+--- kernel.org/arch/mips/configs/pnx8550-jbs_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/pnx8550-jbs_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:54 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:33 2005
+ #
+ CONFIG_MIPS=y
-+config SECCOMP
-+ bool "Enable seccomp to safely compute untrusted bytecode"
-+ depends on PROC_FS && BROKEN
-+ default y
-+ help
-+ This kernel feature is useful for number crunching applications
-+ that may need to compute untrusted bytecode during their
-+ execution. By using pipes or other transports made available to
-+ the process as file descriptors supporting the read/write
-+ syscalls, it's possible to isolate those applications in
-+ their own address space using seccomp. Once seccomp is
-+ enabled via /proc/<pid>/seccomp, it cannot be disabled
-+ and the task is only allowed to execute a few safe syscalls
-+ defined by each seccomp mode.
-+
-+ If unsure, say Y. Only embedded should say N here.
-+
- config PM
- bool "Power Management support (EXPERIMENTAL)"
-- depends on EXPERIMENTAL && MACH_AU1X00
-+ depends on EXPERIMENTAL && SOC_AU1X00
+@@ -156,6 +156,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_ALL is not set
+@@ -165,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/pnx8550-v2pci_defconfig linux-mips/arch/mips/configs/pnx8550-v2pci_defconfig
+--- kernel.org/arch/mips/configs/pnx8550-v2pci_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/pnx8550-v2pci_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:06:58 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:36 2005
+ #
+ CONFIG_MIPS=y
- endmenu
+@@ -116,7 +116,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ CONFIG_CPU_ADVANCED=y
+ CONFIG_CPU_HAS_LLSC=y
+-# CONFIG_CPU_HAS_LLDSCD is not set
+ # CONFIG_CPU_HAS_WB is not set
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+@@ -158,6 +157,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -166,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/qemu_defconfig linux-mips/arch/mips/configs/qemu_defconfig
+--- kernel.org/arch/mips/configs/qemu_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/qemu_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:00 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:38 2005
+ #
+ CONFIG_MIPS=y
-@@ -1638,6 +1450,8 @@ source "drivers/Kconfig"
+@@ -159,7 +159,6 @@
+ # CONFIG_BASE_FULL is not set
+ # CONFIG_FUTEX is not set
+ # CONFIG_EPOLL is not set
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ # CONFIG_SHMEM is not set
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -270,7 +269,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=y
+ CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_CRYPT_TKIP=y
- source "fs/Kconfig"
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/rbhma4500_defconfig linux-mips/arch/mips/configs/rbhma4500_defconfig
+--- kernel.org/arch/mips/configs/rbhma4500_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/rbhma4500_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:03 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:42 2005
+ #
+ CONFIG_MIPS=y
-+source "arch/mips/oprofile/Kconfig"
-+
- source "arch/mips/Kconfig.debug"
+@@ -124,7 +124,6 @@
+ # CONFIG_MIPS_MT is not set
+ CONFIG_CPU_ADVANCED=y
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_WB=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+@@ -166,6 +165,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -174,7 +174,6 @@
+ CONFIG_BASE_FULL=y
+ # CONFIG_FUTEX is not set
+ # CONFIG_EPOLL is not set
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/rm200_defconfig linux-mips/arch/mips/configs/rm200_defconfig
+--- kernel.org/arch/mips/configs/rm200_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/rm200_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:06 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:45 2005
+ #
+ CONFIG_MIPS=y
- source "security/Kconfig"
-@@ -1656,7 +1470,3 @@ config GENERIC_HARDIRQS
- config GENERIC_IRQ_PROBE
- bool
- default y
--
--config ISA_DMA_API
-- bool
-- default y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/Makefile linux_HEAD/arch/mips/Makefile
---- linux-2.6.12/arch/mips/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/Makefile 2005-07-10 12:16:33.000000000 +0200
-@@ -52,6 +52,16 @@ ifdef CONFIG_CROSSCOMPILE
- CROSS_COMPILE := $(tool-prefix)
- endif
+@@ -124,7 +124,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -167,6 +166,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -175,7 +175,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -531,7 +530,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-+CHECKFLAGS-y += -D__linux__ -D__mips__
-+CHECKFLAGS-$(CONFIG_MIPS32) += -D_MIPS_SZLONG=32 \
-+ -D__PTRDIFF_TYPE__=int
-+CHECKFLAGS-$(CONFIG_MIPS64) += -D_MIPS_SZLONG=64 \
-+ -D__PTRDIFF_TYPE__="long int"
-+CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__
-+CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__
-+
-+CHECKFLAGS = $(CHECKFLAGS-y)
-+
- ifdef CONFIG_BUILD_ELF64
- gas-abi = 64
- ld-emul = $(64bit-emul)
-@@ -79,10 +89,20 @@ endif
- cflags-y += -I $(TOPDIR)/include/asm/gcc
- cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
- cflags-y += $(call cc-option, -finline-limit=100000)
--LDFLAGS_vmlinux += -G 0 -static -n
-+LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
- MODFLAGS += -mlong-calls
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/sb1250-swarm_defconfig linux-mips/arch/mips/configs/sb1250-swarm_defconfig
+--- kernel.org/arch/mips/configs/sb1250-swarm_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/sb1250-swarm_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:09 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:47 2005
+ #
+ CONFIG_MIPS=y
--cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
-+#
-+# We explicitly add the endianness specifier if needed, this allows
-+# to compile kernels with a toolchain for the other endianness. We
-+# carefully avoid to add it redundantly because gcc 3.3/3.4 complains
-+# when fed the toolchain default!
-+#
-+cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
-+cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
-+
-+cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-+ -fno-omit-frame-pointer
+@@ -133,7 +133,6 @@
+ # CONFIG_MIPS_MT is not set
+ CONFIG_SB1_PASS_1_WORKAROUNDS=y
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -179,6 +178,7 @@
+ # CONFIG_IKCONFIG is not set
+ CONFIG_CPUSETS=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -187,7 +187,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -330,7 +329,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
#
- # Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
-@@ -167,11 +187,11 @@ cflags-$(CONFIG_CPU_TX49XX) += \
- $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
- -Wa,--trap
-
--cflags-$(CONFIG_CPU_MIPS32) += \
-+cflags-$(CONFIG_CPU_MIPS32_R1) += \
- $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
- -Wa,--trap
-
--cflags-$(CONFIG_CPU_MIPS64) += \
-+cflags-$(CONFIG_CPU_MIPS64_R1) += \
- $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
- -Wa,--trap
-
-@@ -266,6 +286,13 @@ cflags-$(CONFIG_MIPS_PB1550) += -Iinclud
- load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/sead_defconfig linux-mips/arch/mips/configs/sead_defconfig
+--- kernel.org/arch/mips/configs/sead_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/sead_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:10 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:49 2005
+ #
+ CONFIG_MIPS=y
+@@ -156,6 +156,7 @@
+ # CONFIG_HOTPLUG is not set
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -164,7 +165,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/tb0226_defconfig linux-mips/arch/mips/configs/tb0226_defconfig
+--- kernel.org/arch/mips/configs/tb0226_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/tb0226_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
#
-+# AMD Alchemy Pb1200 eval board
-+#
-+libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/
-+cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00
-+load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
-+
-+#
- # AMD Alchemy Db1000 eval board
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:12 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:51 2005
#
- libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/
-@@ -294,6 +321,13 @@ cflags-$(CONFIG_MIPS_DB1550) += -Iinclud
- load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
+ CONFIG_MIPS=y
+
+@@ -160,6 +160,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -168,7 +169,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -313,7 +313,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
#
-+# AMD Alchemy Db1200 eval board
-+#
-+libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/
-+cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00
-+load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
-+
-+#
- # AMD Alchemy Bosporus eval board
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/tb0229_defconfig linux-mips/arch/mips/configs/tb0229_defconfig
+--- kernel.org/arch/mips/configs/tb0229_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/tb0229_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
#
- libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/
-@@ -323,6 +357,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xfffffff
- # Cobalt Server
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:15 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:54 2005
#
- core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
-+cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
- load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
+ CONFIG_MIPS=y
- #
-@@ -469,13 +504,6 @@ cflags-$(CONFIG_LASAT) += -Iinclude/asm
- load-$(CONFIG_LASAT) += 0xffffffff80000000
+@@ -160,6 +160,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -168,7 +169,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -314,7 +314,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
#
--# NEC Osprey (vr4181) board
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/tb0287_defconfig linux-mips/arch/mips/configs/tb0287_defconfig
+--- kernel.org/arch/mips/configs/tb0287_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/tb0287_defconfig 1970-01-01 01:00:00.000000000 +0100
+@@ -1,1105 +0,0 @@
+-#
+-# Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.14-rc5-mm1
+-# Tue Oct 25 00:20:22 2005
-#
--core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \
-- arch/mips/vr4181/osprey/
--load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000
+-CONFIG_MIPS=y
-
-#
- # Common VR41xx
- #
- core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
-@@ -711,6 +739,18 @@ ifdef CONFIG_BOOT_ELF64
- all: $(vmlinux-64)
- endif
-
-+ifdef CONFIG_MIPS_ATLAS
-+all: vmlinux.srec
-+endif
-+
-+ifdef CONFIG_MIPS_MALTA
-+all: vmlinux.srec
-+endif
-+
-+ifdef CONFIG_MIPS_SEAD
-+all: vmlinux.srec
-+endif
-+
- ifdef CONFIG_SNI_RM200_PCI
- all: vmlinux.ecoff
- endif
-diff -urpNX dontdiff linux-2.6.12/arch/mips/arc/Makefile linux_HEAD/arch/mips/arc/Makefile
---- linux-2.6.12/arch/mips/arc/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/arc/Makefile 2005-03-09 22:46:10.000000000 +0100
-@@ -3,7 +3,7 @@
- #
-
- lib-y += cmdline.o env.o file.o identify.o init.o \
-- misc.o time.o tree.o
-+ misc.o salone.o time.o tree.o
-
- lib-$(CONFIG_ARC_MEMORY) += memory.o
- lib-$(CONFIG_ARC_CONSOLE) += arc_con.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/arc/identify.c linux_HEAD/arch/mips/arc/identify.c
---- linux-2.6.12/arch/mips/arc/identify.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/arc/identify.c 2005-07-08 12:04:09.000000000 +0200
-@@ -44,6 +44,11 @@ static struct smatch mach_table[] = {
- MACH_GROUP_SGI,
- MACH_SGI_IP28,
- PROM_FLAG_ARCS
-+ }, { "SGI-IP30",
-+ "SGI Octane",
-+ MACH_GROUP_SGI,
-+ MACH_SGI_IP30,
-+ PROM_FLAG_ARCS
- }, { "SGI-IP32",
- "SGI O2",
- MACH_GROUP_SGI,
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/au1xxx_irqmap.c linux_HEAD/arch/mips/au1000/common/au1xxx_irqmap.c
---- linux-2.6.12/arch/mips/au1000/common/au1xxx_irqmap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/au1xxx_irqmap.c 2005-03-01 15:00:11.000000000 +0100
-@@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
- { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
- { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
- { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
-- { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-- { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-+ { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
- { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
- { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
- { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
-@@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
- { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
- { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
- { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
-- { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-- { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-- { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-+ { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-+ { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
- { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
- { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
- { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/cputable.c linux_HEAD/arch/mips/au1000/common/cputable.c
---- linux-2.6.12/arch/mips/au1000/common/cputable.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/cputable.c 2005-03-01 15:00:11.000000000 +0100
-@@ -37,7 +37,8 @@ struct cpu_spec cpu_specs[] = {
- { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
- { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
- { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
-- { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
-+ { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
-+ { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 },
- { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
- };
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/dbdma.c linux_HEAD/arch/mips/au1000/common/dbdma.c
---- linux-2.6.12/arch/mips/au1000/common/dbdma.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/dbdma.c 2005-03-01 15:00:11.000000000 +0100
-@@ -29,6 +29,7 @@
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-+
- #include <linux/config.h>
- #include <linux/kernel.h>
- #include <linux/errno.h>
-@@ -38,10 +39,12 @@
- #include <linux/string.h>
- #include <linux/delay.h>
- #include <linux/interrupt.h>
-+#include <linux/module.h>
- #include <asm/mach-au1x00/au1000.h>
- #include <asm/mach-au1x00/au1xxx_dbdma.h>
- #include <asm/system.h>
-
-+
- #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-
- /*
-@@ -55,43 +58,16 @@
- * functions. The drivers allocate the data buffers and assign them
- * to the descriptors.
- */
--static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
-+static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED;
-
- /* I couldn't find a macro that did this......
- */
- #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
-
--static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
--static int dbdma_initialized;
-+static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
-+static int dbdma_initialized=0;
- static void au1xxx_dbdma_init(void);
-
--typedef struct dbdma_device_table {
-- u32 dev_id;
-- u32 dev_flags;
-- u32 dev_tsize;
-- u32 dev_devwidth;
-- u32 dev_physaddr; /* If FIFO */
-- u32 dev_intlevel;
-- u32 dev_intpolarity;
--} dbdev_tab_t;
--
--typedef struct dbdma_chan_config {
-- u32 chan_flags;
-- u32 chan_index;
-- dbdev_tab_t *chan_src;
-- dbdev_tab_t *chan_dest;
-- au1x_dma_chan_t *chan_ptr;
-- au1x_ddma_desc_t *chan_desc_base;
-- au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
-- void *chan_callparam;
-- void (*chan_callback)(int, void *, struct pt_regs *);
--} chan_tab_t;
--
--#define DEV_FLAGS_INUSE (1 << 0)
--#define DEV_FLAGS_ANYUSE (1 << 1)
--#define DEV_FLAGS_OUT (1 << 2)
--#define DEV_FLAGS_IN (1 << 3)
--
- static dbdev_tab_t dbdev_tab[] = {
- #ifdef CONFIG_SOC_AU1550
- /* UARTS */
-@@ -157,13 +133,13 @@ static dbdev_tab_t dbdev_tab[] = {
- { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-
-- { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-+ { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
-+ { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
-+ { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
-+ { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
-
-- { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-+ { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
-+ { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
-
- { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
-@@ -173,9 +149,9 @@ static dbdev_tab_t dbdev_tab[] = {
- { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-
-- { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-- { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-+ { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
-+ { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
-+ { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
- { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-
- { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-@@ -184,6 +160,24 @@ static dbdev_tab_t dbdev_tab[] = {
-
- { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-+
-+ /* Provide 16 user definable device types */
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
-+ { 0, 0, 0, 0, 0, 0, 0 },
- };
-
- #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
-@@ -203,6 +197,30 @@ find_dbdev_id (u32 id)
- return NULL;
- }
-
-+u32
-+au1xxx_ddma_add_device(dbdev_tab_t *dev)
-+{
-+ u32 ret = 0;
-+ dbdev_tab_t *p=NULL;
-+ static u16 new_id=0x1000;
-+
-+ p = find_dbdev_id(0);
-+ if ( NULL != p )
-+ {
-+ memcpy(p, dev, sizeof(dbdev_tab_t));
-+ p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
-+ ret = p->dev_id;
-+ new_id++;
-+#if 0
-+ printk("add_device: id:%x flags:%x padd:%x\n",
-+ p->dev_id, p->dev_flags, p->dev_physaddr );
-+#endif
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(au1xxx_ddma_add_device);
-+
- /* Allocate a channel and return a non-zero descriptor if successful.
- */
- u32
-@@ -215,7 +233,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
- int i;
- dbdev_tab_t *stp, *dtp;
- chan_tab_t *ctp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
-
- /* We do the intialization on the first channel allocation.
- * We have to wait because of the interrupt handler initialization
-@@ -225,9 +243,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
- au1xxx_dbdma_init();
- dbdma_initialized = 1;
-
-- if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
-- return 0;
--
- if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
- if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
-
-@@ -269,9 +284,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
- /* If kmalloc fails, it is caught below same
- * as a channel not available.
- */
-- ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
-+ ctp = (chan_tab_t *)
-+ kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
- chan_tab_ptr[i] = ctp;
-- ctp->chan_index = chan = i;
- break;
- }
- }
-@@ -279,10 +294,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
-
- if (ctp != NULL) {
- memset(ctp, 0, sizeof(chan_tab_t));
-+ ctp->chan_index = chan = i;
- dcp = DDMA_CHANNEL_BASE;
- dcp += (0x0100 * chan);
- ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
-- cp = (volatile au1x_dma_chan_t *)dcp;
-+ cp = (au1x_dma_chan_t *)dcp;
- ctp->chan_src = stp;
- ctp->chan_dest = dtp;
- ctp->chan_callback = callback;
-@@ -299,6 +315,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
- i |= DDMA_CFG_DED;
- if (dtp->dev_intpolarity)
- i |= DDMA_CFG_DP;
-+ if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
-+ (dtp->dev_flags & DEV_FLAGS_SYNC))
-+ i |= DDMA_CFG_SYNC;
- cp->ddma_cfg = i;
- au_sync();
-
-@@ -309,14 +328,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 d
- rv = (u32)(&chan_tab_ptr[chan]);
- }
- else {
-- /* Release devices.
-- */
-+ /* Release devices */
- stp->dev_flags &= ~DEV_FLAGS_INUSE;
- dtp->dev_flags &= ~DEV_FLAGS_INUSE;
- }
- }
- return rv;
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
-
- /* Set the device width if source or destination is a FIFO.
- * Should be 8, 16, or 32 bits.
-@@ -344,6 +363,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, in
-
- return rv;
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
-
- /* Allocate a descriptor ring, initializing as much as possible.
- */
-@@ -370,7 +390,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
- * and if we try that first we are likely to not waste larger
- * slabs of memory.
- */
-- desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
-+ desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
-+ GFP_KERNEL|GFP_DMA);
- if (desc_base == 0)
- return 0;
-
-@@ -381,7 +402,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
- kfree((const void *)desc_base);
- i = entries * sizeof(au1x_ddma_desc_t);
- i += (sizeof(au1x_ddma_desc_t) - 1);
-- if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
-+ if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
- return 0;
-
- desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
-@@ -461,9 +482,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
- /* If source input is fifo, set static address.
- */
- if (stp->dev_flags & DEV_FLAGS_IN) {
-- src0 = stp->dev_physaddr;
-+ if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
-+ src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
-+ else
- src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
-+
- }
-+ if (stp->dev_physaddr)
-+ src0 = stp->dev_physaddr;
-
- /* Set up dest1. For now, assume no stride and increment.
- * A channel attribute update can change this later.
-@@ -487,10 +513,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
- /* If destination output is fifo, set static address.
- */
- if (dtp->dev_flags & DEV_FLAGS_OUT) {
-- dest0 = dtp->dev_physaddr;
-+ if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
-+ dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
-+ else
- dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
- }
-+ if (dtp->dev_physaddr)
-+ dest0 = dtp->dev_physaddr;
-
-+#if 0
-+ printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
-+ dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
-+#endif
- for (i=0; i<entries; i++) {
- dp->dscr_cmd0 = cmd0;
- dp->dscr_cmd1 = cmd1;
-@@ -499,6 +533,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
- dp->dscr_dest0 = dest0;
- dp->dscr_dest1 = dest1;
- dp->dscr_stat = 0;
-+ dp->sw_context = dp->sw_status = 0;
- dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
- dp++;
- }
-@@ -511,13 +546,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int
-
- return (u32)(ctp->chan_desc_base);
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
-
- /* Put a source buffer into the DMA ring.
- * This updates the source pointer and byte count. Normally used
- * for memory to fifo transfers.
- */
- u32
--au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
-+_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
- {
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
-@@ -544,24 +580,40 @@ au1xxx_dbdma_put_source(u32 chanid, void
- */
- dp->dscr_source0 = virt_to_phys(buf);
- dp->dscr_cmd1 = nbytes;
-- dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
-- ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
--
-+ /* Check flags */
-+ if (flags & DDMA_FLAGS_IE)
-+ dp->dscr_cmd0 |= DSCR_CMD0_IE;
-+ if (flags & DDMA_FLAGS_NOIE)
-+ dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
- /* Get next descriptor pointer.
- */
- ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
-
-+ /*
-+ * There is an errata on the Au1200/Au1550 parts that could result
-+ * in "stale" data being DMA'd. It has to do with the snoop logic on
-+ * the dache eviction buffer. NONCOHERENT_IO is on by default for
-+ * these parts. If it is fixedin the future, these dma_cache_inv will
-+ * just be nothing more than empty macros. See io.h.
-+ * */
-+ dma_cache_wback_inv((unsigned long)buf, nbytes);
-+ dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
-+ au_sync();
-+ dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
-+ ctp->chan_ptr->ddma_dbell = 0;
-+
- /* return something not zero.
- */
- return nbytes;
- }
-+EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
-
- /* Put a destination buffer into the DMA ring.
- * This updates the destination pointer and byte count. Normally used
- * to place an empty buffer into the ring for fifo to memory transfers.
- */
- u32
--au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
-+_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
- {
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
-@@ -583,11 +635,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void *
- if (dp->dscr_cmd0 & DSCR_CMD0_V)
- return 0;
-
-- /* Load up buffer address and byte count.
-- */
-+ /* Load up buffer address and byte count */
-+
-+ /* Check flags */
-+ if (flags & DDMA_FLAGS_IE)
-+ dp->dscr_cmd0 |= DSCR_CMD0_IE;
-+ if (flags & DDMA_FLAGS_NOIE)
-+ dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
-+
- dp->dscr_dest0 = virt_to_phys(buf);
- dp->dscr_cmd1 = nbytes;
-+#if 0
-+ printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
-+ dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
-+ dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
-+#endif
-+ /*
-+ * There is an errata on the Au1200/Au1550 parts that could result in
-+ * "stale" data being DMA'd. It has to do with the snoop logic on the
-+ * dache eviction buffer. NONCOHERENT_IO is on by default for these
-+ * parts. If it is fixedin the future, these dma_cache_inv will just
-+ * be nothing more than empty macros. See io.h.
-+ * */
-+ dma_cache_inv((unsigned long)buf,nbytes);
- dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
-+ au_sync();
-+ dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
-+ ctp->chan_ptr->ddma_dbell = 0;
-
- /* Get next descriptor pointer.
- */
-@@ -597,6 +671,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void *
- */
- return nbytes;
- }
-+EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
-
- /* Get a destination buffer into the DMA ring.
- * Normally used to get a full buffer from the ring during fifo
-@@ -646,7 +721,7 @@ void
- au1xxx_dbdma_stop(u32 chanid)
- {
- chan_tab_t *ctp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
- int halt_timeout = 0;
-
- ctp = *((chan_tab_t **)chanid);
-@@ -666,6 +741,7 @@ au1xxx_dbdma_stop(u32 chanid)
- cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
- au_sync();
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_stop);
-
- /* Start using the current descriptor pointer. If the dbdma encounters
- * a not valid descriptor, it will stop. In this case, we can just
-@@ -675,17 +751,17 @@ void
- au1xxx_dbdma_start(u32 chanid)
- {
- chan_tab_t *ctp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
-
- ctp = *((chan_tab_t **)chanid);
--
- cp = ctp->chan_ptr;
- cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
- cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
- au_sync();
-- cp->ddma_dbell = 0xffffffff; /* Make it go */
-+ cp->ddma_dbell = 0;
- au_sync();
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_start);
-
- void
- au1xxx_dbdma_reset(u32 chanid)
-@@ -704,15 +780,21 @@ au1xxx_dbdma_reset(u32 chanid)
-
- do {
- dp->dscr_cmd0 &= ~DSCR_CMD0_V;
-+ /* reset our SW status -- this is used to determine
-+ * if a descriptor is in use by upper level SW. Since
-+ * posting can reset 'V' bit.
-+ */
-+ dp->sw_status = 0;
- dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
- } while (dp != ctp->chan_desc_base);
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_reset);
-
- u32
- au1xxx_get_dma_residue(u32 chanid)
- {
- chan_tab_t *ctp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
- u32 rv;
-
- ctp = *((chan_tab_t **)chanid);
-@@ -739,7 +821,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
- au1xxx_dbdma_stop(chanid);
-
- if (ctp->chan_desc_base != NULL)
-- kfree(ctp->chan_desc_base);
-+ kfree((void *)ctp->chan_desc_base);
-
- stp->dev_flags &= ~DEV_FLAGS_INUSE;
- dtp->dev_flags &= ~DEV_FLAGS_INUSE;
-@@ -747,15 +829,16 @@ au1xxx_dbdma_chan_free(u32 chanid)
-
- kfree(ctp);
- }
-+EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
-
- static irqreturn_t
- dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
- {
-- u32 intstat;
-- u32 chan_index;
-+ u32 intstat;
-+ u32 chan_index;
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
-
- intstat = dbdma_gptr->ddma_intstat;
- au_sync();
-@@ -774,19 +857,27 @@ dbdma_interrupt(int irq, void *dev_id, s
- (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
-
- ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
--
-- return IRQ_HANDLED;
-+ return IRQ_RETVAL(1);
- }
-
--static void
--au1xxx_dbdma_init(void)
-+static void au1xxx_dbdma_init(void)
- {
-+ int irq_nr;
-+
- dbdma_gptr->ddma_config = 0;
- dbdma_gptr->ddma_throttle = 0;
- dbdma_gptr->ddma_inten = 0xffff;
- au_sync();
-
-- if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
-+#if defined(CONFIG_SOC_AU1550)
-+ irq_nr = AU1550_DDMA_INT;
-+#elif defined(CONFIG_SOC_AU1200)
-+ irq_nr = AU1200_DDMA_INT;
-+#else
-+ #error Unknown Au1x00 SOC
-+#endif
-+
-+ if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
- "Au1xxx dbdma", (void *)dbdma_gptr))
- printk("Can't get 1550 dbdma irq");
- }
-@@ -797,7 +888,8 @@ au1xxx_dbdma_dump(u32 chanid)
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
- dbdev_tab_t *stp, *dtp;
-- volatile au1x_dma_chan_t *cp;
-+ au1x_dma_chan_t *cp;
-+ u32 i = 0;
-
- ctp = *((chan_tab_t **)chanid);
- stp = ctp->chan_src;
-@@ -822,15 +914,64 @@ au1xxx_dbdma_dump(u32 chanid)
- dp = ctp->chan_desc_base;
-
- do {
-- printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
-- (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
-- printk("src0 %08x, src1 %08x, dest0 %08x\n",
-- dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
-- printk("dest1 %08x, stat %08x, nxtptr %08x\n",
-- dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
-+ printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
-+ i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
-+ printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
-+ dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
-+ printk("stat %08x, nxtptr %08x\n",
-+ dp->dscr_stat, dp->dscr_nxtptr);
- dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
- } while (dp != ctp->chan_desc_base);
- }
-
-+/* Put a descriptor into the DMA ring.
-+ * This updates the source/destination pointers and byte count.
-+ */
-+u32
-+au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
-+{
-+ chan_tab_t *ctp;
-+ au1x_ddma_desc_t *dp;
-+ u32 nbytes=0;
-+
-+ /* I guess we could check this to be within the
-+ * range of the table......
-+ */
-+ ctp = *((chan_tab_t **)chanid);
-+
-+ /* We should have multiple callers for a particular channel,
-+ * an interrupt doesn't affect this pointer nor the descriptor,
-+ * so no locking should be needed.
-+ */
-+ dp = ctp->put_ptr;
-+
-+ /* If the descriptor is valid, we are way ahead of the DMA
-+ * engine, so just return an error condition.
-+ */
-+ if (dp->dscr_cmd0 & DSCR_CMD0_V)
-+ return 0;
-+
-+ /* Load up buffer addresses and byte count.
-+ */
-+ dp->dscr_dest0 = dscr->dscr_dest0;
-+ dp->dscr_source0 = dscr->dscr_source0;
-+ dp->dscr_dest1 = dscr->dscr_dest1;
-+ dp->dscr_source1 = dscr->dscr_source1;
-+ dp->dscr_cmd1 = dscr->dscr_cmd1;
-+ nbytes = dscr->dscr_cmd1;
-+ /* Allow the caller to specifiy if an interrupt is generated */
-+ dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
-+ dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
-+ ctp->chan_ptr->ddma_dbell = 0;
-+
-+ /* Get next descriptor pointer.
-+ */
-+ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
-+
-+ /* return something not zero.
-+ */
-+ return nbytes;
-+}
-+
- #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/dma.c linux_HEAD/arch/mips/au1000/common/dma.c
---- linux-2.6.12/arch/mips/au1000/common/dma.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/dma.c 2005-04-14 16:40:12.000000000 +0200
-@@ -39,7 +39,6 @@
- #include <linux/string.h>
- #include <linux/delay.h>
- #include <linux/interrupt.h>
--#include <linux/module.h>
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
- #include <asm/mach-au1x00/au1000_dma.h>
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/irq.c linux_HEAD/arch/mips/au1000/common/irq.c
---- linux-2.6.12/arch/mips/au1000/common/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/irq.c 2005-03-17 22:10:46.000000000 +0100
-@@ -253,52 +253,70 @@ void restore_local_and_enable(int contro
-
-
- static struct hw_interrupt_type rise_edge_irq_type = {
-- "Au1000 Rise Edge",
-- startup_irq,
-- shutdown_irq,
-- local_enable_irq,
-- local_disable_irq,
-- mask_and_ack_rise_edge_irq,
-- end_irq,
-- NULL
-+ .typename = "Au1000 Rise Edge",
-+ .startup = startup_irq,
-+ .shutdown = shutdown_irq,
-+ .enable = local_enable_irq,
-+ .disable = local_disable_irq,
-+ .ack = mask_and_ack_rise_edge_irq,
-+ .end = end_irq,
- };
-
- static struct hw_interrupt_type fall_edge_irq_type = {
-- "Au1000 Fall Edge",
-- startup_irq,
-- shutdown_irq,
-- local_enable_irq,
-- local_disable_irq,
-- mask_and_ack_fall_edge_irq,
-- end_irq,
-- NULL
-+ .typename = "Au1000 Fall Edge",
-+ .startup = startup_irq,
-+ .shutdown = shutdown_irq,
-+ .enable = local_enable_irq,
-+ .disable = local_disable_irq,
-+ .ack = mask_and_ack_fall_edge_irq,
-+ .end = end_irq,
- };
-
- static struct hw_interrupt_type either_edge_irq_type = {
-- "Au1000 Rise or Fall Edge",
-- startup_irq,
-- shutdown_irq,
-- local_enable_irq,
-- local_disable_irq,
-- mask_and_ack_either_edge_irq,
-- end_irq,
-- NULL
-+ .typename = "Au1000 Rise or Fall Edge",
-+ .startup = startup_irq,
-+ .shutdown = shutdown_irq,
-+ .enable = local_enable_irq,
-+ .disable = local_disable_irq,
-+ .ack = mask_and_ack_either_edge_irq,
-+ .end = end_irq,
- };
-
- static struct hw_interrupt_type level_irq_type = {
-- "Au1000 Level",
-- startup_irq,
-- shutdown_irq,
-- local_enable_irq,
-- local_disable_irq,
-- mask_and_ack_level_irq,
-- end_irq,
-- NULL
-+ .typename = "Au1000 Level",
-+ .startup = startup_irq,
-+ .shutdown = shutdown_irq,
-+ .enable = local_enable_irq,
-+ .disable = local_disable_irq,
-+ .ack = mask_and_ack_level_irq,
-+ .end = end_irq,
- };
-
- #ifdef CONFIG_PM
--void startup_match20_interrupt(void)
-+void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *))
- {
-+ static struct irqaction action;
-+ /* This is a big problem.... since we didn't use request_irq
-+ when kernel/irq.c calls probe_irq_xxx this interrupt will
-+ be probed for usage. This will end up disabling the device :(
-+
-+ Give it a bogus "action" pointer -- this will keep it from
-+ getting auto-probed!
-+
-+ By setting the status to match that of request_irq() we
-+ can avoid it. --cgray
-+ */
-+ action.dev_id = handler;
-+ action.flags = 0;
-+ action.mask = 0;
-+ action.name = "Au1xxx TOY";
-+ action.handler = handler;
-+ action.next = NULL;
-+
-+ irq_desc[AU1000_TOY_MATCH2_INT].action = &action;
-+ irq_desc[AU1000_TOY_MATCH2_INT].status
-+ &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
-+
- local_enable_irq(AU1000_TOY_MATCH2_INT);
- }
- #endif
-@@ -492,7 +510,7 @@ void intc0_req0_irqdispatch(struct pt_re
- intc0_req0 |= au_readl(IC0_REQ0INT);
-
- if (!intc0_req0) return;
--
-+#ifdef AU1000_USB_DEV_REQ_INT
- /*
- * Because of the tight timing of SETUP token to reply
- * transactions, the USB devices-side packet complete
-@@ -503,7 +521,7 @@ void intc0_req0_irqdispatch(struct pt_re
- do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
- return;
- }
+-# Code maturity level options
+-#
+-CONFIG_EXPERIMENTAL=y
+-CONFIG_CLEAN_COMPILE=y
+-CONFIG_BROKEN_ON_SMP=y
+-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-+#endif
- irq = au_ffs(intc0_req0) - 1;
- intc0_req0 &= ~(1<<irq);
- do_IRQ(irq, regs);
-@@ -521,17 +539,7 @@ void intc0_req1_irqdispatch(struct pt_re
-
- irq = au_ffs(intc0_req1) - 1;
- intc0_req1 &= ~(1<<irq);
--#ifdef CONFIG_PM
-- if (irq == AU1000_TOY_MATCH2_INT) {
-- mask_and_ack_rise_edge_irq(irq);
-- counter0_irq(irq, NULL, regs);
-- local_enable_irq(irq);
-- }
-- else
--#endif
-- {
-- do_IRQ(irq, regs);
-- }
-+ do_IRQ(irq, regs);
- }
-
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/platform.c linux_HEAD/arch/mips/au1000/common/platform.c
---- linux-2.6.12/arch/mips/au1000/common/platform.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/platform.c 2005-04-14 16:40:12.000000000 +0200
-@@ -7,6 +7,7 @@
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-+#include <linux/config.h>
- #include <linux/device.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-@@ -41,8 +42,42 @@ static struct platform_device au1xxx_usb
- .resource = au1xxx_usb_ohci_resources,
- };
-
-+/*** AU1100 LCD controller ***/
-+
-+#ifdef CONFIG_FB_AU1100
-+static struct resource au1100_lcd_resources[] = {
-+ [0] = {
-+ .start = LCD_PHYS_ADDR,
-+ .end = LCD_PHYS_ADDR + 0x800 - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = AU1100_LCD_INT,
-+ .end = AU1100_LCD_INT,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static u64 au1100_lcd_dmamask = ~(u32)0;
-+
-+static struct platform_device au1100_lcd_device = {
-+ .name = "au1100-lcd",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &au1100_lcd_dmamask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(au1100_lcd_resources),
-+ .resource = au1100_lcd_resources,
-+};
-+#endif
-+
-+
- static struct platform_device *au1xxx_platform_devices[] __initdata = {
- &au1xxx_usb_ohci_device,
-+#ifdef CONFIG_FB_AU1100
-+ &au1100_lcd_device,
-+#endif
- };
-
- int au1xxx_platform_init(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/power.c linux_HEAD/arch/mips/au1000/common/power.c
---- linux-2.6.12/arch/mips/au1000/common/power.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/power.c 2005-04-08 22:40:40.000000000 +0200
-@@ -297,7 +297,6 @@ static int pm_do_suspend(ctl_table * ctl
- void *buffer, size_t * len)
- {
- int retval = 0;
-- void au1k_wait(void);
-
- if (!write) {
- *len = 0;
-@@ -306,7 +305,7 @@ static int pm_do_suspend(ctl_table * ctl
- if (retval)
- return retval;
- suspend_mode = 1;
-- au1k_wait();
-+
- retval = pm_send_all(PM_RESUME, (void *) 0);
- }
- return retval;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/setup.c linux_HEAD/arch/mips/au1000/common/setup.c
---- linux-2.6.12/arch/mips/au1000/common/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/setup.c 2005-07-01 12:09:16.000000000 +0200
-@@ -57,7 +57,7 @@ extern void au1xxx_time_init(void);
- extern void au1xxx_timer_setup(struct irqaction *irq);
- extern void set_cpuspec(void);
-
--static int __init au1x00_setup(void)
-+void __init plat_setup(void)
- {
- struct cpu_spec *sp;
- char *argptr;
-@@ -106,8 +106,6 @@ static int __init au1x00_setup(void)
- /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
- #ifdef CONFIG_MIPS_HYDROGEN3
- strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
--#else
-- strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
- #endif
- }
- #endif
-@@ -153,15 +151,11 @@ static int __init au1x00_setup(void)
- au_sync();
- while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
- au_writel(0, SYS_TOYTRIM);
+-#
+-# General setup
+-#
+-CONFIG_LOCALVERSION=""
+-CONFIG_LOCALVERSION_AUTO=y
+-CONFIG_SWAP=y
+-CONFIG_SWAP_PREFETCH=y
+-CONFIG_SYSVIPC=y
+-# CONFIG_POSIX_MQUEUE is not set
+-# CONFIG_BSD_PROCESS_ACCT is not set
+-CONFIG_SYSCTL=y
+-# CONFIG_AUDIT is not set
+-# CONFIG_HOTPLUG is not set
+-CONFIG_KOBJECT_UEVENT=y
+-# CONFIG_IKCONFIG is not set
+-CONFIG_INITRAMFS_SOURCE=""
+-CONFIG_EMBEDDED=y
+-CONFIG_KALLSYMS=y
+-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+-CONFIG_PRINTK=y
+-CONFIG_BUG=y
+-CONFIG_BASE_FULL=y
+-CONFIG_FUTEX=y
+-CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+-CONFIG_SHMEM=y
+-CONFIG_CC_ALIGN_FUNCTIONS=0
+-CONFIG_CC_ALIGN_LABELS=0
+-CONFIG_CC_ALIGN_LOOPS=0
+-CONFIG_CC_ALIGN_JUMPS=0
+-# CONFIG_TINY_SHMEM is not set
+-CONFIG_BASE_SMALL=0
-
-- return 0;
- }
-
--early_initcall(au1x00_setup);
+-#
+-# Loadable module support
+-#
+-CONFIG_MODULES=y
+-CONFIG_MODULE_UNLOAD=y
+-# CONFIG_MODULE_FORCE_UNLOAD is not set
+-CONFIG_OBSOLETE_MODPARM=y
+-CONFIG_MODVERSIONS=y
+-CONFIG_MODULE_SRCVERSION_ALL=y
+-CONFIG_KMOD=y
-
- #if defined(CONFIG_64BIT_PHYS_ADDR)
- /* This routine should be valid for all Au1x based boards */
--phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-+phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
- {
- u32 start, end;
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/common/time.c linux_HEAD/arch/mips/au1000/common/time.c
---- linux-2.6.12/arch/mips/au1000/common/time.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/common/time.c 2005-04-08 22:40:40.000000000 +0200
-@@ -50,7 +50,6 @@
- #include <linux/mc146818rtc.h>
- #include <linux/timex.h>
-
--extern void startup_match20_interrupt(void);
- extern void do_softirq(void);
- extern volatile unsigned long wall_jiffies;
- unsigned long missed_heart_beats = 0;
-@@ -58,14 +57,14 @@ unsigned long missed_heart_beats = 0;
- static unsigned long r4k_offset; /* Amount to increment compare reg each time */
- static unsigned long r4k_cur; /* What counter should be at next timer irq */
- int no_au1xxx_32khz;
--void (*au1k_wait_ptr)(void);
-+extern int allow_au1k_wait; /* default off for CP0 Counter */
-
- /* Cycle counter value at the previous timer interrupt.. */
- static unsigned int timerhi = 0, timerlo = 0;
-
- #ifdef CONFIG_PM
- #define MATCH20_INC 328
--extern void startup_match20_interrupt(void);
-+extern void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *));
- static unsigned long last_pc0, last_match20;
- #endif
-
-@@ -388,7 +387,6 @@ void au1xxx_timer_setup(struct irqaction
- {
- unsigned int est_freq;
- extern unsigned long (*do_gettimeoffset)(void);
-- extern void au1k_wait(void);
-
- printk("calculating r4koff... ");
- r4k_offset = cal_r4koff();
-@@ -446,13 +444,13 @@ void au1xxx_timer_setup(struct irqaction
- au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
- au_sync();
- while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
-- startup_match20_interrupt();
-+ startup_match20_interrupt(counter0_irq);
-
- do_gettimeoffset = do_fast_pm_gettimeoffset;
-
- /* We can use the real 'wait' instruction.
- */
-- au1k_wait_ptr = au1k_wait;
-+ allow_au1k_wait = 1;
- }
-
- #else
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/csb250/init.c linux_HEAD/arch/mips/au1000/csb250/init.c
---- linux-2.6.12/arch/mips/au1000/csb250/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/csb250/init.c 2005-04-14 16:40:13.000000000 +0200
-@@ -35,7 +35,6 @@
- #include <asm/bootinfo.h>
- #include <linux/string.h>
- #include <linux/kernel.h>
--#include <linux/sched.h>
-
- int prom_argc;
- char **prom_argv, **prom_envp;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/db1x00/irqmap.c linux_HEAD/arch/mips/au1000/db1x00/irqmap.c
---- linux-2.6.12/arch/mips/au1000/db1x00/irqmap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/db1x00/irqmap.c 2005-03-01 15:00:11.000000000 +0100
-@@ -48,6 +48,38 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
-
-+#ifdef CONFIG_MIPS_DB1500
-+char irq_tab_alchemy[][5] __initdata = {
-+ [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
-+ [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
-+};
-+#endif
-+
-+#ifdef CONFIG_MIPS_BOSPORUS
-+char irq_tab_alchemy[][5] __initdata = {
-+ [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
-+ [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
-+ [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
-+};
-+#endif
-+
-+#ifdef CONFIG_MIPS_MIRAGE
-+char irq_tab_alchemy[][5] __initdata = {
-+ [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
-+ [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
-+ [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
-+};
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1550
-+char irq_tab_alchemy[][5] __initdata = {
-+ [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
-+ [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
-+ [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
-+};
-+#endif
-+
-+
- au1xxx_irq_map_t au1xxx_irq_map[] = {
-
- #ifndef CONFIG_MIPS_MIRAGE
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/db1x00/mirage_ts.c linux_HEAD/arch/mips/au1000/db1x00/mirage_ts.c
---- linux-2.6.12/arch/mips/au1000/db1x00/mirage_ts.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/db1x00/mirage_ts.c 2005-02-28 16:56:39.000000000 +0100
-@@ -102,15 +102,15 @@ static struct {
- } mirage_ts_cal =
- {
- #if 0
-- xscale: 84,
-- xtrans: -157,
-- yscale: 66,
-- ytrans: -150,
-+ .xscale = 84,
-+ .xtrans = -157,
-+ .yscale = 66,
-+ .ytrans = -150,
- #else
-- xscale: 84,
-- xtrans: -150,
-- yscale: 66,
-- ytrans: -146,
-+ .xscale = 84,
-+ .xtrans = -150,
-+ .yscale = 66,
-+ .ytrans = -146,
- #endif
- };
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/hydrogen3/init.c linux_HEAD/arch/mips/au1000/hydrogen3/init.c
---- linux-2.6.12/arch/mips/au1000/hydrogen3/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/hydrogen3/init.c 2005-04-14 16:40:13.000000000 +0200
-@@ -37,7 +37,6 @@
- #include <linux/config.h>
- #include <linux/string.h>
- #include <linux/kernel.h>
--#include <linux/sched.h>
-
- int prom_argc;
- char **prom_argv, **prom_envp;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/mtx-1/init.c linux_HEAD/arch/mips/au1000/mtx-1/init.c
---- linux-2.6.12/arch/mips/au1000/mtx-1/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/mtx-1/init.c 2005-07-10 12:28:27.000000000 +0200
-@@ -33,7 +33,6 @@
- #include <linux/sched.h>
- #include <linux/init.h>
- #include <linux/mm.h>
--#include <linux/sched.h>
- #include <linux/bootmem.h>
- #include <asm/addrspace.h>
- #include <asm/bootinfo.h>
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/mtx-1/irqmap.c linux_HEAD/arch/mips/au1000/mtx-1/irqmap.c
---- linux-2.6.12/arch/mips/au1000/mtx-1/irqmap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/mtx-1/irqmap.c 2005-03-01 15:00:11.000000000 +0100
-@@ -47,6 +47,17 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
-
-+char irq_tab_alchemy[][5] __initdata = {
-+ [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
-+ [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
-+ [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
-+ [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
-+ [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
-+ [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
-+ [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
-+ [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
-+};
-+
- au1xxx_irq_map_t au1xxx_irq_map[] = {
- { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
- { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1200/Makefile linux_HEAD/arch/mips/au1000/pb1200/Makefile
---- linux-2.6.12/arch/mips/au1000/pb1200/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/au1000/pb1200/Makefile 2005-03-01 07:33:16.000000000 +0100
-@@ -0,0 +1,5 @@
-+#
-+# Makefile for the Alchemy Semiconductor PB1200 board.
-+#
-+
-+lib-y := init.o board_setup.o irqmap.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1200/board_setup.c linux_HEAD/arch/mips/au1000/pb1200/board_setup.c
---- linux-2.6.12/arch/mips/au1000/pb1200/board_setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/au1000/pb1200/board_setup.c 2005-03-04 20:36:08.000000000 +0100
-@@ -0,0 +1,183 @@
-+/*
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Alchemy Pb1200/Db1200 board setup.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/ioport.h>
-+#include <linux/mm.h>
-+#include <linux/console.h>
-+#include <linux/mc146818rtc.h>
-+#include <linux/delay.h>
-+
-+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
-+#include <linux/ide.h>
-+#endif
-+
-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
-+#include <asm/irq.h>
-+#include <asm/mipsregs.h>
-+#include <asm/reboot.h>
-+#include <asm/pgtable.h>
-+#include <asm/mach-au1x00/au1000.h>
-+#include <asm/mach-au1x00/au1xxx_dbdma.h>
-+
-+#ifdef CONFIG_MIPS_PB1200
-+#include <asm/mach-pb1x00/pb1200.h>
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1200
-+#include <asm/mach-db1x00/db1200.h>
-+#define PB1200_ETH_INT DB1200_ETH_INT
-+#define PB1200_IDE_INT DB1200_IDE_INT
-+#endif
-+
-+extern void _board_init_irq(void);
-+extern void (*board_init_irq)(void);
-+
-+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
-+extern u32 au1xxx_ide_virtbase;
-+extern u64 au1xxx_ide_physbase;
-+extern int au1xxx_ide_irq;
-+
-+u32 led_base_addr;
-+/* Ddma */
-+chan_tab_t *ide_read_ch, *ide_write_ch;
-+u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
-+
-+dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
-+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
-+
-+void board_reset (void)
-+{
-+ bcsr->resets = 0;
-+}
-+
-+void __init board_setup(void)
-+{
-+ char *argptr = NULL;
-+ u32 pin_func;
-+
-+#if 0
-+ /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
-+ * but it is board specific code, so put it here.
-+ */
-+ pin_func = au_readl(SYS_PINFUNC);
-+ au_sync();
-+ pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
-+ au_writel(pin_func, SYS_PINFUNC);
-+
-+ au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
-+ au_sync();
-+#endif
-+
-+#if defined( CONFIG_I2C_ALGO_AU1550 )
-+ {
-+ u32 freq0, clksrc;
-+
-+ /* Select SMBUS in CPLD */
-+ bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
-+
-+ pin_func = au_readl(SYS_PINFUNC);
-+ au_sync();
-+ pin_func &= ~(3<<17 | 1<<4);
-+ /* Set GPIOs correctly */
-+ pin_func |= 2<<17;
-+ au_writel(pin_func, SYS_PINFUNC);
-+ au_sync();
-+
-+ /* The i2c driver depends on 50Mhz clock */
-+ freq0 = au_readl(SYS_FREQCTRL0);
-+ au_sync();
-+ freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
-+ freq0 |= (3<<SYS_FC_FRDIV1_BIT);
-+ /* 396Mhz / (3+1)*2 == 49.5Mhz */
-+ au_writel(freq0, SYS_FREQCTRL0);
-+ au_sync();
-+ freq0 |= SYS_FC_FE1;
-+ au_writel(freq0, SYS_FREQCTRL0);
-+ au_sync();
-+
-+ clksrc = au_readl(SYS_CLKSRC);
-+ au_sync();
-+ clksrc &= ~0x01f00000;
-+ /* bit 22 is EXTCLK0 for PSC0 */
-+ clksrc |= (0x3 << 22);
-+ au_writel(clksrc, SYS_CLKSRC);
-+ au_sync();
-+ }
-+#endif
-+
-+#ifdef CONFIG_FB_AU1200
-+ argptr = prom_getcmdline();
-+#ifdef CONFIG_MIPS_PB1200
-+ strcat(argptr, " video=au1200fb:panel:s11");
-+#endif
-+#ifdef CONFIG_MIPS_DB1200
-+ strcat(argptr, " video=au1200fb:panel:s7");
-+#endif
-+#endif
-+
-+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
-+ /*
-+ * Iniz IDE parameters
-+ */
-+ au1xxx_ide_irq = PB1200_IDE_INT;
-+ au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
-+ au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
-+ /*
-+ * change PIO or PIO+Ddma
-+ * check the GPIO-5 pin condition. pb1200:s18_dot */
-+ switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0;
-+#endif
-+
-+ /* The Pb1200 development board uses external MUX for PSC0 to
-+ support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
-+ */
-+#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
-+ #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
-+ Refer to Pb1200/Db1200 documentation.
-+#elif defined( CONFIG_AU1550_PSC_SPI )
-+ bcsr->resets |= BCSR_RESETS_PCS0MUX;
-+#elif defined( CONFIG_I2C_ALGO_AU1550 )
-+ bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
-+#endif
-+ au_sync();
-+
-+#ifdef CONFIG_MIPS_PB1200
-+ printk("AMD Alchemy Pb1200 Board\n");
-+#endif
-+#ifdef CONFIG_MIPS_DB1200
-+ printk("AMD Alchemy Db1200 Board\n");
-+#endif
-+
-+ /* Setup Pb1200 External Interrupt Controller */
-+ {
-+ extern void (*board_init_irq)(void);
-+ extern void _board_init_irq(void);
-+ board_init_irq = _board_init_irq;
-+ }
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1200/init.c linux_HEAD/arch/mips/au1000/pb1200/init.c
---- linux-2.6.12/arch/mips/au1000/pb1200/init.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/au1000/pb1200/init.c 2005-03-01 07:33:16.000000000 +0100
-@@ -0,0 +1,69 @@
-+/*
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PB1200 board setup
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * ppopov at mvista.com or source at mvista.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/sched.h>
-+#include <linux/bootmem.h>
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
-+
-+int prom_argc;
-+char **prom_argv, **prom_envp;
-+extern void __init prom_init_cmdline(void);
-+extern char *prom_getenv(char *envname);
-+
-+const char *get_system_type(void)
-+{
-+ return "Alchemy Pb1200";
-+}
-+
-+void __init prom_init(void)
-+{
-+ unsigned char *memsize_str;
-+ unsigned long memsize;
-+
-+ prom_argc = (int) fw_arg0;
-+ prom_argv = (char **) fw_arg1;
-+ prom_envp = (char **) fw_arg2;
-+
-+ mips_machgroup = MACH_GROUP_ALCHEMY;
-+ mips_machtype = MACH_PB1200;
-+
-+ prom_init_cmdline();
-+ memsize_str = prom_getenv("memsize");
-+ if (!memsize_str) {
-+ memsize = 0x08000000;
-+ } else {
-+ memsize = simple_strtol(memsize_str, NULL, 0);
-+ }
-+ add_memory_region(0, memsize, BOOT_MEM_RAM);
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1200/irqmap.c linux_HEAD/arch/mips/au1000/pb1200/irqmap.c
---- linux-2.6.12/arch/mips/au1000/pb1200/irqmap.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/au1000/pb1200/irqmap.c 2005-04-14 16:40:13.000000000 +0200
-@@ -0,0 +1,181 @@
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ * Au1xxx irq map table
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+#include <linux/config.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/module.h>
-+#include <linux/signal.h>
-+#include <linux/sched.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/timex.h>
-+#include <linux/slab.h>
-+#include <linux/random.h>
-+#include <linux/delay.h>
-+
-+#include <asm/bitops.h>
-+#include <asm/bootinfo.h>
-+#include <asm/io.h>
-+#include <asm/mipsregs.h>
-+#include <asm/system.h>
-+#include <asm/mach-au1x00/au1000.h>
-+
-+#ifdef CONFIG_MIPS_PB1200
-+#include <asm/mach-pb1x00/pb1200.h>
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1200
-+#include <asm/mach-db1x00/db1200.h>
-+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
-+#define PB1200_INT_END DB1200_INT_END
-+#endif
-+
-+au1xxx_irq_map_t au1xxx_irq_map[] = {
-+ { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
-+};
-+
-+int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+
-+/*
-+ * Support for External interrupts on the PbAu1200 Development platform.
-+ */
-+static volatile int pb1200_cascade_en=0;
-+
-+void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
-+{
-+ unsigned short bisr = bcsr->int_status;
-+ int extirq_nr = 0;
-+
-+ /* Clear all the edge interrupts. This has no effect on level */
-+ bcsr->int_status = bisr;
-+ for( ; bisr; bisr &= (bisr-1) )
-+ {
-+ extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
-+ /* Ack and dispatch IRQ */
-+ do_IRQ(extirq_nr,regs);
-+ }
-+}
-+
-+inline void pb1200_enable_irq(unsigned int irq_nr)
-+{
-+ bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
-+ bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
-+}
-+
-+inline void pb1200_disable_irq(unsigned int irq_nr)
-+{
-+ bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
-+ bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
-+}
-+
-+static unsigned int pb1200_startup_irq( unsigned int irq_nr )
-+{
-+ if (++pb1200_cascade_en == 1)
-+ {
-+ request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
-+ 0, "Pb1200 Cascade", &pb1200_cascade_handler );
-+#ifdef CONFIG_MIPS_PB1200
-+ /* We have a problem with CPLD rev3. Enable a workaround */
-+ if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
-+ {
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
-+ printk("updated to latest revision. This software will not\n");
-+ printk("work on anything less than CPLD rev4\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ printk("\nWARNING!!!\n");
-+ while(1);
-+ }
-+#endif
-+ }
-+ pb1200_enable_irq(irq_nr);
-+ return 0;
-+}
-+
-+static void pb1200_shutdown_irq( unsigned int irq_nr )
-+{
-+ pb1200_disable_irq(irq_nr);
-+ if (--pb1200_cascade_en == 0)
-+ {
-+ free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
-+ }
-+ return;
-+}
-+
-+static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
-+{
-+ pb1200_disable_irq( irq_nr );
-+}
-+
-+static void pb1200_end_irq(unsigned int irq_nr)
-+{
-+ if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
-+ pb1200_enable_irq(irq_nr);
-+ }
-+}
-+
-+static struct hw_interrupt_type external_irq_type =
-+{
-+#ifdef CONFIG_MIPS_PB1200
-+ "Pb1200 Ext",
-+#endif
-+#ifdef CONFIG_MIPS_DB1200
-+ "Db1200 Ext",
-+#endif
-+ pb1200_startup_irq,
-+ pb1200_shutdown_irq,
-+ pb1200_enable_irq,
-+ pb1200_disable_irq,
-+ pb1200_mask_and_ack_irq,
-+ pb1200_end_irq,
-+ NULL
-+};
-+
-+void _board_init_irq(void)
-+{
-+ int irq_nr;
-+
-+ for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
-+ {
-+ irq_desc[irq_nr].handler = &external_irq_type;
-+ pb1200_disable_irq(irq_nr);
-+ }
-+
-+ /* GPIO_7 can not be hooked here, so it is hooked upon first
-+ request of any source attached to the cascade */
-+}
-+
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1500/irqmap.c linux_HEAD/arch/mips/au1000/pb1500/irqmap.c
---- linux-2.6.12/arch/mips/au1000/pb1500/irqmap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/pb1500/irqmap.c 2005-03-01 15:00:11.000000000 +0100
-@@ -47,6 +47,11 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
-
-+char irq_tab_alchemy[][5] __initdata = {
-+ [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
-+ [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
-+};
-+
- au1xxx_irq_map_t au1xxx_irq_map[] = {
- { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
- { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
-diff -urpNX dontdiff linux-2.6.12/arch/mips/au1000/pb1550/irqmap.c linux_HEAD/arch/mips/au1000/pb1550/irqmap.c
---- linux-2.6.12/arch/mips/au1000/pb1550/irqmap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/au1000/pb1550/irqmap.c 2005-03-01 15:00:12.000000000 +0100
-@@ -47,6 +47,11 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
-
-+char irq_tab_alchemy[][5] __initdata = {
-+ [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
-+ [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
-+};
-+
- au1xxx_irq_map_t au1xxx_irq_map[] = {
- { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
- { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/Makefile linux_HEAD/arch/mips/cobalt/Makefile
---- linux-2.6.12/arch/mips/cobalt/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/Makefile 2005-04-12 15:07:55.000000000 +0200
-@@ -2,6 +2,6 @@
- # Makefile for the Cobalt micro systems family specific parts of the kernel
- #
-
--obj-y := irq.o int-handler.o reset.o setup.o promcon.o
-+obj-y := irq.o int-handler.o reset.o setup.o
-
- EXTRA_AFLAGS := $(CFLAGS)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/int-handler.S linux_HEAD/arch/mips/cobalt/int-handler.S
---- linux-2.6.12/arch/mips/cobalt/int-handler.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/int-handler.S 2005-02-21 22:17:43.000000000 +0100
-@@ -18,8 +18,8 @@
- SAVE_ALL
- CLI
-
-- la ra, ret_from_irq
-- move a1, sp
-+ PTR_LA ra, ret_from_irq
-+ move a0, sp
- j cobalt_irq
-
- END(cobalt_handle_int)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/irq.c linux_HEAD/arch/mips/cobalt/irq.c
---- linux-2.6.12/arch/mips/cobalt/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/irq.c 2005-04-12 15:07:55.000000000 +0200
-@@ -10,6 +10,8 @@
- #include <linux/kernel.h>
- #include <linux/init.h>
- #include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/pci.h>
-
- #include <asm/i8259.h>
- #include <asm/irq_cpu.h>
-@@ -25,8 +27,8 @@ extern void cobalt_handle_int(void);
- * the CPU interrupt lines, and ones that come in on the via chip. The CPU
- * mappings are:
- *
-- * 16, - Software interrupt 0 (unused) IE_SW0
-- * 17 - Software interrupt 1 (unused) IE_SW0
-+ * 16 - Software interrupt 0 (unused) IE_SW0
-+ * 17 - Software interrupt 1 (unused) IE_SW1
- * 18 - Galileo chip (timer) IE_IRQ0
- * 19 - Tulip 0 + NCR SCSI IE_IRQ1
- * 20 - Tulip 1 IE_IRQ2
-@@ -42,61 +44,94 @@ extern void cobalt_handle_int(void);
- * 15 - IDE1
- */
-
--asmlinkage void cobalt_irq(struct pt_regs *regs)
-+static inline void galileo_irq(struct pt_regs *regs)
- {
-- unsigned int pending = read_c0_status() & read_c0_cause();
-+ unsigned int mask, pending, devfn;
-
-- if (pending & CAUSEF_IP2) { /* int 18 */
-- unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
-+ mask = GALILEO_INL(GT_INTRMASK_OFS);
-+ pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
-
-- /* Check for timer irq ... */
-- if (irq_src & GALILEO_T0EXP) {
-- /* Clear the int line */
-- GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
-- do_IRQ(COBALT_TIMER_IRQ, regs);
-- }
-- return;
-- }
-+ if (pending & GALILEO_INTR_T0EXP) {
-
-- if (pending & CAUSEF_IP6) { /* int 22 */
-- int irq = i8259_irq();
-+ GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
-+ do_IRQ(COBALT_GALILEO_IRQ, regs);
-
-- if (irq >= 0)
-- do_IRQ(irq, regs);
-- return;
-- }
-+ } else if (pending & GALILEO_INTR_RETRY_CTR) {
-
-- if (pending & CAUSEF_IP3) { /* int 19 */
-- do_IRQ(COBALT_ETH0_IRQ, regs);
-- return;
-- }
-+ devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
-+ GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
-+ printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
-+ PCI_SLOT(devfn), PCI_FUNC(devfn));
-
-- if (pending & CAUSEF_IP4) { /* int 20 */
-- do_IRQ(COBALT_ETH1_IRQ, regs);
-- return;
-- }
-+ } else {
-
-- if (pending & CAUSEF_IP5) { /* int 21 */
-- do_IRQ(COBALT_SERIAL_IRQ, regs);
-- return;
-+ GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
-+ printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
- }
-+}
-
-- if (pending & CAUSEF_IP7) { /* int 23 */
-- do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
-- return;
-- }
-+static inline void via_pic_irq(struct pt_regs *regs)
-+{
-+ int irq;
-+
-+ irq = i8259_irq();
-+ if (irq >= 0)
-+ do_IRQ(irq, regs);
-+}
-+
-+asmlinkage void cobalt_irq(struct pt_regs *regs)
-+{
-+ unsigned pending;
-+
-+ pending = read_c0_status() & read_c0_cause();
-+
-+ if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
-+
-+ galileo_irq(regs);
-+
-+ else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
-+
-+ via_pic_irq(regs);
-+
-+ else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
-+
-+ do_IRQ(COBALT_CPU_IRQ + 3, regs);
-+
-+ else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
-+
-+ do_IRQ(COBALT_CPU_IRQ + 4, regs);
-+
-+ else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
-+
-+ do_IRQ(COBALT_CPU_IRQ + 5, regs);
-+
-+ else if (pending & CAUSEF_IP7) /* IRQ 23 */
-+
-+ do_IRQ(COBALT_CPU_IRQ + 7, regs);
- }
-
-+static struct irqaction irq_via = {
-+ no_action, 0, { { 0, } }, "cascade", NULL, NULL
-+};
-+
- void __init arch_init_irq(void)
- {
-+ /*
-+ * Mask all Galileo interrupts. The Galileo
-+ * handler is set in cobalt_timer_setup()
-+ */
-+ GALILEO_OUTL(0, GT_INTRMASK_OFS);
-+
- set_except_vector(0, cobalt_handle_int);
-
- init_i8259_irqs(); /* 0 ... 15 */
-- mips_cpu_irq_init(16); /* 16 ... 23 */
-+ mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
-
- /*
- * Mask all cpu interrupts
- * (except IE4, we already masked those at VIA level)
- */
- change_c0_status(ST0_IM, IE_IRQ4);
-+
-+ setup_irq(COBALT_VIA_IRQ, &irq_via);
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/promcon.c linux_HEAD/arch/mips/cobalt/promcon.c
---- linux-2.6.12/arch/mips/cobalt/promcon.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/promcon.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,87 +0,0 @@
--/*
-- * PROM console for Cobalt Raq2
-- *
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License. See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
-- * Copyright (C) 2001 by Liam Davies (ldavies at agile.tv)
-- *
-- */
--
--#include <linux/init.h>
--#include <linux/console.h>
--#include <linux/kdev_t.h>
--#include <linux/serial_reg.h>
--
--#include <asm/delay.h>
--#include <asm/serial.h>
--#include <asm/io.h>
--
--static unsigned long port = 0xc800000;
--
--static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
--{
-- char lsr;
--
-- do {
-- lsr = inb(ioaddr + UART_LSR);
-- } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
-- outb(ch, ioaddr + UART_TX);
--}
--
--static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
--{
-- while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
-- udelay(1);
-- return inb(ioaddr + UART_RX);
--}
--
--void ns16550_console_write(struct console *co, const char *s, unsigned count)
--{
-- char lsr, ier;
-- unsigned i;
--
-- ier = inb(port + UART_IER);
-- outb(0x00, port + UART_IER);
-- for (i=0; i < count; i++, s++) {
--
-- if(*s == '\n')
-- ns16550_cons_put_char('\r', port);
-- ns16550_cons_put_char(*s, port);
-- }
--
-- do {
-- lsr = inb(port + UART_LSR);
-- } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
--
-- outb(ier, port + UART_IER);
--}
--
--char getDebugChar(void)
--{
-- return ns16550_cons_get_char(port);
--}
--
--void putDebugChar(char kgdb_char)
--{
-- ns16550_cons_put_char(kgdb_char, port);
--}
--
--static struct console ns16550_console = {
-- .name = "prom",
-- .setup = NULL,
-- .write = ns16550_console_write,
-- .flags = CON_PRINTBUFFER,
-- .index = -1,
--};
--
--static int __init ns16550_setup_console(void)
--{
-- register_console(&ns16550_console);
--
-- return 0;
--}
--
--console_initcall(ns16550_setup_console);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/reset.c linux_HEAD/arch/mips/cobalt/reset.c
---- linux-2.6.12/arch/mips/cobalt/reset.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/reset.c 2005-02-21 22:17:43.000000000 +0100
-@@ -16,48 +16,45 @@
- #include <asm/reboot.h>
- #include <asm/system.h>
- #include <asm/mipsregs.h>
-+#include <asm/cobalt/cobalt.h>
-
--void cobalt_machine_restart(char *command)
-+void cobalt_machine_halt(void)
- {
-- *(volatile char *)0xbc000000 = 0x0f;
-+ int state, last, diff;
-+ unsigned long mark;
-
- /*
-- * Ouch, we're still alive ... This time we take the silver bullet ...
-- * ... and find that we leave the hardware in a state in which the
-- * kernel in the flush locks up somewhen during of after the PCI
-- * detection stuff.
-+ * turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
-+ *
-+ * restart if ENTER and SELECT are pressed
- */
-- set_c0_status(ST0_BEV | ST0_ERL);
-- change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-- flush_cache_all();
-- write_c0_wired(0);
-- __asm__ __volatile__(
-- "jr\t%0"
-- :
-- : "r" (0xbfc00000));
--}
-
--extern int led_state;
--#define kLED 0xBC000000
--#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x)
-+ last = COBALT_KEY_PORT;
-
--void cobalt_machine_halt(void)
--{
-- int mark;
-+ for (state = 0;;) {
-+
-+ state ^= COBALT_LED_POWER_OFF;
-+ COBALT_LED_PORT = state;
-+
-+ diff = COBALT_KEY_PORT ^ last;
-+ last ^= diff;
-
-- /* Blink our cute? little LED (number 3)... */
-- while (1) {
-- led_state = led_state | ( 1 << 3 );
-- LEDSet(led_state);
-- mark = jiffies;
-- while (jiffies<(mark+HZ));
-- led_state = led_state & ~( 1 << 3 );
-- LEDSet(led_state);
-- mark = jiffies;
-- while (jiffies<(mark+HZ));
-+ if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
-+ COBALT_LED_PORT = COBALT_LED_RESET;
-+
-+ for (mark = jiffies; jiffies - mark < HZ;)
-+ ;
- }
- }
-
-+void cobalt_machine_restart(char *command)
-+{
-+ COBALT_LED_PORT = COBALT_LED_RESET;
-+
-+ /* we should never get here */
-+ cobalt_machine_halt();
-+}
-+
- /*
- * This triggers the luser mode device driver for the power switch ;-)
- */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/cobalt/setup.c linux_HEAD/arch/mips/cobalt/setup.c
---- linux-2.6.12/arch/mips/cobalt/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/cobalt/setup.c 2005-07-07 13:02:52.000000000 +0200
-@@ -13,6 +13,8 @@
- #include <linux/interrupt.h>
- #include <linux/pci.h>
- #include <linux/init.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-
- #include <asm/bootinfo.h>
- #include <asm/time.h>
-@@ -21,6 +23,7 @@
- #include <asm/processor.h>
- #include <asm/reboot.h>
- #include <asm/gt64120.h>
-+#include <asm/serial.h>
-
- #include <asm/cobalt/cobalt.h>
-
-@@ -30,45 +33,44 @@ extern void cobalt_machine_power_off(voi
-
- int cobalt_board_id;
-
--static char my_cmdline[CL_SIZE] = {
-- "console=ttyS0,115200 "
--#ifdef CONFIG_IP_PNP
-- "ip=on "
--#endif
--#ifdef CONFIG_ROOT_NFS
-- "root=/dev/nfs "
--#else
-- "root=/dev/hda1 "
--#endif
-- };
--
- const char *get_system_type(void)
- {
-+ switch (cobalt_board_id) {
-+ case COBALT_BRD_ID_QUBE1:
-+ return "Cobalt Qube";
-+ case COBALT_BRD_ID_RAQ1:
-+ return "Cobalt RaQ";
-+ case COBALT_BRD_ID_QUBE2:
-+ return "Cobalt Qube2";
-+ case COBALT_BRD_ID_RAQ2:
-+ return "Cobalt RaQ2";
-+ }
- return "MIPS Cobalt";
- }
-
- static void __init cobalt_timer_setup(struct irqaction *irq)
- {
-- /* Load timer value for 150 Hz */
-- GALILEO_OUTL(500000, GT_TC0_OFS);
-+ /* Load timer value for 1KHz (TCLK is 50MHz) */
-+ GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
-+
-+ /* Enable timer */
-+ GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
-
-- /* Register our timer interrupt */
-- setup_irq(COBALT_TIMER_IRQ, irq);
-+ /* Register interrupt */
-+ setup_irq(COBALT_GALILEO_IRQ, irq);
-
-- /* Enable timer ints */
-- GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS);
-- /* Unmask timer int */
-- GALILEO_OUTL(0x100, GT_INTRMASK_OFS);
-+ /* Enable interrupt */
-+ GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
- }
-
- extern struct pci_ops gt64111_pci_ops;
-
- static struct resource cobalt_mem_resource = {
-- "GT64111 PCI MEM", GT64111_IO_BASE, 0xffffffffUL, IORESOURCE_MEM
-+ "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
- };
-
- static struct resource cobalt_io_resource = {
-- "GT64111 IO MEM", 0x00001000UL, 0x0fffffffUL, IORESOURCE_IO
-+ "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
- };
-
- static struct resource cobalt_io_resources[] = {
-@@ -86,11 +88,12 @@ static struct pci_controller cobalt_pci_
- .mem_resource = &cobalt_mem_resource,
- .mem_offset = 0,
- .io_resource = &cobalt_io_resource,
-- .io_offset = 0x00001000UL - GT64111_IO_BASE
-+ .io_offset = 0 - GT64111_IO_BASE
- };
-
--static void __init cobalt_setup(void)
-+void __init plat_setup(void)
- {
-+ static struct uart_port uart;
- unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
- int i;
-
-@@ -100,7 +103,10 @@ static void __init cobalt_setup(void)
-
- board_timer_setup = cobalt_timer_setup;
-
-- set_io_port_base(KSEG1ADDR(GT64111_IO_BASE));
-+ set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
-+
-+ /* I/O port resource must include UART and LCD/buttons */
-+ ioport_resource.end = 0x0fffffff;
-
- /*
- * This is a prom style console. We just poke at the
-@@ -120,27 +126,61 @@ static void __init cobalt_setup(void)
- cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
- cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
-
-+ printk("Cobalt board ID: %d\n", cobalt_board_id);
-+
- #ifdef CONFIG_PCI
- register_pci_controller(&cobalt_pci_controller);
- #endif
--}
-
--early_initcall(cobalt_setup);
-+#ifdef CONFIG_SERIAL_8250
-+ if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
-+
-+ uart.line = 0;
-+ uart.type = PORT_UNKNOWN;
-+ uart.uartclk = 18432000;
-+ uart.irq = COBALT_SERIAL_IRQ;
-+ uart.flags = STD_COM_FLAGS;
-+ uart.iobase = 0xc800000;
-+ uart.iotype = UPIO_PORT;
-+
-+ early_serial_setup(&uart);
-+ }
-+#endif
-+}
-
- /*
- * Prom init. We read our one and only communication with the firmware.
-- * Grab the amount of installed memory
-+ * Grab the amount of installed memory.
-+ * Better boot loaders (CoLo) pass a command line too :-)
- */
-
- void __init prom_init(void)
- {
-- int argc = fw_arg0;
--
-- strcpy(arcs_cmdline, my_cmdline);
-+ int narg, indx, posn, nchr;
-+ unsigned long memsz;
-+ char **argv;
-
- mips_machgroup = MACH_GROUP_COBALT;
-
-- add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
-+ memsz = fw_arg0 & 0x7fff0000;
-+ narg = fw_arg0 & 0x0000ffff;
-+
-+ if (narg) {
-+ arcs_cmdline[0] = '\0';
-+ argv = (char **) fw_arg1;
-+ posn = 0;
-+ for (indx = 1; indx < narg; ++indx) {
-+ nchr = strlen(argv[indx]);
-+ if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
-+ break;
-+ if (posn)
-+ arcs_cmdline[posn++] = ' ';
-+ strcpy(arcs_cmdline + posn, argv[indx]);
-+ posn += nchr;
-+ }
-+ }
-+
-+ add_memory_region(0x0, memsz, BOOT_MEM_RAM);
- }
-
- unsigned long __init prom_free_prom_memory(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/atlas_defconfig linux_HEAD/arch/mips/configs/atlas_defconfig
---- linux-2.6.12/arch/mips/configs/atlas_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/atlas_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:00 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:01 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,33 +57,54 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- CONFIG_MIPS_ATLAS=y
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-@@ -90,7 +112,10 @@ CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_MIPS_BONITO64=y
- CONFIG_MIPS_MSC=y
--# CONFIG_CPU_LITTLE_ENDIAN is not set
-+# CONFIG_CPU_BIG_ENDIAN is not set
-+CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_MIPS_BOARDS_GEN=y
- CONFIG_MIPS_GT64120=y
- CONFIG_SWAP_IO_SPACE=y
-@@ -100,8 +125,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -117,10 +142,22 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
- # CONFIG_PAGE_SIZE_64KB is not set
-+CONFIG_BOARD_SCACHE=y
-+CONFIG_RM7000_CPU_SCACHE=y
- CONFIG_CPU_HAS_PREFETCH=y
- # CONFIG_64BIT_PHYS_ADDR is not set
- # CONFIG_CPU_ADVANCED is not set
-@@ -143,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -287,12 +320,8 @@ CONFIG_SCSI_ISCSI_ATTRS=m
- # CONFIG_MEGARAID_NEWGEN is not set
- # CONFIG_MEGARAID_LEGACY is not set
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_IPS is not set
- # CONFIG_SCSI_INITIO is not set
- # CONFIG_SCSI_INIA100 is not set
-@@ -302,7 +331,6 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
- CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
- # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
- # CONFIG_SCSI_IPR is not set
--# CONFIG_SCSI_QLOGIC_ISP is not set
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=y
-@@ -311,6 +339,7 @@ CONFIG_SCSI_QLA2XXX=y
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_NSP32 is not set
-@@ -334,6 +363,8 @@ CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_ZERO=m
-+CONFIG_DM_MULTIPATH=m
-+CONFIG_DM_MULTIPATH_EMC=m
-
- #
- # Fusion MPT device support
-@@ -360,7 +391,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -369,6 +399,7 @@ CONFIG_IP_ADVANCED_ROUTER=y
- CONFIG_IP_MULTIPLE_TABLES=y
- CONFIG_IP_ROUTE_FWMARK=y
- CONFIG_IP_ROUTE_MULTIPATH=y
-+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
- CONFIG_IP_ROUTE_VERBOSE=y
- CONFIG_IP_PNP=y
- CONFIG_IP_PNP_DHCP=y
-@@ -502,7 +533,7 @@ CONFIG_IP_NF_ARPFILTER=m
- CONFIG_IP_NF_ARP_MANGLE=m
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- CONFIG_IP6_NF_QUEUE=m
- CONFIG_IP6_NF_IPTABLES=m
-@@ -601,6 +632,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -611,6 +643,7 @@ CONFIG_NET_CLS_IND=y
- # CONFIG_CLS_U32_MARK is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -628,7 +661,6 @@ CONFIG_DUMMY=m
- CONFIG_BONDING=m
- CONFIG_EQUALIZER=m
- CONFIG_TUN=m
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -683,6 +715,7 @@ CONFIG_LAN_SAA9730=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -740,19 +773,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--CONFIG_SERIO_LIBPS2=y
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -765,6 +785,17 @@ CONFIG_MOUSE_SERIAL=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+CONFIG_SERIO_LIBPS2=y
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -785,6 +816,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -811,6 +843,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -844,7 +881,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -854,13 +890,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -901,7 +933,12 @@ CONFIG_JFS_SECURITY=y
- # CONFIG_JFS_DEBUG is not set
- # CONFIG_JFS_STATISTICS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- CONFIG_XFS_SECURITY=y
-@@ -1050,7 +1087,9 @@ CONFIG_NLS_UTF8=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -1072,6 +1111,7 @@ CONFIG_CRYPTO_SHA1=m
- CONFIG_CRYPTO_SHA256=m
- CONFIG_CRYPTO_SHA512=m
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=m
- CONFIG_CRYPTO_BLOWFISH=m
- CONFIG_CRYPTO_TWOFISH=m
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/capcella_defconfig linux_HEAD/arch/mips/configs/capcella_defconfig
---- linux-2.6.12/arch/mips/configs/capcella_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/capcella_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:00 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:01 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,56 +57,80 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--# CONFIG_CASIO_E55 is not set
--# CONFIG_IBM_WORKPAD is not set
--# CONFIG_TANBAC_TB0226 is not set
--# CONFIG_TANBAC_TB0229 is not set
--# CONFIG_VICTOR_MPC30X is not set
--CONFIG_ZAO_CAPCELLA=y
--CONFIG_PCI_VR41XX=y
--CONFIG_VRC4173=y
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+# CONFIG_CASIO_E55 is not set
-+# CONFIG_IBM_WORKPAD is not set
-+# CONFIG_TANBAC_TB0226 is not set
-+# CONFIG_TANBAC_TB0229 is not set
-+# CONFIG_VICTOR_MPC30X is not set
-+CONFIG_ZAO_CAPCELLA=y
-+CONFIG_PCI_VR41XX=y
-+# CONFIG_GPIO_VR41XX is not set
-+CONFIG_VRC4173=y
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -121,6 +146,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -144,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -274,7 +306,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -337,7 +368,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -372,6 +402,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -428,19 +459,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--CONFIG_SERIO_LIBPS2=m
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -450,6 +468,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+CONFIG_SERIO_LIBPS2=m
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -470,6 +499,8 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -508,6 +539,11 @@ CONFIG_WATCHDOG=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -541,7 +577,6 @@ CONFIG_WATCHDOG=y
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -551,13 +586,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -583,6 +614,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -675,7 +710,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/cobalt_defconfig linux_HEAD/arch/mips/configs/cobalt_defconfig
---- linux-2.6.12/arch/mips/configs/cobalt_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/cobalt_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:00 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:02 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,40 +51,63 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- CONFIG_MIPS_COBALT=y
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_I8259=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_GT64111=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -91,8 +115,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -108,6 +132,17 @@ CONFIG_CPU_NEVADA=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -133,10 +168,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -264,7 +295,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -323,7 +353,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -358,6 +387,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -414,19 +444,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -436,6 +453,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -456,6 +484,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -482,6 +511,11 @@ CONFIG_COBALT_LCD=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -515,7 +549,6 @@ CONFIG_COBALT_LCD=y
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -525,13 +558,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -561,6 +590,10 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -621,7 +654,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFS_DIRECTIO is not set
- # CONFIG_NFSD is not set
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -650,7 +682,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/db1000_defconfig linux_HEAD/arch/mips/configs/db1000_defconfig
---- linux-2.6.12/arch/mips/configs/db1000_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/db1000_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:01 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:02 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,62 +57,71 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+CONFIG_MIPS_DB1000=y
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--CONFIG_SOC_AU1000=y
--# CONFIG_SOC_AU1100 is not set
--# CONFIG_SOC_AU1500 is not set
--# CONFIG_SOC_AU1550 is not set
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--CONFIG_MIPS_DB1000=y
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1000=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -127,6 +137,15 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -168,6 +187,7 @@ CONFIG_PCMCIA=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -183,7 +203,75 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- # Memory Technology Devices (MTD)
- #
--# CONFIG_MTD is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_CFI_AMDSTD_RETRY=0
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+CONFIG_MTD_ALCHEMY=y
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLKMTD is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+# CONFIG_MTD_NAND is not set
-
- #
- # Parallel port support
-@@ -256,7 +344,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -334,7 +421,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -417,18 +503,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -438,6 +512,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -472,7 +556,8 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Watchdog Cards
- #
- # CONFIG_WATCHDOG is not set
--CONFIG_RTC=y
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
- # CONFIG_DTLK is not set
- # CONFIG_R3964 is not set
-
-@@ -488,6 +573,10 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -521,7 +610,6 @@ CONFIG_SYNCLINK_CS=m
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -531,12 +619,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -575,6 +660,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -620,6 +709,8 @@ CONFIG_RAMFS=y
- # CONFIG_BEFS_FS is not set
- # CONFIG_BFS_FS is not set
- # CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+# CONFIG_JFFS2_FS is not set
- CONFIG_CRAMFS=m
- # CONFIG_VXFS_FS is not set
- # CONFIG_HPFS_FS is not set
-@@ -708,7 +799,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -731,6 +824,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/db1100_defconfig linux_HEAD/arch/mips/configs/db1100_defconfig
---- linux-2.6.12/arch/mips/configs/db1100_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/db1100_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:01 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:03 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,62 +57,71 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+CONFIG_MIPS_DB1100=y
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--CONFIG_SOC_AU1100=y
--# CONFIG_SOC_AU1500 is not set
--# CONFIG_SOC_AU1550 is not set
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_DB1000 is not set
--CONFIG_MIPS_DB1100=y
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1100=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -127,12 +137,21 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
- # CONFIG_PAGE_SIZE_64KB is not set
- CONFIG_CPU_HAS_PREFETCH=y
--# CONFIG_64BIT_PHYS_ADDR is not set
-+CONFIG_64BIT_PHYS_ADDR=y
- # CONFIG_CPU_ADVANCED is not set
- CONFIG_CPU_HAS_LLSC=y
- CONFIG_CPU_HAS_SYNC=y
-@@ -146,15 +165,7 @@ CONFIG_MMU=y
- #
- # PCCARD (PCMCIA/CardBus) support
- #
--CONFIG_PCCARD=m
--# CONFIG_PCMCIA_DEBUG is not set
--CONFIG_PCMCIA=m
--
--#
--# PC-card bridges
--#
--# CONFIG_TCIC is not set
--# CONFIG_PCMCIA_AU1X00 is not set
-+# CONFIG_PCCARD is not set
-
- #
- # PCI Hotplug Support
-@@ -166,6 +177,7 @@ CONFIG_PCMCIA=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -181,7 +193,75 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- # Memory Technology Devices (MTD)
- #
--# CONFIG_MTD is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_CFI_AMDSTD_RETRY=0
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+CONFIG_MTD_ALCHEMY=y
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLKMTD is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+# CONFIG_MTD_NAND is not set
-
- #
- # Parallel port support
-@@ -254,7 +334,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -332,14 +411,13 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
- #
- CONFIG_NET_ETHERNET=y
- CONFIG_MII=m
--# CONFIG_MIPS_AU1X00_ENET is not set
-+CONFIG_MIPS_AU1X00_ENET=y
-
- #
- # Ethernet (1000 Mbit)
-@@ -359,19 +437,6 @@ CONFIG_MII=m
- # CONFIG_NET_RADIO is not set
-
- #
--# PCMCIA network device support
--#
--CONFIG_NET_PCMCIA=y
--CONFIG_PCMCIA_3C589=m
--CONFIG_PCMCIA_3C574=m
--CONFIG_PCMCIA_FMVJ18X=m
--CONFIG_PCMCIA_PCNET=m
--CONFIG_PCMCIA_NMCLAN=m
--CONFIG_PCMCIA_SMC91C92=m
--CONFIG_PCMCIA_XIRC2PS=m
--CONFIG_PCMCIA_AXNET=m
--
--#
- # Wan interfaces
- #
- # CONFIG_WAN is not set
-@@ -415,18 +480,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--CONFIG_SERIO_LIBPS2=m
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -436,6 +489,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_LIBPS2=m
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -453,7 +516,10 @@ CONFIG_HW_CONSOLE=y
- #
- # Non-8250 serial port support
- #
--# CONFIG_SERIAL_AU1X00 is not set
-+CONFIG_SERIAL_AU1X00=y
-+CONFIG_SERIAL_AU1X00_CONSOLE=y
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -467,7 +533,8 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Watchdog Cards
- #
- # CONFIG_WATCHDOG is not set
--CONFIG_RTC=y
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
- # CONFIG_DTLK is not set
- # CONFIG_R3964 is not set
-
-@@ -475,12 +542,11 @@ CONFIG_RTC=y
- # Ftape, the floppy tape device driver
- #
- # CONFIG_DRM is not set
-+# CONFIG_RAW_DRIVER is not set
-
- #
--# PCMCIA character devices
-+# TPM devices
- #
--CONFIG_SYNCLINK_CS=m
--# CONFIG_RAW_DRIVER is not set
-
- #
- # I2C support
-@@ -509,13 +575,41 @@ CONFIG_SYNCLINK_CS=m
- #
- # Graphics support
- #
--# CONFIG_FB is not set
-+CONFIG_FB=y
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+CONFIG_FB_SOFT_CURSOR=y
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+CONFIG_FB_AU1100=y
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_VIRTUAL is not set
-
- #
- # Console display driver support
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_FONTS=y
-+CONFIG_FONT_8x8=y
-+CONFIG_FONT_8x16=y
-+# CONFIG_FONT_6x11 is not set
-+# CONFIG_FONT_PEARL_8x8 is not set
-+# CONFIG_FONT_ACORN_8x8 is not set
-+# CONFIG_FONT_MINI_4x6 is not set
-+# CONFIG_FONT_SUN8x16 is not set
-+# CONFIG_FONT_SUN12x22 is not set
-+
-+#
-+# Logo configuration
-+#
-+CONFIG_LOGO=y
-+CONFIG_LOGO_LINUX_MONO=y
-+CONFIG_LOGO_LINUX_VGA16=y
-+CONFIG_LOGO_LINUX_CLUT224=y
- # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
-@@ -526,12 +620,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -570,6 +661,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -615,6 +710,8 @@ CONFIG_RAMFS=y
- # CONFIG_BEFS_FS is not set
- # CONFIG_BFS_FS is not set
- # CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+# CONFIG_JFFS2_FS is not set
- CONFIG_CRAMFS=m
- # CONFIG_VXFS_FS is not set
- # CONFIG_HPFS_FS is not set
-@@ -703,7 +800,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -726,6 +825,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+# CONFIG_CRYPTO_TGR192 is not set
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/db1500_defconfig linux_HEAD/arch/mips/configs/db1500_defconfig
---- linux-2.6.12/arch/mips/configs/db1500_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/db1500_defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:01 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:03 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,63 +57,73 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+CONFIG_MIPS_DB1500=y
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--# CONFIG_SOC_AU1100 is not set
--CONFIG_SOC_AU1500=y
--# CONFIG_SOC_AU1550 is not set
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--CONFIG_MIPS_DB1500=y
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
--CONFIG_DMA_COHERENT=y
-+CONFIG_DMA_NONCOHERENT=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1500=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -128,6 +139,15 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -176,6 +196,7 @@ CONFIG_PCMCIA_AU1X00=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -193,8 +214,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
--CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_REDBOOT_PARTS is not set
- # CONFIG_MTD_CMDLINE_PARTS is not set
-
-@@ -239,9 +260,7 @@ CONFIG_MTD_CFI_UTIL=y
- #
- # CONFIG_MTD_COMPLEX_MAPPINGS is not set
- # CONFIG_MTD_PHYSMAP is not set
--CONFIG_MTD_DB1X00=y
--CONFIG_MTD_DB1X00_BOOT=y
--CONFIG_MTD_DB1X00_USER=y
-+CONFIG_MTD_ALCHEMY=y
-
- #
- # Self-contained MTD device drivers
-@@ -367,7 +386,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -445,7 +463,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -481,6 +498,7 @@ CONFIG_MIPS_AU1X00_ENET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -549,19 +567,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -571,6 +576,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- # CONFIG_VT is not set
-@@ -590,6 +606,7 @@ CONFIG_SERIAL_AU1X00=y
- CONFIG_SERIAL_AU1X00_CONSOLE=y
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -603,7 +620,8 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Watchdog Cards
- #
- # CONFIG_WATCHDOG is not set
--CONFIG_RTC=y
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
- # CONFIG_DTLK is not set
- # CONFIG_R3964 is not set
- # CONFIG_APPLICOM is not set
-@@ -620,6 +638,11 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -647,7 +670,6 @@ CONFIG_SYNCLINK_CS=m
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -689,6 +711,8 @@ CONFIG_SOUND_AU1000=y
- #
- # USB support
- #
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
- CONFIG_USB=y
- # CONFIG_USB_DEBUG is not set
-
-@@ -699,14 +723,14 @@ CONFIG_USB=y
- # CONFIG_USB_BANDWIDTH is not set
- # CONFIG_USB_DYNAMIC_MINORS is not set
- # CONFIG_USB_OTG is not set
--CONFIG_USB_ARCH_HAS_HCD=y
--CONFIG_USB_ARCH_HAS_OHCI=y
-
- #
- # USB Host Controller Drivers
- #
- # CONFIG_USB_EHCI_HCD is not set
- CONFIG_USB_OHCI_HCD=y
-+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
-+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
- # CONFIG_USB_UHCI_HCD is not set
- # CONFIG_USB_SL811_HCD is not set
-
-@@ -762,6 +786,7 @@ CONFIG_USB_HIDINPUT=y
- # CONFIG_USB_PEGASUS is not set
- # CONFIG_USB_RTL8150 is not set
- # CONFIG_USB_USBNET is not set
-+CONFIG_USB_MON=m
-
- #
- # USB port drivers
-@@ -828,6 +853,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -963,7 +992,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -986,6 +1017,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/db1550_defconfig linux_HEAD/arch/mips/configs/db1550_defconfig
---- linux-2.6.12/arch/mips/configs/db1550_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/db1550_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:02 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:04 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,63 +57,72 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+CONFIG_MIPS_DB1550=y
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--# CONFIG_SOC_AU1100 is not set
--# CONFIG_SOC_AU1500 is not set
--CONFIG_SOC_AU1550=y
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--CONFIG_MIPS_DB1550=y
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
--CONFIG_DMA_COHERENT=y
-+CONFIG_DMA_NONCOHERENT=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1550=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -128,6 +138,15 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -176,6 +195,7 @@ CONFIG_PCMCIA_AU1X00=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -193,8 +213,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
--CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_REDBOOT_PARTS is not set
- # CONFIG_MTD_CMDLINE_PARTS is not set
-
-@@ -238,9 +258,7 @@ CONFIG_MTD_CFI_UTIL=y
- #
- # CONFIG_MTD_COMPLEX_MAPPINGS is not set
- # CONFIG_MTD_PHYSMAP is not set
--CONFIG_MTD_DB1550=y
--CONFIG_MTD_DB1550_BOOT=y
--CONFIG_MTD_DB1550_USER=y
-+CONFIG_MTD_ALCHEMY=y
-
- #
- # Self-contained MTD device drivers
-@@ -398,7 +416,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -476,7 +493,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -512,6 +528,7 @@ CONFIG_MIPS_AU1X00_ENET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -588,19 +605,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -610,6 +614,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- # CONFIG_VT is not set
-@@ -629,6 +644,7 @@ CONFIG_SERIAL_AU1X00=y
- CONFIG_SERIAL_AU1X00_CONSOLE=y
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -660,6 +676,11 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -687,7 +708,6 @@ CONFIG_SYNCLINK_CS=m
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -697,13 +717,9 @@ CONFIG_SYNCLINK_CS=m
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -742,6 +758,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -877,7 +897,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -900,6 +922,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ddb5476_defconfig linux_HEAD/arch/mips/configs/ddb5476_defconfig
---- linux-2.6.12/arch/mips/configs/ddb5476_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ddb5476_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:02 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:04 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,40 +51,63 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- CONFIG_DDB5476=y
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_I8259=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_DDB5XXX_COMMON=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -92,8 +116,8 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -109,6 +133,17 @@ CONFIG_CPU_R5432=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -135,11 +170,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--CONFIG_PCMCIA_PROBE=y
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -181,7 +211,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- # Block devices
- #
- # CONFIG_BLK_DEV_FD is not set
--# CONFIG_BLK_DEV_XD is not set
- # CONFIG_BLK_CPQ_DA is not set
- # CONFIG_BLK_CPQ_CISS_DA is not set
- # CONFIG_BLK_DEV_DAC960 is not set
-@@ -274,7 +303,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -336,7 +364,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -351,7 +378,6 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_HAPPYMEAL is not set
- # CONFIG_SUNGEM is not set
- # CONFIG_NET_VENDOR_3COM is not set
--# CONFIG_LANCE is not set
- # CONFIG_NET_VENDOR_SMC is not set
- # CONFIG_NET_VENDOR_RACAL is not set
-
-@@ -378,6 +404,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -434,19 +461,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -456,6 +470,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -476,6 +501,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -502,6 +528,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -529,6 +560,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Graphics support
- #
- CONFIG_FB=y
-+# CONFIG_FB_CFB_FILLRECT is not set
-+# CONFIG_FB_CFB_COPYAREA is not set
-+# CONFIG_FB_CFB_IMAGEBLIT is not set
-+# CONFIG_FB_SOFT_CURSOR is not set
-+# CONFIG_FB_MACMODES is not set
- # CONFIG_FB_MODE_HELPERS is not set
- # CONFIG_FB_TILEBLITTING is not set
- # CONFIG_FB_CIRRUS is not set
-@@ -536,6 +572,7 @@ CONFIG_FB=y
- # CONFIG_FB_CYBER2000 is not set
- # CONFIG_FB_ASILIANT is not set
- # CONFIG_FB_IMSTT is not set
-+# CONFIG_FB_NVIDIA is not set
- # CONFIG_FB_RIVA is not set
- # CONFIG_FB_MATROX is not set
- # CONFIG_FB_RADEON_OLD is not set
-@@ -548,8 +585,10 @@ CONFIG_FB=y
- # CONFIG_FB_KYRO is not set
- # CONFIG_FB_3DFX is not set
- # CONFIG_FB_VOODOO1 is not set
-+# CONFIG_FB_SMIVGX is not set
- # CONFIG_FB_TRIDENT is not set
- # CONFIG_FB_E1356 is not set
-+# CONFIG_FB_S1D13XXX is not set
- # CONFIG_FB_VIRTUAL is not set
-
- #
-@@ -574,13 +613,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -606,6 +641,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -667,7 +706,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -696,7 +734,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE="ip=any"
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ddb5477_defconfig linux_HEAD/arch/mips/configs/ddb5477_defconfig
---- linux-2.6.12/arch/mips/configs/ddb5477_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ddb5477_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:02 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:05 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,41 +51,64 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- CONFIG_DDB5477=y
--CONFIG_DDB5477_BUS_FREQUENCY=0
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+CONFIG_DDB5477_BUS_FREQUENCY=0
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_I8259=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_DDB5XXX_COMMON=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -92,8 +116,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -109,6 +133,17 @@ CONFIG_CPU_R5432=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -134,10 +169,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -242,7 +273,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -304,7 +334,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -359,6 +388,7 @@ CONFIG_PCNET32=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -415,19 +445,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -437,6 +454,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -457,6 +485,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -483,6 +512,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -516,7 +550,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -526,13 +559,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -558,6 +587,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -650,7 +683,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE="ip=any"
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/decstation_defconfig linux_HEAD/arch/mips/configs/decstation_defconfig
---- linux-2.6.12/arch/mips/configs/decstation_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/decstation_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:03 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:15 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,40 +57,63 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- CONFIG_MACH_DECSTATION=y
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_EARLY_PRINTK=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_BOOT_ELF32=y
- CONFIG_MIPS_L1_CACHE_SHIFT=4
-@@ -97,8 +121,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=4
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- CONFIG_CPU_R3000=y
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -114,6 +138,16 @@ CONFIG_CPU_R3000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -134,10 +168,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -266,7 +296,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -328,7 +357,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -391,18 +419,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -412,12 +428,23 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
- CONFIG_VT_CONSOLE=y
- CONFIG_HW_CONSOLE=y
- # CONFIG_SERIAL_NONSTANDARD is not set
-+# CONFIG_SERIAL_DEC is not set
-
- #
- # Serial drivers
-@@ -456,6 +483,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -489,7 +520,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -503,10 +533,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -534,6 +560,10 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -590,7 +620,6 @@ CONFIG_RAMFS=y
- #
- # CONFIG_NFS_FS is not set
- # CONFIG_NFSD is not set
--# CONFIG_EXPORTFS is not set
- # CONFIG_SMB_FS is not set
- # CONFIG_CIFS is not set
- # CONFIG_NCP_FS is not set
-@@ -630,7 +659,9 @@ CONFIG_ULTRIX_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/e55_defconfig linux_HEAD/arch/mips/configs/e55_defconfig
---- linux-2.6.12/arch/mips/configs/e55_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/e55_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:03 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:15 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,55 +57,79 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--CONFIG_CASIO_E55=y
--# CONFIG_IBM_WORKPAD is not set
--# CONFIG_TANBAC_TB0226 is not set
--# CONFIG_TANBAC_TB0229 is not set
--# CONFIG_VICTOR_MPC30X is not set
--# CONFIG_ZAO_CAPCELLA is not set
--# CONFIG_VRC4171 is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+CONFIG_CASIO_E55=y
-+# CONFIG_IBM_WORKPAD is not set
-+# CONFIG_TANBAC_TB0226 is not set
-+# CONFIG_TANBAC_TB0229 is not set
-+# CONFIG_VICTOR_MPC30X is not set
-+# CONFIG_ZAO_CAPCELLA is not set
-+# CONFIG_GPIO_VR41XX is not set
-+# CONFIG_VRC4171 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -120,6 +145,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -140,11 +176,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--CONFIG_PCMCIA_PROBE=y
--
--#
- # PCI Hotplug Support
- #
-
-@@ -185,7 +216,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- # Block devices
- #
- # CONFIG_BLK_DEV_FD is not set
--# CONFIG_BLK_DEV_XD is not set
- # CONFIG_BLK_DEV_COW_COMMON is not set
- # CONFIG_BLK_DEV_LOOP is not set
- # CONFIG_BLK_DEV_NBD is not set
-@@ -270,7 +300,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -330,7 +359,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -343,7 +371,6 @@ CONFIG_NETDEVICES=y
- CONFIG_NET_ETHERNET=y
- # CONFIG_MII is not set
- # CONFIG_NET_VENDOR_3COM is not set
--# CONFIG_LANCE is not set
- # CONFIG_NET_VENDOR_SMC is not set
- # CONFIG_NET_VENDOR_RACAL is not set
- # CONFIG_AT1700 is not set
-@@ -408,18 +435,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -429,6 +444,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -449,6 +474,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -487,6 +513,10 @@ CONFIG_WATCHDOG=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -521,7 +551,6 @@ CONFIG_WATCHDOG=y
- # CONFIG_VGA_CONSOLE is not set
- # CONFIG_MDA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -535,10 +564,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -562,6 +587,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -653,7 +682,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ev64120_defconfig linux_HEAD/arch/mips/configs/ev64120_defconfig
---- linux-2.6.12/arch/mips/configs/ev64120_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ev64120_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:03 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:16 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,40 +57,63 @@ CONFIG_MODULE_SRCVERSION_ALL=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- CONFIG_MIPS_EV64120=y
--# CONFIG_EVB_PCI1 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_EVB_PCI1 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_MIPS_GT64120=y
- # CONFIG_SYSCLK_75 is not set
- # CONFIG_SYSCLK_83 is not set
-@@ -99,8 +123,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -116,6 +140,17 @@ CONFIG_CPU_R5000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -142,10 +177,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -249,7 +280,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -311,7 +341,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -346,6 +375,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -409,19 +439,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -431,6 +448,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -451,6 +479,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -477,6 +506,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -510,7 +544,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -520,13 +553,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -552,6 +581,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -613,7 +646,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -642,7 +674,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::"
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ev96100_defconfig linux_HEAD/arch/mips/configs/ev96100_defconfig
---- linux-2.6.12/arch/mips/configs/ev96100_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ev96100_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:03 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:16 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,39 +57,62 @@ CONFIG_MODULE_SRCVERSION_ALL=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- CONFIG_MIPS_EV96100=y
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_GT64120=y
- CONFIG_SWAP_IO_SPACE=y
-@@ -98,8 +122,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -115,6 +139,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- CONFIG_CPU_RM7000=y
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -142,10 +177,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -241,7 +272,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -303,7 +333,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -366,18 +395,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -387,6 +404,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -432,6 +459,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -465,7 +496,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -479,10 +509,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -506,6 +532,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -567,7 +597,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -596,7 +625,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ip22_defconfig linux_HEAD/arch/mips/configs/ip22_defconfig
---- linux-2.6.12/arch/mips/configs/ip22_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ip22_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:04 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:17 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,7 +23,6 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
-@@ -33,6 +30,9 @@ CONFIG_IKCONFIG_PROC=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,40 +58,63 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- CONFIG_SGI_IP22=y
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_ARC=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_SWAP_IO_SPACE=y
- CONFIG_ARC32=y
-@@ -102,8 +126,8 @@ CONFIG_ARC_PROMLIB=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -119,6 +143,17 @@ CONFIG_CPU_R5000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -135,6 +170,7 @@ CONFIG_CPU_HAS_SYNC=y
- #
- # Bus options (PCI, PCMCIA, EISA, ISA, TC)
- #
-+CONFIG_HW_HAS_EISA=y
- # CONFIG_EISA is not set
- CONFIG_MMU=y
-
-@@ -144,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -276,7 +308,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -409,7 +440,7 @@ CONFIG_IP_NF_ARPFILTER=m
- CONFIG_IP_NF_ARP_MANGLE=m
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- CONFIG_IP6_NF_QUEUE=m
- CONFIG_IP6_NF_IPTABLES=m
-@@ -478,6 +509,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -488,6 +520,7 @@ CONFIG_NET_CLS_U32=m
- # CONFIG_CLS_U32_MARK is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -505,7 +538,6 @@ CONFIG_DUMMY=m
- CONFIG_BONDING=m
- CONFIG_EQUALIZER=m
- CONFIG_TUN=m
--CONFIG_ETHERTAP=m
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -568,18 +600,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--CONFIG_SERIO_LIBPS2=y
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- CONFIG_INPUT_KEYBOARD=y
-@@ -597,6 +617,16 @@ CONFIG_MOUSE_SERIAL=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_LIBPS2=y
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -648,6 +678,10 @@ CONFIG_RAW_DRIVER=m
- CONFIG_MAX_RAW_DEVS=256
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -692,7 +726,6 @@ CONFIG_LOGO=y
- # CONFIG_LOGO_LINUX_VGA16 is not set
- # CONFIG_LOGO_LINUX_CLUT224 is not set
- CONFIG_LOGO_SGI_CLUT224=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -706,10 +739,6 @@ CONFIG_LOGO_SGI_CLUT224=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -739,7 +768,12 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- CONFIG_XFS_SECURITY=y
-@@ -907,7 +941,9 @@ CONFIG_NLS_UTF8=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -930,6 +966,7 @@ CONFIG_CRYPTO_SHA1=m
- CONFIG_CRYPTO_SHA256=m
- CONFIG_CRYPTO_SHA512=m
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=m
- CONFIG_CRYPTO_BLOWFISH=m
- CONFIG_CRYPTO_TWOFISH=m
-@@ -944,7 +981,7 @@ CONFIG_CRYPTO_ANUBIS=m
- CONFIG_CRYPTO_DEFLATE=y
- CONFIG_CRYPTO_MICHAEL_MIC=m
- CONFIG_CRYPTO_CRC32C=m
--CONFIG_CRYPTO_TEST=m
-+# CONFIG_CRYPTO_TEST is not set
-
- #
- # Hardware crypto devices
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ip27_defconfig linux_HEAD/arch/mips/configs/ip27_defconfig
---- linux-2.6.12/arch/mips/configs/ip27_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ip27_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,11 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:04 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:17 2005
- #
- CONFIG_MIPS=y
--CONFIG_MIPS64=y
--CONFIG_64BIT=y
-
- #
- # Code maturity level options
-@@ -13,6 +11,7 @@ CONFIG_64BIT=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_LOCK_KERNEL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -24,14 +23,17 @@ CONFIG_POSIX_MQUEUE=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=15
--# CONFIG_HOTPLUG is not set
-+CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
- CONFIG_IKCONFIG_PROC=y
-+CONFIG_CPUSETS=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,45 +60,69 @@ CONFIG_STOP_MACHINE=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
- CONFIG_SGI_IP27=y
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
-+# CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
- # CONFIG_SGI_SN0_N_MODE is not set
- CONFIG_DISCONTIGMEM=y
- CONFIG_NUMA=y
- # CONFIG_MAPPED_KERNEL is not set
- # CONFIG_REPLICATE_KTEXT is not set
- # CONFIG_REPLICATE_EXHANDLERS is not set
--# CONFIG_SGI_IP32 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
--# CONFIG_SNI_RM200_PCI is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_ARC=y
- CONFIG_DMA_IP27=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_MIPS_L1_CACHE_SHIFT=7
- CONFIG_ARC64=y
- CONFIG_BOOT_ELF64=y
-@@ -104,8 +131,8 @@ CONFIG_QL_ISP_A64=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -121,6 +148,16 @@ CONFIG_CPU_R10000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+# CONFIG_MIPS32 is not set
-+CONFIG_MIPS64=y
-+CONFIG_64BIT=y
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -150,10 +187,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -163,7 +196,7 @@ CONFIG_MMU=y
- #
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
--# CONFIG_BUILD_ELF64 is not set
-+CONFIG_BUILD_ELF64=y
- CONFIG_MIPS32_COMPAT=y
- CONFIG_COMPAT=y
- CONFIG_MIPS32_O32=y
-@@ -179,7 +212,7 @@ CONFIG_BINFMT_ELF32=y
- #
- CONFIG_STANDALONE=y
- CONFIG_PREVENT_FIRMWARE_BUILD=y
--# CONFIG_FW_LOADER is not set
-+CONFIG_FW_LOADER=m
-
- #
- # Memory Technology Devices (MTD)
-@@ -256,7 +289,7 @@ CONFIG_SCSI_LOGGING=y
- #
- CONFIG_SCSI_SPI_ATTRS=y
- # CONFIG_SCSI_FC_ATTRS is not set
--# CONFIG_SCSI_ISCSI_ATTRS is not set
-+CONFIG_SCSI_ISCSI_ATTRS=m
-
- #
- # SCSI low-level drivers
-@@ -271,18 +304,13 @@ CONFIG_SCSI_SPI_ATTRS=y
- # CONFIG_MEGARAID_NEWGEN is not set
- # CONFIG_MEGARAID_LEGACY is not set
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_IPS is not set
- # CONFIG_SCSI_INITIO is not set
- # CONFIG_SCSI_INIA100 is not set
- # CONFIG_SCSI_SYM53C8XX_2 is not set
- # CONFIG_SCSI_IPR is not set
--CONFIG_SCSI_QLOGIC_ISP=y
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=y
-@@ -291,6 +319,7 @@ CONFIG_SCSI_QLA2XXX=y
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_DEBUG is not set
-@@ -313,6 +342,8 @@ CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_ZERO=m
-+CONFIG_DM_MULTIPATH=m
-+CONFIG_DM_MULTIPATH_EMC=m
-
- #
- # Fusion MPT device support
-@@ -339,7 +370,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -404,6 +434,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -413,6 +444,7 @@ CONFIG_NET_CLS_U32=m
- # CONFIG_NET_CLS_IND is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -430,7 +462,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -468,6 +499,7 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -513,25 +545,15 @@ CONFIG_SGI_IOC3_ETH_HW_TX_CSUM=y
- # CONFIG_INPUT is not set
-
- #
--# Userland interfaces
--#
--
--#
--# Input I/O drivers
-+# Hardware I/O ports
- #
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
- CONFIG_SERIO=y
- # CONFIG_SERIO_I8042 is not set
- CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
- # CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_LIBPS2=m
- CONFIG_SERIO_RAW=m
--
--#
--# Input Device Drivers
--#
-+# CONFIG_GAMEPORT is not set
-
- #
- # Character devices
-@@ -557,6 +579,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -584,6 +607,11 @@ CONFIG_SGI_IP27_RTC=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -611,7 +639,6 @@ CONFIG_SGI_IP27_RTC=y
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -621,13 +648,9 @@ CONFIG_SGI_IP27_RTC=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -642,7 +665,11 @@ CONFIG_USB_ARCH_HAS_OHCI=y
- #
- # InfiniBand support
- #
--# CONFIG_INFINIBAND is not set
-+CONFIG_INFINIBAND=m
-+CONFIG_INFINIBAND_MTHCA=m
-+# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-+CONFIG_INFINIBAND_IPOIB=m
-+# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-
- #
- # File systems
-@@ -661,6 +688,10 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
-@@ -728,7 +759,6 @@ CONFIG_NFS_V3=y
- # CONFIG_ROOT_NFS is not set
- CONFIG_LOCKD=y
- CONFIG_LOCKD_V4=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- CONFIG_SUNRPC_GSS=y
- CONFIG_RPCSEC_GSS_KRB5=y
-@@ -772,7 +802,9 @@ CONFIG_SGI_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=15
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -795,6 +827,7 @@ CONFIG_CRYPTO_SHA1=y
- CONFIG_CRYPTO_SHA256=y
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=y
- CONFIG_CRYPTO_BLOWFISH=y
- CONFIG_CRYPTO_TWOFISH=y
-@@ -809,7 +842,7 @@ CONFIG_CRYPTO_ANUBIS=m
- CONFIG_CRYPTO_DEFLATE=y
- CONFIG_CRYPTO_MICHAEL_MIC=y
- CONFIG_CRYPTO_CRC32C=m
--CONFIG_CRYPTO_TEST=m
-+# CONFIG_CRYPTO_TEST is not set
-
- #
- # Hardware crypto devices
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ip32_defconfig linux_HEAD/arch/mips/configs/ip32_defconfig
---- linux-2.6.12/arch/mips/configs/ip32_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ip32_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,11 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:04 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:18 2005
- #
- CONFIG_MIPS=y
--CONFIG_MIPS64=y
--CONFIG_64BIT=y
-
- #
- # Code maturity level options
-@@ -13,6 +11,7 @@ CONFIG_64BIT=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +24,15 @@ CONFIG_BSD_PROCESS_ACCT=y
- # CONFIG_BSD_PROCESS_ACCT_V3 is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,33 +52,55 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
- # CONFIG_SGI_IP27 is not set
- CONFIG_SGI_IP32=y
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
-@@ -84,7 +108,9 @@ CONFIG_ARC=y
- CONFIG_DMA_IP32=y
- CONFIG_OWN_DMA=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_ARC32=y
- CONFIG_BOOT_ELF32=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -94,8 +120,8 @@ CONFIG_ARC_PROMLIB=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -111,6 +137,16 @@ CONFIG_CPU_R5000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+# CONFIG_MIPS32 is not set
-+CONFIG_MIPS64=y
-+CONFIG_64BIT=y
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -138,10 +174,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -243,7 +275,7 @@ CONFIG_SCSI_LOGGING=y
- #
- # SCSI Transport Attributes
- #
--# CONFIG_SCSI_SPI_ATTRS is not set
-+CONFIG_SCSI_SPI_ATTRS=y
- # CONFIG_SCSI_FC_ATTRS is not set
- # CONFIG_SCSI_ISCSI_ATTRS is not set
-
-@@ -265,18 +297,13 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
- # CONFIG_MEGARAID_NEWGEN is not set
- # CONFIG_MEGARAID_LEGACY is not set
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_IPS is not set
- # CONFIG_SCSI_INITIO is not set
- # CONFIG_SCSI_INIA100 is not set
- # CONFIG_SCSI_SYM53C8XX_2 is not set
- # CONFIG_SCSI_IPR is not set
--# CONFIG_SCSI_QLOGIC_ISP is not set
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=y
-@@ -285,6 +312,7 @@ CONFIG_SCSI_QLA2XXX=y
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_DEBUG is not set
-@@ -319,7 +347,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -381,7 +408,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -417,6 +443,7 @@ CONFIG_SGI_O2MACE_ETH=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -474,27 +501,25 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
- #
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
- CONFIG_SERIO=y
- # CONFIG_SERIO_I8042 is not set
- CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
- # CONFIG_SERIO_PCIPS2 is not set
- # CONFIG_SERIO_MACEPS2 is not set
- # CONFIG_SERIO_LIBPS2 is not set
- CONFIG_SERIO_RAW=y
--
--#
--# Input Device Drivers
--#
--# CONFIG_INPUT_KEYBOARD is not set
--# CONFIG_INPUT_MOUSE is not set
--# CONFIG_INPUT_JOYSTICK is not set
--# CONFIG_INPUT_TOUCHSCREEN is not set
--# CONFIG_INPUT_MISC is not set
-+# CONFIG_GAMEPORT is not set
-
- #
- # Character devices
-@@ -517,6 +542,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -543,6 +569,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -576,7 +607,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -586,13 +616,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -618,6 +644,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -681,7 +711,6 @@ CONFIG_NFS_V3=y
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
- CONFIG_LOCKD_V4=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -720,7 +749,9 @@ CONFIG_SGI_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/it8172_defconfig linux_HEAD/arch/mips/configs/it8172_defconfig
---- linux-2.6.12/arch/mips/configs/it8172_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/it8172_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:05 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:19 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -26,13 +24,15 @@ CONFIG_BSD_PROCESS_ACCT=y
- # CONFIG_BSD_PROCESS_ACCT_V3 is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,40 +58,63 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- CONFIG_MIPS_ITE8172=y
--# CONFIG_IT8172_REVC is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_IT8172_REVC is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_ITE_BOARD_GEN=y
- CONFIG_IT8172_CIR=y
- CONFIG_IT8712=y
-@@ -99,8 +123,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -116,6 +140,17 @@ CONFIG_CPU_NEVADA=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -139,10 +174,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -169,8 +200,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
--# CONFIG_MTD_PARTITIONS is not set
- # CONFIG_MTD_CONCAT is not set
-+# CONFIG_MTD_PARTITIONS is not set
-
- #
- # User Modules And Translation Layers
-@@ -330,7 +361,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -392,7 +422,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -454,18 +483,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -475,6 +492,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -524,6 +551,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -557,7 +588,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -591,10 +621,6 @@ CONFIG_SOUND_IT8172=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -618,6 +644,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -681,7 +711,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -710,7 +739,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ivr_defconfig linux_HEAD/arch/mips/configs/ivr_defconfig
---- linux-2.6.12/arch/mips/configs/ivr_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ivr_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:05 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:19 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -26,13 +24,15 @@ CONFIG_BSD_PROCESS_ACCT=y
- # CONFIG_BSD_PROCESS_ACCT_V3 is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,39 +58,62 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- CONFIG_MIPS_IVR=y
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_ITE_BOARD_GEN=y
- CONFIG_IT8172_CIR=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -97,8 +121,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -114,6 +138,17 @@ CONFIG_CPU_NEVADA=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -139,10 +174,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -269,7 +300,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -331,7 +361,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -366,6 +395,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -422,19 +452,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -444,6 +461,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -466,6 +494,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -491,6 +520,11 @@ CONFIG_RTC=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -524,7 +558,6 @@ CONFIG_RTC=y
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -534,13 +567,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -566,6 +595,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -627,7 +660,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -656,7 +688,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/jaguar-atx_defconfig linux_HEAD/arch/mips/configs/jaguar-atx_defconfig
---- linux-2.6.12/arch/mips/configs/jaguar-atx_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/jaguar-atx_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:05 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:20 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- # CONFIG_EXPERIMENTAL is not set
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -24,7 +22,6 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
-@@ -32,6 +29,9 @@ CONFIG_IKCONFIG_PROC=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -54,35 +55,64 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
-+# CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
-+# CONFIG_MIPS_EV64120 is not set
-+# CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
-+# CONFIG_MIPS_SEAD is not set
-+CONFIG_MOMENCO_JAGUAR_ATX=y
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--CONFIG_MOMENCO_JAGUAR_ATX=y
--CONFIG_JAGUAR_DMALOW=y
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
-+# CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+CONFIG_JAGUAR_DMALOW=y
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_LIMITED_DMA=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_CPU_RM7K=y
- CONFIG_IRQ_MV64340=y
-@@ -94,8 +124,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -111,6 +141,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- # CONFIG_CPU_RM7000 is not set
- CONFIG_CPU_RM9000=y
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -142,10 +183,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -247,7 +284,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--# CONFIG_NETLINK_DEV is not set
- CONFIG_UNIX=y
- # CONFIG_NET_KEY is not set
- CONFIG_INET=y
-@@ -265,7 +301,14 @@ CONFIG_IP_PNP_BOOTP=y
- # CONFIG_INET_IPCOMP is not set
- CONFIG_INET_TUNNEL=m
- CONFIG_IP_TCPDIAG=m
--# CONFIG_IP_TCPDIAG_IPV6 is not set
-+CONFIG_IP_TCPDIAG_IPV6=y
-+CONFIG_IPV6=m
-+CONFIG_IPV6_PRIVACY=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_IPV6_TUNNEL=m
- # CONFIG_NETFILTER is not set
- CONFIG_XFRM=y
- CONFIG_XFRM_USER=m
-@@ -345,6 +388,7 @@ CONFIG_EEPRO100=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
- CONFIG_MV643XX_ETH=y
- CONFIG_MV643XX_ETH_0=y
- CONFIG_MV643XX_ETH_1=y
-@@ -390,20 +434,10 @@ CONFIG_MV643XX_ETH_2=y
- # CONFIG_INPUT is not set
-
- #
--# Userland interfaces
--#
--
-+# Hardware I/O ports
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
- # CONFIG_SERIO is not set
--# CONFIG_SERIO_I8042 is not set
--
--#
--# Input Device Drivers
--#
-+# CONFIG_GAMEPORT is not set
-
- #
- # Character devices
-@@ -424,6 +458,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -450,6 +485,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -477,7 +516,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -487,13 +525,9 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -518,6 +552,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -569,7 +607,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_SMB_FS is not set
- # CONFIG_CIFS is not set
-@@ -590,7 +627,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -604,7 +643,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
- #
- # Cryptographic options
- #
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+CONFIG_CRYPTO_HMAC=y
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_MD4=m
-+CONFIG_CRYPTO_MD5=m
-+CONFIG_CRYPTO_SHA1=m
-+CONFIG_CRYPTO_SHA256=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_DES=m
-+CONFIG_CRYPTO_BLOWFISH=m
-+CONFIG_CRYPTO_TWOFISH=m
-+CONFIG_CRYPTO_SERPENT=m
-+CONFIG_CRYPTO_AES=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_CAST6=m
-+CONFIG_CRYPTO_TEA=m
-+CONFIG_CRYPTO_ARC4=m
-+CONFIG_CRYPTO_KHAZAD=m
-+CONFIG_CRYPTO_ANUBIS=m
-+CONFIG_CRYPTO_DEFLATE=m
-+CONFIG_CRYPTO_MICHAEL_MIC=m
-+CONFIG_CRYPTO_CRC32C=m
-+CONFIG_CRYPTO_TEST=m
-
- #
- # Hardware crypto devices
-@@ -615,6 +678,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
- #
- # CONFIG_CRC_CCITT is not set
- # CONFIG_CRC32 is not set
--# CONFIG_LIBCRC32C is not set
-+CONFIG_LIBCRC32C=m
-+CONFIG_ZLIB_INFLATE=m
-+CONFIG_ZLIB_DEFLATE=m
- CONFIG_GENERIC_HARDIRQS=y
- CONFIG_GENERIC_IRQ_PROBE=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/jmr3927_defconfig linux_HEAD/arch/mips/configs/jmr3927_defconfig
---- linux-2.6.12/arch/mips/configs/jmr3927_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/jmr3927_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:06 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:20 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,39 +51,62 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--CONFIG_TOSHIBA_JMR3927=y
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+CONFIG_TOSHIBA_JMR3927=y
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_MIPS_TX3927=y
- CONFIG_SWAP_IO_SPACE=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -91,8 +115,8 @@ CONFIG_TOSHIBA_BOARDS=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- CONFIG_CPU_TX39XX=y
- # CONFIG_CPU_VR41XX is not set
-@@ -108,6 +132,15 @@ CONFIG_CPU_TX39XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -132,10 +165,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -240,7 +269,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -302,7 +330,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -337,6 +364,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -393,19 +421,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -415,6 +430,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -425,11 +451,9 @@ CONFIG_SERIAL_NONSTANDARD=y
- # CONFIG_ROCKETPORT is not set
- # CONFIG_CYCLADES is not set
- # CONFIG_DIGIEPCA is not set
--# CONFIG_DIGI is not set
- # CONFIG_MOXA_INTELLIO is not set
- # CONFIG_MOXA_SMARTIO is not set
- # CONFIG_ISI is not set
--# CONFIG_SYNCLINK is not set
- # CONFIG_SYNCLINKMP is not set
- # CONFIG_N_HDLC is not set
- # CONFIG_RISCOM8 is not set
-@@ -437,10 +461,6 @@ CONFIG_SERIAL_NONSTANDARD=y
- # CONFIG_SX is not set
- # CONFIG_RIO is not set
- # CONFIG_STALDRV is not set
--# CONFIG_SERIAL_TX3912 is not set
--CONFIG_TXX927_SERIAL=y
--CONFIG_TXX927_SERIAL_CONSOLE=y
--# CONFIG_SERIAL_TXX9 is not set
-
- #
- # Serial drivers
-@@ -450,6 +470,13 @@ CONFIG_TXX927_SERIAL_CONSOLE=y
- #
- # Non-8250 serial port support
- #
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_SERIAL_TXX9=y
-+CONFIG_HAS_TXX9_SERIAL=y
-+CONFIG_SERIAL_TXX9_CONSOLE=y
-+CONFIG_SERIAL_TXX9_STDSERIAL=y
-+# CONFIG_SERIAL_JSM is not set
- # CONFIG_UNIX98_PTYS is not set
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -476,6 +503,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -503,6 +535,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Graphics support
- #
- CONFIG_FB=y
-+# CONFIG_FB_CFB_FILLRECT is not set
-+# CONFIG_FB_CFB_COPYAREA is not set
-+# CONFIG_FB_CFB_IMAGEBLIT is not set
-+# CONFIG_FB_SOFT_CURSOR is not set
-+# CONFIG_FB_MACMODES is not set
- # CONFIG_FB_MODE_HELPERS is not set
- # CONFIG_FB_TILEBLITTING is not set
- # CONFIG_FB_CIRRUS is not set
-@@ -510,6 +547,7 @@ CONFIG_FB=y
- # CONFIG_FB_CYBER2000 is not set
- # CONFIG_FB_ASILIANT is not set
- # CONFIG_FB_IMSTT is not set
-+# CONFIG_FB_NVIDIA is not set
- # CONFIG_FB_RIVA is not set
- # CONFIG_FB_MATROX is not set
- # CONFIG_FB_RADEON_OLD is not set
-@@ -522,8 +560,10 @@ CONFIG_FB=y
- # CONFIG_FB_KYRO is not set
- # CONFIG_FB_3DFX is not set
- # CONFIG_FB_VOODOO1 is not set
-+# CONFIG_FB_SMIVGX is not set
- # CONFIG_FB_TRIDENT is not set
- # CONFIG_FB_E1356 is not set
-+# CONFIG_FB_S1D13XXX is not set
- # CONFIG_FB_VIRTUAL is not set
-
- #
-@@ -547,13 +587,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -578,6 +614,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -637,7 +677,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -666,7 +705,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/lasat200_defconfig linux_HEAD/arch/mips/configs/lasat200_defconfig
---- linux-2.6.12/arch/mips/configs/lasat200_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/lasat200_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:06 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:21 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,52 +57,75 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--CONFIG_LASAT=y
--CONFIG_PICVUE=y
--CONFIG_PICVUE_PROC=y
--CONFIG_DS1603=y
--CONFIG_LASAT_SYSCTL=y
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+CONFIG_LASAT=y
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+CONFIG_PICVUE=y
-+CONFIG_PICVUE_PROC=y
-+CONFIG_DS1603=y
-+CONFIG_LASAT_SYSCTL=y
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_MIPS_NILE4=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_MIPS_GT64120=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -117,6 +141,17 @@ CONFIG_CPU_R5000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -145,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -176,8 +207,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
--CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_REDBOOT_PARTS is not set
- # CONFIG_MTD_CMDLINE_PARTS is not set
-
-@@ -372,7 +403,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--# CONFIG_NETLINK_DEV is not set
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -465,6 +495,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -521,19 +552,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -543,6 +561,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -563,6 +592,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -589,6 +619,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -622,7 +657,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -632,13 +666,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -669,6 +699,10 @@ CONFIG_JBD=y
- CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -732,7 +766,6 @@ CONFIG_NFS_V3=y
- # CONFIG_NFSD is not set
- CONFIG_LOCKD=y
- CONFIG_LOCKD_V4=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -761,7 +794,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/malta_defconfig linux_HEAD/arch/mips/configs/malta_defconfig
---- linux-2.6.12/arch/mips/configs/malta_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/malta_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:53:14 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:22 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,33 +57,54 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- CONFIG_MIPS_MALTA=y
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-@@ -92,7 +114,10 @@ CONFIG_GENERIC_ISA_DMA=y
- CONFIG_I8259=y
- CONFIG_MIPS_BONITO64=y
- CONFIG_MIPS_MSC=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_MIPS_BOARDS_GEN=y
- CONFIG_MIPS_GT64120=y
- CONFIG_SWAP_IO_SPACE=y
-@@ -103,8 +128,8 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -120,10 +145,21 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
- # CONFIG_PAGE_SIZE_64KB is not set
-+CONFIG_CPU_HAS_PREFETCH=y
- # CONFIG_64BIT_PHYS_ADDR is not set
- # CONFIG_CPU_ADVANCED is not set
- CONFIG_CPU_HAS_LLSC=y
-@@ -145,10 +181,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -323,18 +355,13 @@ CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
- # CONFIG_MEGARAID_NEWGEN is not set
- # CONFIG_MEGARAID_LEGACY is not set
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_IPS is not set
- # CONFIG_SCSI_INITIO is not set
- # CONFIG_SCSI_INIA100 is not set
- # CONFIG_SCSI_SYM53C8XX_2 is not set
- # CONFIG_SCSI_IPR is not set
--# CONFIG_SCSI_QLOGIC_ISP is not set
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=m
-@@ -343,6 +370,7 @@ CONFIG_SCSI_QLA2XXX=m
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_NSP32 is not set
-@@ -366,6 +394,8 @@ CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_ZERO=m
-+CONFIG_DM_MULTIPATH=m
-+CONFIG_DM_MULTIPATH_EMC=m
-
- #
- # Fusion MPT device support
-@@ -392,7 +422,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -401,6 +430,7 @@ CONFIG_IP_ADVANCED_ROUTER=y
- CONFIG_IP_MULTIPLE_TABLES=y
- CONFIG_IP_ROUTE_FWMARK=y
- CONFIG_IP_ROUTE_MULTIPATH=y
-+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
- CONFIG_IP_ROUTE_VERBOSE=y
- CONFIG_IP_PNP=y
- CONFIG_IP_PNP_DHCP=y
-@@ -534,7 +564,7 @@ CONFIG_IP_NF_ARPFILTER=m
- CONFIG_IP_NF_ARP_MANGLE=m
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- CONFIG_IP6_NF_QUEUE=m
- CONFIG_IP6_NF_IPTABLES=m
-@@ -633,6 +663,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -643,6 +674,7 @@ CONFIG_NET_CLS_IND=y
- # CONFIG_CLS_U32_MARK is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -660,7 +692,6 @@ CONFIG_DUMMY=m
- CONFIG_BONDING=m
- CONFIG_EQUALIZER=m
- CONFIG_TUN=m
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -715,6 +746,7 @@ CONFIG_PCNET32=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -772,19 +804,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--# CONFIG_SERIO_RAW is not set
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -794,6 +813,17 @@ CONFIG_SERIO_SERPORT=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+# CONFIG_SERIO_RAW is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -814,6 +844,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -839,6 +870,11 @@ CONFIG_RTC=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -872,7 +908,6 @@ CONFIG_RTC=y
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -882,13 +917,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -929,7 +960,12 @@ CONFIG_JFS_SECURITY=y
- # CONFIG_JFS_DEBUG is not set
- # CONFIG_JFS_STATISTICS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- CONFIG_XFS_SECURITY=y
-@@ -1078,7 +1114,9 @@ CONFIG_NLS_UTF8=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -1100,6 +1138,7 @@ CONFIG_CRYPTO_SHA1=m
- CONFIG_CRYPTO_SHA256=m
- CONFIG_CRYPTO_SHA512=m
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=m
- CONFIG_CRYPTO_BLOWFISH=m
- CONFIG_CRYPTO_TWOFISH=m
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/mpc30x_defconfig linux_HEAD/arch/mips/configs/mpc30x_defconfig
---- linux-2.6.12/arch/mips/configs/mpc30x_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/mpc30x_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:07 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:22 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,56 +57,80 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--# CONFIG_CASIO_E55 is not set
--# CONFIG_IBM_WORKPAD is not set
--# CONFIG_TANBAC_TB0226 is not set
--# CONFIG_TANBAC_TB0229 is not set
--CONFIG_VICTOR_MPC30X=y
--# CONFIG_ZAO_CAPCELLA is not set
--CONFIG_PCI_VR41XX=y
--CONFIG_VRC4173=y
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+# CONFIG_CASIO_E55 is not set
-+# CONFIG_IBM_WORKPAD is not set
-+# CONFIG_TANBAC_TB0226 is not set
-+# CONFIG_TANBAC_TB0229 is not set
-+CONFIG_VICTOR_MPC30X=y
-+# CONFIG_ZAO_CAPCELLA is not set
-+CONFIG_PCI_VR41XX=y
-+# CONFIG_GPIO_VR41XX is not set
-+CONFIG_VRC4173=y
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -121,6 +146,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -144,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -252,7 +284,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -315,7 +346,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -350,6 +380,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -406,19 +437,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -428,6 +446,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -448,6 +477,8 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -474,6 +505,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -507,7 +543,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -517,13 +552,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -549,6 +580,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -610,7 +645,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -639,7 +673,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -662,6 +698,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ocelot_3_defconfig linux_HEAD/arch/mips/configs/ocelot_3_defconfig
---- linux-2.6.12/arch/mips/configs/ocelot_3_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ocelot_3_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:07 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:23 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,7 +23,6 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
-@@ -33,6 +30,9 @@ CONFIG_IKCONFIG_PROC=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,39 +58,62 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- CONFIG_MOMENCO_OCELOT_3=y
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_CPU_RM7K=y
- CONFIG_IRQ_MV64340=y
-@@ -101,8 +125,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -118,6 +142,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- # CONFIG_CPU_RM7000 is not set
- CONFIG_CPU_RM9000=y
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -149,10 +184,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -265,18 +296,13 @@ CONFIG_SCSI_PROC_FS=y
- # CONFIG_MEGARAID_NEWGEN is not set
- # CONFIG_MEGARAID_LEGACY is not set
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_IPS is not set
- # CONFIG_SCSI_INITIO is not set
- # CONFIG_SCSI_INIA100 is not set
- # CONFIG_SCSI_SYM53C8XX_2 is not set
- # CONFIG_SCSI_IPR is not set
--# CONFIG_SCSI_QLOGIC_ISP is not set
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=m
-@@ -285,6 +311,7 @@ CONFIG_SCSI_QLA2XXX=m
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_NSP32 is not set
-@@ -320,7 +347,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -365,7 +391,7 @@ CONFIG_NETFILTER=y
- # CONFIG_IP_NF_ARPTABLES is not set
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- # CONFIG_IP6_NF_QUEUE is not set
- # CONFIG_IP6_NF_IPTABLES is not set
-@@ -409,7 +435,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- CONFIG_TUN=m
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -439,7 +464,6 @@ CONFIG_NET_PCI=y
- # CONFIG_DGRS is not set
- # CONFIG_EEPRO100 is not set
- CONFIG_E100=y
--# CONFIG_E100_NAPI is not set
- # CONFIG_FEALNX is not set
- # CONFIG_NATSEMI is not set
- # CONFIG_NE2K_PCI is not set
-@@ -465,6 +489,7 @@ CONFIG_E100=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
- CONFIG_MV643XX_ETH=y
- CONFIG_MV643XX_ETH_0=y
- CONFIG_MV643XX_ETH_1=y
-@@ -530,19 +555,6 @@ CONFIG_INPUT=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--# CONFIG_SERIO_SERPORT is not set
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--# CONFIG_SERIO_RAW is not set
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -552,6 +564,17 @@ CONFIG_SERIO=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+# CONFIG_SERIO_SERPORT is not set
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+# CONFIG_SERIO_RAW is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -572,6 +595,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -597,6 +621,11 @@ CONFIG_RTC=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -624,6 +653,11 @@ CONFIG_RTC=y
- # Graphics support
- #
- CONFIG_FB=y
-+# CONFIG_FB_CFB_FILLRECT is not set
-+# CONFIG_FB_CFB_COPYAREA is not set
-+# CONFIG_FB_CFB_IMAGEBLIT is not set
-+# CONFIG_FB_SOFT_CURSOR is not set
-+# CONFIG_FB_MACMODES is not set
- CONFIG_FB_MODE_HELPERS=y
- # CONFIG_FB_TILEBLITTING is not set
- # CONFIG_FB_CIRRUS is not set
-@@ -631,6 +665,7 @@ CONFIG_FB_MODE_HELPERS=y
- # CONFIG_FB_CYBER2000 is not set
- # CONFIG_FB_ASILIANT is not set
- # CONFIG_FB_IMSTT is not set
-+# CONFIG_FB_NVIDIA is not set
- # CONFIG_FB_RIVA is not set
- # CONFIG_FB_MATROX is not set
- # CONFIG_FB_RADEON_OLD is not set
-@@ -643,8 +678,10 @@ CONFIG_FB_MODE_HELPERS=y
- # CONFIG_FB_KYRO is not set
- # CONFIG_FB_3DFX is not set
- # CONFIG_FB_VOODOO1 is not set
-+# CONFIG_FB_SMIVGX is not set
- # CONFIG_FB_TRIDENT is not set
- # CONFIG_FB_E1356 is not set
-+# CONFIG_FB_S1D13XXX is not set
- # CONFIG_FB_VIRTUAL is not set
-
- #
-@@ -674,13 +711,9 @@ CONFIG_LOGO_LINUX_CLUT224=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -714,7 +747,12 @@ CONFIG_REISERFS_FS=m
- # CONFIG_REISERFS_PROC_INFO is not set
- # CONFIG_REISERFS_FS_XATTR is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- # CONFIG_XFS_QUOTA is not set
- # CONFIG_XFS_SECURITY is not set
-@@ -855,7 +893,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE="ip=any root=nfs"
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ocelot_c_defconfig linux_HEAD/arch/mips/configs/ocelot_c_defconfig
---- linux-2.6.12/arch/mips/configs/ocelot_c_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ocelot_c_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,11 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:07 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:23 2005
- #
- CONFIG_MIPS=y
--CONFIG_MIPS64=y
--CONFIG_64BIT=y
-
- #
- # Code maturity level options
-@@ -13,6 +11,7 @@ CONFIG_64BIT=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -24,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -40,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -49,38 +51,62 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--CONFIG_MOMENCO_OCELOT_C=y
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+CONFIG_MOMENCO_OCELOT_C=y
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
- # CONFIG_SGI_IP27 is not set
- # CONFIG_SGI_IP32 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_MV64340=y
- CONFIG_PCI_MARVELL=y
-@@ -90,8 +116,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -107,6 +133,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- CONFIG_CPU_RM7000=y
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+# CONFIG_MIPS32 is not set
-+CONFIG_MIPS64=y
-+CONFIG_64BIT=y
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -134,10 +171,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -245,7 +278,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -307,7 +339,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -342,6 +373,7 @@ CONFIG_NET_ETHERNET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
- # CONFIG_MV643XX_ETH is not set
-
- #
-@@ -399,19 +431,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -421,6 +440,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -441,6 +471,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -467,6 +498,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -500,7 +536,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -510,13 +545,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -542,6 +573,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -634,7 +669,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ocelot_defconfig linux_HEAD/arch/mips/configs/ocelot_defconfig
---- linux-2.6.12/arch/mips/configs/ocelot_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ocelot_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:08 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:24 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -50,39 +51,62 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- CONFIG_MOMENCO_OCELOT=y
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_CPU_RM7K=y
- CONFIG_MIPS_GT64120=y
-@@ -95,8 +119,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -112,6 +136,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- CONFIG_CPU_RM7000=y
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -139,10 +174,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -238,7 +269,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -300,7 +330,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -362,18 +391,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -383,6 +400,16 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -428,6 +455,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -461,7 +492,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -475,10 +505,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -502,6 +528,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -594,7 +624,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/ocelot_g_defconfig linux_HEAD/arch/mips/configs/ocelot_g_defconfig
---- linux-2.6.12/arch/mips/configs/ocelot_g_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/ocelot_g_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,11 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:08 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:24 2005
- #
- CONFIG_MIPS=y
--CONFIG_MIPS64=y
--CONFIG_64BIT=y
-
- #
- # Code maturity level options
-@@ -13,6 +11,7 @@ CONFIG_64BIT=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -24,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -40,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -49,38 +51,62 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--CONFIG_MOMENCO_OCELOT_G=y
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+CONFIG_MOMENCO_OCELOT_G=y
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
- # CONFIG_SGI_IP27 is not set
- # CONFIG_SGI_IP32 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_CPU_RM7K=y
- CONFIG_PCI_MARVELL=y
-@@ -93,8 +119,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -110,6 +136,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- CONFIG_CPU_RM7000=y
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+# CONFIG_MIPS32 is not set
-+CONFIG_MIPS64=y
-+CONFIG_64BIT=y
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -137,10 +174,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -248,7 +281,6 @@ CONFIG_NET=y
- # Networking options
- #
- # CONFIG_PACKET is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -310,7 +342,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -346,6 +377,7 @@ CONFIG_GALILEO_64240_ETH=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -402,19 +434,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -424,6 +443,17 @@ CONFIG_SERIO_RAW=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=y
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -444,6 +474,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -470,6 +501,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -503,7 +539,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -513,13 +548,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -545,6 +576,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -637,7 +672,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/osprey_defconfig linux_HEAD/arch/mips/configs/osprey_defconfig
---- linux-2.6.12/arch/mips/configs/osprey_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/osprey_defconfig 1970-01-01 01:00:00.000000000 +0100
-@@ -1,618 +0,0 @@
--#
--# Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:08 2005
--#
--CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
--
--#
--# Code maturity level options
--#
--CONFIG_EXPERIMENTAL=y
--CONFIG_CLEAN_COMPILE=y
--CONFIG_BROKEN_ON_SMP=y
--
--#
--# General setup
--#
--CONFIG_LOCALVERSION=""
--CONFIG_SWAP=y
--CONFIG_SYSVIPC=y
--# CONFIG_POSIX_MQUEUE is not set
--# CONFIG_BSD_PROCESS_ACCT is not set
--CONFIG_SYSCTL=y
--# CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
--# CONFIG_HOTPLUG is not set
--CONFIG_KOBJECT_UEVENT=y
--# CONFIG_IKCONFIG is not set
--CONFIG_EMBEDDED=y
--CONFIG_KALLSYMS=y
--# CONFIG_KALLSYMS_EXTRA_PASS is not set
--CONFIG_FUTEX=y
--CONFIG_EPOLL=y
--# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
--CONFIG_SHMEM=y
--CONFIG_CC_ALIGN_FUNCTIONS=0
--CONFIG_CC_ALIGN_LABELS=0
--CONFIG_CC_ALIGN_LOOPS=0
--CONFIG_CC_ALIGN_JUMPS=0
--# CONFIG_TINY_SHMEM is not set
--
--#
--# Loadable module support
--#
--CONFIG_MODULES=y
--CONFIG_MODULE_UNLOAD=y
--# CONFIG_MODULE_FORCE_UNLOAD is not set
--CONFIG_OBSOLETE_MODPARM=y
--CONFIG_MODVERSIONS=y
--CONFIG_MODULE_SRCVERSION_ALL=y
--CONFIG_KMOD=y
--
--#
--# Machine selection
--#
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
--# CONFIG_MIPS_COBALT is not set
--# CONFIG_MACH_DECSTATION is not set
--# CONFIG_MIPS_EV64120 is not set
--# CONFIG_MIPS_EV96100 is not set
--# CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
--# CONFIG_MIPS_ITE8172 is not set
--# CONFIG_MIPS_ATLAS is not set
--# CONFIG_MIPS_MALTA is not set
--# CONFIG_MIPS_SEAD is not set
--# CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
--# CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
--# CONFIG_DDB5477 is not set
--CONFIG_NEC_OSPREY=y
--# CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
--# CONFIG_SNI_RM200_PCI is not set
--# CONFIG_TOSHIBA_RBTX4927 is not set
--CONFIG_RWSEM_GENERIC_SPINLOCK=y
--CONFIG_GENERIC_CALIBRATE_DELAY=y
--CONFIG_HAVE_DEC_LOCK=y
--CONFIG_DMA_NONCOHERENT=y
--CONFIG_CPU_LITTLE_ENDIAN=y
--CONFIG_IRQ_CPU=y
--CONFIG_MIPS_L1_CACHE_SHIFT=5
--CONFIG_VR4181=y
--
--#
--# CPU selection
--#
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
--# CONFIG_CPU_R3000 is not set
--# CONFIG_CPU_TX39XX is not set
--CONFIG_CPU_VR41XX=y
--# CONFIG_CPU_R4300 is not set
--# CONFIG_CPU_R4X00 is not set
--# CONFIG_CPU_TX49XX is not set
--# CONFIG_CPU_R5000 is not set
--# CONFIG_CPU_R5432 is not set
--# CONFIG_CPU_R6000 is not set
--# CONFIG_CPU_NEVADA is not set
--# CONFIG_CPU_R8000 is not set
--# CONFIG_CPU_R10000 is not set
--# CONFIG_CPU_RM7000 is not set
--# CONFIG_CPU_RM9000 is not set
--# CONFIG_CPU_SB1 is not set
--CONFIG_PAGE_SIZE_4KB=y
--# CONFIG_PAGE_SIZE_8KB is not set
--# CONFIG_PAGE_SIZE_16KB is not set
--# CONFIG_PAGE_SIZE_64KB is not set
--# CONFIG_CPU_ADVANCED is not set
--CONFIG_CPU_HAS_SYNC=y
--# CONFIG_PREEMPT is not set
--
--#
--# Bus options (PCI, PCMCIA, EISA, ISA, TC)
--#
--CONFIG_MMU=y
--
--#
--# PCCARD (PCMCIA/CardBus) support
--#
--# CONFIG_PCCARD is not set
--
--#
--# PC-card bridges
--#
--
--#
--# PCI Hotplug Support
--#
--
--#
--# Executable file formats
--#
--CONFIG_BINFMT_ELF=y
--# CONFIG_BINFMT_MISC is not set
--CONFIG_TRAD_SIGNALS=y
--
--#
--# Device Drivers
--#
--
--#
--# Generic Driver Options
--#
--CONFIG_STANDALONE=y
--CONFIG_PREVENT_FIRMWARE_BUILD=y
--# CONFIG_FW_LOADER is not set
--
--#
--# Memory Technology Devices (MTD)
--#
--# CONFIG_MTD is not set
--
--#
--# Parallel port support
--#
--# CONFIG_PARPORT is not set
--
--#
--# Plug and Play support
--#
--
--#
--# Block devices
--#
--# CONFIG_BLK_DEV_FD is not set
--# CONFIG_BLK_DEV_COW_COMMON is not set
--# CONFIG_BLK_DEV_LOOP is not set
--# CONFIG_BLK_DEV_NBD is not set
--# CONFIG_BLK_DEV_RAM is not set
--CONFIG_BLK_DEV_RAM_COUNT=16
--CONFIG_INITRAMFS_SOURCE=""
--# CONFIG_LBD is not set
--CONFIG_CDROM_PKTCDVD=m
--CONFIG_CDROM_PKTCDVD_BUFFERS=8
--# CONFIG_CDROM_PKTCDVD_WCACHE is not set
--
--#
--# IO Schedulers
--#
--CONFIG_IOSCHED_NOOP=y
--CONFIG_IOSCHED_AS=y
--CONFIG_IOSCHED_DEADLINE=y
--CONFIG_IOSCHED_CFQ=y
--CONFIG_ATA_OVER_ETH=m
--
--#
--# ATA/ATAPI/MFM/RLL support
--#
--# CONFIG_IDE is not set
--
--#
--# SCSI device support
--#
--# CONFIG_SCSI is not set
--
--#
--# Multi-device support (RAID and LVM)
--#
--# CONFIG_MD is not set
--
--#
--# Fusion MPT device support
--#
--
--#
--# IEEE 1394 (FireWire) support
--#
--
--#
--# I2O device support
--#
--
--#
--# Networking support
--#
--CONFIG_NET=y
--
--#
--# Networking options
--#
--CONFIG_PACKET=y
--# CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
--CONFIG_UNIX=y
--CONFIG_NET_KEY=y
--CONFIG_INET=y
--# CONFIG_IP_MULTICAST is not set
--# CONFIG_IP_ADVANCED_ROUTER is not set
--CONFIG_IP_PNP=y
--# CONFIG_IP_PNP_DHCP is not set
--CONFIG_IP_PNP_BOOTP=y
--# CONFIG_IP_PNP_RARP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
--# CONFIG_ARPD is not set
--# CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
--# CONFIG_INET_IPCOMP is not set
--CONFIG_INET_TUNNEL=m
--CONFIG_IP_TCPDIAG=m
--# CONFIG_IP_TCPDIAG_IPV6 is not set
--# CONFIG_IPV6 is not set
--# CONFIG_NETFILTER is not set
--CONFIG_XFRM=y
--CONFIG_XFRM_USER=m
--
--#
--# SCTP Configuration (EXPERIMENTAL)
--#
--# CONFIG_IP_SCTP is not set
--# CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
--# CONFIG_VLAN_8021Q is not set
--# CONFIG_DECNET is not set
--# CONFIG_LLC2 is not set
--# CONFIG_IPX is not set
--# CONFIG_ATALK is not set
--# CONFIG_X25 is not set
--# CONFIG_LAPB is not set
--# CONFIG_NET_DIVERT is not set
--# CONFIG_ECONET is not set
--# CONFIG_WAN_ROUTER is not set
--
--#
--# QoS and/or fair queueing
--#
--# CONFIG_NET_SCHED is not set
--# CONFIG_NET_CLS_ROUTE is not set
--
--#
--# Network testing
--#
--# CONFIG_NET_PKTGEN is not set
--# CONFIG_NETPOLL is not set
--# CONFIG_NET_POLL_CONTROLLER is not set
--# CONFIG_HAMRADIO is not set
--# CONFIG_IRDA is not set
--# CONFIG_BT is not set
--CONFIG_NETDEVICES=y
--# CONFIG_DUMMY is not set
--# CONFIG_BONDING is not set
--# CONFIG_EQUALIZER is not set
--# CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
--
--#
--# Ethernet (10 or 100Mbit)
--#
--CONFIG_NET_ETHERNET=y
--# CONFIG_MII is not set
--
--#
--# Ethernet (1000 Mbit)
--#
--
--#
--# Ethernet (10000 Mbit)
--#
--
--#
--# Token Ring devices
--#
--
--#
--# Wireless LAN (non-hamradio)
--#
--# CONFIG_NET_RADIO is not set
--
--#
--# Wan interfaces
--#
--# CONFIG_WAN is not set
--# CONFIG_PPP is not set
--# CONFIG_SLIP is not set
--# CONFIG_SHAPER is not set
--# CONFIG_NETCONSOLE is not set
--
--#
--# ISDN subsystem
--#
--# CONFIG_ISDN is not set
--
--#
--# Telephony Support
--#
--# CONFIG_PHONE is not set
--
--#
--# Input device support
--#
--CONFIG_INPUT=y
--
--#
--# Userland interfaces
--#
--CONFIG_INPUT_MOUSEDEV=y
--CONFIG_INPUT_MOUSEDEV_PSAUX=y
--CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
--CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
--# CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_TSDEV is not set
--# CONFIG_INPUT_EVDEV is not set
--# CONFIG_INPUT_EVBUG is not set
--
--#
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
--# Input Device Drivers
--#
--# CONFIG_INPUT_KEYBOARD is not set
--# CONFIG_INPUT_MOUSE is not set
--# CONFIG_INPUT_JOYSTICK is not set
--# CONFIG_INPUT_TOUCHSCREEN is not set
--# CONFIG_INPUT_MISC is not set
--
--#
--# Character devices
--#
--CONFIG_VT=y
--CONFIG_VT_CONSOLE=y
--CONFIG_HW_CONSOLE=y
--# CONFIG_SERIAL_NONSTANDARD is not set
--
--#
--# Serial drivers
--#
--CONFIG_SERIAL_8250=y
--CONFIG_SERIAL_8250_CONSOLE=y
--CONFIG_SERIAL_8250_NR_UARTS=4
--# CONFIG_SERIAL_8250_EXTENDED is not set
--
--#
--# Non-8250 serial port support
--#
--CONFIG_SERIAL_CORE=y
--CONFIG_SERIAL_CORE_CONSOLE=y
--CONFIG_UNIX98_PTYS=y
--CONFIG_LEGACY_PTYS=y
--CONFIG_LEGACY_PTY_COUNT=256
--
--#
--# IPMI
--#
--# CONFIG_IPMI_HANDLER is not set
--
--#
--# Watchdog Cards
--#
--# CONFIG_WATCHDOG is not set
--# CONFIG_RTC is not set
--# CONFIG_GEN_RTC is not set
--# CONFIG_DTLK is not set
--# CONFIG_R3964 is not set
--
--#
--# Ftape, the floppy tape device driver
--#
--# CONFIG_DRM is not set
--# CONFIG_RAW_DRIVER is not set
--
--#
--# I2C support
--#
--# CONFIG_I2C is not set
--
--#
--# Dallas's 1-wire bus
--#
--# CONFIG_W1 is not set
--
--#
--# Misc devices
--#
--
--#
--# Multimedia devices
--#
--# CONFIG_VIDEO_DEV is not set
--
--#
--# Digital Video Broadcasting Devices
--#
--# CONFIG_DVB is not set
--
--#
--# Graphics support
--#
--# CONFIG_FB is not set
--
--#
--# Console display driver support
--#
--# CONFIG_VGA_CONSOLE is not set
--CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
--
--#
--# Sound
--#
--# CONFIG_SOUND is not set
--
--#
--# USB support
--#
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
--# USB Gadget Support
--#
--# CONFIG_USB_GADGET is not set
--
--#
--# MMC/SD Card support
--#
--# CONFIG_MMC is not set
--
--#
--# InfiniBand support
--#
--# CONFIG_INFINIBAND is not set
--
--#
--# File systems
--#
--CONFIG_EXT2_FS=y
--# CONFIG_EXT2_FS_XATTR is not set
--# CONFIG_EXT3_FS is not set
--# CONFIG_JBD is not set
--# CONFIG_REISERFS_FS is not set
--# CONFIG_JFS_FS is not set
--# CONFIG_XFS_FS is not set
--# CONFIG_MINIX_FS is not set
--# CONFIG_ROMFS_FS is not set
--# CONFIG_QUOTA is not set
--CONFIG_DNOTIFY=y
--# CONFIG_AUTOFS_FS is not set
--# CONFIG_AUTOFS4_FS is not set
--
--#
--# CD-ROM/DVD Filesystems
--#
--# CONFIG_ISO9660_FS is not set
--# CONFIG_UDF_FS is not set
--
--#
--# DOS/FAT/NT Filesystems
--#
--# CONFIG_MSDOS_FS is not set
--# CONFIG_VFAT_FS is not set
--# CONFIG_NTFS_FS is not set
--
--#
--# Pseudo filesystems
--#
--CONFIG_PROC_FS=y
--CONFIG_PROC_KCORE=y
--CONFIG_SYSFS=y
--# CONFIG_DEVFS_FS is not set
--CONFIG_DEVPTS_FS_XATTR=y
--CONFIG_DEVPTS_FS_SECURITY=y
--# CONFIG_TMPFS is not set
--# CONFIG_HUGETLB_PAGE is not set
--CONFIG_RAMFS=y
--
--#
--# Miscellaneous filesystems
--#
--# CONFIG_ADFS_FS is not set
--# CONFIG_AFFS_FS is not set
--# CONFIG_HFS_FS is not set
--# CONFIG_HFSPLUS_FS is not set
--# CONFIG_BEFS_FS is not set
--# CONFIG_BFS_FS is not set
--# CONFIG_EFS_FS is not set
--# CONFIG_CRAMFS is not set
--# CONFIG_VXFS_FS is not set
--# CONFIG_HPFS_FS is not set
--# CONFIG_QNX4FS_FS is not set
--# CONFIG_SYSV_FS is not set
--# CONFIG_UFS_FS is not set
--
--#
--# Network File Systems
--#
--CONFIG_NFS_FS=y
--# CONFIG_NFS_V3 is not set
--# CONFIG_NFS_V4 is not set
--# CONFIG_NFS_DIRECTIO is not set
--CONFIG_NFSD=y
--# CONFIG_NFSD_V3 is not set
--# CONFIG_NFSD_TCP is not set
--CONFIG_ROOT_NFS=y
--CONFIG_LOCKD=y
--CONFIG_EXPORTFS=y
--CONFIG_SUNRPC=y
--# CONFIG_RPCSEC_GSS_KRB5 is not set
--# CONFIG_RPCSEC_GSS_SPKM3 is not set
--# CONFIG_SMB_FS is not set
--# CONFIG_CIFS is not set
--# CONFIG_NCP_FS is not set
--# CONFIG_CODA_FS is not set
--# CONFIG_AFS_FS is not set
--
--#
--# Partition Types
--#
--# CONFIG_PARTITION_ADVANCED is not set
--CONFIG_MSDOS_PARTITION=y
--
--#
--# Native Language Support
--#
--# CONFIG_NLS is not set
--
--#
--# Profiling support
--#
--# CONFIG_PROFILING is not set
--
--#
--# Kernel hacking
--#
--# CONFIG_DEBUG_KERNEL is not set
--CONFIG_CROSSCOMPILE=y
--CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0"
--
--#
--# Security options
--#
--CONFIG_KEYS=y
--CONFIG_KEYS_DEBUG_PROC_KEYS=y
--# CONFIG_SECURITY is not set
--
--#
--# Cryptographic options
--#
--# CONFIG_CRYPTO is not set
--
--#
--# Hardware crypto devices
--#
--
--#
--# Library routines
--#
--# CONFIG_CRC_CCITT is not set
--# CONFIG_CRC32 is not set
--CONFIG_LIBCRC32C=m
--CONFIG_GENERIC_HARDIRQS=y
--CONFIG_GENERIC_IRQ_PROBE=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/pb1100_defconfig linux_HEAD/arch/mips/configs/pb1100_defconfig
---- linux-2.6.12/arch/mips/configs/pb1100_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/pb1100_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:08 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:25 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,55 +57,64 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+CONFIG_MIPS_PB1100=y
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--CONFIG_SOC_AU1100=y
--# CONFIG_SOC_AU1500 is not set
--# CONFIG_SOC_AU1550 is not set
--# CONFIG_MIPS_PB1000 is not set
--CONFIG_MIPS_PB1100=y
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1100=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_SWAP_IO_SPACE=y
- # CONFIG_AU1X00_USB_DEVICE is not set
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -112,8 +122,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -129,12 +139,21 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
- # CONFIG_PAGE_SIZE_64KB is not set
- CONFIG_CPU_HAS_PREFETCH=y
--# CONFIG_64BIT_PHYS_ADDR is not set
-+CONFIG_64BIT_PHYS_ADDR=y
- # CONFIG_CPU_ADVANCED is not set
- CONFIG_CPU_HAS_LLSC=y
- CONFIG_CPU_HAS_SYNC=y
-@@ -170,6 +189,7 @@ CONFIG_PCMCIA=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -187,8 +207,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
--CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
- # CONFIG_MTD_REDBOOT_PARTS is not set
- # CONFIG_MTD_CMDLINE_PARTS is not set
-
-@@ -232,9 +252,7 @@ CONFIG_MTD_CFI_UTIL=y
- #
- # CONFIG_MTD_COMPLEX_MAPPINGS is not set
- # CONFIG_MTD_PHYSMAP is not set
--CONFIG_MTD_PB1100=y
--CONFIG_MTD_PB1500_BOOT=y
--CONFIG_MTD_PB1500_USER=y
-+CONFIG_MTD_ALCHEMY=y
-
- #
- # Self-contained MTD device drivers
-@@ -328,7 +346,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -406,7 +423,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -481,18 +497,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -502,6 +506,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -533,7 +547,8 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Watchdog Cards
- #
- # CONFIG_WATCHDOG is not set
--CONFIG_RTC=y
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
- # CONFIG_DTLK is not set
- # CONFIG_R3964 is not set
-
-@@ -549,6 +564,10 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -582,7 +601,6 @@ CONFIG_SYNCLINK_CS=m
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -592,12 +610,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -636,6 +651,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -771,7 +790,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -794,6 +815,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/pb1500_defconfig linux_HEAD/arch/mips/configs/pb1500_defconfig
---- linux-2.6.12/arch/mips/configs/pb1500_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/pb1500_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:09 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:25 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,63 +57,72 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+CONFIG_MIPS_PB1500=y
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--# CONFIG_SOC_AU1100 is not set
--CONFIG_SOC_AU1500=y
--# CONFIG_SOC_AU1550 is not set
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--CONFIG_MIPS_PB1500=y
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
--CONFIG_DMA_COHERENT=y
-+CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1500=y
-+CONFIG_SOC_AU1X00=y
- # CONFIG_AU1X00_USB_DEVICE is not set
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -128,6 +138,15 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -177,6 +196,7 @@ CONFIG_PCCARD_NONSTATIC=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -192,7 +212,76 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- # Memory Technology Devices (MTD)
- #
--# CONFIG_MTD is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_CFI_AMDSTD_RETRY=0
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+CONFIG_MTD_ALCHEMY=y
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_PMC551 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLKMTD is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+# CONFIG_MTD_NAND is not set
-
- #
- # Parallel port support
-@@ -323,7 +412,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -401,7 +489,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -437,6 +524,7 @@ CONFIG_MIPS_AU1X00_ENET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -513,19 +601,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -535,6 +610,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- # CONFIG_VT is not set
-@@ -554,6 +640,7 @@ CONFIG_SERIAL_AU1X00=y
- CONFIG_SERIAL_AU1X00_CONSOLE=y
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -585,6 +672,11 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -612,7 +704,6 @@ CONFIG_SYNCLINK_CS=m
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -622,13 +713,9 @@ CONFIG_SYNCLINK_CS=m
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -667,6 +754,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -712,6 +803,8 @@ CONFIG_RAMFS=y
- # CONFIG_BEFS_FS is not set
- # CONFIG_BFS_FS is not set
- # CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+# CONFIG_JFFS2_FS is not set
- CONFIG_CRAMFS=m
- # CONFIG_VXFS_FS is not set
- # CONFIG_HPFS_FS is not set
-@@ -800,7 +893,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -823,6 +918,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/pb1550_defconfig linux_HEAD/arch/mips/configs/pb1550_defconfig
---- linux-2.6.12/arch/mips/configs/pb1550_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/pb1550_defconfig 2005-07-07 11:22:48.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:09 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:26 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,63 +57,72 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+CONFIG_MIPS_PB1550=y
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--CONFIG_SOC_AU1X00=y
--# CONFIG_SOC_AU1000 is not set
--# CONFIG_SOC_AU1100 is not set
--# CONFIG_SOC_AU1500 is not set
--CONFIG_SOC_AU1550=y
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--CONFIG_MIPS_PB1550=y
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
--CONFIG_DMA_COHERENT=y
-+CONFIG_DMA_NONCOHERENT=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_SOC_AU1550=y
-+CONFIG_SOC_AU1X00=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -128,6 +138,15 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -177,6 +196,7 @@ CONFIG_PCCARD_NONSTATIC=m
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
- CONFIG_TRAD_SIGNALS=y
-+# CONFIG_PM is not set
-
- #
- # Device Drivers
-@@ -192,7 +212,76 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- # Memory Technology Devices (MTD)
- #
--# CONFIG_MTD is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_CFI_AMDSTD_RETRY=0
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+CONFIG_MTD_ALCHEMY=y
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_PMC551 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLKMTD is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+# CONFIG_MTD_NAND is not set
-
- #
- # Parallel port support
-@@ -323,7 +412,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -401,7 +489,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -437,6 +524,7 @@ CONFIG_MIPS_AU1X00_ENET=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -505,19 +593,6 @@ CONFIG_INPUT_EVDEV=y
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -527,6 +602,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+# CONFIG_SERIO_I8042 is not set
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- # CONFIG_VT is not set
-@@ -546,6 +632,7 @@ CONFIG_SERIAL_AU1X00=y
- CONFIG_SERIAL_AU1X00_CONSOLE=y
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -577,6 +664,11 @@ CONFIG_SYNCLINK_CS=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -604,7 +696,6 @@ CONFIG_SYNCLINK_CS=m
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -614,13 +705,9 @@ CONFIG_SYNCLINK_CS=m
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -659,6 +746,10 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -704,6 +795,8 @@ CONFIG_RAMFS=y
- # CONFIG_BEFS_FS is not set
- # CONFIG_BFS_FS is not set
- # CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+# CONFIG_JFFS2_FS is not set
- CONFIG_CRAMFS=m
- # CONFIG_VXFS_FS is not set
- # CONFIG_HPFS_FS is not set
-@@ -792,7 +885,9 @@ CONFIG_NLS_DEFAULT="iso8859-1"
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -815,6 +910,7 @@ CONFIG_CRYPTO_NULL=y
- # CONFIG_CRYPTO_SHA256 is not set
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- # CONFIG_CRYPTO_DES is not set
- # CONFIG_CRYPTO_BLOWFISH is not set
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/rm200_defconfig linux_HEAD/arch/mips/configs/rm200_defconfig
---- linux-2.6.12/arch/mips/configs/rm200_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/rm200_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:09 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:26 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -26,14 +24,16 @@ CONFIG_BSD_PROCESS_ACCT=y
- # CONFIG_BSD_PROCESS_ACCT_V3 is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
--# CONFIG_HOTPLUG is not set
-+CONFIG_HOTPLUG=y
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
- CONFIG_IKCONFIG_PROC=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -43,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -58,33 +59,54 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- CONFIG_SNI_RM200_PCI=y
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-@@ -93,7 +115,10 @@ CONFIG_ARC=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_GENERIC_ISA_DMA=y
- CONFIG_I8259=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_ARC32=y
- CONFIG_BOOT_ELF32=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -105,8 +130,8 @@ CONFIG_ARC_PROMLIB=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -122,6 +147,17 @@ CONFIG_CPU_R4X00=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -136,6 +172,7 @@ CONFIG_CPU_HAS_SYNC=y
- #
- # Bus options (PCI, PCMCIA, EISA, ISA, TC)
- #
-+CONFIG_HW_HAS_EISA=y
- CONFIG_HW_HAS_PCI=y
- CONFIG_PCI=y
- CONFIG_PCI_LEGACY_PROC=y
-@@ -150,11 +187,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--CONFIG_PCMCIA_PROBE=y
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -175,7 +207,7 @@ CONFIG_TRAD_SIGNALS=y
- #
- CONFIG_STANDALONE=y
- CONFIG_PREVENT_FIRMWARE_BUILD=y
--# CONFIG_FW_LOADER is not set
-+CONFIG_FW_LOADER=m
-
- #
- # Memory Technology Devices (MTD)
-@@ -187,11 +219,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- #
- CONFIG_PARPORT=m
- CONFIG_PARPORT_PC=m
--CONFIG_PARPORT_PC_CML1=m
- CONFIG_PARPORT_SERIAL=m
- # CONFIG_PARPORT_PC_FIFO is not set
- # CONFIG_PARPORT_PC_SUPERIO is not set
--# CONFIG_PARPORT_OTHER is not set
-+CONFIG_PARPORT_NOT_PC=y
-+# CONFIG_PARPORT_GSC is not set
- CONFIG_PARPORT_1284=y
-
- #
-@@ -203,7 +235,6 @@ CONFIG_PARPORT_1284=y
- # Block devices
- #
- CONFIG_BLK_DEV_FD=m
--# CONFIG_BLK_DEV_XD is not set
- CONFIG_PARIDE=m
- CONFIG_PARIDE_PARPORT=m
-
-@@ -296,17 +327,15 @@ CONFIG_SCSI_CONSTANTS=y
- #
- CONFIG_SCSI_SPI_ATTRS=y
- # CONFIG_SCSI_FC_ATTRS is not set
--# CONFIG_SCSI_ISCSI_ATTRS is not set
-+CONFIG_SCSI_ISCSI_ATTRS=m
-
- #
- # SCSI low-level drivers
- #
- # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
- # CONFIG_SCSI_3W_9XXX is not set
--# CONFIG_SCSI_7000FASST is not set
- # CONFIG_SCSI_ACARD is not set
- # CONFIG_SCSI_AHA152X is not set
--# CONFIG_SCSI_AHA1542 is not set
- # CONFIG_SCSI_AACRAID is not set
- # CONFIG_SCSI_AIC7XXX is not set
- # CONFIG_SCSI_AIC7XXX_OLD is not set
-@@ -317,13 +346,9 @@ CONFIG_MEGARAID_NEWGEN=y
- CONFIG_MEGARAID_MM=m
- CONFIG_MEGARAID_MAILBOX=m
- # CONFIG_SCSI_SATA is not set
--# CONFIG_SCSI_BUSLOGIC is not set
- # CONFIG_SCSI_DMX3191D is not set
- # CONFIG_SCSI_DTC3280 is not set
--# CONFIG_SCSI_EATA is not set
--# CONFIG_SCSI_EATA_PIO is not set
- # CONFIG_SCSI_FUTURE_DOMAIN is not set
--# CONFIG_SCSI_GDTH is not set
- # CONFIG_SCSI_GENERIC_NCR5380 is not set
- # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
- # CONFIG_SCSI_IPS is not set
-@@ -343,7 +368,6 @@ CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
- # CONFIG_SCSI_PAS16 is not set
- # CONFIG_SCSI_PSI240I is not set
- # CONFIG_SCSI_QLOGIC_FAS is not set
--# CONFIG_SCSI_QLOGIC_ISP is not set
- # CONFIG_SCSI_QLOGIC_FC is not set
- # CONFIG_SCSI_QLOGIC_1280 is not set
- CONFIG_SCSI_QLA2XXX=y
-@@ -352,11 +376,11 @@ CONFIG_SCSI_QLA2XXX=y
- # CONFIG_SCSI_QLA2300 is not set
- # CONFIG_SCSI_QLA2322 is not set
- # CONFIG_SCSI_QLA6312 is not set
-+# CONFIG_SCSI_LPFC is not set
- # CONFIG_SCSI_SYM53C416 is not set
- # CONFIG_SCSI_DC395x is not set
- # CONFIG_SCSI_DC390T is not set
- # CONFIG_SCSI_T128 is not set
--# CONFIG_SCSI_U14_34F is not set
- # CONFIG_SCSI_NSP32 is not set
- # CONFIG_SCSI_DEBUG is not set
-
-@@ -383,6 +407,8 @@ CONFIG_BLK_DEV_DM=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_ZERO=m
-+CONFIG_DM_MULTIPATH=m
-+CONFIG_DM_MULTIPATH_EMC=m
-
- #
- # Fusion MPT device support
-@@ -409,7 +435,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=m
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=m
- CONFIG_UNIX=y
- CONFIG_NET_KEY=m
- CONFIG_INET=y
-@@ -515,7 +540,7 @@ CONFIG_IP_NF_ARPFILTER=m
- CONFIG_IP_NF_ARP_MANGLE=m
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- CONFIG_IP6_NF_QUEUE=m
- CONFIG_IP6_NF_IPTABLES=m
-@@ -566,7 +591,7 @@ CONFIG_BRIDGE_EBT_MARK_T=m
- CONFIG_BRIDGE_EBT_REDIRECT=m
- CONFIG_BRIDGE_EBT_SNAT=m
- CONFIG_BRIDGE_EBT_LOG=m
--# CONFIG_BRIDGE_EBT_ULOG is not set
-+CONFIG_BRIDGE_EBT_ULOG=m
- CONFIG_XFRM=y
- # CONFIG_XFRM_USER is not set
-
-@@ -610,6 +635,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -620,6 +646,7 @@ CONFIG_NET_CLS_U32=m
- # CONFIG_CLS_U32_MARK is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -645,8 +672,6 @@ CONFIG_ROSE=m
- CONFIG_MKISS=m
- CONFIG_6PACK=m
- CONFIG_BPQETHER=m
--# CONFIG_DMASCC is not set
--# CONFIG_SCC is not set
- # CONFIG_BAYCOM_SER_FDX is not set
- # CONFIG_BAYCOM_SER_HDX is not set
- # CONFIG_BAYCOM_PAR is not set
-@@ -659,7 +684,6 @@ CONFIG_DUMMY=m
- CONFIG_BONDING=m
- CONFIG_EQUALIZER=m
- CONFIG_TUN=m
--CONFIG_ETHERTAP=m
-
- #
- # ARCnet devices
-@@ -674,7 +698,6 @@ CONFIG_MII=y
- # CONFIG_HAPPYMEAL is not set
- # CONFIG_SUNGEM is not set
- # CONFIG_NET_VENDOR_3COM is not set
--# CONFIG_LANCE is not set
- # CONFIG_NET_VENDOR_SMC is not set
- # CONFIG_NET_VENDOR_RACAL is not set
-
-@@ -695,7 +718,6 @@ CONFIG_NET_ISA=y
- # CONFIG_LP486E is not set
- # CONFIG_ETH16I is not set
- CONFIG_NE2000=m
--# CONFIG_ZNET is not set
- # CONFIG_SEEQ8005 is not set
- CONFIG_NET_PCI=y
- CONFIG_PCNET32=y
-@@ -735,6 +757,7 @@ CONFIG_EEPRO100=m
- # CONFIG_SK98LIN is not set
- CONFIG_VIA_VELOCITY=m
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -793,20 +816,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--CONFIG_SERIO_PARKBD=m
--# CONFIG_SERIO_PCIPS2 is not set
--CONFIG_SERIO_LIBPS2=y
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- CONFIG_INPUT_KEYBOARD=y
-@@ -827,6 +836,18 @@ CONFIG_MOUSE_PS2=y
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_PARKBD=m
-+# CONFIG_SERIO_PCIPS2 is not set
-+CONFIG_SERIO_LIBPS2=y
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -850,6 +871,7 @@ CONFIG_SERIAL_8250_RSA=y
- # Non-8250 serial port support
- #
- CONFIG_SERIAL_CORE=m
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -880,6 +902,11 @@ CONFIG_RTC=m
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -919,7 +946,6 @@ CONFIG_W1_SMEM=m
- CONFIG_VGA_CONSOLE=y
- # CONFIG_MDA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -929,6 +955,8 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
- CONFIG_USB=m
- # CONFIG_USB_DEBUG is not set
-
-@@ -939,8 +967,6 @@ CONFIG_USB_DEVICEFS=y
- # CONFIG_USB_BANDWIDTH is not set
- # CONFIG_USB_DYNAMIC_MINORS is not set
- # CONFIG_USB_OTG is not set
--CONFIG_USB_ARCH_HAS_HCD=y
--CONFIG_USB_ARCH_HAS_OHCI=y
-
- #
- # USB Host Controller Drivers
-@@ -949,6 +975,8 @@ CONFIG_USB_EHCI_HCD=m
- # CONFIG_USB_EHCI_SPLIT_ISO is not set
- # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
- CONFIG_USB_OHCI_HCD=m
-+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
-+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
- CONFIG_USB_UHCI_HCD=m
- # CONFIG_USB_SL811_HCD is not set
-
-@@ -964,11 +992,10 @@ CONFIG_USB_PRINTER=m
- #
- CONFIG_USB_STORAGE=m
- # CONFIG_USB_STORAGE_DEBUG is not set
--# CONFIG_USB_STORAGE_RW_DETECT is not set
- CONFIG_USB_STORAGE_DATAFAB=y
- CONFIG_USB_STORAGE_FREECOM=y
- CONFIG_USB_STORAGE_DPCM=y
--CONFIG_USB_STORAGE_HP8200e=y
-+# CONFIG_USB_STORAGE_USBAT is not set
- CONFIG_USB_STORAGE_SDDR09=y
- CONFIG_USB_STORAGE_SDDR55=y
- CONFIG_USB_STORAGE_JUMPSHOT=y
-@@ -1045,6 +1072,7 @@ CONFIG_USB_CDCETHER=y
- # USB Network Adapters
- #
- CONFIG_USB_AX8817X=y
-+CONFIG_USB_MON=m
-
- #
- # USB port drivers
-@@ -1056,9 +1084,11 @@ CONFIG_USB_USS720=m
- #
- CONFIG_USB_SERIAL=m
- CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRPRIME=m
- CONFIG_USB_SERIAL_BELKIN=m
- CONFIG_USB_SERIAL_WHITEHEAT=m
- CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+# CONFIG_USB_SERIAL_CP2101 is not set
- CONFIG_USB_SERIAL_CYPRESS_M8=m
- CONFIG_USB_SERIAL_EMPEG=m
- CONFIG_USB_SERIAL_FTDI_SIO=m
-@@ -1087,6 +1117,7 @@ CONFIG_USB_SERIAL_KLSI=m
- CONFIG_USB_SERIAL_KOBIL_SCT=m
- CONFIG_USB_SERIAL_MCT_U232=m
- CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_HP4X=m
- CONFIG_USB_SERIAL_SAFE=m
- CONFIG_USB_SERIAL_SAFE_PADDED=y
- # CONFIG_USB_SERIAL_TI is not set
-@@ -1109,6 +1140,7 @@ CONFIG_USB_CYTHERM=m
- CONFIG_USB_PHIDGETKIT=m
- CONFIG_USB_PHIDGETSERVO=m
- # CONFIG_USB_IDMOUSE is not set
-+CONFIG_USB_SISUSBVGA=m
- CONFIG_USB_TEST=m
-
- #
-@@ -1150,7 +1182,12 @@ CONFIG_REISERFS_FS_POSIX_ACL=y
- CONFIG_REISERFS_FS_SECURITY=y
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- CONFIG_XFS_SECURITY=y
-@@ -1328,7 +1365,9 @@ CONFIG_NLS_UTF8=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -1351,6 +1390,7 @@ CONFIG_CRYPTO_SHA1=m
- CONFIG_CRYPTO_SHA256=m
- CONFIG_CRYPTO_SHA512=m
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=m
- CONFIG_CRYPTO_BLOWFISH=m
- CONFIG_CRYPTO_TWOFISH=m
-@@ -1365,7 +1405,7 @@ CONFIG_CRYPTO_ANUBIS=m
- CONFIG_CRYPTO_DEFLATE=m
- CONFIG_CRYPTO_MICHAEL_MIC=m
- # CONFIG_CRYPTO_CRC32C is not set
--CONFIG_CRYPTO_TEST=m
-+# CONFIG_CRYPTO_TEST is not set
-
- #
- # Hardware crypto devices
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/sb1250-swarm_defconfig linux_HEAD/arch/mips/configs/sb1250-swarm_defconfig
---- linux-2.6.12/arch/mips/configs/sb1250-swarm_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/sb1250-swarm_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:10 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:27 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_LOCK_KERNEL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,16 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=15
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
-+CONFIG_CPUSETS=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,32 +59,44 @@ CONFIG_STOP_MACHINE=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--CONFIG_SIBYTE_SB1xxx_SOC=y
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
- CONFIG_SIBYTE_SWARM=y
- # CONFIG_SIBYTE_SENTOSA is not set
- # CONFIG_SIBYTE_RHONE is not set
-@@ -91,9 +105,11 @@ CONFIG_SIBYTE_SWARM=y
- # CONFIG_SIBYTE_LITTLESUR is not set
- # CONFIG_SIBYTE_CRHINE is not set
- # CONFIG_SIBYTE_CRHONE is not set
--# CONFIG_SIBYTE_UNKNOWN is not set
--CONFIG_SIBYTE_BOARD=y
-+# CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_SIBYTE_SB1250=y
-+CONFIG_SIBYTE_SB1xxx_SOC=y
- CONFIG_CPU_SB1_PASS_1=y
- # CONFIG_CPU_SB1_PASS_2_1250 is not set
- # CONFIG_CPU_SB1_PASS_2_2 is not set
-@@ -107,13 +123,14 @@ CONFIG_SIBYTE_CFE=y
- # CONFIG_SIBYTE_BUS_WATCHER is not set
- # CONFIG_SIBYTE_SB1250_PROF is not set
- # CONFIG_SIBYTE_TBPROF is not set
--# CONFIG_SNI_RM200_PCI is not set
--# CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_COHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_SWAP_IO_SPACE=y
- CONFIG_BOOT_ELF32=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -121,8 +138,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -138,6 +155,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- CONFIG_CPU_SB1=y
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+# CONFIG_MIPS32 is not set
-+CONFIG_MIPS64=y
-+CONFIG_64BIT=y
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -145,12 +173,9 @@ CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_SIBYTE_DMA_PAGEOPS is not set
- CONFIG_CPU_HAS_PREFETCH=y
- CONFIG_SB1_PASS_1_WORKAROUNDS=y
--# CONFIG_64BIT_PHYS_ADDR is not set
--# CONFIG_CPU_ADVANCED is not set
- CONFIG_CPU_HAS_LLSC=y
- CONFIG_CPU_HAS_LLDSCD=y
- CONFIG_CPU_HAS_SYNC=y
--# CONFIG_HIGHMEM is not set
- CONFIG_SMP=y
- CONFIG_NR_CPUS=2
- # CONFIG_PREEMPT is not set
-@@ -170,10 +195,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -183,7 +204,12 @@ CONFIG_MMU=y
- #
- CONFIG_BINFMT_ELF=y
- # CONFIG_BINFMT_MISC is not set
--CONFIG_TRAD_SIGNALS=y
-+# CONFIG_BUILD_ELF64 is not set
-+CONFIG_MIPS32_COMPAT=y
-+CONFIG_COMPAT=y
-+CONFIG_MIPS32_O32=y
-+# CONFIG_MIPS32_N32 is not set
-+CONFIG_BINFMT_ELF32=y
-
- #
- # Device Drivers
-@@ -227,7 +253,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16
- CONFIG_BLK_DEV_RAM_SIZE=9220
- CONFIG_BLK_DEV_INITRD=y
- CONFIG_INITRAMFS_SOURCE=""
--# CONFIG_LBD is not set
- CONFIG_CDROM_PKTCDVD=m
- CONFIG_CDROM_PKTCDVD_BUFFERS=8
- # CONFIG_CDROM_PKTCDVD_WCACHE is not set
-@@ -263,7 +288,7 @@ CONFIG_BLK_DEV_IDEFLOPPY=y
- #
- CONFIG_IDE_GENERIC=y
- # CONFIG_BLK_DEV_IDEPCI is not set
--CONFIG_BLK_DEV_IDE_SWARM=y
-+# CONFIG_BLK_DEV_IDE_SWARM is not set
- # CONFIG_IDE_ARM is not set
- # CONFIG_BLK_DEV_IDEDMA is not set
- # CONFIG_IDEDMA_AUTO is not set
-@@ -303,7 +328,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -365,7 +389,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -401,6 +424,7 @@ CONFIG_MII=y
- CONFIG_NET_SB1250_MAC=y
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -445,25 +469,15 @@ CONFIG_NET_SB1250_MAC=y
- # CONFIG_INPUT is not set
-
- #
--# Userland interfaces
--#
--
--#
--# Input I/O drivers
-+# Hardware I/O ports
- #
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
- CONFIG_SERIO=y
- # CONFIG_SERIO_I8042 is not set
- CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
- # CONFIG_SERIO_PCIPS2 is not set
- # CONFIG_SERIO_LIBPS2 is not set
- CONFIG_SERIO_RAW=m
--
--#
--# Input Device Drivers
--#
-+# CONFIG_GAMEPORT is not set
-
- #
- # Character devices
-@@ -474,9 +488,10 @@ CONFIG_SERIAL_NONSTANDARD=y
- # CONFIG_CYCLADES is not set
- # CONFIG_MOXA_SMARTIO is not set
- # CONFIG_ISI is not set
--# CONFIG_SYNCLINK is not set
- # CONFIG_SYNCLINKMP is not set
- # CONFIG_N_HDLC is not set
-+# CONFIG_SPECIALIX is not set
-+# CONFIG_SX is not set
- # CONFIG_STALDRV is not set
- CONFIG_SIBYTE_SB1250_DUART=y
- CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
-@@ -489,6 +504,7 @@ CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
- #
- # Non-8250 serial port support
- #
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -515,6 +531,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -542,7 +563,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -552,13 +572,9 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -588,6 +604,10 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -649,7 +669,6 @@ CONFIG_NFS_V3=y
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
- CONFIG_LOCKD_V4=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_RPCSEC_GSS_KRB5 is not set
- # CONFIG_RPCSEC_GSS_SPKM3 is not set
-@@ -678,7 +697,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=15
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
- # CONFIG_SB1XXX_CORELIS is not set
-@@ -702,6 +723,7 @@ CONFIG_CRYPTO_SHA1=y
- CONFIG_CRYPTO_SHA256=y
- CONFIG_CRYPTO_SHA512=y
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=y
- CONFIG_CRYPTO_BLOWFISH=y
- CONFIG_CRYPTO_TWOFISH=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/sead_defconfig linux_HEAD/arch/mips/configs/sead_defconfig
---- linux-2.6.12/arch/mips/configs/sead_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/sead_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:10 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:27 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,22 +11,25 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
- #
- CONFIG_LOCALVERSION=""
--CONFIG_SWAP=y
--# CONFIG_SYSVIPC is not set
-+# CONFIG_SWAP is not set
-+CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -39,6 +39,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -48,39 +49,63 @@ CONFIG_CC_ALIGN_JUMPS=0
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- CONFIG_MIPS_SEAD=y
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_BOARDS_GEN=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-@@ -88,8 +113,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--CONFIG_CPU_MIPS32=y
--# CONFIG_CPU_MIPS64 is not set
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -105,6 +130,16 @@ CONFIG_CPU_MIPS32=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -127,10 +162,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -179,9 +210,7 @@ CONFIG_BLK_DEV_RAM_SIZE=18432
- CONFIG_BLK_DEV_INITRD=y
- CONFIG_INITRAMFS_SOURCE=""
- # CONFIG_LBD is not set
--CONFIG_CDROM_PKTCDVD=y
--CONFIG_CDROM_PKTCDVD_BUFFERS=8
--# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-
- #
- # IO Schedulers
-@@ -237,47 +266,18 @@ CONFIG_IOSCHED_CFQ=y
- #
- # Input device support
- #
--CONFIG_INPUT=y
-+# CONFIG_INPUT is not set
-
- #
--# Userland interfaces
--#
--CONFIG_INPUT_MOUSEDEV=y
--CONFIG_INPUT_MOUSEDEV_PSAUX=y
--CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
--CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
--# CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_TSDEV is not set
--# CONFIG_INPUT_EVDEV is not set
--# CONFIG_INPUT_EVBUG is not set
--
--#
--# Input I/O drivers
-+# Hardware I/O ports
- #
-+# CONFIG_SERIO is not set
- # CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--
--#
--# Input Device Drivers
--#
--# CONFIG_INPUT_KEYBOARD is not set
--# CONFIG_INPUT_MOUSE is not set
--# CONFIG_INPUT_JOYSTICK is not set
--# CONFIG_INPUT_TOUCHSCREEN is not set
--# CONFIG_INPUT_MISC is not set
-
- #
- # Character devices
- #
--CONFIG_VT=y
--CONFIG_VT_CONSOLE=y
--CONFIG_HW_CONSOLE=y
-+# CONFIG_VT is not set
- # CONFIG_SERIAL_NONSTANDARD is not set
-
- #
-@@ -293,7 +293,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
--# CONFIG_UNIX98_PTYS is not set
-+CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-
-@@ -318,6 +318,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -346,13 +350,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_FB is not set
-
- #
--# Console display driver support
--#
--# CONFIG_VGA_CONSOLE is not set
--CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
--
--#
- # Sound
- #
- # CONFIG_SOUND is not set
-@@ -364,10 +361,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -386,15 +379,15 @@ CONFIG_DUMMY_CONSOLE=y
- # File systems
- #
- CONFIG_EXT2_FS=y
--CONFIG_EXT2_FS_XATTR=y
--CONFIG_EXT2_FS_POSIX_ACL=y
--CONFIG_EXT2_FS_SECURITY=y
-+# CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT3_FS is not set
- # CONFIG_JBD is not set
--CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
--CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -423,6 +416,7 @@ CONFIG_PROC_FS=y
- CONFIG_PROC_KCORE=y
- CONFIG_SYSFS=y
- # CONFIG_DEVFS_FS is not set
-+# CONFIG_DEVPTS_FS_XATTR is not set
- # CONFIG_TMPFS is not set
- # CONFIG_HUGETLB_PAGE is not set
- CONFIG_RAMFS=y
-@@ -447,8 +441,18 @@ CONFIG_RAMFS=y
- #
- # Partition Types
- #
--# CONFIG_PARTITION_ADVANCED is not set
--CONFIG_MSDOS_PARTITION=y
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+# CONFIG_MSDOS_PARTITION is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-
- #
- # Native Language Support
-@@ -463,15 +467,16 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
- #
- # Security options
- #
--CONFIG_KEYS=y
--CONFIG_KEYS_DEBUG_PROC_KEYS=y
-+# CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
-
- #
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/tb0226_defconfig linux_HEAD/arch/mips/configs/tb0226_defconfig
---- linux-2.6.12/arch/mips/configs/tb0226_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/tb0226_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:12 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:28 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,54 +57,78 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--# CONFIG_CASIO_E55 is not set
--# CONFIG_IBM_WORKPAD is not set
--CONFIG_TANBAC_TB0226=y
--# CONFIG_TANBAC_TB0229 is not set
--# CONFIG_VICTOR_MPC30X is not set
--# CONFIG_ZAO_CAPCELLA is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+# CONFIG_CASIO_E55 is not set
-+# CONFIG_IBM_WORKPAD is not set
-+CONFIG_TANBAC_TB0226=y
-+# CONFIG_TANBAC_TB0229 is not set
-+# CONFIG_VICTOR_MPC30X is not set
-+# CONFIG_ZAO_CAPCELLA is not set
-+# CONFIG_GPIO_VR41XX is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -119,6 +144,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -140,10 +176,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -295,7 +327,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=m
- CONFIG_UNIX=y
- # CONFIG_NET_KEY is not set
- CONFIG_INET=y
-@@ -303,6 +334,7 @@ CONFIG_IP_MULTICAST=y
- CONFIG_IP_ADVANCED_ROUTER=y
- CONFIG_IP_MULTIPLE_TABLES=y
- CONFIG_IP_ROUTE_MULTIPATH=y
-+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
- CONFIG_IP_ROUTE_VERBOSE=y
- CONFIG_IP_PNP=y
- # CONFIG_IP_PNP_DHCP is not set
-@@ -361,7 +393,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -430,18 +461,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -451,6 +470,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -471,6 +500,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -496,6 +526,10 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -523,8 +557,14 @@ CONFIG_LEGACY_PTY_COUNT=256
- # Graphics support
- #
- CONFIG_FB=y
-+# CONFIG_FB_CFB_FILLRECT is not set
-+# CONFIG_FB_CFB_COPYAREA is not set
-+# CONFIG_FB_CFB_IMAGEBLIT is not set
-+# CONFIG_FB_SOFT_CURSOR is not set
-+# CONFIG_FB_MACMODES is not set
- # CONFIG_FB_MODE_HELPERS is not set
- # CONFIG_FB_TILEBLITTING is not set
-+# CONFIG_FB_S1D13XXX is not set
- # CONFIG_FB_VIRTUAL is not set
-
- #
-@@ -562,10 +602,6 @@ CONFIG_SOUND=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -589,6 +625,10 @@ CONFIG_EXT2_FS=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- CONFIG_ROMFS_FS=m
-@@ -731,7 +771,9 @@ CONFIG_NLS_ISO8859_1=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/tb0229_defconfig linux_HEAD/arch/mips/configs/tb0229_defconfig
---- linux-2.6.12/arch/mips/configs/tb0229_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/tb0229_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:12 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:28 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,57 +57,80 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--# CONFIG_CASIO_E55 is not set
--# CONFIG_IBM_WORKPAD is not set
--# CONFIG_TANBAC_TB0226 is not set
--CONFIG_TANBAC_TB0229=y
--CONFIG_TANBAC_TB0219=y
--# CONFIG_VICTOR_MPC30X is not set
--# CONFIG_ZAO_CAPCELLA is not set
--CONFIG_PCI_VR41XX=y
--# CONFIG_VRC4173 is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+# CONFIG_CASIO_E55 is not set
-+# CONFIG_IBM_WORKPAD is not set
-+# CONFIG_TANBAC_TB0226 is not set
-+CONFIG_TANBAC_TB0229=y
-+# CONFIG_VICTOR_MPC30X is not set
-+# CONFIG_ZAO_CAPCELLA is not set
-+CONFIG_PCI_VR41XX=y
-+# CONFIG_GPIO_VR41XX is not set
-+# CONFIG_VRC4173 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -122,6 +146,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -145,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
- # CONFIG_HOTPLUG_PCI is not set
-@@ -256,7 +287,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- # CONFIG_PACKET_MMAP is not set
--CONFIG_NETLINK_DEV=m
- CONFIG_UNIX=y
- # CONFIG_NET_KEY is not set
- CONFIG_INET=y
-@@ -264,6 +294,7 @@ CONFIG_IP_MULTICAST=y
- CONFIG_IP_ADVANCED_ROUTER=y
- CONFIG_IP_MULTIPLE_TABLES=y
- CONFIG_IP_ROUTE_MULTIPATH=y
-+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
- CONFIG_IP_ROUTE_VERBOSE=y
- CONFIG_IP_PNP=y
- # CONFIG_IP_PNP_DHCP is not set
-@@ -323,7 +354,6 @@ CONFIG_DUMMY=m
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -378,6 +408,7 @@ CONFIG_EEPRO100=y
- # CONFIG_SK98LIN is not set
- # CONFIG_VIA_VELOCITY is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-
- #
- # Ethernet (10000 Mbit)
-@@ -444,19 +475,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -466,6 +484,17 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_PCIPS2 is not set
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -486,6 +515,8 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -504,6 +535,7 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_DTLK is not set
- # CONFIG_R3964 is not set
- # CONFIG_APPLICOM is not set
-+CONFIG_TANBAC_TB0219=y
-
- #
- # Ftape, the floppy tape device driver
-@@ -512,6 +544,11 @@ CONFIG_LEGACY_PTY_COUNT=256
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -545,7 +582,6 @@ CONFIG_LEGACY_PTY_COUNT=256
- #
- # CONFIG_VGA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -555,13 +591,9 @@ CONFIG_DUMMY_CONSOLE=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -596,7 +628,12 @@ CONFIG_JFS_FS=m
- # CONFIG_JFS_SECURITY is not set
- # CONFIG_JFS_DEBUG is not set
- # CONFIG_JFS_STATISTICS is not set
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=y
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- # CONFIG_XFS_SECURITY is not set
-@@ -743,7 +780,9 @@ CONFIG_NLS_ISO8859_1=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE="mem=64M console=ttyS0,38400 ip=bootp root=/dev/nfs"
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/workpad_defconfig linux_HEAD/arch/mips/configs/workpad_defconfig
---- linux-2.6.12/arch/mips/configs/workpad_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/workpad_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:12 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:29 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,13 +23,15 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- # CONFIG_IKCONFIG is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -41,6 +41,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,55 +57,79 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--CONFIG_MACH_VR41XX=y
--# CONFIG_NEC_CMBVR4133 is not set
--# CONFIG_CASIO_E55 is not set
--CONFIG_IBM_WORKPAD=y
--# CONFIG_TANBAC_TB0226 is not set
--# CONFIG_TANBAC_TB0229 is not set
--# CONFIG_VICTOR_MPC30X is not set
--# CONFIG_ZAO_CAPCELLA is not set
--CONFIG_VRC4171=y
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+CONFIG_MACH_VR41XX=y
-+# CONFIG_PMC_YOSEMITE is not set
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_NEC_CMBVR4133 is not set
-+# CONFIG_CASIO_E55 is not set
-+CONFIG_IBM_WORKPAD=y
-+# CONFIG_TANBAC_TB0226 is not set
-+# CONFIG_TANBAC_TB0229 is not set
-+# CONFIG_VICTOR_MPC30X is not set
-+# CONFIG_ZAO_CAPCELLA is not set
-+# CONFIG_GPIO_VR41XX is not set
-+CONFIG_VRC4171=y
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_NONCOHERENT=y
-+# CONFIG_CPU_BIG_ENDIAN is not set
- CONFIG_CPU_LITTLE_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_MIPS_L1_CACHE_SHIFT=5
-
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- CONFIG_CPU_VR41XX=y
-@@ -120,6 +145,17 @@ CONFIG_CPU_VR41XX=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -140,11 +176,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--CONFIG_PCMCIA_PROBE=y
--
--#
- # PCI Hotplug Support
- #
-
-@@ -185,7 +216,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
- # Block devices
- #
- # CONFIG_BLK_DEV_FD is not set
--# CONFIG_BLK_DEV_XD is not set
- # CONFIG_BLK_DEV_COW_COMMON is not set
- # CONFIG_BLK_DEV_LOOP is not set
- # CONFIG_BLK_DEV_NBD is not set
-@@ -270,7 +300,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -330,7 +359,6 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
--# CONFIG_ETHERTAP is not set
-
- #
- # ARCnet devices
-@@ -343,7 +371,6 @@ CONFIG_NETDEVICES=y
- CONFIG_NET_ETHERNET=y
- # CONFIG_MII is not set
- # CONFIG_NET_VENDOR_3COM is not set
--# CONFIG_LANCE is not set
- # CONFIG_NET_VENDOR_SMC is not set
- # CONFIG_NET_VENDOR_RACAL is not set
- # CONFIG_AT1700 is not set
-@@ -408,18 +435,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- # CONFIG_INPUT_KEYBOARD is not set
-@@ -429,6 +444,16 @@ CONFIG_SERIO_RAW=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+# CONFIG_SERIO_LIBPS2 is not set
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -449,6 +474,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_VR41XX is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -487,6 +513,10 @@ CONFIG_WATCHDOG=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -521,7 +551,6 @@ CONFIG_WATCHDOG=y
- # CONFIG_VGA_CONSOLE is not set
- # CONFIG_MDA_CONSOLE is not set
- CONFIG_DUMMY_CONSOLE=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -535,10 +564,6 @@ CONFIG_DUMMY_CONSOLE=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -566,6 +591,10 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -657,7 +686,9 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/configs/yosemite_defconfig linux_HEAD/arch/mips/configs/yosemite_defconfig
---- linux-2.6.12/arch/mips/configs/yosemite_defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/configs/yosemite_defconfig 2005-07-07 11:22:49.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:49:13 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:29 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- # CONFIG_EXPERIMENTAL is not set
- CONFIG_CLEAN_COMPILE=y
- CONFIG_LOCK_KERNEL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -24,15 +22,18 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
- CONFIG_IKCONFIG_PROC=y
-+# CONFIG_CPUSETS is not set
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_ALL is not set
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +43,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -56,34 +58,63 @@ CONFIG_STOP_MACHINE=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
-+# CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
-+# CONFIG_MIPS_EV64120 is not set
-+# CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
-+# CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--CONFIG_PMC_YOSEMITE=y
--# CONFIG_HYPERTRANSPORT is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
-+# CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+CONFIG_PMC_YOSEMITE=y
- # CONFIG_SGI_IP22 is not set
--# CONFIG_SOC_AU1X00 is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_HYPERTRANSPORT is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_DMA_COHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_IRQ_CPU_RM7K=y
- CONFIG_IRQ_CPU_RM9K=y
-@@ -93,8 +124,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -110,6 +141,17 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
- # CONFIG_CPU_RM7000 is not set
- CONFIG_CPU_RM9000=y
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -132,6 +174,7 @@ CONFIG_HW_HAS_PCI=y
- CONFIG_PCI=y
- CONFIG_PCI_LEGACY_PROC=y
- CONFIG_PCI_NAMES=y
-+# CONFIG_PCI_DEBUG is not set
- CONFIG_MMU=y
-
- #
-@@ -140,10 +183,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -247,7 +286,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=m
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=m
- CONFIG_UNIX=y
- # CONFIG_NET_KEY is not set
- CONFIG_INET=y
-@@ -265,7 +303,14 @@ CONFIG_IP_PNP_BOOTP=y
- # CONFIG_INET_IPCOMP is not set
- CONFIG_INET_TUNNEL=m
- CONFIG_IP_TCPDIAG=m
--# CONFIG_IP_TCPDIAG_IPV6 is not set
-+CONFIG_IP_TCPDIAG_IPV6=y
-+CONFIG_IPV6=m
-+CONFIG_IPV6_PRIVACY=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_IPV6_TUNNEL=m
- # CONFIG_NETFILTER is not set
- CONFIG_XFRM=y
- CONFIG_XFRM_USER=m
-@@ -329,6 +374,7 @@ CONFIG_MII=y
- # CONFIG_R8169 is not set
- # CONFIG_SK98LIN is not set
- # CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
- CONFIG_TITAN_GE=y
-
- #
-@@ -371,20 +417,10 @@ CONFIG_TITAN_GE=y
- # CONFIG_INPUT is not set
-
- #
--# Userland interfaces
--#
--
-+# Hardware I/O ports
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
- # CONFIG_SERIO is not set
--# CONFIG_SERIO_I8042 is not set
--
--#
--# Input Device Drivers
--#
-+# CONFIG_GAMEPORT is not set
-
- #
- # Character devices
-@@ -405,6 +441,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
- #
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
- CONFIG_UNIX98_PTYS=y
- CONFIG_LEGACY_PTYS=y
- CONFIG_LEGACY_PTY_COUNT=256
-@@ -432,6 +469,10 @@ CONFIG_GEN_RTC_X=y
- # CONFIG_RAW_DRIVER is not set
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -459,7 +500,6 @@ CONFIG_GEN_RTC_X=y
- # Graphics support
- #
- # CONFIG_FB is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -469,13 +509,9 @@ CONFIG_GEN_RTC_X=y
- #
- # USB support
- #
--# CONFIG_USB is not set
- CONFIG_USB_ARCH_HAS_HCD=y
- CONFIG_USB_ARCH_HAS_OHCI=y
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
-+# CONFIG_USB is not set
-
- #
- # USB Gadget Support
-@@ -500,6 +536,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
- # CONFIG_JBD is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-+
-+#
-+# XFS support
-+#
- # CONFIG_XFS_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
-@@ -552,7 +592,6 @@ CONFIG_NFS_FS=y
- # CONFIG_NFSD is not set
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
--# CONFIG_EXPORTFS is not set
- CONFIG_SUNRPC=y
- # CONFIG_SMB_FS is not set
- # CONFIG_CIFS is not set
-@@ -573,8 +612,10 @@ CONFIG_MSDOS_PARTITION=y
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- CONFIG_DEBUG_KERNEL=y
- # CONFIG_MAGIC_SYSRQ is not set
-+CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_SCHEDSTATS is not set
- # CONFIG_DEBUG_SLAB is not set
- # CONFIG_DEBUG_SPINLOCK is not set
-@@ -599,7 +640,31 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
- #
- # Cryptographic options
- #
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+CONFIG_CRYPTO_HMAC=y
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_MD4=m
-+CONFIG_CRYPTO_MD5=m
-+CONFIG_CRYPTO_SHA1=m
-+CONFIG_CRYPTO_SHA256=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_DES=m
-+CONFIG_CRYPTO_BLOWFISH=m
-+CONFIG_CRYPTO_TWOFISH=m
-+CONFIG_CRYPTO_SERPENT=m
-+CONFIG_CRYPTO_AES=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_CAST6=m
-+CONFIG_CRYPTO_TEA=m
-+CONFIG_CRYPTO_ARC4=m
-+CONFIG_CRYPTO_KHAZAD=m
-+CONFIG_CRYPTO_ANUBIS=m
-+CONFIG_CRYPTO_DEFLATE=m
-+CONFIG_CRYPTO_MICHAEL_MIC=m
-+CONFIG_CRYPTO_CRC32C=m
-+CONFIG_CRYPTO_TEST=m
-
- #
- # Hardware crypto devices
-@@ -610,6 +675,8 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
- #
- # CONFIG_CRC_CCITT is not set
- # CONFIG_CRC32 is not set
--# CONFIG_LIBCRC32C is not set
-+CONFIG_LIBCRC32C=m
-+CONFIG_ZLIB_INFLATE=m
-+CONFIG_ZLIB_DEFLATE=m
- CONFIG_GENERIC_HARDIRQS=y
- CONFIG_GENERIC_IRQ_PROBE=y
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/Kconfig linux_HEAD/arch/mips/ddb5xxx/Kconfig
---- linux-2.6.12/arch/mips/ddb5xxx/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/ddb5xxx/Kconfig 2005-01-30 21:45:36.000000000 +0100
-@@ -0,0 +1,4 @@
-+config DDB5477_BUS_FREQUENCY
-+ int "bus frequency (in kHZ, 0 for auto-detect)"
-+ depends on DDB5477
-+ default 0
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5074/nile4_pic.c linux_HEAD/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5074/nile4_pic.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5074/nile4_pic.c 2005-02-28 16:56:41.000000000 +0100
-@@ -209,14 +209,13 @@ static void nile4_irq_end(unsigned int i
- #define nile4_irq_shutdown nile4_disable_irq
-
- static hw_irq_controller nile4_irq_controller = {
-- "nile4",
-- nile4_irq_startup,
-- nile4_irq_shutdown,
-- nile4_enable_irq,
-- nile4_disable_irq,
-- nile4_ack_irq,
-- nile4_irq_end,
-- NULL
-+ .typename = "nile4",
-+ .startup = nile4_irq_startup,
-+ .shutdown = nile4_irq_shutdown,
-+ .enable = nile4_enable_irq,
-+ .disable = nile4_disable_irq,
-+ .ack = nile4_ack_irq,
-+ .end = nile4_irq_end,
- };
-
- void nile4_irq_setup(u32 base) {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5074/setup.c linux_HEAD/arch/mips/ddb5xxx/ddb5074/setup.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5074/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5074/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -85,7 +85,7 @@ static void __init ddb_time_init(void)
-
-
-
--static void __init ddb5074_setup(void)
-+void __init plat_setup(void)
- {
- set_io_port_base(NILE4_PCI_IO_BASE);
- isa_slot_offset = NILE4_PCI_MEM_BASE;
-@@ -106,8 +106,6 @@ static void __init ddb5074_setup(void)
- panic_timeout = 180;
- }
-
--early_initcall(ddb5074_setup);
--
- #define USE_NILE4_SERIAL 0
-
- #if USE_NILE4_SERIAL
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5476/setup.c linux_HEAD/arch/mips/ddb5xxx/ddb5476/setup.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5476/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5476/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -124,7 +124,7 @@ static struct {
-
- static void ddb5476_board_init(void);
-
--static void __init ddb5476_setup(void)
-+void __init plat_setup(void)
- {
- set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
-
-@@ -158,8 +158,6 @@ static void __init ddb5476_setup(void)
- ddb5476_board_init();
- }
-
--early_initcall(ddb5476_setup);
--
- /*
- * We don't trust bios. We essentially does hardware re-initialization
- * as complete as possible, as far as we know we can safely do.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c linux_HEAD/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 2005-02-28 16:56:41.000000000 +0100
-@@ -53,14 +53,13 @@ static void vrc5476_irq_end(uint irq)
- }
-
- static hw_irq_controller vrc5476_irq_controller = {
-- "vrc5476",
-- vrc5476_irq_startup,
-- vrc5476_irq_shutdown,
-- vrc5476_irq_enable,
-- vrc5476_irq_disable,
-- vrc5476_irq_ack,
-- vrc5476_irq_end,
-- NULL /* no affinity stuff for UP */
-+ .typename = "vrc5476",
-+ .startup = vrc5476_irq_startup,
-+ .shutdown = vrc5476_irq_shutdown,
-+ .enable = vrc5476_irq_enable,
-+ .disable = vrc5476_irq_disable,
-+ .ack = vrc5476_irq_ack,
-+ .end = vrc5476_irq_end
- };
-
- void __init
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5477/irq_5477.c linux_HEAD/arch/mips/ddb5xxx/ddb5477/irq_5477.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2005-02-28 16:56:41.000000000 +0100
-@@ -90,14 +90,13 @@ vrc5477_irq_end(unsigned int irq)
- }
-
- hw_irq_controller vrc5477_irq_controller = {
-- "vrc5477_irq",
-- vrc5477_irq_startup,
-- vrc5477_irq_shutdown,
-- vrc5477_irq_enable,
-- vrc5477_irq_disable,
-- vrc5477_irq_ack,
-- vrc5477_irq_end,
-- NULL /* no affinity stuff for UP */
-+ .typename = "vrc5477_irq",
-+ .startup = vrc5477_irq_startup,
-+ .shutdown = vrc5477_irq_shutdown,
-+ .enable = vrc5477_irq_enable,
-+ .disable = vrc5477_irq_disable,
-+ .ack = vrc5477_irq_ack,
-+ .end = vrc5477_irq_end
- };
-
- void __init vrc5477_irq_init(u32 irq_base)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ddb5xxx/ddb5477/setup.c linux_HEAD/arch/mips/ddb5xxx/ddb5477/setup.c
---- linux-2.6.12/arch/mips/ddb5xxx/ddb5477/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ddb5xxx/ddb5477/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -170,7 +170,7 @@ static void ddb5477_board_init(void);
- extern struct pci_controller ddb5477_ext_controller;
- extern struct pci_controller ddb5477_io_controller;
-
--static int ddb5477_setup(void)
-+static void ddb5477_setup(void)
- {
- /* initialize board - we don't trust the loader */
- ddb5477_board_init();
-@@ -193,12 +193,8 @@ static int ddb5477_setup(void)
-
- register_pci_controller (&ddb5477_ext_controller);
- register_pci_controller (&ddb5477_io_controller);
--
-- return 0;
- }
-
--early_initcall(ddb5477_setup);
--
- static void __init ddb5477_board_init(void)
- {
- /* ----------- setup PDARs ------------ */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/Makefile linux_HEAD/arch/mips/dec/Makefile
---- linux-2.6.12/arch/mips/dec/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/Makefile 2005-07-01 12:09:17.000000000 +0200
-@@ -2,8 +2,8 @@
- # Makefile for the DECstation family specific parts of the kernel
- #
-
--obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \
-- setup.o time.o
-+obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
-+ kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
-
- obj-$(CONFIG_PROM_CONSOLE) += promcon.o
- obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/ecc-berr.c linux_HEAD/arch/mips/dec/ecc-berr.c
---- linux-2.6.12/arch/mips/dec/ecc-berr.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/ecc-berr.c 2005-07-03 16:44:19.000000000 +0200
-@@ -6,7 +6,7 @@
- * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
- * 5900/260 (KN05) systems.
- *
-- * Copyright (c) 2003 Maciej W. Rozycki
-+ * Copyright (c) 2003, 2005 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
-@@ -15,6 +15,7 @@
- */
-
- #include <linux/init.h>
-+#include <linux/interrupt.h>
- #include <linux/kernel.h>
- #include <linux/sched.h>
- #include <linux/spinlock.h>
-@@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_
-
- const char *kind, *agent, *cycle, *event;
- const char *status = "", *xbit = "", *fmt = "";
-- dma_addr_t address;
-+ unsigned long address;
- u16 syn = 0, sngl;
-
- int i = 0;
-@@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_
- u32 chksyn = *kn0x_chksyn;
- int action = MIPS_BE_FATAL;
-
-- /* For non-ECC ack ASAP, so any subsequent errors get caught. */
-+ /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
- if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
- dec_ecc_be_ack();
-
-@@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_
-
- if (!(erraddr & KN0X_EAR_VALID)) {
- /* No idea what happened. */
-- printk(KERN_ALERT "Unidentified bus error %s.\n", kind);
-+ printk(KERN_ALERT "Unidentified bus error %s\n", kind);
- return action;
- }
-
-@@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_
- /* Ack now, no rewrite will happen. */
- dec_ecc_be_ack();
-
-- fmt = KERN_ALERT "%s" "invalid.\n";
-+ fmt = KERN_ALERT "%s" "invalid\n";
- } else {
- sngl = syn & KN0X_ESR_SNGLO;
- syn &= KN0X_ESR_SYNLO;
-@@ -144,7 +145,8 @@ static int dec_ecc_be_backend(struct pt_
- } else if (!sngl) {
- status = dbestr;
- } else {
-- volatile u32 *ptr = (void *)KSEG1ADDR(address);
-+ volatile u32 *ptr =
-+ (void *)CKSEG1ADDR(address);
-
- *ptr = *ptr; /* Rewrite. */
- iob();
-@@ -160,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_
- if (syn == 0x01) {
- fmt = KERN_ALERT "%s"
- "%#04x -- %s bit error "
-- "at check bit C%s.\n";
-+ "at check bit C%s\n";
- xbit = "X";
- } else {
- fmt = KERN_ALERT "%s"
- "%#04x -- %s bit error "
-- "at check bit C%s%u.\n";
-+ "at check bit C%s%u\n";
- }
- i = syn >> 2;
- } else {
-@@ -175,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_
- if (i < 32)
- fmt = KERN_ALERT "%s"
- "%#04x -- %s bit error "
-- "at data bit D%s%u.\n";
-+ "at data bit D%s%u\n";
- else
- fmt = KERN_ALERT "%s"
-- "%#04x -- %s bit error.\n";
-+ "%#04x -- %s bit error\n";
- }
- }
- }
-
- if (action != MIPS_BE_FIXUP)
-- printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n",
-+ printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
- kind, agent, cycle, event, address);
-
- if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
-@@ -203,11 +205,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq
- int action = dec_ecc_be_backend(regs, 0, 1);
-
- if (action == MIPS_BE_DISCARD)
-- return IRQ_NONE;
-+ return IRQ_HANDLED;
-
- /*
-- * FIXME: Find affected processes and kill them, otherwise we
-- * must die.
-+ * FIXME: Find the affected processes and kill them, otherwise
-+ * we must die.
- *
- * The interrupt is asynchronously delivered thus EPC and RA
- * may be irrelevant, but are printed for a reference.
-@@ -225,16 +227,16 @@ irqreturn_t dec_ecc_be_interrupt(int irq
- */
- static inline void dec_kn02_be_init(void)
- {
-- volatile u32 *csr = (void *)KN02_CSR_BASE;
-+ volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
- unsigned long flags;
-
-- kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR);
-- kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN);
-+ kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
-+ kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
-
- spin_lock_irqsave(&kn02_lock, flags);
-
- /* Preset write-only bits of the Control Register cache. */
-- cached_kn02_csr = *csr | KN03_CSR_LEDS;
-+ cached_kn02_csr = *csr | KN02_CSR_LEDS;
-
- /* Set normal ECC detection and generation. */
- cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
-@@ -248,11 +250,11 @@ static inline void dec_kn02_be_init(void
-
- static inline void dec_kn03_be_init(void)
- {
-- volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
-- volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR);
-+ volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
-+ volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
-
-- kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
-- kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
-+ kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
-+ kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
-
- /*
- * Set normal ECC detection and generation, enable ECC correction.
-@@ -264,7 +266,7 @@ static inline void dec_kn03_be_init(void
- *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
- KN03_MCR_CORRECT;
- if (current_cpu_data.cputype == CPU_R4400SC)
-- *mbcs |= KN05_MB_CSR_EE;
-+ *mbcs |= KN4K_MB_CSR_EE;
- fast_iob();
- }
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/int-handler.S linux_HEAD/arch/mips/dec/int-handler.S
---- linux-2.6.12/arch/mips/dec/int-handler.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/int-handler.S 2005-07-03 16:44:20.000000000 +0200
-@@ -2,9 +2,9 @@
- * arch/mips/dec/int-handler.S
- *
- * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
-- * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
- *
-- * Written by Ralf Baechle and Andreas Busse, modified for DECStation
-+ * Written by Ralf Baechle and Andreas Busse, modified for DECstation
- * support by Paul Antoine and Harald Koerfgen.
- *
- * completly rewritten:
-@@ -14,11 +14,12 @@
- * by Maciej W. Rozycki.
- */
- #include <linux/config.h>
-+
-+#include <asm/addrspace.h>
- #include <asm/asm.h>
--#include <asm/regdef.h>
- #include <asm/mipsregs.h>
-+#include <asm/regdef.h>
- #include <asm/stackframe.h>
--#include <asm/addrspace.h>
-
- #include <asm/dec/interrupts.h>
- #include <asm/dec/ioasic_addrs.h>
-@@ -28,11 +29,14 @@
- #include <asm/dec/kn02xa.h>
- #include <asm/dec/kn03.h>
-
-+#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
-+#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
-+#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
-
- .text
- .set noreorder
- /*
-- * decstation_handle_int: Interrupt handler for DECStations
-+ * decstation_handle_int: Interrupt handler for DECstations
- *
- * We follow the model in the Indy interrupt code by David Miller, where he
- * says: a lot of complication here is taken away because:
-@@ -48,7 +52,7 @@
- * 3) Linux only thinks in terms of all IRQs on or all IRQs
- * off, nothing in between like BSD spl() brain-damage.
- *
-- * Furthermore, the IRQs on the DECStations look basically (barring
-+ * Furthermore, the IRQs on the DECstations look basically (barring
- * software IRQs which we don't use at all) like...
- *
- * DS2100/3100's, aka kn01, aka Pmax:
-@@ -61,7 +65,7 @@
- * 3 Lance Ethernet
- * 4 DZ11 serial
- * 5 RTC
-- * 6 Memory Controller
-+ * 6 Memory Controller & Video
- * 7 FPU
- *
- * DS5000/200, aka kn02, aka 3max:
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/kn01-berr.c linux_HEAD/arch/mips/dec/kn01-berr.c
---- linux-2.6.12/arch/mips/dec/kn01-berr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/dec/kn01-berr.c 2005-07-03 16:44:20.000000000 +0200
-@@ -0,0 +1,201 @@
-+/*
-+ * linux/arch/mips/dec/kn01-berr.c
-+ *
-+ * Bus error event handling code for DECstation/DECsystem 3100
-+ * and 2100 (KN01) systems equipped with parity error detection
-+ * logic.
-+ *
-+ * Copyright (c) 2005 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+#include <asm/inst.h>
-+#include <asm/mipsregs.h>
-+#include <asm/page.h>
-+#include <asm/system.h>
-+#include <asm/traps.h>
-+#include <asm/uaccess.h>
-+
-+#include <asm/dec/kn01.h>
-+
-+
-+/* CP0 hazard avoidance. */
-+#define BARRIER \
-+ __asm__ __volatile__( \
-+ ".set push\n\t" \
-+ ".set noreorder\n\t" \
-+ "nop\n\t" \
-+ ".set pop\n\t")
-+
-+/*
-+ * Bits 7:0 of the Control Register are write-only -- the
-+ * corresponding bits of the Status Register have a different
-+ * meaning. Hence we use a cache. It speeds up things a bit
-+ * as well.
-+ *
-+ * There is no default value -- it has to be initialized.
-+ */
-+u16 cached_kn01_csr;
-+DEFINE_SPINLOCK(kn01_lock);
-+
-+
-+static inline void dec_kn01_be_ack(void)
-+{
-+ volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&kn01_lock, flags);
-+
-+ *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
-+ iob();
-+
-+ spin_unlock_irqrestore(&kn01_lock, flags);
-+}
-+
-+static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
-+{
-+ volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
-+ KN01_ERRADDR);
-+
-+ static const char excstr[] = "exception";
-+ static const char intstr[] = "interrupt";
-+ static const char cpustr[] = "CPU";
-+ static const char mreadstr[] = "memory read";
-+ static const char readstr[] = "read";
-+ static const char writestr[] = "write";
-+ static const char timestr[] = "timeout";
-+ static const char paritystr[] = "parity error";
-+
-+ int data = regs->cp0_cause & 4;
-+ unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
-+ ((regs->cp0_cause & CAUSEF_BD) != 0);
-+ union mips_instruction insn;
-+ unsigned long entrylo, offset;
-+ long asid, entryhi, vaddr;
-+
-+ const char *kind, *agent, *cycle, *event;
-+ unsigned long address;
-+
-+ u32 erraddr = *kn01_erraddr;
-+ int action = MIPS_BE_FATAL;
-+
-+ /* Ack ASAP, so that any subsequent errors get caught. */
-+ dec_kn01_be_ack();
-+
-+ kind = invoker ? intstr : excstr;
-+
-+ agent = cpustr;
-+
-+ if (invoker)
-+ address = erraddr;
-+ else {
-+ /* Bloody hardware doesn't record the address for reads... */
-+ if (data) {
-+ /* This never faults. */
-+ __get_user(insn.word, pc);
-+ vaddr = regs->regs[insn.i_format.rs] +
-+ insn.i_format.simmediate;
-+ } else
-+ vaddr = (long)pc;
-+ if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
-+ address = CPHYSADDR(vaddr);
-+ else {
-+ /* Peek at what physical address the CPU used. */
-+ asid = read_c0_entryhi();
-+ entryhi = asid & (PAGE_SIZE - 1);
-+ entryhi |= vaddr & ~(PAGE_SIZE - 1);
-+ write_c0_entryhi(entryhi);
-+ BARRIER;
-+ tlb_probe();
-+ /* No need to check for presence. */
-+ tlb_read();
-+ entrylo = read_c0_entrylo0();
-+ write_c0_entryhi(asid);
-+ offset = vaddr & (PAGE_SIZE - 1);
-+ address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
-+ }
-+ }
-+
-+ /* Treat low 256MB as memory, high -- as I/O. */
-+ if (address < 0x10000000) {
-+ cycle = mreadstr;
-+ event = paritystr;
-+ } else {
-+ cycle = invoker ? writestr : readstr;
-+ event = timestr;
-+ }
-+
-+ if (is_fixup)
-+ action = MIPS_BE_FIXUP;
-+
-+ if (action != MIPS_BE_FIXUP)
-+ printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
-+ kind, agent, cycle, event, address);
-+
-+ return action;
-+}
-+
-+int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
-+{
-+ return dec_kn01_be_backend(regs, is_fixup, 0);
-+}
-+
-+irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs)
-+{
-+ volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
-+ int action;
-+
-+ if (!(*csr & KN01_CSR_MEMERR))
-+ return IRQ_NONE; /* Must have been video. */
-+
-+ action = dec_kn01_be_backend(regs, 0, 1);
-+
-+ if (action == MIPS_BE_DISCARD)
-+ return IRQ_HANDLED;
-+
-+ /*
-+ * FIXME: Find the affected processes and kill them, otherwise
-+ * we must die.
-+ *
-+ * The interrupt is asynchronously delivered thus EPC and RA
-+ * may be irrelevant, but are printed for a reference.
-+ */
-+ printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
-+ regs->cp0_epc, regs->regs[31]);
-+ die("Unrecoverable bus error", regs);
-+}
-+
-+
-+void __init dec_kn01_be_init(void)
-+{
-+ volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&kn01_lock, flags);
-+
-+ /* Preset write-only bits of the Control Register cache. */
-+ cached_kn01_csr = *csr;
-+ cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
-+ cached_kn01_csr |= KN01_CSR_LEDS;
-+
-+ /* Enable parity error detection. */
-+ cached_kn01_csr &= ~KN01_CSR_PARDIS;
-+ *csr = cached_kn01_csr;
-+ iob();
-+
-+ spin_unlock_irqrestore(&kn01_lock, flags);
-+
-+ /* Clear any leftover errors from the firmware. */
-+ dec_kn01_be_ack();
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/kn02-irq.c linux_HEAD/arch/mips/dec/kn02-irq.c
---- linux-2.6.12/arch/mips/dec/kn02-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/kn02-irq.c 2005-07-03 16:44:20.000000000 +0200
-@@ -4,7 +4,7 @@
- * DECstation 5000/200 (KN02) Control and Status Register
- * interrupts.
- *
-- * Copyright (c) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
-@@ -37,7 +37,8 @@ static int kn02_irq_base;
-
- static inline void unmask_kn02_irq(unsigned int irq)
- {
-- volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
-+ volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
-+ KN02_CSR);
-
- cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
- *csr = cached_kn02_csr;
-@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsig
-
- static inline void mask_kn02_irq(unsigned int irq)
- {
-- volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
-+ volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
-+ KN02_CSR);
-
- cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
- *csr = cached_kn02_csr;
-@@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq
-
- void __init init_kn02_irqs(int base)
- {
-- volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
-+ volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
-+ KN02_CSR);
- unsigned long flags;
- int i;
-
- /* Mask interrupts. */
- spin_lock_irqsave(&kn02_lock, flags);
-- cached_kn02_csr &= ~KN03_CSR_IOINTEN;
-+ cached_kn02_csr &= ~KN02_CSR_IOINTEN;
- *csr = cached_kn02_csr;
- iob();
- spin_unlock_irqrestore(&kn02_lock, flags);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/kn02xa-berr.c linux_HEAD/arch/mips/dec/kn02xa-berr.c
---- linux-2.6.12/arch/mips/dec/kn02xa-berr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/dec/kn02xa-berr.c 2005-07-03 16:44:20.000000000 +0200
-@@ -0,0 +1,139 @@
-+/*
-+ * linux/arch/mips/dec/kn02xa-berr.c
-+ *
-+ * Bus error event handling code for 5000-series systems equipped
-+ * with parity error detection logic, i.e. DECstation/DECsystem
-+ * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
-+ * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
-+ * (KN04-CA) systems.
-+ *
-+ * Copyright (c) 2005 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/system.h>
-+#include <asm/traps.h>
-+
-+#include <asm/dec/kn02ca.h>
-+#include <asm/dec/kn02xa.h>
-+#include <asm/dec/kn05.h>
-+
-+static inline void dec_kn02xa_be_ack(void)
-+{
-+ volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
-+ volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
-+
-+ *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
-+ *mem_intr = 0; /* Any write clears the bus IRQ. */
-+ iob();
-+}
-+
-+static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
-+ int invoker)
-+{
-+ volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
-+ volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
-+
-+ static const char excstr[] = "exception";
-+ static const char intstr[] = "interrupt";
-+ static const char cpustr[] = "CPU";
-+ static const char mreadstr[] = "memory read";
-+ static const char readstr[] = "read";
-+ static const char writestr[] = "write";
-+ static const char timestr[] = "timeout";
-+ static const char paritystr[] = "parity error";
-+ static const char lanestat[][4] = { " OK", "BAD" };
-+
-+ const char *kind, *agent, *cycle, *event;
-+ unsigned long address;
-+
-+ u32 mer = *kn02xa_mer;
-+ u32 ear = *kn02xa_ear;
-+ int action = MIPS_BE_FATAL;
-+
-+ /* Ack ASAP, so that any subsequent errors get caught. */
-+ dec_kn02xa_be_ack();
-+
-+ kind = invoker ? intstr : excstr;
-+
-+ /* No DMA errors? */
-+ agent = cpustr;
-+
-+ address = ear & KN02XA_EAR_ADDRESS;
-+
-+ /* Low 256MB is decoded as memory, high -- as TC. */
-+ if (address < 0x10000000) {
-+ cycle = mreadstr;
-+ event = paritystr;
-+ } else {
-+ cycle = invoker ? writestr : readstr;
-+ event = timestr;
-+ }
-+
-+ if (is_fixup)
-+ action = MIPS_BE_FIXUP;
-+
-+ if (action != MIPS_BE_FIXUP)
-+ printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
-+ kind, agent, cycle, event, address);
-+
-+ if (action != MIPS_BE_FIXUP && address < 0x10000000)
-+ printk(KERN_ALERT " Byte lane status %#3x -- "
-+ "#3: %s, #2: %s, #1: %s, #0: %s\n",
-+ (mer & KN02XA_MER_BYTERR) >> 8,
-+ lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
-+ lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
-+ lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
-+ lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
-+
-+ return action;
-+}
-+
-+int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
-+{
-+ return dec_kn02xa_be_backend(regs, is_fixup, 0);
-+}
-+
-+irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs)
-+{
-+ int action = dec_kn02xa_be_backend(regs, 0, 1);
-+
-+ if (action == MIPS_BE_DISCARD)
-+ return IRQ_HANDLED;
-+
-+ /*
-+ * FIXME: Find the affected processes and kill them, otherwise
-+ * we must die.
-+ *
-+ * The interrupt is asynchronously delivered thus EPC and RA
-+ * may be irrelevant, but are printed for a reference.
-+ */
-+ printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
-+ regs->cp0_epc, regs->regs[31]);
-+ die("Unrecoverable bus error", regs);
-+}
-+
-+
-+void __init dec_kn02xa_be_init(void)
-+{
-+ volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
-+
-+ /* For KN04 we need to make sure EE (?) is enabled in the MB. */
-+ if (current_cpu_data.cputype == CPU_R4000SC)
-+ *mbcs |= KN4K_MB_CSR_EE;
-+ fast_iob();
-+
-+ /* Clear any leftover errors from the firmware. */
-+ dec_kn02xa_be_ack();
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/prom/identify.c linux_HEAD/arch/mips/dec/prom/identify.c
---- linux-2.6.12/arch/mips/dec/prom/identify.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/prom/identify.c 2005-07-03 16:44:20.000000000 +0200
-@@ -2,7 +2,7 @@
- * identify.c: machine identification code.
- *
- * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
-- * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
- */
- #include <linux/init.h>
- #include <linux/kernel.h>
-@@ -12,6 +12,7 @@
- #include <linux/types.h>
-
- #include <asm/bootinfo.h>
-+
- #include <asm/dec/ioasic.h>
- #include <asm/dec/ioasic_addrs.h>
- #include <asm/dec/kn01.h>
-@@ -21,6 +22,7 @@
- #include <asm/dec/kn03.h>
- #include <asm/dec/kn230.h>
- #include <asm/dec/prom.h>
-+#include <asm/dec/system.h>
-
- #include "dectypes.h"
-
-@@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
-
- static inline void prom_init_kn01(void)
- {
-- dec_rtc_base = (void *)KN01_RTC_BASE;
-+ dec_kn_slot_base = KN01_SLOT_BASE;
- dec_kn_slot_size = KN01_SLOT_SIZE;
-+
-+ dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
- }
-
- static inline void prom_init_kn230(void)
- {
-- dec_rtc_base = (void *)KN01_RTC_BASE;
-+ dec_kn_slot_base = KN01_SLOT_BASE;
- dec_kn_slot_size = KN01_SLOT_SIZE;
-+
-+ dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
- }
-
- static inline void prom_init_kn02(void)
- {
-- dec_rtc_base = (void *)KN02_RTC_BASE;
-+ dec_kn_slot_base = KN02_SLOT_BASE;
- dec_kn_slot_size = KN02_SLOT_SIZE;
-+
-+ dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
- }
-
- static inline void prom_init_kn02xa(void)
- {
-- ioasic_base = (void *)KN02XA_IOASIC_BASE;
-- dec_rtc_base = (void *)KN02XA_RTC_BASE;
-+ dec_kn_slot_base = KN02XA_SLOT_BASE;
- dec_kn_slot_size = IOASIC_SLOT_SIZE;
-+
-+ ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
-+ dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
- }
-
- static inline void prom_init_kn03(void)
- {
-- ioasic_base = (void *)KN03_IOASIC_BASE;
-- dec_rtc_base = (void *)KN03_RTC_BASE;
-+ dec_kn_slot_base = KN03_SLOT_BASE;
- dec_kn_slot_size = IOASIC_SLOT_SIZE;
-+
-+ ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
-+ dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
- }
-
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/prom/init.c linux_HEAD/arch/mips/dec/prom/init.c
---- linux-2.6.12/arch/mips/dec/prom/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/prom/init.c 2005-07-01 12:09:17.000000000 +0200
-@@ -6,6 +6,8 @@
- */
- #include <linux/config.h>
- #include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/linkage.h>
- #include <linux/smp.h>
- #include <linux/string.h>
- #include <linux/types.h>
-@@ -85,17 +87,13 @@ void __init which_prom(s32 magic, s32 *p
-
- void __init prom_init(void)
- {
-- extern void dec_machine_halt(void);
-+ extern void ATTRIB_NORET dec_machine_halt(void);
- static char cpu_msg[] __initdata =
- "Sorry, this kernel is compiled for a wrong CPU type!\n";
-- static char r3k_msg[] __initdata =
-- "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
-- static char r4k_msg[] __initdata =
-- "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
- s32 argc = fw_arg0;
-- s32 argv = fw_arg1;
-+ s32 *argv = (void *)fw_arg1;
- u32 magic = fw_arg2;
-- s32 prom_vec = fw_arg3;
-+ s32 *prom_vec = (void *)fw_arg3;
-
- /*
- * Determine which PROM we have
-@@ -113,6 +111,8 @@ void __init prom_init(void)
- #if defined(CONFIG_CPU_R3000)
- if ((current_cpu_data.cputype == CPU_R4000SC) ||
- (current_cpu_data.cputype == CPU_R4400SC)) {
-+ static char r4k_msg[] __initdata =
-+ "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
- printk(cpu_msg);
- printk(r4k_msg);
- dec_machine_halt();
-@@ -122,6 +122,8 @@ void __init prom_init(void)
- #if defined(CONFIG_CPU_R4X00)
- if ((current_cpu_data.cputype == CPU_R3000) ||
- (current_cpu_data.cputype == CPU_R3000A)) {
-+ static char r3k_msg[] __initdata =
-+ "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
- printk(cpu_msg);
- printk(r3k_msg);
- dec_machine_halt();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/prom/memory.c linux_HEAD/arch/mips/dec/prom/memory.c
---- linux-2.6.12/arch/mips/dec/prom/memory.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/prom/memory.c 2005-07-01 12:09:17.000000000 +0200
-@@ -35,22 +35,22 @@ static inline void pmax_setup_memory_reg
- extern char genexcept_early;
-
- /* Install exception handler */
-- memcpy(&old_handler, (void *)(KSEG0 + 0x80), 0x80);
-- memcpy((void *)(KSEG0 + 0x80), &genexcept_early, 0x80);
-+ memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80);
-+ memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80);
-
- /* read unmapped and uncached (KSEG1)
- * DECstations have at least 4MB RAM
- * Assume less than 480MB of RAM, as this is max for 5000/2xx
- * FIXME this should be replaced by the first free page!
- */
-- for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE;
-- (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000));
-+ for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE;
-+ mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000;
- memory_page += CHUNK_SIZE) {
- dummy = *memory_page;
- }
-- memcpy((void *)(KSEG0 + 0x80), &old_handler, 0x80);
-+ memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
-
-- add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE,
-+ add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE,
- BOOT_MEM_RAM);
- }
-
-@@ -65,7 +65,7 @@ static inline void rex_setup_memory_regi
- memmap *bm;
-
- /* some free 64k */
-- bm = (memmap *)KSEG0ADDR(0x28000);
-+ bm = (memmap *)CKSEG0ADDR(0x28000);
-
- bitmap_size = rex_getbitmap(bm);
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/reset.c linux_HEAD/arch/mips/dec/reset.c
---- linux-2.6.12/arch/mips/dec/reset.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/reset.c 2005-07-01 12:09:17.000000000 +0200
-@@ -14,7 +14,7 @@ typedef void ATTRIB_NORET (* noret_func_
-
- static inline void ATTRIB_NORET back_to_prom(void)
- {
-- noret_func_t func = (void *) KSEG1ADDR(0x1fc00000);
-+ noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);
-
- func();
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/dec/setup.c linux_HEAD/arch/mips/dec/setup.c
---- linux-2.6.12/arch/mips/dec/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/dec/setup.c 2005-07-03 16:44:20.000000000 +0200
-@@ -1,19 +1,20 @@
- /*
-- * Setup the interrupt stuff.
-+ * System-specific setup, especially interrupts.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Harald Koerfgen
-- * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
- */
--#include <linux/sched.h>
--#include <linux/interrupt.h>
--#include <linux/param.h>
- #include <linux/console.h>
- #include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
- #include <linux/module.h>
-+#include <linux/param.h>
-+#include <linux/sched.h>
- #include <linux/spinlock.h>
- #include <linux/types.h>
-
-@@ -38,6 +39,7 @@
- #include <asm/dec/kn02ca.h>
- #include <asm/dec/kn03.h>
- #include <asm/dec/kn230.h>
-+#include <asm/dec/system.h>
-
-
- extern void dec_machine_restart(char *command);
-@@ -47,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq
-
- extern asmlinkage void decstation_handle_int(void);
-
-+unsigned long dec_kn_slot_base, dec_kn_slot_size;
-+
-+EXPORT_SYMBOL(dec_kn_slot_base);
-+EXPORT_SYMBOL(dec_kn_slot_size);
-+
- spinlock_t ioasic_ssr_lock;
-
- volatile u32 *ioasic_base;
--unsigned long dec_kn_slot_size;
-+
-+EXPORT_SYMBOL(ioasic_base);
-
- /*
- * IRQ routing and priority tables. Priorites are set as follows:
-@@ -77,6 +85,9 @@ unsigned long dec_kn_slot_size;
- int dec_interrupt[DEC_NR_INTS] = {
- [0 ... DEC_NR_INTS - 1] = -1
- };
-+
-+EXPORT_SYMBOL(dec_interrupt);
-+
- int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
- { { .i = ~0 }, { .p = dec_intr_unimplemented } },
- };
-@@ -112,7 +123,16 @@ void __init dec_be_init(void)
- {
- switch (mips_machtype) {
- case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
-+ board_be_handler = dec_kn01_be_handler;
-+ busirq.handler = dec_kn01_be_interrupt;
- busirq.flags |= SA_SHIRQ;
-+ dec_kn01_be_init();
-+ break;
-+ case MACH_DS5000_1XX: /* DS5000/1xx 3min */
-+ case MACH_DS5000_XX: /* DS5000/xx Maxine */
-+ board_be_handler = dec_kn02xa_be_handler;
-+ busirq.handler = dec_kn02xa_be_interrupt;
-+ dec_kn02xa_be_init();
- break;
- case MACH_DS5000_200: /* DS5000/200 3max */
- case MACH_DS5000_2X0: /* DS5000/240 3max+ */
-@@ -128,7 +148,7 @@ void __init dec_be_init(void)
- extern void dec_time_init(void);
- extern void dec_timer_setup(struct irqaction *);
-
--static void __init decstation_setup(void)
-+void __init decstation_setup(void)
- {
- board_be_init = dec_be_init;
- board_time_init = dec_time_init;
-@@ -139,9 +159,10 @@ static void __init decstation_setup(void
- _machine_restart = dec_machine_restart;
- _machine_halt = dec_machine_halt;
- _machine_power_off = dec_machine_power_off;
--}
-
--early_initcall(decstation_setup);
-+ ioport_resource.start = ~0UL;
-+ ioport_resource.end = 0UL;
-+}
-
- /*
- * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
-@@ -744,7 +765,3 @@ void __init arch_init_irq(void)
- if (dec_interrupt[DEC_IRQ_HALT] >= 0)
- setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
- }
--
--EXPORT_SYMBOL(ioasic_base);
--EXPORT_SYMBOL(dec_kn_slot_size);
--EXPORT_SYMBOL(dec_interrupt);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/defconfig linux_HEAD/arch/mips/defconfig
---- linux-2.6.12/arch/mips/defconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/defconfig 2005-07-07 11:22:47.000000000 +0200
-@@ -1,12 +1,9 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.11-rc2
--# Wed Jan 26 02:48:59 2005
-+# Linux kernel version: 2.6.12
-+# Sat Jun 18 14:53:00 2005
- #
- CONFIG_MIPS=y
--# CONFIG_MIPS64 is not set
--# CONFIG_64BIT is not set
--CONFIG_MIPS32=y
-
- #
- # Code maturity level options
-@@ -14,6 +11,7 @@ CONFIG_MIPS32=y
- CONFIG_EXPERIMENTAL=y
- CONFIG_CLEAN_COMPILE=y
- CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-
- #
- # General setup
-@@ -25,7 +23,6 @@ CONFIG_SYSVIPC=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- CONFIG_SYSCTL=y
- # CONFIG_AUDIT is not set
--CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_HOTPLUG is not set
- CONFIG_KOBJECT_UEVENT=y
- CONFIG_IKCONFIG=y
-@@ -33,6 +30,9 @@ CONFIG_IKCONFIG_PROC=y
- CONFIG_EMBEDDED=y
- CONFIG_KALLSYMS=y
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_BASE_FULL=y
- CONFIG_FUTEX=y
- CONFIG_EPOLL=y
- # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-@@ -42,6 +42,7 @@ CONFIG_CC_ALIGN_LABELS=0
- CONFIG_CC_ALIGN_LOOPS=0
- CONFIG_CC_ALIGN_JUMPS=0
- # CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-
- #
- # Loadable module support
-@@ -57,40 +58,63 @@ CONFIG_KMOD=y
- #
- # Machine selection
- #
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
- # CONFIG_MIPS_COBALT is not set
- # CONFIG_MACH_DECSTATION is not set
- # CONFIG_MIPS_EV64120 is not set
- # CONFIG_MIPS_EV96100 is not set
- # CONFIG_MIPS_IVR is not set
--# CONFIG_LASAT is not set
- # CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
- # CONFIG_MIPS_ATLAS is not set
- # CONFIG_MIPS_MALTA is not set
- # CONFIG_MIPS_SEAD is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
- # CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
- # CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
- # CONFIG_DDB5074 is not set
- # CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
--# CONFIG_NEC_OSPREY is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
- CONFIG_SGI_IP22=y
--# CONFIG_SOC_AU1X00 is not set
--# CONFIG_SIBYTE_SB1xxx_SOC is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
- # CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- CONFIG_RWSEM_GENERIC_SPINLOCK=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
- CONFIG_HAVE_DEC_LOCK=y
- CONFIG_ARC=y
- CONFIG_DMA_NONCOHERENT=y
-+CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
- CONFIG_IRQ_CPU=y
- CONFIG_SWAP_IO_SPACE=y
- CONFIG_ARC32=y
-@@ -102,8 +126,8 @@ CONFIG_ARC_PROMLIB=y
- #
- # CPU selection
- #
--# CONFIG_CPU_MIPS32 is not set
--# CONFIG_CPU_MIPS64 is not set
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
- # CONFIG_CPU_R3000 is not set
- # CONFIG_CPU_TX39XX is not set
- # CONFIG_CPU_VR41XX is not set
-@@ -119,6 +143,17 @@ CONFIG_CPU_R5000=y
- # CONFIG_CPU_RM7000 is not set
- # CONFIG_CPU_RM9000 is not set
- # CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_MIPS32=y
-+# CONFIG_MIPS64 is not set
-+# CONFIG_64BIT is not set
- CONFIG_PAGE_SIZE_4KB=y
- # CONFIG_PAGE_SIZE_8KB is not set
- # CONFIG_PAGE_SIZE_16KB is not set
-@@ -135,6 +170,7 @@ CONFIG_CPU_HAS_SYNC=y
- #
- # Bus options (PCI, PCMCIA, EISA, ISA, TC)
- #
-+CONFIG_HW_HAS_EISA=y
- # CONFIG_EISA is not set
- CONFIG_MMU=y
-
-@@ -144,10 +180,6 @@ CONFIG_MMU=y
- # CONFIG_PCCARD is not set
-
- #
--# PC-card bridges
--#
--
--#
- # PCI Hotplug Support
- #
-
-@@ -276,7 +308,6 @@ CONFIG_NET=y
- #
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
--CONFIG_NETLINK_DEV=y
- CONFIG_UNIX=y
- CONFIG_NET_KEY=y
- CONFIG_INET=y
-@@ -409,7 +440,7 @@ CONFIG_IP_NF_ARPFILTER=m
- CONFIG_IP_NF_ARP_MANGLE=m
-
- #
--# IPv6: Netfilter Configuration
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
- #
- CONFIG_IP6_NF_QUEUE=m
- CONFIG_IP6_NF_IPTABLES=m
-@@ -478,6 +509,7 @@ CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_QOS=y
- CONFIG_NET_ESTIMATOR=y
- CONFIG_NET_CLS=y
-+CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
- CONFIG_NET_CLS_ROUTE=y
-@@ -488,6 +520,7 @@ CONFIG_NET_CLS_U32=m
- # CONFIG_CLS_U32_MARK is not set
- CONFIG_NET_CLS_RSVP=m
- CONFIG_NET_CLS_RSVP6=m
-+# CONFIG_NET_EMATCH is not set
- # CONFIG_NET_CLS_ACT is not set
- CONFIG_NET_CLS_POLICE=y
-
-@@ -505,7 +538,6 @@ CONFIG_DUMMY=m
- CONFIG_BONDING=m
- CONFIG_EQUALIZER=m
- CONFIG_TUN=m
--CONFIG_ETHERTAP=m
-
- #
- # Ethernet (10 or 100Mbit)
-@@ -568,18 +600,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_EVBUG is not set
-
- #
--# Input I/O drivers
--#
--# CONFIG_GAMEPORT is not set
--CONFIG_SOUND_GAMEPORT=y
--CONFIG_SERIO=y
--CONFIG_SERIO_I8042=y
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_CT82C710 is not set
--CONFIG_SERIO_LIBPS2=y
--CONFIG_SERIO_RAW=m
--
--#
- # Input Device Drivers
- #
- CONFIG_INPUT_KEYBOARD=y
-@@ -597,6 +617,16 @@ CONFIG_MOUSE_SERIAL=m
- # CONFIG_INPUT_MISC is not set
-
- #
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_I8042=y
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_LIBPS2=y
-+CONFIG_SERIO_RAW=m
-+# CONFIG_GAMEPORT is not set
-+
-+#
- # Character devices
- #
- CONFIG_VT=y
-@@ -648,6 +678,10 @@ CONFIG_RAW_DRIVER=m
- CONFIG_MAX_RAW_DEVS=256
-
- #
-+# TPM devices
-+#
-+
-+#
- # I2C support
- #
- # CONFIG_I2C is not set
-@@ -692,7 +726,6 @@ CONFIG_LOGO=y
- # CONFIG_LOGO_LINUX_VGA16 is not set
- # CONFIG_LOGO_LINUX_CLUT224 is not set
- CONFIG_LOGO_SGI_CLUT224=y
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
- #
- # Sound
-@@ -706,10 +739,6 @@ CONFIG_LOGO_SGI_CLUT224=y
- # CONFIG_USB_ARCH_HAS_OHCI is not set
-
- #
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
--#
--
--#
- # USB Gadget Support
- #
- # CONFIG_USB_GADGET is not set
-@@ -739,7 +768,12 @@ CONFIG_FS_MBCACHE=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- CONFIG_FS_POSIX_ACL=y
-+
-+#
-+# XFS support
-+#
- CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
- # CONFIG_XFS_RT is not set
- CONFIG_XFS_QUOTA=y
- CONFIG_XFS_SECURITY=y
-@@ -907,7 +941,9 @@ CONFIG_NLS_UTF8=m
- #
- # Kernel hacking
- #
-+# CONFIG_PRINTK_TIME is not set
- # CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
- CONFIG_CROSSCOMPILE=y
- CONFIG_CMDLINE=""
-
-@@ -930,6 +966,7 @@ CONFIG_CRYPTO_SHA1=m
- CONFIG_CRYPTO_SHA256=m
- CONFIG_CRYPTO_SHA512=m
- CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_DES=m
- CONFIG_CRYPTO_BLOWFISH=m
- CONFIG_CRYPTO_TWOFISH=m
-diff -urpNX dontdiff linux-2.6.12/arch/mips/galileo-boards/ev96100/setup.c linux_HEAD/arch/mips/galileo-boards/ev96100/setup.c
---- linux-2.6.12/arch/mips/galileo-boards/ev96100/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/galileo-boards/ev96100/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -55,7 +55,7 @@ extern void mips_reboot_setup(void);
-
- unsigned char mac_0_1[12];
-
--static void __init ev96100_setup(void)
-+void __init plat_setup(void)
- {
- unsigned int config = read_c0_config();
- unsigned int status = read_c0_status();
-@@ -142,8 +142,6 @@ static void __init ev96100_setup(void)
- tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
- }
-
--early_initcall(ev96100_setup);
--
- unsigned short get_gt_devid(void)
- {
- u32 gt_devid;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/gt64120/ev64120/Kconfig linux_HEAD/arch/mips/gt64120/ev64120/Kconfig
---- linux-2.6.12/arch/mips/gt64120/ev64120/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/gt64120/ev64120/Kconfig 2005-01-30 21:45:37.000000000 +0100
-@@ -0,0 +1,3 @@
-+config EVB_PCI1
-+ bool "Enable Second PCI (PCI1)"
-+ depends on MIPS_EV64120
-diff -urpNX dontdiff linux-2.6.12/arch/mips/gt64120/ev64120/setup.c linux_HEAD/arch/mips/gt64120/ev64120/setup.c
---- linux-2.6.12/arch/mips/gt64120/ev64120/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/gt64120/ev64120/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -69,7 +69,7 @@ unsigned long __init prom_free_prom_memo
- */
- extern void gt64120_time_init(void);
-
--static void __init ev64120_setup(void)
-+void __init plat_setup(void)
- {
- _machine_restart = galileo_machine_restart;
- _machine_halt = galileo_machine_halt;
-@@ -79,8 +79,6 @@ static void __init ev64120_setup(void)
- set_io_port_base(KSEG1);
- }
-
--early_initcall(ev64120_setup);
--
- const char *get_system_type(void)
- {
- return "Galileo EV64120A";
-diff -urpNX dontdiff linux-2.6.12/arch/mips/gt64120/momenco_ocelot/setup.c linux_HEAD/arch/mips/gt64120/momenco_ocelot/setup.c
---- linux-2.6.12/arch/mips/gt64120/momenco_ocelot/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/gt64120/momenco_ocelot/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -150,7 +150,7 @@ void PMON_v2_setup()
- gt64120_base = 0xe0000000;
- }
-
--static void __init momenco_ocelot_setup(void)
-+void __init plat_setup(void)
- {
- void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
- unsigned int tmpword;
-@@ -307,8 +307,6 @@ static void __init momenco_ocelot_setup(
- GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
- }
-
--early_initcall(momenco_ocelot_setup);
--
- extern int rm7k_tcache_enabled;
- /*
- * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ite-boards/Kconfig linux_HEAD/arch/mips/ite-boards/Kconfig
---- linux-2.6.12/arch/mips/ite-boards/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/ite-boards/Kconfig 2005-01-30 21:45:36.000000000 +0100
-@@ -0,0 +1,8 @@
-+config IT8172_REVC
-+ bool "Support for older IT8172 (Rev C)"
-+ depends on MIPS_ITE8172
-+ help
-+ Say Y here to support the older, Revision C version of the Integrated
-+ Technology Express, Inc. ITE8172 SBC. Vendor page at
-+ <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
-+ board at <http://www.mvista.com/partners/semiconductor/ite.html>.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ite-boards/generic/irq.c linux_HEAD/arch/mips/ite-boards/generic/irq.c
---- linux-2.6.12/arch/mips/ite-boards/generic/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ite-boards/generic/irq.c 2005-02-28 16:56:41.000000000 +0100
-@@ -138,14 +138,13 @@ static void end_ite_irq(unsigned int irq
- }
-
- static struct hw_interrupt_type it8172_irq_type = {
-- "ITE8172",
-- startup_ite_irq,
-- shutdown_ite_irq,
-- enable_it8172_irq,
-- disable_it8172_irq,
-- mask_and_ack_ite_irq,
-- end_ite_irq,
-- NULL
-+ .typename = "ITE8172",
-+ .startup = startup_ite_irq,
-+ .shutdown = shutdown_ite_irq,
-+ .enable = enable_it8172_irq,
-+ .disable = disable_it8172_irq,
-+ .ack = mask_and_ack_ite_irq,
-+ .end = end_ite_irq,
- };
-
-
-@@ -159,13 +158,13 @@ static void ack_none(unsigned int irq) {
- #define end_none enable_none
-
- static struct hw_interrupt_type cp0_irq_type = {
-- "CP0 Count",
-- startup_none,
-- shutdown_none,
-- enable_none,
-- disable_none,
-- ack_none,
-- end_none
-+ .typename = "CP0 Count",
-+ .startup = startup_none,
-+ .shutdown = shutdown_none,
-+ .enable = enable_none,
-+ .disable = disable_none,
-+ .ack = ack_none,
-+ .end = end_none
- };
-
- void enable_cpu_timer(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/ite-boards/generic/it8172_setup.c linux_HEAD/arch/mips/ite-boards/generic/it8172_setup.c
---- linux-2.6.12/arch/mips/ite-boards/generic/it8172_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/ite-boards/generic/it8172_setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -105,7 +105,7 @@ void __init it8172_init_ram_resource(uns
- it8172_resources.ram.end = memsize;
- }
-
--static void __init it8172_setup(void)
-+void __init plat_setup(void)
- {
- unsigned short dsr;
- char *argptr;
-@@ -251,8 +251,6 @@ static void __init it8172_setup(void)
- #endif /* CONFIG_IT8172_SCR1 */
- }
-
--early_initcall(it8172_setup);
--
- #ifdef CONFIG_SERIO_I8042
- /*
- * According to the ITE Special BIOS Note for waking up the
-diff -urpNX dontdiff linux-2.6.12/arch/mips/jazz/Kconfig linux_HEAD/arch/mips/jazz/Kconfig
---- linux-2.6.12/arch/mips/jazz/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/jazz/Kconfig 2005-01-30 21:45:36.000000000 +0100
-@@ -0,0 +1,33 @@
-+config ACER_PICA_61
-+ bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
-+ depends on MACH_JAZZ && EXPERIMENTAL
-+ select DMA_NONCOHERENT
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+ This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
-+ kernel that runs on these, say Y here. For details about Linux on
-+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-+ <http://www.linux-mips.org/>.
-+
-+config MIPS_MAGNUM_4000
-+ bool "Support for MIPS Magnum 4000"
-+ depends on MACH_JAZZ
-+ select DMA_NONCOHERENT
-+ select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+ This is a machine with a R4000 100 MHz CPU. To compile a Linux
-+ kernel that runs on these, say Y here. For details about Linux on
-+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-+ <http://www.linux-mips.org/>.
-+
-+config OLIVETTI_M700
-+ bool "Support for Olivetti M700-10"
-+ depends on MACH_JAZZ
-+ select DMA_NONCOHERENT
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+ This is a machine with a R4000 100 MHz CPU. To compile a Linux
-+ kernel that runs on these, say Y here. For details about Linux on
-+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
-+ <http://www.linux-mips.org/>.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/jazz/irq.c linux_HEAD/arch/mips/jazz/irq.c
---- linux-2.6.12/arch/mips/jazz/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/jazz/irq.c 2005-02-28 16:56:41.000000000 +0100
-@@ -58,14 +58,13 @@ static void end_r4030_irq(unsigned int i
- }
-
- static struct hw_interrupt_type r4030_irq_type = {
-- "R4030",
-- startup_r4030_irq,
-- shutdown_r4030_irq,
-- enable_r4030_irq,
-- disable_r4030_irq,
-- mask_and_ack_r4030_irq,
-- end_r4030_irq,
-- NULL
-+ .typename = "R4030",
-+ .startup = startup_r4030_irq,
-+ .shutdown = shutdown_r4030_irq,
-+ .enable = enable_r4030_irq,
-+ .disable = disable_r4030_irq,
-+ .ack = mask_and_ack_r4030_irq,
-+ .end = end_r4030_irq,
- };
-
- void __init init_r4030_ints(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/jazz/setup.c linux_HEAD/arch/mips/jazz/setup.c
---- linux-2.6.12/arch/mips/jazz/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/jazz/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -50,7 +50,7 @@ static struct resource jazz_io_resources
- { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
- };
-
--static void __init jazz_setup(void)
-+void __init plat_setup(void)
- {
- int i;
-
-@@ -97,5 +97,3 @@ static void __init jazz_setup(void)
-
- vdma_init();
- }
--
--early_initcall(jazz_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/jmr3927/rbhma3100/irq.c linux_HEAD/arch/mips/jmr3927/rbhma3100/irq.c
---- linux-2.6.12/arch/mips/jmr3927/rbhma3100/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/jmr3927/rbhma3100/irq.c 2005-02-28 16:56:41.000000000 +0100
-@@ -412,13 +412,13 @@ void __init arch_init_irq(void)
- }
-
- static hw_irq_controller jmr3927_irq_controller = {
-- "jmr3927_irq",
-- jmr3927_irq_startup,
-- jmr3927_irq_shutdown,
-- jmr3927_irq_enable,
-- jmr3927_irq_disable,
-- jmr3927_irq_ack,
-- jmr3927_irq_end,
-+ .typename = "jmr3927_irq",
-+ .startup = jmr3927_irq_startup,
-+ .shutdown = jmr3927_irq_shutdown,
-+ .enable = jmr3927_irq_enable,
-+ .disable = jmr3927_irq_disable,
-+ .ack = jmr3927_irq_ack,
-+ .end = jmr3927_irq_end,
- };
-
- void jmr3927_irq_init(u32 irq_base)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/jmr3927/rbhma3100/setup.c linux_HEAD/arch/mips/jmr3927/rbhma3100/setup.c
---- linux-2.6.12/arch/mips/jmr3927/rbhma3100/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/jmr3927/rbhma3100/setup.c 2005-07-01 12:09:17.000000000 +0200
-@@ -44,6 +44,11 @@
- #include <linux/ioport.h>
- #include <linux/param.h> /* for HZ */
- #include <linux/delay.h>
-+#ifdef CONFIG_SERIAL_TXX9
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#endif
-
- #include <asm/addrspace.h>
- #include <asm/time.h>
-@@ -193,7 +198,7 @@ static void jmr3927_board_init(void);
- extern struct resource pci_io_resource;
- extern struct resource pci_mem_resource;
-
--static void __init jmr3927_setup(void)
-+void __init plat_setup(void)
- {
- char *argptr;
-
-@@ -211,8 +216,8 @@ static void __init jmr3927_setup(void)
- */
- ioport_resource.start = pci_io_resource.start;
- ioport_resource.end = pci_io_resource.end;
-- iomem_resource.start = pci_mem_resource.start;
-- iomem_resource.end = pci_mem_resource.end;
-+ iomem_resource.start = 0;
-+ iomem_resource.end = 0xffffffff;
-
- /* Reboot on panic */
- panic_timeout = 180;
-@@ -265,18 +270,35 @@ static void __init jmr3927_setup(void)
- strcat(argptr, " ip=bootp");
- }
-
--#ifdef CONFIG_TXX927_SERIAL_CONSOLE
-+#ifdef CONFIG_SERIAL_TXX9
-+ {
-+ extern int early_serial_txx9_setup(struct uart_port *port);
-+ int i;
-+ struct uart_port req;
-+ for(i = 0; i < 2; i++) {
-+ memset(&req, 0, sizeof(req));
-+ req.line = i;
-+ req.iotype = UPIO_MEM;
-+ req.membase = (char *)TX3927_SIO_REG(i);
-+ req.mapbase = TX3927_SIO_REG(i);
-+ req.irq = i == 0 ?
-+ JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
-+ if (i == 0)
-+ req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-+ req.uartclk = JMR3927_IMCLK;
-+ early_serial_txx9_setup(&req);
-+ }
-+ }
-+#ifdef CONFIG_SERIAL_TXX9_CONSOLE
- argptr = prom_getcmdline();
- if ((argptr = strstr(argptr, "console=")) == NULL) {
- argptr = prom_getcmdline();
- strcat(argptr, " console=ttyS1,115200");
- }
- #endif
-+#endif
- }
-
--early_initcall(jmr3927_setup);
--
--
- static void tx3927_setup(void);
-
- #ifdef CONFIG_PCI
-@@ -335,7 +357,7 @@ static void __init jmr3927_board_init(vo
- jmr3927_io_dipsw());
- }
-
--static void __init tx3927_setup(void)
-+void __init plat_setup(void)
- {
- int i;
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/Makefile linux_HEAD/arch/mips/kernel/Makefile
---- linux-2.6.12/arch/mips/kernel/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/Makefile 2005-07-07 11:22:49.000000000 +0200
-@@ -11,11 +11,7 @@ obj-y += cpu-probe.o branch.o entry.o g
- binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
- irix5sys.o sysirix.o
-
--ifdef CONFIG_MODULES
--obj-y += mips_ksyms.o module.o
--obj-$(CONFIG_MIPS32) += module-elf32.o
--obj-$(CONFIG_MIPS64) += module-elf64.o
--endif
-+obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
-
- obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
- obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
-@@ -32,8 +28,8 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4
- obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
- obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
- obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
--obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
--obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
-+obj-$(CONFIG_CPU_MIPS32_R1) += r4k_fpu.o r4k_switch.o
-+obj-$(CONFIG_CPU_MIPS64_R1) += r4k_fpu.o r4k_switch.o
- obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
-
- obj-$(CONFIG_SMP) += smp.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/binfmt_elfn32.c linux_HEAD/arch/mips/kernel/binfmt_elfn32.c
---- linux-2.6.12/arch/mips/kernel/binfmt_elfn32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/binfmt_elfn32.c 2005-02-17 21:48:54.000000000 +0100
-@@ -52,7 +52,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N
-
- #include <asm/processor.h>
- #include <linux/module.h>
--#include <linux/config.h>
- #include <linux/elfcore.h>
- #include <linux/compat.h>
-
-@@ -116,4 +115,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf at linux-
- #undef MODULE_DESCRIPTION
- #undef MODULE_AUTHOR
-
-+#undef TASK_SIZE
-+#define TASK_SIZE TASK_SIZE32
-+
- #include "../../../fs/binfmt_elf.c"
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/binfmt_elfo32.c linux_HEAD/arch/mips/kernel/binfmt_elfo32.c
---- linux-2.6.12/arch/mips/kernel/binfmt_elfo32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/binfmt_elfo32.c 2005-02-17 21:48:54.000000000 +0100
-@@ -54,7 +54,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N
-
- #include <asm/processor.h>
- #include <linux/module.h>
--#include <linux/config.h>
- #include <linux/elfcore.h>
- #include <linux/compat.h>
-
-@@ -98,7 +97,7 @@ struct elf_prpsinfo32
- #define init_elf_binfmt init_elf32_binfmt
-
- #define jiffies_to_timeval jiffies_to_compat_timeval
--static __inline__ void
-+static inline void
- jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
- {
- /*
-@@ -113,21 +112,26 @@ jiffies_to_compat_timeval(unsigned long
- #undef ELF_CORE_COPY_REGS
- #define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs);
-
--void elf32_core_copy_regs(elf_gregset_t _dest, struct pt_regs *_regs)
-+void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
- {
- int i;
-
-- memset(_dest, 0, sizeof(elf_gregset_t));
--
-- /* XXXKW the 6 is from EF_REG0 in gdb/gdb/mips-linux-tdep.c, include/asm-mips/reg.h */
-- for (i=6; i<38; i++)
-- _dest[i] = (elf_greg_t) _regs->regs[i-6];
-- _dest[i++] = (elf_greg_t) _regs->lo;
-- _dest[i++] = (elf_greg_t) _regs->hi;
-- _dest[i++] = (elf_greg_t) _regs->cp0_epc;
-- _dest[i++] = (elf_greg_t) _regs->cp0_badvaddr;
-- _dest[i++] = (elf_greg_t) _regs->cp0_status;
-- _dest[i++] = (elf_greg_t) _regs->cp0_cause;
-+ for (i = 0; i < EF_R0; i++)
-+ grp[i] = 0;
-+ grp[EF_R0] = 0;
-+ for (i = 1; i <= 31; i++)
-+ grp[EF_R0 + i] = (elf_greg_t) regs->regs[i];
-+ grp[EF_R26] = 0;
-+ grp[EF_R27] = 0;
-+ grp[EF_LO] = (elf_greg_t) regs->lo;
-+ grp[EF_HI] = (elf_greg_t) regs->hi;
-+ grp[EF_CP0_EPC] = (elf_greg_t) regs->cp0_epc;
-+ grp[EF_CP0_BADVADDR] = (elf_greg_t) regs->cp0_badvaddr;
-+ grp[EF_CP0_STATUS] = (elf_greg_t) regs->cp0_status;
-+ grp[EF_CP0_CAUSE] = (elf_greg_t) regs->cp0_cause;
-+#ifdef EF_UNUSED0
-+ grp[EF_UNUSED0] = 0;
-+#endif
- }
-
- MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries");
-@@ -136,4 +140,7 @@ MODULE_AUTHOR("Ralf Baechle (ralf at linux-
- #undef MODULE_DESCRIPTION
- #undef MODULE_AUTHOR
-
-+#undef TASK_SIZE
-+#define TASK_SIZE TASK_SIZE32
-+
- #include "../../../fs/binfmt_elf.c"
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/branch.c linux_HEAD/arch/mips/kernel/branch.c
---- linux-2.6.12/arch/mips/kernel/branch.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/branch.c 2005-07-01 12:09:17.000000000 +0200
-@@ -12,6 +12,7 @@
- #include <asm/branch.h>
- #include <asm/cpu.h>
- #include <asm/cpu-features.h>
-+#include <asm/fpu.h>
- #include <asm/inst.h>
- #include <asm/ptrace.h>
- #include <asm/uaccess.h>
-@@ -21,7 +22,7 @@
- */
- int __compute_return_epc(struct pt_regs *regs)
- {
-- unsigned int *addr, bit, fcr31;
-+ unsigned int *addr, bit, fcr31, dspcontrol;
- long epc;
- union mips_instruction insn;
-
-@@ -98,6 +99,18 @@ int __compute_return_epc(struct pt_regs
- epc += 8;
- regs->cp0_epc = epc;
- break;
-+ case bposge32_op:
-+ if (!cpu_has_dsp)
-+ goto sigill;
-+
-+ dspcontrol = rddsp(0x01);
-+
-+ if (dspcontrol >= 32) {
-+ epc = epc + 4 + (insn.i_format.simmediate << 2);
-+ } else
-+ epc += 8;
-+ regs->cp0_epc = epc;
-+ break;
- }
- break;
-
-@@ -161,10 +174,13 @@ int __compute_return_epc(struct pt_regs
- * And now the FPA/cp1 branch instructions.
- */
- case cop1_op:
-- if (!cpu_has_fpu)
-- fcr31 = current->thread.fpu.soft.fcr31;
-- else
-+ preempt_disable();
-+ if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
-+ else
-+ fcr31 = current->thread.fpu.hard.fcr31;
-+ preempt_enable();
-+
- bit = (insn.i_format.rt >> 2);
- bit += (bit != 0);
- bit += 23;
-@@ -196,4 +212,9 @@ unaligned:
- printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
- force_sig(SIGBUS, current);
- return -EFAULT;
-+
-+sigill:
-+ printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
-+ force_sig(SIGBUS, current);
-+ return -EFAULT;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/cpu-probe.c linux_HEAD/arch/mips/kernel/cpu-probe.c
---- linux-2.6.12/arch/mips/kernel/cpu-probe.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/cpu-probe.c 2005-07-01 12:09:17.000000000 +0200
-@@ -2,9 +2,9 @@
- * Processor capabilities determination functions.
- *
- * Copyright (C) xxxx the Anonymous
-- * Copyright (C) 2003 Maciej W. Rozycki
-+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
- * Copyright (C) 1994 - 2003 Ralf Baechle
-- * Copyright (C) 2001 MIPS Inc.
-+ * Copyright (C) 2001, 2004 MIPS Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
-@@ -17,7 +17,6 @@
- #include <linux/ptrace.h>
- #include <linux/stddef.h>
-
--#include <asm/bugs.h>
- #include <asm/cpu.h>
- #include <asm/fpu.h>
- #include <asm/mipsregs.h>
-@@ -51,29 +50,25 @@ static void r4k_wait(void)
- ".set\tmips0");
- }
-
--/*
-- * The Au1xxx wait is available only if we run CONFIG_PM and
-- * the timer setup found we had a 32KHz counter available.
-- * There are still problems with functions that may call au1k_wait
-- * directly, but that will be discovered pretty quickly.
-- */
--extern void (*au1k_wait_ptr)(void);
-+/* The Au1xxx wait is available only if using 32khz counter or
-+ * external timer source, but specifically not CP0 Counter. */
-+int allow_au1k_wait;
-
--void au1k_wait(void)
-+static void au1k_wait(void)
- {
--#ifdef CONFIG_PM
- /* using the wait instruction makes CP0 counter unusable */
-- __asm__(".set\tmips3\n\t"
-+ __asm__(".set mips3\n\t"
-+ "cache 0x14, 0(%0)\n\t"
-+ "cache 0x14, 32(%0)\n\t"
-+ "sync\n\t"
-+ "nop\n\t"
- "wait\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
-- ".set\tmips0");
--#else
-- __asm__("nop\n\t"
-- "nop");
--#endif
-+ ".set mips0\n\t"
-+ : : "r" (au1k_wait));
- }
-
- static inline void check_wait(void)
-@@ -112,19 +107,17 @@ static inline void check_wait(void)
- cpu_wait = r4k_wait;
- printk(" available.\n");
- break;
--#ifdef CONFIG_PM
- case CPU_AU1000:
- case CPU_AU1100:
- case CPU_AU1500:
-- if (au1k_wait_ptr != NULL) {
-- cpu_wait = au1k_wait_ptr;
-+ case CPU_AU1550:
-+ case CPU_AU1200:
-+ if (allow_au1k_wait) {
-+ cpu_wait = au1k_wait;
- printk(" available.\n");
-- }
-- else {
-+ } else
- printk(" unavailable.\n");
-- }
- break;
--#endif
- default:
- printk(" unavailable.\n");
- break;
-@@ -427,65 +420,127 @@ static inline void cpu_probe_legacy(stru
- }
- }
-
--static inline void decode_config1(struct cpuinfo_mips *c)
-+static inline unsigned int decode_config0(struct cpuinfo_mips *c)
- {
-- unsigned long config0 = read_c0_config();
-- unsigned long config1;
-+ unsigned int config0;
-+ int isa;
-+
-+ config0 = read_c0_config();
-+
-+ if (((config0 & MIPS_CONF_MT) >> 7) == 1)
-+ c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
-+ isa = (config0 & MIPS_CONF_AT) >> 13;
-+ switch (isa) {
-+ case 0:
-+ c->isa_level = MIPS_CPU_ISA_M32;
-+ break;
-+ case 2:
-+ c->isa_level = MIPS_CPU_ISA_M64;
-+ break;
-+ default:
-+ panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
-+ }
-+
-+ return config0 & MIPS_CONF_M;
-+}
-
-- if ((config0 & (1 << 31)) == 0)
-- return; /* actually wort a panic() */
-+static inline unsigned int decode_config1(struct cpuinfo_mips *c)
-+{
-+ unsigned int config1;
-
-- /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
-- c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-- MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
- config1 = read_c0_config1();
-- if (config1 & (1 << 3))
-+
-+ if (config1 & MIPS_CONF1_MD)
-+ c->ases |= MIPS_ASE_MDMX;
-+ if (config1 & MIPS_CONF1_WR)
- c->options |= MIPS_CPU_WATCH;
-- if (config1 & (1 << 2))
-- c->options |= MIPS_CPU_MIPS16;
-- if (config1 & (1 << 1))
-+ if (config1 & MIPS_CONF1_CA)
-+ c->ases |= MIPS_ASE_MIPS16;
-+ if (config1 & MIPS_CONF1_EP)
- c->options |= MIPS_CPU_EJTAG;
-- if (config1 & 1) {
-+ if (config1 & MIPS_CONF1_FP) {
- c->options |= MIPS_CPU_FPU;
- c->options |= MIPS_CPU_32FPR;
- }
-+ if (cpu_has_tlb)
-+ c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
-+
-+ return config1 & MIPS_CONF_M;
-+}
-+
-+static inline unsigned int decode_config2(struct cpuinfo_mips *c)
-+{
-+ unsigned int config2;
-+
-+ config2 = read_c0_config2();
-+
-+ if (config2 & MIPS_CONF2_SL)
-+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
-+
-+ return config2 & MIPS_CONF_M;
-+}
-+
-+static inline unsigned int decode_config3(struct cpuinfo_mips *c)
-+{
-+ unsigned int config3;
-+
-+ config3 = read_c0_config3();
-+
-+ if (config3 & MIPS_CONF3_SM)
-+ c->ases |= MIPS_ASE_SMARTMIPS;
-+ if (config3 & MIPS_CONF3_DSP)
-+ c->ases |= MIPS_ASE_DSP;
-+
-+ return config3 & MIPS_CONF_M;
-+}
-+
-+static inline void decode_configs(struct cpuinfo_mips *c)
-+{
-+ /* MIPS32 or MIPS64 compliant CPU. */
-+ c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-+ MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
-+
- c->scache.flags = MIPS_CACHE_NOT_PRESENT;
-
-- c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
-+ /* Read Config registers. */
-+ if (!decode_config0(c))
-+ return; /* actually worth a panic() */
-+ if (!decode_config1(c))
-+ return;
-+ if (!decode_config2(c))
-+ return;
-+ if (!decode_config3(c))
-+ return;
- }
-
- static inline void cpu_probe_mips(struct cpuinfo_mips *c)
- {
-- decode_config1(c);
-+ decode_configs(c);
- switch (c->processor_id & 0xff00) {
- case PRID_IMP_4KC:
- c->cputype = CPU_4KC;
-- c->isa_level = MIPS_CPU_ISA_M32;
- break;
- case PRID_IMP_4KEC:
- c->cputype = CPU_4KEC;
-- c->isa_level = MIPS_CPU_ISA_M32;
-+ break;
-+ case PRID_IMP_4KECR2:
-+ c->cputype = CPU_4KEC;
- break;
- case PRID_IMP_4KSC:
- c->cputype = CPU_4KSC;
-- c->isa_level = MIPS_CPU_ISA_M32;
- break;
- case PRID_IMP_5KC:
- c->cputype = CPU_5KC;
-- c->isa_level = MIPS_CPU_ISA_M64;
- break;
- case PRID_IMP_20KC:
- c->cputype = CPU_20KC;
-- c->isa_level = MIPS_CPU_ISA_M64;
- break;
- case PRID_IMP_24K:
-+ case PRID_IMP_24KE:
- c->cputype = CPU_24K;
-- c->isa_level = MIPS_CPU_ISA_M32;
- break;
- case PRID_IMP_25KF:
- c->cputype = CPU_25KF;
-- c->isa_level = MIPS_CPU_ISA_M64;
- /* Probe for L2 cache */
- c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
- break;
-@@ -494,7 +549,7 @@ static inline void cpu_probe_mips(struct
-
- static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
- {
-- decode_config1(c);
-+ decode_configs(c);
- switch (c->processor_id & 0xff00) {
- case PRID_IMP_AU1_REV1:
- case PRID_IMP_AU1_REV2:
-@@ -511,29 +566,26 @@ static inline void cpu_probe_alchemy(str
- case 3:
- c->cputype = CPU_AU1550;
- break;
-+ case 4:
-+ c->cputype = CPU_AU1200;
-+ break;
- default:
- panic("Unknown Au Core!");
- break;
- }
-- c->isa_level = MIPS_CPU_ISA_M32;
- break;
- }
- }
-
- static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
- {
-- decode_config1(c);
-+ decode_configs(c);
- switch (c->processor_id & 0xff00) {
- case PRID_IMP_SB1:
- c->cputype = CPU_SB1;
-- c->isa_level = MIPS_CPU_ISA_M64;
-- c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-- MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
-- MIPS_CPU_WATCH | MIPS_CPU_LLSC;
--#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
-+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
- /* FPU in pass1 is known to have issues. */
-- c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
-+ c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
- #endif
- break;
- }
-@@ -541,14 +593,10 @@ static inline void cpu_probe_sibyte(stru
-
- static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
- {
-- decode_config1(c);
-+ decode_configs(c);
- switch (c->processor_id & 0xff00) {
- case PRID_IMP_SR71000:
- c->cputype = CPU_SR71000;
-- c->isa_level = MIPS_CPU_ISA_M64;
-- c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-- MIPS_CPU_4KTLB | MIPS_CPU_FPU |
-- MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
- c->scache.ways = 8;
- c->tlbsize = 64;
- break;
-@@ -577,15 +625,21 @@ __init void cpu_probe(void)
- case PRID_COMP_SIBYTE:
- cpu_probe_sibyte(c);
- break;
--
- case PRID_COMP_SANDCRAFT:
- cpu_probe_sandcraft(c);
- break;
- default:
- c->cputype = CPU_UNKNOWN;
- }
-- if (c->options & MIPS_CPU_FPU)
-+ if (c->options & MIPS_CPU_FPU) {
- c->fpu_id = cpu_get_fpu_id();
-+
-+ if (c->isa_level == MIPS_CPU_ISA_M32 ||
-+ c->isa_level == MIPS_CPU_ISA_M64) {
-+ if (c->fpu_id & MIPS_FPIR_3D)
-+ c->ases |= MIPS_ASE_MIPS3D;
-+ }
-+ }
- }
-
- __init void cpu_report(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/dma-no-isa.c linux_HEAD/arch/mips/kernel/dma-no-isa.c
---- linux-2.6.12/arch/mips/kernel/dma-no-isa.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/kernel/dma-no-isa.c 2005-02-17 21:48:54.000000000 +0100
-@@ -0,0 +1,28 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2004 by Ralf Baechle
-+ *
-+ * Dummy ISA DMA functions for systems that don't have ISA but share drivers
-+ * with ISA such as legacy free PCI.
-+ */
-+#include <linux/errno.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+
-+DEFINE_SPINLOCK(dma_spin_lock);
-+
-+int request_dma(unsigned int dmanr, const char * device_id)
-+{
-+ return -EINVAL;
-+}
-+
-+void free_dma(unsigned int dmanr)
-+{
-+}
-+
-+EXPORT_SYMBOL(dma_spin_lock);
-+EXPORT_SYMBOL(request_dma);
-+EXPORT_SYMBOL(free_dma);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/entry.S linux_HEAD/arch/mips/kernel/entry.S
---- linux-2.6.12/arch/mips/kernel/entry.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/entry.S 2005-03-04 20:36:08.000000000 +0100
-@@ -19,11 +19,11 @@
- #include <asm/war.h>
-
- #ifdef CONFIG_PREEMPT
-- .macro preempt_stop reg=t0
-+ .macro preempt_stop
- .endm
- #else
-- .macro preempt_stop reg=t0
-- local_irq_disable \reg
-+ .macro preempt_stop
-+ local_irq_disable
- .endm
- #define resume_kernel restore_all
- #endif
-@@ -37,17 +37,18 @@ FEXPORT(ret_from_irq)
- andi t0, t0, KU_USER
- beqz t0, resume_kernel
-
--FEXPORT(resume_userspace)
-- local_irq_disable t0 # make sure we dont miss an
-+resume_userspace:
-+ local_irq_disable # make sure we dont miss an
- # interrupt setting need_resched
- # between sampling and return
- LONG_L a2, TI_FLAGS($28) # current->work
-- andi a2, _TIF_WORK_MASK # (ignoring syscall_trace)
-- bnez a2, work_pending
-+ andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
-+ bnez t0, work_pending
- j restore_all
-
- #ifdef CONFIG_PREEMPT
--ENTRY(resume_kernel)
-+resume_kernel:
-+ local_irq_disable
- lw t0, TI_PRE_COUNT($28)
- bnez t0, restore_all
- need_resched:
-@@ -57,12 +58,7 @@ need_resched:
- LONG_L t0, PT_STATUS(sp) # Interrupts off?
- andi t0, 1
- beqz t0, restore_all
-- li t0, PREEMPT_ACTIVE
-- sw t0, TI_PRE_COUNT($28)
-- local_irq_enable t0
-- jal schedule
-- sw zero, TI_PRE_COUNT($28)
-- local_irq_disable t0
-+ jal preempt_schedule_irq
- b need_resched
- #endif
-
-@@ -88,13 +84,13 @@ FEXPORT(restore_partial) # restore part
- RESTORE_SP_AND_RET
- .set at
-
--FEXPORT(work_pending)
-- andi t0, a2, _TIF_NEED_RESCHED
-+work_pending:
-+ andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
- beqz t0, work_notifysig
- work_resched:
- jal schedule
-
-- local_irq_disable t0 # make sure need_resched and
-+ local_irq_disable # make sure need_resched and
- # signals dont change between
- # sampling and return
- LONG_L a2, TI_FLAGS($28)
-@@ -113,11 +109,10 @@ work_notifysig: # deal with pending s
-
- FEXPORT(syscall_exit_work_partial)
- SAVE_STATIC
--FEXPORT(syscall_exit_work)
-- LONG_L t0, TI_FLAGS($28)
-- li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
-- and t0, t1
-- beqz t0, work_pending # trace bit is set
-+syscall_exit_work:
-+ li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
-+ and t0, a2 # a2 is preloaded with TI_FLAGS
-+ beqz t0, work_pending # trace bit set?
- local_irq_enable # could let do_syscall_trace()
- # call schedule() instead
- move a0, sp
-@@ -128,28 +123,25 @@ FEXPORT(syscall_exit_work)
- /*
- * Common spurious interrupt handler.
- */
-- .text
-- .align 5
- LEAF(spurious_interrupt)
- /*
- * Someone tried to fool us by sending an interrupt but we
- * couldn't find a cause for it.
- */
-+ PTR_LA t1, irq_err_count
- #ifdef CONFIG_SMP
-- lui t1, %hi(irq_err_count)
--1: ll t0, %lo(irq_err_count)(t1)
-+1: ll t0, (t1)
- addiu t0, 1
-- sc t0, %lo(irq_err_count)(t1)
-+ sc t0, (t1)
- #if R10000_LLSC_WAR
- beqzl t0, 1b
- #else
- beqz t0, 1b
- #endif
- #else
-- lui t1, %hi(irq_err_count)
-- lw t0, %lo(irq_err_count)(t1)
-+ lw t0, (t1)
- addiu t0, 1
-- sw t0, %lo(irq_err_count)(t1)
-+ sw t0, (t1)
- #endif
- j ret_from_irq
- END(spurious_interrupt)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/gdb-stub.c linux_HEAD/arch/mips/kernel/gdb-stub.c
---- linux-2.6.12/arch/mips/kernel/gdb-stub.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/gdb-stub.c 2005-02-17 21:48:54.000000000 +0100
-@@ -176,7 +176,7 @@ int kgdb_enabled;
- /*
- * spin locks for smp case
- */
--static spinlock_t kgdb_lock = SPIN_LOCK_UNLOCKED;
-+static DEFINE_SPINLOCK(kgdb_lock);
- static spinlock_t kgdb_cpulock[NR_CPUS] = { [0 ... NR_CPUS-1] = SPIN_LOCK_UNLOCKED};
-
- /*
-@@ -637,15 +637,18 @@ static struct gdb_bp_save async_bp;
- * and only one can be active at a time.
- */
- extern spinlock_t smp_call_lock;
-+
- void set_async_breakpoint(unsigned long *epc)
- {
- /* skip breaking into userland */
- if ((*epc & 0x80000000) == 0)
- return;
-
-+#ifdef CONFIG_SMP
- /* avoid deadlock if someone is make IPC */
- if (spin_is_locked(&smp_call_lock))
- return;
-+#endif
-
- async_bp.addr = *epc;
- *epc = (unsigned long)async_breakpoint;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/genex.S linux_HEAD/arch/mips/kernel/genex.S
---- linux-2.6.12/arch/mips/kernel/genex.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/genex.S 2005-07-01 12:09:17.000000000 +0200
-@@ -82,7 +82,7 @@ NESTED(except_vec3_r4000, 0, sp)
- li k0, 14<<2
- beq k1, k0, handle_vcei
- #ifdef CONFIG_MIPS64
-- dsll k1, k1, 1
-+ dsll k1, k1, 1
- #endif
- .set pop
- PTR_L k0, exception_handlers(k1)
-@@ -90,17 +90,17 @@ NESTED(except_vec3_r4000, 0, sp)
-
- /*
- * Big shit, we now may have two dirty primary cache lines for the same
-- * physical address. We can savely invalidate the line pointed to by
-+ * physical address. We can safely invalidate the line pointed to by
- * c0_badvaddr because after return from this exception handler the
- * load / store will be re-executed.
- */
- handle_vced:
-- DMFC0 k0, CP0_BADVADDR
-+ MFC0 k0, CP0_BADVADDR
- li k1, -4 # Is this ...
- and k0, k1 # ... really needed?
- mtc0 zero, CP0_TAGLO
-- cache Index_Store_Tag_D,(k0)
-- cache Hit_Writeback_Inv_SD,(k0)
-+ cache Index_Store_Tag_D, (k0)
-+ cache Hit_Writeback_Inv_SD, (k0)
- #ifdef CONFIG_PROC_FS
- PTR_LA k0, vced_count
- lw k1, (k0)
-@@ -291,6 +291,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
- BUILD_HANDLER mdmx mdmx sti silent /* #22 */
- BUILD_HANDLER watch watch sti verbose /* #23 */
- BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
-+ BUILD_HANDLER dsp dsp sti silent /* #26 */
- BUILD_HANDLER reserved reserved sti verbose /* others */
-
- #ifdef CONFIG_MIPS64
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/genrtc.c linux_HEAD/arch/mips/kernel/genrtc.c
---- linux-2.6.12/arch/mips/kernel/genrtc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/genrtc.c 2005-02-17 21:48:54.000000000 +0100
-@@ -14,7 +14,7 @@
- #include <asm/rtc.h>
- #include <asm/time.h>
-
--static spinlock_t mips_rtc_lock = SPIN_LOCK_UNLOCKED;
-+static DEFINE_SPINLOCK(mips_rtc_lock);
-
- unsigned int get_rtc_time(struct rtc_time *time)
- {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/head.S linux_HEAD/arch/mips/kernel/head.S
---- linux-2.6.12/arch/mips/kernel/head.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/head.S 2005-03-28 22:29:17.000000000 +0200
-@@ -157,6 +157,7 @@ NESTED(kernel_entry, 16, sp) # kernel
- LONG_S a2, fw_arg2
- LONG_S a3, fw_arg3
-
-+ MTC0 zero, CP0_CONTEXT # clear context register
- PTR_LA $28, init_thread_union
- PTR_ADDIU sp, $28, _THREAD_SIZE - 32
- set_saved_sp sp, t0, t1
-@@ -200,19 +201,13 @@ NESTED(smp_bootstrap, 16, sp)
- .comm fw_arg2, SZREG, SZREG
- .comm fw_arg3, SZREG, SZREG
-
-- .macro page name, order=0
-- .globl \name
--\name: .size \name, (_PAGE_SIZE << \order)
-- .org . + (_PAGE_SIZE << \order)
-- .type \name, @object
-+ .macro page name, order
-+ .comm \name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order)
- .endm
-
-- .data
-- .align PAGE_SHIFT
--
- /*
-- * ... but on 64-bit we've got three-level pagetables with a
-- * slightly different layout ...
-+ * On 64-bit we've got three-level pagetables with a slightly
-+ * different layout ...
- */
- page swapper_pg_dir, _PGD_ORDER
- #ifdef CONFIG_MIPS64
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/i8259.c linux_HEAD/arch/mips/kernel/i8259.c
---- linux-2.6.12/arch/mips/kernel/i8259.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/i8259.c 2005-03-01 22:49:39.000000000 +0100
-@@ -31,7 +31,7 @@ void disable_8259A_irq(unsigned int irq)
- * moves to arch independent land
- */
-
--spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
-+DEFINE_SPINLOCK(i8259A_lock);
-
- static void end_8259A_irq (unsigned int irq)
- {
-@@ -52,14 +52,13 @@ static unsigned int startup_8259A_irq(un
- }
-
- static struct hw_interrupt_type i8259A_irq_type = {
-- "XT-PIC",
-- startup_8259A_irq,
-- shutdown_8259A_irq,
-- enable_8259A_irq,
-- disable_8259A_irq,
-- mask_and_ack_8259A,
-- end_8259A_irq,
-- NULL
-+ .typename = "XT-PIC",
-+ .startup = startup_8259A_irq,
-+ .shutdown = shutdown_8259A_irq,
-+ .enable = enable_8259A_irq,
-+ .disable = disable_8259A_irq,
-+ .ack = mask_and_ack_8259A,
-+ .end = end_8259A_irq,
- };
-
- /*
-@@ -322,7 +321,7 @@ void __init init_i8259_irqs (void)
-
- for (i = 0; i < 16; i++) {
- irq_desc[i].status = IRQ_DISABLED;
-- irq_desc[i].action = 0;
-+ irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].handler = &i8259A_irq_type;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irixelf.c linux_HEAD/arch/mips/kernel/irixelf.c
---- linux-2.6.12/arch/mips/kernel/irixelf.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irixelf.c 2005-04-08 22:40:40.000000000 +0200
-@@ -8,7 +8,7 @@
- *
- * Copyright (C) 1993 - 1994 Eric Youngdale <ericy at cais.com>
- * Copyright (C) 1996 - 2004 David S. Miller <dm at engr.sgi.com>
-- * Copyright (C) 2004 Steven J. Hill <sjhill at realitydiluted.com>
-+ * Copyright (C) 2004 - 2005 Steven J. Hill <sjhill at realitydiluted.com>
- */
- #include <linux/module.h>
- #include <linux/fs.h>
-@@ -31,15 +31,16 @@
- #include <linux/elfcore.h>
- #include <linux/smp_lock.h>
-
--#include <asm/uaccess.h>
- #include <asm/mipsregs.h>
-+#include <asm/namei.h>
- #include <asm/prctl.h>
-+#include <asm/uaccess.h>
-
- #define DLINFO_ITEMS 12
-
- #include <linux/elf.h>
-
--#undef DEBUG_ELF
-+#undef DEBUG
-
- static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs);
- static int load_irix_library(struct file *);
-@@ -55,7 +56,7 @@ static struct linux_binfmt irix_format =
- #define elf_addr_t unsigned long
- #endif
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- /* Debugging routines. */
- static char *get_elf_p_type(Elf32_Word p_type)
- {
-@@ -120,7 +121,7 @@ static void dump_phdrs(struct elf_phdr *
- print_phdr(i, ep);
- }
- }
--#endif /* (DEBUG_ELF) */
-+#endif /* DEBUG */
-
- static void set_brk(unsigned long start, unsigned long end)
- {
-@@ -146,20 +147,20 @@ static void padzero(unsigned long elf_bs
- nbyte = elf_bss & (PAGE_SIZE-1);
- if (nbyte) {
- nbyte = PAGE_SIZE - nbyte;
-- clear_user((void *) elf_bss, nbyte);
-+ clear_user((void __user *) elf_bss, nbyte);
- }
- }
-
--unsigned long * create_irix_tables(char * p, int argc, int envc,
-- struct elfhdr * exec, unsigned int load_addr,
-- unsigned int interp_load_addr,
-- struct pt_regs *regs, struct elf_phdr *ephdr)
-+static unsigned long * create_irix_tables(char * p, int argc, int envc,
-+ struct elfhdr * exec, unsigned int load_addr,
-+ unsigned int interp_load_addr, struct pt_regs *regs,
-+ struct elf_phdr *ephdr)
- {
- elf_addr_t *argv;
- elf_addr_t *envp;
- elf_addr_t *sp, *csp;
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- printk("create_irix_tables: p[%p] argc[%d] envc[%d] "
- "load_addr[%08x] interp_load_addr[%08x]\n",
- p, argc, envc, load_addr, interp_load_addr);
-@@ -248,14 +249,13 @@ static unsigned int load_irix_interp(str
- last_bss = 0;
- error = load_addr = 0;
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- print_elfhdr(interp_elf_ex);
- #endif
-
- /* First of all, some simple consistency checks */
- if ((interp_elf_ex->e_type != ET_EXEC &&
- interp_elf_ex->e_type != ET_DYN) ||
-- !irix_elf_check_arch(interp_elf_ex) ||
- !interpreter->f_op->mmap) {
- printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type);
- return 0xffffffff;
-@@ -290,7 +290,7 @@ static unsigned int load_irix_interp(str
- (char *) elf_phdata,
- sizeof(struct elf_phdr) * interp_elf_ex->e_phnum);
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- dump_phdrs(elf_phdata, interp_elf_ex->e_phnum);
- #endif
-
-@@ -306,13 +306,11 @@ static unsigned int load_irix_interp(str
- elf_type |= MAP_FIXED;
- vaddr = eppnt->p_vaddr;
-
--#ifdef DEBUG_ELF
-- printk("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
-+ pr_debug("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
- interpreter, vaddr,
- (unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)),
- (unsigned long) elf_prot, (unsigned long) elf_type,
- (unsigned long) (eppnt->p_offset & 0xfffff000));
--#endif
- down_write(¤t->mm->mmap_sem);
- error = do_mmap(interpreter, vaddr,
- eppnt->p_filesz + (eppnt->p_vaddr & 0xfff),
-@@ -324,14 +322,10 @@ static unsigned int load_irix_interp(str
- printk("Aieee IRIX interp mmap error=%d\n", error);
- break; /* Real error */
- }
--#ifdef DEBUG_ELF
-- printk("error=%08lx ", (unsigned long) error);
--#endif
-+ pr_debug("error=%08lx ", (unsigned long) error);
- if(!load_addr && interp_elf_ex->e_type == ET_DYN) {
- load_addr = error;
--#ifdef DEBUG_ELF
-- printk("load_addr = error ");
--#endif
-+ pr_debug("load_addr = error ");
- }
-
- /* Find the end of the file mapping for this phdr, and keep
-@@ -345,17 +339,13 @@ static unsigned int load_irix_interp(str
- */
- k = eppnt->p_memsz + eppnt->p_vaddr;
- if(k > last_bss) last_bss = k;
--#ifdef DEBUG_ELF
-- printk("\n");
--#endif
-+ pr_debug("\n");
- }
- }
-
- /* Now use mmap to map the library into memory. */
- if(error < 0 && error > -1024) {
--#ifdef DEBUG_ELF
-- printk("got error %d\n", error);
--#endif
-+ pr_debug("got error %d\n", error);
- kfree(elf_phdata);
- return 0xffffffff;
- }
-@@ -365,16 +355,12 @@ static unsigned int load_irix_interp(str
- * that there are zero-mapped pages up to and including the
- * last bss page.
- */
--#ifdef DEBUG_ELF
-- printk("padzero(%08lx) ", (unsigned long) (elf_bss));
--#endif
-+ pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss));
- padzero(elf_bss);
- len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */
-
--#ifdef DEBUG_ELF
-- printk("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss,
-- (unsigned long) len);
--#endif
-+ pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss,
-+ (unsigned long) len);
-
- /* Map the last of the bss segment */
- if (last_bss > len) {
-@@ -396,12 +382,7 @@ static int verify_binary(struct elfhdr *
-
- /* First of all, some simple consistency checks */
- if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) ||
-- !irix_elf_check_arch(ehp) || !bprm->file->f_op->mmap) {
-- return -ENOEXEC;
-- }
--
-- /* Only support MIPS ARCH2 or greater IRIX binaries for now. */
-- if(!(ehp->e_flags & EF_MIPS_ARCH) && !(ehp->e_flags & 0x04)) {
-+ !bprm->file->f_op->mmap) {
- return -ENOEXEC;
- }
-
-@@ -411,16 +392,17 @@ static int verify_binary(struct elfhdr *
- * XXX all registers as 64bits on cpu's capable of this at
- * XXX exception time plus frob the XTLB exception vector.
- */
-- if((ehp->e_flags & 0x20)) {
-+ if((ehp->e_flags & EF_MIPS_ABI2))
- return -ENOEXEC;
-- }
-
-- return 0; /* It's ok. */
-+ return 0;
- }
-
--#define IRIX_INTERP_PREFIX "/usr/gnemul/irix"
--
--/* Look for an IRIX ELF interpreter. */
-+/*
-+ * This is where the detailed check is performed. Irix binaries
-+ * use interpreters with 'libc.so' in the name, so this function
-+ * can differentiate between Linux and Irix binaries.
-+ */
- static inline int look_for_irix_interpreter(char **name,
- struct file **interpreter,
- struct elfhdr *interp_elf_ex,
-@@ -440,12 +422,13 @@ static inline int look_for_irix_interpre
- if (*name != NULL)
- goto out;
-
-- *name = kmalloc((epp->p_filesz + strlen(IRIX_INTERP_PREFIX)),
-- GFP_KERNEL);
-+ *name = (char *) kmalloc((epp->p_filesz +
-+ strlen(IRIX_EMUL)),
-+ GFP_KERNEL);
- if (!*name)
- return -ENOMEM;
-
-- strcpy(*name, IRIX_INTERP_PREFIX);
-+ strcpy(*name, IRIX_EMUL);
- retval = kernel_read(bprm->file, epp->p_offset, (*name + 16),
- epp->p_filesz);
- if (retval < 0)
-@@ -562,7 +545,7 @@ static inline int map_interpreter(struct
- * process and the system, here we map the page and fill the
- * structure
- */
--void irix_map_prda_page (void)
-+static void irix_map_prda_page(void)
- {
- unsigned long v;
- struct prda *pp;
-@@ -601,14 +584,33 @@ static int load_irix_binary(struct linux
-
- load_addr = 0;
- has_interp = has_ephdr = 0;
-- elf_ihdr = elf_ephdr = 0;
-+ elf_ihdr = elf_ephdr = NULL;
- elf_ex = *((struct elfhdr *) bprm->buf);
- retval = -ENOEXEC;
-
- if (verify_binary(&elf_ex, bprm))
- goto out;
-
--#ifdef DEBUG_ELF
-+ /*
-+ * Telling -o32 static binaries from Linux and Irix apart from each
-+ * other is difficult. There are 2 differences to be noted for static
-+ * binaries from the 2 operating systems:
-+ *
-+ * 1) Irix binaries have their .text section before their .init
-+ * section. Linux binaries are just the opposite.
-+ *
-+ * 2) Irix binaries usually have <= 12 sections and Linux
-+ * binaries have > 20.
-+ *
-+ * We will use Method #2 since Method #1 would require us to read in
-+ * the section headers which is way too much overhead. This appears
-+ * to work for everything we have ran into so far. If anyone has a
-+ * better method to tell the binaries apart, I'm listening.
-+ */
-+ if (elf_ex.e_shnum > 20)
-+ goto out;
-+
-+#ifdef DEBUG
- print_elfhdr(&elf_ex);
- #endif
-
-@@ -623,11 +625,10 @@ static int load_irix_binary(struct linux
- }
-
- retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size);
--
- if (retval < 0)
- goto out_free_ph;
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- dump_phdrs(elf_phdata, elf_ex.e_phnum);
- #endif
-
-@@ -644,9 +645,8 @@ static int load_irix_binary(struct linux
- break;
- };
- }
--#ifdef DEBUG_ELF
-- printk("\n");
--#endif
-+
-+ pr_debug("\n");
-
- elf_bss = 0;
- elf_brk = 0;
-@@ -657,12 +657,19 @@ static int load_irix_binary(struct linux
- end_code = 0;
- end_data = 0;
-
-- retval = look_for_irix_interpreter(&elf_interpreter,
-- &interpreter,
-+ /*
-+ * If we get a return value, we change the value to be ENOEXEC
-+ * so that we can exit gracefully and the main binary format
-+ * search loop in 'fs/exec.c' will move onto the next handler
-+ * which should be the normal ELF binary handler.
-+ */
-+ retval = look_for_irix_interpreter(&elf_interpreter, &interpreter,
- &interp_elf_ex, elf_phdata, bprm,
- elf_ex.e_phnum);
-- if (retval)
-+ if (retval) {
-+ retval = -ENOEXEC;
- goto out_free_file;
-+ }
-
- if (elf_interpreter) {
- retval = verify_irix_interpreter(&interp_elf_ex);
-@@ -746,18 +753,16 @@ static int load_irix_binary(struct linux
- * IRIX maps a page at 0x200000 which holds some system
- * information. Programs depend on this.
- */
-- irix_map_prda_page ();
-+ irix_map_prda_page();
-
- padzero(elf_bss);
-
--#ifdef DEBUG_ELF
-- printk("(start_brk) %lx\n" , (long) current->mm->start_brk);
-- printk("(end_code) %lx\n" , (long) current->mm->end_code);
-- printk("(start_code) %lx\n" , (long) current->mm->start_code);
-- printk("(end_data) %lx\n" , (long) current->mm->end_data);
-- printk("(start_stack) %lx\n" , (long) current->mm->start_stack);
-- printk("(brk) %lx\n" , (long) current->mm->brk);
--#endif
-+ pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk);
-+ pr_debug("(end_code) %lx\n" , (long) current->mm->end_code);
-+ pr_debug("(start_code) %lx\n" , (long) current->mm->start_code);
-+ pr_debug("(end_data) %lx\n" , (long) current->mm->end_data);
-+ pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack);
-+ pr_debug("(brk) %lx\n" , (long) current->mm->brk);
-
- #if 0 /* XXX No fucking way dude... */
- /* Why this, you ask??? Well SVr4 maps page 0 as read-only,
-@@ -813,7 +818,7 @@ static int load_irix_library(struct file
-
- /* First of all, some simple consistency checks. */
- if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 ||
-- !irix_elf_check_arch(&elf_ex) || !file->f_op->mmap)
-+ !file->f_op->mmap)
- return -ENOEXEC;
-
- /* Now read in all of the header information. */
-@@ -874,35 +879,36 @@ static int load_irix_library(struct file
- * phdrs there are in the USER_PHDRP array. We return the vaddr the
- * first phdr was successfully mapped to.
- */
--unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt)
-+unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt)
- {
-- struct elf_phdr *hp;
-+ unsigned long type, vaddr, filesz, offset, flags;
-+ struct elf_phdr __user *hp;
- struct file *filp;
- int i, retval;
-
--#ifdef DEBUG_ELF
-- printk("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n",
-- fd, user_phdrp, cnt);
--#endif
-+ pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n",
-+ fd, user_phdrp, cnt);
-
- /* First get the verification out of the way. */
- hp = user_phdrp;
- if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) {
--#ifdef DEBUG_ELF
-- printk("irix_mapelf: access_ok fails!\n");
--#endif
-+ pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n");
-+
- return -EFAULT;
- }
-
--#ifdef DEBUG_ELF
-+#ifdef DEBUG
- dump_phdrs(user_phdrp, cnt);
- #endif
-
-- for(i = 0; i < cnt; i++, hp++)
-- if(hp->p_type != PT_LOAD) {
-+ for (i = 0; i < cnt; i++, hp++) {
-+ if (__get_user(type, &hp->p_type))
-+ return -EFAULT;
-+ if (type != PT_LOAD) {
- printk("irix_mapelf: One section is not PT_LOAD!\n");
- return -ENOEXEC;
- }
-+ }
-
- filp = fget(fd);
- if (!filp)
-@@ -917,29 +923,40 @@ unsigned long irix_mapelf(int fd, struct
- for(i = 0; i < cnt; i++, hp++) {
- int prot;
-
-- prot = (hp->p_flags & PF_R) ? PROT_READ : 0;
-- prot |= (hp->p_flags & PF_W) ? PROT_WRITE : 0;
-- prot |= (hp->p_flags & PF_X) ? PROT_EXEC : 0;
-+ retval = __get_user(vaddr, &hp->p_vaddr);
-+ retval |= __get_user(filesz, &hp->p_filesz);
-+ retval |= __get_user(offset, &hp->p_offset);
-+ retval |= __get_user(flags, &hp->p_flags);
-+ if (retval)
-+ return retval;
-+
-+ prot = (flags & PF_R) ? PROT_READ : 0;
-+ prot |= (flags & PF_W) ? PROT_WRITE : 0;
-+ prot |= (flags & PF_X) ? PROT_EXEC : 0;
-+
- down_write(¤t->mm->mmap_sem);
-- retval = do_mmap(filp, (hp->p_vaddr & 0xfffff000),
-- (hp->p_filesz + (hp->p_vaddr & 0xfff)),
-+ retval = do_mmap(filp, (vaddr & 0xfffff000),
-+ (filesz + (vaddr & 0xfff)),
- prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE),
-- (hp->p_offset & 0xfffff000));
-+ (offset & 0xfffff000));
- up_write(¤t->mm->mmap_sem);
-
-- if(retval != (hp->p_vaddr & 0xfffff000)) {
-+ if (retval != (vaddr & 0xfffff000)) {
- printk("irix_mapelf: do_mmap fails with %d!\n", retval);
- fput(filp);
- return retval;
- }
- }
-
--#ifdef DEBUG_ELF
-- printk("irix_mapelf: Success, returning %08lx\n",
-- (unsigned long) user_phdrp->p_vaddr);
--#endif
-+ pr_debug("irix_mapelf: Success, returning %08lx\n",
-+ (unsigned long) user_phdrp->p_vaddr);
-+
- fput(filp);
-- return user_phdrp->p_vaddr;
-+
-+ if (__get_user(vaddr, &user_phdrp->p_vaddr))
-+ return -EFAULT;
-+
-+ return vaddr;
- }
-
- /*
-@@ -952,9 +969,9 @@ unsigned long irix_mapelf(int fd, struct
- /* These are the only things you should do on a core-file: use only these
- * functions to write out all the necessary info.
- */
--static int dump_write(struct file *file, const void *addr, int nr)
-+static int dump_write(struct file *file, const void __user *addr, int nr)
- {
-- return file->f_op->write(file, addr, nr, &file->f_pos) == nr;
-+ return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr;
- }
-
- static int dump_seek(struct file *file, off_t off)
-@@ -1073,7 +1090,7 @@ static int irix_core_dump(long signr, st
- /* Count what's needed to dump, up to the limit of coredump size. */
- segs = 0;
- size = 0;
-- for(vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) {
-+ for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) {
- if (maydump(vma))
- {
- int sz = vma->vm_end-vma->vm_start;
-@@ -1187,9 +1204,9 @@ static int irix_core_dump(long signr, st
-
- len = current->mm->arg_end - current->mm->arg_start;
- len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len;
-- copy_from_user(&psinfo.pr_psargs,
-- (const char *)current->mm->arg_start, len);
-- for(i = 0; i < len; i++)
-+ (void *) copy_from_user(&psinfo.pr_psargs,
-+ (const char __user *)current->mm->arg_start, len);
-+ for (i = 0; i < len; i++)
- if (psinfo.pr_psargs[i] == 0)
- psinfo.pr_psargs[i] = ' ';
- psinfo.pr_psargs[len] = 0;
-@@ -1256,8 +1273,10 @@ static int irix_core_dump(long signr, st
- phdr.p_memsz = sz;
- offset += phdr.p_filesz;
- phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0;
-- if (vma->vm_flags & VM_WRITE) phdr.p_flags |= PF_W;
-- if (vma->vm_flags & VM_EXEC) phdr.p_flags |= PF_X;
-+ if (vma->vm_flags & VM_WRITE)
-+ phdr.p_flags |= PF_W;
-+ if (vma->vm_flags & VM_EXEC)
-+ phdr.p_flags |= PF_X;
- phdr.p_align = PAGE_SIZE;
-
- DUMP_WRITE(&phdr, sizeof(phdr));
-@@ -1283,7 +1302,7 @@ static int irix_core_dump(long signr, st
- #ifdef DEBUG
- printk("elf_core_dump: writing %08lx %lx\n", addr, len);
- #endif
-- DUMP_WRITE((void *)addr, len);
-+ DUMP_WRITE((void __user *)addr, len);
- }
-
- if ((off_t) file->f_pos != offset) {
-@@ -1299,7 +1318,7 @@ end_coredump:
-
- static int __init init_irix_binfmt(void)
- {
-- int init_inventory(void);
-+ extern int init_inventory(void);
- extern asmlinkage unsigned long sys_call_table;
- extern asmlinkage unsigned long sys_call_table_irix5;
-
-@@ -1318,7 +1337,9 @@ static int __init init_irix_binfmt(void)
-
- static void __exit exit_irix_binfmt(void)
- {
-- /* Remove the IRIX ELF loaders. */
-+ /*
-+ * Remove the Irix ELF loader.
-+ */
- unregister_binfmt(&irix_format);
- }
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irixinv.c linux_HEAD/arch/mips/kernel/irixinv.c
---- linux-2.6.12/arch/mips/kernel/irixinv.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irixinv.c 2005-03-17 22:20:26.000000000 +0100
-@@ -30,10 +30,10 @@ void add_to_inventory (int class, int ty
- inventory_items++;
- }
-
--int dump_inventory_to_user (void *userbuf, int size)
-+int dump_inventory_to_user (void __user *userbuf, int size)
- {
- inventory_t *inv = &inventory [0];
-- inventory_t *user = userbuf;
-+ inventory_t __user *user = userbuf;
- int v;
-
- if (!access_ok(VERIFY_WRITE, userbuf, size))
-@@ -41,7 +41,8 @@ int dump_inventory_to_user (void *userbu
-
- for (v = 0; v < inventory_items; v++){
- inv = &inventory [v];
-- copy_to_user (user, inv, sizeof (inventory_t));
-+ if (copy_to_user (user, inv, sizeof (inventory_t)))
-+ return -EFAULT;
- user++;
- }
- return inventory_items * sizeof (inventory_t);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irixioctl.c linux_HEAD/arch/mips/kernel/irixioctl.c
---- linux-2.6.12/arch/mips/kernel/irixioctl.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irixioctl.c 2005-03-17 22:20:26.000000000 +0100
-@@ -58,7 +58,7 @@ asmlinkage int irix_ioctl(int fd, unsign
- {
- struct tty_struct *tp, *rtp;
- mm_segment_t old_fs;
-- int error = 0;
-+ int i, error = 0;
-
- #ifdef DEBUG_IOCTLS
- printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd);
-@@ -73,12 +73,13 @@ asmlinkage int irix_ioctl(int fd, unsign
-
- case 0x0000540d: {
- struct termios kt;
-- struct irix_termios *it = (struct irix_termios *) arg;
-+ struct irix_termios __user *it =
-+ (struct irix_termios __user *) arg;
-
- #ifdef DEBUG_IOCTLS
- printk("TCGETS, %08lx) ", arg);
- #endif
-- if(!access_ok(VERIFY_WRITE, it, sizeof(*it))) {
-+ if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) {
- error = -EFAULT;
- break;
- }
-@@ -87,13 +88,14 @@ asmlinkage int irix_ioctl(int fd, unsign
- set_fs(old_fs);
- if (error)
- break;
-- __put_user(kt.c_iflag, &it->c_iflag);
-- __put_user(kt.c_oflag, &it->c_oflag);
-- __put_user(kt.c_cflag, &it->c_cflag);
-- __put_user(kt.c_lflag, &it->c_lflag);
-- for(error = 0; error < NCCS; error++)
-- __put_user(kt.c_cc[error], &it->c_cc[error]);
-- error = 0;
-+
-+ error = __put_user(kt.c_iflag, &it->c_iflag);
-+ error |= __put_user(kt.c_oflag, &it->c_oflag);
-+ error |= __put_user(kt.c_cflag, &it->c_cflag);
-+ error |= __put_user(kt.c_lflag, &it->c_lflag);
-+
-+ for (i = 0; i < NCCS; i++)
-+ error |= __put_user(kt.c_cc[i], &it->c_cc[i]);
- break;
- }
-
-@@ -111,14 +113,19 @@ asmlinkage int irix_ioctl(int fd, unsign
- old_fs = get_fs(); set_fs(get_ds());
- error = sys_ioctl(fd, TCGETS, (unsigned long) &kt);
- set_fs(old_fs);
-- if(error)
-+ if (error)
-+ break;
-+
-+ error = __get_user(kt.c_iflag, &it->c_iflag);
-+ error |= __get_user(kt.c_oflag, &it->c_oflag);
-+ error |= __get_user(kt.c_cflag, &it->c_cflag);
-+ error |= __get_user(kt.c_lflag, &it->c_lflag);
-+
-+ for (i = 0; i < NCCS; i++)
-+ error |= __get_user(kt.c_cc[i], &it->c_cc[i]);
-+
-+ if (error)
- break;
-- __get_user(kt.c_iflag, &it->c_iflag);
-- __get_user(kt.c_oflag, &it->c_oflag);
-- __get_user(kt.c_cflag, &it->c_cflag);
-- __get_user(kt.c_lflag, &it->c_lflag);
-- for(error = 0; error < NCCS; error++)
-- __get_user(kt.c_cc[error], &it->c_cc[error]);
- old_fs = get_fs(); set_fs(get_ds());
- error = sys_ioctl(fd, TCSETS, (unsigned long) &kt);
- set_fs(old_fs);
-@@ -152,7 +159,7 @@ asmlinkage int irix_ioctl(int fd, unsign
- #ifdef DEBUG_IOCTLS
- printk("rtp->session=%d ", rtp->session);
- #endif
-- error = put_user(rtp->session, (unsigned long *) arg);
-+ error = put_user(rtp->session, (unsigned long __user *) arg);
- break;
-
- case 0x746e:
-@@ -194,50 +201,32 @@ asmlinkage int irix_ioctl(int fd, unsign
- break;
-
- case 0x8004667e:
--#ifdef DEBUG_IOCTLS
-- printk("FIONBIO, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, FIONBIO, arg);
- break;
-
- case 0x80047476:
--#ifdef DEBUG_IOCTLS
-- printk("TIOCSPGRP, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, TIOCSPGRP, arg);
- break;
-
- case 0x8020690c:
--#ifdef DEBUG_IOCTLS
-- printk("SIOCSIFADDR, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, SIOCSIFADDR, arg);
- break;
-
- case 0x80206910:
--#ifdef DEBUG_IOCTLS
-- printk("SIOCSIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, SIOCSIFFLAGS, arg);
- break;
-
- case 0xc0206911:
--#ifdef DEBUG_IOCTLS
-- printk("SIOCGIFFLAGS, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, SIOCGIFFLAGS, arg);
- break;
-
- case 0xc020691b:
--#ifdef DEBUG_IOCTLS
-- printk("SIOCGIFMETRIC, %08lx) arg=%d ", arg, *(int *)arg);
--#endif
- error = sys_ioctl(fd, SIOCGIFMETRIC, arg);
- break;
-
- default: {
- #ifdef DEBUG_MISSING_IOCTL
-- char *msg = "Unimplemented IOCTL cmd tell linux at engr.sgi.com\n";
-+ char *msg = "Unimplemented IOCTL cmd tell linux-mips at linux-mips.org\n";
-
- #ifdef DEBUG_IOCTLS
- printk("UNIMP_IOCTL, %08lx)\n", arg);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irixsig.c linux_HEAD/arch/mips/kernel/irixsig.c
---- linux-2.6.12/arch/mips/kernel/irixsig.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irixsig.c 2005-03-17 22:20:26.000000000 +0100
-@@ -79,33 +79,36 @@ static inline void dump_irix5_sigctx(str
- static void setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs,
- int signr, sigset_t *oldmask)
- {
-+ struct sigctx_irix5 __user *ctx;
- unsigned long sp;
-- struct sigctx_irix5 *ctx;
-- int i;
-+ int error, i;
-
- sp = regs->regs[29];
- sp -= sizeof(struct sigctx_irix5);
- sp &= ~(0xf);
-- ctx = (struct sigctx_irix5 *) sp;
-+ ctx = (struct sigctx_irix5 __user *) sp;
- if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)))
- goto segv_and_exit;
-
-- __put_user(0, &ctx->weird_fpu_thing);
-- __put_user(~(0x00000001), &ctx->rmask);
-- __put_user(0, &ctx->regs[0]);
-+ error = __put_user(0, &ctx->weird_fpu_thing);
-+ error |= __put_user(~(0x00000001), &ctx->rmask);
-+ error |= __put_user(0, &ctx->regs[0]);
- for(i = 1; i < 32; i++)
-- __put_user((u64) regs->regs[i], &ctx->regs[i]);
-+ error |= __put_user((u64) regs->regs[i], &ctx->regs[i]);
-
-- __put_user((u64) regs->hi, &ctx->hi);
-- __put_user((u64) regs->lo, &ctx->lo);
-- __put_user((u64) regs->cp0_epc, &ctx->pc);
-- __put_user(!!used_math(), &ctx->usedfp);
-- __put_user((u64) regs->cp0_cause, &ctx->cp0_cause);
-- __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr);
-+ error |= __put_user((u64) regs->hi, &ctx->hi);
-+ error |= __put_user((u64) regs->lo, &ctx->lo);
-+ error |= __put_user((u64) regs->cp0_epc, &ctx->pc);
-+ error |= __put_user(!!used_math(), &ctx->usedfp);
-+ error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause);
-+ error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr);
-
-- __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */
-+ error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */
-
-- __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t));
-+ error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0;
-+
-+ if (error)
-+ goto segv_and_exit;
-
- #ifdef DEBUG_SIG
- dump_irix5_sigctx(ctx);
-@@ -209,10 +212,11 @@ no_signal:
- asmlinkage void
- irix_sigreturn(struct pt_regs *regs)
- {
-- struct sigctx_irix5 *context, *magic;
-+ struct sigctx_irix5 __user *context, *magic;
- unsigned long umask, mask;
- u64 *fregs;
-- int sig, i, base = 0;
-+ u32 usedfp;
-+ int error, sig, i, base = 0;
- sigset_t blocked;
-
- /* Always make any pending restarted system calls return -EINTR */
-@@ -221,8 +225,8 @@ irix_sigreturn(struct pt_regs *regs)
- if (regs->regs[2] == 1000)
- base = 1;
-
-- context = (struct sigctx_irix5 *) regs->regs[base + 4];
-- magic = (struct sigctx_irix5 *) regs->regs[base + 5];
-+ context = (struct sigctx_irix5 __user *) regs->regs[base + 4];
-+ magic = (struct sigctx_irix5 __user *) regs->regs[base + 5];
- sig = (int) regs->regs[base + 6];
- #ifdef DEBUG_SIG
- printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n",
-@@ -237,25 +241,31 @@ irix_sigreturn(struct pt_regs *regs)
- dump_irix5_sigctx(context);
- #endif
-
-- __get_user(regs->cp0_epc, &context->pc);
-- umask = context->rmask; mask = 2;
-+ error = __get_user(regs->cp0_epc, &context->pc);
-+ error |= __get_user(umask, &context->rmask);
-+
-+ mask = 2;
- for (i = 1; i < 32; i++, mask <<= 1) {
-- if(umask & mask)
-- __get_user(regs->regs[i], &context->regs[i]);
-+ if (umask & mask)
-+ error |= __get_user(regs->regs[i], &context->regs[i]);
- }
-- __get_user(regs->hi, &context->hi);
-- __get_user(regs->lo, &context->lo);
-+ error |= __get_user(regs->hi, &context->hi);
-+ error |= __get_user(regs->lo, &context->lo);
-
-- if ((umask & 1) && context->usedfp) {
-+ error |= __get_user(usedfp, &context->usedfp);
-+ if ((umask & 1) && usedfp) {
- fregs = (u64 *) ¤t->thread.fpu;
-+
- for(i = 0; i < 32; i++)
-- fregs[i] = (u64) context->fpregs[i];
-- __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr);
-+ error |= __get_user(fregs[i], &context->fpregs[i]);
-+ error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr);
- }
-
- /* XXX do sigstack crapola here... XXX */
-
-- if (__copy_from_user(&blocked, &context->sigset, sizeof(blocked)))
-+ error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0;
-+
-+ if (error)
- goto badframe;
-
- sigdelsetmask(&blocked, ~_BLOCKABLE);
-@@ -297,8 +307,8 @@ static inline void dump_sigact_irix5(str
- #endif
-
- asmlinkage int
--irix_sigaction(int sig, const struct sigaction *act,
-- struct sigaction *oact, void *trampoline)
-+irix_sigaction(int sig, const struct sigaction __user *act,
-+ struct sigaction __user *oact, void __user *trampoline)
- {
- struct k_sigaction new_ka, old_ka;
- int ret;
-@@ -312,12 +322,16 @@ irix_sigaction(int sig, const struct sig
- #endif
- if (act) {
- sigset_t mask;
-- if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
-- __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-- __get_user(new_ka.sa.sa_flags, &act->sa_flags))
-+ int err;
-+
-+ if (!access_ok(VERIFY_READ, act, sizeof(*act)))
- return -EFAULT;
-+ err = __get_user(new_ka.sa.sa_handler, &act->sa_handler);
-+ err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
-
-- __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t));
-+ err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0;
-+ if (err)
-+ return err;
-
- /*
- * Hmmm... methinks IRIX libc always passes a valid trampoline
-@@ -331,30 +345,37 @@ irix_sigaction(int sig, const struct sig
- ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-
- if (!ret && oact) {
-- if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
-- __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-- __put_user(old_ka.sa.sa_flags, &oact->sa_flags))
-+ int err;
-+
-+ if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)))
-+ return -EFAULT;
-+
-+ err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler);
-+ err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-+ err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask,
-+ sizeof(sigset_t)) ? -EFAULT : 0;
-+ if (err)
- return -EFAULT;
-- __copy_to_user(&old_ka.sa.sa_mask, &oact->sa_mask,
-- sizeof(sigset_t));
- }
-
- return ret;
- }
-
--asmlinkage int irix_sigpending(irix_sigset_t *set)
-+asmlinkage int irix_sigpending(irix_sigset_t __user *set)
- {
- return do_sigpending(set, sizeof(*set));
- }
-
--asmlinkage int irix_sigprocmask(int how, irix_sigset_t *new, irix_sigset_t *old)
-+asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new,
-+ irix_sigset_t __user *old)
- {
- sigset_t oldbits, newbits;
-
- if (new) {
- if (!access_ok(VERIFY_READ, new, sizeof(*new)))
- return -EFAULT;
-- __copy_from_user(&newbits, new, sizeof(unsigned long)*4);
-+ if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4))
-+ return -EFAULT;
- sigdelsetmask(&newbits, ~_BLOCKABLE);
-
- spin_lock_irq(¤t->sighand->siglock);
-@@ -382,20 +403,19 @@ asmlinkage int irix_sigprocmask(int how,
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- }
-- if(old) {
-- if (!access_ok(VERIFY_WRITE, old, sizeof(*old)))
-- return -EFAULT;
-- __copy_to_user(old, ¤t->blocked, sizeof(unsigned long)*4);
-- }
-+ if (old)
-+ return copy_to_user(old, ¤t->blocked,
-+ sizeof(unsigned long)*4) ? -EFAULT : 0;
-
- return 0;
- }
-
- asmlinkage int irix_sigsuspend(struct pt_regs *regs)
- {
-- sigset_t *uset, saveset, newset;
-+ sigset_t saveset, newset;
-+ sigset_t __user *uset;
-
-- uset = (sigset_t *) regs->regs[4];
-+ uset = (sigset_t __user *) regs->regs[4];
- if (copy_from_user(&newset, uset, sizeof(sigset_t)))
- return -EFAULT;
- sigdelsetmask(&newset, ~_BLOCKABLE);
-@@ -453,12 +473,13 @@ static inline unsigned long timespectoji
- return HZ * sec + nsec;
- }
-
--asmlinkage int irix_sigpoll_sys(unsigned long *set, struct irix5_siginfo *info,
-- struct timespec *tp)
-+asmlinkage int irix_sigpoll_sys(unsigned long __user *set,
-+ struct irix5_siginfo __user *info, struct timespec __user *tp)
- {
- long expire = MAX_SCHEDULE_TIMEOUT;
- sigset_t kset;
- int i, sig, error, timeo = 0;
-+ struct timespec ktp;
-
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n",
-@@ -469,14 +490,8 @@ asmlinkage int irix_sigpoll_sys(unsigned
- if (!set)
- return -EINVAL;
-
-- if (!access_ok(VERIFY_READ, set, sizeof(kset))) {
-- error = -EFAULT;
-- goto out;
-- }
--
-- __copy_from_user(&kset, set, sizeof(set));
-- if (error)
-- goto out;
-+ if (copy_from_user(&kset, set, sizeof(set)))
-+ return -EFAULT;
-
- if (info && clear_user(info, sizeof(*info))) {
- error = -EFAULT;
-@@ -484,13 +499,13 @@ asmlinkage int irix_sigpoll_sys(unsigned
- }
-
- if (tp) {
-- if (!access_ok(VERIFY_READ, tp, sizeof(*tp)))
-+ if (copy_from_user(&ktp, tp, sizeof(*tp)))
- return -EFAULT;
-- if (!tp->tv_sec && !tp->tv_nsec) {
-- error = -EINVAL;
-- goto out;
-- }
-- expire = timespectojiffies(tp)+(tp->tv_sec||tp->tv_nsec);
-+
-+ if (!ktp.tv_sec && !ktp.tv_nsec)
-+ return -EINVAL;
-+
-+ expire = timespectojiffies(&ktp) + (ktp.tv_sec || ktp.tv_nsec);
- }
-
- while(1) {
-@@ -514,15 +529,14 @@ asmlinkage int irix_sigpoll_sys(unsigned
- if (timeo)
- return -EAGAIN;
-
-- for(sig = 1; i <= 65 /* IRIX_NSIG */; sig++) {
-+ for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) {
- if (sigismember (&kset, sig))
- continue;
- if (sigismember (¤t->pending.signal, sig)) {
- /* XXX need more than this... */
- if (info)
-- info->sig = sig;
-- error = 0;
-- goto out;
-+ return copy_to_user(&info->sig, &sig, sizeof(sig));
-+ return 0;
- }
- }
-
-@@ -548,8 +562,9 @@ extern int getrusage(struct task_struct
-
- #define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG)
-
--asmlinkage int irix_waitsys(int type, int pid, struct irix5_siginfo *info,
-- int options, struct rusage *ru)
-+asmlinkage int irix_waitsys(int type, int pid,
-+ struct irix5_siginfo __user *info, int options,
-+ struct rusage __user *ru)
- {
- int flag, retval;
- DECLARE_WAITQUEUE(wait, current);
-@@ -557,28 +572,22 @@ asmlinkage int irix_waitsys(int type, in
- struct task_struct *p;
- struct list_head *_p;
-
-- if (!info) {
-- retval = -EINVAL;
-- goto out;
-- }
-- if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) {
-- retval = -EFAULT;
-- goto out;
-- }
-- if (ru) {
-- if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) {
-- retval = -EFAULT;
-- goto out;
-- }
-- }
-- if (options & ~(W_MASK)) {
-- retval = -EINVAL;
-- goto out;
-- }
-- if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) {
-- retval = -EINVAL;
-- goto out;
-- }
-+ if (!info)
-+ return -EINVAL;
-+
-+ if (!access_ok(VERIFY_WRITE, info, sizeof(*info)))
-+ return -EFAULT;
-+
-+ if (ru)
-+ if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru)))
-+ return -EFAULT;
-+
-+ if (options & ~W_MASK)
-+ return -EINVAL;
-+
-+ if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL)
-+ return -EINVAL;
-+
- add_wait_queue(¤t->signal->wait_chldexit, &wait);
- repeat:
- flag = 0;
-@@ -609,18 +618,20 @@ repeat:
- add_parent(p, p->parent);
- write_unlock_irq(&tasklist_lock);
- retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0;
-- if (!retval && ru) {
-- retval |= __put_user(SIGCHLD, &info->sig);
-- retval |= __put_user(0, &info->code);
-- retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
-- retval |= __put_user((p->exit_code >> 8) & 0xff,
-- &info->stuff.procinfo.procdata.child.status);
-- retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime);
-- retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime);
-- }
-- if (!retval) {
-- p->exit_code = 0;
-- }
-+ if (retval)
-+ goto end_waitsys;
-+
-+ retval = __put_user(SIGCHLD, &info->sig);
-+ retval |= __put_user(0, &info->code);
-+ retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
-+ retval |= __put_user((p->exit_code >> 8) & 0xff,
-+ &info->stuff.procinfo.procdata.child.status);
-+ retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime);
-+ retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime);
-+ if (retval)
-+ goto end_waitsys;
-+
-+ p->exit_code = 0;
- goto end_waitsys;
-
- case EXIT_ZOMBIE:
-@@ -628,16 +639,18 @@ repeat:
- current->signal->cstime += p->stime + p->signal->cstime;
- if (ru != NULL)
- getrusage(p, RUSAGE_BOTH, ru);
-- __put_user(SIGCHLD, &info->sig);
-- __put_user(1, &info->code); /* CLD_EXITED */
-- __put_user(p->pid, &info->stuff.procinfo.pid);
-- __put_user((p->exit_code >> 8) & 0xff,
-+ retval = __put_user(SIGCHLD, &info->sig);
-+ retval |= __put_user(1, &info->code); /* CLD_EXITED */
-+ retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
-+ retval |= __put_user((p->exit_code >> 8) & 0xff,
- &info->stuff.procinfo.procdata.child.status);
-- __put_user(p->utime,
-+ retval |= __put_user(p->utime,
- &info->stuff.procinfo.procdata.child.utime);
-- __put_user(p->stime,
-+ retval |= __put_user(p->stime,
- &info->stuff.procinfo.procdata.child.stime);
-- retval = 0;
-+ if (retval)
-+ return retval;
-+
- if (p->real_parent != p->parent) {
- write_lock_irq(&tasklist_lock);
- remove_parent(p);
-@@ -670,7 +683,6 @@ end_waitsys:
- current->state = TASK_RUNNING;
- remove_wait_queue(¤t->signal->wait_chldexit, &wait);
-
--out:
- return retval;
- }
-
-@@ -689,39 +701,39 @@ struct irix5_context {
-
- asmlinkage int irix_getcontext(struct pt_regs *regs)
- {
-- int i, base = 0;
-- struct irix5_context *ctx;
-+ int error, i, base = 0;
-+ struct irix5_context __user *ctx;
- unsigned long flags;
-
- if (regs->regs[2] == 1000)
- base = 1;
-- ctx = (struct irix5_context *) regs->regs[base + 4];
-+ ctx = (struct irix5_context __user *) regs->regs[base + 4];
-
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_getcontext(%p)\n",
- current->comm, current->pid, ctx);
- #endif
-
-- if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)))
-+ if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)));
- return -EFAULT;
-
-- __put_user(current->thread.irix_oldctx, &ctx->link);
-+ error = __put_user(current->thread.irix_oldctx, &ctx->link);
-
-- __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t));
-+ error |= __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0;
-
- /* XXX Do sigstack stuff someday... */
-- __put_user(0, &ctx->stack.sp);
-- __put_user(0, &ctx->stack.size);
-- __put_user(0, &ctx->stack.flags);
-+ error |= __put_user(0, &ctx->stack.sp);
-+ error |= __put_user(0, &ctx->stack.size);
-+ error |= __put_user(0, &ctx->stack.flags);
-
-- __put_user(0, &ctx->weird_graphics_thing);
-- __put_user(0, &ctx->regs[0]);
-+ error |= __put_user(0, &ctx->weird_graphics_thing);
-+ error |= __put_user(0, &ctx->regs[0]);
- for (i = 1; i < 32; i++)
-- __put_user(regs->regs[i], &ctx->regs[i]);
-- __put_user(regs->lo, &ctx->regs[32]);
-- __put_user(regs->hi, &ctx->regs[33]);
-- __put_user(regs->cp0_cause, &ctx->regs[34]);
-- __put_user(regs->cp0_epc, &ctx->regs[35]);
-+ error |= __put_user(regs->regs[i], &ctx->regs[i]);
-+ error |= __put_user(regs->lo, &ctx->regs[32]);
-+ error |= __put_user(regs->hi, &ctx->regs[33]);
-+ error |= __put_user(regs->cp0_cause, &ctx->regs[34]);
-+ error |= __put_user(regs->cp0_epc, &ctx->regs[35]);
-
- flags = 0x0f;
- if (!used_math()) {
-@@ -730,119 +742,124 @@ asmlinkage int irix_getcontext(struct pt
- /* XXX wheee... */
- printk("Wheee, no code for saving IRIX FPU context yet.\n");
- }
-- __put_user(flags, &ctx->flags);
-+ error |= __put_user(flags, &ctx->flags);
-
-- return 0;
-+ return error;
- }
-
--asmlinkage unsigned long irix_setcontext(struct pt_regs *regs)
-+asmlinkage void irix_setcontext(struct pt_regs *regs)
- {
-- int error, base = 0;
-- struct irix5_context *ctx;
-+ struct irix5_context __user *ctx;
-+ int err, base = 0;
-+ u32 flags;
-
-- if(regs->regs[2] == 1000)
-+ if (regs->regs[2] == 1000)
- base = 1;
-- ctx = (struct irix5_context *) regs->regs[base + 4];
-+ ctx = (struct irix5_context __user *) regs->regs[base + 4];
-
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_setcontext(%p)\n",
- current->comm, current->pid, ctx);
- #endif
-
-- if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) {
-- error = -EFAULT;
-- goto out;
-- }
-+ if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)))
-+ goto segv_and_exit;
-
-- if (ctx->flags & 0x02) {
-+ err = __get_user(flags, &ctx->flags);
-+ if (flags & 0x02) {
- /* XXX sigstack garbage, todo... */
- printk("Wheee, cannot do sigstack stuff in setcontext\n");
- }
-
-- if (ctx->flags & 0x04) {
-+ if (flags & 0x04) {
- int i;
-
- /* XXX extra control block stuff... todo... */
-- for(i = 1; i < 32; i++)
-- regs->regs[i] = ctx->regs[i];
-- regs->lo = ctx->regs[32];
-- regs->hi = ctx->regs[33];
-- regs->cp0_epc = ctx->regs[35];
-+ for (i = 1; i < 32; i++)
-+ err |= __get_user(regs->regs[i], &ctx->regs[i]);
-+ err |= __get_user(regs->lo, &ctx->regs[32]);
-+ err |= __get_user(regs->hi, &ctx->regs[33]);
-+ err |= __get_user(regs->cp0_epc, &ctx->regs[35]);
- }
-
-- if (ctx->flags & 0x08) {
-+ if (flags & 0x08)
- /* XXX fpu context, blah... */
-- printk("Wheee, cannot restore FPU context yet...\n");
-- }
-- current->thread.irix_oldctx = ctx->link;
-- error = regs->regs[2];
-+ printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n");
-
--out:
-- return error;
-+ err |= __get_user(current->thread.irix_oldctx, &ctx->link);
-+ if (err)
-+ goto segv_and_exit;
-+
-+ /*
-+ * Don't let your children do this ...
-+ */
-+ if (current_thread_info()->flags & TIF_SYSCALL_TRACE)
-+ do_syscall_trace(regs, 1);
-+ __asm__ __volatile__(
-+ "move\t$29,%0\n\t"
-+ "j\tsyscall_exit"
-+ :/* no outputs */
-+ :"r" (®s));
-+ /* Unreached */
-+
-+segv_and_exit:
-+ force_sigsegv(SIGSEGV, current);
- }
-
--struct irix_sigstack { unsigned long sp; int status; };
-+struct irix_sigstack {
-+ unsigned long sp;
-+ int status;
-+};
-
--asmlinkage int irix_sigstack(struct irix_sigstack *new, struct irix_sigstack *old)
-+asmlinkage int irix_sigstack(struct irix_sigstack __user *new,
-+ struct irix_sigstack __user *old)
- {
-- int error = -EFAULT;
--
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_sigstack(%p,%p)\n",
- current->comm, current->pid, new, old);
- #endif
-- if(new) {
-+ if (new) {
- if (!access_ok(VERIFY_READ, new, sizeof(*new)))
-- goto out;
-+ return -EFAULT;
- }
-
-- if(old) {
-+ if (old) {
- if (!access_ok(VERIFY_WRITE, old, sizeof(*old)))
-- goto out;
-+ return -EFAULT;
- }
-- error = 0;
-
--out:
-- return error;
-+ return 0;
- }
-
- struct irix_sigaltstack { unsigned long sp; int size; int status; };
-
--asmlinkage int irix_sigaltstack(struct irix_sigaltstack *new,
-- struct irix_sigaltstack *old)
-+asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new,
-+ struct irix_sigaltstack __user *old)
- {
-- int error = -EFAULT;
--
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_sigaltstack(%p,%p)\n",
- current->comm, current->pid, new, old);
- #endif
-- if (new) {
-+ if (new)
- if (!access_ok(VERIFY_READ, new, sizeof(*new)))
-- goto out;
-- }
-+ return -EFAULT;
-
- if (old) {
- if (!access_ok(VERIFY_WRITE, old, sizeof(*old)))
-- goto out;
-+ return -EFAULT;
- }
-- error = 0;
--
--out:
-- error = 0;
-
-- return error;
-+ return 0;
- }
-
- struct irix_procset {
- int cmd, ltype, lid, rtype, rid;
- };
-
--asmlinkage int irix_sigsendset(struct irix_procset *pset, int sig)
-+asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig)
- {
- if (!access_ok(VERIFY_READ, pset, sizeof(*pset)))
- return -EFAULT;
--
- #ifdef DEBUG_SIG
- printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n",
- current->comm, current->pid,
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irq-msc01.c linux_HEAD/arch/mips/kernel/irq-msc01.c
---- linux-2.6.12/arch/mips/kernel/irq-msc01.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irq-msc01.c 2005-02-28 16:56:41.000000000 +0100
-@@ -129,25 +129,23 @@ msc_bind_eic_interrupt (unsigned int irq
- #define shutdown_msc_irq disable_msc_irq
-
- struct hw_interrupt_type msc_levelirq_type = {
-- "SOC-it-Level",
-- startup_msc_irq,
-- shutdown_msc_irq,
-- enable_msc_irq,
-- disable_msc_irq,
-- level_mask_and_ack_msc_irq,
-- end_msc_irq,
-- NULL
-+ .typename = "SOC-it-Level",
-+ .startup = startup_msc_irq,
-+ .shutdown = shutdown_msc_irq,
-+ .enable = enable_msc_irq,
-+ .disable = disable_msc_irq,
-+ .ack = level_mask_and_ack_msc_irq,
-+ .end = end_msc_irq,
- };
-
- struct hw_interrupt_type msc_edgeirq_type = {
-- "SOC-it-Edge",
-- startup_msc_irq,
-- shutdown_msc_irq,
-- enable_msc_irq,
-- disable_msc_irq,
-- edge_mask_and_ack_msc_irq,
-- end_msc_irq,
-- NULL
-+ .typename = "SOC-it-Edge",
-+ .startup =startup_msc_irq,
-+ .shutdown = shutdown_msc_irq,
-+ .enable = enable_msc_irq,
-+ .disable = disable_msc_irq,
-+ .ack = edge_mask_and_ack_msc_irq,
-+ .end = end_msc_irq,
- };
-
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irq-mv6434x.c linux_HEAD/arch/mips/kernel/irq-mv6434x.c
---- linux-2.6.12/arch/mips/kernel/irq-mv6434x.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irq-mv6434x.c 2005-02-28 16:56:41.000000000 +0100
-@@ -135,14 +135,13 @@ void ll_mv64340_irq(struct pt_regs *regs
- #define shutdown_mv64340_irq disable_mv64340_irq
-
- struct hw_interrupt_type mv64340_irq_type = {
-- "MV-64340",
-- startup_mv64340_irq,
-- shutdown_mv64340_irq,
-- enable_mv64340_irq,
-- disable_mv64340_irq,
-- mask_and_ack_mv64340_irq,
-- end_mv64340_irq,
-- NULL
-+ .typename = "MV-64340",
-+ .startup = startup_mv64340_irq,
-+ .shutdown = shutdown_mv64340_irq,
-+ .enable = enable_mv64340_irq,
-+ .disable = disable_mv64340_irq,
-+ .ack = mask_and_ack_mv64340_irq,
-+ .end = end_mv64340_irq,
- };
-
- void __init mv64340_irq_init(unsigned int base)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irq-rm7000.c linux_HEAD/arch/mips/kernel/irq-rm7000.c
---- linux-2.6.12/arch/mips/kernel/irq-rm7000.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irq-rm7000.c 2005-02-28 16:56:41.000000000 +0100
-@@ -72,13 +72,13 @@ static void rm7k_cpu_irq_end(unsigned in
- }
-
- static hw_irq_controller rm7k_irq_controller = {
-- "RM7000",
-- rm7k_cpu_irq_startup,
-- rm7k_cpu_irq_shutdown,
-- rm7k_cpu_irq_enable,
-- rm7k_cpu_irq_disable,
-- rm7k_cpu_irq_ack,
-- rm7k_cpu_irq_end,
-+ .typename = "RM7000",
-+ .startup = rm7k_cpu_irq_startup,
-+ .shutdown = rm7k_cpu_irq_shutdown,
-+ .enable = rm7k_cpu_irq_enable,
-+ .disable = rm7k_cpu_irq_disable,
-+ .ack = rm7k_cpu_irq_ack,
-+ .end = rm7k_cpu_irq_end,
- };
-
- void __init rm7k_cpu_irq_init(int base)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irq-rm9000.c linux_HEAD/arch/mips/kernel/irq-rm9000.c
---- linux-2.6.12/arch/mips/kernel/irq-rm9000.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irq-rm9000.c 2005-02-28 16:56:41.000000000 +0100
-@@ -106,23 +106,23 @@ static void rm9k_cpu_irq_end(unsigned in
- }
-
- static hw_irq_controller rm9k_irq_controller = {
-- "RM9000",
-- rm9k_cpu_irq_startup,
-- rm9k_cpu_irq_shutdown,
-- rm9k_cpu_irq_enable,
-- rm9k_cpu_irq_disable,
-- rm9k_cpu_irq_ack,
-- rm9k_cpu_irq_end,
-+ .typename = "RM9000",
-+ .startup = rm9k_cpu_irq_startup,
-+ .shutdown = rm9k_cpu_irq_shutdown,
-+ .enable = rm9k_cpu_irq_enable,
-+ .disable = rm9k_cpu_irq_disable,
-+ .ack = rm9k_cpu_irq_ack,
-+ .end = rm9k_cpu_irq_end,
- };
-
- static hw_irq_controller rm9k_perfcounter_irq = {
-- "RM9000",
-- rm9k_perfcounter_irq_startup,
-- rm9k_perfcounter_irq_shutdown,
-- rm9k_cpu_irq_enable,
-- rm9k_cpu_irq_disable,
-- rm9k_cpu_irq_ack,
-- rm9k_cpu_irq_end,
-+ .typename = "RM9000",
-+ .startup = rm9k_perfcounter_irq_startup,
-+ .shutdown = rm9k_perfcounter_irq_shutdown,
-+ .enable = rm9k_cpu_irq_enable,
-+ .disable = rm9k_cpu_irq_disable,
-+ .ack = rm9k_cpu_irq_ack,
-+ .end = rm9k_cpu_irq_end,
- };
-
- unsigned int rm9000_perfcount_irq;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/irq_cpu.c linux_HEAD/arch/mips/kernel/irq_cpu.c
---- linux-2.6.12/arch/mips/kernel/irq_cpu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/irq_cpu.c 2005-02-28 16:56:41.000000000 +0100
-@@ -3,6 +3,8 @@
- * Author: Jun Sun, jsun at mvista.com or jsun at junsun.net
- *
- * Copyright (C) 2001 Ralf Baechle
-+ * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
-+ * Author: Maciej W. Rozycki <macro at mips.com>
- *
- * This file define the irq handler for MIPS CPU interrupts.
- *
-@@ -37,7 +39,6 @@ static int mips_cpu_irq_base;
-
- static inline void unmask_mips_irq(unsigned int irq)
- {
-- clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
- set_c0_status(0x100 << (irq - mips_cpu_irq_base));
- }
-
-@@ -92,14 +93,13 @@ static void mips_cpu_irq_end(unsigned in
- }
-
- static hw_irq_controller mips_cpu_irq_controller = {
-- "MIPS",
-- mips_cpu_irq_startup,
-- mips_cpu_irq_shutdown,
-- mips_cpu_irq_enable,
-- mips_cpu_irq_disable,
-- mips_cpu_irq_ack,
-- mips_cpu_irq_end,
-- NULL /* no affinity stuff for UP */
-+ .typename = "MIPS",
-+ .startup = mips_cpu_irq_startup,
-+ .shutdown = mips_cpu_irq_shutdown,
-+ .enable = mips_cpu_irq_enable,
-+ .disable = mips_cpu_irq_disable,
-+ .ack = mips_cpu_irq_ack,
-+ .end = mips_cpu_irq_end,
- };
-
-
-@@ -107,6 +107,10 @@ void __init mips_cpu_irq_init(int irq_ba
- {
- int i;
-
-+ /* Mask interrupts. */
-+ clear_c0_status(ST0_IM);
-+ clear_c0_cause(CAUSEF_IP);
-+
- for (i = irq_base; i < irq_base + 8; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/linux32.c linux_HEAD/arch/mips/kernel/linux32.c
---- linux-2.6.12/arch/mips/kernel/linux32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/linux32.c 2005-04-13 19:06:33.000000000 +0200
-@@ -215,81 +215,35 @@ sys32_readdir(unsigned int fd, void * di
- return(n);
- }
-
--struct rusage32 {
-- struct compat_timeval ru_utime;
-- struct compat_timeval ru_stime;
-- int ru_maxrss;
-- int ru_ixrss;
-- int ru_idrss;
-- int ru_isrss;
-- int ru_minflt;
-- int ru_majflt;
-- int ru_nswap;
-- int ru_inblock;
-- int ru_oublock;
-- int ru_msgsnd;
-- int ru_msgrcv;
-- int ru_nsignals;
-- int ru_nvcsw;
-- int ru_nivcsw;
--};
-+asmlinkage int compat_sys_wait4(compat_pid_t pid, unsigned int * stat_addr,
-+ int options, struct compat_rusage * ru);
-
--static int
--put_rusage (struct rusage32 *ru, struct rusage *r)
-+asmlinkage int
-+sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options)
- {
-- int err;
--
-- if (!access_ok(VERIFY_WRITE, ru, sizeof *ru))
-- return -EFAULT;
--
-- err = __put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec);
-- err |= __put_user (r->ru_utime.tv_usec, &ru->ru_utime.tv_usec);
-- err |= __put_user (r->ru_stime.tv_sec, &ru->ru_stime.tv_sec);
-- err |= __put_user (r->ru_stime.tv_usec, &ru->ru_stime.tv_usec);
-- err |= __put_user (r->ru_maxrss, &ru->ru_maxrss);
-- err |= __put_user (r->ru_ixrss, &ru->ru_ixrss);
-- err |= __put_user (r->ru_idrss, &ru->ru_idrss);
-- err |= __put_user (r->ru_isrss, &ru->ru_isrss);
-- err |= __put_user (r->ru_minflt, &ru->ru_minflt);
-- err |= __put_user (r->ru_majflt, &ru->ru_majflt);
-- err |= __put_user (r->ru_nswap, &ru->ru_nswap);
-- err |= __put_user (r->ru_inblock, &ru->ru_inblock);
-- err |= __put_user (r->ru_oublock, &ru->ru_oublock);
-- err |= __put_user (r->ru_msgsnd, &ru->ru_msgsnd);
-- err |= __put_user (r->ru_msgrcv, &ru->ru_msgrcv);
-- err |= __put_user (r->ru_nsignals, &ru->ru_nsignals);
-- err |= __put_user (r->ru_nvcsw, &ru->ru_nvcsw);
-- err |= __put_user (r->ru_nivcsw, &ru->ru_nivcsw);
--
-- return err;
-+ return compat_sys_wait4(pid, stat_addr, options, NULL);
- }
-
--asmlinkage int
--sys32_wait4(compat_pid_t pid, unsigned int * stat_addr, int options,
-- struct rusage32 * ru)
-+asmlinkage long
-+sysn32_waitid(int which, compat_pid_t pid,
-+ siginfo_t __user *uinfo, int options,
-+ struct compat_rusage __user *uru)
- {
-- if (!ru)
-- return sys_wait4(pid, stat_addr, options, NULL);
-- else {
-- struct rusage r;
-- int ret;
-- unsigned int status;
-- mm_segment_t old_fs = get_fs();
-+ struct rusage ru;
-+ long ret;
-+ mm_segment_t old_fs = get_fs();
-
-- set_fs(KERNEL_DS);
-- ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r);
-- set_fs(old_fs);
-- if (put_rusage (ru, &r)) return -EFAULT;
-- if (stat_addr && put_user (status, stat_addr))
-- return -EFAULT;
-+ set_fs (KERNEL_DS);
-+ ret = sys_waitid(which, pid, uinfo, options,
-+ uru ? (struct rusage __user *) &ru : NULL);
-+ set_fs (old_fs);
-+
-+ if (ret < 0 || uinfo->si_signo == 0)
- return ret;
-- }
--}
-
--asmlinkage int
--sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options)
--{
-- return sys32_wait4(pid, stat_addr, options, NULL);
-+ if (uru)
-+ ret = put_compat_rusage(&ru, uru);
-+ return ret;
- }
-
- struct sysinfo32 {
-@@ -1467,3 +1421,80 @@ asmlinkage long sys32_socketcall(int cal
- }
- return err;
- }
-+
-+struct sigevent32 {
-+ u32 sigev_value;
-+ u32 sigev_signo;
-+ u32 sigev_notify;
-+ u32 payload[(64 / 4) - 3];
-+};
-+
-+extern asmlinkage long
-+sys_timer_create(clockid_t which_clock,
-+ struct sigevent __user *timer_event_spec,
-+ timer_t __user * created_timer_id);
-+
-+long
-+sys32_timer_create(u32 clock, struct sigevent32 __user *se32, timer_t __user *timer_id)
-+{
-+ struct sigevent __user *p = NULL;
-+ if (se32) {
-+ struct sigevent se;
-+ p = compat_alloc_user_space(sizeof(struct sigevent));
-+ memset(&se, 0, sizeof(struct sigevent));
-+ if (get_user(se.sigev_value.sival_int, &se32->sigev_value) ||
-+ __get_user(se.sigev_signo, &se32->sigev_signo) ||
-+ __get_user(se.sigev_notify, &se32->sigev_notify) ||
-+ __copy_from_user(&se._sigev_un._pad, &se32->payload,
-+ sizeof(se32->payload)) ||
-+ copy_to_user(p, &se, sizeof(se)))
-+ return -EFAULT;
-+ }
-+ return sys_timer_create(clock, p, timer_id);
-+}
-+
-+asmlinkage long
-+sysn32_rt_sigtimedwait(const sigset_t __user *uthese,
-+ siginfo_t __user *uinfo,
-+ const struct compat_timespec __user *uts32,
-+ size_t sigsetsize)
-+{
-+ struct timespec __user *uts = NULL;
-+
-+ if (uts32) {
-+ struct timespec ts;
-+ uts = compat_alloc_user_space(sizeof(struct timespec));
-+ if (get_user(ts.tv_sec, &uts32->tv_sec) ||
-+ get_user(ts.tv_nsec, &uts32->tv_nsec) ||
-+ copy_to_user (uts, &ts, sizeof (ts)))
-+ return -EFAULT;
-+ }
-+ return sys_rt_sigtimedwait(uthese, uinfo, uts, sigsetsize);
-+}
-+
-+save_static_function(sys32_clone);
-+__attribute_used__ noinline static int
-+_sys32_clone(nabi_no_regargs struct pt_regs regs)
-+{
-+ unsigned long clone_flags;
-+ unsigned long newsp;
-+ int __user *parent_tidptr, *child_tidptr;
-+
-+ clone_flags = regs.regs[4];
-+ newsp = regs.regs[5];
-+ if (!newsp)
-+ newsp = regs.regs[29];
-+ parent_tidptr = (int *) regs.regs[6];
-+
-+ /* Use __dummy4 instead of getting it off the stack, so that
-+ syscall() works. */
-+ child_tidptr = (int __user *) __dummy4;
-+ return do_fork(clone_flags, newsp, ®s, 0,
-+ parent_tidptr, child_tidptr);
-+}
-+
-+extern asmlinkage void sys_set_thread_area(u32 addr);
-+asmlinkage void sys32_set_thread_area(u32 addr)
-+{
-+ sys_set_thread_area(AA(addr));
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/module-elf32.c linux_HEAD/arch/mips/kernel/module-elf32.c
---- linux-2.6.12/arch/mips/kernel/module-elf32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/module-elf32.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,250 +0,0 @@
--/*
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- *
-- * Copyright (C) 2001 Rusty Russell.
-- * Copyright (C) 2003, 2004 Ralf Baechle (ralf at linux-mips.org)
-- */
--
--#undef DEBUG
--
--#include <linux/moduleloader.h>
--#include <linux/elf.h>
--#include <linux/vmalloc.h>
--#include <linux/slab.h>
--#include <linux/fs.h>
--#include <linux/string.h>
--#include <linux/kernel.h>
--
--struct mips_hi16 {
-- struct mips_hi16 *next;
-- Elf32_Addr *addr;
-- Elf32_Addr value;
--};
--
--static struct mips_hi16 *mips_hi16_list;
--
--void *module_alloc(unsigned long size)
--{
-- if (size == 0)
-- return NULL;
-- return vmalloc(size);
--}
--
--
--/* Free memory returned from module_alloc */
--void module_free(struct module *mod, void *module_region)
--{
-- vfree(module_region);
-- /* FIXME: If module_region == mod->init_region, trim exception
-- table entries. */
--}
--
--int module_frob_arch_sections(Elf_Ehdr *hdr,
-- Elf_Shdr *sechdrs,
-- char *secstrings,
-- struct module *mod)
--{
-- return 0;
--}
--
--static int apply_r_mips_none(struct module *me, uint32_t *location,
-- Elf32_Addr v)
--{
-- return 0;
--}
--
--static int apply_r_mips_32(struct module *me, uint32_t *location,
-- Elf32_Addr v)
--{
-- *location += v;
--
-- return 0;
--}
--
--static int apply_r_mips_26(struct module *me, uint32_t *location,
-- Elf32_Addr v)
--{
-- if (v % 4) {
-- printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
-- return -ENOEXEC;
-- }
--
-- if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-- printk(KERN_ERR
-- "module %s: relocation overflow\n",
-- me->name);
-- return -ENOEXEC;
-- }
--
-- *location = (*location & ~0x03ffffff) |
-- ((*location + (v >> 2)) & 0x03ffffff);
--
-- return 0;
--}
--
--static int apply_r_mips_hi16(struct module *me, uint32_t *location,
-- Elf32_Addr v)
--{
-- struct mips_hi16 *n;
--
-- /*
-- * We cannot relocate this one now because we don't know the value of
-- * the carry we need to add. Save the information, and let LO16 do the
-- * actual relocation.
-- */
-- n = kmalloc(sizeof *n, GFP_KERNEL);
-- if (!n)
-- return -ENOMEM;
--
-- n->addr = location;
-- n->value = v;
-- n->next = mips_hi16_list;
-- mips_hi16_list = n;
--
-- return 0;
--}
--
--static int apply_r_mips_lo16(struct module *me, uint32_t *location,
-- Elf32_Addr v)
--{
-- unsigned long insnlo = *location;
-- Elf32_Addr val, vallo;
--
-- /* Sign extend the addend we extract from the lo insn. */
-- vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
--
-- if (mips_hi16_list != NULL) {
-- struct mips_hi16 *l;
--
-- l = mips_hi16_list;
-- while (l != NULL) {
-- struct mips_hi16 *next;
-- unsigned long insn;
--
-- /*
-- * The value for the HI16 had best be the same.
-- */
-- if (v != l->value)
-- goto out_danger;
--
-- /*
-- * Do the HI16 relocation. Note that we actually don't
-- * need to know anything about the LO16 itself, except
-- * where to find the low 16 bits of the addend needed
-- * by the LO16.
-- */
-- insn = *l->addr;
-- val = ((insn & 0xffff) << 16) + vallo;
-- val += v;
--
-- /*
-- * Account for the sign extension that will happen in
-- * the low bits.
-- */
-- val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
--
-- insn = (insn & ~0xffff) | val;
-- *l->addr = insn;
--
-- next = l->next;
-- kfree(l);
-- l = next;
-- }
--
-- mips_hi16_list = NULL;
-- }
--
-- /*
-- * Ok, we're done with the HI16 relocs. Now deal with the LO16.
-- */
-- val = v + vallo;
-- insnlo = (insnlo & ~0xffff) | (val & 0xffff);
-- *location = insnlo;
--
-- return 0;
--
--out_danger:
-- printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
--
-- return -ENOEXEC;
--}
--
--static int (*reloc_handlers[]) (struct module *me, uint32_t *location,
-- Elf32_Addr v) = {
-- [R_MIPS_NONE] = apply_r_mips_none,
-- [R_MIPS_32] = apply_r_mips_32,
-- [R_MIPS_26] = apply_r_mips_26,
-- [R_MIPS_HI16] = apply_r_mips_hi16,
-- [R_MIPS_LO16] = apply_r_mips_lo16
--};
--
--int apply_relocate(Elf32_Shdr *sechdrs,
-- const char *strtab,
-- unsigned int symindex,
-- unsigned int relsec,
-- struct module *me)
--{
-- Elf32_Rel *rel = (void *) sechdrs[relsec].sh_addr;
-- Elf32_Sym *sym;
-- uint32_t *location;
-- unsigned int i;
-- Elf32_Addr v;
-- int res;
--
-- pr_debug("Applying relocate section %u to %u\n", relsec,
-- sechdrs[relsec].sh_info);
--
-- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-- Elf32_Word r_info = rel[i].r_info;
--
-- /* This is where to make the change */
-- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-- + rel[i].r_offset;
-- /* This is the symbol it is referring to */
-- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
-- + ELF32_R_SYM(r_info);
-- if (!sym->st_value) {
-- printk(KERN_WARNING "%s: Unknown symbol %s\n",
-- me->name, strtab + sym->st_name);
-- return -ENOENT;
-- }
--
-- v = sym->st_value;
--
-- res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
-- if (res)
-- return res;
-- }
--
-- return 0;
--}
--
--int apply_relocate_add(Elf32_Shdr *sechdrs,
-- const char *strtab,
-- unsigned int symindex,
-- unsigned int relsec,
-- struct module *me)
--{
-- /*
-- * Current binutils always generate .rela relocations. Keep smiling
-- * if it's empty, abort otherwise.
-- */
-- if (!sechdrs[relsec].sh_size)
-- return 0;
--
-- printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n",
-- me->name);
-- return -ENOEXEC;
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/module-elf64.c linux_HEAD/arch/mips/kernel/module-elf64.c
---- linux-2.6.12/arch/mips/kernel/module-elf64.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/module-elf64.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,274 +0,0 @@
--/*
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- *
-- * Copyright (C) 2001 Rusty Russell.
-- * Copyright (C) 2003, 2004 Ralf Baechle (ralf at linux-mips.org)
-- */
--
--#undef DEBUG
--
--#include <linux/moduleloader.h>
--#include <linux/elf.h>
--#include <linux/vmalloc.h>
--#include <linux/slab.h>
--#include <linux/fs.h>
--#include <linux/string.h>
--#include <linux/kernel.h>
--
--struct mips_hi16 {
-- struct mips_hi16 *next;
-- Elf32_Addr *addr;
-- Elf64_Addr value;
--};
--
--static struct mips_hi16 *mips_hi16_list;
--
--void *module_alloc(unsigned long size)
--{
-- if (size == 0)
-- return NULL;
-- return vmalloc(size);
--}
--
--
--/* Free memory returned from module_alloc */
--void module_free(struct module *mod, void *module_region)
--{
-- vfree(module_region);
-- /* FIXME: If module_region == mod->init_region, trim exception
-- table entries. */
--}
--
--int module_frob_arch_sections(Elf_Ehdr *hdr,
-- Elf_Shdr *sechdrs,
-- char *secstrings,
-- struct module *mod)
--{
-- return 0;
--}
--
--int apply_relocate(Elf64_Shdr *sechdrs,
-- const char *strtab,
-- unsigned int symindex,
-- unsigned int relsec,
-- struct module *me)
--{
-- /*
-- * We don't want to deal with REL relocations - RELA is so much saner.
-- */
-- if (!sechdrs[relsec].sh_size)
-- return 0;
--
-- printk(KERN_ERR "module %s: REL relocation unsupported\n",
-- me->name);
-- return -ENOEXEC;
--}
--
--static int apply_r_mips_none(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- return 0;
--}
--
--static int apply_r_mips_32(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- *location = v;
--
-- return 0;
--}
--
--static int apply_r_mips_26(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- if (v % 4) {
-- printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
-- return -ENOEXEC;
-- }
--
-- if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-- printk(KERN_ERR
-- "module %s: relocation overflow\n",
-- me->name);
-- return -ENOEXEC;
-- }
--
-- *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
--
-- return 0;
--}
--
--static int apply_r_mips_hi16(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- struct mips_hi16 *n;
--
-- /*
-- * We cannot relocate this one now because we don't know the value of
-- * the carry we need to add. Save the information, and let LO16 do the
-- * actual relocation.
-- */
-- n = kmalloc(sizeof *n, GFP_KERNEL);
-- if (!n)
-- return -ENOMEM;
--
-- n->addr = location;
-- n->value = v;
-- n->next = mips_hi16_list;
-- mips_hi16_list = n;
--
-- return 0;
--}
--
--static int apply_r_mips_lo16(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- unsigned long insnlo = *location;
-- Elf32_Addr val, vallo;
--
-- /* Sign extend the addend we extract from the lo insn. */
-- vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
--
-- if (mips_hi16_list != NULL) {
-- struct mips_hi16 *l;
--
-- l = mips_hi16_list;
-- while (l != NULL) {
-- struct mips_hi16 *next;
-- unsigned long insn;
--
-- /*
-- * The value for the HI16 had best be the same.
-- */
-- if (v != l->value)
-- goto out_danger;
--
-- /*
-- * Do the HI16 relocation. Note that we actually don't
-- * need to know anything about the LO16 itself, except
-- * where to find the low 16 bits of the addend needed
-- * by the LO16.
-- */
-- insn = *l->addr;
-- val = ((insn & 0xffff) << 16) + vallo;
-- val += v;
--
-- /*
-- * Account for the sign extension that will happen in
-- * the low bits.
-- */
-- val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
--
-- insn = (insn & ~0xffff) | val;
-- *l->addr = insn;
--
-- next = l->next;
-- kfree(l);
-- l = next;
-- }
--
-- mips_hi16_list = NULL;
-- }
--
-- /*
-- * Ok, we're done with the HI16 relocs. Now deal with the LO16.
-- */
-- insnlo = (insnlo & ~0xffff) | (v & 0xffff);
-- *location = insnlo;
--
-- return 0;
--
--out_danger:
-- printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
--
-- return -ENOEXEC;
--}
--
--static int apply_r_mips_64(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- *(uint64_t *) location = v;
--
-- return 0;
--}
--
--
--static int apply_r_mips_higher(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- *location = (*location & 0xffff0000) |
-- ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
--
-- return 0;
--}
--
--static int apply_r_mips_highest(struct module *me, uint32_t *location,
-- Elf64_Addr v)
--{
-- *location = (*location & 0xffff0000) |
-- ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
--
-- return 0;
--}
--
--static int (*reloc_handlers[]) (struct module *me, uint32_t *location,
-- Elf64_Addr v) = {
-- [R_MIPS_NONE] = apply_r_mips_none,
-- [R_MIPS_32] = apply_r_mips_32,
-- [R_MIPS_26] = apply_r_mips_26,
-- [R_MIPS_HI16] = apply_r_mips_hi16,
-- [R_MIPS_LO16] = apply_r_mips_lo16,
-- [R_MIPS_64] = apply_r_mips_64,
-- [R_MIPS_HIGHER] = apply_r_mips_higher,
-- [R_MIPS_HIGHEST] = apply_r_mips_highest
--};
--
--int apply_relocate_add(Elf64_Shdr *sechdrs,
-- const char *strtab,
-- unsigned int symindex,
-- unsigned int relsec,
-- struct module *me)
--{
-- Elf64_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
-- Elf64_Sym *sym;
-- uint32_t *location;
-- unsigned int i;
-- Elf64_Addr v;
-- int res;
--
-- pr_debug("Applying relocate section %u to %u\n", relsec,
-- sechdrs[relsec].sh_info);
--
-- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-- /* This is where to make the change */
-- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-- + rel[i].r_offset;
-- /* This is the symbol it is referring to */
-- sym = (Elf64_Sym *)sechdrs[symindex].sh_addr + rel[i].r_sym;
-- if (!sym->st_value) {
-- printk(KERN_WARNING "%s: Unknown symbol %s\n",
-- me->name, strtab + sym->st_name);
-- return -ENOENT;
-- }
--
-- v = sym->st_value;
--
-- res = reloc_handlers[rel[i].r_type](me, location, v);
-- if (res)
-- return res;
-- }
--
-- return 0;
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/module.c linux_HEAD/arch/mips/kernel/module.c
---- linux-2.6.12/arch/mips/kernel/module.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/module.c 2005-03-30 09:06:31.000000000 +0200
-@@ -1,9 +1,345 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ * Copyright (C) 2001 Rusty Russell.
-+ * Copyright (C) 2003, 2004 Ralf Baechle (ralf at linux-mips.org)
-+ * Copyright (C) 2005 Thiemo Seufer
-+ */
-+
-+#undef DEBUG
-+
-+#include <linux/moduleloader.h>
-+#include <linux/elf.h>
-+#include <linux/vmalloc.h>
-+#include <linux/slab.h>
-+#include <linux/fs.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/spinlock.h>
-
-+struct mips_hi16 {
-+ struct mips_hi16 *next;
-+ Elf_Addr *addr;
-+ Elf_Addr value;
-+};
-+
-+static struct mips_hi16 *mips_hi16_list;
-+
- static LIST_HEAD(dbe_list);
- static DEFINE_SPINLOCK(dbe_lock);
-
-+void *module_alloc(unsigned long size)
-+{
-+ if (size == 0)
-+ return NULL;
-+ return vmalloc(size);
-+}
-+
-+/* Free memory returned from module_alloc */
-+void module_free(struct module *mod, void *module_region)
-+{
-+ vfree(module_region);
-+ /* FIXME: If module_region == mod->init_region, trim exception
-+ table entries. */
-+}
-+
-+int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
-+ char *secstrings, struct module *mod)
-+{
-+ return 0;
-+}
-+
-+static int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ return 0;
-+}
-+
-+static int apply_r_mips_32_rel(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ *location += v;
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_32_rela(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ *location = v;
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ if (v % 4) {
-+ printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
-+ return -ENOEXEC;
-+ }
-+
-+ if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-+ printk(KERN_ERR
-+ "module %s: relocation overflow\n",
-+ me->name);
-+ return -ENOEXEC;
-+ }
-+
-+ *location = (*location & ~0x03ffffff) |
-+ ((*location + (v >> 2)) & 0x03ffffff);
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ if (v % 4) {
-+ printk(KERN_ERR "module %s: dangerous relocation\n", me->name);
-+ return -ENOEXEC;
-+ }
-+
-+ if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-+ printk(KERN_ERR
-+ "module %s: relocation overflow\n",
-+ me->name);
-+ return -ENOEXEC;
-+ }
-+
-+ *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ struct mips_hi16 *n;
-+
-+ /*
-+ * We cannot relocate this one now because we don't know the value of
-+ * the carry we need to add. Save the information, and let LO16 do the
-+ * actual relocation.
-+ */
-+ n = kmalloc(sizeof *n, GFP_KERNEL);
-+ if (!n)
-+ return -ENOMEM;
-+
-+ n->addr = (Elf_Addr *)location;
-+ n->value = v;
-+ n->next = mips_hi16_list;
-+ mips_hi16_list = n;
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ *location = (*location & 0xffff0000) |
-+ ((((long long) v + 0x8000LL) >> 16) & 0xffff);
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ unsigned long insnlo = *location;
-+ Elf_Addr val, vallo;
-+
-+ /* Sign extend the addend we extract from the lo insn. */
-+ vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
-+
-+ if (mips_hi16_list != NULL) {
-+ struct mips_hi16 *l;
-+
-+ l = mips_hi16_list;
-+ while (l != NULL) {
-+ struct mips_hi16 *next;
-+ unsigned long insn;
-+
-+ /*
-+ * The value for the HI16 had best be the same.
-+ */
-+ if (v != l->value)
-+ goto out_danger;
-+
-+ /*
-+ * Do the HI16 relocation. Note that we actually don't
-+ * need to know anything about the LO16 itself, except
-+ * where to find the low 16 bits of the addend needed
-+ * by the LO16.
-+ */
-+ insn = *l->addr;
-+ val = ((insn & 0xffff) << 16) + vallo;
-+ val += v;
-+
-+ /*
-+ * Account for the sign extension that will happen in
-+ * the low bits.
-+ */
-+ val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff;
-+
-+ insn = (insn & ~0xffff) | val;
-+ *l->addr = insn;
-+
-+ next = l->next;
-+ kfree(l);
-+ l = next;
-+ }
-+
-+ mips_hi16_list = NULL;
-+ }
-+
-+ /*
-+ * Ok, we're done with the HI16 relocs. Now deal with the LO16.
-+ */
-+ val = v + vallo;
-+ insnlo = (insnlo & ~0xffff) | (val & 0xffff);
-+ *location = insnlo;
-+
-+ return 0;
-+
-+out_danger:
-+ printk(KERN_ERR "module %s: dangerous " "relocation\n", me->name);
-+
-+ return -ENOEXEC;
-+}
-+
-+static int apply_r_mips_lo16_rela(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ *location = (*location & 0xffff0000) | (v & 0xffff);
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_64_rela(struct module *me, u32 *location, Elf_Addr v)
-+{
-+ *(Elf_Addr *)location = v;
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_higher_rela(struct module *me, u32 *location,
-+ Elf_Addr v)
-+{
-+ *location = (*location & 0xffff0000) |
-+ ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
-+
-+ return 0;
-+}
-+
-+static int apply_r_mips_highest_rela(struct module *me, u32 *location,
-+ Elf_Addr v)
-+{
-+ *location = (*location & 0xffff0000) |
-+ ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
-+
-+ return 0;
-+}
-+
-+static int (*reloc_handlers_rel[]) (struct module *me, u32 *location,
-+ Elf_Addr v) = {
-+ [R_MIPS_NONE] = apply_r_mips_none,
-+ [R_MIPS_32] = apply_r_mips_32_rel,
-+ [R_MIPS_26] = apply_r_mips_26_rel,
-+ [R_MIPS_HI16] = apply_r_mips_hi16_rel,
-+ [R_MIPS_LO16] = apply_r_mips_lo16_rel
-+};
-+
-+static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
-+ Elf_Addr v) = {
-+ [R_MIPS_NONE] = apply_r_mips_none,
-+ [R_MIPS_32] = apply_r_mips_32_rela,
-+ [R_MIPS_26] = apply_r_mips_26_rela,
-+ [R_MIPS_HI16] = apply_r_mips_hi16_rela,
-+ [R_MIPS_LO16] = apply_r_mips_lo16_rela,
-+ [R_MIPS_64] = apply_r_mips_64_rela,
-+ [R_MIPS_HIGHER] = apply_r_mips_higher_rela,
-+ [R_MIPS_HIGHEST] = apply_r_mips_highest_rela
-+};
-+
-+int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
-+ unsigned int symindex, unsigned int relsec,
-+ struct module *me)
-+{
-+ Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
-+ Elf_Sym *sym;
-+ u32 *location;
-+ unsigned int i;
-+ Elf_Addr v;
-+ int res;
-+
-+ pr_debug("Applying relocate section %u to %u\n", relsec,
-+ sechdrs[relsec].sh_info);
-+
-+ for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-+ /* This is where to make the change */
-+ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-+ + rel[i].r_offset;
-+ /* This is the symbol it is referring to */
-+ sym = (Elf_Sym *)sechdrs[symindex].sh_addr
-+ + ELF_MIPS_R_SYM(rel[i]);
-+ if (!sym->st_value) {
-+ printk(KERN_WARNING "%s: Unknown symbol %s\n",
-+ me->name, strtab + sym->st_name);
-+ return -ENOENT;
-+ }
-+
-+ v = sym->st_value;
-+
-+ res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
-+ if (res)
-+ return res;
-+ }
-+
-+ return 0;
-+}
-+
-+int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
-+ unsigned int symindex, unsigned int relsec,
-+ struct module *me)
-+{
-+ Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
-+ Elf_Sym *sym;
-+ u32 *location;
-+ unsigned int i;
-+ Elf_Addr v;
-+ int res;
-+
-+ pr_debug("Applying relocate section %u to %u\n", relsec,
-+ sechdrs[relsec].sh_info);
-+
-+ for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-+ /* This is where to make the change */
-+ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
-+ + rel[i].r_offset;
-+ /* This is the symbol it is referring to */
-+ sym = (Elf_Sym *)sechdrs[symindex].sh_addr
-+ + ELF_MIPS_R_SYM(rel[i]);
-+ if (!sym->st_value) {
-+ printk(KERN_WARNING "%s: Unknown symbol %s\n",
-+ me->name, strtab + sym->st_name);
-+ return -ENOENT;
-+ }
-+
-+ v = sym->st_value + rel[i].r_addend;
-+
-+ res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
-+ if (res)
-+ return res;
-+ }
-+
-+ return 0;
-+}
-+
- /* Given an address, look for it in the module exception tables. */
- const struct exception_table_entry *search_module_dbetables(unsigned long addr)
- {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/offset.c linux_HEAD/arch/mips/kernel/offset.c
---- linux-2.6.12/arch/mips/kernel/offset.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/offset.c 2005-07-01 12:09:18.000000000 +0200
-@@ -95,6 +95,7 @@ void output_thread_info_defines(void)
- offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count);
- offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit);
- offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block);
-+ offset("#define TI_TP_VALUE ", struct thread_info, tp_value);
- constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER);
- constant("#define _THREAD_SIZE ", THREAD_SIZE);
- constant("#define _THREAD_MASK ", THREAD_MASK);
-@@ -240,6 +241,7 @@ void output_mm_defines(void)
- linefeed;
- }
-
-+#ifdef CONFIG_MIPS32
- void output_sc_defines(void)
- {
- text("/* Linux sigcontext offsets. */");
-@@ -251,10 +253,29 @@ void output_sc_defines(void)
- offset("#define SC_STATUS ", struct sigcontext, sc_status);
- offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr);
- offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir);
-- offset("#define SC_CAUSE ", struct sigcontext, sc_cause);
-- offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr);
-+ offset("#define SC_HI1 ", struct sigcontext, sc_hi1);
-+ offset("#define SC_LO1 ", struct sigcontext, sc_lo1);
-+ offset("#define SC_HI2 ", struct sigcontext, sc_hi2);
-+ offset("#define SC_LO2 ", struct sigcontext, sc_lo2);
-+ offset("#define SC_HI3 ", struct sigcontext, sc_hi3);
-+ offset("#define SC_LO3 ", struct sigcontext, sc_lo3);
- linefeed;
- }
-+#endif
-+
-+#ifdef CONFIG_MIPS64
-+void output_sc_defines(void)
-+{
-+ text("/* Linux sigcontext offsets. */");
-+ offset("#define SC_REGS ", struct sigcontext, sc_regs);
-+ offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs);
-+ offset("#define SC_MDHI ", struct sigcontext, sc_hi);
-+ offset("#define SC_MDLO ", struct sigcontext, sc_lo);
-+ offset("#define SC_PC ", struct sigcontext, sc_pc);
-+ offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr);
-+ linefeed;
-+}
-+#endif
-
- #ifdef CONFIG_MIPS32_COMPAT
- void output_sc32_defines(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/proc.c linux_HEAD/arch/mips/kernel/proc.c
---- linux-2.6.12/arch/mips/kernel/proc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/proc.c 2005-05-09 13:20:25.000000000 +0200
-@@ -2,7 +2,8 @@
- * linux/arch/mips/kernel/proc.c
- *
- * Copyright (C) 1995, 1996, 2001 Ralf Baechle
-- * Copyright (C) 2001 MIPS Technologies, Inc.
-+ * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
-+ * Copyright (C) 2004 Maciej W. Rozycki
- */
- #include <linux/config.h>
- #include <linux/delay.h>
-@@ -19,63 +20,66 @@
- unsigned int vced_count, vcei_count;
-
- static const char *cpu_name[] = {
-- [CPU_UNKNOWN] "unknown",
-- [CPU_R2000] "R2000",
-- [CPU_R3000] "R3000",
-- [CPU_R3000A] "R3000A",
-- [CPU_R3041] "R3041",
-- [CPU_R3051] "R3051",
-- [CPU_R3052] "R3052",
-- [CPU_R3081] "R3081",
-- [CPU_R3081E] "R3081E",
-- [CPU_R4000PC] "R4000PC",
-- [CPU_R4000SC] "R4000SC",
-- [CPU_R4000MC] "R4000MC",
-- [CPU_R4200] "R4200",
-- [CPU_R4400PC] "R4400PC",
-- [CPU_R4400SC] "R4400SC",
-- [CPU_R4400MC] "R4400MC",
-- [CPU_R4600] "R4600",
-- [CPU_R6000] "R6000",
-- [CPU_R6000A] "R6000A",
-- [CPU_R8000] "R8000",
-- [CPU_R10000] "R10000",
-- [CPU_R12000] "R12000",
-- [CPU_R4300] "R4300",
-- [CPU_R4650] "R4650",
-- [CPU_R4700] "R4700",
-- [CPU_R5000] "R5000",
-- [CPU_R5000A] "R5000A",
-- [CPU_R4640] "R4640",
-- [CPU_NEVADA] "Nevada",
-- [CPU_RM7000] "RM7000",
-- [CPU_RM9000] "RM9000",
-- [CPU_R5432] "R5432",
-- [CPU_4KC] "MIPS 4Kc",
-- [CPU_5KC] "MIPS 5Kc",
-- [CPU_R4310] "R4310",
-- [CPU_SB1] "SiByte SB1",
-- [CPU_TX3912] "TX3912",
-- [CPU_TX3922] "TX3922",
-- [CPU_TX3927] "TX3927",
-- [CPU_AU1000] "Au1000",
-- [CPU_AU1500] "Au1500",
-- [CPU_4KEC] "MIPS 4KEc",
-- [CPU_4KSC] "MIPS 4KSc",
-- [CPU_VR41XX] "NEC Vr41xx",
-- [CPU_R5500] "R5500",
-- [CPU_TX49XX] "TX49xx",
-- [CPU_20KC] "MIPS 20Kc",
-- [CPU_24K] "MIPS 24K",
-- [CPU_25KF] "MIPS 25Kf",
-- [CPU_VR4111] "NEC VR4111",
-- [CPU_VR4121] "NEC VR4121",
-- [CPU_VR4122] "NEC VR4122",
-- [CPU_VR4131] "NEC VR4131",
-- [CPU_VR4133] "NEC VR4133",
-- [CPU_VR4181] "NEC VR4181",
-- [CPU_VR4181A] "NEC VR4181A",
-- [CPU_SR71000] "Sandcraft SR71000"
-+ [CPU_UNKNOWN] = "unknown",
-+ [CPU_R2000] = "R2000",
-+ [CPU_R3000] = "R3000",
-+ [CPU_R3000A] = "R3000A",
-+ [CPU_R3041] = "R3041",
-+ [CPU_R3051] = "R3051",
-+ [CPU_R3052] = "R3052",
-+ [CPU_R3081] = "R3081",
-+ [CPU_R3081E] = "R3081E",
-+ [CPU_R4000PC] = "R4000PC",
-+ [CPU_R4000SC] = "R4000SC",
-+ [CPU_R4000MC] = "R4000MC",
-+ [CPU_R4200] = "R4200",
-+ [CPU_R4400PC] = "R4400PC",
-+ [CPU_R4400SC] = "R4400SC",
-+ [CPU_R4400MC] = "R4400MC",
-+ [CPU_R4600] = "R4600",
-+ [CPU_R6000] = "R6000",
-+ [CPU_R6000A] = "R6000A",
-+ [CPU_R8000] = "R8000",
-+ [CPU_R10000] = "R10000",
-+ [CPU_R12000] = "R12000",
-+ [CPU_R4300] = "R4300",
-+ [CPU_R4650] = "R4650",
-+ [CPU_R4700] = "R4700",
-+ [CPU_R5000] = "R5000",
-+ [CPU_R5000A] = "R5000A",
-+ [CPU_R4640] = "R4640",
-+ [CPU_NEVADA] = "Nevada",
-+ [CPU_RM7000] = "RM7000",
-+ [CPU_RM9000] = "RM9000",
-+ [CPU_R5432] = "R5432",
-+ [CPU_4KC] = "MIPS 4Kc",
-+ [CPU_5KC] = "MIPS 5Kc",
-+ [CPU_R4310] = "R4310",
-+ [CPU_SB1] = "SiByte SB1",
-+ [CPU_TX3912] = "TX3912",
-+ [CPU_TX3922] = "TX3922",
-+ [CPU_TX3927] = "TX3927",
-+ [CPU_AU1000] = "Au1000",
-+ [CPU_AU1500] = "Au1500",
-+ [CPU_AU1100] = "Au1100",
-+ [CPU_AU1550] = "Au1550",
-+ [CPU_AU1200] = "Au1200",
-+ [CPU_4KEC] = "MIPS 4KEc",
-+ [CPU_4KSC] = "MIPS 4KSc",
-+ [CPU_VR41XX] = "NEC Vr41xx",
-+ [CPU_R5500] = "R5500",
-+ [CPU_TX49XX] = "TX49xx",
-+ [CPU_20KC] = "MIPS 20Kc",
-+ [CPU_24K] = "MIPS 24K",
-+ [CPU_25KF] = "MIPS 25Kf",
-+ [CPU_VR4111] = "NEC VR4111",
-+ [CPU_VR4121] = "NEC VR4121",
-+ [CPU_VR4122] = "NEC VR4122",
-+ [CPU_VR4131] = "NEC VR4131",
-+ [CPU_VR4133] = "NEC VR4133",
-+ [CPU_VR4181] = "NEC VR4181",
-+ [CPU_VR4181A] = "NEC VR4181A",
-+ [CPU_SR71000] = "Sandcraft SR71000"
- };
-
-
-@@ -105,8 +109,8 @@ static int show_cpuinfo(struct seq_file
- (version >> 4) & 0x0f, version & 0x0f,
- (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
- seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
-- loops_per_jiffy / (500000/HZ),
-- (loops_per_jiffy / (5000/HZ)) % 100);
-+ cpu_data[n].udelay_val / (500000/HZ),
-+ (cpu_data[n].udelay_val / (5000/HZ)) % 100);
- seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
- seq_printf(m, "microsecond timers\t: %s\n",
- cpu_has_counter ? "yes" : "no");
-@@ -115,6 +119,11 @@ static int show_cpuinfo(struct seq_file
- cpu_has_divec ? "yes" : "no");
- seq_printf(m, "hardware watchpoint\t: %s\n",
- cpu_has_watch ? "yes" : "no");
-+ seq_printf(m, "ASEs implemented\t:%s%s%s%s\n",
-+ cpu_has_mips16 ? " mips16" : "",
-+ cpu_has_mdmx ? " mdmx" : "",
-+ cpu_has_mips3d ? " mips3d" : "",
-+ cpu_has_smartmips ? " smartmips" : "");
-
- sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
- cpu_has_vce ? "%u" : "not available");
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/process.c linux_HEAD/arch/mips/kernel/process.c
---- linux-2.6.12/arch/mips/kernel/process.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/process.c 2005-07-01 12:09:18.000000000 +0200
-@@ -25,8 +25,10 @@
- #include <linux/init.h>
- #include <linux/completion.h>
-
-+#include <asm/abi.h>
- #include <asm/bootinfo.h>
- #include <asm/cpu.h>
-+#include <asm/dsp.h>
- #include <asm/fpu.h>
- #include <asm/pgtable.h>
- #include <asm/system.h>
-@@ -39,14 +41,6 @@
- #include <asm/inst.h>
-
- /*
-- * We use this if we don't have any better idle routine..
-- * (This to kill: kernel/platform.c.
-- */
--void default_idle (void)
--{
--}
--
--/*
- * The idle thread. There's no useful work to be done, so just try to conserve
- * power and have a low exit latency (ie sit in a loop waiting for somebody to
- * say that they'd like to reschedule)
-@@ -62,6 +56,54 @@ ATTRIB_NORET void cpu_idle(void)
- }
- }
-
-+extern int do_signal(sigset_t *oldset, struct pt_regs *regs);
-+extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
-+
-+/*
-+ * Native o32 and N64 ABI without DSP ASE
-+ */
-+extern void setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
-+ int signr, sigset_t *set);
-+extern void setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
-+ int signr, sigset_t *set, siginfo_t *info);
-+
-+struct mips_abi mips_abi = {
-+ .do_signal = do_signal,
-+#ifdef CONFIG_TRAD_SIGNALS
-+ .setup_frame = setup_frame,
-+#endif
-+ .setup_rt_frame = setup_rt_frame
-+};
-+
-+#ifdef CONFIG_MIPS32_O32
-+/*
-+ * o32 compatibility on 64-bit kernels, without DSP ASE
-+ */
-+extern void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
-+ int signr, sigset_t *set);
-+extern void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
-+ int signr, sigset_t *set, siginfo_t *info);
-+
-+struct mips_abi mips_abi_32 = {
-+ .do_signal = do_signal32,
-+ .setup_frame = setup_frame_32,
-+ .setup_rt_frame = setup_rt_frame_32
-+};
-+#endif /* CONFIG_MIPS32_O32 */
-+
-+#ifdef CONFIG_MIPS32_N32
-+/*
-+ * N32 on 64-bit kernels, without DSP ASE
-+ */
-+extern void setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs,
-+ int signr, sigset_t *set, siginfo_t *info);
-+
-+struct mips_abi mips_abi_n32 = {
-+ .do_signal = do_signal,
-+ .setup_rt_frame = setup_rt_frame_n32
-+};
-+#endif /* CONFIG_MIPS32_N32 */
-+
- asmlinkage void ret_from_fork(void);
-
- void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
-@@ -78,6 +120,8 @@ void start_thread(struct pt_regs * regs,
- regs->cp0_status = status;
- clear_used_math();
- lose_fpu();
-+ if (cpu_has_dsp)
-+ __init_dsp();
- regs->cp0_epc = pc;
- regs->regs[29] = sp;
- current_thread_info()->addr_limit = USER_DS;
-@@ -97,14 +141,17 @@ int copy_thread(int nr, unsigned long cl
- struct thread_info *ti = p->thread_info;
- struct pt_regs *childregs;
- long childksp;
-+ p->set_child_tid = p->clear_child_tid = NULL;
-
- childksp = (unsigned long)ti + THREAD_SIZE - 32;
-
- preempt_disable();
-
-- if (is_fpu_owner()) {
-+ if (is_fpu_owner())
- save_fp(p);
-- }
-+
-+ if (cpu_has_dsp)
-+ save_dsp(p);
-
- preempt_enable();
-
-@@ -142,6 +189,9 @@ int copy_thread(int nr, unsigned long cl
- childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
- clear_tsk_thread_flag(p, TIF_USEDFPU);
-
-+ if (clone_flags & CLONE_SETTLS)
-+ ti->tp_value = regs->regs[7];
-+
- return 0;
- }
-
-@@ -175,6 +225,14 @@ void dump_regs(elf_greg_t *gp, struct pt
- #endif
- }
-
-+int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs)
-+{
-+ struct thread_info *ti = tsk->thread_info;
-+ long ksp = (unsigned long)ti + THREAD_SIZE - 32;
-+ dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1);
-+ return 1;
-+}
-+
- int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr)
- {
- memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
-@@ -211,22 +269,48 @@ long kernel_thread(int (*fn)(void *), vo
- return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
- }
-
--struct mips_frame_info {
-+static struct mips_frame_info {
-+ void *func;
-+ int omit_fp; /* compiled without fno-omit-frame-pointer */
- int frame_offset;
- int pc_offset;
-+} schedule_frame, mfinfo[] = {
-+ { schedule, 0 }, /* must be first */
-+ /* arch/mips/kernel/semaphore.c */
-+ { __down, 1 },
-+ { __down_interruptible, 1 },
-+ /* kernel/sched.c */
-+#ifdef CONFIG_PREEMPT
-+ { preempt_schedule, 0 },
-+#endif
-+ { wait_for_completion, 0 },
-+ { interruptible_sleep_on, 0 },
-+ { interruptible_sleep_on_timeout, 0 },
-+ { sleep_on, 0 },
-+ { sleep_on_timeout, 0 },
-+ { yield, 0 },
-+ { io_schedule, 0 },
-+ { io_schedule_timeout, 0 },
-+#if defined(CONFIG_SMP) && defined(CONFIG_PREEMPT)
-+ { __preempt_spin_lock, 0 },
-+ { __preempt_write_lock, 0 },
-+#endif
-+ /* kernel/timer.c */
-+ { schedule_timeout, 1 },
-+/* { nanosleep_restart, 1 }, */
-+ /* lib/rwsem-spinlock.c */
-+ { __down_read, 1 },
-+ { __down_write, 1 },
- };
--static struct mips_frame_info schedule_frame;
--static struct mips_frame_info schedule_timeout_frame;
--static struct mips_frame_info sleep_on_frame;
--static struct mips_frame_info sleep_on_timeout_frame;
--static struct mips_frame_info wait_for_completion_frame;
-+
- static int mips_frame_info_initialized;
--static int __init get_frame_info(struct mips_frame_info *info, void *func)
-+static int __init get_frame_info(struct mips_frame_info *info)
- {
- int i;
-+ void *func = info->func;
- union mips_instruction *ip = (union mips_instruction *)func;
- info->pc_offset = -1;
-- info->frame_offset = -1;
-+ info->frame_offset = info->omit_fp ? 0 : -1;
- for (i = 0; i < 128; i++, ip++) {
- /* if jal, jalr, jr, stop. */
- if (ip->j_format.opcode == jal_op ||
-@@ -247,14 +331,16 @@ static int __init get_frame_info(struct
- /* sw / sd $ra, offset($sp) */
- if (ip->i_format.rt == 31) {
- if (info->pc_offset != -1)
-- break;
-+ continue;
- info->pc_offset =
- ip->i_format.simmediate / sizeof(long);
- }
- /* sw / sd $s8, offset($sp) */
- if (ip->i_format.rt == 30) {
-+//#if 0 /* gcc 3.4 does aggressive optimization... */
- if (info->frame_offset != -1)
-- break;
-+ continue;
-+//#endif
- info->frame_offset =
- ip->i_format.simmediate / sizeof(long);
- }
-@@ -272,13 +358,25 @@ static int __init get_frame_info(struct
-
- static int __init frame_info_init(void)
- {
-- mips_frame_info_initialized =
-- !get_frame_info(&schedule_frame, schedule) &&
-- !get_frame_info(&schedule_timeout_frame, schedule_timeout) &&
-- !get_frame_info(&sleep_on_frame, sleep_on) &&
-- !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) &&
-- !get_frame_info(&wait_for_completion_frame, wait_for_completion);
--
-+ int i, found;
-+ for (i = 0; i < ARRAY_SIZE(mfinfo); i++)
-+ if (get_frame_info(&mfinfo[i]))
-+ return -1;
-+ schedule_frame = mfinfo[0];
-+ /* bubble sort */
-+ do {
-+ struct mips_frame_info tmp;
-+ found = 0;
-+ for (i = 1; i < ARRAY_SIZE(mfinfo); i++) {
-+ if (mfinfo[i-1].func > mfinfo[i].func) {
-+ tmp = mfinfo[i];
-+ mfinfo[i] = mfinfo[i-1];
-+ mfinfo[i-1] = tmp;
-+ found = 1;
-+ }
-+ }
-+ } while (found);
-+ mips_frame_info_initialized = 1;
- return 0;
- }
-
-@@ -311,53 +409,27 @@ unsigned long get_wchan(struct task_stru
- if (!mips_frame_info_initialized)
- return 0;
- pc = thread_saved_pc(p);
-+
- if (!in_sched_functions(pc))
- goto out;
-
-- if (pc >= (unsigned long) sleep_on_timeout)
-- goto schedule_timeout_caller;
-- if (pc >= (unsigned long) sleep_on)
-- goto schedule_caller;
-- if (pc >= (unsigned long) interruptible_sleep_on_timeout)
-- goto schedule_timeout_caller;
-- if (pc >= (unsigned long)interruptible_sleep_on)
-- goto schedule_caller;
-- if (pc >= (unsigned long)wait_for_completion)
-- goto schedule_caller;
-- goto schedule_timeout_caller;
--
--schedule_caller:
-- frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset];
-- if (pc >= (unsigned long) sleep_on)
-- pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset];
-- else
-- pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset];
-- goto out;
--
--schedule_timeout_caller:
-- /*
-- * The schedule_timeout frame
-- */
- frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset];
-+ do {
-+ int i;
-+ for (i = ARRAY_SIZE(mfinfo) - 1; i >= 0; i--) {
-+ if (pc >= (unsigned long) mfinfo[i].func)
-+ break;
-+ }
-+ if (i < 0)
-+ break;
-
-- /*
-- * frame now points to sleep_on_timeout's frame
-- */
-- pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset];
--
-- if (in_sched_functions(pc)) {
-- /* schedule_timeout called by [interruptible_]sleep_on_timeout */
-- frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset];
-- pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset];
-- }
-+ if (mfinfo[i].omit_fp)
-+ break;
-+ pc = ((unsigned long *)frame)[mfinfo[i].pc_offset];
-+ frame = ((unsigned long *)frame)[mfinfo[i].frame_offset];
-+ } while (in_sched_functions(pc));
-
- out:
--
--#ifdef CONFIG_MIPS64
-- if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */
-- pc &= 0xffffffffUL;
--#endif
--
- return pc;
- }
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/ptrace.c linux_HEAD/arch/mips/kernel/ptrace.c
---- linux-2.6.12/arch/mips/kernel/ptrace.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/ptrace.c 2005-07-01 12:09:18.000000000 +0200
-@@ -21,14 +21,16 @@
- #include <linux/mm.h>
- #include <linux/errno.h>
- #include <linux/ptrace.h>
--#include <linux/audit.h>
- #include <linux/smp.h>
- #include <linux/smp_lock.h>
- #include <linux/user.h>
- #include <linux/security.h>
--#include <linux/signal.h>
-+#include <linux/audit.h>
-+#include <linux/seccomp.h>
-
-+#include <asm/byteorder.h>
- #include <asm/cpu.h>
-+#include <asm/dsp.h>
- #include <asm/fpu.h>
- #include <asm/mipsregs.h>
- #include <asm/pgtable.h>
-@@ -103,7 +105,7 @@ asmlinkage int sys_ptrace(long request,
- ret = -EIO;
- if (copied != sizeof(tmp))
- break;
-- ret = put_user(tmp,(unsigned long *) data);
-+ ret = put_user(tmp,(unsigned long __user *) data);
- break;
- }
-
-@@ -175,12 +177,36 @@ asmlinkage int sys_ptrace(long request,
- write_c0_status(flags);
- break;
- }
-+ case DSP_BASE ... DSP_BASE + 5: {
-+ dspreg_t *dregs;
-+
-+ if (!cpu_has_dsp) {
-+ tmp = 0;
-+ ret = -EIO;
-+ goto out_tsk;
-+ }
-+ if (child->thread.dsp.used_dsp) {
-+ dregs = __get_dsp_regs(child);
-+ tmp = (unsigned long) (dregs[addr - DSP_BASE]);
-+ } else {
-+ tmp = -1; /* DSP registers yet used */
-+ }
-+ break;
-+ }
-+ case DSP_CONTROL:
-+ if (!cpu_has_dsp) {
-+ tmp = 0;
-+ ret = -EIO;
-+ goto out_tsk;
-+ }
-+ tmp = child->thread.dsp.dspcontrol;
-+ break;
- default:
- tmp = 0;
- ret = -EIO;
- goto out_tsk;
- }
-- ret = put_user(tmp, (unsigned long *) data);
-+ ret = put_user(tmp, (unsigned long __user *) data);
- break;
- }
-
-@@ -247,6 +273,25 @@ asmlinkage int sys_ptrace(long request,
- else
- child->thread.fpu.soft.fcr31 = data;
- break;
-+ case DSP_BASE ... DSP_BASE + 5: {
-+ dspreg_t *dregs;
-+
-+ if (!cpu_has_dsp) {
-+ ret = -EIO;
-+ break;
-+ }
-+
-+ dregs = __get_dsp_regs(child);
-+ dregs[addr - DSP_BASE] = data;
-+ break;
-+ }
-+ case DSP_CONTROL:
-+ if (!cpu_has_dsp) {
-+ ret = -EIO;
-+ break;
-+ }
-+ child->thread.dsp.dspcontrol = data;
-+ break;
- default:
- /* The rest are not allowed. */
- ret = -EIO;
-@@ -289,6 +334,11 @@ asmlinkage int sys_ptrace(long request,
- ret = ptrace_detach(child, data);
- break;
-
-+ case PTRACE_GET_THREAD_AREA:
-+ ret = put_user(child->thread_info->tp_value,
-+ (unsigned long __user *) data);
-+ break;
-+
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
-@@ -303,21 +353,14 @@ out:
-
- static inline int audit_arch(void)
- {
--#ifdef CONFIG_CPU_LITTLE_ENDIAN
--#ifdef CONFIG_MIPS64
-- if (!(current->thread.mflags & MF_32BIT_REGS))
-- return AUDIT_ARCH_MIPSEL64;
--#endif /* MIPS64 */
-- return AUDIT_ARCH_MIPSEL;
--
--#else /* big endian... */
-+ int arch = EM_MIPS;
- #ifdef CONFIG_MIPS64
-- if (!(current->thread.mflags & MF_32BIT_REGS))
-- return AUDIT_ARCH_MIPS64;
--#endif /* MIPS64 */
-- return AUDIT_ARCH_MIPS;
--
--#endif /* endian */
-+ arch |= __AUDIT_ARCH_64BIT;
-+#endif
-+#if defined(__LITTLE_ENDIAN)
-+ arch |= __AUDIT_ARCH_LE;
-+#endif
-+ return arch;
- }
-
- /*
-@@ -326,14 +369,19 @@ static inline int audit_arch(void)
- */
- asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
- {
-+ /* do the secure computing check first */
-+ secure_computing(regs->orig_eax);
-+
- if (unlikely(current->audit_context) && entryexit)
-- audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), regs->regs[2]);
-+ audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]),
-+ regs->regs[2]);
-
-- if (!test_thread_flag(TIF_SYSCALL_TRACE))
-- goto out;
- if (!(current->ptrace & PT_PTRACED))
- goto out;
-
-+ if (!test_thread_flag(TIF_SYSCALL_TRACE))
-+ goto out;
-+
- /* The 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
-@@ -348,9 +396,14 @@ asmlinkage void do_syscall_trace(struct
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-- out:
-+
-+out:
-+ /* There is no ->orig_eax and that's quite intensional for now making
-+ this work will require some work in various other place before it's
-+ more than a placebo. */
-+
- if (unlikely(current->audit_context) && !entryexit)
-- audit_syscall_entry(current, audit_arch(), regs->regs[2],
-- regs->regs[4], regs->regs[5],
-- regs->regs[6], regs->regs[7]);
-+ audit_syscall_entry(current, audit_arch(), regs->orig_eax,
-+ regs->regs[4], regs->regs[5],
-+ regs->regs[6], regs->regs[7]);
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/ptrace32.c linux_HEAD/arch/mips/kernel/ptrace32.c
---- linux-2.6.12/arch/mips/kernel/ptrace32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/ptrace32.c 2005-07-01 12:09:18.000000000 +0200
-@@ -24,9 +24,9 @@
- #include <linux/smp_lock.h>
- #include <linux/user.h>
- #include <linux/security.h>
--#include <linux/signal.h>
-
- #include <asm/cpu.h>
-+#include <asm/dsp.h>
- #include <asm/fpu.h>
- #include <asm/mipsregs.h>
- #include <asm/pgtable.h>
-@@ -162,6 +162,27 @@ asmlinkage int sys32_ptrace(int request,
- write_c0_status(flags);
- break;
- }
-+ case DSP_BASE ... DSP_BASE + 5:
-+ if (!cpu_has_dsp) {
-+ tmp = 0;
-+ ret = -EIO;
-+ goto out_tsk;
-+ }
-+ if (child->thread.dsp.used_dsp) {
-+ dspreg_t *dregs = __get_dsp_regs(child);
-+ tmp = (unsigned long) (dregs[addr - DSP_BASE]);
-+ } else {
-+ tmp = -1; /* DSP registers yet used */
-+ }
-+ break;
-+ case DSP_CONTROL:
-+ if (!cpu_has_dsp) {
-+ tmp = 0;
-+ ret = -EIO;
-+ goto out_tsk;
-+ }
-+ tmp = child->thread.dsp.dspcontrol;
-+ break;
- default:
- tmp = 0;
- ret = -EIO;
-@@ -231,6 +252,22 @@ asmlinkage int sys32_ptrace(int request,
- else
- child->thread.fpu.soft.fcr31 = data;
- break;
-+ case DSP_BASE ... DSP_BASE + 5:
-+ if (!cpu_has_dsp) {
-+ ret = -EIO;
-+ break;
-+ }
-+
-+ dspreg_t *dregs = __get_dsp_regs(child);
-+ dregs[addr - DSP_BASE] = data;
-+ break;
-+ case DSP_CONTROL:
-+ if (!cpu_has_dsp) {
-+ ret = -EIO;
-+ break;
-+ }
-+ child->thread.dsp.dspcontrol = data;
-+ break;
- default:
- /* The rest are not allowed. */
- ret = -EIO;
-@@ -269,10 +306,20 @@ asmlinkage int sys32_ptrace(int request,
- wake_up_process(child);
- break;
-
-+ case PTRACE_GET_THREAD_AREA:
-+ ret = put_user(child->thread_info->tp_value,
-+ (unsigned int __user *) (unsigned long) data);
-+ break;
-+
- case PTRACE_DETACH: /* detach a process that was attached. */
- ret = ptrace_detach(child, data);
- break;
-
-+ case PTRACE_GETEVENTMSG:
-+ ret = put_user(child->ptrace_message,
-+ (unsigned int __user *) (unsigned long) data);
-+ break;
-+
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/r4k_fpu.S linux_HEAD/arch/mips/kernel/r4k_fpu.S
---- linux-2.6.12/arch/mips/kernel/r4k_fpu.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/r4k_fpu.S 2005-07-01 12:09:18.000000000 +0200
-@@ -32,7 +32,7 @@
-
- .set noreorder
- .set mips3
-- /* Save floating point context */
-+
- LEAF(_save_fp_context)
- cfc1 t1, fcr31
-
-@@ -74,9 +74,6 @@ LEAF(_save_fp_context)
- EX sdc1 $f28, SC_FPREGS+224(a0)
- EX sdc1 $f30, SC_FPREGS+240(a0)
- EX sw t1, SC_FPC_CSR(a0)
-- cfc1 t0, $0 # implementation/version
-- EX sw t0, SC_FPC_EIR(a0)
--
- jr ra
- li v0, 0 # success
- END(_save_fp_context)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/r4k_switch.S linux_HEAD/arch/mips/kernel/r4k_switch.S
---- linux-2.6.12/arch/mips/kernel/r4k_switch.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/r4k_switch.S 2005-07-07 11:22:49.000000000 +0200
-@@ -165,7 +165,7 @@ LEAF(_init_fpu)
- 1:
- #endif
-
--#ifdef CONFIG_CPU_MIPS32
-+#ifdef CONFIG_CPU_MIPS32_R1
- mtc1 t1, $f0
- mtc1 t1, $f1
- mtc1 t1, $f2
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/scall32-o32.S linux_HEAD/arch/mips/kernel/scall32-o32.S
---- linux-2.6.12/arch/mips/kernel/scall32-o32.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/scall32-o32.S 2005-07-01 12:09:18.000000000 +0200
-@@ -578,7 +578,7 @@ einval: li v0, -EINVAL
- sys sys_fremovexattr 2 /* 4235 */
- sys sys_tkill 2
- sys sys_sendfile64 5
-- sys sys_futex 2
-+ sys sys_futex 6
- sys sys_sched_setaffinity 3
- sys sys_sched_getaffinity 3 /* 4240 */
- sys sys_io_setup 2
-@@ -618,11 +618,12 @@ einval: li v0, -EINVAL
- sys sys_mq_notify 2 /* 4275 */
- sys sys_mq_getsetattr 3
- sys sys_ni_syscall 0 /* sys_vserver */
-- sys sys_waitid 4
-+ sys sys_waitid 5
- sys sys_ni_syscall 0 /* available, was setaltroot */
-- sys sys_add_key 5
-+ sys sys_add_key 5 /* 4280 */
- sys sys_request_key 4
- sys sys_keyctl 5
-+ sys sys_set_thread_area 1
-
- .endm
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/scall64-64.S linux_HEAD/arch/mips/kernel/scall64-64.S
---- linux-2.6.12/arch/mips/kernel/scall64-64.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/scall64-64.S 2005-04-13 19:06:33.000000000 +0200
-@@ -449,3 +449,4 @@ sys_call_table:
- PTR sys_add_key
- PTR sys_request_key /* 5240 */
- PTR sys_keyctl
-+ PTR sys_set_thread_area
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/scall64-n32.S linux_HEAD/arch/mips/kernel/scall64-n32.S
---- linux-2.6.12/arch/mips/kernel/scall64-n32.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/scall64-n32.S 2005-04-16 22:59:17.000000000 +0200
-@@ -176,7 +176,7 @@ EXPORT(sysn32_call_table)
- PTR sys_fork
- PTR sys32_execve
- PTR sys_exit
-- PTR sys32_wait4
-+ PTR compat_sys_wait4
- PTR sys_kill /* 6060 */
- PTR sys32_newuname
- PTR sys_semget
-@@ -243,14 +243,14 @@ EXPORT(sysn32_call_table)
- PTR sys_capget
- PTR sys_capset
- PTR sys32_rt_sigpending /* 6125 */
-- PTR compat_sys_rt_sigtimedwait
-- PTR sys32_rt_sigqueueinfo
-+ PTR sysn32_rt_sigtimedwait
-+ PTR sys_rt_sigqueueinfo
- PTR sys32_rt_sigsuspend
- PTR sys32_sigaltstack
- PTR compat_sys_utime /* 6130 */
- PTR sys_mknod
- PTR sys32_personality
-- PTR sys_ustat
-+ PTR sys32_ustat
- PTR compat_sys_statfs
- PTR compat_sys_fstatfs /* 6135 */
- PTR sys_sysfs
-@@ -329,7 +329,7 @@ EXPORT(sysn32_call_table)
- PTR sys_epoll_wait
- PTR sys_remap_file_pages /* 6210 */
- PTR sysn32_rt_sigreturn
-- PTR sys_fcntl
-+ PTR compat_sys_fcntl64
- PTR sys_set_tid_address
- PTR sys_restart_syscall
- PTR sys_semtimedop /* 6215 */
-@@ -337,15 +337,15 @@ EXPORT(sysn32_call_table)
- PTR compat_sys_statfs64
- PTR compat_sys_fstatfs64
- PTR sys_sendfile64
-- PTR sys_timer_create /* 6220 */
-- PTR sys_timer_settime
-- PTR sys_timer_gettime
-+ PTR sys32_timer_create /* 6220 */
-+ PTR compat_sys_timer_settime
-+ PTR compat_sys_timer_gettime
- PTR sys_timer_getoverrun
- PTR sys_timer_delete
-- PTR sys_clock_settime /* 6225 */
-- PTR sys_clock_gettime
-- PTR sys_clock_getres
-- PTR sys_clock_nanosleep
-+ PTR compat_sys_clock_settime /* 6225 */
-+ PTR compat_sys_clock_gettime
-+ PTR compat_sys_clock_getres
-+ PTR compat_sys_clock_nanosleep
- PTR sys_tgkill
- PTR compat_sys_utimes /* 6230 */
- PTR sys_ni_syscall /* sys_mbind */
-@@ -358,8 +358,9 @@ EXPORT(sysn32_call_table)
- PTR compat_sys_mq_notify
- PTR compat_sys_mq_getsetattr
- PTR sys_ni_syscall /* 6240, sys_vserver */
-- PTR sys_waitid
-+ PTR sysn32_waitid
- PTR sys_ni_syscall /* available, was setaltroot */
- PTR sys_add_key
- PTR sys_request_key
- PTR sys_keyctl /* 6245 */
-+ PTR sys_set_thread_area
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/scall64-o32.S linux_HEAD/arch/mips/kernel/scall64-o32.S
---- linux-2.6.12/arch/mips/kernel/scall64-o32.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/scall64-o32.S 2005-05-09 13:20:25.000000000 +0200
-@@ -316,13 +316,13 @@ sys_call_table:
- PTR sys_vhangup
- PTR sys_ni_syscall /* was sys_idle */
- PTR sys_ni_syscall /* sys_vm86 */
-- PTR sys32_wait4
-+ PTR compat_sys_wait4
- PTR sys_swapoff /* 4115 */
- PTR sys32_sysinfo
- PTR sys32_ipc
- PTR sys_fsync
- PTR sys32_sigreturn
-- PTR sys_clone /* 4120 */
-+ PTR sys32_clone /* 4120 */
- PTR sys_setdomainname
- PTR sys32_newuname
- PTR sys_ni_syscall /* sys_modify_ldt */
-@@ -391,7 +391,7 @@ sys_call_table:
- PTR sys_getresuid
- PTR sys_ni_syscall /* was query_module */
- PTR sys_poll
-- PTR sys_nfsservctl
-+ PTR compat_sys_nfsservctl
- PTR sys_setresgid /* 4190 */
- PTR sys_getresgid
- PTR sys_prctl
-@@ -459,7 +459,7 @@ sys_call_table:
- PTR sys_fadvise64_64
- PTR compat_sys_statfs64 /* 4255 */
- PTR compat_sys_fstatfs64
-- PTR sys_timer_create
-+ PTR sys32_timer_create
- PTR compat_sys_timer_settime
- PTR compat_sys_timer_gettime
- PTR sys_timer_getoverrun /* 4260 */
-@@ -480,9 +480,10 @@ sys_call_table:
- PTR compat_sys_mq_notify /* 4275 */
- PTR compat_sys_mq_getsetattr
- PTR sys_ni_syscall /* sys_vserver */
-- PTR sys_waitid
-+ PTR sys32_waitid
- PTR sys_ni_syscall /* available, was setaltroot */
- PTR sys_add_key /* 4280 */
- PTR sys_request_key
- PTR sys_keyctl
-+ PTR sys_set_thread_area
- .size sys_call_table,.-sys_call_table
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/semaphore.c linux_HEAD/arch/mips/kernel/semaphore.c
---- linux-2.6.12/arch/mips/kernel/semaphore.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/semaphore.c 2005-07-01 12:09:18.000000000 +0200
-@@ -42,24 +42,28 @@ static inline int __sem_update_count(str
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
-- "1: ll %0, %2 \n"
-+ " .set mips3 \n"
-+ "1: ll %0, %2 # __sem_update_count \n"
- " sra %1, %0, 31 \n"
- " not %1 \n"
- " and %1, %0, %1 \n"
-- " add %1, %1, %3 \n"
-+ " addu %1, %1, %3 \n"
- " sc %1, %2 \n"
- " beqzl %1, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
- : "r" (incr), "m" (sem->count));
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
-- "1: ll %0, %2 \n"
-+ " .set mips3 \n"
-+ "1: ll %0, %2 # __sem_update_count \n"
- " sra %1, %0, 31 \n"
- " not %1 \n"
- " and %1, %0, %1 \n"
-- " add %1, %1, %3 \n"
-+ " addu %1, %1, %3 \n"
- " sc %1, %2 \n"
- " beqz %1, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
- : "r" (incr), "m" (sem->count));
- } else {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/setup.c linux_HEAD/arch/mips/kernel/setup.c
---- linux-2.6.12/arch/mips/kernel/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/setup.c 2005-07-10 12:16:33.000000000 +0200
-@@ -507,32 +507,6 @@ static inline void resource_init(void)
- #undef MAXMEM
- #undef MAXMEM_PFN
-
--static int __initdata earlyinit_debug;
--
--static int __init earlyinit_debug_setup(char *str)
--{
-- earlyinit_debug = 1;
-- return 1;
--}
--__setup("earlyinit_debug", earlyinit_debug_setup);
--
--extern initcall_t __earlyinitcall_start, __earlyinitcall_end;
--
--static void __init do_earlyinitcalls(void)
--{
-- initcall_t *call, *start, *end;
--
-- start = &__earlyinitcall_start;
-- end = &__earlyinitcall_end;
--
-- for (call = start; call < end; call++) {
-- if (earlyinit_debug)
-- printk("calling earlyinitcall 0x%p\n", *call);
--
-- (*call)();
-- }
--}
--
- void __init setup_arch(char **cmdline_p)
- {
- cpu_probe();
-@@ -548,7 +522,7 @@ void __init setup_arch(char **cmdline_p)
- #endif
-
- /* call board setup routine */
-- do_earlyinitcalls();
-+ plat_setup();
-
- strlcpy(command_line, arcs_cmdline, sizeof(command_line));
- strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
-@@ -569,3 +543,12 @@ int __init fpu_disable(char *s)
- }
-
- __setup("nofpu", fpu_disable);
-+
-+int __init dsp_disable(char *s)
-+{
-+ cpu_data[0].options &= ~MIPS_ASE_DSP;
-+
-+ return 1;
-+}
-+
-+__setup("nodsp", dsp_disable);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/signal-common.h linux_HEAD/arch/mips/kernel/signal-common.h
---- linux-2.6.12/arch/mips/kernel/signal-common.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/signal-common.h 2005-07-01 12:09:18.000000000 +0200
-@@ -8,13 +8,14 @@
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-
-+#include <linux/config.h>
-+
- static inline int
- setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
- {
- int err = 0;
-
- err |= __put_user(regs->cp0_epc, &sc->sc_pc);
-- err |= __put_user(regs->cp0_status, &sc->sc_status);
-
- #define save_gp_reg(i) do { \
- err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \
-@@ -30,10 +31,32 @@ setup_sigcontext(struct pt_regs *regs, s
- save_gp_reg(31);
- #undef save_gp_reg
-
-+#ifdef CONFIG_MIPS32
- err |= __put_user(regs->hi, &sc->sc_mdhi);
- err |= __put_user(regs->lo, &sc->sc_mdlo);
-- err |= __put_user(regs->cp0_cause, &sc->sc_cause);
-- err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr);
-+ if (cpu_has_dsp) {
-+ err |= __put_user(mfhi1(), &sc->sc_hi1);
-+ err |= __put_user(mflo1(), &sc->sc_lo1);
-+ err |= __put_user(mfhi2(), &sc->sc_hi2);
-+ err |= __put_user(mflo2(), &sc->sc_lo2);
-+ err |= __put_user(mfhi3(), &sc->sc_hi3);
-+ err |= __put_user(mflo3(), &sc->sc_lo3);
-+ err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
-+ }
-+#endif
-+#ifdef CONFIG_MIPS64
-+ err |= __put_user(regs->hi, &sc->sc_hi[0]);
-+ err |= __put_user(regs->lo, &sc->sc_lo[0]);
-+ if (cpu_has_dsp) {
-+ err |= __put_user(mfhi1(), &sc->sc_hi[1]);
-+ err |= __put_user(mflo1(), &sc->sc_lo[1]);
-+ err |= __put_user(mfhi2(), &sc->sc_hi[2]);
-+ err |= __put_user(mflo2(), &sc->sc_lo[2]);
-+ err |= __put_user(mfhi3(), &sc->sc_hi[3]);
-+ err |= __put_user(mflo3(), &sc->sc_lo[3]);
-+ err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
-+ }
-+#endif
-
- err |= __put_user(!!used_math(), &sc->sc_used_math);
-
-@@ -61,15 +84,40 @@ out:
- static inline int
- restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
- {
-- int err = 0;
- unsigned int used_math;
-+ unsigned long treg;
-+ int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current_thread_info()->restart_block.fn = do_no_restart_syscall;
-
- err |= __get_user(regs->cp0_epc, &sc->sc_pc);
-+#ifdef CONFIG_MIPS32
- err |= __get_user(regs->hi, &sc->sc_mdhi);
- err |= __get_user(regs->lo, &sc->sc_mdlo);
-+ if (cpu_has_dsp) {
-+ err |= __get_user(treg, &sc->sc_hi1); mthi1(treg);
-+ err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg);
-+ err |= __get_user(treg, &sc->sc_hi2); mthi2(treg);
-+ err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg);
-+ err |= __get_user(treg, &sc->sc_hi3); mthi3(treg);
-+ err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
-+ err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
-+ }
-+#endif
-+#ifdef CONFIG_MIPS64
-+ err |= __get_user(regs->hi, &sc->sc_hi[0]);
-+ err |= __get_user(regs->lo, &sc->sc_lo[0]);
-+ if (cpu_has_dsp) {
-+ err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg);
-+ err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg);
-+ err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg);
-+ err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg);
-+ err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg);
-+ err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg);
-+ err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
-+ }
-+#endif
-
- #define restore_gp_reg(i) do { \
- err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
-@@ -112,7 +160,7 @@ restore_sigcontext(struct pt_regs *regs,
- static inline void *
- get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
- {
-- unsigned long sp, almask;
-+ unsigned long sp;
-
- /* Default to using normal stack */
- sp = regs->regs[29];
-@@ -128,10 +176,32 @@ get_sigframe(struct k_sigaction *ka, str
- if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
- sp = current->sas_ss_sp + current->sas_ss_size;
-
-- if (PLAT_TRAMPOLINE_STUFF_LINE)
-- almask = ~(PLAT_TRAMPOLINE_STUFF_LINE - 1);
-- else
-- almask = ALMASK;
-+ return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK));
-+}
-+
-+static inline int install_sigtramp(unsigned int __user *tramp,
-+ unsigned int syscall)
-+{
-+ int err;
-+
-+ /*
-+ * Set up the return code ...
-+ *
-+ * li v0, __NR__foo_sigreturn
-+ * syscall
-+ */
-+
-+ err |= __put_user(0x24020000 + syscall, tramp + 0);
-+ err |= __put_user(0x0000000c , tramp + 1);
-+ if (ICACHE_REFILLS_WORKAROUND_WAR) {
-+ err |= __put_user(0, tramp + 2);
-+ err |= __put_user(0, tramp + 3);
-+ err |= __put_user(0, tramp + 4);
-+ err |= __put_user(0, tramp + 5);
-+ err |= __put_user(0, tramp + 6);
-+ err |= __put_user(0, tramp + 7);
-+ }
-+ flush_cache_sigtramp((unsigned long) tramp);
-
-- return (void *)((sp - frame_size) & almask);
-+ return err;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/signal.c linux_HEAD/arch/mips/kernel/signal.c
---- linux-2.6.12/arch/mips/kernel/signal.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/signal.c 2005-07-01 12:09:18.000000000 +0200
-@@ -8,6 +8,7 @@
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
- #include <linux/config.h>
-+#include <linux/cache.h>
- #include <linux/sched.h>
- #include <linux/mm.h>
- #include <linux/personality.h>
-@@ -21,6 +22,7 @@
- #include <linux/unistd.h>
- #include <linux/compiler.h>
-
-+#include <asm/abi.h>
- #include <asm/asm.h>
- #include <linux/bitops.h>
- #include <asm/cacheflush.h>
-@@ -29,6 +31,7 @@
- #include <asm/uaccess.h>
- #include <asm/ucontext.h>
- #include <asm/cpu-features.h>
-+#include <asm/war.h>
-
- #include "signal-common.h"
-
-@@ -36,7 +39,7 @@
-
- #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
--static int do_signal(sigset_t *oldset, struct pt_regs *regs);
-+int do_signal(sigset_t *oldset, struct pt_regs *regs);
-
- /*
- * Atomically swap in the new signal mask, and wait for a signal.
-@@ -47,9 +50,10 @@ save_static_function(sys_sigsuspend);
- __attribute_used__ noinline static int
- _sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
- {
-- sigset_t *uset, saveset, newset;
-+ sigset_t saveset, newset;
-+ sigset_t __user *uset;
-
-- uset = (sigset_t *) regs.regs[4];
-+ uset = (sigset_t __user *) regs.regs[4];
- if (copy_from_user(&newset, uset, sizeof(sigset_t)))
- return -EFAULT;
- sigdelsetmask(&newset, ~_BLOCKABLE);
-@@ -75,7 +79,8 @@ save_static_function(sys_rt_sigsuspend);
- __attribute_used__ noinline static int
- _sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
- {
-- sigset_t *unewset, saveset, newset;
-+ sigset_t saveset, newset;
-+ sigset_t __user *unewset;
- size_t sigsetsize;
-
- /* XXX Don't preclude handling different sized sigset_t's. */
-@@ -83,7 +88,7 @@ _sys_rt_sigsuspend(nabi_no_regargs struc
- if (sigsetsize != sizeof(sigset_t))
- return -EINVAL;
-
-- unewset = (sigset_t *) regs.regs[4];
-+ unewset = (sigset_t __user *) regs.regs[4];
- if (copy_from_user(&newset, unewset, sizeof(newset)))
- return -EFAULT;
- sigdelsetmask(&newset, ~_BLOCKABLE);
-@@ -147,33 +152,46 @@ asmlinkage int sys_sigaction(int sig, co
-
- asmlinkage int sys_sigaltstack(nabi_no_regargs struct pt_regs regs)
- {
-- const stack_t *uss = (const stack_t *) regs.regs[4];
-- stack_t *uoss = (stack_t *) regs.regs[5];
-+ const stack_t __user *uss = (const stack_t __user *) regs.regs[4];
-+ stack_t __user *uoss = (stack_t __user *) regs.regs[5];
- unsigned long usp = regs.regs[29];
-
- return do_sigaltstack(uss, uoss, usp);
- }
-
--#if PLAT_TRAMPOLINE_STUFF_LINE
--#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE)))
--#else
--#define __tramp
--#endif
--
-+/*
-+ * Horribly complicated - with the bloody RM9000 workarounds enabled
-+ * the signal trampolines is moving to the end of the structure so we can
-+ * increase the alignment without breaking software compatibility.
-+ */
- #ifdef CONFIG_TRAD_SIGNALS
- struct sigframe {
- u32 sf_ass[4]; /* argument save space for o32 */
-- u32 sf_code[2] __tramp; /* signal trampoline */
-- struct sigcontext sf_sc __tramp;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 sf_pad[2];
-+#else
-+ u32 sf_code[2]; /* signal trampoline */
-+#endif
-+ struct sigcontext sf_sc;
- sigset_t sf_mask;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */
-+#endif
- };
- #endif
-
- struct rt_sigframe {
- u32 rs_ass[4]; /* argument save space for o32 */
-- u32 rs_code[2] __tramp; /* signal trampoline */
-- struct siginfo rs_info __tramp;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_pad[2];
-+#else
-+ u32 rs_code[2]; /* signal trampoline */
-+#endif
-+ struct siginfo rs_info;
- struct ucontext rs_uc;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */
-+#endif
- };
-
- #ifdef CONFIG_TRAD_SIGNALS
-@@ -214,7 +232,7 @@ _sys_sigreturn(nabi_no_regargs struct pt
- badframe:
- force_sig(SIGSEGV, current);
- }
--#endif
-+#endif /* CONFIG_TRAD_SIGNALS */
-
- save_static_function(sys_rt_sigreturn);
- __attribute_used__ noinline static void
-@@ -260,7 +278,7 @@ badframe:
- }
-
- #ifdef CONFIG_TRAD_SIGNALS
--static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
-+void setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
- int signr, sigset_t *set)
- {
- struct sigframe *frame;
-@@ -270,17 +288,7 @@ static void inline setup_frame(struct k_
- if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
- goto give_sigsegv;
-
-- /*
-- * Set up the return code ...
-- *
-- * li v0, __NR_sigreturn
-- * syscall
-- */
-- if (PLAT_TRAMPOLINE_STUFF_LINE)
-- __clear_user(frame->sf_code, PLAT_TRAMPOLINE_STUFF_LINE);
-- err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0);
-- err |= __put_user(0x0000000c , frame->sf_code + 1);
-- flush_cache_sigtramp((unsigned long) frame->sf_code);
-+ install_sigtramp(frame->sf_code, __NR_sigreturn);
-
- err |= setup_sigcontext(regs, &frame->sf_sc);
- err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set));
-@@ -316,7 +324,7 @@ give_sigsegv:
- }
- #endif
-
--static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
-+void setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
- int signr, sigset_t *set, siginfo_t *info)
- {
- struct rt_sigframe *frame;
-@@ -326,17 +334,7 @@ static void inline setup_rt_frame(struct
- if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
- goto give_sigsegv;
-
-- /*
-- * Set up the return code ...
-- *
-- * li v0, __NR_rt_sigreturn
-- * syscall
-- */
-- if (PLAT_TRAMPOLINE_STUFF_LINE)
-- __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE);
-- err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0);
-- err |= __put_user(0x0000000c , frame->rs_code + 1);
-- flush_cache_sigtramp((unsigned long) frame->rs_code);
-+ install_sigtramp(frame->rs_code, __NR_rt_sigreturn);
-
- /* Create siginfo. */
- err |= copy_siginfo_to_user(&frame->rs_info, info);
-@@ -408,22 +406,10 @@ static inline void handle_signal(unsigne
-
- regs->regs[0] = 0; /* Don't deal with this again. */
-
--#ifdef CONFIG_TRAD_SIGNALS
-- if (ka->sa.sa_flags & SA_SIGINFO) {
--#else
-- if (1) {
--#endif
--#ifdef CONFIG_MIPS32_N32
-- if ((current->thread.mflags & MF_ABI_MASK) == MF_N32)
-- setup_rt_frame_n32 (ka, regs, sig, oldset, info);
-- else
--#endif
-- setup_rt_frame(ka, regs, sig, oldset, info);
-- }
--#ifdef CONFIG_TRAD_SIGNALS
-+ if (sig_uses_siginfo(ka))
-+ current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info);
- else
-- setup_frame(ka, regs, sig, oldset);
--#endif
-+ current->thread.abi->setup_frame(ka, regs, sig, oldset);
-
- if (!(ka->sa.sa_flags & SA_NODEFER)) {
- spin_lock_irq(¤t->sighand->siglock);
-@@ -434,21 +420,12 @@ static inline void handle_signal(unsigne
- }
- }
-
--extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
--extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs);
--
--static int do_signal(sigset_t *oldset, struct pt_regs *regs)
-+int do_signal(sigset_t *oldset, struct pt_regs *regs)
- {
- struct k_sigaction ka;
- siginfo_t info;
- int signr;
-
--#ifdef CONFIG_BINFMT_ELF32
-- if ((current->thread.mflags & MF_ABI_MASK) == MF_O32) {
-- return do_signal32(oldset, regs);
-- }
--#endif
--
- /*
- * We want the common case to go fast, which is why we may in certain
- * cases get here from kernel mode. Just return without doing anything
-@@ -500,18 +477,6 @@ asmlinkage void do_notify_resume(struct
- {
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING) {
--#ifdef CONFIG_BINFMT_ELF32
-- if (likely((current->thread.mflags & MF_ABI_MASK) == MF_O32)) {
-- do_signal32(oldset, regs);
-- return;
-- }
--#endif
--#ifdef CONFIG_BINFMT_IRIX
-- if (unlikely(current->personality != PER_LINUX)) {
-- do_irix_signal(oldset, regs);
-- return;
-- }
--#endif
-- do_signal(oldset, regs);
-+ current->thread.abi->do_signal(oldset, regs);
- }
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/signal32.c linux_HEAD/arch/mips/kernel/signal32.c
---- linux-2.6.12/arch/mips/kernel/signal32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/signal32.c 2005-07-01 12:09:18.000000000 +0200
-@@ -7,6 +7,7 @@
- * Copyright (C) 1994 - 2000 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-+#include <linux/cache.h>
- #include <linux/sched.h>
- #include <linux/mm.h>
- #include <linux/smp.h>
-@@ -21,6 +22,7 @@
- #include <linux/suspend.h>
- #include <linux/compiler.h>
-
-+#include <asm/abi.h>
- #include <asm/asm.h>
- #include <linux/bitops.h>
- #include <asm/cacheflush.h>
-@@ -29,6 +31,7 @@
- #include <asm/ucontext.h>
- #include <asm/system.h>
- #include <asm/fpu.h>
-+#include <asm/war.h>
-
- #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-@@ -76,8 +79,10 @@ typedef struct compat_siginfo {
-
- /* POSIX.1b timers */
- struct {
-- unsigned int _timer1;
-- unsigned int _timer2;
-+ timer_t _tid; /* timer id */
-+ int _overrun; /* overrun count */
-+ compat_sigval_t _sigval;/* same as below */
-+ int _sys_private; /* not to be passed to user */
- } _timer;
-
- /* POSIX.1b signals */
-@@ -259,11 +264,12 @@ asmlinkage int sys32_sigaction(int sig,
-
- if (act) {
- old_sigset_t mask;
-+ s32 handler;
-
- if (!access_ok(VERIFY_READ, act, sizeof(*act)))
- return -EFAULT;
-- err |= __get_user((u32)(u64)new_ka.sa.sa_handler,
-- &act->sa_handler);
-+ err |= __get_user(handler, &act->sa_handler);
-+ new_ka.sa.sa_handler = (void*)(s64)handler;
- err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
- err |= __get_user(mask, &act->sa_mask.sig[0]);
- if (err)
-@@ -331,8 +337,9 @@ asmlinkage int sys32_sigaltstack(nabi_no
-
- static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc)
- {
-+ u32 used_math;
- int err = 0;
-- __u32 used_math;
-+ s32 treg;
-
- /* Always make any pending restarted system calls return -EINTR */
- current_thread_info()->restart_block.fn = do_no_restart_syscall;
-@@ -340,6 +347,15 @@ static int restore_sigcontext32(struct p
- err |= __get_user(regs->cp0_epc, &sc->sc_pc);
- err |= __get_user(regs->hi, &sc->sc_mdhi);
- err |= __get_user(regs->lo, &sc->sc_mdlo);
-+ if (cpu_has_dsp) {
-+ err |= __get_user(treg, &sc->sc_hi1); mthi1(treg);
-+ err |= __get_user(treg, &sc->sc_lo1); mtlo1(treg);
-+ err |= __get_user(treg, &sc->sc_hi2); mthi2(treg);
-+ err |= __get_user(treg, &sc->sc_lo2); mtlo2(treg);
-+ err |= __get_user(treg, &sc->sc_hi3); mthi3(treg);
-+ err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
-+ err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
-+ }
-
- #define restore_gp_reg(i) do { \
- err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
-@@ -378,16 +394,30 @@ static int restore_sigcontext32(struct p
-
- struct sigframe {
- u32 sf_ass[4]; /* argument save space for o32 */
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 sf_pad[2];
-+#else
- u32 sf_code[2]; /* signal trampoline */
-+#endif
- struct sigcontext32 sf_sc;
- sigset_t sf_mask;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */
-+#endif
- };
-
- struct rt_sigframe32 {
- u32 rs_ass[4]; /* argument save space for o32 */
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_pad[2];
-+#else
- u32 rs_code[2]; /* signal trampoline */
-+#endif
- compat_siginfo_t rs_info;
- struct ucontext32 rs_uc;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */
-+#endif
- };
-
- int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from)
-@@ -411,6 +441,11 @@ int copy_siginfo_to_user32(compat_siginf
- err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE);
- else {
- switch (from->si_code >> 16) {
-+ case __SI_TIMER >> 16:
-+ err |= __put_user(from->si_tid, &to->si_tid);
-+ err |= __put_user(from->si_overrun, &to->si_overrun);
-+ err |= __put_user(from->si_int, &to->si_int);
-+ break;
- case __SI_CHLD >> 16:
- err |= __put_user(from->si_utime, &to->si_utime);
- err |= __put_user(from->si_stime, &to->si_stime);
-@@ -480,6 +515,7 @@ __attribute_used__ noinline static void
- _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
- {
- struct rt_sigframe32 *frame;
-+ mm_segment_t old_fs;
- sigset_t set;
- stack_t st;
- s32 sp;
-@@ -510,7 +546,10 @@ _sys32_rt_sigreturn(nabi_no_regargs stru
-
- /* It is more difficult to avoid calling this function than to
- call it and ignore errors. */
-+ old_fs = get_fs();
-+ set_fs (KERNEL_DS);
- do_sigaltstack(&st, NULL, regs.regs[29]);
-+ set_fs (old_fs);
-
- /*
- * Don't let your children do this ...
-@@ -550,8 +589,15 @@ static inline int setup_sigcontext32(str
-
- err |= __put_user(regs->hi, &sc->sc_mdhi);
- err |= __put_user(regs->lo, &sc->sc_mdlo);
-- err |= __put_user(regs->cp0_cause, &sc->sc_cause);
-- err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr);
-+ if (cpu_has_dsp) {
-+ err |= __put_user(rddsp(DSP_MASK), &sc->sc_hi1);
-+ err |= __put_user(mfhi1(), &sc->sc_hi1);
-+ err |= __put_user(mflo1(), &sc->sc_lo1);
-+ err |= __put_user(mfhi2(), &sc->sc_hi2);
-+ err |= __put_user(mflo2(), &sc->sc_lo2);
-+ err |= __put_user(mfhi3(), &sc->sc_hi3);
-+ err |= __put_user(mflo3(), &sc->sc_lo3);
-+ }
-
- err |= __put_user(!!used_math(), &sc->sc_used_math);
-
-@@ -601,7 +647,7 @@ static inline void *get_sigframe(struct
- return (void *)((sp - frame_size) & ALMASK);
- }
-
--static inline void setup_frame(struct k_sigaction * ka, struct pt_regs *regs,
-+void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
- int signr, sigset_t *set)
- {
- struct sigframe *frame;
-@@ -654,9 +700,7 @@ give_sigsegv:
- force_sigsegv(signr, current);
- }
-
--static inline void setup_rt_frame(struct k_sigaction * ka,
-- struct pt_regs *regs, int signr,
-- sigset_t *set, siginfo_t *info)
-+void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info)
- {
- struct rt_sigframe32 *frame;
- int err = 0;
-@@ -747,9 +791,9 @@ static inline void handle_signal(unsigne
- regs->regs[0] = 0; /* Don't deal with this again. */
-
- if (ka->sa.sa_flags & SA_SIGINFO)
-- setup_rt_frame(ka, regs, sig, oldset, info);
-+ current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info);
- else
-- setup_frame(ka, regs, sig, oldset);
-+ current->thread.abi->setup_frame(ka, regs, sig, oldset);
-
- if (!(ka->sa.sa_flags & SA_NODEFER)) {
- spin_lock_irq(¤t->sighand->siglock);
-@@ -820,12 +864,13 @@ asmlinkage int sys32_rt_sigaction(int si
- goto out;
-
- if (act) {
-+ s32 handler;
- int err = 0;
-
- if (!access_ok(VERIFY_READ, act, sizeof(*act)))
- return -EFAULT;
-- err |= __get_user((u32)(u64)new_sa.sa.sa_handler,
-- &act->sa_handler);
-+ err |= __get_user(handler, &act->sa_handler);
-+ new_sa.sa.sa_handler = (void*)(s64)handler;
- err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags);
- err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask);
- if (err)
-@@ -903,3 +948,30 @@ asmlinkage int sys32_rt_sigqueueinfo(int
- set_fs (old_fs);
- return ret;
- }
-+
-+asmlinkage long
-+sys32_waitid(int which, compat_pid_t pid,
-+ compat_siginfo_t __user *uinfo, int options,
-+ struct compat_rusage __user *uru)
-+{
-+ siginfo_t info;
-+ struct rusage ru;
-+ long ret;
-+ mm_segment_t old_fs = get_fs();
-+
-+ info.si_signo = 0;
-+ set_fs (KERNEL_DS);
-+ ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options,
-+ uru ? (struct rusage __user *) &ru : NULL);
-+ set_fs (old_fs);
-+
-+ if (ret < 0 || info.si_signo == 0)
-+ return ret;
-+
-+ if (uru && (ret = put_compat_rusage(&ru, uru)))
-+ return ret;
-+
-+ BUG_ON(info.si_code & __SI_MASK);
-+ info.si_code |= __SI_CHLD;
-+ return copy_siginfo_to_user32(uinfo, &info);
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/signal_n32.c linux_HEAD/arch/mips/kernel/signal_n32.c
---- linux-2.6.12/arch/mips/kernel/signal_n32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/signal_n32.c 2005-07-01 12:09:18.000000000 +0200
-@@ -15,6 +15,8 @@
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-+#include <linux/cache.h>
-+#include <linux/sched.h>
- #include <linux/sched.h>
- #include <linux/mm.h>
- #include <linux/smp.h>
-@@ -36,6 +38,7 @@
- #include <asm/system.h>
- #include <asm/fpu.h>
- #include <asm/cpu-features.h>
-+#include <asm/war.h>
-
- #include "signal-common.h"
-
-@@ -62,17 +65,18 @@ struct ucontextn32 {
- sigset_t uc_sigmask; /* mask last for extensibility */
- };
-
--#if PLAT_TRAMPOLINE_STUFF_LINE
--#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE)))
--#else
--#define __tramp
--#endif
--
- struct rt_sigframe_n32 {
- u32 rs_ass[4]; /* argument save space for o32 */
-- u32 rs_code[2] __tramp; /* signal trampoline */
-- struct siginfo rs_info __tramp;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_pad[2];
-+#else
-+ u32 rs_code[2]; /* signal trampoline */
-+#endif
-+ struct siginfo rs_info;
- struct ucontextn32 rs_uc;
-+#if ICACHE_REFILLS_WORKAROUND_WAR
-+ u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */
-+#endif
- };
-
- save_static_function(sysn32_rt_sigreturn);
-@@ -137,17 +141,7 @@ void setup_rt_frame_n32(struct k_sigacti
- if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
- goto give_sigsegv;
-
-- /*
-- * Set up the return code ...
-- *
-- * li v0, __NR_rt_sigreturn
-- * syscall
-- */
-- if (PLAT_TRAMPOLINE_STUFF_LINE)
-- __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE);
-- err |= __put_user(0x24020000 + __NR_N32_rt_sigreturn, frame->rs_code + 0);
-- err |= __put_user(0x0000000c , frame->rs_code + 1);
-- flush_cache_sigtramp((unsigned long) frame->rs_code);
-+ install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn);
-
- /* Create siginfo. */
- err |= copy_siginfo_to_user(&frame->rs_info, info);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/smp.c linux_HEAD/arch/mips/kernel/smp.c
---- linux-2.6.12/arch/mips/kernel/smp.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/smp.c 2005-04-13 19:06:33.000000000 +0200
-@@ -121,7 +121,19 @@ struct call_data_struct *call_data;
- * or are or have executed.
- *
- * You must not call this function with disabled interrupts or from a
-- * hardware interrupt handler or from a bottom half handler.
-+ * hardware interrupt handler or from a bottom half handler:
-+ *
-+ * CPU A CPU B
-+ * Disable interrupts
-+ * smp_call_function()
-+ * Take call_lock
-+ * Send IPIs
-+ * Wait for all cpus to acknowledge IPI
-+ * CPU A has not responded, spin waiting
-+ * for cpu A to respond, holding call_lock
-+ * smp_call_function()
-+ * Spin waiting for call_lock
-+ * Deadlock Deadlock
- */
- int smp_call_function (void (*func) (void *info), void *info, int retry,
- int wait)
-@@ -214,7 +226,6 @@ void __init smp_cpus_done(unsigned int m
- /* called from main before smp_init() */
- void __init smp_prepare_cpus(unsigned int max_cpus)
- {
-- cpu_data[0].udelay_val = loops_per_jiffy;
- init_new_context(current, &init_mm);
- current_thread_info()->cpu = 0;
- smp_tune_scheduling();
-@@ -236,23 +247,28 @@ void __devinit smp_prepare_boot_cpu(void
- }
-
- /*
-- * Startup the CPU with this logical number
-+ * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
-+ * and keep control until "cpu_online(cpu)" is set. Note: cpu is
-+ * physical, not logical.
- */
--static int __init do_boot_cpu(int cpu)
-+int __devinit __cpu_up(unsigned int cpu)
- {
- struct task_struct *idle;
-
- /*
-+ * Processor goes to start_secondary(), sets online flag
- * The following code is purely to make sure
- * Linux can schedule processes on this slave.
- */
- idle = fork_idle(cpu);
- if (IS_ERR(idle))
-- panic("failed fork for CPU %d\n", cpu);
-+ panic(KERN_ERR "Fork failed for CPU %d\n", cpu);
-
- prom_boot_secondary(cpu, idle);
-
-- /* XXXKW timeout */
-+ /*
-+ * Trust is futile. We should really have timeouts ...
-+ */
- while (!cpu_isset(cpu, cpu_callin_map))
- udelay(100);
-
-@@ -261,23 +277,6 @@ static int __init do_boot_cpu(int cpu)
- return 0;
- }
-
--/*
-- * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
-- * and keep control until "cpu_online(cpu)" is set. Note: cpu is
-- * physical, not logical.
-- */
--int __devinit __cpu_up(unsigned int cpu)
--{
-- int ret;
--
-- /* Processor goes to start_secondary(), sets online flag */
-- ret = do_boot_cpu(cpu);
-- if (ret < 0)
-- return ret;
--
-- return 0;
--}
--
- /* Not really SMP stuff ... */
- int setup_profiling_timer(unsigned int multiplier)
- {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/syscall.c linux_HEAD/arch/mips/kernel/syscall.c
---- linux-2.6.12/arch/mips/kernel/syscall.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/syscall.c 2005-07-01 12:09:18.000000000 +0200
-@@ -7,6 +7,7 @@
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-+#include <linux/config.h>
- #include <linux/a.out.h>
- #include <linux/errno.h>
- #include <linux/linkage.h>
-@@ -26,6 +27,7 @@
- #include <linux/msg.h>
- #include <linux/shm.h>
- #include <linux/compiler.h>
-+#include <linux/module.h>
-
- #include <asm/branch.h>
- #include <asm/cachectl.h>
-@@ -56,6 +58,8 @@ out:
-
- unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
-
-+EXPORT_SYMBOL(shm_align_mask);
-+
- #define COLOUR_ALIGN(addr,pgoff) \
- ((((addr) + shm_align_mask) & ~shm_align_mask) + \
- (((pgoff) << PAGE_SHIFT) & shm_align_mask))
-@@ -173,14 +177,28 @@ _sys_clone(nabi_no_regargs struct pt_reg
- {
- unsigned long clone_flags;
- unsigned long newsp;
-- int *parent_tidptr, *child_tidptr;
-+ int __user *parent_tidptr, *child_tidptr;
-
- clone_flags = regs.regs[4];
- newsp = regs.regs[5];
- if (!newsp)
- newsp = regs.regs[29];
-- parent_tidptr = (int *) regs.regs[6];
-- child_tidptr = (int *) regs.regs[7];
-+ parent_tidptr = (int __user *) regs.regs[6];
-+#ifdef CONFIG_MIPS32
-+ /* We need to fetch the fifth argument off the stack. */
-+ child_tidptr = NULL;
-+ if (clone_flags & (CLONE_CHILD_SETTID | CLONE_CHILD_CLEARTID)) {
-+ int __user *__user *usp = (int __user *__user *) regs.regs[29];
-+ if (regs.regs[2] == __NR_syscall) {
-+ if (get_user (child_tidptr, &usp[5]))
-+ return -EFAULT;
-+ }
-+ else if (get_user (child_tidptr, &usp[4]))
-+ return -EFAULT;
-+ }
-+#else
-+ child_tidptr = (int __user *) regs.regs[8];
-+#endif
- return do_fork(clone_flags, newsp, ®s, 0,
- parent_tidptr, child_tidptr);
- }
-@@ -242,6 +260,16 @@ asmlinkage int sys_olduname(struct oldol
- return error;
- }
-
-+void sys_set_thread_area(unsigned long addr)
-+{
-+ struct thread_info *ti = current->thread_info;
-+
-+ ti->tp_value = addr;
-+
-+ /* If some future MIPS implementation has this register in hardware,
-+ * we will need to update it here (and in context switches). */
-+}
-+
- asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
- {
- int tmp, len;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/sysirix.c linux_HEAD/arch/mips/kernel/sysirix.c
---- linux-2.6.12/arch/mips/kernel/sysirix.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/sysirix.c 2005-03-17 22:20:26.000000000 +0100
-@@ -73,32 +73,30 @@ asmlinkage int irix_sysmp(struct pt_regs
- }
-
- /* The prctl commands. */
--#define PR_MAXPROCS 1 /* Tasks/user. */
--#define PR_ISBLOCKED 2 /* If blocked, return 1. */
--#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */
--#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */
--#define PR_MAXPPROCS 5 /* Num parallel tasks. */
--#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */
--#define PR_SETEXITSIG 8 /* When task exit's, set signal. */
--#define PR_RESIDENT 9 /* Make task unswappable. */
--#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */
--#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */
--#define PR_TERMCHILD 12 /* When parent sleeps with fishes, kill child. */
--#define PR_GETSHMASK 13 /* Get the sproc() share mask. */
--#define PR_GETNSHARE 14 /* Number of share group members. */
--#define PR_COREPID 15 /* Add task pid to name when it core. */
--#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */
--#define PR_PTHREADEXIT 17 /* Kill a pthread without prejudice. */
-+#define PR_MAXPROCS 1 /* Tasks/user. */
-+#define PR_ISBLOCKED 2 /* If blocked, return 1. */
-+#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */
-+#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */
-+#define PR_MAXPPROCS 5 /* Num parallel tasks. */
-+#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */
-+#define PR_SETEXITSIG 8 /* When task exit's, set signal. */
-+#define PR_RESIDENT 9 /* Make task unswappable. */
-+#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */
-+#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */
-+#define PR_TERMCHILD 12 /* Kill child if the parent dies. */
-+#define PR_GETSHMASK 13 /* Get the sproc() share mask. */
-+#define PR_GETNSHARE 14 /* Number of share group members. */
-+#define PR_COREPID 15 /* Add task pid to name when it core. */
-+#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */
-+#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */
-
--asmlinkage int irix_prctl(struct pt_regs *regs)
-+asmlinkage int irix_prctl(unsigned option, ...)
- {
-- unsigned long cmd;
-- int error = 0, base = 0;
-+ va_list args;
-+ int error = 0;
-
-- if (regs->regs[2] == 1000)
-- base = 1;
-- cmd = regs->regs[base + 4];
-- switch (cmd) {
-+ va_start(args, option);
-+ switch (option) {
- case PR_MAXPROCS:
- printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n",
- current->comm, current->pid);
-@@ -111,7 +109,7 @@ asmlinkage int irix_prctl(struct pt_regs
- printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n",
- current->comm, current->pid);
- read_lock(&tasklist_lock);
-- task = find_task_by_pid(regs->regs[base + 5]);
-+ task = find_task_by_pid(va_arg(args, pid_t));
- error = -ESRCH;
- if (error)
- error = (task->run_list.next != NULL);
-@@ -121,7 +119,7 @@ asmlinkage int irix_prctl(struct pt_regs
- }
-
- case PR_SETSTACKSIZE: {
-- long value = regs->regs[base + 5];
-+ long value = va_arg(args, long);
-
- printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n",
- current->comm, current->pid, (unsigned long) value);
-@@ -222,24 +220,20 @@ asmlinkage int irix_prctl(struct pt_regs
- error = -EINVAL;
- break;
-
-- case PR_PTHREADEXIT:
-- printk("irix_prctl[%s:%d]: Wants PR_PTHREADEXIT\n",
-- current->comm, current->pid);
-- do_exit(regs->regs[base + 5]);
--
- default:
- printk("irix_prctl[%s:%d]: Non-existant opcode %d\n",
-- current->comm, current->pid, (int)cmd);
-+ current->comm, current->pid, option);
- error = -EINVAL;
- break;
- }
-+ va_end(args);
-
- return error;
- }
-
- #undef DEBUG_PROCGRPS
-
--extern unsigned long irix_mapelf(int fd, struct elf_phdr *user_phdrp, int cnt);
-+extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt);
- extern int getrusage(struct task_struct *p, int who, struct rusage __user *ru);
- extern char *prom_getenv(char *name);
- extern long prom_setenv(char *name, char *value);
-@@ -276,23 +270,19 @@ asmlinkage int irix_syssgi(struct pt_reg
- cmd = regs->regs[base + 4];
- switch(cmd) {
- case SGI_SYSID: {
-- char *buf = (char *) regs->regs[base + 5];
-+ char __user *buf = (char __user *) regs->regs[base + 5];
-
- /* XXX Use ethernet addr.... */
-- retval = clear_user(buf, 64);
-+ retval = clear_user(buf, 64) ? -EFAULT : 0;
- break;
- }
- #if 0
- case SGI_RDNAME: {
- int pid = (int) regs->regs[base + 5];
-- char *buf = (char *) regs->regs[base + 6];
-+ char __user *buf = (char *) regs->regs[base + 6];
- struct task_struct *p;
- char tcomm[sizeof(current->comm)];
-
-- if (!access_ok(VERIFY_WRITE, buf, sizeof(tcomm))) {
-- retval = -EFAULT;
-- break;
-- }
- read_lock(&tasklist_lock);
- p = find_task_by_pid(pid);
- if (!p) {
-@@ -304,34 +294,28 @@ asmlinkage int irix_syssgi(struct pt_reg
- read_unlock(&tasklist_lock);
-
- /* XXX Need to check sizes. */
-- copy_to_user(buf, tcomm, sizeof(tcomm));
-- retval = 0;
-+ retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0;
- break;
- }
-
- case SGI_GETNVRAM: {
-- char *name = (char *) regs->regs[base+5];
-- char *buf = (char *) regs->regs[base+6];
-+ char __user *name = (char __user *) regs->regs[base+5];
-+ char __user *buf = (char __user *) regs->regs[base+6];
- char *value;
- return -EINVAL; /* til I fix it */
-- if (!access_ok(VERIFY_WRITE, buf, 128)) {
-- retval = -EFAULT;
-- break;
-- }
- value = prom_getenv(name); /* PROM lock? */
- if (!value) {
- retval = -EINVAL;
- break;
- }
- /* Do I strlen() for the length? */
-- copy_to_user(buf, value, 128);
-- retval = 0;
-+ retval = copy_to_user(buf, value, 128) ? -EFAULT : 0;
- break;
- }
-
- case SGI_SETNVRAM: {
-- char *name = (char *) regs->regs[base+5];
-- char *value = (char *) regs->regs[base+6];
-+ char __user *name = (char __user *) regs->regs[base+5];
-+ char __user *value = (char __user *) regs->regs[base+6];
- return -EINVAL; /* til I fix it */
- retval = prom_setenv(name, value);
- /* XXX make sure retval conforms to syssgi(2) */
-@@ -407,16 +391,16 @@ asmlinkage int irix_syssgi(struct pt_reg
-
- case SGI_SETGROUPS:
- retval = sys_setgroups((int) regs->regs[base + 5],
-- (gid_t *) regs->regs[base + 6]);
-+ (gid_t __user *) regs->regs[base + 6]);
- break;
-
- case SGI_GETGROUPS:
- retval = sys_getgroups((int) regs->regs[base + 5],
-- (gid_t *) regs->regs[base + 6]);
-+ (gid_t __user *) regs->regs[base + 6]);
- break;
-
- case SGI_RUSAGE: {
-- struct rusage *ru = (struct rusage *) regs->regs[base + 6];
-+ struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6];
-
- switch((int) regs->regs[base + 5]) {
- case 0:
-@@ -453,7 +437,7 @@ asmlinkage int irix_syssgi(struct pt_reg
-
- case SGI_ELFMAP:
- retval = irix_mapelf((int) regs->regs[base + 5],
-- (struct elf_phdr *) regs->regs[base + 6],
-+ (struct elf_phdr __user *) regs->regs[base + 6],
- (int) regs->regs[base + 7]);
- break;
-
-@@ -468,24 +452,24 @@ asmlinkage int irix_syssgi(struct pt_reg
-
- case SGI_PHYSP: {
- unsigned long addr = regs->regs[base + 5];
-- int *pageno = (int *) (regs->regs[base + 6]);
-+ int __user *pageno = (int __user *) (regs->regs[base + 6]);
- struct mm_struct *mm = current->mm;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
-
-- if (!access_ok(VERIFY_WRITE, pageno, sizeof(int)))
-- return -EFAULT;
--
- down_read(&mm->mmap_sem);
- pgdp = pgd_offset(mm, addr);
-- pmdp = pmd_offset(pgdp, addr);
-+ pudp = pud_offset(pgdp, addr);
-+ pmdp = pmd_offset(pudp, addr);
- ptep = pte_offset(pmdp, addr);
- retval = -EINVAL;
- if (ptep) {
- pte_t pte = *ptep;
-
- if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) {
-+ /* b0rked on 64-bit */
- retval = put_user((pte_val(pte) & PAGE_MASK) >>
- PAGE_SHIFT, pageno);
- }
-@@ -496,7 +480,7 @@ asmlinkage int irix_syssgi(struct pt_reg
-
- case SGI_INVENT: {
- int arg1 = (int) regs->regs [base + 5];
-- void *buffer = (void *) regs->regs [base + 6];
-+ void __user *buffer = (void __user *) regs->regs [base + 6];
- int count = (int) regs->regs [base + 7];
-
- switch (arg1) {
-@@ -700,8 +684,8 @@ asmlinkage int irix_pause(void)
- }
-
- /* XXX need more than this... */
--asmlinkage int irix_mount(char *dev_name, char *dir_name, unsigned long flags,
-- char *type, void *data, int datalen)
-+asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name,
-+ unsigned long flags, char __user *type, void __user *data, int datalen)
- {
- printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n",
- current->comm, current->pid,
-@@ -716,8 +700,8 @@ struct irix_statfs {
- char f_fname[6], f_fpack[6];
- };
-
--asmlinkage int irix_statfs(const char *path, struct irix_statfs *buf,
-- int len, int fs_type)
-+asmlinkage int irix_statfs(const char __user *path,
-+ struct irix_statfs __user *buf, int len, int fs_type)
- {
- struct nameidata nd;
- struct kstatfs kbuf;
-@@ -732,6 +716,7 @@ asmlinkage int irix_statfs(const char *p
- error = -EFAULT;
- goto out;
- }
-+
- error = user_path_walk(path, &nd);
- if (error)
- goto out;
-@@ -740,18 +725,17 @@ asmlinkage int irix_statfs(const char *p
- if (error)
- goto dput_and_out;
-
-- __put_user(kbuf.f_type, &buf->f_type);
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-+ error = __put_user(kbuf.f_type, &buf->f_type);
-+ error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
- for (i = 0; i < 6; i++) {
-- __put_user(0, &buf->f_fname[i]);
-- __put_user(0, &buf->f_fpack[i]);
-+ error |= __put_user(0, &buf->f_fname[i]);
-+ error |= __put_user(0, &buf->f_fpack[i]);
- }
-- error = 0;
-
- dput_and_out:
- path_release(&nd);
-@@ -759,7 +743,7 @@ out:
- return error;
- }
-
--asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs *buf)
-+asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf)
- {
- struct kstatfs kbuf;
- struct file *file;
-@@ -769,6 +753,7 @@ asmlinkage int irix_fstatfs(unsigned int
- error = -EFAULT;
- goto out;
- }
-+
- if (!(file = fget(fd))) {
- error = -EBADF;
- goto out;
-@@ -778,16 +763,17 @@ asmlinkage int irix_fstatfs(unsigned int
- if (error)
- goto out_f;
-
-- __put_user(kbuf.f_type, &buf->f_type);
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-- for(i = 0; i < 6; i++) {
-- __put_user(0, &buf->f_fname[i]);
-- __put_user(0, &buf->f_fpack[i]);
-+ error = __put_user(kbuf.f_type, &buf->f_type);
-+ error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
-+
-+ for (i = 0; i < 6; i++) {
-+ error |= __put_user(0, &buf->f_fname[i]);
-+ error |= __put_user(0, &buf->f_fpack[i]);
- }
-
- out_f:
-@@ -814,14 +800,15 @@ asmlinkage int irix_setpgrp(int flags)
- return error;
- }
-
--asmlinkage int irix_times(struct tms * tbuf)
-+asmlinkage int irix_times(struct tms __user *tbuf)
- {
- int err = 0;
-
- if (tbuf) {
- if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf))
- return -EFAULT;
-- err |= __put_user(current->utime, &tbuf->tms_utime);
-+
-+ err = __put_user(current->utime, &tbuf->tms_utime);
- err |= __put_user(current->stime, &tbuf->tms_stime);
- err |= __put_user(current->signal->cutime, &tbuf->tms_cutime);
- err |= __put_user(current->signal->cstime, &tbuf->tms_cstime);
-@@ -837,13 +824,13 @@ asmlinkage int irix_exec(struct pt_regs
-
- if(regs->regs[2] == 1000)
- base = 1;
-- filename = getname((char *) (long)regs->regs[base + 4]);
-+ filename = getname((char __user *) (long)regs->regs[base + 4]);
- error = PTR_ERR(filename);
- if (IS_ERR(filename))
- return error;
-
-- error = do_execve(filename, (char **) (long)regs->regs[base + 5],
-- (char **) 0, regs);
-+ error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5],
-+ NULL, regs);
- putname(filename);
-
- return error;
-@@ -856,12 +843,12 @@ asmlinkage int irix_exece(struct pt_regs
-
- if (regs->regs[2] == 1000)
- base = 1;
-- filename = getname((char *) (long)regs->regs[base + 4]);
-+ filename = getname((char __user *) (long)regs->regs[base + 4]);
- error = PTR_ERR(filename);
- if (IS_ERR(filename))
- return error;
-- error = do_execve(filename, (char **) (long)regs->regs[base + 5],
-- (char **) (long)regs->regs[base + 6], regs);
-+ error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5],
-+ (char __user * __user *) (long)regs->regs[base + 6], regs);
- putname(filename);
-
- return error;
-@@ -917,22 +904,17 @@ asmlinkage int irix_socket(int family, i
- return sys_socket(family, type, protocol);
- }
-
--asmlinkage int irix_getdomainname(char *name, int len)
-+asmlinkage int irix_getdomainname(char __user *name, int len)
- {
-- int error;
--
-- if (!access_ok(VERIFY_WRITE, name, len))
-- return -EFAULT;
-+ int err;
-
- down_read(&uts_sem);
- if (len > __NEW_UTS_LEN)
- len = __NEW_UTS_LEN;
-- error = 0;
-- if (copy_to_user(name, system_utsname.domainname, len))
-- error = -EFAULT;
-+ err = copy_to_user(name, system_utsname.domainname, len) ? -EFAULT : 0;
- up_read(&uts_sem);
-
-- return error;
-+ return err;
- }
-
- asmlinkage unsigned long irix_getpagesize(void)
-@@ -948,12 +930,13 @@ asmlinkage int irix_msgsys(int opcode, u
- case 0:
- return sys_msgget((key_t) arg0, (int) arg1);
- case 1:
-- return sys_msgctl((int) arg0, (int) arg1, (struct msqid_ds *)arg2);
-+ return sys_msgctl((int) arg0, (int) arg1,
-+ (struct msqid_ds __user *)arg2);
- case 2:
-- return sys_msgrcv((int) arg0, (struct msgbuf *) arg1,
-+ return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1,
- (size_t) arg2, (long) arg3, (int) arg4);
- case 3:
-- return sys_msgsnd((int) arg0, (struct msgbuf *) arg1,
-+ return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1,
- (size_t) arg2, (int) arg3);
- default:
- return -EINVAL;
-@@ -965,12 +948,13 @@ asmlinkage int irix_shmsys(int opcode, u
- {
- switch (opcode) {
- case 0:
-- return do_shmat((int) arg0, (char *)arg1, (int) arg2,
-+ return do_shmat((int) arg0, (char __user *) arg1, (int) arg2,
- (unsigned long *) arg3);
- case 1:
-- return sys_shmctl((int)arg0, (int)arg1, (struct shmid_ds *)arg2);
-+ return sys_shmctl((int)arg0, (int)arg1,
-+ (struct shmid_ds __user *)arg2);
- case 2:
-- return sys_shmdt((char *)arg0);
-+ return sys_shmdt((char __user *)arg0);
- case 3:
- return sys_shmget((key_t) arg0, (int) arg1, (int) arg2);
- default:
-@@ -988,7 +972,7 @@ asmlinkage int irix_semsys(int opcode, u
- case 1:
- return sys_semget((key_t) arg0, (int) arg1, (int) arg2);
- case 2:
-- return sys_semop((int) arg0, (struct sembuf *)arg1,
-+ return sys_semop((int) arg0, (struct sembuf __user *)arg1,
- (unsigned int) arg2);
- default:
- return -EINVAL;
-@@ -1006,15 +990,16 @@ static inline loff_t llseek(struct file
- lock_kernel();
- retval = fn(file, offset, origin);
- unlock_kernel();
-+
- return retval;
- }
-
- asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow,
- int origin)
- {
-- int retval;
- struct file * file;
- loff_t offset;
-+ int retval;
-
- retval = -EBADF;
- file = fget(fd);
-@@ -1040,12 +1025,12 @@ asmlinkage int irix_sginap(int ticks)
- return 0;
- }
-
--asmlinkage int irix_sgikopt(char *istring, char *ostring, int len)
-+asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len)
- {
- return -EINVAL;
- }
-
--asmlinkage int irix_gettimeofday(struct timeval *tv)
-+asmlinkage int irix_gettimeofday(struct timeval __user *tv)
- {
- time_t sec;
- long nsec, seq;
-@@ -1086,7 +1071,7 @@ asmlinkage unsigned long irix_mmap32(uns
-
- if (max_size > file->f_dentry->d_inode->i_size) {
- old_pos = sys_lseek (fd, max_size - 1, 0);
-- sys_write (fd, "", 1);
-+ sys_write (fd, (void __user *) "", 1);
- sys_lseek (fd, old_pos, 0);
- }
- }
-@@ -1111,7 +1096,7 @@ asmlinkage int irix_madvise(unsigned lon
- return -EINVAL;
- }
-
--asmlinkage int irix_pagelock(char *addr, int len, int op)
-+asmlinkage int irix_pagelock(char __user *addr, int len, int op)
- {
- printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n",
- current->comm, current->pid, addr, len, op);
-@@ -1151,7 +1136,7 @@ asmlinkage int irix_BSDsetpgrp(int pid,
- return error;
- }
-
--asmlinkage int irix_systeminfo(int cmd, char *buf, int cnt)
-+asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt)
- {
- printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n",
- current->comm, current->pid, cmd, buf, cnt);
-@@ -1167,14 +1152,14 @@ struct iuname {
- char _unused3[257], _unused4[257], _unused5[257];
- };
-
--asmlinkage int irix_uname(struct iuname *buf)
-+asmlinkage int irix_uname(struct iuname __user *buf)
- {
- down_read(&uts_sem);
-- if (copy_to_user(system_utsname.sysname, buf->sysname, 65)
-- || copy_to_user(system_utsname.nodename, buf->nodename, 65)
-- || copy_to_user(system_utsname.release, buf->release, 65)
-- || copy_to_user(system_utsname.version, buf->version, 65)
-- || copy_to_user(system_utsname.machine, buf->machine, 65)) {
-+ if (copy_from_user(system_utsname.sysname, buf->sysname, 65)
-+ || copy_from_user(system_utsname.nodename, buf->nodename, 65)
-+ || copy_from_user(system_utsname.release, buf->release, 65)
-+ || copy_from_user(system_utsname.version, buf->version, 65)
-+ || copy_from_user(system_utsname.machine, buf->machine, 65)) {
- return -EFAULT;
- }
- up_read(&uts_sem);
-@@ -1184,7 +1169,7 @@ asmlinkage int irix_uname(struct iuname
-
- #undef DEBUG_XSTAT
-
--static int irix_xstat32_xlate(struct kstat *stat, void *ubuf)
-+static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf)
- {
- struct xstat32 {
- u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid;
-@@ -1224,7 +1209,7 @@ static int irix_xstat32_xlate(struct kst
- return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0;
- }
-
--static int irix_xstat64_xlate(struct kstat *stat, void *ubuf)
-+static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf)
- {
- struct xstat64 {
- u32 st_dev; s32 st_pad1[3];
-@@ -1274,7 +1259,7 @@ static int irix_xstat64_xlate(struct kst
- return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0;
- }
-
--asmlinkage int irix_xstat(int version, char *filename, struct stat *statbuf)
-+asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf)
- {
- int retval;
- struct kstat stat;
-@@ -1300,7 +1285,7 @@ asmlinkage int irix_xstat(int version, c
- return retval;
- }
-
--asmlinkage int irix_lxstat(int version, char *filename, struct stat *statbuf)
-+asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf)
- {
- int error;
- struct kstat stat;
-@@ -1327,7 +1312,7 @@ asmlinkage int irix_lxstat(int version,
- return error;
- }
-
--asmlinkage int irix_fxstat(int version, int fd, struct stat *statbuf)
-+asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf)
- {
- int error;
- struct kstat stat;
-@@ -1353,7 +1338,7 @@ asmlinkage int irix_fxstat(int version,
- return error;
- }
-
--asmlinkage int irix_xmknod(int ver, char *filename, int mode, unsigned dev)
-+asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev)
- {
- int retval;
- printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n",
-@@ -1373,7 +1358,7 @@ asmlinkage int irix_xmknod(int ver, char
- return retval;
- }
-
--asmlinkage int irix_swapctl(int cmd, char *arg)
-+asmlinkage int irix_swapctl(int cmd, char __user *arg)
- {
- printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n",
- current->comm, current->pid, cmd, arg);
-@@ -1389,7 +1374,7 @@ struct irix_statvfs {
- char f_fstr[32]; u32 f_filler[16];
- };
-
--asmlinkage int irix_statvfs(char *fname, struct irix_statvfs *buf)
-+asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf)
- {
- struct nameidata nd;
- struct kstatfs kbuf;
-@@ -1397,10 +1382,9 @@ asmlinkage int irix_statvfs(char *fname,
-
- printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n",
- current->comm, current->pid, fname, buf);
-- if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) {
-- error = -EFAULT;
-- goto out;
-- }
-+ if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs)))
-+ return -EFAULT;
-+
- error = user_path_walk(fname, &nd);
- if (error)
- goto out;
-@@ -1408,27 +1392,25 @@ asmlinkage int irix_statvfs(char *fname,
- if (error)
- goto dput_and_out;
-
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-- __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
-+ error |= __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
- #ifdef __MIPSEB__
-- __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
- #else
-- __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
- #endif
- for (i = 0; i < 16; i++)
-- __put_user(0, &buf->f_basetype[i]);
-- __put_user(0, &buf->f_flag);
-- __put_user(kbuf.f_namelen, &buf->f_namemax);
-+ error |= __put_user(0, &buf->f_basetype[i]);
-+ error |= __put_user(0, &buf->f_flag);
-+ error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
- for (i = 0; i < 32; i++)
-- __put_user(0, &buf->f_fstr[i]);
--
-- error = 0;
-+ error |= __put_user(0, &buf->f_fstr[i]);
-
- dput_and_out:
- path_release(&nd);
-@@ -1436,7 +1418,7 @@ out:
- return error;
- }
-
--asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs *buf)
-+asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf)
- {
- struct kstatfs kbuf;
- struct file *file;
-@@ -1445,10 +1427,9 @@ asmlinkage int irix_fstatvfs(int fd, str
- printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n",
- current->comm, current->pid, fd, buf);
-
-- if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) {
-- error = -EFAULT;
-- goto out;
-- }
-+ if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs)))
-+ return -EFAULT;
-+
- if (!(file = fget(fd))) {
- error = -EBADF;
- goto out;
-@@ -1457,24 +1438,24 @@ asmlinkage int irix_fstatvfs(int fd, str
- if (error)
- goto out_f;
-
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-- __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
-+ error = __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
- #ifdef __MIPSEB__
-- __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
- #else
-- __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
- #endif
- for(i = 0; i < 16; i++)
-- __put_user(0, &buf->f_basetype[i]);
-- __put_user(0, &buf->f_flag);
-- __put_user(kbuf.f_namelen, &buf->f_namemax);
-- __clear_user(&buf->f_fstr, sizeof(buf->f_fstr));
-+ error |= __put_user(0, &buf->f_basetype[i]);
-+ error |= __put_user(0, &buf->f_flag);
-+ error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
-+ error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0;
-
- out_f:
- fput(file);
-@@ -1498,7 +1479,7 @@ asmlinkage int irix_sigqueue(int pid, in
- return -EINVAL;
- }
-
--asmlinkage int irix_truncate64(char *name, int pad, int size1, int size2)
-+asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2)
- {
- int retval;
-
-@@ -1531,6 +1512,7 @@ asmlinkage int irix_mmap64(struct pt_reg
- int len, prot, flags, fd, off1, off2, error, base = 0;
- unsigned long addr, pgoff, *sp;
- struct file *file = NULL;
-+ int err;
-
- if (regs->regs[2] == 1000)
- base = 1;
-@@ -1540,36 +1522,31 @@ asmlinkage int irix_mmap64(struct pt_reg
- prot = regs->regs[base + 6];
- if (!base) {
- flags = regs->regs[base + 7];
-- if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) {
-- error = -EFAULT;
-- goto out;
-- }
-+ if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long))))
-+ return -EFAULT;
- fd = sp[0];
-- __get_user(off1, &sp[1]);
-- __get_user(off2, &sp[2]);
-+ err = __get_user(off1, &sp[1]);
-+ err |= __get_user(off2, &sp[2]);
- } else {
-- if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) {
-- error = -EFAULT;
-- goto out;
-- }
-- __get_user(flags, &sp[0]);
-- __get_user(fd, &sp[1]);
-- __get_user(off1, &sp[2]);
-- __get_user(off2, &sp[3]);
-+ if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long))))
-+ return -EFAULT;
-+ err = __get_user(flags, &sp[0]);
-+ err |= __get_user(fd, &sp[1]);
-+ err |= __get_user(off1, &sp[2]);
-+ err |= __get_user(off2, &sp[3]);
- }
-
-- if (off1 & PAGE_MASK) {
-- error = -EOVERFLOW;
-- goto out;
-- }
-+ if (err)
-+ return err;
-+
-+ if (off1 & PAGE_MASK)
-+ return -EOVERFLOW;
-
- pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT);
-
- if (!(flags & MAP_ANONYMOUS)) {
-- if (!(file = fget(fd))) {
-- error = -EBADF;
-- goto out;
-- }
-+ if (!(file = fget(fd)))
-+ return -EBADF;
-
- /* Ok, bad taste hack follows, try to think in something else
- when reading this */
-@@ -1579,7 +1556,7 @@ asmlinkage int irix_mmap64(struct pt_reg
-
- if (max_size > file->f_dentry->d_inode->i_size) {
- old_pos = sys_lseek (fd, max_size - 1, 0);
-- sys_write (fd, "", 1);
-+ sys_write (fd, (void __user *) "", 1);
- sys_lseek (fd, old_pos, 0);
- }
- }
-@@ -1594,7 +1571,6 @@ asmlinkage int irix_mmap64(struct pt_reg
- if (file)
- fput(file);
-
--out:
- return error;
- }
-
-@@ -1606,7 +1582,7 @@ asmlinkage int irix_dmi(struct pt_regs *
- return -EINVAL;
- }
-
--asmlinkage int irix_pread(int fd, char *buf, int cnt, int off64,
-+asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64,
- int off1, int off2)
- {
- printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n",
-@@ -1615,7 +1591,7 @@ asmlinkage int irix_pread(int fd, char *
- return -EINVAL;
- }
-
--asmlinkage int irix_pwrite(int fd, char *buf, int cnt, int off64,
-+asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64,
- int off1, int off2)
- {
- printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n",
-@@ -1647,7 +1623,7 @@ struct irix_statvfs64 {
- u32 f_filler[16];
- };
-
--asmlinkage int irix_statvfs64(char *fname, struct irix_statvfs64 *buf)
-+asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf)
- {
- struct nameidata nd;
- struct kstatfs kbuf;
-@@ -1659,6 +1635,7 @@ asmlinkage int irix_statvfs64(char *fnam
- error = -EFAULT;
- goto out;
- }
-+
- error = user_path_walk(fname, &nd);
- if (error)
- goto out;
-@@ -1666,27 +1643,25 @@ asmlinkage int irix_statvfs64(char *fnam
- if (error)
- goto dput_and_out;
-
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-- __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
-+ error = __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
- #ifdef __MIPSEB__
-- __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
- #else
-- __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
- #endif
- for(i = 0; i < 16; i++)
-- __put_user(0, &buf->f_basetype[i]);
-- __put_user(0, &buf->f_flag);
-- __put_user(kbuf.f_namelen, &buf->f_namemax);
-+ error |= __put_user(0, &buf->f_basetype[i]);
-+ error |= __put_user(0, &buf->f_flag);
-+ error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
- for(i = 0; i < 32; i++)
-- __put_user(0, &buf->f_fstr[i]);
--
-- error = 0;
-+ error |= __put_user(0, &buf->f_fstr[i]);
-
- dput_and_out:
- path_release(&nd);
-@@ -1694,7 +1669,7 @@ out:
- return error;
- }
-
--asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs *buf)
-+asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf)
- {
- struct kstatfs kbuf;
- struct file *file;
-@@ -1715,24 +1690,24 @@ asmlinkage int irix_fstatvfs64(int fd, s
- if (error)
- goto out_f;
-
-- __put_user(kbuf.f_bsize, &buf->f_bsize);
-- __put_user(kbuf.f_frsize, &buf->f_frsize);
-- __put_user(kbuf.f_blocks, &buf->f_blocks);
-- __put_user(kbuf.f_bfree, &buf->f_bfree);
-- __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-- __put_user(kbuf.f_files, &buf->f_files);
-- __put_user(kbuf.f_ffree, &buf->f_ffree);
-- __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
-+ error = __put_user(kbuf.f_bsize, &buf->f_bsize);
-+ error |= __put_user(kbuf.f_frsize, &buf->f_frsize);
-+ error |= __put_user(kbuf.f_blocks, &buf->f_blocks);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bfree);
-+ error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */
-+ error |= __put_user(kbuf.f_files, &buf->f_files);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_ffree);
-+ error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */
- #ifdef __MIPSEB__
-- __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid);
- #else
-- __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
-+ error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid);
- #endif
- for(i = 0; i < 16; i++)
-- __put_user(0, &buf->f_basetype[i]);
-- __put_user(0, &buf->f_flag);
-- __put_user(kbuf.f_namelen, &buf->f_namemax);
-- __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i]));
-+ error |= __put_user(0, &buf->f_basetype[i]);
-+ error |= __put_user(0, &buf->f_flag);
-+ error |= __put_user(kbuf.f_namelen, &buf->f_namemax);
-+ error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0;
-
- out_f:
- fput(file);
-@@ -1740,9 +1715,9 @@ out:
- return error;
- }
-
--asmlinkage int irix_getmountid(char *fname, unsigned long *midbuf)
-+asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf)
- {
-- int err = 0;
-+ int err;
-
- printk("[%s:%d] irix_getmountid(%s, %p)\n",
- current->comm, current->pid, fname, midbuf);
-@@ -1755,7 +1730,7 @@ asmlinkage int irix_getmountid(char *fna
- * fsid of the filesystem to try and make the right decision, but
- * we don't have this so for now. XXX
- */
-- err |= __put_user(0, &midbuf[0]);
-+ err = __put_user(0, &midbuf[0]);
- err |= __put_user(0, &midbuf[1]);
- err |= __put_user(0, &midbuf[2]);
- err |= __put_user(0, &midbuf[3]);
-@@ -1782,8 +1757,8 @@ struct irix_dirent32 {
- };
-
- struct irix_dirent32_callback {
-- struct irix_dirent32 *current_dir;
-- struct irix_dirent32 *previous;
-+ struct irix_dirent32 __user *current_dir;
-+ struct irix_dirent32 __user *previous;
- int count;
- int error;
- };
-@@ -1791,13 +1766,13 @@ struct irix_dirent32_callback {
- #define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de)))
- #define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1))
-
--static int irix_filldir32(void *__buf, const char *name, int namlen,
-- loff_t offset, ino_t ino, unsigned int d_type)
-+static int irix_filldir32(void *__buf, const char *name,
-+ int namlen, loff_t offset, ino_t ino, unsigned int d_type)
- {
-- struct irix_dirent32 *dirent;
-- struct irix_dirent32_callback *buf =
-- (struct irix_dirent32_callback *)__buf;
-+ struct irix_dirent32 __user *dirent;
-+ struct irix_dirent32_callback *buf = __buf;
- unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1);
-+ int err = 0;
-
- #ifdef DEBUG_GETDENTS
- printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]",
-@@ -1808,25 +1783,26 @@ static int irix_filldir32(void *__buf, c
- return -EINVAL;
- dirent = buf->previous;
- if (dirent)
-- __put_user(offset, &dirent->d_off);
-+ err = __put_user(offset, &dirent->d_off);
- dirent = buf->current_dir;
-- buf->previous = dirent;
-- __put_user(ino, &dirent->d_ino);
-- __put_user(reclen, &dirent->d_reclen);
-- copy_to_user(dirent->d_name, name, namlen);
-- __put_user(0, &dirent->d_name[namlen]);
-- ((char *) dirent) += reclen;
-+ err |= __put_user(dirent, &buf->previous);
-+ err |= __put_user(ino, &dirent->d_ino);
-+ err |= __put_user(reclen, &dirent->d_reclen);
-+ err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0;
-+ err |= __put_user(0, &dirent->d_name[namlen]);
-+ dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen);
-+
- buf->current_dir = dirent;
- buf->count -= reclen;
-
-- return 0;
-+ return err;
- }
-
--asmlinkage int irix_ngetdents(unsigned int fd, void * dirent,
-- unsigned int count, int *eob)
-+asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent,
-+ unsigned int count, int __user *eob)
- {
- struct file *file;
-- struct irix_dirent32 *lastdirent;
-+ struct irix_dirent32 __user *lastdirent;
- struct irix_dirent32_callback buf;
- int error;
-
-@@ -1839,7 +1815,7 @@ asmlinkage int irix_ngetdents(unsigned i
- if (!file)
- goto out;
-
-- buf.current_dir = (struct irix_dirent32 *) dirent;
-+ buf.current_dir = (struct irix_dirent32 __user *) dirent;
- buf.previous = NULL;
- buf.count = count;
- buf.error = 0;
-@@ -1879,8 +1855,8 @@ struct irix_dirent64 {
- };
-
- struct irix_dirent64_callback {
-- struct irix_dirent64 *curr;
-- struct irix_dirent64 *previous;
-+ struct irix_dirent64 __user *curr;
-+ struct irix_dirent64 __user *previous;
- int count;
- int error;
- };
-@@ -1888,37 +1864,44 @@ struct irix_dirent64_callback {
- #define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de)))
- #define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1))
-
--static int irix_filldir64(void * __buf, const char * name, int namlen,
-- loff_t offset, ino_t ino, unsigned int d_type)
-+static int irix_filldir64(void *__buf, const char *name,
-+ int namlen, loff_t offset, ino_t ino, unsigned int d_type)
- {
-- struct irix_dirent64 *dirent;
-- struct irix_dirent64_callback * buf =
-- (struct irix_dirent64_callback *) __buf;
-+ struct irix_dirent64 __user *dirent;
-+ struct irix_dirent64_callback * buf = __buf;
- unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1);
-+ int err = 0;
-
-- buf->error = -EINVAL; /* only used if we fail.. */
-+ if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf)))
-+ return -EFAULT;
-+
-+ if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */
-+ return -EFAULT;
- if (reclen > buf->count)
- return -EINVAL;
- dirent = buf->previous;
- if (dirent)
-- __put_user(offset, &dirent->d_off);
-+ err = __put_user(offset, &dirent->d_off);
- dirent = buf->curr;
- buf->previous = dirent;
-- __put_user(ino, &dirent->d_ino);
-- __put_user(reclen, &dirent->d_reclen);
-- __copy_to_user(dirent->d_name, name, namlen);
-- __put_user(0, &dirent->d_name[namlen]);
-- ((char *) dirent) += reclen;
-+ err |= __put_user(ino, &dirent->d_ino);
-+ err |= __put_user(reclen, &dirent->d_reclen);
-+ err |= __copy_to_user((char __user *)dirent->d_name, name, namlen)
-+ ? -EFAULT : 0;
-+ err |= __put_user(0, &dirent->d_name[namlen]);
-+
-+ dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen);
-+
- buf->curr = dirent;
- buf->count -= reclen;
-
-- return 0;
-+ return err;
- }
-
--asmlinkage int irix_getdents64(int fd, void *dirent, int cnt)
-+asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt)
- {
- struct file *file;
-- struct irix_dirent64 *lastdirent;
-+ struct irix_dirent64 __user *lastdirent;
- struct irix_dirent64_callback buf;
- int error;
-
-@@ -1938,7 +1921,7 @@ asmlinkage int irix_getdents64(int fd, v
- if (cnt < (sizeof(struct irix_dirent64) + 255))
- goto out_f;
-
-- buf.curr = (struct irix_dirent64 *) dirent;
-+ buf.curr = (struct irix_dirent64 __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-@@ -1950,7 +1933,8 @@ asmlinkage int irix_getdents64(int fd, v
- error = buf.error;
- goto out_f;
- }
-- lastdirent->d_off = (u64) file->f_pos;
-+ if (put_user(file->f_pos, &lastdirent->d_off))
-+ return -EFAULT;
- #ifdef DEBUG_GETDENTS
- printk("returning %d\n", cnt - buf.count);
- #endif
-@@ -1962,10 +1946,10 @@ out:
- return error;
- }
-
--asmlinkage int irix_ngetdents64(int fd, void *dirent, int cnt, int *eob)
-+asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob)
- {
- struct file *file;
-- struct irix_dirent64 *lastdirent;
-+ struct irix_dirent64 __user *lastdirent;
- struct irix_dirent64_callback buf;
- int error;
-
-@@ -1987,7 +1971,7 @@ asmlinkage int irix_ngetdents64(int fd,
- goto out_f;
-
- *eob = 0;
-- buf.curr = (struct irix_dirent64 *) dirent;
-+ buf.curr = (struct irix_dirent64 __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-@@ -1999,7 +1983,8 @@ asmlinkage int irix_ngetdents64(int fd,
- error = buf.error;
- goto out_f;
- }
-- lastdirent->d_off = (u64) file->f_pos;
-+ if (put_user(file->f_pos, &lastdirent->d_off))
-+ return -EFAULT;
- #ifdef DEBUG_GETDENTS
- printk("eob=%d returning %d\n", *eob, cnt - buf.count);
- #endif
-@@ -2062,14 +2047,14 @@ out:
- return retval;
- }
-
--asmlinkage int irix_utssys(char *inbuf, int arg, int type, char *outbuf)
-+asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf)
- {
- int retval;
-
- switch(type) {
- case 0:
- /* uname() */
-- retval = irix_uname((struct iuname *)inbuf);
-+ retval = irix_uname((struct iuname __user *)inbuf);
- goto out;
-
- case 2:
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/traps.c linux_HEAD/arch/mips/kernel/traps.c
---- linux-2.6.12/arch/mips/kernel/traps.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/traps.c 2005-07-07 11:22:49.000000000 +0200
-@@ -9,7 +9,7 @@
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Kevin D. Kissell, kevink at mips.com and Carsten Langgaard, carstenl at mips.com
- * Copyright (C) 2000, 01 MIPS Technologies, Inc.
-- * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
- */
- #include <linux/config.h>
- #include <linux/init.h>
-@@ -25,6 +25,7 @@
- #include <asm/branch.h>
- #include <asm/break.h>
- #include <asm/cpu.h>
-+#include <asm/dsp.h>
- #include <asm/fpu.h>
- #include <asm/module.h>
- #include <asm/pgtable.h>
-@@ -54,6 +55,7 @@ extern asmlinkage void handle_tr(void);
- extern asmlinkage void handle_fpe(void);
- extern asmlinkage void handle_mdmx(void);
- extern asmlinkage void handle_watch(void);
-+extern asmlinkage void handle_dsp(void);
- extern asmlinkage void handle_mcheck(void);
- extern asmlinkage void handle_reserved(void);
-
-@@ -201,32 +203,47 @@ void show_regs(struct pt_regs *regs)
-
- printk("Status: %08x ", (uint32_t) regs->cp0_status);
-
-- if (regs->cp0_status & ST0_KX)
-- printk("KX ");
-- if (regs->cp0_status & ST0_SX)
-- printk("SX ");
-- if (regs->cp0_status & ST0_UX)
-- printk("UX ");
-- switch (regs->cp0_status & ST0_KSU) {
-- case KSU_USER:
-- printk("USER ");
-- break;
-- case KSU_SUPERVISOR:
-- printk("SUPERVISOR ");
-- break;
-- case KSU_KERNEL:
-- printk("KERNEL ");
-- break;
-- default:
-- printk("BAD_MODE ");
-- break;
-+ if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
-+ if (regs->cp0_status & ST0_KUO)
-+ printk("KUo ");
-+ if (regs->cp0_status & ST0_IEO)
-+ printk("IEo ");
-+ if (regs->cp0_status & ST0_KUP)
-+ printk("KUp ");
-+ if (regs->cp0_status & ST0_IEP)
-+ printk("IEp ");
-+ if (regs->cp0_status & ST0_KUC)
-+ printk("KUc ");
-+ if (regs->cp0_status & ST0_IEC)
-+ printk("IEc ");
-+ } else {
-+ if (regs->cp0_status & ST0_KX)
-+ printk("KX ");
-+ if (regs->cp0_status & ST0_SX)
-+ printk("SX ");
-+ if (regs->cp0_status & ST0_UX)
-+ printk("UX ");
-+ switch (regs->cp0_status & ST0_KSU) {
-+ case KSU_USER:
-+ printk("USER ");
-+ break;
-+ case KSU_SUPERVISOR:
-+ printk("SUPERVISOR ");
-+ break;
-+ case KSU_KERNEL:
-+ printk("KERNEL ");
-+ break;
-+ default:
-+ printk("BAD_MODE ");
-+ break;
-+ }
-+ if (regs->cp0_status & ST0_ERL)
-+ printk("ERL ");
-+ if (regs->cp0_status & ST0_EXL)
-+ printk("EXL ");
-+ if (regs->cp0_status & ST0_IE)
-+ printk("IE ");
- }
-- if (regs->cp0_status & ST0_ERL)
-- printk("ERL ");
-- if (regs->cp0_status & ST0_EXL)
-- printk("EXL ");
-- if (regs->cp0_status & ST0_IE)
-- printk("IE ");
- printk("\n");
-
- printk("Cause : %08x\n", cause);
-@@ -252,8 +269,9 @@ void show_registers(struct pt_regs *regs
-
- static DEFINE_SPINLOCK(die_lock);
-
--NORET_TYPE void __die(const char * str, struct pt_regs * regs,
-- const char * file, const char * func, unsigned long line)
-+NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs,
-+ const char * file, const char * func,
-+ unsigned long line)
- {
- static int die_counter;
-
-@@ -339,9 +357,9 @@ asmlinkage void do_be(struct pt_regs *re
-
- static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
- {
-- unsigned int *epc;
-+ unsigned int __user *epc;
-
-- epc = (unsigned int *) regs->cp0_epc +
-+ epc = (unsigned int __user *) regs->cp0_epc +
- ((regs->cp0_cause & CAUSEF_BD) != 0);
- if (!get_user(*opcode, epc))
- return 0;
-@@ -360,6 +378,10 @@ static inline int get_insn_opcode(struct
- #define OFFSET 0x0000ffff
- #define LL 0xc0000000
- #define SC 0xe0000000
-+#define SPEC3 0x7c000000
-+#define RD 0x0000f800
-+#define FUNC 0x0000003f
-+#define RDHWR 0x0000003b
-
- /*
- * The ll_bit is cleared by r*_switch.S
-@@ -371,7 +393,7 @@ static struct task_struct *ll_task = NUL
-
- static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
- {
-- unsigned long value, *vaddr;
-+ unsigned long value, __user *vaddr;
- long offset;
- int signal = 0;
-
-@@ -385,7 +407,8 @@ static inline void simulate_ll(struct pt
- offset <<= 16;
- offset >>= 16;
-
-- vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
-+ vaddr = (unsigned long __user *)
-+ ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
-
- if ((unsigned long)vaddr & 3) {
- signal = SIGBUS;
-@@ -407,9 +430,10 @@ static inline void simulate_ll(struct pt
-
- preempt_enable();
-
-+ compute_return_epc(regs);
-+
- regs->regs[(opcode & RT) >> 16] = value;
-
-- compute_return_epc(regs);
- return;
-
- sig:
-@@ -418,7 +442,8 @@ sig:
-
- static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
- {
-- unsigned long *vaddr, reg;
-+ unsigned long __user *vaddr;
-+ unsigned long reg;
- long offset;
- int signal = 0;
-
-@@ -432,7 +457,8 @@ static inline void simulate_sc(struct pt
- offset <<= 16;
- offset >>= 16;
-
-- vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
-+ vaddr = (unsigned long __user *)
-+ ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
- reg = (opcode & RT) >> 16;
-
- if ((unsigned long)vaddr & 3) {
-@@ -443,9 +469,9 @@ static inline void simulate_sc(struct pt
- preempt_disable();
-
- if (ll_bit == 0 || ll_task != current) {
-+ compute_return_epc(regs);
- regs->regs[reg] = 0;
- preempt_enable();
-- compute_return_epc(regs);
- return;
- }
-
-@@ -456,9 +482,9 @@ static inline void simulate_sc(struct pt
- goto sig;
- }
-
-+ compute_return_epc(regs);
- regs->regs[reg] = 1;
-
-- compute_return_epc(regs);
- return;
-
- sig:
-@@ -491,6 +517,37 @@ static inline int simulate_llsc(struct p
- return -EFAULT; /* Strange things going on ... */
- }
-
-+/*
-+ * Simulate trapping 'rdhwr' instructions to provide user accessible
-+ * registers not implemented in hardware. The only current use of this
-+ * is the thread area pointer.
-+ */
-+static inline int simulate_rdhwr(struct pt_regs *regs)
-+{
-+ struct thread_info *ti = current->thread_info;
-+ unsigned int opcode;
-+
-+ if (unlikely(get_insn_opcode(regs, &opcode)))
-+ return -EFAULT;
-+
-+ if (unlikely(compute_return_epc(regs)))
-+ return -EFAULT;
-+
-+ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
-+ int rd = (opcode & RD) >> 11;
-+ int rt = (opcode & RT) >> 16;
-+ switch (rd) {
-+ case 29:
-+ regs->regs[rt] = ti->tp_value;
-+ break;
-+ default:
-+ return -EFAULT;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
- asmlinkage void do_ov(struct pt_regs *regs)
- {
- siginfo_t info;
-@@ -498,7 +555,7 @@ asmlinkage void do_ov(struct pt_regs *re
- info.si_code = FPE_INTOVF;
- info.si_signo = SIGFPE;
- info.si_errno = 0;
-- info.si_addr = (void *)regs->cp0_epc;
-+ info.si_addr = (void __user *) regs->cp0_epc;
- force_sig_info(SIGFPE, &info, current);
- }
-
-@@ -512,6 +569,14 @@ asmlinkage void do_fpe(struct pt_regs *r
-
- preempt_disable();
-
-+#ifdef CONFIG_PREEMPT
-+ if (!is_fpu_owner()) {
-+ /* We might lose fpu before disabling preempt... */
-+ own_fpu();
-+ BUG_ON(!used_math());
-+ restore_fp(current);
-+ }
-+#endif
- /*
- * Unimplemented operation exception. If we've got the full
- * software emulator on-board, let's use it...
-@@ -523,11 +588,18 @@ asmlinkage void do_fpe(struct pt_regs *r
- * a bit extreme for what should be an infrequent event.
- */
- save_fp(current);
-+ /* Ensure 'resume' not overwrite saved fp context again. */
-+ lose_fpu();
-+
-+ preempt_enable();
-
- /* Run the emulator */
- sig = fpu_emulator_cop1Handler (0, regs,
- ¤t->thread.fpu.soft);
-
-+ preempt_disable();
-+
-+ own_fpu(); /* Using the FPU again. */
- /*
- * We can't allow the emulated instruction to leave any of
- * the cause bit set in $fcr31.
-@@ -584,7 +656,7 @@ asmlinkage void do_bp(struct pt_regs *re
- info.si_code = FPE_INTOVF;
- info.si_signo = SIGFPE;
- info.si_errno = 0;
-- info.si_addr = (void *)regs->cp0_epc;
-+ info.si_addr = (void __user *) regs->cp0_epc;
- force_sig_info(SIGFPE, &info, current);
- break;
- default:
-@@ -621,7 +693,7 @@ asmlinkage void do_tr(struct pt_regs *re
- info.si_code = FPE_INTOVF;
- info.si_signo = SIGFPE;
- info.si_errno = 0;
-- info.si_addr = (void *)regs->cp0_epc;
-+ info.si_addr = (void __user *) regs->cp0_epc;
- force_sig_info(SIGFPE, &info, current);
- break;
- default:
-@@ -637,6 +709,9 @@ asmlinkage void do_ri(struct pt_regs *re
- if (!simulate_llsc(regs))
- return;
-
-+ if (!simulate_rdhwr(regs))
-+ return;
-+
- force_sig(SIGILL, current);
- }
-
-@@ -650,11 +725,13 @@ asmlinkage void do_cpu(struct pt_regs *r
-
- switch (cpid) {
- case 0:
-- if (cpu_has_llsc)
-- break;
-+ if (!cpu_has_llsc)
-+ if (!simulate_llsc(regs))
-+ return;
-
-- if (!simulate_llsc(regs))
-+ if (!simulate_rdhwr(regs))
- return;
-+
- break;
-
- case 1:
-@@ -668,6 +745,8 @@ asmlinkage void do_cpu(struct pt_regs *r
- set_used_math();
- }
-
-+ preempt_enable();
-+
- if (!cpu_has_fpu) {
- int sig = fpu_emulator_cop1Handler(0, regs,
- ¤t->thread.fpu.soft);
-@@ -675,8 +754,6 @@ asmlinkage void do_cpu(struct pt_regs *r
- force_sig(sig, current);
- }
-
-- preempt_enable();
--
- return;
-
- case 2:
-@@ -716,6 +793,14 @@ asmlinkage void do_mcheck(struct pt_regs
- (regs->cp0_status & ST0_TS) ? "" : "not ");
- }
-
-+asmlinkage void do_dsp(struct pt_regs *regs)
-+{
-+ if (cpu_has_dsp)
-+ panic("Unexpected DSP exception\n");
-+
-+ force_sig(SIGILL, current);
-+}
-+
- asmlinkage void do_reserved(struct pt_regs *regs)
- {
- /*
-@@ -736,16 +821,12 @@ static inline void parity_protection_ini
- {
- switch (current_cpu_data.cputype) {
- case CPU_24K:
-- /* 24K cache parity not currently implemented in FPGA */
-- printk(KERN_INFO "Disable cache parity protection for "
-- "MIPS 24K CPU.\n");
-- write_c0_ecc(read_c0_ecc() & ~0x80000000);
-- break;
- case CPU_5KC:
-- /* Set the PE bit (bit 31) in the c0_ecc register. */
-- printk(KERN_INFO "Enable cache parity protection for "
-- "MIPS 5KC/24K CPUs.\n");
-- write_c0_ecc(read_c0_ecc() | 0x80000000);
-+ write_c0_ecc(0x80000000);
-+ back_to_back_c0_hazard();
-+ /* Set the PE bit (bit 31) in the c0_errctl register. */
-+ printk(KERN_INFO "Cache parity protection %sabled\n",
-+ (read_c0_ecc() & 0x80000000) ? "en" : "dis");
- break;
- case CPU_20KC:
- case CPU_25KF:
-@@ -783,7 +864,7 @@ asmlinkage void cache_parity_error(void)
- reg_val & (1<<22) ? "E0 " : "");
- printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
-
--#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
-+#if defined(CONFIG_CPU_MIPS32_R1) || defined (CONFIG_CPU_MIPS64_R1)
- if (reg_val & (1<<22))
- printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
-
-@@ -929,9 +1010,12 @@ void __init per_cpu_trap_init(void)
- #endif
- if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
- status_set |= ST0_XX;
-- change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
-+ change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
- status_set);
-
-+ if (cpu_has_dsp)
-+ set_c0_status(ST0_MX);
-+
- /*
- * Some MIPS CPUs have a dedicated interrupt vector which reduces the
- * interrupt processing overhead. Use it where available.
-@@ -1023,21 +1107,6 @@ void __init trap_init(void)
- set_except_vector(11, handle_cpu);
- set_except_vector(12, handle_ov);
- set_except_vector(13, handle_tr);
-- set_except_vector(22, handle_mdmx);
--
-- if (cpu_has_fpu && !cpu_has_nofpuex)
-- set_except_vector(15, handle_fpe);
--
-- if (cpu_has_mcheck)
-- set_except_vector(24, handle_mcheck);
--
-- if (cpu_has_vce)
-- /* Special exception: R4[04]00 uses also the divec space. */
-- memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
-- else if (cpu_has_4kex)
-- memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
-- else
-- memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
-
- if (current_cpu_data.cputype == CPU_R6000 ||
- current_cpu_data.cputype == CPU_R6000A) {
-@@ -1053,6 +1122,25 @@ void __init trap_init(void)
- //set_except_vector(15, handle_ndc);
- }
-
-+ if (cpu_has_fpu && !cpu_has_nofpuex)
-+ set_except_vector(15, handle_fpe);
-+
-+ set_except_vector(22, handle_mdmx);
-+
-+ if (cpu_has_mcheck)
-+ set_except_vector(24, handle_mcheck);
-+
-+ if (cpu_has_dsp)
-+ set_except_vector(26, handle_dsp);
-+
-+ if (cpu_has_vce)
-+ /* Special exception: R4[04]00 uses also the divec space. */
-+ memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
-+ else if (cpu_has_4kex)
-+ memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
-+ else
-+ memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
-+
- signal_init();
- #ifdef CONFIG_MIPS32_COMPAT
- signal32_init();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/unaligned.c linux_HEAD/arch/mips/kernel/unaligned.c
---- linux-2.6.12/arch/mips/kernel/unaligned.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/unaligned.c 2005-03-17 22:20:26.000000000 +0100
-@@ -94,7 +94,7 @@ unsigned long unaligned_instructions;
- #endif
-
- static inline int emulate_load_store_insn(struct pt_regs *regs,
-- void *addr, unsigned long pc,
-+ void __user *addr, unsigned int __user *pc,
- unsigned long **regptr, unsigned long *newvalue)
- {
- union mips_instruction insn;
-@@ -107,7 +107,7 @@ static inline int emulate_load_store_ins
- /*
- * This load never faults.
- */
-- __get_user(insn.word, (unsigned int *)pc);
-+ __get_user(insn.word, pc);
-
- switch (insn.i_format.opcode) {
- /*
-@@ -494,8 +494,8 @@ asmlinkage void do_ade(struct pt_regs *r
- {
- unsigned long *regptr, newval;
- extern int do_dsemulret(struct pt_regs *);
-+ unsigned int __user *pc;
- mm_segment_t seg;
-- unsigned long pc;
-
- /*
- * Address errors may be deliberately induced by the FPU emulator to
-@@ -515,7 +515,7 @@ asmlinkage void do_ade(struct pt_regs *r
- if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
- goto sigbus;
-
-- pc = exception_epc(regs);
-+ pc = (unsigned int __user *) exception_epc(regs);
- if ((current->thread.mflags & MF_FIXADE) == 0)
- goto sigbus;
-
-@@ -526,7 +526,7 @@ asmlinkage void do_ade(struct pt_regs *r
- seg = get_fs();
- if (!user_mode(regs))
- set_fs(KERNEL_DS);
-- if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc,
-+ if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
- ®ptr, &newval)) {
- compute_return_epc(regs);
- /*
-diff -urpNX dontdiff linux-2.6.12/arch/mips/kernel/vmlinux.lds.S linux_HEAD/arch/mips/kernel/vmlinux.lds.S
---- linux-2.6.12/arch/mips/kernel/vmlinux.lds.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/kernel/vmlinux.lds.S 2005-07-01 12:09:18.000000000 +0200
-@@ -54,13 +54,6 @@ SECTIONS
-
- *(.data)
-
-- /* Align the initial ramdisk image (INITRD) on page boundaries. */
-- . = ALIGN(4096);
-- __rd_start = .;
-- *(.initrd)
-- . = ALIGN(4096);
-- __rd_end = .;
--
- CONSTRUCTORS
- }
- _gp = . + 0x8000;
-@@ -96,12 +89,6 @@ SECTIONS
- .init.setup : { *(.init.setup) }
- __setup_end = .;
-
-- .early_initcall.init : {
-- __earlyinitcall_start = .;
-- *(.initcall.early1.init)
-- }
-- __earlyinitcall_end = .;
--
- __initcall_start = .;
- .initcall.init : {
- *(.initcall1.init)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lasat/Kconfig linux_HEAD/arch/mips/lasat/Kconfig
---- linux-2.6.12/arch/mips/lasat/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/lasat/Kconfig 2005-01-30 21:45:37.000000000 +0100
-@@ -0,0 +1,15 @@
-+config PICVUE
-+ tristate "PICVUE LCD display driver"
-+ depends on LASAT
-+
-+config PICVUE_PROC
-+ tristate "PICVUE LCD display driver /proc interface"
-+ depends on PICVUE
-+
-+config DS1603
-+ bool "DS1603 RTC driver"
-+ depends on LASAT
-+
-+config LASAT_SYSCTL
-+ bool "LASAT sysctl interface"
-+ depends on LASAT
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lasat/interrupt.c linux_HEAD/arch/mips/lasat/interrupt.c
---- linux-2.6.12/arch/mips/lasat/interrupt.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lasat/interrupt.c 2005-02-28 16:56:42.000000000 +0100
-@@ -71,14 +71,13 @@ static void end_lasat_irq(unsigned int i
- }
-
- static struct hw_interrupt_type lasat_irq_type = {
-- "Lasat",
-- startup_lasat_irq,
-- shutdown_lasat_irq,
-- enable_lasat_irq,
-- disable_lasat_irq,
-- mask_and_ack_lasat_irq,
-- end_lasat_irq,
-- NULL
-+ .typename = "Lasat",
-+ .startup = startup_lasat_irq,
-+ .shutdown = shutdown_lasat_irq,
-+ .enable = enable_lasat_irq,
-+ .disable = disable_lasat_irq,
-+ .ack = mask_and_ack_lasat_irq,
-+ .end = end_lasat_irq,
- };
-
- static inline int ls1bit32(unsigned int x)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lasat/setup.c linux_HEAD/arch/mips/lasat/setup.c
---- linux-2.6.12/arch/mips/lasat/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lasat/setup.c 2005-07-01 12:09:18.000000000 +0200
-@@ -155,7 +155,7 @@ void __init serial_init(void)
- }
- #endif
-
--static int __init lasat_setup(void)
-+void __init plat_setup(void)
- {
- int i;
- lasat_misc = &lasat_misc_info[mips_machtype];
-@@ -185,8 +185,4 @@ static int __init lasat_setup(void)
- change_c0_status(ST0_BEV,0);
-
- prom_printf("Lasat specific initialization complete\n");
--
-- return 0;
- }
--
--early_initcall(lasat_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib/Makefile linux_HEAD/arch/mips/lib/Makefile
---- linux-2.6.12/arch/mips/lib/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib/Makefile 2005-04-23 05:27:41.000000000 +0200
-@@ -2,9 +2,7 @@
- # Makefile for MIPS-specific library files..
- #
-
--lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o \
-- strlen_user.o strncpy_user.o strnlen_user.o
--
--obj-y += iomap.o
-+lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o strlen_user.o \
-+ strncpy_user.o strnlen_user.o uncached.o
-
- EXTRA_AFLAGS := $(CFLAGS)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib/csum_partial_copy.c linux_HEAD/arch/mips/lib/csum_partial_copy.c
---- linux-2.6.12/arch/mips/lib/csum_partial_copy.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib/csum_partial_copy.c 2005-02-17 21:48:56.000000000 +0100
-@@ -16,8 +16,8 @@
- /*
- * copy while checksumming, otherwise like csum_partial
- */
--unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *dst,
-- int len, unsigned int sum)
-+unsigned int csum_partial_copy_nocheck(const unsigned char *src,
-+ unsigned char *dst, int len, unsigned int sum)
- {
- /*
- * It's 2:30 am and I don't feel like doing it real ...
-@@ -33,8 +33,8 @@ unsigned int csum_partial_copy_nocheck(c
- * Copy from userspace and compute checksum. If we catch an exception
- * then zero the rest of the buffer.
- */
--unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst,
-- int len, unsigned int sum, int *err_ptr)
-+unsigned int csum_partial_copy_from_user (const unsigned char *src,
-+ unsigned char *dst, int len, unsigned int sum, int *err_ptr)
- {
- int missing;
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib/iomap.c linux_HEAD/arch/mips/lib/iomap.c
---- linux-2.6.12/arch/mips/lib/iomap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib/iomap.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,78 +0,0 @@
--/*
-- * iomap.c, Memory Mapped I/O routines for MIPS architecture.
-- *
-- * This code is based on lib/iomap.c, by Linus Torvalds.
-- *
-- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#include <linux/ioport.h>
--#include <linux/module.h>
--#include <linux/pci.h>
--
--#include <asm/io.h>
--
--void __iomem *ioport_map(unsigned long port, unsigned int nr)
--{
-- unsigned long end;
--
-- end = port + nr - 1UL;
-- if (ioport_resource.start > port ||
-- ioport_resource.end < end || port > end)
-- return NULL;
--
-- return (void __iomem *)(mips_io_port_base + port);
--}
--
--void ioport_unmap(void __iomem *addr)
--{
--}
--EXPORT_SYMBOL(ioport_map);
--EXPORT_SYMBOL(ioport_unmap);
--
--void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
--{
-- unsigned long start, len, flags;
--
-- if (dev == NULL)
-- return NULL;
--
-- start = pci_resource_start(dev, bar);
-- len = pci_resource_len(dev, bar);
-- if (!start || !len)
-- return NULL;
--
-- if (maxlen != 0 && len > maxlen)
-- len = maxlen;
--
-- flags = pci_resource_flags(dev, bar);
-- if (flags & IORESOURCE_IO)
-- return ioport_map(start, len);
-- if (flags & IORESOURCE_MEM) {
-- if (flags & IORESOURCE_CACHEABLE)
-- return ioremap_cacheable_cow(start, len);
-- return ioremap_nocache(start, len);
-- }
--
-- return NULL;
--}
--
--void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
--{
-- iounmap(addr);
--}
--EXPORT_SYMBOL(pci_iomap);
--EXPORT_SYMBOL(pci_iounmap);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib/uncached.c linux_HEAD/arch/mips/lib/uncached.c
---- linux-2.6.12/arch/mips/lib/uncached.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/lib/uncached.c 2005-04-23 17:08:56.000000000 +0200
-@@ -0,0 +1,36 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005 Thiemo Seufer
-+ */
-+#include <linux/init.h>
-+
-+#include <asm/addrspace.h>
-+
-+/*
-+ * FUNC is executed in the uncached segment CKSEG1. This works only if
-+ * both code and stack live in CKSEG0. The stack handling works because
-+ * we don't handle stack arguments or more complex return values, so we
-+ * can avoid to share the same stack area between cached and uncached
-+ * mode.
-+ */
-+unsigned long __init run_uncached(void *func)
-+{
-+ register unsigned long sp __asm__("$sp");
-+ register unsigned long ret __asm__("$2");
-+ unsigned long usp = sp - CAC_BASE + UNCAC_BASE;
-+ unsigned long ufunc = func - CAC_BASE + UNCAC_BASE;
-+
-+ __asm__ __volatile__ (
-+ " move $16, $sp\n"
-+ " move $sp, %1\n"
-+ " jalr $ra, %2\n"
-+ " move $sp, $16"
-+ : "=&r" (ret)
-+ : "r" (usp), "r" (ufunc)
-+ : "$16", "$31");
-+
-+ return ret;
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib-32/Makefile linux_HEAD/arch/mips/lib-32/Makefile
---- linux-2.6.12/arch/mips/lib-32/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib-32/Makefile 2005-07-07 11:22:49.000000000 +0200
-@@ -4,8 +4,8 @@
-
- lib-y += csum_partial.o memset.o watch.o
-
--obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
--obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
-+obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
-+obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
- obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
- obj-$(CONFIG_CPU_R10000) += dump_tlb.o
- obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib-32/dump_tlb.c linux_HEAD/arch/mips/lib-32/dump_tlb.c
---- linux-2.6.12/arch/mips/lib-32/dump_tlb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib-32/dump_tlb.c 2005-02-17 21:48:56.000000000 +0100
-@@ -32,8 +32,6 @@ static inline const char *msk2str(unsign
- case PM_256M: return "256Mb";
- #endif
- }
--
-- return "unknown";
- }
-
- #define BARRIER() \
-@@ -139,6 +137,7 @@ void dump_tlb_nonwired(void)
- void dump_list_process(struct task_struct *t, void *address)
- {
- pgd_t *page_dir, *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte, page;
- unsigned long addr, val;
-@@ -162,7 +161,10 @@ void dump_list_process(struct task_struc
- pgd = pgd_offset(t->mm, addr);
- printk("pgd == %08x, ", (unsigned int) pgd);
-
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ printk("pud == %08x, ", (unsigned int) pud);
-+
-+ pmd = pmd_offset(pud, addr);
- printk("pmd == %08x, ", (unsigned int) pmd);
-
- pte = pte_offset(pmd, addr);
-@@ -195,13 +197,15 @@ void dump_list_current(void *address)
- unsigned int vtop(void *address)
- {
- pgd_t *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned int addr, paddr;
-
- addr = (unsigned long) address;
- pgd = pgd_offset(current->mm, addr);
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ pmd = pmd_offset(pud, addr);
- pte = pte_offset(pmd, addr);
- paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
- paddr |= (addr & ~PAGE_MASK);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib-32/r3k_dump_tlb.c linux_HEAD/arch/mips/lib-32/r3k_dump_tlb.c
---- linux-2.6.12/arch/mips/lib-32/r3k_dump_tlb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib-32/r3k_dump_tlb.c 2005-02-17 21:48:56.000000000 +0100
-@@ -105,6 +105,7 @@ void dump_tlb_nonwired(void)
- void dump_list_process(struct task_struct *t, void *address)
- {
- pgd_t *page_dir, *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte, page;
- unsigned int addr;
-@@ -121,7 +122,10 @@ void dump_list_process(struct task_struc
- pgd = pgd_offset(t->mm, addr);
- printk("pgd == %08x, ", (unsigned int) pgd);
-
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ printk("pud == %08x, ", (unsigned int) pud);
-+
-+ pmd = pmd_offset(pud, addr);
- printk("pmd == %08x, ", (unsigned int) pmd);
-
- pte = pte_offset(pmd, addr);
-@@ -149,13 +153,15 @@ void dump_list_current(void *address)
- unsigned int vtop(void *address)
- {
- pgd_t *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned int addr, paddr;
-
- addr = (unsigned long) address;
- pgd = pgd_offset(current->mm, addr);
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ pmd = pmd_offset(pud, addr);
- pte = pte_offset(pmd, addr);
- paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
- paddr |= (addr & ~PAGE_MASK);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib-64/Makefile linux_HEAD/arch/mips/lib-64/Makefile
---- linux-2.6.12/arch/mips/lib-64/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib-64/Makefile 2005-07-07 11:22:49.000000000 +0200
-@@ -4,8 +4,8 @@
-
- lib-y += csum_partial.o memset.o watch.o
-
--obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
--obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
-+obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
-+obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
- obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
- obj-$(CONFIG_CPU_R10000) += dump_tlb.o
- obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/lib-64/dump_tlb.c linux_HEAD/arch/mips/lib-64/dump_tlb.c
---- linux-2.6.12/arch/mips/lib-64/dump_tlb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/lib-64/dump_tlb.c 2005-02-17 21:48:56.000000000 +0100
-@@ -32,8 +32,6 @@ static inline const char *msk2str(unsign
- case PM_256M: return "256Mb";
- #endif
- }
--
-- return "unknown";
- }
-
- #define BARRIER() \
-@@ -140,6 +138,7 @@ void dump_tlb_nonwired(void)
- void dump_list_process(struct task_struct *t, void *address)
- {
- pgd_t *page_dir, *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte, page;
- unsigned long addr, val;
-@@ -155,7 +154,10 @@ void dump_list_process(struct task_struc
- pgd = pgd_offset(t->mm, addr);
- printk("pgd == %016lx\n", (unsigned long) pgd);
-
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ printk("pud == %016lx\n", (unsigned long) pud);
-+
-+ pmd = pmd_offset(pud, addr);
- printk("pmd == %016lx\n", (unsigned long) pmd);
-
- pte = pte_offset(pmd, addr);
-@@ -184,13 +186,15 @@ void dump_list_current(void *address)
- unsigned int vtop(void *address)
- {
- pgd_t *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned int addr, paddr;
-
- addr = (unsigned long) address;
- pgd = pgd_offset(current->mm, addr);
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ pmd = pmd_offset(pud, addr);
- pte = pte_offset(pmd, addr);
- paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
- paddr |= (addr & ~PAGE_MASK);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/cp1emu.c linux_HEAD/arch/mips/math-emu/cp1emu.c
---- linux-2.6.12/arch/mips/math-emu/cp1emu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/cp1emu.c 2005-05-14 14:38:21.000000000 +0200
-@@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *,
-
- /* Further private data for which no space exists in mips_fpu_soft_struct */
-
--struct mips_fpu_emulator_private fpuemuprivate;
-+struct mips_fpu_emulator_stats fpuemustats;
-
- /* Control registers */
-
-@@ -79,7 +79,17 @@ struct mips_fpu_emulator_private fpuemup
-
- /* Convert Mips rounding mode (0..3) to IEEE library modes. */
- static const unsigned char ieee_rm[4] = {
-- IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD
-+ [FPU_CSR_RN] = IEEE754_RN,
-+ [FPU_CSR_RZ] = IEEE754_RZ,
-+ [FPU_CSR_RU] = IEEE754_RU,
-+ [FPU_CSR_RD] = IEEE754_RD,
-+};
-+/* Convert IEEE library modes to Mips rounding mode (0..3). */
-+static const unsigned char mips_rm[4] = {
-+ [IEEE754_RN] = FPU_CSR_RN,
-+ [IEEE754_RZ] = FPU_CSR_RZ,
-+ [IEEE754_RD] = FPU_CSR_RD,
-+ [IEEE754_RU] = FPU_CSR_RU,
- };
-
- #if __mips >= 4
-@@ -196,11 +206,11 @@ static int isBranchInstr(mips_instructio
- static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
- {
- mips_instruction ir;
-- vaddr_t emulpc, contpc;
-+ void * emulpc, *contpc;
- unsigned int cond;
-
- if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
-
-@@ -221,41 +231,40 @@ static int cop1Emulate(struct pt_regs *x
- * Linux MIPS branch emulator operates on context, updating the
- * cp0_epc.
- */
-- emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */
-+ emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
-
- if (__compute_return_epc(xcp)) {
- #ifdef CP1DBG
- printk("failed to emulate branch at %p\n",
-- REG_TO_VA(xcp->cp0_epc));
-+ (void *) (xcp->cp0_epc));
- #endif
- return SIGILL;
- }
- if (get_user(ir, (mips_instruction *) emulpc)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- /* __compute_return_epc() will have updated cp0_epc */
-- contpc = REG_TO_VA xcp->cp0_epc;
-+ contpc = (void *) xcp->cp0_epc;
- /* In order not to confuse ptrace() et al, tweak context */
-- xcp->cp0_epc = VA_TO_REG emulpc - 4;
-- }
-- else {
-- emulpc = REG_TO_VA xcp->cp0_epc;
-- contpc = REG_TO_VA(xcp->cp0_epc + 4);
-+ xcp->cp0_epc = (unsigned long) emulpc - 4;
-+ } else {
-+ emulpc = (void *) xcp->cp0_epc;
-+ contpc = (void *) (xcp->cp0_epc + 4);
- }
-
- emul:
-- fpuemuprivate.stats.emulated++;
-+ fpuemustats.emulated++;
- switch (MIPSInst_OPCODE(ir)) {
- #ifndef SINGLE_ONLY_FPU
- case ldc1_op:{
-- u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
-+ u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
- MIPSInst_SIMM(ir));
- u64 val;
-
-- fpuemuprivate.stats.loads++;
-+ fpuemustats.loads++;
- if (get_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- DITOREG(val, MIPSInst_RT(ir));
-@@ -263,14 +272,14 @@ static int cop1Emulate(struct pt_regs *x
- }
-
- case sdc1_op:{
-- u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
-+ u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
- MIPSInst_SIMM(ir));
- u64 val;
-
-- fpuemuprivate.stats.stores++;
-+ fpuemustats.stores++;
- DIFROMREG(val, MIPSInst_RT(ir));
- if (put_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- break;
-@@ -278,13 +287,13 @@ static int cop1Emulate(struct pt_regs *x
- #endif
-
- case lwc1_op:{
-- u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
-+ u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
- MIPSInst_SIMM(ir));
- u32 val;
-
-- fpuemuprivate.stats.loads++;
-+ fpuemustats.loads++;
- if (get_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- #ifdef SINGLE_ONLY_FPU
-@@ -298,11 +307,11 @@ static int cop1Emulate(struct pt_regs *x
- }
-
- case swc1_op:{
-- u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
-+ u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
- MIPSInst_SIMM(ir));
- u32 val;
-
-- fpuemuprivate.stats.stores++;
-+ fpuemustats.stores++;
- #ifdef SINGLE_ONLY_FPU
- if (MIPSInst_RT(ir) & 1) {
- /* illegal register in single-float mode */
-@@ -311,7 +320,7 @@ static int cop1Emulate(struct pt_regs *x
- #endif
- SIFROMREG(val, MIPSInst_RT(ir));
- if (put_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- break;
-@@ -369,9 +378,10 @@ static int cop1Emulate(struct pt_regs *x
- }
- if (MIPSInst_RD(ir) == FPCREG_CSR) {
- value = ctx->fcr31;
-+ value = (value & ~0x3) | mips_rm[value & 0x3];
- #ifdef CSRTRACE
- printk("%p gpr[%d]<-csr=%08x\n",
-- REG_TO_VA(xcp->cp0_epc),
-+ (void *) (xcp->cp0_epc),
- MIPSInst_RT(ir), value);
- #endif
- }
-@@ -398,14 +408,13 @@ static int cop1Emulate(struct pt_regs *x
- if (MIPSInst_RD(ir) == FPCREG_CSR) {
- #ifdef CSRTRACE
- printk("%p gpr[%d]->csr=%08x\n",
-- REG_TO_VA(xcp->cp0_epc),
-+ (void *) (xcp->cp0_epc),
- MIPSInst_RT(ir), value);
- #endif
-- ctx->fcr31 = value;
-- /* copy new rounding mode and
-- flush bit to ieee library state! */
-- ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
-- ieee754_csr.rm = ieee_rm[value & 0x3];
-+ value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
-+ ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
-+ /* convert to ieee library modes */
-+ ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
- }
- if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
- return SIGFPE;
-@@ -445,13 +454,13 @@ static int cop1Emulate(struct pt_regs *x
- * instruction
- */
- xcp->cp0_epc += 4;
-- contpc = REG_TO_VA
-+ contpc = (void *)
- (xcp->cp0_epc +
- (MIPSInst_SIMM(ir) << 2));
-
- if (get_user(ir, (mips_instruction *)
-- REG_TO_VA xcp->cp0_epc)) {
-- fpuemuprivate.stats.errors++;
-+ (void *) xcp->cp0_epc)) {
-+ fpuemustats.errors++;
- return SIGBUS;
- }
-
-@@ -480,7 +489,7 @@ static int cop1Emulate(struct pt_regs *x
- * Single step the non-cp1
- * instruction in the dslot
- */
-- return mips_dsemul(xcp, ir, VA_TO_REG contpc);
-+ return mips_dsemul(xcp, ir, (unsigned long) contpc);
- }
- else {
- /* branch not taken */
-@@ -539,8 +548,9 @@ static int cop1Emulate(struct pt_regs *x
- }
-
- /* we did it !! */
-- xcp->cp0_epc = VA_TO_REG(contpc);
-+ xcp->cp0_epc = (unsigned long) contpc;
- xcp->cp0_cause &= ~CAUSEF_BD;
-+
- return 0;
- }
-
-@@ -570,7 +580,7 @@ static const unsigned char cmptab[8] = {
- static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
- ieee754##p t) \
- { \
-- struct ieee754_csr ieee754_csr_save; \
-+ struct _ieee754_csr ieee754_csr_save; \
- s = f1 (s, t); \
- ieee754_csr_save = ieee754_csr; \
- s = f2 (s, r); \
-@@ -616,7 +626,7 @@ static int fpux_emu(struct pt_regs *xcp,
- {
- unsigned rcsr = 0; /* resulting csr */
-
-- fpuemuprivate.stats.cp1xops++;
-+ fpuemustats.cp1xops++;
-
- switch (MIPSInst_FMA_FFMT(ir)) {
- case s_fmt:{ /* 0 */
-@@ -628,12 +638,12 @@ static int fpux_emu(struct pt_regs *xcp,
-
- switch (MIPSInst_FUNC(ir)) {
- case lwxc1_op:
-- va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
-+ va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
-
-- fpuemuprivate.stats.loads++;
-+ fpuemustats.loads++;
- if (get_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- #ifdef SINGLE_ONLY_FPU
-@@ -648,10 +658,10 @@ static int fpux_emu(struct pt_regs *xcp,
- break;
-
- case swxc1_op:
-- va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
-+ va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
-
-- fpuemuprivate.stats.stores++;
-+ fpuemustats.stores++;
- #ifdef SINGLE_ONLY_FPU
- if (MIPSInst_FS(ir) & 1) {
- /* illegal register in single-float
-@@ -663,7 +673,7 @@ static int fpux_emu(struct pt_regs *xcp,
-
- SIFROMREG(val, MIPSInst_FS(ir));
- if (put_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- break;
-@@ -699,8 +709,6 @@ static int fpux_emu(struct pt_regs *xcp,
- rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
-
- ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
-- if (ieee754_csr.nod)
-- ctx->fcr31 |= 0x1000000;
- if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
- /*printk ("SIGFPE: fpu csr = %08x\n",
- ctx->fcr31); */
-@@ -724,25 +732,25 @@ static int fpux_emu(struct pt_regs *xcp,
-
- switch (MIPSInst_FUNC(ir)) {
- case ldxc1_op:
-- va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
-+ va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
-
-- fpuemuprivate.stats.loads++;
-+ fpuemustats.loads++;
- if (get_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- DITOREG(val, MIPSInst_FD(ir));
- break;
-
- case sdxc1_op:
-- va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
-+ va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
- xcp->regs[MIPSInst_FT(ir)]);
-
-- fpuemuprivate.stats.stores++;
-+ fpuemustats.stores++;
- DIFROMREG(val, MIPSInst_FS(ir));
- if (put_user(val, va)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- break;
-@@ -810,7 +818,7 @@ static int fpu_emu(struct pt_regs *xcp,
- #endif
- } rv; /* resulting value */
-
-- fpuemuprivate.stats.cp1ops++;
-+ fpuemustats.cp1ops++;
- switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
- case s_fmt:{ /* 0 */
- union {
-@@ -1282,7 +1290,7 @@ static int fpu_emu(struct pt_regs *xcp,
- int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
- struct mips_fpu_soft_struct *ctx)
- {
-- gpreg_t oldepc, prevepc;
-+ unsigned long oldepc, prevepc;
- mips_instruction insn;
- int sig = 0;
-
-@@ -1291,18 +1299,23 @@ int fpu_emulator_cop1Handler(int xcptno,
- prevepc = xcp->cp0_epc;
-
- if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
- if (insn == 0)
- xcp->cp0_epc += 4; /* skip nops */
- else {
-- /* Update ieee754_csr. Only relevant if we have a
-- h/w FPU */
-- ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
-- ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3];
-- ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f;
-+ /*
-+ * The 'ieee754_csr' is an alias of
-+ * ctx->fcr31. No need to copy ctx->fcr31 to
-+ * ieee754_csr. But ieee754_csr.rm is ieee
-+ * library modes. (not mips rounding mode)
-+ */
-+ /* convert to ieee library modes */
-+ ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
- sig = cop1Emulate(xcp, ctx);
-+ /* revert to mips rounding mode */
-+ ieee754_csr.rm = mips_rm[ieee754_csr.rm];
- }
-
- if (cpu_has_fpu)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/dp_sqrt.c linux_HEAD/arch/mips/math-emu/dp_sqrt.c
---- linux-2.6.12/arch/mips/math-emu/dp_sqrt.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/dp_sqrt.c 2005-04-30 15:33:39.000000000 +0200
-@@ -37,7 +37,7 @@ static const unsigned table[] = {
-
- ieee754dp ieee754dp_sqrt(ieee754dp x)
- {
-- struct ieee754_csr oldcsr;
-+ struct _ieee754_csr oldcsr;
- ieee754dp y, z, t;
- unsigned scalx, yh;
- COMPXDP;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/dsemul.c linux_HEAD/arch/mips/math-emu/dsemul.c
---- linux-2.6.12/arch/mips/math-emu/dsemul.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/dsemul.c 2005-05-14 14:38:21.000000000 +0200
-@@ -28,9 +28,6 @@
- #endif
- #define __mips 4
-
--extern struct mips_fpu_emulator_private fpuemuprivate;
--
--
- /*
- * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
- * we have to emulate the instruction in a COP1 branch delay slot. Do
-@@ -52,10 +49,10 @@ struct emuframe {
- mips_instruction emul;
- mips_instruction badinst;
- mips_instruction cookie;
-- gpreg_t epc;
-+ unsigned long epc;
- };
-
--int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
-+int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
- {
- extern asmlinkage void handle_dsemulret(void);
- mips_instruction *dsemul_insns;
-@@ -91,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mi
- */
-
- /* Ensure that the two instructions are in the same cache line */
-- dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
-+ dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
- fr = (struct emuframe *) dsemul_insns;
-
- /* Verify that the stack pointer is not competely insane */
-@@ -104,11 +101,11 @@ int mips_dsemul(struct pt_regs *regs, mi
- err |= __put_user(cpc, &fr->epc);
-
- if (unlikely(err)) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return SIGBUS;
- }
-
-- regs->cp0_epc = VA_TO_REG & fr->emul;
-+ regs->cp0_epc = (unsigned long) &fr->emul;
-
- flush_cache_sigtramp((unsigned long)&fr->badinst);
-
-@@ -118,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mi
- int do_dsemulret(struct pt_regs *xcp)
- {
- struct emuframe *fr;
-- gpreg_t epc;
-+ unsigned long epc;
- u32 insn, cookie;
- int err = 0;
-
-@@ -141,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp)
- err |= __get_user(cookie, &fr->cookie);
-
- if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
-- fpuemuprivate.stats.errors++;
-+ fpuemustats.errors++;
- return 0;
- }
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/dsemul.h linux_HEAD/arch/mips/math-emu/dsemul.h
---- linux-2.6.12/arch/mips/math-emu/dsemul.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/dsemul.h 2005-02-28 22:37:28.000000000 +0100
-@@ -1,11 +1,5 @@
--typedef long gpreg_t;
--typedef void *vaddr_t;
--
--#define REG_TO_VA (vaddr_t)
--#define VA_TO_REG (gpreg_t)
--
--int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc);
--int do_dsemulret(struct pt_regs *xcp);
-+extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
-+extern int do_dsemulret(struct pt_regs *xcp);
-
- /* Instruction which will always cause an address error */
- #define AdELOAD 0x8c000001 /* lw $0,1($0) */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/ieee754.c linux_HEAD/arch/mips/math-emu/ieee754.c
---- linux-2.6.12/arch/mips/math-emu/ieee754.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/ieee754.c 2005-04-30 15:33:39.000000000 +0200
-@@ -50,10 +50,6 @@ const char *const ieee754_cname[] = {
- "SNaN",
- };
-
--/* the control status register
--*/
--struct ieee754_csr ieee754_csr;
--
- /* special constants
- */
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/ieee754.h linux_HEAD/arch/mips/math-emu/ieee754.h
---- linux-2.6.12/arch/mips/math-emu/ieee754.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/ieee754.h 2005-04-30 15:33:39.000000000 +0200
-@@ -1,13 +1,8 @@
--/* single and double precision fp ops
-- * missing extended precision.
--*/
- /*
- * MIPS floating point support
- * Copyright (C) 1994-2000 Algorithmics Ltd.
- * http://www.algor.co.uk
- *
-- * ########################################################################
-- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
-@@ -21,20 +16,16 @@
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
-- * ########################################################################
-- */
--
--/**************************************************************************
- * Nov 7, 2000
- * Modification to allow integration with Linux kernel
- *
- * Kevin D. Kissell, kevink at mips.com and Carsten Langgard, carstenl at mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
-- *************************************************************************/
-+ */
-
--#ifdef __KERNEL__
--/* Going from Algorithmics to Linux native environment, add this */
-+#include <asm/byteorder.h>
- #include <linux/types.h>
-+#include <linux/sched.h>
-
- /*
- * Not very pretty, but the Linux kernel's normal va_list definition
-@@ -44,18 +35,7 @@
- #include <stdarg.h>
- #endif
-
--#else
--
--/* Note that __KERNEL__ is taken to mean Linux kernel */
--
--#if #system(OpenBSD)
--#include <machine/types.h>
--#endif
--#include <machine/endian.h>
--
--#endif /* __KERNEL__ */
--
--#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
-+#ifdef __LITTLE_ENDIAN
- struct ieee754dp_konst {
- unsigned mantlo:32;
- unsigned manthi:20;
-@@ -86,13 +66,14 @@ typedef union _ieee754sp {
- } ieee754sp;
- #endif
-
--#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__)
-+#ifdef __BIG_ENDIAN
- struct ieee754dp_konst {
- unsigned sign:1;
- unsigned bexp:11;
- unsigned manthi:20;
- unsigned mantlo:32;
- };
-+
- typedef union _ieee754dp {
- struct ieee754dp_konst oparts;
- struct {
-@@ -251,93 +232,109 @@ extern const char *const ieee754_cname[]
-
- /* "normal" comparisons
- */
--static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_eq(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y, IEEE754_CEQ, 0);
- }
-
--static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_ne(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y,
- IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
- }
-
--static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_lt(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y, IEEE754_CLT, 0);
- }
-
--static __inline int ieee754sp_le(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_le(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
- }
-
--static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_gt(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y, IEEE754_CGT, 0);
- }
-
-
--static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y)
-+static inline int ieee754sp_ge(ieee754sp x, ieee754sp y)
- {
- return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
- }
-
--static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_eq(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y, IEEE754_CEQ, 0);
- }
-
--static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_ne(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y,
- IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
- }
-
--static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_lt(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y, IEEE754_CLT, 0);
- }
-
--static __inline int ieee754dp_le(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_le(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
- }
-
--static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_gt(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y, IEEE754_CGT, 0);
- }
-
--static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y)
-+static inline int ieee754dp_ge(ieee754dp x, ieee754dp y)
- {
- return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
- }
-
-
--/* like strtod
--*/
-+/*
-+ * Like strtod
-+ */
- ieee754dp ieee754dp_fstr(const char *s, char **endp);
- char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af);
-
-
--/* the control status register
--*/
--struct ieee754_csr {
-- unsigned pad:13;
-+/*
-+ * The control status register
-+ */
-+struct _ieee754_csr {
-+#ifdef __BIG_ENDIAN
-+ unsigned pad0:7;
- unsigned nod:1; /* set 1 for no denormalised numbers */
-- unsigned cx:5; /* exceptions this operation */
-+ unsigned c:1; /* condition */
-+ unsigned pad1:5;
-+ unsigned cx:6; /* exceptions this operation */
- unsigned mx:5; /* exception enable mask */
- unsigned sx:5; /* exceptions total */
- unsigned rm:2; /* current rounding mode */
-+#endif
-+#ifdef __LITTLE_ENDIAN
-+ unsigned rm:2; /* current rounding mode */
-+ unsigned sx:5; /* exceptions total */
-+ unsigned mx:5; /* exception enable mask */
-+ unsigned cx:6; /* exceptions this operation */
-+ unsigned pad1:5;
-+ unsigned c:1; /* condition */
-+ unsigned nod:1; /* set 1 for no denormalised numbers */
-+ unsigned pad0:7;
-+#endif
- };
--extern struct ieee754_csr ieee754_csr;
-+#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.soft.fcr31))
-
--static __inline unsigned ieee754_getrm(void)
-+static inline unsigned ieee754_getrm(void)
- {
- return (ieee754_csr.rm);
- }
--static __inline unsigned ieee754_setrm(unsigned rm)
-+static inline unsigned ieee754_setrm(unsigned rm)
- {
- return (ieee754_csr.rm = rm);
- }
-@@ -345,14 +342,14 @@ static __inline unsigned ieee754_setrm(u
- /*
- * get current exceptions
- */
--static __inline unsigned ieee754_getcx(void)
-+static inline unsigned ieee754_getcx(void)
- {
- return (ieee754_csr.cx);
- }
-
- /* test for current exception condition
- */
--static __inline int ieee754_cxtest(unsigned n)
-+static inline int ieee754_cxtest(unsigned n)
- {
- return (ieee754_csr.cx & n);
- }
-@@ -360,21 +357,21 @@ static __inline int ieee754_cxtest(unsig
- /*
- * get sticky exceptions
- */
--static __inline unsigned ieee754_getsx(void)
-+static inline unsigned ieee754_getsx(void)
- {
- return (ieee754_csr.sx);
- }
-
- /* clear sticky conditions
- */
--static __inline unsigned ieee754_clrsx(void)
-+static inline unsigned ieee754_clrsx(void)
- {
- return (ieee754_csr.sx = 0);
- }
-
- /* test for sticky exception condition
- */
--static __inline int ieee754_sxtest(unsigned n)
-+static inline int ieee754_sxtest(unsigned n)
- {
- return (ieee754_csr.sx & n);
- }
-@@ -406,52 +403,34 @@ extern const struct ieee754sp_konst __ie
- #define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals)
- #define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals)
-
--/* return infinity with given sign
--*/
--#define ieee754dp_inf(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
--#define ieee754dp_zero(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
--#define ieee754dp_one(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
--#define ieee754dp_ten(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
--#define ieee754dp_indef() \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF])
--#define ieee754dp_max(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
--#define ieee754dp_min(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
--#define ieee754dp_mind(sn) \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
--#define ieee754dp_1e31() \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31])
--#define ieee754dp_1e63() \
-- (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63])
--
--#define ieee754sp_inf(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
--#define ieee754sp_zero(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
--#define ieee754sp_one(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
--#define ieee754sp_ten(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
--#define ieee754sp_indef() \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])
--#define ieee754sp_max(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
--#define ieee754sp_min(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
--#define ieee754sp_mind(sn) \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
--#define ieee754sp_1e31() \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31])
--#define ieee754sp_1e63() \
-- (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63])
-+/*
-+ * Return infinity with given sign
-+ */
-+#define ieee754dp_inf(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
-+#define ieee754dp_zero(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
-+#define ieee754dp_one(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
-+#define ieee754dp_ten(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
-+#define ieee754dp_indef() (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF])
-+#define ieee754dp_max(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
-+#define ieee754dp_min(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
-+#define ieee754dp_mind(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
-+#define ieee754dp_1e31() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31])
-+#define ieee754dp_1e63() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63])
-+
-+#define ieee754sp_inf(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
-+#define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
-+#define ieee754sp_one(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
-+#define ieee754sp_ten(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
-+#define ieee754sp_indef() (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])
-+#define ieee754sp_max(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
-+#define ieee754sp_min(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
-+#define ieee754sp_mind(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
-+#define ieee754sp_1e31() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31])
-+#define ieee754sp_1e63() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63])
-
--/* indefinite integer value
--*/
-+/*
-+ * Indefinite integer value
-+ */
- #define ieee754si_indef() INT_MAX
- #ifdef LONG_LONG_MAX
- #define ieee754di_indef() LONG_LONG_MAX
-diff -urpNX dontdiff linux-2.6.12/arch/mips/math-emu/kernel_linkage.c linux_HEAD/arch/mips/math-emu/kernel_linkage.c
---- linux-2.6.12/arch/mips/math-emu/kernel_linkage.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/math-emu/kernel_linkage.c 2005-05-14 14:38:21.000000000 +0200
-@@ -27,8 +27,6 @@
-
- #include <asm/fpu_emulator.h>
-
--extern struct mips_fpu_emulator_private fpuemuprivate;
--
- #define SIGNALLING_NAN 0x7ff800007ff80000LL
-
- void fpu_emulator_init_fpu(void)
-@@ -65,7 +63,6 @@ int fpu_emulator_save_context(struct sig
- &sc->sc_fpregs[i]);
- }
- err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-- err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
-
- return err;
- }
-@@ -81,7 +78,6 @@ int fpu_emulator_restore_context(struct
- &sc->sc_fpregs[i]);
- }
- err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-- err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
-
- return err;
- }
-@@ -102,7 +98,6 @@ int fpu_emulator_save_context32(struct s
- &sc->sc_fpregs[i]);
- }
- err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-- err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
-
- return err;
- }
-@@ -118,7 +113,6 @@ int fpu_emulator_restore_context32(struc
- &sc->sc_fpregs[i]);
- }
- err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-- err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir);
-
- return err;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/atlas/atlas_int.c linux_HEAD/arch/mips/mips-boards/atlas/atlas_int.c
---- linux-2.6.12/arch/mips/mips-boards/atlas/atlas_int.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/atlas/atlas_int.c 2005-02-28 16:56:42.000000000 +0100
-@@ -76,14 +76,13 @@ static void end_atlas_irq(unsigned int i
- }
-
- static struct hw_interrupt_type atlas_irq_type = {
-- "Atlas",
-- startup_atlas_irq,
-- shutdown_atlas_irq,
-- enable_atlas_irq,
-- disable_atlas_irq,
-- mask_and_ack_atlas_irq,
-- end_atlas_irq,
-- NULL
-+ .typename = "Atlas",
-+ .startup = startup_atlas_irq,
-+ .shutdown = shutdown_atlas_irq,
-+ .enable = enable_atlas_irq,
-+ .disable = disable_atlas_irq,
-+ .ack = mask_and_ack_atlas_irq,
-+ .end = end_atlas_irq,
- };
-
- static inline int ls1bit32(unsigned int x)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/atlas/atlas_setup.c linux_HEAD/arch/mips/mips-boards/atlas/atlas_setup.c
---- linux-2.6.12/arch/mips/mips-boards/atlas/atlas_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/atlas/atlas_setup.c 2005-07-01 12:09:18.000000000 +0200
-@@ -50,8 +50,10 @@ const char *get_system_type(void)
- return "MIPS Atlas";
- }
-
--static int __init atlas_setup(void)
-+void __init plat_setup(void)
- {
-+ mips_pcibios_init();
-+
- ioport_resource.end = 0x7fffffff;
-
- serial_init ();
-@@ -64,12 +66,8 @@ static int __init atlas_setup(void)
- board_time_init = mips_time_init;
- board_timer_setup = mips_timer_setup;
- rtc_get_time = mips_rtc_get_time;
--
-- return 0;
- }
-
--early_initcall(atlas_setup);
--
- static void __init serial_init(void)
- {
- #ifdef CONFIG_SERIAL_8250
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/generic/init.c linux_HEAD/arch/mips/mips-boards/generic/init.c
---- linux-2.6.12/arch/mips/mips-boards/generic/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/generic/init.c 2005-02-17 21:48:56.000000000 +0100
-@@ -1,6 +1,8 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
-+ * All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -22,18 +24,17 @@
- #include <linux/string.h>
- #include <linux/kernel.h>
-
--#include <asm/io.h>
- #include <asm/bootinfo.h>
-+#include <asm/gt64120.h>
-+#include <asm/io.h>
-+#include <asm/system.h>
-+
- #include <asm/mips-boards/prom.h>
- #include <asm/mips-boards/generic.h>
--#ifdef CONFIG_MIPS_GT64120
--#include <asm/gt64120.h>
--#endif
--#include <asm/mips-boards/msc01_pci.h>
- #include <asm/mips-boards/bonito64.h>
--#ifdef CONFIG_MIPS_MALTA
-+#include <asm/mips-boards/msc01_pci.h>
-+
- #include <asm/mips-boards/malta.h>
--#endif
-
- #ifdef CONFIG_KGDB
- extern int rs_kgdb_hook(int, int);
-@@ -225,6 +226,8 @@ void __init kgdb_config (void)
-
- void __init prom_init(void)
- {
-+ u32 start, map, mask, data;
-+
- prom_argc = fw_arg0;
- _prom_argv = (int *) fw_arg1;
- _prom_envp = (int *) fw_arg2;
-@@ -266,12 +269,15 @@ void __init prom_init(void)
- #else
- GT_WRITE(GT_PCI0_CMD_OFS, 0);
- #endif
-+ /* Fix up PCI I/O mapping if necessary (for Atlas). */
-+ start = GT_READ(GT_PCI0IOLD_OFS);
-+ map = GT_READ(GT_PCI0IOREMAP_OFS);
-+ if ((start & map) != 0) {
-+ map &= ~start;
-+ GT_WRITE(GT_PCI0IOREMAP_OFS, map);
-+ }
-
--#ifdef CONFIG_MIPS_MALTA
- set_io_port_base(MALTA_GT_PORT_BASE);
--#else
-- set_io_port_base((unsigned long)ioremap(0, 0x20000000));
--#endif
- break;
-
- case MIPS_REVISION_CORID_CORE_EMUL_BON:
-@@ -300,11 +306,7 @@ void __init prom_init(void)
- BONITO_BONGENCFG_BYTESWAP;
- #endif
-
--#ifdef CONFIG_MIPS_MALTA
- set_io_port_base(MALTA_BONITO_PORT_BASE);
--#else
-- set_io_port_base((unsigned long)ioremap(0, 0x20000000));
--#endif
- break;
-
- case MIPS_REVISION_CORID_CORE_MSC:
-@@ -312,6 +314,12 @@ void __init prom_init(void)
- case MIPS_REVISION_CORID_CORE_EMUL_MSC:
- _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
-
-+ mb();
-+ MSC_READ(MSC01_PCI_CFG, data);
-+ MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
-+ wmb();
-+
-+ /* Fix up lane swapping. */
- #ifdef CONFIG_CPU_LITTLE_ENDIAN
- MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
- #else
-@@ -320,12 +328,23 @@ void __init prom_init(void)
- MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
- MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
- #endif
-+ /* Fix up target memory mapping. */
-+ MSC_READ(MSC01_PCI_BAR0, mask);
-+ MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
-+
-+ /* Don't handle target retries indefinitely. */
-+ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
-+ MSC01_PCI_CFG_MAXRTRY_MSK)
-+ data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
-+ MSC01_PCI_CFG_MAXRTRY_SHF)) |
-+ ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
-+ MSC01_PCI_CFG_MAXRTRY_SHF);
-+
-+ wmb();
-+ MSC_WRITE(MSC01_PCI_CFG, data);
-+ mb();
-
--#ifdef CONFIG_MIPS_MALTA
- set_io_port_base(MALTA_MSC_PORT_BASE);
--#else
-- set_io_port_base((unsigned long)ioremap(0, 0x20000000));
--#endif
- break;
-
- default:
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/generic/pci.c linux_HEAD/arch/mips/mips-boards/generic/pci.c
---- linux-2.6.12/arch/mips/mips-boards/generic/pci.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/generic/pci.c 2005-07-01 12:09:18.000000000 +0200
-@@ -1,6 +1,8 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
-+ * All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf at linux-mips.org)
- *
-@@ -19,65 +21,46 @@
- *
- * MIPS boards specific PCI support.
- */
--#include <linux/config.h>
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-
--#include <asm/mips-boards/generic.h>
- #include <asm/gt64120.h>
-+
-+#include <asm/mips-boards/generic.h>
- #include <asm/mips-boards/bonito64.h>
- #include <asm/mips-boards/msc01_pci.h>
--#ifdef CONFIG_MIPS_MALTA
--#include <asm/mips-boards/malta.h>
--#endif
-
- static struct resource bonito64_mem_resource = {
- .name = "Bonito PCI MEM",
-- .start = 0x10000000UL,
-- .end = 0x1bffffffUL,
- .flags = IORESOURCE_MEM,
- };
-
- static struct resource bonito64_io_resource = {
-- .name = "Bonito IO MEM",
-- .start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */
-+ .name = "Bonito PCI I/O",
-+ .start = 0x00000000UL,
- .end = 0x000fffffUL,
- .flags = IORESOURCE_IO,
- };
-
- static struct resource gt64120_mem_resource = {
-- .name = "GT64120 PCI MEM",
-- .start = 0x10000000UL,
-- .end = 0x1bdfffffUL,
-+ .name = "GT-64120 PCI MEM",
- .flags = IORESOURCE_MEM,
- };
-
- static struct resource gt64120_io_resource = {
-- .name = "GT64120 IO MEM",
--#ifdef CONFIG_MIPS_ATLAS
-- .start = 0x18000000UL,
-- .end = 0x181fffffUL,
--#endif
--#ifdef CONFIG_MIPS_MALTA
-- .start = 0x00002000UL,
-- .end = 0x001fffffUL,
--#endif
-+ .name = "GT-64120 PCI I/O",
- .flags = IORESOURCE_IO,
- };
-
- static struct resource msc_mem_resource = {
- .name = "MSC PCI MEM",
-- .start = 0x10000000UL,
-- .end = 0x1fffffffUL,
- .flags = IORESOURCE_MEM,
- };
-
- static struct resource msc_io_resource = {
-- .name = "MSC IO MEM",
-- .start = 0x00002000UL,
-- .end = 0x007fffffUL,
-+ .name = "MSC PCI I/O",
- .flags = IORESOURCE_IO,
- };
-
-@@ -89,7 +72,6 @@ static struct pci_controller bonito64_co
- .pci_ops = &bonito64_pci_ops,
- .io_resource = &bonito64_io_resource,
- .mem_resource = &bonito64_mem_resource,
-- .mem_offset = 0x10000000UL,
- .io_offset = 0x00000000UL,
- };
-
-@@ -97,21 +79,18 @@ static struct pci_controller gt64120_con
- .pci_ops = >64120_pci_ops,
- .io_resource = >64120_io_resource,
- .mem_resource = >64120_mem_resource,
-- .mem_offset = 0x00000000UL,
-- .io_offset = 0x00000000UL,
- };
-
--static struct pci_controller msc_controller = {
-+static struct pci_controller msc_controller = {
- .pci_ops = &msc_pci_ops,
- .io_resource = &msc_io_resource,
- .mem_resource = &msc_mem_resource,
-- .mem_offset = 0x10000000UL,
-- .io_offset = 0x00000000UL,
- };
-
--static int __init pcibios_init(void)
-+void __init mips_pcibios_init(void)
- {
- struct pci_controller *controller;
-+ unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
-
- switch (mips_revision_corid) {
- case MIPS_REVISION_CORID_QED_RM5261:
-@@ -130,34 +109,139 @@ static int __init pcibios_init(void)
- (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
- (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
- ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
-- GT_PCI0_CFGADDR_CONFIGEN_BIT );
-+ GT_PCI0_CFGADDR_CONFIGEN_BIT);
-
- /* Perform the write */
- GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
-
-+ /* Set up resource ranges from the controller's registers. */
-+ start = GT_READ(GT_PCI0M0LD_OFS);
-+ end = GT_READ(GT_PCI0M0HD_OFS);
-+ map = GT_READ(GT_PCI0M0REMAP_OFS);
-+ end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
-+ start1 = GT_READ(GT_PCI0M1LD_OFS);
-+ end1 = GT_READ(GT_PCI0M1HD_OFS);
-+ map1 = GT_READ(GT_PCI0M1REMAP_OFS);
-+ end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
-+ /* Cannot support multiple windows, use the wider. */
-+ if (end1 - start1 > end - start) {
-+ start = start1;
-+ end = end1;
-+ map = map1;
-+ }
-+ mask = ~(start ^ end);
-+ /* We don't support remapping with a discontiguous mask. */
-+ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
-+ mask != ~((mask & -mask) - 1));
-+ gt64120_mem_resource.start = start;
-+ gt64120_mem_resource.end = end;
-+ gt64120_controller.mem_offset = (start & mask) - (map & mask);
-+ /* Addresses are 36-bit, so do shifts in the destinations. */
-+ gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
-+ gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
-+ gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
-+ gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
-+
-+ start = GT_READ(GT_PCI0IOLD_OFS);
-+ end = GT_READ(GT_PCI0IOHD_OFS);
-+ map = GT_READ(GT_PCI0IOREMAP_OFS);
-+ end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
-+ mask = ~(start ^ end);
-+ /* We don't support remapping with a discontiguous mask. */
-+ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
-+ mask != ~((mask & -mask) - 1));
-+ gt64120_io_resource.start = map & mask;
-+ gt64120_io_resource.end = (map & mask) | ~mask;
-+ gt64120_controller.io_offset = 0;
-+ /* Addresses are 36-bit, so do shifts in the destinations. */
-+ gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
-+ gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
-+ gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
-+
- controller = >64120_controller;
- break;
-
- case MIPS_REVISION_CORID_BONITO64:
- case MIPS_REVISION_CORID_CORE_20K:
- case MIPS_REVISION_CORID_CORE_EMUL_BON:
-+ /* Set up resource ranges from the controller's registers. */
-+ map = BONITO_PCIMAP;
-+ map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
-+ BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
-+ map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
-+ BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
-+ map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
-+ BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
-+ /* Combine as many adjacent windows as possible. */
-+ map = map1;
-+ start = BONITO_PCILO0_BASE;
-+ end = 1;
-+ if (map3 == map2 + 1) {
-+ map = map2;
-+ start = BONITO_PCILO1_BASE;
-+ end++;
-+ }
-+ if (map2 == map1 + 1) {
-+ map = map1;
-+ start = BONITO_PCILO0_BASE;
-+ end++;
-+ }
-+ bonito64_mem_resource.start = start;
-+ bonito64_mem_resource.end = start +
-+ BONITO_PCIMAP_WINBASE(end) - 1;
-+ bonito64_controller.mem_offset = start -
-+ BONITO_PCIMAP_WINBASE(map);
-+
- controller = &bonito64_controller;
- break;
-
- case MIPS_REVISION_CORID_CORE_MSC:
- case MIPS_REVISION_CORID_CORE_FPGA2:
- case MIPS_REVISION_CORID_CORE_EMUL_MSC:
-+ /* Set up resource ranges from the controller's registers. */
-+ MSC_READ(MSC01_PCI_SC2PMBASL, start);
-+ MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
-+ MSC_READ(MSC01_PCI_SC2PMMAPL, map);
-+ msc_mem_resource.start = start & mask;
-+ msc_mem_resource.end = (start & mask) | ~mask;
-+ msc_controller.mem_offset = (start & mask) - (map & mask);
-+
-+ MSC_READ(MSC01_PCI_SC2PIOBASL, start);
-+ MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
-+ MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
-+ msc_io_resource.start = map & mask;
-+ msc_io_resource.end = (map & mask) | ~mask;
-+ msc_controller.io_offset = 0;
-+ ioport_resource.end = ~mask;
-+
-+ /* If ranges overlap I/O takes precedence. */
-+ start = start & mask;
-+ end = start | ~mask;
-+ if ((start >= msc_mem_resource.start &&
-+ start <= msc_mem_resource.end) ||
-+ (end >= msc_mem_resource.start &&
-+ end <= msc_mem_resource.end)) {
-+ /* Use the larger space. */
-+ start = max(start, msc_mem_resource.start);
-+ end = min(end, msc_mem_resource.end);
-+ if (start - msc_mem_resource.start >=
-+ msc_mem_resource.end - end)
-+ msc_mem_resource.end = start - 1;
-+ else
-+ msc_mem_resource.start = end + 1;
-+ }
-+
- controller = &msc_controller;
- break;
- default:
-- return 1;
-+ return;
- }
-
-+ if (controller->io_resource->start < 0x00001000UL) /* FIXME */
-+ controller->io_resource->start = 0x00001000UL;
-+
-+ iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
- ioport_resource.end = controller->io_resource->end;
-
- register_pci_controller (controller);
--
-- return 0;
- }
--
--early_initcall(pcibios_init);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/malta/malta_setup.c linux_HEAD/arch/mips/mips-boards/malta/malta_setup.c
---- linux-2.6.12/arch/mips/mips-boards/malta/malta_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/malta/malta_setup.c 2005-07-01 12:09:18.000000000 +0200
-@@ -111,10 +111,12 @@ void __init fd_activate(void)
- }
- #endif
-
--static int __init malta_setup(void)
-+void __init plat_setup(void)
- {
- unsigned int i;
-
-+ mips_pcibios_init();
-+
- /* Request I/O space for devices used on the Malta board. */
- for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
- request_resource(&ioport_resource, standard_io_resources+i);
-@@ -224,8 +226,4 @@ static int __init malta_setup(void)
- board_time_init = mips_time_init;
- board_timer_setup = mips_timer_setup;
- rtc_get_time = mips_rtc_get_time;
--
-- return 0;
- }
--
--early_initcall(malta_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/sead/sead_int.c linux_HEAD/arch/mips/mips-boards/sead/sead_int.c
---- linux-2.6.12/arch/mips/mips-boards/sead/sead_int.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/sead/sead_int.c 2005-02-17 21:48:56.000000000 +0100
-@@ -2,6 +2,7 @@
- * Carsten Langgaard, carstenl at mips.com
- * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
- * Copyright (C) 2003 Ralf Baechle (ralf at linux-mips.org)
-+ * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -21,7 +22,9 @@
- */
- #include <linux/init.h>
- #include <linux/irq.h>
--#include <linux/interrupt.h>
-+
-+#include <asm/irq_cpu.h>
-+#include <asm/system.h>
-
- #include <asm/mips-boards/seadint.h>
-
-@@ -39,13 +42,8 @@ asmlinkage void sead_hw1_irqdispatch(str
-
- void __init arch_init_irq(void)
- {
-- /*
-- * Mask out all interrupt
-- */
-- clear_c0_status(0x0000ff00);
-+ mips_cpu_irq_init(0);
-
- /* Now safe to set the exception vector. */
- set_except_vector(0, mipsIRQ);
--
-- mips_cpu_irq_init(0);
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mips-boards/sead/sead_setup.c linux_HEAD/arch/mips/mips-boards/sead/sead_setup.c
---- linux-2.6.12/arch/mips/mips-boards/sead/sead_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mips-boards/sead/sead_setup.c 2005-07-01 12:09:18.000000000 +0200
-@@ -57,8 +57,6 @@ static void __init sead_setup(void)
- mips_reboot_setup();
- }
-
--early_initcall(sead_setup);
--
- static void __init serial_init(void)
- {
- #ifdef CONFIG_SERIAL_8250
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/Makefile linux_HEAD/arch/mips/mm/Makefile
---- linux-2.6.12/arch/mips/mm/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/Makefile 2005-07-07 11:22:49.000000000 +0200
-@@ -9,8 +9,8 @@ obj-$(CONFIG_MIPS32) += ioremap.o pgtab
- obj-$(CONFIG_MIPS64) += pgtable-64.o
- obj-$(CONFIG_HIGHMEM) += highmem.o
-
--obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
--obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
-+obj-$(CONFIG_CPU_MIPS32_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
-+obj-$(CONFIG_CPU_MIPS64_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
- obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
- obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o
- obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/c-r3k.c linux_HEAD/arch/mips/mm/c-r3k.c
---- linux-2.6.12/arch/mips/mm/c-r3k.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/c-r3k.c 2005-07-01 12:09:18.000000000 +0200
-@@ -221,12 +221,14 @@ static inline unsigned long get_phys_pag
- struct mm_struct *mm)
- {
- pgd_t *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned long physpage;
-
- pgd = pgd_offset(mm, addr);
-- pmd = pmd_offset(pgd, addr);
-+ pud = pud_offset(pgd, addr);
-+ pmd = pmd_offset(pud, addr);
- pte = pte_offset(pmd, addr);
-
- if ((physpage = pte_val(*pte)) & _PAGE_VALID)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/c-r4k.c linux_HEAD/arch/mips/mm/c-r4k.c
---- linux-2.6.12/arch/mips/mm/c-r4k.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/c-r4k.c 2005-07-10 12:16:57.000000000 +0200
-@@ -26,6 +26,7 @@
- #include <asm/system.h>
- #include <asm/mmu_context.h>
- #include <asm/war.h>
-+#include <asm/cacheflush.h> /* for run_uncached() */
-
- static unsigned long icache_size, dcache_size, scache_size;
-
-@@ -372,12 +373,21 @@ static inline void local_r4k_flush_cache
- int exec = vma->vm_flags & VM_EXEC;
- struct mm_struct *mm = vma->vm_mm;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
-
-+ /*
-+ * If ownes no valid ASID yet, cannot possibly have gotten
-+ * this page into the cache.
-+ */
-+ if (cpu_context(smp_processor_id(), mm) == 0)
-+ return;
-+
- page &= PAGE_MASK;
- pgdp = pgd_offset(mm, page);
-- pmdp = pmd_offset(pgdp, page);
-+ pudp = pud_offset(pgdp, page);
-+ pmdp = pmd_offset(pudp, page);
- ptep = pte_offset(pmdp, page);
-
- /*
-@@ -419,8 +429,8 @@ static inline void local_r4k_flush_cache
- if (cpu_has_vtag_icache) {
- int cpu = smp_processor_id();
-
-- if (cpu_context(cpu, vma->vm_mm) != 0)
-- drop_mmu_context(vma->vm_mm, cpu);
-+ if (cpu_context(cpu, mm) != 0)
-+ drop_mmu_context(mm, cpu);
- } else
- r4k_blast_icache_page_indexed(page);
- }
-@@ -430,13 +440,6 @@ static void r4k_flush_cache_page(struct
- {
- struct flush_cache_page_args args;
-
-- /*
-- * If ownes no valid ASID yet, cannot possibly have gotten
-- * this page into the cache.
-- */
-- if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
-- return;
--
- args.vma = vma;
- args.page = page;
-
-@@ -454,8 +457,8 @@ static void r4k_flush_data_cache_page(un
- }
-
- struct flush_icache_range_args {
-- unsigned long start;
-- unsigned long end;
-+ unsigned long __user start;
-+ unsigned long __user end;
- };
-
- static inline void local_r4k_flush_icache_range(void *args)
-@@ -517,7 +520,8 @@ static inline void local_r4k_flush_icach
- }
- }
-
--static void r4k_flush_icache_range(unsigned long start, unsigned long end)
-+static void r4k_flush_icache_range(unsigned long __user start,
-+ unsigned long __user end)
- {
- struct flush_icache_range_args args;
-
-@@ -1011,9 +1015,19 @@ static void __init probe_pcache(void)
- * normally they'd suffer from aliases but magic in the hardware deals
- * with that for us so we don't need to take care ourselves.
- */
-- if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
-- if (c->dcache.waysize > PAGE_SIZE)
-- c->dcache.flags |= MIPS_CACHE_ALIASES;
-+ switch (c->cputype) {
-+ case CPU_20KC:
-+ case CPU_25KF:
-+ case CPU_R10000:
-+ case CPU_R12000:
-+ case CPU_SB1:
-+ break;
-+ case CPU_24K:
-+ if (!(read_c0_config7() & (1 << 16)))
-+ default:
-+ if (c->dcache.waysize > PAGE_SIZE)
-+ c->dcache.flags |= MIPS_CACHE_ALIASES;
-+ }
-
- switch (c->cputype) {
- case CPU_20KC:
-@@ -1024,7 +1038,11 @@ static void __init probe_pcache(void)
- c->icache.flags |= MIPS_CACHE_VTAG;
- break;
-
-+ case CPU_AU1000:
- case CPU_AU1500:
-+ case CPU_AU1100:
-+ case CPU_AU1550:
-+ case CPU_AU1200:
- c->icache.flags |= MIPS_CACHE_IC_F_DC;
- break;
- }
-@@ -1102,7 +1120,6 @@ static int __init probe_scache(void)
- return 1;
- }
-
--typedef int (*probe_func_t)(unsigned long);
- extern int r5k_sc_init(void);
- extern int rm7k_sc_init(void);
-
-@@ -1110,7 +1127,6 @@ static void __init setup_scache(void)
- {
- struct cpuinfo_mips *c = ¤t_cpu_data;
- unsigned int config = read_c0_config();
-- probe_func_t probe_scache_kseg1;
- int sc_present = 0;
-
- /*
-@@ -1123,8 +1139,7 @@ static void __init setup_scache(void)
- case CPU_R4000MC:
- case CPU_R4400SC:
- case CPU_R4400MC:
-- probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
-- sc_present = probe_scache_kseg1(config);
-+ sc_present = run_uncached(probe_scache);
- if (sc_present)
- c->options |= MIPS_CPU_CACHE_CDEX_S;
- break;
-@@ -1212,9 +1227,6 @@ void __init ld_mmu_r4xx0(void)
- probe_pcache();
- setup_scache();
-
-- if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
-- c->dcache.flags |= MIPS_CACHE_ALIASES;
--
- r4k_blast_dcache_page_setup();
- r4k_blast_dcache_page_indexed_setup();
- r4k_blast_dcache_setup();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/c-sb1.c linux_HEAD/arch/mips/mm/c-sb1.c
---- linux-2.6.12/arch/mips/mm/c-sb1.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/c-sb1.c 2005-03-21 20:03:46.000000000 +0100
-@@ -235,7 +235,7 @@ static inline void __sb1_flush_icache_ra
- /*
- * Invalidate all caches on this CPU
- */
--static void local_sb1___flush_cache_all(void)
-+static void __attribute_used__ local_sb1___flush_cache_all(void)
- {
- __sb1_writeback_inv_dcache_all();
- __sb1_flush_icache_all();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/c-tx39.c linux_HEAD/arch/mips/mm/c-tx39.c
---- linux-2.6.12/arch/mips/mm/c-tx39.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/c-tx39.c 2005-07-10 12:16:57.000000000 +0200
-@@ -183,6 +183,7 @@ static void tx39_flush_cache_page(struct
- int exec = vma->vm_flags & VM_EXEC;
- struct mm_struct *mm = vma->vm_mm;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
-
-@@ -195,7 +196,8 @@ static void tx39_flush_cache_page(struct
-
- page &= PAGE_MASK;
- pgdp = pgd_offset(mm, page);
-- pmdp = pmd_offset(pgdp, page);
-+ pudp = pud_offset(pgdp, page);
-+ pmdp = pmd_offset(pudp, page);
- ptep = pte_offset(pmdp, page);
-
- /*
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/cache.c linux_HEAD/arch/mips/mm/cache.c
---- linux-2.6.12/arch/mips/mm/cache.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/cache.c 2005-07-07 11:22:49.000000000 +0200
-@@ -23,8 +23,10 @@ void (*__flush_cache_all)(void);
- void (*flush_cache_mm)(struct mm_struct *mm);
- void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
--void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--void (*flush_icache_range)(unsigned long start, unsigned long end);
-+void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
-+ unsigned long pfn);
-+void (*flush_icache_range)(unsigned long __user start,
-+ unsigned long __user end);
- void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
-
- /* MIPS specific cache operations */
-@@ -32,6 +34,8 @@ void (*flush_cache_sigtramp)(unsigned lo
- void (*flush_data_cache_page)(unsigned long addr);
- void (*flush_icache_all)(void);
-
-+EXPORT_SYMBOL(flush_data_cache_page);
-+
- #ifdef CONFIG_DMA_NONCOHERENT
-
- /* DMA cache operations. */
-@@ -49,10 +53,10 @@ EXPORT_SYMBOL(_dma_cache_inv);
- * We could optimize the case where the cache argument is not BCACHE but
- * that seems very atypical use ...
- */
--asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes,
-- unsigned int cache)
-+asmlinkage int sys_cacheflush(unsigned long __user addr,
-+ unsigned long bytes, unsigned int cache)
- {
-- if (!access_ok(VERIFY_WRITE, (void *) addr, bytes))
-+ if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
- return -EFAULT;
-
- flush_icache_range(addr, addr + bytes);
-@@ -114,8 +118,8 @@ void __init cpu_cache_init(void)
- #if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
- defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
- defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
-- defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \
-- defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
-+ defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \
-+ defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
- defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
- ld_mmu_r4xx0();
- #endif
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/dma-coherent.c linux_HEAD/arch/mips/mm/dma-coherent.c
---- linux-2.6.12/arch/mips/mm/dma-coherent.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/dma-coherent.c 2005-04-14 16:40:13.000000000 +0200
-@@ -9,16 +9,16 @@
- */
- #include <linux/config.h>
- #include <linux/types.h>
-+#include <linux/dma-mapping.h>
- #include <linux/mm.h>
- #include <linux/module.h>
- #include <linux/string.h>
--#include <linux/pci.h>
-
- #include <asm/cache.h>
- #include <asm/io.h>
-
- void *dma_alloc_noncoherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
- /* ignore region specifiers */
-@@ -39,7 +39,7 @@ void *dma_alloc_noncoherent(struct devic
- EXPORT_SYMBOL(dma_alloc_noncoherent);
-
- void *dma_alloc_coherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- __attribute__((alias("dma_alloc_noncoherent")));
-
- EXPORT_SYMBOL(dma_alloc_coherent);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/dma-ip27.c linux_HEAD/arch/mips/mm/dma-ip27.c
---- linux-2.6.12/arch/mips/mm/dma-ip27.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/dma-ip27.c 2005-07-10 12:16:33.000000000 +0200
-@@ -22,7 +22,7 @@
- pdev_to_baddr(to_pci_dev(dev), (addr))
-
- void *dma_alloc_noncoherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
-
-@@ -44,7 +44,7 @@ void *dma_alloc_noncoherent(struct devic
- EXPORT_SYMBOL(dma_alloc_noncoherent);
-
- void *dma_alloc_coherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- __attribute__((alias("dma_alloc_noncoherent")));
-
- EXPORT_SYMBOL(dma_alloc_coherent);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/dma-ip32.c linux_HEAD/arch/mips/mm/dma-ip32.c
---- linux-2.6.12/arch/mips/mm/dma-ip32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/dma-ip32.c 2005-07-10 12:28:27.000000000 +0200
-@@ -37,7 +37,7 @@
- #define RAM_OFFSET_MASK 0x3fffffff
-
- void *dma_alloc_noncoherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
- /* ignore region specifiers */
-@@ -61,7 +61,7 @@ void *dma_alloc_noncoherent(struct devic
- EXPORT_SYMBOL(dma_alloc_noncoherent);
-
- void *dma_alloc_coherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/dma-noncoherent.c linux_HEAD/arch/mips/mm/dma-noncoherent.c
---- linux-2.6.12/arch/mips/mm/dma-noncoherent.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/dma-noncoherent.c 2005-04-08 22:40:41.000000000 +0200
-@@ -24,7 +24,7 @@
- */
-
- void *dma_alloc_noncoherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
- /* ignore region specifiers */
-@@ -45,7 +45,7 @@ void *dma_alloc_noncoherent(struct devic
- EXPORT_SYMBOL(dma_alloc_noncoherent);
-
- void *dma_alloc_coherent(struct device *dev, size_t size,
-- dma_addr_t * dma_handle, int gfp)
-+ dma_addr_t * dma_handle, unsigned int __nocast gfp)
- {
- void *ret;
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/fault.c linux_HEAD/arch/mips/mm/fault.c
---- linux-2.6.12/arch/mips/mm/fault.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/fault.c 2005-03-01 22:49:39.000000000 +0100
-@@ -25,6 +25,7 @@
- #include <asm/system.h>
- #include <asm/uaccess.h>
- #include <asm/ptrace.h>
-+#include <asm/highmem.h> /* For VMALLOC_END */
-
- /*
- * This routine handles page faults. It determines the address,
-@@ -57,7 +58,7 @@ asmlinkage void do_page_fault(struct pt_
- * only copy the information from the master page table,
- * nothing more.
- */
-- if (unlikely(address >= VMALLOC_START))
-+ if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
- goto vmalloc_fault;
-
- /*
-@@ -140,7 +141,7 @@ bad_area_nosemaphore:
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
-- info.si_addr = (void *) address;
-+ info.si_addr = (void __user *) address;
- force_sig_info(SIGSEGV, &info, tsk);
- return;
- }
-@@ -196,7 +197,7 @@ do_sigbus:
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
-- info.si_addr = (void *) address;
-+ info.si_addr = (void __user *) address;
- force_sig_info(SIGBUS, &info, tsk);
-
- return;
-@@ -212,6 +213,7 @@ vmalloc_fault:
- */
- int offset = __pgd_offset(address);
- pgd_t *pgd, *pgd_k;
-+ pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
-@@ -222,8 +224,13 @@ vmalloc_fault:
- goto no_context;
- set_pgd(pgd, *pgd_k);
-
-- pmd = pmd_offset(pgd, address);
-- pmd_k = pmd_offset(pgd_k, address);
-+ pud = pud_offset(pgd, address);
-+ pud_k = pud_offset(pgd_k, address);
-+ if (!pud_present(*pud_k))
-+ goto no_context;
-+
-+ pmd = pmd_offset(pud, address);
-+ pmd_k = pmd_offset(pud_k, address);
- if (!pmd_present(*pmd_k))
- goto no_context;
- set_pmd(pmd, *pmd_k);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/init.c linux_HEAD/arch/mips/mm/init.c
---- linux-2.6.12/arch/mips/mm/init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/init.c 2005-07-10 12:16:33.000000000 +0200
-@@ -83,7 +83,7 @@ pte_t *kmap_pte;
- pgprot_t kmap_prot;
-
- #define kmap_get_fixmap_pte(vaddr) \
-- pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr))
-+ pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
-
- static void __init kmap_init(void)
- {
-@@ -96,36 +96,42 @@ static void __init kmap_init(void)
- kmap_prot = PAGE_KERNEL;
- }
-
--#ifdef CONFIG_MIPS64
--static void __init fixrange_init(unsigned long start, unsigned long end,
-+#ifdef CONFIG_MIPS32
-+void __init fixrange_init(unsigned long start, unsigned long end,
- pgd_t *pgd_base)
- {
- pgd_t *pgd;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
-- int i, j;
-+ int i, j, k;
- unsigned long vaddr;
-
- vaddr = start;
- i = __pgd_offset(vaddr);
-- j = __pmd_offset(vaddr);
-+ j = __pud_offset(vaddr);
-+ k = __pmd_offset(vaddr);
- pgd = pgd_base + i;
-
- for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
-- pmd = (pmd_t *)pgd;
-- for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) {
-- if (pmd_none(*pmd)) {
-- pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-- set_pmd(pmd, __pmd(pte));
-- if (pte != pte_offset_kernel(pmd, 0))
-- BUG();
-+ pud = (pud_t *)pgd;
-+ for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
-+ pmd = (pmd_t *)pud;
-+ for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
-+ if (pmd_none(*pmd)) {
-+ pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-+ set_pmd(pmd, __pmd(pte));
-+ if (pte != pte_offset_kernel(pmd, 0))
-+ BUG();
-+ }
-+ vaddr += PMD_SIZE;
- }
-- vaddr += PMD_SIZE;
-+ k = 0;
- }
- j = 0;
- }
- }
--#endif /* CONFIG_MIPS64 */
-+#endif /* CONFIG_MIPS32 */
- #endif /* CONFIG_HIGHMEM */
-
- #ifndef CONFIG_DISCONTIGMEM
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/ioremap.c linux_HEAD/arch/mips/mm/ioremap.c
---- linux-2.6.12/arch/mips/mm/ioremap.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/ioremap.c 2005-07-01 12:09:18.000000000 +0200
-@@ -79,9 +79,14 @@ static int remap_area_pages(unsigned lon
- BUG();
- spin_lock(&init_mm.page_table_lock);
- do {
-+ pud_t *pud;
- pmd_t *pmd;
-- pmd = pmd_alloc(&init_mm, dir, address);
-+
- error = -ENOMEM;
-+ pud = pud_alloc(&init_mm, dir, address);
-+ if (!pud)
-+ break;
-+ pmd = pmd_alloc(&init_mm, pud, address);
- if (!pmd)
- break;
- if (remap_area_pmd(pmd, address, end - address,
-@@ -97,15 +102,6 @@ static int remap_area_pages(unsigned lon
- }
-
- /*
-- * Allow physical addresses to be fixed up to help 36 bit peripherals.
-- */
--phys_t __attribute__ ((weak))
--fixup_bigphys_addr(phys_t phys_addr, phys_t size)
--{
-- return phys_addr;
--}
--
--/*
- * Generic mapping function (not visible outside):
- */
-
-@@ -141,7 +137,7 @@ void * __ioremap(phys_t phys_addr, phys_
- */
- if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
- flags == _CACHE_UNCACHED)
-- return (void *) KSEG1ADDR(phys_addr);
-+ return (void *) CKSEG1ADDR(phys_addr);
-
- /*
- * Don't allow anybody to remap normal RAM that we're using..
-@@ -180,7 +176,7 @@ void * __ioremap(phys_t phys_addr, phys_
- return (void *) (offset + (char *)addr);
- }
-
--#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1)
-+#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
-
- void __iounmap(volatile void __iomem *addr)
- {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/pg-sb1.c linux_HEAD/arch/mips/mm/pg-sb1.c
---- linux-2.6.12/arch/mips/mm/pg-sb1.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/pg-sb1.c 2005-04-05 06:42:28.000000000 +0200
-@@ -60,7 +60,8 @@ static inline void clear_page_cpu(void *
- " .set noreorder \n"
- #ifdef CONFIG_CPU_HAS_PREFETCH
- " daddiu %0, %0, 128 \n"
-- " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */
-+ " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n"
-+ /* Prefetch the first 4 lines */
- " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n"
- " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n"
- " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
-@@ -106,7 +107,8 @@ static inline void copy_page_cpu(void *t
- #ifdef CONFIG_CPU_HAS_PREFETCH
- " daddiu %0, %0, 128 \n"
- " daddiu %1, %1, 128 \n"
-- " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */
-+ " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n"
-+ /* Prefetch the first 4 lines */
- " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n"
- " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n"
- " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n"
-@@ -207,66 +209,73 @@ typedef struct dmadscr_s {
- u64 pad_b;
- } dmadscr_t;
-
--static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES)));
-+static dmadscr_t page_descr[DM_NUM_CHANNELS]
-+ __attribute__((aligned(SMP_CACHE_BYTES)));
-
- void sb1_dma_init(void)
- {
-- int cpu = smp_processor_id();
-- u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1);
-+ int i;
-
-- bus_writeq(base_val,
-- (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
-- bus_writeq(base_val | M_DM_DSCR_BASE_RESET,
-- (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
-- bus_writeq(base_val | M_DM_DSCR_BASE_ENABL,
-- (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
-+ for (i = 0; i < DM_NUM_CHANNELS; i++) {
-+ const u64 base_val = CPHYSADDR(&page_descr[i]) |
-+ V_DM_DSCR_BASE_RINGSZ(1);
-+ volatile void *base_reg =
-+ IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
-+
-+ __raw_writeq(base_val, base_reg);
-+ __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
-+ __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg);
-+ }
- }
-
- void clear_page(void *page)
- {
-- int cpu = smp_processor_id();
-+ u64 to_phys = CPHYSADDR(page);
-+ unsigned int cpu = smp_processor_id();
-
-- /* if the page is above Kseg0, use old way */
-+ /* if the page is not in KSEG0, use old way */
- if ((long)KSEGX(page) != (long)CKSEG0)
- return clear_page_cpu(page);
-
-- page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
-+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
-+ M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
- page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
-- bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
-+ __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
-
- /*
- * Don't really want to do it this way, but there's no
- * reliable way to delay completion detection.
- */
-- while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) &
-- M_DM_DSCR_BASE_INTERRUPT))))
-+ while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
-+ & M_DM_DSCR_BASE_INTERRUPT))
- ;
-- bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
-+ __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
- }
-
- void copy_page(void *to, void *from)
- {
-- unsigned long from_phys = CPHYSADDR(from);
-- unsigned long to_phys = CPHYSADDR(to);
-- int cpu = smp_processor_id();
-+ u64 from_phys = CPHYSADDR(from);
-+ u64 to_phys = CPHYSADDR(to);
-+ unsigned int cpu = smp_processor_id();
-
-- /* if either page is above Kseg0, use old way */
-+ /* if any page is not in KSEG0, use old way */
- if ((long)KSEGX(to) != (long)CKSEG0
- || (long)KSEGX(from) != (long)CKSEG0)
- return copy_page_cpu(to, from);
-
-- page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
-- page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
-- bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
-+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
-+ M_DM_DSCRA_INTERRUPT;
-+ page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
-+ __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
-
- /*
- * Don't really want to do it this way, but there's no
- * reliable way to delay completion detection.
- */
-- while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) &
-- M_DM_DSCR_BASE_INTERRUPT))))
-+ while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
-+ & M_DM_DSCR_BASE_INTERRUPT))
- ;
-- bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
-+ __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
- }
-
- #else /* !CONFIG_SIBYTE_DMA_PAGEOPS */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/pgtable-32.c linux_HEAD/arch/mips/mm/pgtable-32.c
---- linux-2.6.12/arch/mips/mm/pgtable-32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/pgtable-32.c 2005-02-20 02:08:41.000000000 +0100
-@@ -10,6 +10,7 @@
- #include <linux/mm.h>
- #include <linux/bootmem.h>
- #include <linux/highmem.h>
-+#include <asm/fixmap.h>
- #include <asm/pgtable.h>
-
- void pgd_init(unsigned long page)
-@@ -29,42 +30,12 @@ void pgd_init(unsigned long page)
- }
- }
-
--#ifdef CONFIG_HIGHMEM
--static void __init fixrange_init (unsigned long start, unsigned long end,
-- pgd_t *pgd_base)
--{
-- pgd_t *pgd;
-- pmd_t *pmd;
-- pte_t *pte;
-- int i, j;
-- unsigned long vaddr;
--
-- vaddr = start;
-- i = __pgd_offset(vaddr);
-- j = __pmd_offset(vaddr);
-- pgd = pgd_base + i;
--
-- for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
-- pmd = (pmd_t *)pgd;
-- for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) {
-- if (pmd_none(*pmd)) {
-- pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-- set_pmd(pmd, __pmd((unsigned long)pte));
-- if (pte != pte_offset_kernel(pmd, 0))
-- BUG();
-- }
-- vaddr += PMD_SIZE;
-- }
-- j = 0;
-- }
--}
--#endif
--
- void __init pagetable_init(void)
- {
- #ifdef CONFIG_HIGHMEM
- unsigned long vaddr;
- pgd_t *pgd, *pgd_base;
-+ pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- #endif
-@@ -90,7 +61,8 @@ void __init pagetable_init(void)
- fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
-
- pgd = swapper_pg_dir + __pgd_offset(vaddr);
-- pmd = pmd_offset(pgd, vaddr);
-+ pud = pud_offset(pgd, vaddr);
-+ pmd = pmd_offset(pud, vaddr);
- pte = pte_offset_kernel(pmd, vaddr);
- pkmap_page_table = pte;
- #endif
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/sc-rm7k.c linux_HEAD/arch/mips/mm/sc-rm7k.c
---- linux-2.6.12/arch/mips/mm/sc-rm7k.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/sc-rm7k.c 2005-07-01 12:09:18.000000000 +0200
-@@ -15,6 +15,7 @@
- #include <asm/cacheops.h>
- #include <asm/mipsregs.h>
- #include <asm/processor.h>
-+#include <asm/cacheflush.h> /* for run_uncached() */
-
- /* Primary cache parameters. */
- #define sc_lsize 32
-@@ -96,25 +97,13 @@ static void rm7k_sc_inv(unsigned long ad
- }
-
- /*
-- * This function is executed in the uncached segment CKSEG1.
-- * It must not touch the stack, because the stack pointer still points
-- * into CKSEG0.
-- *
-- * Three options:
-- * - Write it in assembly and guarantee that we don't use the stack.
-- * - Disable caching for CKSEG0 before calling it.
-- * - Pray that GCC doesn't randomly start using the stack.
-- *
-- * This being Linux, we obviously take the least sane of those options -
-- * following DaveM's lead in c-r4k.c
-- *
-- * It seems we get our kicks from relying on unguaranteed behaviour in GCC
-+ * This function is executed in uncached address space.
- */
- static __init void __rm7k_sc_enable(void)
- {
- int i;
-
-- set_c0_config(1 << 3); /* CONF_SE */
-+ set_c0_config(RM7K_CONF_SE);
-
- write_c0_taglo(0);
- write_c0_taghi(0);
-@@ -127,24 +116,22 @@ static __init void __rm7k_sc_enable(void
- ".set mips0\n\t"
- ".set reorder"
- :
-- : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
-+ : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
- }
- }
-
- static __init void rm7k_sc_enable(void)
- {
-- void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable);
--
-- if (read_c0_config() & 0x08) /* CONF_SE */
-+ if (read_c0_config() & RM7K_CONF_SE)
- return;
-
-- printk(KERN_INFO "Enabling secondary cache...");
-- func();
-+ printk(KERN_INFO "Enabling secondary cache...\n");
-+ run_uncached(__rm7k_sc_enable);
- }
-
- static void rm7k_sc_disable(void)
- {
-- clear_c0_config(1<<3); /* CONF_SE */
-+ clear_c0_config(RM7K_CONF_SE);
- }
-
- struct bcache_ops rm7k_sc_ops = {
-@@ -158,19 +145,19 @@ void __init rm7k_sc_init(void)
- {
- unsigned int config = read_c0_config();
-
-- if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */
-+ if ((config & RM7K_CONF_SC))
- return;
-
- printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
- (scache_size >> 10), sc_lsize);
-
-- if (!((config >> 3) & 1)) /* CONF_SE */
-+ if (!(config & RM7K_CONF_SE))
- rm7k_sc_enable();
-
- /*
- * While we're at it let's deal with the tertiary cache.
- */
-- if (!((config >> 17) & 1)) {
-+ if (!(config & RM7K_CONF_TC)) {
-
- /*
- * We can't enable the L3 cache yet. There may be board-specific
-@@ -183,9 +170,9 @@ void __init rm7k_sc_init(void)
- * to probe it.
- */
- printk(KERN_INFO "Tertiary cache present, %s enabled\n",
-- config&(1<<12) ? "already" : "not (yet)");
-+ (config & RM7K_CONF_TE) ? "already" : "not (yet)");
-
-- if ((config >> 12) & 1)
-+ if ((config & RM7K_CONF_TE))
- rm7k_tcache_enabled = 1;
- }
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/tlb-andes.c linux_HEAD/arch/mips/mm/tlb-andes.c
---- linux-2.6.12/arch/mips/mm/tlb-andes.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/tlb-andes.c 2005-02-17 21:48:57.000000000 +0100
-@@ -195,6 +195,7 @@ void __update_tlb(struct vm_area_struct
- {
- unsigned long flags;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
- int idx, pid;
-@@ -220,7 +221,8 @@ void __update_tlb(struct vm_area_struct
- write_c0_entryhi(address | (pid));
- pgdp = pgd_offset(vma->vm_mm, address);
- tlb_probe();
-- pmdp = pmd_offset(pgdp, address);
-+ pudp = pud_offset(pgdp, address);
-+ pmdp = pmd_offset(pudp, address);
- idx = read_c0_index();
- ptep = pte_offset_map(pmdp, address);
- write_c0_entrylo0(pte_val(*ptep++) >> 6);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/tlb-r4k.c linux_HEAD/arch/mips/mm/tlb-r4k.c
---- linux-2.6.12/arch/mips/mm/tlb-r4k.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/tlb-r4k.c 2005-07-07 11:22:49.000000000 +0200
-@@ -21,6 +21,12 @@
-
- extern void build_tlb_refill_handler(void);
-
-+/*
-+ * Make sure all entries differ. If they're not different
-+ * MIPS32 will take revenge ...
-+ */
-+#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-+
- /* CP0 hazard avoidance. */
- #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
-@@ -42,11 +48,8 @@ void local_flush_tlb_all(void)
-
- /* Blast 'em all away. */
- while (entry < current_cpu_data.tlbsize) {
-- /*
-- * Make sure all entries differ. If they're not different
-- * MIPS32 will take revenge ...
-- */
-- write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
-+ /* Make sure all entries differ. */
-+ write_c0_entryhi(UNIQUE_ENTRYHI(entry));
- write_c0_index(entry);
- mtc0_tlbw_hazard();
- tlb_write_indexed();
-@@ -57,12 +60,21 @@ void local_flush_tlb_all(void)
- local_irq_restore(flags);
- }
-
-+/* All entries common to a mm share an asid. To effectively flush
-+ these entries, we just bump the asid. */
- void local_flush_tlb_mm(struct mm_struct *mm)
- {
-- int cpu = smp_processor_id();
-+ int cpu;
-+
-+ preempt_disable();
-
-- if (cpu_context(cpu, mm) != 0)
-- drop_mmu_context(mm,cpu);
-+ cpu = smp_processor_id();
-+
-+ if (cpu_context(cpu, mm) != 0) {
-+ drop_mmu_context(mm, cpu);
-+ }
-+
-+ preempt_enable();
- }
-
- void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-@@ -75,9 +87,9 @@ void local_flush_tlb_range(struct vm_are
- unsigned long flags;
- int size;
-
-- local_irq_save(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
-+ local_irq_save(flags);
- if (size <= current_cpu_data.tlbsize/2) {
- int oldpid = read_c0_entryhi();
- int newpid = cpu_asid(cpu, mm);
-@@ -99,8 +111,7 @@ void local_flush_tlb_range(struct vm_are
- if (idx < 0)
- continue;
- /* Make sure all entries differ. */
-- write_c0_entryhi(CKSEG0 +
-- (idx << (PAGE_SHIFT + 1)));
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- }
-@@ -118,9 +129,9 @@ void local_flush_tlb_kernel_range(unsign
- unsigned long flags;
- int size;
-
-- local_irq_save(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
-+ local_irq_save(flags);
- if (size <= current_cpu_data.tlbsize / 2) {
- int pid = read_c0_entryhi();
-
-@@ -142,7 +153,7 @@ void local_flush_tlb_kernel_range(unsign
- if (idx < 0)
- continue;
- /* Make sure all entries differ. */
-- write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- }
-@@ -176,7 +187,7 @@ void local_flush_tlb_page(struct vm_area
- if (idx < 0)
- goto finish;
- /* Make sure all entries differ. */
-- write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- tlbw_use_hazard();
-@@ -197,8 +208,8 @@ void local_flush_tlb_one(unsigned long p
- int oldpid, idx;
-
- local_irq_save(flags);
-- page &= (PAGE_MASK << 1);
- oldpid = read_c0_entryhi();
-+ page &= (PAGE_MASK << 1);
- write_c0_entryhi(page);
- mtc0_tlbw_hazard();
- tlb_probe();
-@@ -208,7 +219,7 @@ void local_flush_tlb_one(unsigned long p
- write_c0_entrylo1(0);
- if (idx >= 0) {
- /* Make sure all entries differ. */
-- write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- tlbw_use_hazard();
-@@ -227,6 +238,7 @@ void __update_tlb(struct vm_area_struct
- {
- unsigned long flags;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
- int idx, pid;
-@@ -237,35 +249,34 @@ void __update_tlb(struct vm_area_struct
- if (current->active_mm != vma->vm_mm)
- return;
-
-- pid = read_c0_entryhi() & ASID_MASK;
--
- local_irq_save(flags);
-+
-+ pid = read_c0_entryhi() & ASID_MASK;
- address &= (PAGE_MASK << 1);
- write_c0_entryhi(address | pid);
- pgdp = pgd_offset(vma->vm_mm, address);
- mtc0_tlbw_hazard();
- tlb_probe();
- BARRIER;
-- pmdp = pmd_offset(pgdp, address);
-+ pudp = pud_offset(pgdp, address);
-+ pmdp = pmd_offset(pudp, address);
- idx = read_c0_index();
- ptep = pte_offset_map(pmdp, address);
-
-- #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-- write_c0_entrylo0(ptep->pte_high);
-- ptep++;
-- write_c0_entrylo1(ptep->pte_high);
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
-+ write_c0_entrylo0(ptep->pte_high);
-+ ptep++;
-+ write_c0_entrylo1(ptep->pte_high);
- #else
-- write_c0_entrylo0(pte_val(*ptep++) >> 6);
-- write_c0_entrylo1(pte_val(*ptep) >> 6);
-+ write_c0_entrylo0(pte_val(*ptep++) >> 6);
-+ write_c0_entrylo1(pte_val(*ptep) >> 6);
- #endif
-- write_c0_entryhi(address | pid);
- mtc0_tlbw_hazard();
- if (idx < 0)
- tlb_write_random();
- else
- tlb_write_indexed();
- tlbw_use_hazard();
-- write_c0_entryhi(pid);
- local_irq_restore(flags);
- }
-
-@@ -357,7 +368,8 @@ __init int add_temporary_entry(unsigned
- old_pagemask = read_c0_pagemask();
- wired = read_c0_wired();
- if (--temp_tlb_entry < wired) {
-- printk(KERN_WARNING "No TLB space left for add_temporary_entry\n");
-+ printk(KERN_WARNING
-+ "No TLB space left for add_temporary_entry\n");
- ret = -ENOSPC;
- goto out;
- }
-@@ -388,7 +400,7 @@ static void __init probe_tlb(unsigned lo
- * is not supported, we assume R4k style. Cpu probing already figured
- * out the number of tlb entries.
- */
-- if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
-+ if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
- return;
-
- reg = read_c0_config1();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/tlb-sb1.c linux_HEAD/arch/mips/mm/tlb-sb1.c
---- linux-2.6.12/arch/mips/mm/tlb-sb1.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/tlb-sb1.c 2005-07-07 11:22:49.000000000 +0200
-@@ -17,6 +17,7 @@
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-+#include <linux/config.h>
- #include <linux/init.h>
- #include <asm/mmu_context.h>
- #include <asm/bootinfo.h>
-@@ -94,7 +95,7 @@ void local_flush_tlb_all(void)
-
- local_irq_save(flags);
- /* Save old context and create impossible VPN2 value */
-- old_ctx = read_c0_entryhi() & ASID_MASK;
-+ old_ctx = read_c0_entryhi();
- write_c0_entrylo0(0);
- write_c0_entrylo1(0);
-
-@@ -144,17 +145,17 @@ void local_flush_tlb_range(struct vm_are
- unsigned long end)
- {
- struct mm_struct *mm = vma->vm_mm;
-- unsigned long flags;
-- int cpu;
-+ int cpu = smp_processor_id();
-
-- local_irq_save(flags);
-- cpu = smp_processor_id();
- if (cpu_context(cpu, mm) != 0) {
-+ unsigned long flags;
- int size;
-+
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
-+ local_irq_save(flags);
- if (size <= (current_cpu_data.tlbsize/2)) {
-- int oldpid = read_c0_entryhi() & ASID_MASK;
-+ int oldpid = read_c0_entryhi();
- int newpid = cpu_asid(cpu, mm);
-
- start &= (PAGE_MASK << 1);
-@@ -169,17 +170,17 @@ void local_flush_tlb_range(struct vm_are
- idx = read_c0_index();
- write_c0_entrylo0(0);
- write_c0_entrylo1(0);
-- write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- if (idx < 0)
- continue;
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- tlb_write_indexed();
- }
- write_c0_entryhi(oldpid);
- } else {
- drop_mmu_context(mm, cpu);
- }
-+ local_irq_restore(flags);
- }
-- local_irq_restore(flags);
- }
-
- void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
-@@ -189,7 +190,6 @@ void local_flush_tlb_kernel_range(unsign
-
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
--
- local_irq_save(flags);
- if (size <= (current_cpu_data.tlbsize/2)) {
- int pid = read_c0_entryhi();
-@@ -207,9 +207,9 @@ void local_flush_tlb_kernel_range(unsign
- idx = read_c0_index();
- write_c0_entrylo0(0);
- write_c0_entrylo1(0);
-- write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- if (idx < 0)
- continue;
-+ write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- tlb_write_indexed();
- }
- write_c0_entryhi(pid);
-@@ -221,15 +221,16 @@ void local_flush_tlb_kernel_range(unsign
-
- void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
- {
-- unsigned long flags;
- int cpu = smp_processor_id();
-
-- local_irq_save(flags);
- if (cpu_context(cpu, vma->vm_mm) != 0) {
-+ unsigned long flags;
- int oldpid, newpid, idx;
-+
- newpid = cpu_asid(cpu, vma->vm_mm);
- page &= (PAGE_MASK << 1);
-- oldpid = read_c0_entryhi() & ASID_MASK;
-+ local_irq_save(flags);
-+ oldpid = read_c0_entryhi();
- write_c0_entryhi(page | newpid);
- tlb_probe();
- idx = read_c0_index();
-@@ -240,10 +241,11 @@ void local_flush_tlb_page(struct vm_area
- /* Make sure all entries differ. */
- write_c0_entryhi(UNIQUE_ENTRYHI(idx));
- tlb_write_indexed();
-+
- finish:
- write_c0_entryhi(oldpid);
-+ local_irq_restore(flags);
- }
-- local_irq_restore(flags);
- }
-
- /*
-@@ -255,18 +257,17 @@ void local_flush_tlb_one(unsigned long p
- unsigned long flags;
- int oldpid, idx;
-
-- page &= (PAGE_MASK << 1);
-- oldpid = read_c0_entryhi() & ASID_MASK;
--
- local_irq_save(flags);
-+ oldpid = read_c0_entryhi();
-+ page &= (PAGE_MASK << 1);
- write_c0_entryhi(page);
- tlb_probe();
- idx = read_c0_index();
-+ write_c0_entrylo0(0);
-+ write_c0_entrylo1(0);
- if (idx >= 0) {
- /* Make sure all entries differ. */
- write_c0_entryhi(UNIQUE_ENTRYHI(idx));
-- write_c0_entrylo0(0);
-- write_c0_entrylo1(0);
- tlb_write_indexed();
- }
-
-@@ -297,6 +298,7 @@ void __update_tlb(struct vm_area_struct
- {
- unsigned long flags;
- pgd_t *pgdp;
-+ pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
- int idx, pid;
-@@ -311,19 +313,26 @@ void __update_tlb(struct vm_area_struct
-
- pid = read_c0_entryhi() & ASID_MASK;
- address &= (PAGE_MASK << 1);
-- write_c0_entryhi(address | (pid));
-+ write_c0_entryhi(address | pid);
- pgdp = pgd_offset(vma->vm_mm, address);
- tlb_probe();
-- pmdp = pmd_offset(pgdp, address);
-+ pudp = pud_offset(pgdp, address);
-+ pmdp = pmd_offset(pudp, address);
- idx = read_c0_index();
- ptep = pte_offset_map(pmdp, address);
-+
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
-+ write_c0_entrylo0(ptep->pte_high);
-+ ptep++;
-+ write_c0_entrylo1(ptep->pte_high);
-+#else
- write_c0_entrylo0(pte_val(*ptep++) >> 6);
- write_c0_entrylo1(pte_val(*ptep) >> 6);
-- if (idx < 0) {
-+#endif
-+ if (idx < 0)
- tlb_write_random();
-- } else {
-+ else
- tlb_write_indexed();
-- }
- local_irq_restore(flags);
- }
-
-@@ -336,7 +345,8 @@ void __init add_wired_entry(unsigned lon
- unsigned long old_ctx;
-
- local_irq_save(flags);
-- old_ctx = read_c0_entryhi() & 0xff;
-+ /* Save old context and create impossible VPN2 value */
-+ old_ctx = read_c0_entryhi();
- old_pagemask = read_c0_pagemask();
- wired = read_c0_wired();
- write_c0_wired(wired + 1);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/mm/tlbex.c linux_HEAD/arch/mips/mm/tlbex.c
---- linux-2.6.12/arch/mips/mm/tlbex.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/mm/tlbex.c 2005-07-10 12:16:57.000000000 +0200
-@@ -6,6 +6,7 @@
- * Synthesize TLB refill handlers at runtime.
- *
- * Copyright (C) 2004,2005 by Thiemo Seufer
-+ * Copyright (C) 2005 Maciej W. Rozycki
- */
-
- #include <stdarg.h>
-@@ -91,7 +92,7 @@ enum opcode {
- insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
- insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
- insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
-- insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
-+ insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
- insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
- insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
- insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
-@@ -134,7 +135,6 @@ static __initdata struct insn insn_table
- { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
- { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
- { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
-- { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
- { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
- { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
- { insn_j, M(j_op,0,0,0,0,0), JIMM },
-@@ -366,7 +366,6 @@ I_u2u1u3(_dsll);
- I_u2u1u3(_dsll32);
- I_u2u1u3(_dsra);
- I_u2u1u3(_dsrl);
--I_u2u1u3(_dsrl32);
- I_u3u1u2(_dsubu);
- I_0(_eret);
- I_u1(_j);
-@@ -412,7 +411,6 @@ enum label_id {
- label_nopage_tlbm,
- label_smp_pgtable_change,
- label_r3000_write_probe_fail,
-- label_r3000_write_probe_ok
- };
-
- struct label {
-@@ -445,7 +443,6 @@ L_LA(_nopage_tlbs)
- L_LA(_nopage_tlbm)
- L_LA(_smp_pgtable_change)
- L_LA(_r3000_write_probe_fail)
--L_LA(_r3000_write_probe_ok)
-
- /* convenience macros for instructions */
- #ifdef CONFIG_MIPS64
-@@ -490,7 +487,7 @@ L_LA(_r3000_write_probe_ok)
- static __init int __attribute__((unused)) in_compat_space_p(long addr)
- {
- /* Is this address in 32bit compat space? */
-- return (((addr) & 0xffffffff00000000) == 0xffffffff00000000);
-+ return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
- }
-
- static __init int __attribute__((unused)) rel_highest(long val)
-@@ -734,7 +731,7 @@ static void __init build_r3000_tlb_refil
- if (p > tlb_handler + 32)
- panic("TLB refill handler space exceeded");
-
-- printk("Synthesized TLB handler (%u instructions).\n",
-+ printk("Synthesized TLB refill handler (%u instructions).\n",
- (unsigned int)(p - tlb_handler));
- #ifdef DEBUG_TLB
- {
-@@ -834,12 +831,19 @@ static __init void build_tlb_write_entry
- case CPU_R4700:
- case CPU_R5000:
- case CPU_R5000A:
-+ i_nop(p);
-+ tlbw(p);
-+ i_nop(p);
-+ break;
-+
-+ case CPU_R4300:
- case CPU_5KC:
- case CPU_TX49XX:
- case CPU_AU1000:
- case CPU_AU1100:
- case CPU_AU1500:
- case CPU_AU1550:
-+ case CPU_AU1200:
- i_nop(p);
- tlbw(p);
- break;
-@@ -942,34 +946,29 @@ build_get_pmde64(u32 **p, struct label *
- /* No i_nop needed here, since the next insn doesn't touch TMP. */
-
- #ifdef CONFIG_SMP
-+# ifdef CONFIG_BUILD_ELF64
- /*
-- * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()]
-+ * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
- * stored in CONTEXT.
- */
-- if (in_compat_space_p(pgdc)) {
-- i_dmfc0(p, ptr, C0_CONTEXT);
-- i_dsra(p, ptr, ptr, 23);
-- i_ld(p, ptr, 0, ptr);
-- } else {
--#ifdef CONFIG_BUILD_ELF64
-- i_dmfc0(p, ptr, C0_CONTEXT);
-- i_dsrl(p, ptr, ptr, 23);
-- i_dsll(p, ptr, ptr, 3);
-- i_LA_mostly(p, tmp, pgdc);
-- i_daddu(p, ptr, ptr, tmp);
-- i_dmfc0(p, tmp, C0_BADVADDR);
-- i_ld(p, ptr, rel_lo(pgdc), ptr);
--#else
-- i_dmfc0(p, ptr, C0_CONTEXT);
-- i_lui(p, tmp, rel_highest(pgdc));
-- i_dsll(p, ptr, ptr, 9);
-- i_daddiu(p, tmp, tmp, rel_higher(pgdc));
-- i_dsrl32(p, ptr, ptr, 0);
-- i_and(p, ptr, ptr, tmp);
-- i_dmfc0(p, tmp, C0_BADVADDR);
-- i_ld(p, ptr, 0, ptr);
--#endif
-- }
-+ i_dmfc0(p, ptr, C0_CONTEXT);
-+ i_dsrl(p, ptr, ptr, 23);
-+ i_LA_mostly(p, tmp, pgdc);
-+ i_daddu(p, ptr, ptr, tmp);
-+ i_dmfc0(p, tmp, C0_BADVADDR);
-+ i_ld(p, ptr, rel_lo(pgdc), ptr);
-+# else
-+ /*
-+ * 64 bit SMP running in compat space has the lower part of
-+ * &pgd_current[smp_processor_id()] stored in CONTEXT.
-+ */
-+ if (!in_compat_space_p(pgdc))
-+ panic("Invalid page directory address!");
-+
-+ i_dmfc0(p, ptr, C0_CONTEXT);
-+ i_dsra(p, ptr, ptr, 23);
-+ i_ld(p, ptr, 0, ptr);
-+# endif
- #else
- i_LA_mostly(p, ptr, pgdc);
- i_ld(p, ptr, rel_lo(pgdc), ptr);
-@@ -1026,7 +1025,6 @@ build_get_pgde32(u32 **p, unsigned int t
- i_mfc0(p, ptr, C0_CONTEXT);
- i_LA_mostly(p, tmp, pgdc);
- i_srl(p, ptr, ptr, 23);
-- i_sll(p, ptr, ptr, 2);
- i_addu(p, ptr, tmp, ptr);
- #else
- i_LA_mostly(p, ptr, pgdc);
-@@ -1245,8 +1243,15 @@ static void __init build_r4000_tlb_refil
- {
- int i;
-
-- for (i = 0; i < 64; i++)
-- printk("%08x\n", final_handler[i]);
-+ f = final_handler;
-+#ifdef CONFIG_MIPS64
-+ if (final_len > 32)
-+ final_len = 64;
-+ else
-+ f = final_handler + 32;
-+#endif /* CONFIG_MIPS64 */
-+ for (i = 0; i < final_len; i++)
-+ printk("%08x\n", f[i]);
- }
- #endif
-
-@@ -1256,7 +1261,7 @@ static void __init build_r4000_tlb_refil
-
- /*
- * TLB load/store/modify handlers.
-- *
-+ *
- * Only the fastpath gets synthesized at runtime, the slowpath for
- * do_page_fault remains normal asm.
- */
-@@ -1277,37 +1282,41 @@ u32 __tlb_handler_align handle_tlbs[FAST
- u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
-
- static void __init
--iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset,
-- unsigned int ptr)
-+iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
- {
- #ifdef CONFIG_SMP
- # ifdef CONFIG_64BIT_PHYS_ADDR
- if (cpu_has_64bits)
-- i_lld(p, pte, offset, ptr);
-+ i_lld(p, pte, 0, ptr);
- else
- # endif
-- i_LL(p, pte, offset, ptr);
-+ i_LL(p, pte, 0, ptr);
- #else
- # ifdef CONFIG_64BIT_PHYS_ADDR
- if (cpu_has_64bits)
-- i_ld(p, pte, offset, ptr);
-+ i_ld(p, pte, 0, ptr);
- else
- # endif
-- i_LW(p, pte, offset, ptr);
-+ i_LW(p, pte, 0, ptr);
- #endif
- }
-
- static void __init
--iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset,
-- unsigned int ptr)
-+iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
-+ unsigned int mode)
- {
-+#ifdef CONFIG_64BIT_PHYS_ADDR
-+ unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
-+#endif
-+
-+ i_ori(p, pte, pte, mode);
- #ifdef CONFIG_SMP
- # ifdef CONFIG_64BIT_PHYS_ADDR
- if (cpu_has_64bits)
-- i_scd(p, pte, offset, ptr);
-+ i_scd(p, pte, 0, ptr);
- else
- # endif
-- i_SC(p, pte, offset, ptr);
-+ i_SC(p, pte, 0, ptr);
-
- if (r10000_llsc_war())
- il_beqzl(p, r, pte, label_smp_pgtable_change);
-@@ -1318,7 +1327,7 @@ iPTE_SW(u32 **p, struct reloc **r, unsig
- if (!cpu_has_64bits) {
- /* no i_nop needed */
- i_ll(p, pte, sizeof(pte_t) / 2, ptr);
-- i_ori(p, pte, pte, _PAGE_VALID);
-+ i_ori(p, pte, pte, hwmode);
- i_sc(p, pte, sizeof(pte_t) / 2, ptr);
- il_beqz(p, r, pte, label_smp_pgtable_change);
- /* no i_nop needed */
-@@ -1331,15 +1340,15 @@ iPTE_SW(u32 **p, struct reloc **r, unsig
- #else
- # ifdef CONFIG_64BIT_PHYS_ADDR
- if (cpu_has_64bits)
-- i_sd(p, pte, offset, ptr);
-+ i_sd(p, pte, 0, ptr);
- else
- # endif
-- i_SW(p, pte, offset, ptr);
-+ i_SW(p, pte, 0, ptr);
-
- # ifdef CONFIG_64BIT_PHYS_ADDR
- if (!cpu_has_64bits) {
- i_lw(p, pte, sizeof(pte_t) / 2, ptr);
-- i_ori(p, pte, pte, _PAGE_VALID);
-+ i_ori(p, pte, pte, hwmode);
- i_sw(p, pte, sizeof(pte_t) / 2, ptr);
- i_lw(p, pte, 0, ptr);
- }
-@@ -1359,7 +1368,7 @@ build_pte_present(u32 **p, struct label
- i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
- i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
- il_bnez(p, r, pte, lid);
-- iPTE_LW(p, l, pte, 0, ptr);
-+ iPTE_LW(p, l, pte, ptr);
- }
-
- /* Make PTE valid, store result in PTR. */
-@@ -1367,8 +1376,9 @@ static void __init
- build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
- unsigned int ptr)
- {
-- i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED);
-- iPTE_SW(p, r, pte, 0, ptr);
-+ unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
-+
-+ iPTE_SW(p, r, pte, ptr, mode);
- }
-
- /*
-@@ -1382,7 +1392,7 @@ build_pte_writable(u32 **p, struct label
- i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
- i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
- il_bnez(p, r, pte, lid);
-- iPTE_LW(p, l, pte, 0, ptr);
-+ iPTE_LW(p, l, pte, ptr);
- }
-
- /* Make PTE writable, update software status bits as well, then store
-@@ -1392,9 +1402,10 @@ static void __init
- build_make_write(u32 **p, struct reloc **r, unsigned int pte,
- unsigned int ptr)
- {
-- i_ori(p, pte, pte,
-- _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
-- iPTE_SW(p, r, pte, 0, ptr);
-+ unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
-+ | _PAGE_DIRTY);
-+
-+ iPTE_SW(p, r, pte, ptr, mode);
- }
-
- /*
-@@ -1407,41 +1418,48 @@ build_pte_modifiable(u32 **p, struct lab
- {
- i_andi(p, pte, pte, _PAGE_WRITE);
- il_beqz(p, r, pte, lid);
-- iPTE_LW(p, l, pte, 0, ptr);
-+ iPTE_LW(p, l, pte, ptr);
- }
-
- /*
- * R3000 style TLB load/store/modify handlers.
- */
-
--/* This places the pte in the page table at PTR into ENTRYLO0. */
-+/*
-+ * This places the pte into ENTRYLO0 and writes it with tlbwi.
-+ * Then it returns.
-+ */
- static void __init
--build_r3000_pte_reload(u32 **p, unsigned int ptr)
-+build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
- {
-- i_lw(p, ptr, 0, ptr);
-- i_nop(p); /* load delay */
-- i_mtc0(p, ptr, C0_ENTRYLO0);
-- i_nop(p); /* cp0 delay */
-+ i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
-+ i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
-+ i_tlbwi(p);
-+ i_jr(p, tmp);
-+ i_rfe(p); /* branch delay */
- }
-
- /*
-- * The index register may have the probe fail bit set,
-- * because we would trap on access kseg2, i.e. without refill.
-+ * This places the pte into ENTRYLO0 and writes it with tlbwi
-+ * or tlbwr as appropriate. This is because the index register
-+ * may have the probe fail bit set as a result of a trap on a
-+ * kseg2 access, i.e. without refill. Then it returns.
- */
- static void __init
--build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r,
-- unsigned int tmp)
-+build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
-+ unsigned int pte, unsigned int tmp)
- {
- i_mfc0(p, tmp, C0_INDEX);
-- i_nop(p); /* cp0 delay */
-- il_bltz(p, r, tmp, label_r3000_write_probe_fail);
-- i_nop(p); /* branch delay */
-- i_tlbwi(p);
-- il_b(p, r, label_r3000_write_probe_ok);
-- i_nop(p); /* branch delay */
-+ i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
-+ il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
-+ i_mfc0(p, tmp, C0_EPC); /* branch delay */
-+ i_tlbwi(p); /* cp0 delay */
-+ i_jr(p, tmp);
-+ i_rfe(p); /* branch delay */
- l_r3000_write_probe_fail(l, *p);
-- i_tlbwr(p);
-- l_r3000_write_probe_ok(l, *p);
-+ i_tlbwr(p); /* cp0 delay */
-+ i_jr(p, tmp);
-+ i_rfe(p); /* branch delay */
- }
-
- static void __init
-@@ -1461,17 +1479,7 @@ build_r3000_tlbchange_handler_head(u32 *
- i_andi(p, pte, pte, 0xffc); /* load delay */
- i_addu(p, ptr, ptr, pte);
- i_lw(p, pte, 0, ptr);
-- i_nop(p); /* load delay */
-- i_tlbp(p);
--}
--
--static void __init
--build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp)
--{
-- i_mfc0(p, tmp, C0_EPC);
-- i_nop(p); /* cp0 delay */
-- i_jr(p, tmp);
-- i_rfe(p); /* branch delay */
-+ i_tlbp(p); /* load delay */
- }
-
- static void __init build_r3000_tlb_load_handler(void)
-@@ -1486,10 +1494,9 @@ static void __init build_r3000_tlb_load_
-
- build_r3000_tlbchange_handler_head(&p, K0, K1);
- build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
-+ i_nop(&p); /* load delay */
- build_make_valid(&p, &r, K0, K1);
-- build_r3000_pte_reload(&p, K1);
-- build_r3000_tlb_write(&p, &l, &r, K0);
-- build_r3000_tlbchange_handler_tail(&p, K0);
-+ build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
-
- l_nopage_tlbl(&l, p);
- i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
-@@ -1506,7 +1513,7 @@ static void __init build_r3000_tlb_load_
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbl); i++)
- printk("%08x\n", handle_tlbl[i]);
- }
- #endif
-@@ -1527,10 +1534,9 @@ static void __init build_r3000_tlb_store
-
- build_r3000_tlbchange_handler_head(&p, K0, K1);
- build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
-+ i_nop(&p); /* load delay */
- build_make_write(&p, &r, K0, K1);
-- build_r3000_pte_reload(&p, K1);
-- build_r3000_tlb_write(&p, &l, &r, K0);
-- build_r3000_tlbchange_handler_tail(&p, K0);
-+ build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
-
- l_nopage_tlbs(&l, p);
- i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
-@@ -1547,7 +1553,7 @@ static void __init build_r3000_tlb_store
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbs); i++)
- printk("%08x\n", handle_tlbs[i]);
- }
- #endif
-@@ -1568,10 +1574,9 @@ static void __init build_r3000_tlb_modif
-
- build_r3000_tlbchange_handler_head(&p, K0, K1);
- build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
-+ i_nop(&p); /* load delay */
- build_make_write(&p, &r, K0, K1);
-- build_r3000_pte_reload(&p, K1);
-- i_tlbwi(&p);
-- build_r3000_tlbchange_handler_tail(&p, K0);
-+ build_r3000_pte_reload_tlbwi(&p, K0, K1);
-
- l_nopage_tlbm(&l, p);
- i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
-@@ -1588,7 +1593,7 @@ static void __init build_r3000_tlb_modif
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbm); i++)
- printk("%08x\n", handle_tlbm[i]);
- }
- #endif
-@@ -1620,7 +1625,7 @@ build_r4000_tlbchange_handler_head(u32 *
- #ifdef CONFIG_SMP
- l_smp_pgtable_change(l, *p);
- # endif
-- iPTE_LW(p, l, pte, 0, ptr); /* get even pte */
-+ iPTE_LW(p, l, pte, ptr); /* get even pte */
- build_tlb_probe_entry(p);
- }
-
-@@ -1680,7 +1685,7 @@ static void __init build_r4000_tlb_load_
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbl); i++)
- printk("%08x\n", handle_tlbl[i]);
- }
- #endif
-@@ -1719,7 +1724,7 @@ static void __init build_r4000_tlb_store
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbs); i++)
- printk("%08x\n", handle_tlbs[i]);
- }
- #endif
-@@ -1759,7 +1764,7 @@ static void __init build_r4000_tlb_modif
- {
- int i;
-
-- for (i = 0; i < FASTPATH_SIZE; i++)
-+ for (i = 0; i < (p - handle_tlbm); i++)
- printk("%08x\n", handle_tlbm[i]);
- }
- #endif
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/Kconfig linux_HEAD/arch/mips/momentum/Kconfig
---- linux-2.6.12/arch/mips/momentum/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/momentum/Kconfig 2005-01-30 21:45:37.000000000 +0100
-@@ -0,0 +1,6 @@
-+config JAGUAR_DMALOW
-+ bool "Low DMA Mode"
-+ depends on MOMENCO_JAGUAR_ATX
-+ help
-+ Select to Y if jump JP5 is set on your board, N otherwise. Normally
-+ the jumper is set, so if you feel unsafe, just say Y.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/jaguar_atx/setup.c linux_HEAD/arch/mips/momentum/jaguar_atx/setup.c
---- linux-2.6.12/arch/mips/momentum/jaguar_atx/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/jaguar_atx/setup.c 2005-07-07 13:02:51.000000000 +0200
-@@ -351,7 +351,7 @@ static __init int __init ja_pci_init(voi
-
- arch_initcall(ja_pci_init);
-
--static int __init momenco_jaguar_atx_setup(void)
-+void __init plat_setup(void)
- {
- unsigned int tmpword;
-
-@@ -467,8 +467,4 @@ static int __init momenco_jaguar_atx_se
-
- }
- #endif
--
-- return 0;
- }
--
--early_initcall(momenco_jaguar_atx_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/ocelot_3/setup.c linux_HEAD/arch/mips/momentum/ocelot_3/setup.c
---- linux-2.6.12/arch/mips/momentum/ocelot_3/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/ocelot_3/setup.c 2005-07-07 13:02:50.000000000 +0200
-@@ -307,7 +307,7 @@ static __init int __init ja_pci_init(voi
-
- arch_initcall(ja_pci_init);
-
--static int __init momenco_ocelot_3_setup(void)
-+void __init plat_setup(void)
- {
- unsigned int tmpword;
-
-@@ -391,8 +391,4 @@ static int __init momenco_ocelot_3_setup
-
- /* Support for 128 MB memory */
- add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
--
-- return 0;
- }
--
--early_initcall(momenco_ocelot_3_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/ocelot_c/cpci-irq.c linux_HEAD/arch/mips/momentum/ocelot_c/cpci-irq.c
---- linux-2.6.12/arch/mips/momentum/ocelot_c/cpci-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/ocelot_c/cpci-irq.c 2005-02-28 16:56:42.000000000 +0100
-@@ -129,14 +129,13 @@ void ll_cpci_irq(struct pt_regs *regs)
- #define shutdown_cpci_irq disable_cpci_irq
-
- struct hw_interrupt_type cpci_irq_type = {
-- "CPCI/FPGA",
-- startup_cpci_irq,
-- shutdown_cpci_irq,
-- enable_cpci_irq,
-- disable_cpci_irq,
-- mask_and_ack_cpci_irq,
-- end_cpci_irq,
-- NULL
-+ .typename = "CPCI/FPGA",
-+ .startup = startup_cpci_irq,
-+ .shutdown = shutdown_cpci_irq,
-+ .enable = enable_cpci_irq,
-+ .disable = disable_cpci_irq,
-+ .ack = mask_and_ack_cpci_irq,
-+ .end = end_cpci_irq,
- };
-
- void cpci_irq_init(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/ocelot_c/setup.c linux_HEAD/arch/mips/momentum/ocelot_c/setup.c
---- linux-2.6.12/arch/mips/momentum/ocelot_c/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/ocelot_c/setup.c 2005-07-01 12:09:19.000000000 +0200
-@@ -222,7 +222,7 @@ void momenco_time_init(void)
- rtc_set_time = m48t37y_set_time;
- }
-
--static void __init momenco_ocelot_c_setup(void)
-+void __init plat_setup(void)
- {
- unsigned int tmpword;
-
-@@ -340,8 +340,6 @@ static void __init momenco_ocelot_c_setu
- }
- }
-
--early_initcall(momenco_ocelot_c_setup);
--
- #ifndef CONFIG_MIPS64
- /* This needs to be one of the first initcalls, because no I/O port access
- can work before this */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/ocelot_c/uart-irq.c linux_HEAD/arch/mips/momentum/ocelot_c/uart-irq.c
---- linux-2.6.12/arch/mips/momentum/ocelot_c/uart-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/ocelot_c/uart-irq.c 2005-02-28 16:56:42.000000000 +0100
-@@ -122,14 +122,13 @@ void ll_uart_irq(struct pt_regs *regs)
- #define shutdown_uart_irq disable_uart_irq
-
- struct hw_interrupt_type uart_irq_type = {
-- "UART/FPGA",
-- startup_uart_irq,
-- shutdown_uart_irq,
-- enable_uart_irq,
-- disable_uart_irq,
-- mask_and_ack_uart_irq,
-- end_uart_irq,
-- NULL
-+ .typename = "UART/FPGA",
-+ .startup = startup_uart_irq,
-+ .shutdown = shutdown_uart_irq,
-+ .enable = enable_uart_irq,
-+ .disable = disable_uart_irq,
-+ .ack = mask_and_ack_uart_irq,
-+ .end = end_uart_irq,
- };
-
- void uart_irq_init(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/momentum/ocelot_g/setup.c linux_HEAD/arch/mips/momentum/ocelot_g/setup.c
---- linux-2.6.12/arch/mips/momentum/ocelot_g/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/momentum/ocelot_g/setup.c 2005-07-07 13:02:50.000000000 +0200
-@@ -160,7 +160,7 @@ static void __init setup_l3cache(unsigne
- printk("Done\n");
- }
-
--static int __init momenco_ocelot_g_setup(void)
-+void __init plat_setup(void)
- {
- void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
- unsigned int tmpword;
-@@ -240,12 +240,8 @@ static int __init momenco_ocelot_g_setu
-
- /* FIXME: Fix up the DiskOnChip mapping */
- MV_WRITE(0x468, 0xfef73);
--
-- return 0;
- }
-
--early_initcall(momenco_ocelot_g_setup);
--
- /* This needs to be one of the first initcalls, because no I/O port access
- can work before this */
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/oprofile/Makefile linux_HEAD/arch/mips/oprofile/Makefile
---- linux-2.6.12/arch/mips/oprofile/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/oprofile/Makefile 2005-07-07 11:22:49.000000000 +0200
-@@ -10,6 +10,6 @@ DRIVER_OBJS = $(addprefix ../../../drive
-
- oprofile-y := $(DRIVER_OBJS) common.o
-
--oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
--oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
-+oprofile-$(CONFIG_CPU_MIPS32_R1) += op_model_mipsxx.o
-+oprofile-$(CONFIG_CPU_MIPS64_R1) += op_model_mipsxx.o
- oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/oprofile/common.c linux_HEAD/arch/mips/oprofile/common.c
---- linux-2.6.12/arch/mips/oprofile/common.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/oprofile/common.c 2005-02-17 21:48:57.000000000 +0100
-@@ -68,9 +68,18 @@ static void op_mips_stop(void)
- on_each_cpu(model->cpu_stop, NULL, 0, 1);
- }
-
--void __init oprofile_arch_init(struct oprofile_operations *ops)
-+static struct oprofile_operations oprof_mips_ops = {
-+ .create_files = op_mips_create_files,
-+ .setup = op_mips_setup,
-+ .start = op_mips_start,
-+ .stop = op_mips_stop,
-+ .cpu_type = NULL
-+};
-+
-+int __init oprofile_arch_init(struct oprofile_operations **ops)
- {
- struct op_mips_model *lmodel = NULL;
-+ int res;
-
- switch (current_cpu_data.cputype) {
- case CPU_24K:
-@@ -83,21 +92,21 @@ void __init oprofile_arch_init(struct op
- };
-
- if (!lmodel)
-- return;
-+ return -ENODEV;
-
-- if (lmodel->init())
-- return;
-+ res = lmodel->init();
-+ if (res)
-+ return res;
-
- model = lmodel;
-
-- ops->create_files = op_mips_create_files;
-- ops->setup = op_mips_setup;
-- ops->start = op_mips_start;
-- ops->stop = op_mips_stop;
-- ops->cpu_type = lmodel->cpu_type;
-+ oprof_mips_ops.cpu_type = lmodel->cpu_type;
-+ *ops = &oprof_mips_ops;
-
- printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
- lmodel->cpu_type);
-+
-+ return 0;
- }
-
- void oprofile_arch_exit(void)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/oprofile/op_model_rm9000.c linux_HEAD/arch/mips/oprofile/op_model_rm9000.c
---- linux-2.6.12/arch/mips/oprofile/op_model_rm9000.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/oprofile/op_model_rm9000.c 2005-02-17 21:48:57.000000000 +0100
-@@ -5,6 +5,7 @@
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-+#include <linux/init.h>
- #include <linux/oprofile.h>
- #include <linux/interrupt.h>
- #include <linux/smp.h>
-@@ -114,7 +115,7 @@ static irqreturn_t rm9000_perfcount_hand
- return IRQ_HANDLED;
- }
-
--static int rm9000_init(void)
-+static int __init rm9000_init(void)
- {
- return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
- 0, "Perfcounter", NULL);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/fixup-atlas.c linux_HEAD/arch/mips/pci/fixup-atlas.c
---- linux-2.6.12/arch/mips/pci/fixup-atlas.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/fixup-atlas.c 2005-02-17 21:48:57.000000000 +0100
-@@ -1,14 +1,37 @@
-+/*
-+ * Copyright (C) 2003, 2004 Ralf Baechle (ralf at linux-mips.org)
-+ * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
-+ * Author: Maciej W. Rozycki <macro at mips.com>
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ */
- #include <linux/config.h>
- #include <linux/init.h>
- #include <linux/pci.h>
-+
- #include <asm/mips-boards/atlasint.h>
-
--#define INTD ATLASINT_INTD
--#define INTC ATLASINT_INTC
--#define INTB ATLASINT_INTB
-+#define PCIA ATLASINT_PCIA
-+#define PCIB ATLASINT_PCIB
-+#define PCIC ATLASINT_PCIC
-+#define PCID ATLASINT_PCID
- #define INTA ATLASINT_INTA
--#define SCSI ATLASINT_SCSI
-+#define INTB ATLASINT_INTB
- #define ETH ATLASINT_ETH
-+#define INTC ATLASINT_INTC
-+#define SCSI ATLASINT_SCSI
-+#define INTD ATLASINT_INTD
-
- static char irq_tab[][5] __initdata = {
- /* INTA INTB INTC INTD */
-@@ -27,13 +50,13 @@ static char irq_tab[][5] __initdata = {
- {0, 0, 0, 0, 0 }, /* 12: Unused */
- {0, 0, 0, 0, 0 }, /* 13: Unused */
- {0, 0, 0, 0, 0 }, /* 14: Unused */
-- {0, 0, 0, 0, 0 }, /* 15: Unused */
-+ {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */
- {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */
- {0, 0, 0, 0, 0 }, /* 17: Core */
-- {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot 1 */
-- {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Ethernet */
-- {0, 0, 0, 0, 0 }, /* 20: PCI Slot 3 */
-- {0, 0, 0, 0, 0 } /* 21: PCI Slot 4 */
-+ {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */
-+ {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */
-+ {0, 0, 0, 0, 0 }, /* 20: Unused */
-+ {0, 0, 0, 0, 0 } /* 21: Unused */
- };
-
- int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/fixup-au1000.c linux_HEAD/arch/mips/pci/fixup-au1000.c
---- linux-2.6.12/arch/mips/pci/fixup-au1000.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/fixup-au1000.c 2005-04-14 16:40:13.000000000 +0200
-@@ -26,7 +26,6 @@
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
--#include <linux/config.h>
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <linux/kernel.h>
-@@ -34,82 +33,7 @@
-
- #include <asm/mach-au1x00/au1000.h>
-
--/*
-- * Shortcut
-- */
--#ifdef CONFIG_SOC_AU1500
--#define INTA AU1000_PCI_INTA
--#define INTB AU1000_PCI_INTB
--#define INTC AU1000_PCI_INTC
--#define INTD AU1000_PCI_INTD
--#endif
--
--#ifdef CONFIG_SOC_AU1550
--#define INTA AU1550_PCI_INTA
--#define INTB AU1550_PCI_INTB
--#define INTC AU1550_PCI_INTC
--#define INTD AU1550_PCI_INTD
--#endif
--
--#define INTX 0xFF /* not valid */
--
--#ifdef CONFIG_MIPS_DB1500
--static char irq_tab_alchemy[][5] __initdata = {
-- [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT371 */
-- [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
--};
--#endif
--
--#ifdef CONFIG_MIPS_BOSPORUS
--static char irq_tab_alchemy[][5] __initdata = {
-- [11] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 11 - miniPCI */
-- [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - SN1741 */
-- [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
--};
--#endif
--
--#ifdef CONFIG_MIPS_MIRAGE
--static char irq_tab_alchemy[][5] __initdata = {
-- [11] = { -1, INTD, INTX, INTX, INTX}, /* IDSEL 11 - SMI VGX */
-- [12] = { -1, INTX, INTX, INTC, INTX}, /* IDSEL 12 - PNX1300 */
-- [13] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 13 - miniPCI */
--};
--#endif
--
--#ifdef CONFIG_MIPS_DB1550
--static char irq_tab_alchemy[][5] __initdata = {
-- [11] = { -1, INTC, INTX, INTX, INTX}, /* IDSEL 11 - on-board HPT371 */
-- [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
-- [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
--};
--#endif
--
--#ifdef CONFIG_MIPS_PB1500
--static char irq_tab_alchemy[][5] __initdata = {
-- [12] = { -1, INTA, INTX, INTX, INTX}, /* IDSEL 12 - HPT370 */
-- [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
--};
--#endif
--
--#ifdef CONFIG_MIPS_PB1550
--static char irq_tab_alchemy[][5] __initdata = {
-- [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */
-- [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
--};
--#endif
--
--#ifdef CONFIG_MIPS_MTX1
--static char irq_tab_alchemy[][5] __initdata = {
-- [0] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 00 - AdapterA-Slot0 (top) */
-- [1] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
-- [2] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 02 - AdapterB-Slot0 (top) */
-- [3] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
-- [4] = { -1, INTA, INTB, INTX, INTX}, /* IDSEL 04 - AdapterC-Slot0 (top) */
-- [5] = { -1, INTB, INTA, INTX, INTX}, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
-- [6] = { -1, INTC, INTD, INTX, INTX}, /* IDSEL 06 - AdapterD-Slot0 (top) */
-- [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
--};
--#endif
-+extern char irq_tab_alchemy[][5];
-
- int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
- {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/fixup-cobalt.c linux_HEAD/arch/mips/pci/fixup-cobalt.c
---- linux-2.6.12/arch/mips/pci/fixup-cobalt.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/fixup-cobalt.c 2005-04-12 15:07:55.000000000 +0200
-@@ -21,6 +21,20 @@
-
- extern int cobalt_board_id;
-
-+static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
-+{
-+ if (dev->devfn == PCI_DEVFN(0, 0) &&
-+ (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
-+
-+ dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
-+
-+ printk(KERN_INFO "Galileo: fixed bridge class\n");
-+ }
-+}
-+
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
-+ qube_raq_galileo_early_fixup);
-+
- static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
- {
- unsigned short cfgword;
-@@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struc
- {
- unsigned short galileo_id;
-
-+ if (dev->devfn != PCI_DEVFN(0, 0))
-+ return;
-+
- /* Fix PCI latency-timer and cache-line-size values in Galileo
- * host bridge.
- */
-@@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struc
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
-
- /*
-+ * The code described by the comment below has been removed
-+ * as it causes bus mastering by the Ethernet controllers
-+ * to break under any kind of network load. We always set
-+ * the retry timeouts to their maximum.
-+ *
-+ * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
-+ *
- * On all machines prior to Q2, we had the STOP line disconnected
- * from Galileo to VIA on PCI. The new Galileo does not function
- * correctly unless we have it connected.
-@@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struc
- */
- pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
- galileo_id &= 0xff; /* mask off class info */
-+
-+ printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
-+
-+#if 0
- if (galileo_id >= 0x10) {
- /* New Galileo, assumes PCI stop line to VIA is connected. */
- GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
-- } else if (galileo_id == 0x1 || galileo_id == 0x2) {
-+ } else if (galileo_id == 0x1 || galileo_id == 0x2)
-+#endif
-+ {
- signed int timeo;
- /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
- timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
- /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
-- GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
-+ GALILEO_OUTL(
-+ (0xff << 16) | /* retry count */
-+ (0xff << 8) | /* timeout 1 */
-+ 0xff, /* timeout 0 */
-+ GT_PCI0_TOR_OFS);
-+
-+ /* enable PCI retry exceeded interrupt */
-+ GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
- }
- }
-
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID,
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
- qube_raq_galileo_fixup);
-
-+static char irq_tab_qube1[] __initdata = {
-+ [COBALT_PCICONF_CPU] = 0,
-+ [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
-+ [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
-+ [COBALT_PCICONF_VIA] = 0,
-+ [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
-+ [COBALT_PCICONF_ETH1] = 0
-+};
-+
- static char irq_tab_cobalt[] __initdata = {
- [COBALT_PCICONF_CPU] = 0,
- [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
-@@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata =
-
- int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
- {
-+ if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
-+ return irq_tab_qube1[slot];
-+
- if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
- return irq_tab_raq2[slot];
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/ops-au1000.c linux_HEAD/arch/mips/pci/ops-au1000.c
---- linux-2.6.12/arch/mips/pci/ops-au1000.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/ops-au1000.c 2005-02-28 16:56:42.000000000 +0100
-@@ -50,11 +50,6 @@
-
- int (*board_pci_idsel)(unsigned int devsel, int assert);
-
--/* CP0 hazard avoidance. */
--#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
-- "nop; nop; nop; nop;\t" \
-- ".set reorder\n\t")
--
- void mod_wired_entry(int entry, unsigned long entrylo0,
- unsigned long entrylo1, unsigned long entryhi,
- unsigned long pagemask)
-@@ -66,16 +61,12 @@ void mod_wired_entry(int entry, unsigned
- old_ctx = read_c0_entryhi() & 0xff;
- old_pagemask = read_c0_pagemask();
- write_c0_index(entry);
-- BARRIER;
- write_c0_pagemask(pagemask);
- write_c0_entryhi(entryhi);
- write_c0_entrylo0(entrylo0);
- write_c0_entrylo1(entrylo1);
-- BARRIER;
- tlb_write_indexed();
-- BARRIER;
- write_c0_entryhi(old_ctx);
-- BARRIER;
- write_c0_pagemask(old_pagemask);
- }
-
-@@ -128,9 +119,8 @@ static int config_access(unsigned char a
- last_entryLo0 = last_entryLo1 = 0xffffffff;
- }
-
-- /* Since the Au1xxx doesn't do the idsel timing exactly to spec,
-- * many board vendors implement their own off-chip idsel, so call
-- * it now. If it doesn't succeed, may as well bail out at this point.
-+ /* Allow board vendors to implement their own off-chip idsel.
-+ * If it doesn't succeed, may as well bail out at this point.
- */
- if (board_pci_idsel) {
- if (board_pci_idsel(device, 1) == 0) {
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/ops-bonito64.c linux_HEAD/arch/mips/pci/ops-bonito64.c
---- linux-2.6.12/arch/mips/pci/ops-bonito64.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/ops-bonito64.c 2005-04-14 16:40:13.000000000 +0200
-@@ -1,6 +1,8 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
-+ * All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -17,7 +19,6 @@
- *
- * MIPS boards specific PCI support.
- */
--#include <linux/config.h>
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <linux/kernel.h>
-@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_acces
- return -1;
- }
-
--#ifdef CONFIG_MIPS_BOARDS_GEN
-- if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-- /* MIPS Core boards have Bonito connected as device 17 */
-- return -1;
-- }
--#endif
--
- /* Clear cause register bits */
- BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
- BONITO_PCICMD_MTABORT_CLR);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/ops-gt64111.c linux_HEAD/arch/mips/pci/ops-gt64111.c
---- linux-2.6.12/arch/mips/pci/ops-gt64111.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/ops-gt64111.c 2005-04-12 15:07:55.000000000 +0200
-@@ -18,15 +18,15 @@
- #include <asm/cobalt/cobalt.h>
-
- /*
-- * Accessing device 31 hangs the GT64120. Not sure if this will also hang
-- * the GT64111, let's be paranoid for now.
-+ * Device 31 on the GT64111 is used to generate PCI special
-+ * cycles, so we shouldn't expected to find a device there ...
- */
- static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
- {
-- if (bus->number == 0 && devfn == PCI_DEVFN(31, 0))
-- return -1;
-+ if (bus->number == 0 && PCI_SLOT(devfn) < 31)
-+ return 0;
-
-- return 0;
-+ return -1;
- }
-
- static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/ops-gt64120.c linux_HEAD/arch/mips/pci/ops-gt64120.c
---- linux-2.6.12/arch/mips/pci/ops-gt64120.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/ops-gt64120.c 2005-02-17 21:48:57.000000000 +0100
-@@ -1,6 +1,8 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
-+ * All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access
- unsigned char busnum = bus->number;
- u32 intr;
-
-- if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
-- /* Galileo itself is devfn 0, don't move it around */
-- return -1;
--
- if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
- return -1; /* Because of a bug in the galileo (for slot 31). */
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/ops-msc.c linux_HEAD/arch/mips/pci/ops-msc.c
---- linux-2.6.12/arch/mips/pci/ops-msc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/ops-msc.c 2005-07-10 12:28:27.000000000 +0200
-@@ -21,7 +21,6 @@
- * MIPS boards specific PCI support.
- *
- */
--#include <linux/config.h>
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <linux/kernel.h>
-@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(uns
- struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
- {
- unsigned char busnum = bus->number;
-- unsigned char type;
- u32 intr;
-
--#ifdef CONFIG_MIPS_BOARDS_GEN
-- if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-- /* MIPS Core boards have SOCit connected as device 17 */
-- return -1;
-- }
--#endif
--
- /* Clear status register bits. */
- MSC_WRITE(MSC01_PCI_INTSTAT,
- (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
-
-- /* Setup address */
-- if (busnum == 0)
-- type = 0; /* Type 0 */
-- else
-- type = 1; /* Type 1 */
--
- MSC_WRITE(MSC01_PCI_CFGADDR,
- ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
-- (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
-- | (PCI_FUNC(devfn) <<
-- MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
-- 4) <<
-- MSC01_PCI_CFGADDR_RNUM_SHF)
-- | (type)));
-+ (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
-+ (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
-+ ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
-
- /* Perform access */
- if (access_type == PCI_ACCESS_WRITE)
-@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(uns
-
- /* Detect Master/Target abort */
- MSC_READ(MSC01_PCI_INTSTAT, intr);
-- if (intr & (MSC01_PCI_INTCFG_MA_BIT |
-- MSC01_PCI_INTCFG_TA_BIT)) {
-+ if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
- /* Error occurred */
-
- /* Clear bits */
-- MSC_READ(MSC01_PCI_INTSTAT, intr);
- MSC_WRITE(MSC01_PCI_INTSTAT,
-- (MSC01_PCI_INTCFG_MA_BIT |
-- MSC01_PCI_INTCFG_TA_BIT));
-+ (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
-
- return -1;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/pci-ip32.c linux_HEAD/arch/mips/pci/pci-ip32.c
---- linux-2.6.12/arch/mips/pci/pci-ip32.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/pci-ip32.c 2005-02-01 13:09:52.000000000 +0100
-@@ -136,7 +136,9 @@ static int __init mace_init(void)
- BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
- "MACE PCI error", NULL));
-
-- ioport_resource.end = mace_pci_io_resource.end;
-+ iomem_resource = mace_pci_mem_resource;
-+ ioport_resource = mace_pci_io_resource;
-+
- register_pci_controller(&mace_pci_controller);
-
- return 0;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/pci-lasat.c linux_HEAD/arch/mips/pci/pci-lasat.c
---- linux-2.6.12/arch/mips/pci/pci-lasat.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/pci-lasat.c 2005-07-03 21:13:58.000000000 +0200
-@@ -7,12 +7,8 @@
- */
- #include <linux/kernel.h>
- #include <linux/init.h>
--#include <linux/interrupt.h>
- #include <linux/pci.h>
- #include <linux/types.h>
--#include <linux/interrupt.h>
--#include <linux/pci.h>
--#include <linux/delay.h>
- #include <asm/bootinfo.h>
-
- extern struct pci_ops nile4_pci_ops;
-@@ -20,14 +16,14 @@ extern struct pci_ops gt64120_pci_ops;
- static struct resource lasat_pci_mem_resource = {
- .name = "LASAT PCI MEM",
- .start = 0x18000000,
-- .end = 0x19FFFFFF,
-+ .end = 0x19ffffff,
- .flags = IORESOURCE_MEM,
- };
-
- static struct resource lasat_pci_io_resource = {
- .name = "LASAT PCI IO",
- .start = 0x1a000000,
-- .end = 0x1bFFFFFF,
-+ .end = 0x1bffffff,
- .flags = IORESOURCE_IO,
- };
-
-@@ -38,23 +34,25 @@ static struct pci_controller lasat_pci_c
-
- static int __init lasat_pci_setup(void)
- {
-- printk("PCI: starting\n");
-+ printk("PCI: starting\n");
-
-- switch (mips_machtype) {
-- case MACH_LASAT_100:
-+ switch (mips_machtype) {
-+ case MACH_LASAT_100:
- lasat_pci_controller.pci_ops = >64120_pci_ops;
- break;
-- case MACH_LASAT_200:
-+ case MACH_LASAT_200:
- lasat_pci_controller.pci_ops = &nile4_pci_ops;
- break;
-- default:
-+ default:
- panic("pcibios_init: mips_machtype incorrect");
- }
-
- register_pci_controller(&lasat_pci_controller);
-- return 0;
-+
-+ return 0;
- }
--early_initcall(lasat_pci_setup);
-+
-+arch_initcall(lasat_pci_setup);
-
- #define LASATINT_ETH1 0
- #define LASATINT_ETH0 1
-@@ -68,24 +66,22 @@ early_initcall(lasat_pci_setup);
-
- int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
- {
-- switch (slot) {
-- case 1:
-- return LASATINT_PCIA; /* Expansion Module 0 */
-- case 2:
-- return LASATINT_PCIB; /* Expansion Module 1 */
-- case 3:
-- return LASATINT_PCIC; /* Expansion Module 2 */
-- case 4:
-- return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
-- case 5:
-- return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
-- case 6:
-- return LASATINT_HDC; /* IDE controller */
-- default:
-- return 0xff; /* Illegal */
-- }
-+ switch (slot) {
-+ case 1:
-+ case 2:
-+ case 3:
-+ return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
-+ case 4:
-+ return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
-+ case 5:
-+ return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
-+ case 6:
-+ return LASATINT_HDC; /* IDE controller */
-+ default:
-+ return 0xff; /* Illegal */
-+ }
-
-- return -1;
-+ return -1;
- }
-
- /* Do platform specific device initialization at pci_enable_device() time */
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pci/pci-vr41xx.c linux_HEAD/arch/mips/pci/pci-vr41xx.c
---- linux-2.6.12/arch/mips/pci/pci-vr41xx.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pci/pci-vr41xx.c 2005-03-09 22:46:11.000000000 +0100
-@@ -123,10 +123,8 @@ static int __init vr41xx_pciu_init(void)
- return -EBUSY;
-
- pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
-- if (pciu_base == NULL) {
-- release_mem_region(PCIU_BASE, PCIU_SIZE);
-+ if (pciu_base == NULL)
- return -EBUSY;
-- }
-
- /* Disable PCI interrupt */
- vr41xx_disable_pciint();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pmc-sierra/Kconfig linux_HEAD/arch/mips/pmc-sierra/Kconfig
---- linux-2.6.12/arch/mips/pmc-sierra/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/pmc-sierra/Kconfig 2005-01-30 21:45:37.000000000 +0100
-@@ -0,0 +1,3 @@
-+config HYPERTRANSPORT
-+ bool "Hypertransport Support for PMC-Sierra Yosemite"
-+ depends on PMC_YOSEMITE
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h linux_HEAD/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
---- linux-2.6.12/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h 2005-04-14 16:40:13.000000000 +0200
-@@ -34,7 +34,6 @@
- #include <linux/pci.h>
- #include <linux/kernel.h>
- #include <linux/slab.h>
--#include <linux/version.h>
- #include <asm/pci.h>
- #include <asm/io.h>
- #include <linux/init.h>
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pmc-sierra/yosemite/ht-irq.c linux_HEAD/arch/mips/pmc-sierra/yosemite/ht-irq.c
---- linux-2.6.12/arch/mips/pmc-sierra/yosemite/ht-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pmc-sierra/yosemite/ht-irq.c 2005-04-14 16:40:13.000000000 +0200
-@@ -26,7 +26,6 @@
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <linux/kernel.h>
--#include <linux/version.h>
- #include <linux/init.h>
- #include <asm/pci.h>
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pmc-sierra/yosemite/ht.c linux_HEAD/arch/mips/pmc-sierra/yosemite/ht.c
---- linux-2.6.12/arch/mips/pmc-sierra/yosemite/ht.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pmc-sierra/yosemite/ht.c 2005-04-14 16:40:13.000000000 +0200
-@@ -28,7 +28,6 @@
- #include <linux/pci.h>
- #include <linux/kernel.h>
- #include <linux/slab.h>
--#include <linux/version.h>
- #include <asm/pci.h>
- #include <asm/io.h>
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/pmc-sierra/yosemite/setup.c linux_HEAD/arch/mips/pmc-sierra/yosemite/setup.c
---- linux-2.6.12/arch/mips/pmc-sierra/yosemite/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/pmc-sierra/yosemite/setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -212,7 +212,7 @@ static void __init py_late_time_init(voi
- py_rtc_setup();
- }
-
--static int __init pmc_yosemite_setup(void)
-+void __init plat_setup(void)
- {
- board_time_init = yosemite_time_init;
- late_time_init = py_late_time_init;
-@@ -228,8 +228,4 @@ static int __init pmc_yosemite_setup(voi
- OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
- OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
- #endif
--
-- return 0;
- }
--
--early_initcall(pmc_yosemite_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip22/ip22-setup.c linux_HEAD/arch/mips/sgi-ip22/ip22-setup.c
---- linux-2.6.12/arch/mips/sgi-ip22/ip22-setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip22/ip22-setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break);
- extern void ip22_be_init(void) __init;
- extern void ip22_time_init(void) __init;
-
--static int __init ip22_setup(void)
-+void __init plat_setup(void)
- {
- char *ctype;
-
-@@ -137,8 +137,4 @@ static int __init ip22_setup(void)
- }
- }
- #endif
--
-- return 0;
- }
--
--early_initcall(ip22_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip27/Kconfig linux_HEAD/arch/mips/sgi-ip27/Kconfig
---- linux-2.6.12/arch/mips/sgi-ip27/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/sgi-ip27/Kconfig 2005-01-30 21:45:36.000000000 +0100
-@@ -0,0 +1,54 @@
-+#config SGI_SN0_XXL
-+# bool "IP27 XXL"
-+# depends on SGI_IP27
-+# This options adds support for userspace processes upto 16TB size.
-+# Normally the limit is just .5TB.
-+
-+config SGI_SN0_N_MODE
-+ bool "IP27 N-Mode"
-+ depends on SGI_IP27
-+ help
-+ The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
-+ configured in either N-Modes which allows for more nodes or M-Mode
-+ which allows for more memory. Your system is most probably
-+ running in M-Mode, so you should say N here.
-+
-+config DISCONTIGMEM
-+ bool
-+ default y if SGI_IP27
-+ help
-+ Say Y to upport efficient handling of discontiguous physical memory,
-+ for architectures which are either NUMA (Non-Uniform Memory Access)
-+ or have huge holes in the physical address space for other reasons.
-+ See <file:Documentation/vm/numa> for more.
-+
-+config NUMA
-+ bool "NUMA Support"
-+ depends on SGI_IP27
-+ help
-+ Say Y to compile the kernel to support NUMA (Non-Uniform Memory
-+ Access). This option is for configuring high-end multiprocessor
-+ server machines. If in doubt, say N.
-+
-+config MAPPED_KERNEL
-+ bool "Mapped kernel support"
-+ depends on SGI_IP27
-+ help
-+ Change the way a Linux kernel is loaded into memory on a MIPS64
-+ machine. This is required in order to support text replication and
-+ NUMA. If you need to understand it, read the source code.
-+
-+config REPLICATE_KTEXT
-+ bool "Kernel text replication support"
-+ depends on SGI_IP27
-+ help
-+ Say Y here to enable replicating the kernel text across multiple
-+ nodes in a NUMA cluster. This trades memory for speed.
-+
-+config REPLICATE_EXHANDLERS
-+ bool "Exception handler replication support"
-+ depends on SGI_IP27
-+ help
-+ Say Y here to enable replicating the kernel exception handlers
-+ across multiple nodes in a NUMA cluster. This trades memory for
-+ speed.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip27/ip27-console.c linux_HEAD/arch/mips/sgi-ip27/ip27-console.c
---- linux-2.6.12/arch/mips/sgi-ip27/ip27-console.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip27/ip27-console.c 2005-07-01 12:09:20.000000000 +0200
-@@ -30,8 +30,10 @@
- static inline struct ioc3_uartregs *console_uart(void)
- {
- struct ioc3 *ioc3;
-+ nasid_t nasid;
-
-- ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base;
-+ nasid = (master_nasid == INVALID_NASID) ? get_nasid() : master_nasid;
-+ ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(nasid)->memory_base;
-
- return &ioc3->sregs.uarta;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip27/ip27-init.c linux_HEAD/arch/mips/sgi-ip27/ip27-init.c
---- linux-2.6.12/arch/mips/sgi-ip27/ip27-init.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip27/ip27-init.c 2005-07-07 13:20:27.000000000 +0200
-@@ -56,12 +56,12 @@ static void __init per_hub_init(cnodeid_
- {
- struct hub_data *hub = hub_data(cnode);
- nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
-+ int i;
-
- cpu_set(smp_processor_id(), hub->h_cpus);
-
- if (test_and_set_bit(cnode, hub_init_mask))
- return;
--
- /*
- * Set CRB timeout at 5ms, (< PI timeout of 10ms)
- */
-@@ -88,6 +88,24 @@ static void __init per_hub_init(cnodeid_
- __flush_cache_all();
- }
- #endif
-+
-+ /*
-+ * Some interrupts are reserved by hardware or by software convention.
-+ * Mark these as reserved right away so they won't be used accidently
-+ * later.
-+ */
-+ for (i = 0; i <= BASE_PCI_IRQ; i++) {
-+ __set_bit(i, hub->irq_alloc_mask);
-+ LOCAL_HUB_CLR_INTR(INT_PEND0_BASELVL + i);
-+ }
-+
-+ __set_bit(IP_PEND0_6_63, hub->irq_alloc_mask);
-+ LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63);
-+
-+ for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) {
-+ __set_bit(i, hub->irq_alloc_mask);
-+ LOCAL_HUB_CLR_INTR(INT_PEND1_BASELVL + i);
-+ }
- }
-
- void __init per_cpu_init(void)
-@@ -104,30 +122,12 @@ void __init per_cpu_init(void)
-
- clear_c0_status(ST0_IM);
-
-+ per_hub_init(cnode);
-+
- for (i = 0; i < LEVELS_PER_SLICE; i++)
- si->level_to_irq[i] = -1;
-
- /*
-- * Some interrupts are reserved by hardware or by software convention.
-- * Mark these as reserved right away so they won't be used accidently
-- * later.
-- */
-- for (i = 0; i <= BASE_PCI_IRQ; i++) {
-- __set_bit(i, si->irq_alloc_mask);
-- LOCAL_HUB_S(PI_INT_PEND_MOD, i);
-- }
--
-- __set_bit(IP_PEND0_6_63, si->irq_alloc_mask);
-- LOCAL_HUB_S(PI_INT_PEND_MOD, IP_PEND0_6_63);
--
-- for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) {
-- __set_bit(i, si->irq_alloc_mask + 1);
-- LOCAL_HUB_S(PI_INT_PEND_MOD, i);
-- }
--
-- LOCAL_HUB_L(PI_INT_PEND0);
--
-- /*
- * We use this so we can find the local hub's data as fast as only
- * possible.
- */
-@@ -140,8 +140,6 @@ void __init per_cpu_init(void)
- install_cpu_nmi_handler(cputoslice(cpu));
-
- set_c0_status(SRB_DEV0 | SRB_DEV1);
--
-- per_hub_init(cnode);
- }
-
- /*
-@@ -198,7 +196,7 @@ extern void ip27_setup_console(void);
- extern void ip27_time_init(void);
- extern void ip27_reboot_setup(void);
-
--static int __init ip27_setup(void)
-+void __init plat_setup(void)
- {
- hubreg_t p, e, n_mode;
- nasid_t nid;
-@@ -245,8 +243,4 @@ static int __init ip27_setup(void)
- set_io_port_base(IO_BASE);
-
- board_time_init = ip27_time_init;
--
-- return 0;
- }
--
--early_initcall(ip27_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip27/ip27-irq.c linux_HEAD/arch/mips/sgi-ip27/ip27-irq.c
---- linux-2.6.12/arch/mips/sgi-ip27/ip27-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip27/ip27-irq.c 2005-06-18 17:49:19.000000000 +0200
-@@ -14,7 +14,6 @@
- #include <linux/types.h>
- #include <linux/interrupt.h>
- #include <linux/ioport.h>
--#include <linux/irq.h>
- #include <linux/timex.h>
- #include <linux/slab.h>
- #include <linux/random.h>
-@@ -74,14 +73,15 @@ extern int irq_to_slot[];
-
- static inline int alloc_level(int cpu, int irq)
- {
-+ struct hub_data *hub = hub_data(cpu_to_node(cpu));
- struct slice_data *si = cpu_data[cpu].data;
-- int level; /* pre-allocated entries */
-+ int level;
-
-- level = find_first_zero_bit(si->irq_alloc_mask, LEVELS_PER_SLICE);
-+ level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
- if (level >= LEVELS_PER_SLICE)
- panic("Cpu %d flooded with devices\n", cpu);
-
-- __set_bit(level, si->irq_alloc_mask);
-+ __set_bit(level, hub->irq_alloc_mask);
- si->level_to_irq[level] = irq;
-
- return level;
-@@ -216,9 +216,11 @@ static int intr_connect_level(int cpu, i
- {
- nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
- struct slice_data *si = cpu_data[cpu].data;
-+ unsigned long flags;
-
-- __set_bit(bit, si->irq_enable_mask);
-+ set_bit(bit, si->irq_enable_mask);
-
-+ local_irq_save(flags);
- if (!cputoslice(cpu)) {
- REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
- REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
-@@ -226,6 +228,7 @@ static int intr_connect_level(int cpu, i
- REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
- REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
- }
-+ local_irq_restore(flags);
-
- return 0;
- }
-@@ -235,7 +238,7 @@ static int intr_disconnect_level(int cpu
- nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
- struct slice_data *si = cpu_data[cpu].data;
-
-- __clear_bit(bit, si->irq_enable_mask);
-+ clear_bit(bit, si->irq_enable_mask);
-
- if (!cputoslice(cpu)) {
- REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
-@@ -298,6 +301,7 @@ static unsigned int startup_bridge_irq(u
- static void shutdown_bridge_irq(unsigned int irq)
- {
- struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
-+ struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
- bridge_t *bridge = bc->base;
- struct slice_data *si = cpu_data[bc->irq_cpu].data;
- int pin, swlevel;
-@@ -313,7 +317,7 @@ static void shutdown_bridge_irq(unsigned
- swlevel = find_level(&cpu, irq);
- intr_disconnect_level(cpu, swlevel);
-
-- __clear_bit(swlevel, si->irq_alloc_mask);
-+ __clear_bit(swlevel, hub->irq_alloc_mask);
- si->level_to_irq[swlevel] = -1;
-
- bridge->b_int_enable &= ~(1 << pin);
-@@ -433,25 +437,24 @@ void install_ipi(void)
- int slice = LOCAL_HUB_L(PI_CPU_NUM);
- int cpu = smp_processor_id();
- struct slice_data *si = cpu_data[cpu].data;
-- hubreg_t mask, set;
-+ struct hub_data *hub = hub_data(cpu_to_node(cpu));
-+ int resched, call;
-+
-+ resched = CPU_RESCHED_A_IRQ + slice;
-+ __set_bit(resched, hub->irq_alloc_mask);
-+ __set_bit(resched, si->irq_enable_mask);
-+ LOCAL_HUB_CLR_INTR(resched);
-+
-+ call = CPU_CALL_A_IRQ + slice;
-+ __set_bit(call, hub->irq_alloc_mask);
-+ __set_bit(call, si->irq_enable_mask);
-+ LOCAL_HUB_CLR_INTR(call);
-
- if (slice == 0) {
-- LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
-- LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
-- mask = LOCAL_HUB_L(PI_INT_MASK0_A); /* Slice A */
-- set = (1UL << CPU_RESCHED_A_IRQ) | (1UL << CPU_CALL_A_IRQ);
-- mask |= set;
-- si->irq_enable_mask[0] |= set;
-- si->irq_alloc_mask[0] |= set;
-- LOCAL_HUB_S(PI_INT_MASK0_A, mask);
-+ LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
-+ LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
- } else {
-- LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
-- LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
-- mask = LOCAL_HUB_L(PI_INT_MASK0_B); /* Slice B */
-- set = (1UL << CPU_RESCHED_B_IRQ) | (1UL << CPU_CALL_B_IRQ);
-- mask |= set;
-- si->irq_enable_mask[1] |= set;
-- si->irq_alloc_mask[1] |= set;
-- LOCAL_HUB_S(PI_INT_MASK0_B, mask);
-+ LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
-+ LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
- }
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip27/ip27-smp.c linux_HEAD/arch/mips/sgi-ip27/ip27-smp.c
---- linux-2.6.12/arch/mips/sgi-ip27/ip27-smp.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip27/ip27-smp.c 2005-02-17 21:48:58.000000000 +0100
-@@ -127,37 +127,28 @@ void cpu_node_probe(void)
- printk("Discovered %d cpus on %d nodes\n", highest + 1, num_online_nodes());
- }
-
--static void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend,
-- int base_level)
-+static __init void intr_clear_all(nasid_t nasid)
- {
-- volatile hubreg_t bits;
- int i;
-
-- /* Check pending interrupts */
-- if ((bits = HUB_L(pend)) != 0)
-- for (i = 0; i < N_INTPEND_BITS; i++)
-- if (bits & (1 << i))
-- LOCAL_HUB_CLR_INTR(base_level + i);
--}
--
--static void intr_clear_all(nasid_t nasid)
--{
- REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0);
- REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0);
- REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0);
- REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0);
-- intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0),
-- INT_PEND0_BASELVL);
-- intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1),
-- INT_PEND1_BASELVL);
-+
-+ for (i = 0; i < 128; i++)
-+ REMOTE_HUB_CLR_INTR(nasid, i);
- }
-
- void __init prom_prepare_cpus(unsigned int max_cpus)
- {
- cnodeid_t cnode;
-
-- for_each_online_node(cnode)
-+ for_each_online_node(cnode) {
-+ if (cnode == 0)
-+ continue;
- intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
-+ }
-
- replicate_kernel_text();
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip32/ip32-irq.c linux_HEAD/arch/mips/sgi-ip32/ip32-irq.c
---- linux-2.6.12/arch/mips/sgi-ip32/ip32-irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip32/ip32-irq.c 2005-02-28 16:56:42.000000000 +0100
-@@ -163,14 +163,13 @@ static void end_cpu_irq(unsigned int irq
- #define mask_and_ack_cpu_irq disable_cpu_irq
-
- static struct hw_interrupt_type ip32_cpu_interrupt = {
-- "IP32 CPU",
-- startup_cpu_irq,
-- shutdown_cpu_irq,
-- enable_cpu_irq,
-- disable_cpu_irq,
-- mask_and_ack_cpu_irq,
-- end_cpu_irq,
-- NULL
-+ .typename = "IP32 CPU",
-+ .startup = startup_cpu_irq,
-+ .shutdown = shutdown_cpu_irq,
-+ .enable = enable_cpu_irq,
-+ .disable = disable_cpu_irq,
-+ .ack = mask_and_ack_cpu_irq,
-+ .end = end_cpu_irq,
- };
-
- /*
-@@ -234,14 +233,13 @@ static void end_crime_irq(unsigned int i
- #define shutdown_crime_irq disable_crime_irq
-
- static struct hw_interrupt_type ip32_crime_interrupt = {
-- "IP32 CRIME",
-- startup_crime_irq,
-- shutdown_crime_irq,
-- enable_crime_irq,
-- disable_crime_irq,
-- mask_and_ack_crime_irq,
-- end_crime_irq,
-- NULL
-+ .typename = "IP32 CRIME",
-+ .startup = startup_crime_irq,
-+ .shutdown = shutdown_crime_irq,
-+ .enable = enable_crime_irq,
-+ .disable = disable_crime_irq,
-+ .ack = mask_and_ack_crime_irq,
-+ .end = end_crime_irq,
- };
-
- /*
-@@ -294,14 +292,13 @@ static void end_macepci_irq(unsigned int
- #define mask_and_ack_macepci_irq disable_macepci_irq
-
- static struct hw_interrupt_type ip32_macepci_interrupt = {
-- "IP32 MACE PCI",
-- startup_macepci_irq,
-- shutdown_macepci_irq,
-- enable_macepci_irq,
-- disable_macepci_irq,
-- mask_and_ack_macepci_irq,
-- end_macepci_irq,
-- NULL
-+ .typename = "IP32 MACE PCI",
-+ .startup = startup_macepci_irq,
-+ .shutdown = shutdown_macepci_irq,
-+ .enable = enable_macepci_irq,
-+ .disable = disable_macepci_irq,
-+ .ack = mask_and_ack_macepci_irq,
-+ .end = end_macepci_irq,
- };
-
- /* This is used for MACE ISA interrupts. That means bits 4-6 in the
-@@ -425,14 +422,13 @@ static void end_maceisa_irq(unsigned irq
- #define shutdown_maceisa_irq disable_maceisa_irq
-
- static struct hw_interrupt_type ip32_maceisa_interrupt = {
-- "IP32 MACE ISA",
-- startup_maceisa_irq,
-- shutdown_maceisa_irq,
-- enable_maceisa_irq,
-- disable_maceisa_irq,
-- mask_and_ack_maceisa_irq,
-- end_maceisa_irq,
-- NULL
-+ .typename = "IP32 MACE ISA",
-+ .startup = startup_maceisa_irq,
-+ .shutdown = shutdown_maceisa_irq,
-+ .enable = enable_maceisa_irq,
-+ .disable = disable_maceisa_irq,
-+ .ack = mask_and_ack_maceisa_irq,
-+ .end = end_maceisa_irq,
- };
-
- /* This is used for regular non-ISA, non-PCI MACE interrupts. That means
-@@ -476,14 +472,13 @@ static void end_mace_irq(unsigned int ir
- #define mask_and_ack_mace_irq disable_mace_irq
-
- static struct hw_interrupt_type ip32_mace_interrupt = {
-- "IP32 MACE",
-- startup_mace_irq,
-- shutdown_mace_irq,
-- enable_mace_irq,
-- disable_mace_irq,
-- mask_and_ack_mace_irq,
-- end_mace_irq,
-- NULL
-+ .typename = "IP32 MACE",
-+ .startup = startup_mace_irq,
-+ .shutdown = shutdown_mace_irq,
-+ .enable = enable_mace_irq,
-+ .disable = disable_mace_irq,
-+ .ack = mask_and_ack_mace_irq,
-+ .end = end_mace_irq,
- };
-
- static void ip32_unknown_interrupt(struct pt_regs *regs)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip32/ip32-memory.c linux_HEAD/arch/mips/sgi-ip32/ip32-memory.c
---- linux-2.6.12/arch/mips/sgi-ip32/ip32-memory.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip32/ip32-memory.c 2005-01-31 21:33:22.000000000 +0100
-@@ -36,8 +36,8 @@ void __init prom_meminit (void)
- if (base + size > (256 << 20))
- base += CRIME_HI_MEM_BASE;
-
-- printk("CRIME MC: bank %u base 0x%016lx size %luMB\n",
-- bank, base, size);
-+ printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
-+ bank, base, size >> 20);
- add_memory_region (base, size, BOOT_MEM_RAM);
- }
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sgi-ip32/ip32-setup.c linux_HEAD/arch/mips/sgi-ip32/ip32-setup.c
---- linux-2.6.12/arch/mips/sgi-ip32/ip32-setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sgi-ip32/ip32-setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -92,7 +92,7 @@ void __init ip32_timer_setup(struct irqa
- setup_irq(IP32_R4K_TIMER_IRQ, irq);
- }
-
--static int __init ip32_setup(void)
-+void __init plat_setup(void)
- {
- board_be_init = ip32_be_init;
-
-@@ -152,8 +152,4 @@ static int __init ip32_setup(void)
- }
- }
- #endif
--
-- return 0;
- }
--
--early_initcall(ip32_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/Kconfig linux_HEAD/arch/mips/sibyte/Kconfig
---- linux-2.6.12/arch/mips/sibyte/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/sibyte/Kconfig 2005-02-03 15:28:23.000000000 +0100
-@@ -0,0 +1,143 @@
-+config SIBYTE_SB1250
-+ bool
-+ select HW_HAS_PCI
-+ select SIBYTE_HAS_LDT
-+ select SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_BCM1120
-+ bool
-+ select SIBYTE_BCM112X
-+ select SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_BCM1125
-+ bool
-+ select HW_HAS_PCI
-+ select SIBYTE_BCM112X
-+ select SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_BCM1125H
-+ bool
-+ select HW_HAS_PCI
-+ select SIBYTE_BCM112X
-+ select SIBYTE_HAS_LDT
-+ select SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_BCM112X
-+ bool
-+ select SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_SB1xxx_SOC
-+ bool
-+ depends on EXPERIMENTAL
-+ select DMA_COHERENT
-+ select SIBYTE_CFE
-+ select SWAP_IO_SPACE
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL
-+
-+choice
-+ prompt "SiByte SOC Stepping"
-+ depends on SIBYTE_SB1xxx_SOC
-+
-+config CPU_SB1_PASS_1
-+ bool "1250 Pass1"
-+ depends on SIBYTE_SB1250
-+ select CPU_HAS_PREFETCH
-+
-+config CPU_SB1_PASS_2_1250
-+ bool "1250 An"
-+ depends on SIBYTE_SB1250
-+ select CPU_SB1_PASS_2
-+ help
-+ Also called BCM1250 Pass 2
-+
-+config CPU_SB1_PASS_2_2
-+ bool "1250 Bn"
-+ depends on SIBYTE_SB1250
-+ select CPU_HAS_PREFETCH
-+ help
-+ Also called BCM1250 Pass 2.2
-+
-+config CPU_SB1_PASS_4
-+ bool "1250 Cn"
-+ depends on SIBYTE_SB1250
-+ select CPU_HAS_PREFETCH
-+ help
-+ Also called BCM1250 Pass 3
-+
-+config CPU_SB1_PASS_2_112x
-+ bool "112x Hybrid"
-+ depends on SIBYTE_BCM112X
-+ select CPU_SB1_PASS_2
-+
-+config CPU_SB1_PASS_3
-+ bool "112x An"
-+ depends on SIBYTE_BCM112X
-+ select CPU_HAS_PREFETCH
-+
-+endchoice
-+
-+config CPU_SB1_PASS_2
-+ bool
-+
-+config SIBYTE_HAS_LDT
-+ bool
-+ depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
-+ default y
-+
-+config SIMULATION
-+ bool "Running under simulation"
-+ depends on SIBYTE_SB1xxx_SOC
-+ help
-+ Build a kernel suitable for running under the GDB simulator.
-+ Primarily adjusts the kernel's notion of time.
-+
-+config SIBYTE_CFE
-+ bool "Booting from CFE"
-+ depends on SIBYTE_SB1xxx_SOC
-+ help
-+ Make use of the CFE API for enumerating available memory,
-+ controlling secondary CPUs, and possibly console output.
-+
-+config SIBYTE_CFE_CONSOLE
-+ bool "Use firmware console"
-+ depends on SIBYTE_CFE
-+ help
-+ Use the CFE API's console write routines during boot. Other console
-+ options (VT console, sb1250 duart console, etc.) should not be
-+ configured.
-+
-+config SIBYTE_STANDALONE
-+ bool
-+ depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
-+ default y
-+
-+config SIBYTE_STANDALONE_RAM_SIZE
-+ int "Memory size (in megabytes)"
-+ depends on SIBYTE_STANDALONE
-+ default "32"
-+
-+config SIBYTE_BUS_WATCHER
-+ bool "Support for Bus Watcher statistics"
-+ depends on SIBYTE_SB1xxx_SOC
-+ help
-+ Handle and keep statistics on the bus error interrupts (COR_ECC,
-+ BAD_ECC, IO_BUS).
-+
-+config SIBYTE_BW_TRACE
-+ bool "Capture bus trace before bus error"
-+ depends on SIBYTE_BUS_WATCHER
-+ help
-+ Run a continuous bus trace, dumping the raw data as soon as
-+ a ZBbus error is detected. Cannot work if ZBbus profiling
-+ is turned on, and also will interfere with JTAG-based trace
-+ buffer activity. Raw buffer data is dumped to console, and
-+ must be processed off-line.
-+
-+config SIBYTE_SB1250_PROF
-+ bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
-+ depends on SIBYTE_SB1xxx_SOC
-+
-+config SIBYTE_TBPROF
-+ bool "Support for ZBbus profiling"
-+ depends on SIBYTE_SB1xxx_SOC
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/bcm1250_tbprof.c linux_HEAD/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/bcm1250_tbprof.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/bcm1250_tbprof.c 2005-02-24 00:13:17.000000000 +0100
-@@ -28,6 +28,7 @@
- #include <linux/fs.h>
- #include <linux/errno.h>
- #include <linux/reboot.h>
-+#include <linux/wait.h>
- #include <asm/uaccess.h>
- #include <asm/io.h>
- #include <asm/sibyte/sb1250.h>
-@@ -64,24 +65,25 @@ static void arm_tb(void)
- u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
- /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
- trigger start of trace. XXX vary sampling period */
-- bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
-- scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
-+ __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
-+ scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
- /* Unfortunately, in Pass 2 we must clear all counters to knock down
- a previous interrupt request. This means that bus profiling
- requires ALL of the SCD perf counters. */
-- bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
-- M_SPC_CFG_ENABLE | // enable counting
-- M_SPC_CFG_CLEAR | // clear all counters
-- V_SPC_CFG_SRC1(1), // counter 1 counts cycles
-- IOADDR(A_SCD_PERF_CNT_CFG));
-- bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
-+ __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
-+ // keep counters 0,2,3 as is
-+ M_SPC_CFG_ENABLE | // enable counting
-+ M_SPC_CFG_CLEAR | // clear all counters
-+ V_SPC_CFG_SRC1(1), // counter 1 counts cycles
-+ IOADDR(A_SCD_PERF_CNT_CFG));
-+ __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
- /* Reset the trace buffer */
-- bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
-+ __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
- #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
- /* XXXKW may want to expose control to the data-collector */
- tb_options |= M_SCD_TRACE_CFG_FORCECNT;
- #endif
-- bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
-+ __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
- sbp.tb_armed = 1;
- }
-
-@@ -93,23 +95,30 @@ static irqreturn_t sbprof_tb_intr(int ir
- /* XXX should use XKPHYS to make writes bypass L2 */
- u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
- /* Read out trace */
-- bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
-+ __raw_writeq(M_SCD_TRACE_CFG_START_READ,
-+ IOADDR(A_SCD_TRACE_CFG));
- __asm__ __volatile__ ("sync" : : : "memory");
- /* Loop runs backwards because bundles are read out in reverse order */
- for (i = 256 * 6; i > 0; i -= 6) {
- // Subscripts decrease to put bundle in the order
- // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
-- p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
-- p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
-- p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
-- p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
-- p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
-- p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
-+ p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t2 hi
-+ p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t2 lo
-+ p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t1 hi
-+ p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t1 lo
-+ p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t0 hi
-+ p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-+ // read t0 lo
- }
- if (!sbp.tb_enable) {
- DBG(printk(DEVNAME ": tb_intr shutdown\n"));
-- bus_writeq(M_SCD_TRACE_CFG_RESET,
-- IOADDR(A_SCD_TRACE_CFG));
-+ __raw_writeq(M_SCD_TRACE_CFG_RESET,
-+ IOADDR(A_SCD_TRACE_CFG));
- sbp.tb_armed = 0;
- wake_up(&sbp.tb_sync);
- } else {
-@@ -118,7 +127,7 @@ static irqreturn_t sbprof_tb_intr(int ir
- } else {
- /* No more trace buffer samples */
- DBG(printk(DEVNAME ": tb_intr full\n"));
-- bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
-+ __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
- sbp.tb_armed = 0;
- if (!sbp.tb_enable) {
- wake_up(&sbp.tb_sync);
-@@ -152,13 +161,11 @@ int sbprof_zbprof_start(struct file *fil
- return -EBUSY;
- }
- /* Make sure there isn't a perf-cnt interrupt waiting */
-- scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
-+ scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
- /* Disable and clear counters, override SRC_1 */
-- bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
-- M_SPC_CFG_ENABLE |
-- M_SPC_CFG_CLEAR |
-- V_SPC_CFG_SRC1(1),
-- IOADDR(A_SCD_PERF_CNT_CFG));
-+ __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
-+ M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
-+ IOADDR(A_SCD_PERF_CNT_CFG));
-
- /* We grab this interrupt to prevent others from trying to use
- it, even though we don't want to service the interrupts
-@@ -172,55 +179,55 @@ int sbprof_zbprof_start(struct file *fil
- /* I need the core to mask these, but the interrupt mapper to
- pass them through. I am exploiting my knowledge that
- cp0_status masks out IP[5]. krw */
-- bus_writeq(K_INT_MAP_I3,
-- IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-- (K_INT_PERF_CNT << 3)));
-+ __raw_writeq(K_INT_MAP_I3,
-+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-+ (K_INT_PERF_CNT << 3)));
-
- /* Initialize address traps */
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
--
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
--
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
-- bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
-+
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
-+
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
-+ __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
-
- /* Initialize Trace Event 0-7 */
- // when interrupt
-- bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
-+ __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
-
- /* Initialize Trace Sequence 0-7 */
- // Start on event 0 (interrupt)
-- bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
-- IOADDR(A_SCD_TRACE_SEQUENCE_0));
-+ __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
-+ IOADDR(A_SCD_TRACE_SEQUENCE_0));
- // dsamp when d used | asamp when a used
-- bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
-- K_SCD_TRSEQ_TRIGGER_ALL,
-- IOADDR(A_SCD_TRACE_SEQUENCE_1));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
-- bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
-+ __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
-+ K_SCD_TRSEQ_TRIGGER_ALL,
-+ IOADDR(A_SCD_TRACE_SEQUENCE_1));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
-+ __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
-
- /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
-- bus_writeq((1ULL << K_INT_PERF_CNT),
-- IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
-+ __raw_writeq(1ULL << K_INT_PERF_CNT,
-+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
-
- arm_tb();
-
-@@ -231,6 +238,7 @@ int sbprof_zbprof_start(struct file *fil
-
- int sbprof_zbprof_stop(void)
- {
-+ DEFINE_WAIT(wait);
- DBG(printk(DEVNAME ": stopping\n"));
-
- if (sbp.tb_enable) {
-@@ -240,7 +248,9 @@ int sbprof_zbprof_stop(void)
- this sleep happens. */
- if (sbp.tb_armed) {
- DBG(printk(DEVNAME ": wait for disarm\n"));
-- interruptible_sleep_on(&sbp.tb_sync);
-+ prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
-+ schedule();
-+ finish_wait(&sbp.tb_sync, &wait);
- DBG(printk(DEVNAME ": disarm complete\n"));
- }
- free_irq(K_INT_TRACE_FREEZE, &sbp);
-@@ -348,7 +358,10 @@ static int sbprof_tb_ioctl(struct inode
- error = sbprof_zbprof_stop();
- break;
- case SBPROF_ZBWAITFULL:
-- interruptible_sleep_on(&sbp.tb_read);
-+ DEFINE_WAIT(wait);
-+ prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
-+ schedule();
-+ finish_wait(&sbp.tb_read, &wait);
- /* XXXKW check if interrupted? */
- return put_user(TB_FULL, (int *) arg);
- default:
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/bus_watcher.c linux_HEAD/arch/mips/sibyte/sb1250/bus_watcher.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/bus_watcher.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/bus_watcher.c 2005-02-24 00:13:17.000000000 +0100
-@@ -189,7 +189,7 @@ static irqreturn_t sibyte_bw_int(int irq
-
- for (i=0; i<256*6; i++)
- printk("%016llx\n",
-- (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ)));
-+ (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ)));
-
- csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
- csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/irq.c linux_HEAD/arch/mips/sibyte/sb1250/irq.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/irq.c 2005-02-28 16:56:42.000000000 +0100
-@@ -71,17 +71,15 @@ extern char sb1250_duart_present[];
- #endif
-
- static struct hw_interrupt_type sb1250_irq_type = {
-- "SB1250-IMR",
-- startup_sb1250_irq,
-- shutdown_sb1250_irq,
-- enable_sb1250_irq,
-- disable_sb1250_irq,
-- ack_sb1250_irq,
-- end_sb1250_irq,
-+ .typename = "SB1250-IMR",
-+ .startup = startup_sb1250_irq,
-+ .shutdown = shutdown_sb1250_irq,
-+ .enable = enable_sb1250_irq,
-+ .disable = disable_sb1250_irq,
-+ .ack = ack_sb1250_irq,
-+ .end = end_sb1250_irq,
- #ifdef CONFIG_SMP
-- sb1250_set_affinity
--#else
-- NULL
-+ .set_affinity = sb1250_set_affinity
- #endif
- };
-
-@@ -96,11 +94,11 @@ void sb1250_mask_irq(int cpu, int irq)
- u64 cur_ints;
-
- spin_lock_irqsave(&sb1250_imr_lock, flags);
-- cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- cur_ints |= (((u64) 1) << irq);
-- __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- spin_unlock_irqrestore(&sb1250_imr_lock, flags);
- }
-
-@@ -110,11 +108,11 @@ void sb1250_unmask_irq(int cpu, int irq)
- u64 cur_ints;
-
- spin_lock_irqsave(&sb1250_imr_lock, flags);
-- cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- cur_ints &= ~(((u64) 1) << irq);
-- __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- spin_unlock_irqrestore(&sb1250_imr_lock, flags);
- }
-
-@@ -149,23 +147,23 @@ static void sb1250_set_affinity(unsigned
-
- /* Swizzle each CPU's IMR (but leave the IP selection alone) */
- old_cpu = sb1250_irq_owner[irq];
-- cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
-+ R_IMR_INTERRUPT_MASK));
- int_on = !(cur_ints & (((u64) 1) << irq));
- if (int_on) {
- /* If it was on, mask it */
- cur_ints |= (((u64) 1) << irq);
-- __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
-+ R_IMR_INTERRUPT_MASK));
- }
- sb1250_irq_owner[irq] = cpu;
- if (int_on) {
- /* unmask for the new CPU */
-- cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- cur_ints &= ~(((u64) 1) << irq);
-- __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-- R_IMR_INTERRUPT_MASK));
-+ ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
-+ R_IMR_INTERRUPT_MASK));
- }
- spin_unlock(&sb1250_imr_lock);
- spin_unlock_irqrestore(&desc->lock, flags);
-@@ -208,8 +206,8 @@ static void ack_sb1250_irq(unsigned int
- * deliver the interrupts to all CPUs (which makes affinity
- * changing easier for us)
- */
-- pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
-- R_IMR_LDT_INTERRUPT)));
-+ pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
-+ R_IMR_LDT_INTERRUPT)));
- pending &= ((u64)1 << (irq));
- if (pending) {
- int i;
-@@ -224,8 +222,8 @@ static void ack_sb1250_irq(unsigned int
- * Clear for all CPUs so an affinity switch
- * doesn't find an old status
- */
-- bus_writeq(pending,
-- IOADDR(A_IMR_REGISTER(cpu,
-+ __raw_writeq(pending,
-+ IOADDR(A_IMR_REGISTER(cpu,
- R_IMR_LDT_INTERRUPT_CLR)));
- }
-
-@@ -340,12 +338,14 @@ void __init arch_init_irq(void)
-
- /* Default everything to IP2 */
- for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
-- bus_writeq(IMR_IP2_VAL,
-- IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-- (i << 3)));
-- bus_writeq(IMR_IP2_VAL,
-- IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
-- (i << 3)));
-+ __raw_writeq(IMR_IP2_VAL,
-+ IOADDR(A_IMR_REGISTER(0,
-+ R_IMR_INTERRUPT_MAP_BASE) +
-+ (i << 3)));
-+ __raw_writeq(IMR_IP2_VAL,
-+ IOADDR(A_IMR_REGISTER(1,
-+ R_IMR_INTERRUPT_MAP_BASE) +
-+ (i << 3)));
- }
-
- init_sb1250_irqs();
-@@ -355,23 +355,23 @@ void __init arch_init_irq(void)
- * inter-cpu messages
- */
- /* Was I1 */
-- bus_writeq(IMR_IP3_VAL,
-- IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-- (K_INT_MBOX_0 << 3)));
-- bus_writeq(IMR_IP3_VAL,
-- IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
-- (K_INT_MBOX_0 << 3)));
-+ __raw_writeq(IMR_IP3_VAL,
-+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-+ (K_INT_MBOX_0 << 3)));
-+ __raw_writeq(IMR_IP3_VAL,
-+ IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
-+ (K_INT_MBOX_0 << 3)));
-
- /* Clear the mailboxes. The firmware may leave them dirty */
-- bus_writeq(0xffffffffffffffffULL,
-- IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
-- bus_writeq(0xffffffffffffffffULL,
-- IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
-+ __raw_writeq(0xffffffffffffffffULL,
-+ IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
-+ __raw_writeq(0xffffffffffffffffULL,
-+ IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
-
- /* Mask everything except the mailbox registers for both cpus */
- tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
-- bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
-- bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
-+ __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
-+ __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
-
- sb1250_steal_irq(K_INT_MBOX_0);
-
-@@ -396,12 +396,14 @@ void __init arch_init_irq(void)
- sb1250_duart_present[kgdb_port] = 0;
- #endif
- /* Setup uart 1 settings, mapper */
-- bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
-+ __raw_writeq(M_DUART_IMR_BRK,
-+ IOADDR(A_DUART_IMRREG(kgdb_port)));
-
- sb1250_steal_irq(kgdb_irq);
-- bus_writeq(IMR_IP6_VAL,
-- IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
-- (kgdb_irq<<3)));
-+ __raw_writeq(IMR_IP6_VAL,
-+ IOADDR(A_IMR_REGISTER(0,
-+ R_IMR_INTERRUPT_MAP_BASE) +
-+ (kgdb_irq << 3)));
- sb1250_unmask_irq(0, kgdb_irq);
- }
- #endif
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/setup.c linux_HEAD/arch/mips/sibyte/sb1250/setup.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/setup.c 2005-02-24 00:13:17.000000000 +0100
-@@ -153,7 +153,7 @@ void sb1250_setup(void)
- int bad_config = 0;
-
- sb1_pass = read_c0_prid() & 0xff;
-- sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION));
-+ sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
- soc_type = SYS_SOC_TYPE(sys_rev);
- soc_pass = G_SYS_REVISION(sys_rev);
-
-@@ -162,7 +162,7 @@ void sb1250_setup(void)
- machine_restart(NULL);
- }
-
-- plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG)));
-+ plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
- zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
-
- prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/smp.c linux_HEAD/arch/mips/sibyte/sb1250/smp.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/smp.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/smp.c 2005-02-24 00:13:17.000000000 +0100
-@@ -29,18 +29,18 @@
- #include <asm/sibyte/sb1250_int.h>
-
- static void *mailbox_set_regs[] = {
-- (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
-- (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
-+ IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
-+ IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
- };
-
- static void *mailbox_clear_regs[] = {
-- (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
-- (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
-+ IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
-+ IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
- };
-
- static void *mailbox_regs[] = {
-- (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
-- (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
-+ IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
-+ IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
- };
-
- /*
-@@ -73,7 +73,7 @@ void sb1250_smp_finish(void)
- */
- void core_send_ipi(int cpu, unsigned int action)
- {
-- bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
-+ __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
- }
-
- void sb1250_mailbox_interrupt(struct pt_regs *regs)
-@@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_
-
- kstat_this_cpu.irqs[K_INT_MBOX_0]++;
- /* Load the mailbox register to figure out what we're supposed to do */
-- action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
-+ action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
-
- /* Clear the mailbox to clear the interrupt */
-- __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
-+ ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
-
- /*
- * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/sb1250/time.c linux_HEAD/arch/mips/sibyte/sb1250/time.c
---- linux-2.6.12/arch/mips/sibyte/sb1250/time.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/sb1250/time.c 2005-07-07 11:22:49.000000000 +0200
-@@ -67,24 +67,24 @@ void sb1250_time_init(void)
- sb1250_mask_irq(cpu, irq);
-
- /* Map the timer interrupt to ip[4] of this cpu */
-- bus_writeq(IMR_IP4_VAL,
-- IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
-- (irq << 3)));
-+ __raw_writeq(IMR_IP4_VAL,
-+ IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
-+ (irq << 3)));
-
- /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
- /* Disable the timer and set up the count */
-- bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-+ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
- #ifdef CONFIG_SIMULATION
-- bus_writeq(50000 / HZ,
-- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-+ __raw_writeq(50000 / HZ,
-+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
- #else
-- bus_writeq(1000000/HZ,
-- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-+ __raw_writeq(1000000 / HZ,
-+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
- #endif
-
- /* Set the timer running */
-- bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-+ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-
- sb1250_unmask_irq(cpu, irq);
- sb1250_steal_irq(irq);
-@@ -100,13 +100,12 @@ void sb1250_time_init(void)
-
- void sb1250_timer_interrupt(struct pt_regs *regs)
- {
-- extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
- int cpu = smp_processor_id();
- int irq = K_INT_TIMER_0 + cpu;
-
- /* Reset the timer */
-- __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-+ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-
- /*
- * CPU 0 handles the global timer interrupt job
-@@ -130,7 +129,7 @@ void sb1250_timer_interrupt(struct pt_re
- unsigned long sb1250_gettimeoffset(void)
- {
- unsigned long count =
-- bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
-+ __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
-
- return 1000000/HZ - count;
- }
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/swarm/rtc_m41t81.c linux_HEAD/arch/mips/sibyte/swarm/rtc_m41t81.c
---- linux-2.6.12/arch/mips/sibyte/swarm/rtc_m41t81.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/swarm/rtc_m41t81.c 2005-02-24 00:13:17.000000000 +0100
-@@ -82,59 +82,60 @@
- #define M41T81REG_SQW 0x13 /* square wave register */
-
- #define M41T81_CCR_ADDRESS 0x68
--#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
-+
-+#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
-
- static int m41t81_read(uint8_t addr)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
-- bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- }
-
-- return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
-+ return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
- }
-
- static int m41t81_write(uint8_t addr, int b)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD));
-- bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA));
-- bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
-+ __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- }
-
- /* read the same byte again to make sure it is written */
-- bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
- return 0;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/swarm/rtc_xicor1241.c linux_HEAD/arch/mips/sibyte/swarm/rtc_xicor1241.c
---- linux-2.6.12/arch/mips/sibyte/swarm/rtc_xicor1241.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/swarm/rtc_xicor1241.c 2005-02-24 00:13:17.000000000 +0100
-@@ -57,52 +57,52 @@
-
- #define X1241_CCR_ADDRESS 0x6F
-
--#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
-+#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
-
- static int xicor_read(uint8_t addr)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
-- bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
-- bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- }
-
-- return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
-+ return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
- }
-
- static int xicor_write(uint8_t addr, int b)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq(addr, SMB_CSR(R_SMB_CMD));
-- bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
-- bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- } else {
- return 0;
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/swarm/setup.c linux_HEAD/arch/mips/sibyte/swarm/setup.c
---- linux-2.6.12/arch/mips/sibyte/swarm/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/swarm/setup.c 2005-07-07 13:02:51.000000000 +0200
-@@ -84,7 +84,7 @@ int swarm_be_handler(struct pt_regs *reg
- return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
- }
-
--static int __init swarm_setup(void)
-+void __init plat_setup(void)
- {
- sb1250_setup();
-
-@@ -133,12 +133,8 @@ static int __init swarm_setup(void)
- };
- /* XXXKW for CFE, get lines/cols from environment */
- #endif
--
-- return 0;
- }
-
--early_initcall(swarm_setup);
--
- #ifdef LEDS_PHYS
-
- #ifdef CONFIG_SIBYTE_CARMEL
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sibyte/swarm/time.c linux_HEAD/arch/mips/sibyte/swarm/time.c
---- linux-2.6.12/arch/mips/sibyte/swarm/time.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sibyte/swarm/time.c 2005-02-24 00:13:17.000000000 +0100
-@@ -79,48 +79,48 @@ static unsigned int usec_bias = 0;
-
- static int xicor_read(uint8_t addr)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
-- bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
-- bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- }
-
-- return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
-+ return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
- }
-
- static int xicor_write(uint8_t addr, int b)
- {
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- bus_writeq(addr, SMB_CSR(R_SMB_CMD));
-- bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
-- bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
-- SMB_CSR(R_SMB_START));
-+ __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
-+ __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
-+ __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
-+ SMB_CSR(R_SMB_START));
-
-- while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-+ while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
- ;
-
-- if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-+ if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
- /* Clear error bit by writing a 1 */
-- bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-+ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
- return -1;
- } else {
- return 0;
-@@ -228,8 +228,8 @@ void __init swarm_time_init(void)
- /* Establish communication with the Xicor 1241 RTC */
- /* XXXKW how do I share the SMBus with the I2C subsystem? */
-
-- bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
-- bus_writeq(0, SMB_CSR(R_SMB_CONTROL));
-+ __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
-+ __raw_writeq(0, SMB_CSR(R_SMB_CONTROL));
-
- if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
- printk("x1241: couldn't detect on SWARM SMBus 1\n");
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sni/irq.c linux_HEAD/arch/mips/sni/irq.c
---- linux-2.6.12/arch/mips/sni/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sni/irq.c 2005-02-28 16:56:42.000000000 +0100
-@@ -58,14 +58,13 @@ static void end_pciasic_irq(unsigned int
- }
-
- static struct hw_interrupt_type pciasic_irq_type = {
-- "ASIC-PCI",
-- startup_pciasic_irq,
-- shutdown_pciasic_irq,
-- enable_pciasic_irq,
-- disable_pciasic_irq,
-- mask_and_ack_pciasic_irq,
-- end_pciasic_irq,
-- NULL
-+ .typename = "ASIC-PCI",
-+ .startup = startup_pciasic_irq,
-+ .shutdown = shutdown_pciasic_irq,
-+ .enable = enable_pciasic_irq,
-+ .disable = disable_pciasic_irq,
-+ .ack = mask_and_ack_pciasic_irq,
-+ .end = end_pciasic_irq,
- };
-
- /*
-diff -urpNX dontdiff linux-2.6.12/arch/mips/sni/setup.c linux_HEAD/arch/mips/sni/setup.c
---- linux-2.6.12/arch/mips/sni/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/sni/setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -167,7 +167,7 @@ static inline void sni_pcimt_time_init(v
- rtc_set_time = mc146818_set_rtc_mmss;
- }
-
--static int __init sni_rm200_pci_setup(void)
-+void __init plat_setup(void)
- {
- sni_pcimt_detect();
- sni_pcimt_sc_init();
-@@ -196,8 +196,4 @@ static int __init sni_rm200_pci_setup(vo
- #ifdef CONFIG_PCI
- register_pci_controller(&sni_controller);
- #endif
--
-- return 0;
- }
--
--early_initcall(sni_rm200_pci_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/tx4927/Kconfig linux_HEAD/arch/mips/tx4927/Kconfig
---- linux-2.6.12/arch/mips/tx4927/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/tx4927/Kconfig 2005-01-30 21:45:36.000000000 +0100
-@@ -0,0 +1,3 @@
-+config TOSHIBA_FPCIB0
-+ bool "FPCIB0 Backplane Support"
-+ depends on TOSHIBA_RBTX4927
-diff -urpNX dontdiff linux-2.6.12/arch/mips/tx4927/common/tx4927_setup.c linux_HEAD/arch/mips/tx4927/common/tx4927_setup.c
---- linux-2.6.12/arch/mips/tx4927/common/tx4927_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/tx4927/common/tx4927_setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(vo
- }
-
-
--static void __init tx4927_setup(void)
-+void __init plat_setup(void)
- {
- board_time_init = tx4927_time_init;
- board_timer_setup = tx4927_timer_setup;
-@@ -76,12 +76,8 @@ static void __init tx4927_setup(void)
- toshiba_rbtx4927_setup();
- }
- #endif
--
-- return;
- }
-
--early_initcall(tx4927_setup);
--
- void __init tx4927_time_init(void)
- {
-
-diff -urpNX dontdiff linux-2.6.12/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c linux_HEAD/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
---- linux-2.6.12/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 2005-03-04 20:36:08.000000000 +0100
-@@ -77,6 +77,11 @@
- #include <linux/hdreg.h>
- #include <linux/ide.h>
- #endif
-+#ifdef CONFIG_SERIAL_TXX9
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#endif
-
- #undef TOSHIBA_RBTX4927_SETUP_DEBUG
-
-@@ -920,12 +925,30 @@ void __init toshiba_rbtx4927_setup(void)
-
- #endif /* CONFIG_PCI */
-
-+#ifdef CONFIG_SERIAL_TXX9
-+ {
-+ extern int early_serial_txx9_setup(struct uart_port *port);
-+ int i;
-+ struct uart_port req;
-+ for(i = 0; i < 2; i++) {
-+ memset(&req, 0, sizeof(req));
-+ req.line = i;
-+ req.iotype = UPIO_MEM;
-+ req.membase = (char *)(0xff1ff300 + i * 0x100);
-+ req.mapbase = 0xff1ff300 + i * 0x100;
-+ req.irq = 32 + i;
-+ req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-+ req.uartclk = 50000000;
-+ early_serial_txx9_setup(&req);
-+ }
-+ }
- #ifdef CONFIG_SERIAL_TXX9_CONSOLE
- argptr = prom_getcmdline();
- if (strstr(argptr, "console=") == NULL) {
- strcat(argptr, " console=ttyS0,38400");
- }
- #endif
-+#endif
-
- #ifdef CONFIG_ROOT_NFS
- argptr = prom_getcmdline();
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/common/Makefile linux_HEAD/arch/mips/vr4181/common/Makefile
---- linux-2.6.12/arch/mips/vr4181/common/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/common/Makefile 1970-01-01 01:00:00.000000000 +0100
-@@ -1,7 +0,0 @@
--#
--# Makefile for common code of NEC vr4181 based boards
--#
--
--obj-y := irq.o int_handler.o serial.o time.o
--
--EXTRA_AFLAGS := $(CFLAGS)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/common/int_handler.S linux_HEAD/arch/mips/vr4181/common/int_handler.S
---- linux-2.6.12/arch/mips/vr4181/common/int_handler.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/common/int_handler.S 1970-01-01 01:00:00.000000000 +0100
-@@ -1,206 +0,0 @@
--/*
-- * arch/mips/vr4181/common/int_handler.S
-- *
-- * Adapted to the VR4181 and almost entirely rewritten:
-- * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
-- *
-- * Clean up to conform to the new IRQ
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun at mvista.com or jsun at junsun.net
-- *
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License. See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- */
--
--#include <asm/asm.h>
--#include <asm/regdef.h>
--#include <asm/mipsregs.h>
--#include <asm/stackframe.h>
--
--#include <asm/vr4181/vr4181.h>
--
--/*
-- * [jsun]
-- * See include/asm/vr4181/irq.h for IRQ assignment and strategy.
-- */
--
-- .text
-- .set noreorder
--
-- .align 5
-- NESTED(vr4181_handle_irq, PT_SIZE, ra)
--
-- .set noat
-- SAVE_ALL
-- CLI
--
-- .set at
-- .set noreorder
--
-- mfc0 t0, CP0_CAUSE
-- mfc0 t2, CP0_STATUS
--
-- and t0, t2
--
-- /* we check IP3 first; it happens most frequently */
-- andi t1, t0, STATUSF_IP3
-- bnez t1, ll_cpu_ip3
-- andi t1, t0, STATUSF_IP2
-- bnez t1, ll_cpu_ip2
-- andi t1, t0, STATUSF_IP7 /* cpu timer */
-- bnez t1, ll_cputimer_irq
-- andi t1, t0, STATUSF_IP4
-- bnez t1, ll_cpu_ip4
-- andi t1, t0, STATUSF_IP5
-- bnez t1, ll_cpu_ip5
-- andi t1, t0, STATUSF_IP6
-- bnez t1, ll_cpu_ip6
-- andi t1, t0, STATUSF_IP0 /* software int 0 */
-- bnez t1, ll_cpu_ip0
-- andi t1, t0, STATUSF_IP1 /* software int 1 */
-- bnez t1, ll_cpu_ip1
-- nop
--
-- .set reorder
--do_spurious:
-- j spurious_interrupt
--
--/*
-- * regular CPU irqs
-- */
--ll_cputimer_irq:
-- li a0, VR4181_IRQ_TIMER
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--
--ll_cpu_ip0:
-- li a0, VR4181_IRQ_SW1
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--ll_cpu_ip1:
-- li a0, VR4181_IRQ_SW2
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--ll_cpu_ip3:
-- li a0, VR4181_IRQ_INT1
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--ll_cpu_ip4:
-- li a0, VR4181_IRQ_INT2
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--ll_cpu_ip5:
-- li a0, VR4181_IRQ_INT3
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--ll_cpu_ip6:
-- li a0, VR4181_IRQ_INT4
-- move a1, sp
-- jal do_IRQ
-- j ret_from_irq
--
--/*
-- * One of the sys irq has happend.
-- *
-- * In the interest of speed, we first determine in the following order
-- * which 16-irq block have pending interrupts:
-- * sysint1 (16 sources, including cascading intrs from GPIO)
-- * sysint2
-- * gpio (16 intr sources)
-- *
-- * Then we do binary search to find the exact interrupt source.
-- */
--ll_cpu_ip2:
--
-- lui t3,%hi(VR4181_SYSINT1REG)
-- lhu t0,%lo(VR4181_SYSINT1REG)(t3)
-- lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
-- and t0, 0xfffb /* hack - remove RTC Long 1 intr */
-- and t0, t2
-- beqz t0, check_sysint2
--
-- /* check for GPIO interrupts */
-- andi t1, t0, 0x0100
-- bnez t1, check_gpio_int
--
-- /* so we have an interrupt in sysint1 which is not gpio int */
-- li a0, VR4181_SYS_IRQ_BASE - 1
-- j check_16
--
--check_sysint2:
--
-- lhu t0,%lo(VR4181_SYSINT2REG)(t3)
-- lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
-- and t0, 0xfffe /* hack - remove RTC Long 2 intr */
-- and t0, t2
-- li a0, VR4181_SYS_IRQ_BASE + 16 - 1
-- j check_16
--
--check_gpio_int:
-- lui t3,%hi(VR4181_GPINTMSK)
-- lhu t0,%lo(VR4181_GPINTMSK)(t3)
-- lhu t2,%lo(VR4181_GPINTSTAT)(t3)
-- xori t0, 0xffff /* why? reverse logic? */
-- and t0, t2
-- li a0, VR4181_GPIO_IRQ_BASE - 1
-- j check_16
--
--/*
-- * When we reach check_16, we have 16-bit status in t0 and base irq number
-- * in a0.
-- */
--check_16:
-- andi t1, t0, 0xff
-- bnez t1, check_8
--
-- srl t0, 8
-- addi a0, 8
-- j check_8
--
--/*
-- * When we reach check_8, we have 8-bit status in t0 and base irq number
-- * in a0.
-- */
--check_8:
-- andi t1, t0, 0xf
-- bnez t1, check_4
--
-- srl t0, 4
-- addi a0, 4
-- j check_4
--
--/*
-- * When we reach check_4, we have 4-bit status in t0 and base irq number
-- * in a0.
-- */
--check_4:
-- andi t0, t0, 0xf
-- beqz t0, do_spurious
--
--loop:
-- andi t2, t0, 0x1
-- srl t0, 1
-- addi a0, 1
-- beqz t2, loop
--
--found_it:
-- move a1, sp
-- jal do_IRQ
--
-- j ret_from_irq
--
-- END(vr4181_handle_irq)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/common/irq.c linux_HEAD/arch/mips/vr4181/common/irq.c
---- linux-2.6.12/arch/mips/vr4181/common/irq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/common/irq.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,239 +0,0 @@
--/*
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun at mvista.com or jsun at junsun.net
-- * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-- *
-- * linux/arch/mips/vr4181/common/irq.c
-- * Completely re-written to use the new irq.c
-- *
-- * Credits to Bradley D. LaRonde and Michael Klar for writing the original
-- * irq.c file which was derived from the common irq.c file.
-- *
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License. See the file "COPYING" in the main directory of this archive
-- * for more details.
-- */
--#include <linux/types.h>
--#include <linux/init.h>
--#include <linux/kernel_stat.h>
--#include <linux/signal.h>
--#include <linux/sched.h>
--#include <linux/interrupt.h>
--#include <linux/slab.h>
--#include <linux/random.h>
--
--#include <asm/irq.h>
--#include <asm/mipsregs.h>
--#include <asm/gdb-stub.h>
--
--#include <asm/vr4181/vr4181.h>
--
--/*
-- * Strategy:
-- *
-- * We essentially have three irq controllers, CPU, system, and gpio.
-- *
-- * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
-- * CONFIG_IRQ_CPU config option.
-- *
-- * We here provide sys_irq and gpio_irq controller code.
-- */
--
--static int sys_irq_base;
--static int gpio_irq_base;
--
--/* ---------------------- sys irq ------------------------ */
--static void
--sys_irq_enable(unsigned int irq)
--{
-- irq -= sys_irq_base;
-- if (irq < 16) {
-- *VR4181_MSYSINT1REG |= (u16)(1 << irq);
-- } else {
-- irq -= 16;
-- *VR4181_MSYSINT2REG |= (u16)(1 << irq);
-- }
--}
--
--static void
--sys_irq_disable(unsigned int irq)
--{
-- irq -= sys_irq_base;
-- if (irq < 16) {
-- *VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
-- } else {
-- irq -= 16;
-- *VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
-- }
--
--}
--
--static unsigned int
--sys_irq_startup(unsigned int irq)
--{
-- sys_irq_enable(irq);
-- return 0;
--}
--
--#define sys_irq_shutdown sys_irq_disable
--#define sys_irq_ack sys_irq_disable
--
--static void
--sys_irq_end(unsigned int irq)
--{
-- if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-- sys_irq_enable(irq);
--}
--
--static hw_irq_controller sys_irq_controller = {
-- "vr4181_sys_irq",
-- sys_irq_startup,
-- sys_irq_shutdown,
-- sys_irq_enable,
-- sys_irq_disable,
-- sys_irq_ack,
-- sys_irq_end,
-- NULL /* no affinity stuff for UP */
--};
--
--/* ---------------------- gpio irq ------------------------ */
--/* gpio irq lines use reverse logic */
--static void
--gpio_irq_enable(unsigned int irq)
--{
-- irq -= gpio_irq_base;
-- *VR4181_GPINTMSK &= ~((u16)(1 << irq));
--}
--
--static void
--gpio_irq_disable(unsigned int irq)
--{
-- irq -= gpio_irq_base;
-- *VR4181_GPINTMSK |= (u16)(1 << irq);
--}
--
--static unsigned int
--gpio_irq_startup(unsigned int irq)
--{
-- gpio_irq_enable(irq);
--
-- irq -= gpio_irq_base;
-- *VR4181_GPINTEN |= (u16)(1 << irq );
--
-- return 0;
--}
--
--static void
--gpio_irq_shutdown(unsigned int irq)
--{
-- gpio_irq_disable(irq);
--
-- irq -= gpio_irq_base;
-- *VR4181_GPINTEN &= ~((u16)(1 << irq ));
--}
--
--static void
--gpio_irq_ack(unsigned int irq)
--{
-- u16 irqtype;
-- u16 irqshift;
--
-- gpio_irq_disable(irq);
--
-- /* we clear interrupt if it is edge triggered */
-- irq -= gpio_irq_base;
-- if (irq < 8) {
-- irqtype = *VR4181_GPINTTYPL;
-- irqshift = 2 << (irq*2);
-- } else {
-- irqtype = *VR4181_GPINTTYPH;
-- irqshift = 2 << ((irq-8)*2);
-- }
-- if ( ! (irqtype & irqshift) ) {
-- *VR4181_GPINTSTAT = (u16) (1 << irq);
-- }
--}
--
--static void
--gpio_irq_end(unsigned int irq)
--{
-- if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-- gpio_irq_enable(irq);
--}
--
--static hw_irq_controller gpio_irq_controller = {
-- "vr4181_gpio_irq",
-- gpio_irq_startup,
-- gpio_irq_shutdown,
-- gpio_irq_enable,
-- gpio_irq_disable,
-- gpio_irq_ack,
-- gpio_irq_end,
-- NULL /* no affinity stuff for UP */
--};
--
--/* --------------------- IRQ init stuff ---------------------- */
--
--extern asmlinkage void vr4181_handle_irq(void);
--extern void breakpoint(void);
--extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
--extern void mips_cpu_irq_init(u32 irq_base);
--
--static struct irqaction cascade =
-- { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
--static struct irqaction reserved =
-- { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
--
--void __init arch_init_irq(void)
--{
-- int i;
--
-- set_except_vector(0, vr4181_handle_irq);
--
-- /* init CPU irqs */
-- mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
--
-- /* init sys irqs */
-- sys_irq_base = VR4181_SYS_IRQ_BASE;
-- for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
-- irq_desc[i].status = IRQ_DISABLED;
-- irq_desc[i].action = NULL;
-- irq_desc[i].depth = 1;
-- irq_desc[i].handler = &sys_irq_controller;
-- }
--
-- /* init gpio irqs */
-- gpio_irq_base = VR4181_GPIO_IRQ_BASE;
-- for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
-- irq_desc[i].status = IRQ_DISABLED;
-- irq_desc[i].action = NULL;
-- irq_desc[i].depth = 1;
-- irq_desc[i].handler = &gpio_irq_controller;
-- }
--
-- /* Default all ICU IRQs to off ... */
-- *VR4181_MSYSINT1REG = 0;
-- *VR4181_MSYSINT2REG = 0;
--
-- /* We initialize the level 2 ICU registers to all bits disabled. */
-- *VR4181_MPIUINTREG = 0;
-- *VR4181_MAIUINTREG = 0;
-- *VR4181_MKIUINTREG = 0;
--
-- /* disable all GPIO intrs */
-- *VR4181_GPINTMSK = 0xffff;
--
-- /* vector handler. What these do is register the IRQ as non-sharable */
-- setup_irq(VR4181_IRQ_INT0, &cascade);
-- setup_irq(VR4181_IRQ_GIU, &cascade);
--
-- /*
-- * RTC interrupts are interesting. They have two destinations.
-- * One is at sys irq controller, and the other is at CPU IP3 and IP4.
-- * RTC timer is used as system timer.
-- * We enable them here, but timer routine will register later
-- * with CPU IP3/IP4.
-- */
-- setup_irq(VR4181_IRQ_RTCL1, &reserved);
-- setup_irq(VR4181_IRQ_RTCL2, &reserved);
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/common/serial.c linux_HEAD/arch/mips/vr4181/common/serial.c
---- linux-2.6.12/arch/mips/vr4181/common/serial.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/common/serial.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,51 +0,0 @@
--/*
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun at mvista.com or jsun at junsun.net
-- *
-- * arch/mips/vr4181/common/serial.c
-- * initialize serial port on vr4181.
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- */
--
--/*
-- * [jsun, 010925]
-- * You need to make sure rs_table has at least one element in
-- * drivers/char/serial.c file. There is no good way to do it right
-- * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
-- * configure file, which would gives you 64 ports and wastes 11K ram.
-- */
--
--#include <linux/types.h>
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/serial.h>
--
--#include <asm/vr4181/vr4181.h>
--
--void __init vr4181_init_serial(void)
--{
-- struct serial_struct s;
--
-- /* turn on UART clock */
-- *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;
--
-- /* clear memory */
-- memset(&s, 0, sizeof(s));
--
-- s.line = 0; /* we set the first one */
-- s.baud_base = 1152000;
-- s.irq = VR4181_IRQ_SIU;
-- s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
-- s.iomem_base = (u8*)VR4181_SIURB;
-- s.iomem_reg_shift = 0;
-- s.io_type = SERIAL_IO_MEM;
-- if (early_serial_setup(&s) != 0) {
-- panic("vr4181_init_serial() failed!");
-- }
--}
--
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/common/time.c linux_HEAD/arch/mips/vr4181/common/time.c
---- linux-2.6.12/arch/mips/vr4181/common/time.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/common/time.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,145 +0,0 @@
--/*
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- *
-- * rtc and time ops for vr4181. Part of code is drived from
-- * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- */
--
--#include <linux/kernel.h>
--#include <linux/spinlock.h>
--#include <linux/param.h> /* for HZ */
--#include <linux/time.h>
--#include <linux/interrupt.h>
--
--#include <asm/system.h>
--#include <asm/time.h>
--
--#include <asm/vr4181/vr4181.h>
--
--#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
--
--/*
-- * RTC ops
-- */
--
--DEFINE_SPINLOCK(rtc_lock);
--
--/* per VR41xx docs, bad data can be read if between 2 counts */
--static inline unsigned short
--read_time_reg(volatile unsigned short *reg)
--{
-- unsigned short value;
-- do {
-- value = *reg;
-- barrier();
-- } while (value != *reg);
-- return value;
--}
--
--static unsigned long
--vr4181_rtc_get_time(void)
--{
-- unsigned short regh, regm, regl;
--
-- // why this crazy order, you ask? to guarantee that neither m
-- // nor l wrap before all 3 read
-- do {
-- regm = read_time_reg(VR4181_ETIMEMREG);
-- barrier();
-- regh = read_time_reg(VR4181_ETIMEHREG);
-- barrier();
-- regl = read_time_reg(VR4181_ETIMELREG);
-- } while (regm != read_time_reg(VR4181_ETIMEMREG));
-- return ((regh << 17) | (regm << 1) | (regl >> 15));
--}
--
--static int
--vr4181_rtc_set_time(unsigned long timeval)
--{
-- unsigned short intreg;
-- unsigned long flags;
--
-- spin_lock_irqsave(&rtc_lock, flags);
-- intreg = *VR4181_RTCINTREG & 0x05;
-- barrier();
-- *VR4181_ETIMELREG = timeval << 15;
-- *VR4181_ETIMEMREG = timeval >> 1;
-- *VR4181_ETIMEHREG = timeval >> 17;
-- barrier();
-- // assume that any ints that just triggered are invalid, since the
-- // time value is written non-atomically in 3 separate regs
-- *VR4181_RTCINTREG = 0x05 ^ intreg;
-- spin_unlock_irqrestore(&rtc_lock, flags);
--
-- return 0;
--}
--
--
--/*
-- * timer interrupt routine (wrapper)
-- *
-- * we need our own interrupt routine because we need to clear
-- * RTC1 interrupt.
-- */
--static void
--vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
--{
-- /* Clear the interrupt. */
-- *VR4181_RTCINTREG = 0x2;
--
-- /* call the generic one */
-- timer_interrupt(irq, dev_id, regs);
--}
--
--
--/*
-- * vr4181_time_init:
-- *
-- * We pick the following choices:
-- * . we use elapsed timer as the RTC. We set some reasonable init data since
-- * it does not persist across reset
-- * . we use RTC1 as the system timer interrupt source.
-- * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
-- * frequency. In other words, we use calibrate_div64_gettimeoffset().
-- * . we use our own timer interrupt routine which clears the interrupt
-- * and then calls the generic high-level timer interrupt routine.
-- *
-- */
--
--extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
--
--static void
--vr4181_timer_setup(struct irqaction *irq)
--{
-- /* over-write the handler to be our own one */
-- irq->handler = vr4181_timer_interrupt;
--
-- /* sets up the frequency */
-- *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
-- *VR4181_RTCL1HREG = 0;
--
-- /* and ack any pending ints */
-- *VR4181_RTCINTREG = 0x2;
--
-- /* setup irqaction */
-- setup_irq(VR4181_IRQ_INT1, irq);
--
--}
--
--void
--vr4181_init_time(void)
--{
-- /* setup hookup functions */
-- rtc_get_time = vr4181_rtc_get_time;
-- rtc_set_time = vr4181_rtc_set_time;
--
-- board_timer_setup = vr4181_timer_setup;
--}
--
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/osprey/Makefile linux_HEAD/arch/mips/vr4181/osprey/Makefile
---- linux-2.6.12/arch/mips/vr4181/osprey/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/osprey/Makefile 1970-01-01 01:00:00.000000000 +0100
-@@ -1,7 +0,0 @@
--#
--# Makefile for common code of NEC Osprey board
--#
--
--obj-y := setup.o prom.o reset.o
--
--obj-$(CONFIG_KGDB) += dbg_io.o
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/osprey/dbg_io.c linux_HEAD/arch/mips/vr4181/osprey/dbg_io.c
---- linux-2.6.12/arch/mips/vr4181/osprey/dbg_io.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/osprey/dbg_io.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,136 +0,0 @@
--/*
-- * kgdb io functions for osprey. We use the serial port on debug board.
-- *
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- */
--
--/* ======================= CONFIG ======================== */
--
--/* [jsun] we use the second serial port for kdb */
--#define BASE 0xb7fffff0
--#define MAX_BAUD 115200
--
--/* distance in bytes between two serial registers */
--#define REG_OFFSET 1
--
--/*
-- * 0 - kgdb does serial init
-- * 1 - kgdb skip serial init
-- */
--static int remoteDebugInitialized = 1;
--
--/*
-- * the default baud rate *if* kgdb does serial init
-- */
--#define BAUD_DEFAULT UART16550_BAUD_38400
--
--/* ======================= END OF CONFIG ======================== */
--
--typedef unsigned char uint8;
--typedef unsigned int uint32;
--
--#define UART16550_BAUD_2400 2400
--#define UART16550_BAUD_4800 4800
--#define UART16550_BAUD_9600 9600
--#define UART16550_BAUD_19200 19200
--#define UART16550_BAUD_38400 38400
--#define UART16550_BAUD_57600 57600
--#define UART16550_BAUD_115200 115200
--
--#define UART16550_PARITY_NONE 0
--#define UART16550_PARITY_ODD 0x08
--#define UART16550_PARITY_EVEN 0x18
--#define UART16550_PARITY_MARK 0x28
--#define UART16550_PARITY_SPACE 0x38
--
--#define UART16550_DATA_5BIT 0x0
--#define UART16550_DATA_6BIT 0x1
--#define UART16550_DATA_7BIT 0x2
--#define UART16550_DATA_8BIT 0x3
--
--#define UART16550_STOP_1BIT 0x0
--#define UART16550_STOP_2BIT 0x4
--
--/* register offset */
--#define OFS_RCV_BUFFER 0
--#define OFS_TRANS_HOLD 0
--#define OFS_SEND_BUFFER 0
--#define OFS_INTR_ENABLE (1*REG_OFFSET)
--#define OFS_INTR_ID (2*REG_OFFSET)
--#define OFS_DATA_FORMAT (3*REG_OFFSET)
--#define OFS_LINE_CONTROL (3*REG_OFFSET)
--#define OFS_MODEM_CONTROL (4*REG_OFFSET)
--#define OFS_RS232_OUTPUT (4*REG_OFFSET)
--#define OFS_LINE_STATUS (5*REG_OFFSET)
--#define OFS_MODEM_STATUS (6*REG_OFFSET)
--#define OFS_RS232_INPUT (6*REG_OFFSET)
--#define OFS_SCRATCH_PAD (7*REG_OFFSET)
--
--#define OFS_DIVISOR_LSB (0*REG_OFFSET)
--#define OFS_DIVISOR_MSB (1*REG_OFFSET)
--
--
--/* memory-mapped read/write of the port */
--#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
--#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
--
--void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
--{
-- /* disable interrupts */
-- UART16550_WRITE(OFS_INTR_ENABLE, 0);
--
-- /* set up buad rate */
-- {
-- uint32 divisor;
--
-- /* set DIAB bit */
-- UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
--
-- /* set divisor */
-- divisor = MAX_BAUD / baud;
-- UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-- UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
--
-- /* clear DIAB bit */
-- UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-- }
--
-- /* set data format */
-- UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
--}
--
--
--uint8 getDebugChar(void)
--{
-- if (!remoteDebugInitialized) {
-- remoteDebugInitialized = 1;
-- debugInit(BAUD_DEFAULT,
-- UART16550_DATA_8BIT,
-- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-- }
--
-- while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-- return UART16550_READ(OFS_RCV_BUFFER);
--}
--
--
--int putDebugChar(uint8 byte)
--{
-- if (!remoteDebugInitialized) {
-- remoteDebugInitialized = 1;
-- debugInit(BAUD_DEFAULT,
-- UART16550_DATA_8BIT,
-- UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-- }
--
-- while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-- UART16550_WRITE(OFS_SEND_BUFFER, byte);
-- return 1;
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/osprey/prom.c linux_HEAD/arch/mips/vr4181/osprey/prom.c
---- linux-2.6.12/arch/mips/vr4181/osprey/prom.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/osprey/prom.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,49 +0,0 @@
--/*
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- *
-- * arch/mips/vr4181/osprey/prom.c
-- * prom code for osprey.
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- */
--#include <linux/init.h>
--#include <linux/kernel.h>
--#include <linux/string.h>
--#include <linux/mm.h>
--#include <linux/bootmem.h>
--#include <asm/bootinfo.h>
--#include <asm/addrspace.h>
--
--const char *get_system_type(void)
--{
-- return "NEC_Vr41xx Osprey";
--}
--
--/*
-- * [jsun] right now we assume it is the nec debug monitor, which does
-- * not pass any arguments.
-- */
--void __init prom_init(void)
--{
-- // cmdline is now set in default config
-- // strcpy(arcs_cmdline, "ip=bootp ");
-- // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
-- // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
-- // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
--
-- mips_machgroup = MACH_GROUP_NEC_VR41XX;
-- mips_machtype = MACH_NEC_OSPREY;
--
-- /* 16MB fixed */
-- add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
--}
--
--unsigned long __init prom_free_prom_memory(void)
--{
-- return 0;
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/osprey/reset.c linux_HEAD/arch/mips/vr4181/osprey/reset.c
---- linux-2.6.12/arch/mips/vr4181/osprey/reset.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/osprey/reset.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,40 +0,0 @@
--/*
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- * Copyright (C) 1997, 2001 Ralf Baechle
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- */
--#include <linux/sched.h>
--#include <linux/mm.h>
--#include <asm/io.h>
--#include <asm/cacheflush.h>
--#include <asm/processor.h>
--#include <asm/reboot.h>
--#include <asm/system.h>
--
--void nec_osprey_restart(char *command)
--{
-- set_c0_status(ST0_ERL);
-- change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-- flush_cache_all();
-- write_c0_wired(0);
-- __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
--}
--
--void nec_osprey_halt(void)
--{
-- printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-- while (1)
-- __asm__(".set\tmips3\n\t"
-- "wait\n\t"
-- ".set\tmips0");
--}
--
--void nec_osprey_power_off(void)
--{
-- nec_osprey_halt();
--}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr4181/osprey/setup.c linux_HEAD/arch/mips/vr4181/osprey/setup.c
---- linux-2.6.12/arch/mips/vr4181/osprey/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr4181/osprey/setup.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,68 +0,0 @@
--/*
-- * linux/arch/mips/vr4181/setup.c
-- *
-- * VR41xx setup routines
-- *
-- * Copyright (C) 1999 Bradley D. LaRonde
-- * Copyright (C) 1999, 2000 Michael Klar
-- *
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-- *
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License. See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- */
--
--#include <linux/ide.h>
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <asm/reboot.h>
--#include <asm/vr4181/vr4181.h>
--#include <asm/io.h>
--
--
--extern void nec_osprey_restart(char* c);
--extern void nec_osprey_halt(void);
--extern void nec_osprey_power_off(void);
--
--extern void vr4181_init_serial(void);
--extern void vr4181_init_time(void);
--
--static void __init nec_osprey_setup(void)
--{
-- set_io_port_base(VR4181_PORT_BASE);
-- isa_slot_offset = VR4181_ISAMEM_BASE;
--
-- vr4181_init_serial();
-- vr4181_init_time();
--
-- _machine_restart = nec_osprey_restart;
-- _machine_halt = nec_osprey_halt;
-- _machine_power_off = nec_osprey_power_off;
--
-- /* setup resource limit */
-- ioport_resource.end = 0xffffffff;
-- iomem_resource.end = 0xffffffff;
--
-- /* [jsun] hack */
-- /*
-- printk("[jsun] hack to change external ISA control register, %x -> %x\n",
-- (*VR4181_XISACTL),
-- (*VR4181_XISACTL) | 0x2);
-- *VR4181_XISACTL |= 0x2;
-- */
--
-- // *VR4181_GPHIBSTH = 0x2000;
-- // *VR4181_GPMD0REG = 0x00c0;
-- // *VR4181_GPINTEN = 1<<6;
--
-- /* [jsun] I believe this will get the interrupt type right
-- * for the ether port.
-- */
-- *VR4181_GPINTTYPL = 0x3000;
--}
--
--early_initcall(nec_osprey_setup);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/Kconfig linux_HEAD/arch/mips/vr41xx/Kconfig
---- linux-2.6.12/arch/mips/vr41xx/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/vr41xx/Kconfig 2005-03-21 20:03:47.000000000 +0100
-@@ -0,0 +1,107 @@
-+config NEC_CMBVR4133
-+ bool "Support for NEC CMB-VR4133"
-+ depends on MACH_VR41XX
-+ select CPU_VR41XX
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select HW_HAS_PCI
-+ select PCI_VR41XX
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+
-+config ROCKHOPPER
-+ bool "Support for Rockhopper baseboard"
-+ depends on NEC_CMBVR4133
-+ select I8259
-+ select HAVE_STD_PC_SERIAL_PORT
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+
-+config CASIO_E55
-+ bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+
-+config IBM_WORKPAD
-+ bool "Support for IBM WorkPad z50"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select ISA
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+
-+config TANBAC_TB0226
-+ bool "Support for TANBAC TB0226 (Mbase)"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+ The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by
-+ TANBAC. Please refer to <http://www.tanbac.co.jp/> about Mbase.
-+
-+config TANBAC_TB0229
-+ bool "Support for TANBAC TB0229 (VR4131DIMM)"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ help
-+ The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured
-+ by TANBAC. Please refer to <http://www.tanbac.co.jp/> about
-+ VR4131DIMM.
-+
-+config VICTOR_MPC30X
-+ bool "Support for Victor MP-C303/304"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ depends on MACH_VR41XX
-+
-+config ZAO_CAPCELLA
-+ bool "Support for ZAO Networks Capcella"
-+ depends on MACH_VR41XX
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+
-+config PCI_VR41XX
-+ bool "Add PCI control unit support of NEC VR4100 series"
-+ depends on MACH_VR41XX && PCI
-+
-+config GPIO_VR41XX
-+ tristate "Add General-purpose I/O unit support of NEC VR4100 series"
-+ depends on MACH_VR41XX
-+
-+config VRC4171
-+ tristate "Add NEC VRC4171 companion chip support"
-+ depends on MACH_VR41XX && ISA
-+ help
-+ The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121.
-+
-+config VRC4173
-+ tristate "Add NEC VRC4173 companion chip support"
-+ depends on MACH_VR41XX && PCI_VR41XX
-+ help
-+ The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/Makefile linux_HEAD/arch/mips/vr41xx/common/Makefile
---- linux-2.6.12/arch/mips/vr41xx/common/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr41xx/common/Makefile 2005-07-01 12:09:20.000000000 +0200
-@@ -2,7 +2,8 @@
- # Makefile for common code of the NEC VR4100 series.
- #
-
--obj-y += bcu.o cmu.o giu.o icu.o init.o int-handler.o pmu.o
-+obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o
-+obj-$(CONFIG_GPIO_VR41XX) += giu.o
- obj-$(CONFIG_VRC4173) += vrc4173.o
-
- EXTRA_AFLAGS := $(CFLAGS)
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/giu.c linux_HEAD/arch/mips/vr41xx/common/giu.c
---- linux-2.6.12/arch/mips/vr41xx/common/giu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr41xx/common/giu.c 2005-07-01 12:09:20.000000000 +0200
-@@ -3,8 +3,7 @@
- *
- * Copyright (C) 2002 MontaVista Software Inc.
- * Author: Yoichi Yuasa <yyuasa at mvista.com or source at mvista.com>
-- * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-+ * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -63,12 +62,6 @@
-
- static uint32_t giu_base;
-
--static struct irqaction giu_cascade = {
-- .handler = no_action,
-- .mask = CPU_MASK_NONE,
-- .name = "cascade",
--};
--
- #define read_giuint(offset) readw(giu_base + (offset))
- #define write_giuint(val, offset) writew((val), giu_base + (offset))
-
-@@ -192,18 +185,20 @@ static struct hw_interrupt_type giuint_h
- .end = end_giuint_high_irq,
- };
-
--void __init init_vr41xx_giuint_irq(void)
-+void vr41xx_enable_giuint(unsigned int pin)
- {
-- int i;
--
-- for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
-- if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
-- irq_desc[i].handler = &giuint_low_irq_type;
-- else
-- irq_desc[i].handler = &giuint_high_irq_type;
-- }
-+ if (pin < GIUINT_HIGH_OFFSET)
-+ enable_giuint_low_irq(GIU_IRQ(pin));
-+ else
-+ enable_giuint_high_irq(GIU_IRQ(pin));
-+}
-
-- setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade);
-+void vr41xx_disable_giuint(unsigned int pin)
-+{
-+ if (pin < GIUINT_HIGH_OFFSET)
-+ disable_giuint_low_irq(GIU_IRQ(pin));
-+ else
-+ disable_giuint_high_irq(GIU_IRQ(pin));
- }
-
- void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
-@@ -296,52 +291,7 @@ void vr41xx_set_irq_level(int pin, int l
-
- EXPORT_SYMBOL(vr41xx_set_irq_level);
-
--#define GIUINT_NR_IRQS 32
--
--enum {
-- GIUINT_NO_CASCADE,
-- GIUINT_CASCADE
--};
--
--struct vr41xx_giuint_cascade {
-- unsigned int flag;
-- int (*get_irq_number)(int irq);
--};
--
--static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
--
--static int no_irq_number(int irq)
--{
-- return -EINVAL;
--}
--
--int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
--{
-- unsigned int pin;
-- int retval;
--
-- if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31))
-- return -EINVAL;
--
-- if(!get_irq_number)
-- return -EINVAL;
--
-- pin = GIU_IRQ_TO_PIN(irq);
-- giuint_cascade[pin].flag = GIUINT_CASCADE;
-- giuint_cascade[pin].get_irq_number = get_irq_number;
--
-- retval = setup_irq(irq, &giu_cascade);
-- if (retval != 0) {
-- giuint_cascade[pin].flag = GIUINT_NO_CASCADE;
-- giuint_cascade[pin].get_irq_number = no_irq_number;
-- }
--
-- return retval;
--}
--
--EXPORT_SYMBOL(vr41xx_cascade_irq);
--
--static inline int get_irq_pin_number(void)
-+static int giu_get_irq(unsigned int irq, struct pt_regs *regs)
- {
- uint16_t pendl, pendh, maskl, maskh;
- int i;
-@@ -357,12 +307,12 @@ static inline int get_irq_pin_number(voi
- if (maskl) {
- for (i = 0; i < 16; i++) {
- if (maskl & ((uint16_t)1 << i))
-- return i;
-+ return GIU_IRQ(i);
- }
- } else if (maskh) {
- for (i = 0; i < 16; i++) {
- if (maskh & ((uint16_t)1 << i))
-- return i + GIUINT_HIGH_OFFSET;
-+ return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
- }
- }
-
-@@ -374,54 +324,7 @@ static inline int get_irq_pin_number(voi
- return -1;
- }
-
--static inline void ack_giuint_irq(int pin)
--{
-- if (pin < GIUINT_HIGH_OFFSET) {
-- clear_giuint(GIUINTENL, (uint16_t)1 << pin);
-- write_giuint((uint16_t)1 << pin, GIUINTSTATL);
-- } else {
-- pin -= GIUINT_HIGH_OFFSET;
-- clear_giuint(GIUINTENH, (uint16_t)1 << pin);
-- write_giuint((uint16_t)1 << pin, GIUINTSTATH);
-- }
--}
--
--static inline void end_giuint_irq(int pin)
--{
-- if (pin < GIUINT_HIGH_OFFSET)
-- set_giuint(GIUINTENL, (uint16_t)1 << pin);
-- else
-- set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET));
--}
--
--void giuint_irq_dispatch(struct pt_regs *regs)
--{
-- struct vr41xx_giuint_cascade *cascade;
-- unsigned int giuint_irq;
-- int pin;
--
-- pin = get_irq_pin_number();
-- if (pin < 0)
-- return;
--
-- disable_irq(GIUINT_CASCADE_IRQ);
--
-- cascade = &giuint_cascade[pin];
-- giuint_irq = GIU_IRQ(pin);
-- if (cascade->flag == GIUINT_CASCADE) {
-- int irq = cascade->get_irq_number(giuint_irq);
-- ack_giuint_irq(pin);
-- if (irq >= 0)
-- do_IRQ(irq, regs);
-- end_giuint_irq(pin);
-- } else {
-- do_IRQ(giuint_irq, regs);
-- }
--
-- enable_irq(GIUINT_CASCADE_IRQ);
--}
--
--static int __init vr41xx_giu_init(void)
-+static int __init vr41xx_giu_init(void)
- {
- int i;
-
-@@ -437,19 +340,24 @@ static int __init vr41xx_giu_init(void)
- break;
- default:
- printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n");
-- return -EINVAL;
-+ return -ENODEV;
- }
-
-- for (i = 0; i < GIUINT_NR_IRQS; i++) {
-+ for (i = 0; i < 32; i++) {
- if (i < GIUINT_HIGH_OFFSET)
- clear_giuint(GIUINTENL, (uint16_t)1 << i);
- else
- clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET));
-- giuint_cascade[i].flag = GIUINT_NO_CASCADE;
-- giuint_cascade[i].get_irq_number = no_irq_number;
- }
-
-- return 0;
-+ for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
-+ if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
-+ irq_desc[i].handler = &giuint_low_irq_type;
-+ else
-+ irq_desc[i].handler = &giuint_high_irq_type;
-+ }
-+
-+ return cascade_irq(GIUINT_IRQ, giu_get_irq);
- }
-
--early_initcall(vr41xx_giu_init);
-+postcore_initcall(vr41xx_giu_init);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/icu.c linux_HEAD/arch/mips/vr41xx/common/icu.c
---- linux-2.6.12/arch/mips/vr41xx/common/icu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr41xx/common/icu.c 2005-07-01 12:09:20.000000000 +0200
-@@ -3,8 +3,7 @@
- *
- * Copyright (C) 2001-2002 MontaVista Software Inc.
- * Author: Yoichi Yuasa <yyuasa at mvista.com or source at mvista.com>
-- * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-+ * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -32,6 +31,7 @@
- #include <linux/errno.h>
- #include <linux/init.h>
- #include <linux/interrupt.h>
-+#include <linux/ioport.h>
- #include <linux/irq.h>
- #include <linux/module.h>
- #include <linux/smp.h>
-@@ -43,30 +43,22 @@
- #include <asm/irq_cpu.h>
- #include <asm/vr41xx/vr41xx.h>
-
--extern asmlinkage void vr41xx_handle_interrupt(void);
--
--extern void init_vr41xx_giuint_irq(void);
--extern void giuint_irq_dispatch(struct pt_regs *regs);
--
--static uint32_t icu1_base;
--static uint32_t icu2_base;
--
--static struct irqaction icu_cascade = {
-- .handler = no_action,
-- .mask = CPU_MASK_NONE,
-- .name = "cascade",
--};
-+static void __iomem *icu1_base;
-+static void __iomem *icu2_base;
-
- static unsigned char sysint1_assign[16] = {
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
- static unsigned char sysint2_assign[16] = {
-- 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
-+ 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
-
--#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080)
--#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200)
-+#define ICU1_TYPE1_BASE 0x0b000080UL
-+#define ICU2_TYPE1_BASE 0x0b000200UL
-
--#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080)
--#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0)
-+#define ICU1_TYPE2_BASE 0x0f000080UL
-+#define ICU2_TYPE2_BASE 0x0f0000a0UL
-+
-+#define ICU1_SIZE 0x20
-+#define ICU2_SIZE 0x1c
-
- #define SYSINT1REG 0x00
- #define PIUINTREG 0x02
-@@ -106,61 +98,61 @@ static unsigned char sysint2_assign[16]
- #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
- #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
-
--#define read_icu1(offset) readw(icu1_base + (offset))
--#define write_icu1(val, offset) writew((val), icu1_base + (offset))
-+#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
-+
-+#define icu1_read(offset) readw(icu1_base + (offset))
-+#define icu1_write(offset, value) writew((value), icu1_base + (offset))
-
--#define read_icu2(offset) readw(icu2_base + (offset))
--#define write_icu2(val, offset) writew((val), icu2_base + (offset))
-+#define icu2_read(offset) readw(icu2_base + (offset))
-+#define icu2_write(offset, value) writew((value), icu2_base + (offset))
-
- #define INTASSIGN_MAX 4
- #define INTASSIGN_MASK 0x0007
-
--static inline uint16_t set_icu1(uint8_t offset, uint16_t set)
-+static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
- {
-- uint16_t res;
-+ uint16_t data;
-
-- res = read_icu1(offset);
-- res |= set;
-- write_icu1(res, offset);
-+ data = icu1_read(offset);
-+ data |= set;
-+ icu1_write(offset, data);
-
-- return res;
-+ return data;
- }
-
--static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear)
-+static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
- {
-- uint16_t res;
-+ uint16_t data;
-
-- res = read_icu1(offset);
-- res &= ~clear;
-- write_icu1(res, offset);
-+ data = icu1_read(offset);
-+ data &= ~clear;
-+ icu1_write(offset, data);
-
-- return res;
-+ return data;
- }
-
--static inline uint16_t set_icu2(uint8_t offset, uint16_t set)
-+static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
- {
-- uint16_t res;
-+ uint16_t data;
-
-- res = read_icu2(offset);
-- res |= set;
-- write_icu2(res, offset);
-+ data = icu2_read(offset);
-+ data |= set;
-+ icu2_write(offset, data);
-
-- return res;
-+ return data;
- }
-
--static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear)
-+static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
- {
-- uint16_t res;
-+ uint16_t data;
-
-- res = read_icu2(offset);
-- res &= ~clear;
-- write_icu2(res, offset);
-+ data = icu2_read(offset);
-+ data &= ~clear;
-+ icu2_write(offset, data);
-
-- return res;
-+ return data;
- }
-
--/*=======================================================================*/
--
- void vr41xx_enable_piuint(uint16_t mask)
- {
- irq_desc_t *desc = irq_desc + PIU_IRQ;
-@@ -169,7 +161,7 @@ void vr41xx_enable_piuint(uint16_t mask)
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu1(MPIUINTREG, mask);
-+ icu1_set(MPIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -184,7 +176,7 @@ void vr41xx_disable_piuint(uint16_t mask
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu1(MPIUINTREG, mask);
-+ icu1_clear(MPIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -199,7 +191,7 @@ void vr41xx_enable_aiuint(uint16_t mask)
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu1(MAIUINTREG, mask);
-+ icu1_set(MAIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -214,7 +206,7 @@ void vr41xx_disable_aiuint(uint16_t mask
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu1(MAIUINTREG, mask);
-+ icu1_clear(MAIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -229,7 +221,7 @@ void vr41xx_enable_kiuint(uint16_t mask)
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu1(MKIUINTREG, mask);
-+ icu1_set(MKIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -244,7 +236,7 @@ void vr41xx_disable_kiuint(uint16_t mask
- if (current_cpu_data.cputype == CPU_VR4111 ||
- current_cpu_data.cputype == CPU_VR4121) {
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu1(MKIUINTREG, mask);
-+ icu1_clear(MKIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -257,7 +249,7 @@ void vr41xx_enable_dsiuint(uint16_t mask
- unsigned long flags;
-
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu1(MDSIUINTREG, mask);
-+ icu1_set(MDSIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
-
-@@ -269,7 +261,7 @@ void vr41xx_disable_dsiuint(uint16_t mas
- unsigned long flags;
-
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu1(MDSIUINTREG, mask);
-+ icu1_clear(MDSIUINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
-
-@@ -281,7 +273,7 @@ void vr41xx_enable_firint(uint16_t mask)
- unsigned long flags;
-
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu2(MFIRINTREG, mask);
-+ icu2_set(MFIRINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
-
-@@ -293,7 +285,7 @@ void vr41xx_disable_firint(uint16_t mask
- unsigned long flags;
-
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu2(MFIRINTREG, mask);
-+ icu2_clear(MFIRINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
-
-@@ -308,7 +300,7 @@ void vr41xx_enable_pciint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(PCIINT0, MPCIINTREG);
-+ icu2_write(MPCIINTREG, PCIINT0);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -324,7 +316,7 @@ void vr41xx_disable_pciint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(0, MPCIINTREG);
-+ icu2_write(MPCIINTREG, 0);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -340,7 +332,7 @@ void vr41xx_enable_scuint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(SCUINT0, MSCUINTREG);
-+ icu2_write(MSCUINTREG, SCUINT0);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -356,7 +348,7 @@ void vr41xx_disable_scuint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(0, MSCUINTREG);
-+ icu2_write(MSCUINTREG, 0);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -372,7 +364,7 @@ void vr41xx_enable_csiint(uint16_t mask)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- set_icu2(MCSIINTREG, mask);
-+ icu2_set(MCSIINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -388,7 +380,7 @@ void vr41xx_disable_csiint(uint16_t mask
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- clear_icu2(MCSIINTREG, mask);
-+ icu2_clear(MCSIINTREG, mask);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -404,7 +396,7 @@ void vr41xx_enable_bcuint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(BCUINTR, MBCUINTREG);
-+ icu2_write(MBCUINTREG, BCUINTR);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-@@ -420,30 +412,28 @@ void vr41xx_disable_bcuint(void)
- current_cpu_data.cputype == CPU_VR4131 ||
- current_cpu_data.cputype == CPU_VR4133) {
- spin_lock_irqsave(&desc->lock, flags);
-- write_icu2(0, MBCUINTREG);
-+ icu2_write(MBCUINTREG, 0);
- spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-
- EXPORT_SYMBOL(vr41xx_disable_bcuint);
-
--/*=======================================================================*/
--
- static unsigned int startup_sysint1_irq(unsigned int irq)
- {
-- set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
-+ icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
-
- return 0; /* never anything pending */
- }
-
- static void shutdown_sysint1_irq(unsigned int irq)
- {
-- clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
-+ icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
- }
-
- static void enable_sysint1_irq(unsigned int irq)
- {
-- set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
-+ icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
- }
-
- #define disable_sysint1_irq shutdown_sysint1_irq
-@@ -452,7 +442,7 @@ static void enable_sysint1_irq(unsigned
- static void end_sysint1_irq(unsigned int irq)
- {
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-- set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
-+ icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
- }
-
- static struct hw_interrupt_type sysint1_irq_type = {
-@@ -465,23 +455,21 @@ static struct hw_interrupt_type sysint1_
- .end = end_sysint1_irq,
- };
-
--/*=======================================================================*/
--
- static unsigned int startup_sysint2_irq(unsigned int irq)
- {
-- set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
-+ icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
-
- return 0; /* never anything pending */
- }
-
- static void shutdown_sysint2_irq(unsigned int irq)
- {
-- clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
-+ icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
- }
-
- static void enable_sysint2_irq(unsigned int irq)
- {
-- set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
-+ icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
- }
-
- #define disable_sysint2_irq shutdown_sysint2_irq
-@@ -490,7 +478,7 @@ static void enable_sysint2_irq(unsigned
- static void end_sysint2_irq(unsigned int irq)
- {
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-- set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
-+ icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
- }
-
- static struct hw_interrupt_type sysint2_irq_type = {
-@@ -503,8 +491,6 @@ static struct hw_interrupt_type sysint2_
- .end = end_sysint2_irq,
- };
-
--/*=======================================================================*/
--
- static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
- {
- irq_desc_t *desc = irq_desc + irq;
-@@ -515,8 +501,8 @@ static inline int set_sysint1_assign(uns
-
- spin_lock_irq(&desc->lock);
-
-- intassign0 = read_icu1(INTASSIGN0);
-- intassign1 = read_icu1(INTASSIGN1);
-+ intassign0 = icu1_read(INTASSIGN0);
-+ intassign1 = icu1_read(INTASSIGN1);
-
- switch (pin) {
- case 0:
-@@ -556,8 +542,8 @@ static inline int set_sysint1_assign(uns
- }
-
- sysint1_assign[pin] = assign;
-- write_icu1(intassign0, INTASSIGN0);
-- write_icu1(intassign1, INTASSIGN1);
-+ icu1_write(INTASSIGN0, intassign0);
-+ icu1_write(INTASSIGN1, intassign1);
-
- spin_unlock_irq(&desc->lock);
-
-@@ -574,8 +560,8 @@ static inline int set_sysint2_assign(uns
-
- spin_lock_irq(&desc->lock);
-
-- intassign2 = read_icu1(INTASSIGN2);
-- intassign3 = read_icu1(INTASSIGN3);
-+ intassign2 = icu1_read(INTASSIGN2);
-+ intassign3 = icu1_read(INTASSIGN3);
-
- switch (pin) {
- case 0:
-@@ -623,8 +609,8 @@ static inline int set_sysint2_assign(uns
- }
-
- sysint2_assign[pin] = assign;
-- write_icu1(intassign2, INTASSIGN2);
-- write_icu1(intassign3, INTASSIGN3);
-+ icu1_write(INTASSIGN2, intassign2);
-+ icu1_write(INTASSIGN3, intassign3);
-
- spin_unlock_irq(&desc->lock);
-
-@@ -651,88 +637,92 @@ int vr41xx_set_intassign(unsigned int ir
-
- EXPORT_SYMBOL(vr41xx_set_intassign);
-
--/*=======================================================================*/
--
--asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs)
-+static int icu_get_irq(unsigned int irq, struct pt_regs *regs)
- {
- uint16_t pend1, pend2;
- uint16_t mask1, mask2;
- int i;
-
-- pend1 = read_icu1(SYSINT1REG);
-- mask1 = read_icu1(MSYSINT1REG);
-+ pend1 = icu1_read(SYSINT1REG);
-+ mask1 = icu1_read(MSYSINT1REG);
-
-- pend2 = read_icu2(SYSINT2REG);
-- mask2 = read_icu2(MSYSINT2REG);
-+ pend2 = icu2_read(SYSINT2REG);
-+ mask2 = icu2_read(MSYSINT2REG);
-
- mask1 &= pend1;
- mask2 &= pend2;
-
- if (mask1) {
- for (i = 0; i < 16; i++) {
-- if (intnum == sysint1_assign[i] &&
-- (mask1 & ((uint16_t)1 << i))) {
-- if (i == 8)
-- giuint_irq_dispatch(regs);
-- else
-- do_IRQ(SYSINT1_IRQ(i), regs);
-- return;
-- }
-+ if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
-+ return SYSINT1_IRQ(i);
- }
- }
-
- if (mask2) {
- for (i = 0; i < 16; i++) {
-- if (intnum == sysint2_assign[i] &&
-- (mask2 & ((uint16_t)1 << i))) {
-- do_IRQ(SYSINT2_IRQ(i), regs);
-- return;
-- }
-+ if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
-+ return SYSINT2_IRQ(i);
- }
- }
-
- printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
-
- atomic_inc(&irq_err_count);
--}
-
--/*=======================================================================*/
-+ return -1;
-+}
-
- static int __init vr41xx_icu_init(void)
- {
-+ unsigned long icu1_start, icu2_start;
-+ int i;
-+
- switch (current_cpu_data.cputype) {
- case CPU_VR4111:
- case CPU_VR4121:
-- icu1_base = SYSINT1REG_TYPE1;
-- icu2_base = SYSINT2REG_TYPE1;
-+ icu1_start = ICU1_TYPE1_BASE;
-+ icu2_start = ICU2_TYPE1_BASE;
- break;
- case CPU_VR4122:
- case CPU_VR4131:
- case CPU_VR4133:
-- icu1_base = SYSINT1REG_TYPE2;
-- icu2_base = SYSINT2REG_TYPE2;
-+ icu1_start = ICU1_TYPE2_BASE;
-+ icu2_start = ICU2_TYPE2_BASE;
- break;
- default:
- printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
-- return -EINVAL;
-+ return -ENODEV;
- }
-
-- write_icu1(0, MSYSINT1REG);
-- write_icu1(0xffff, MGIUINTLREG);
-+ if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
-+ return -EBUSY;
-
-- write_icu2(0, MSYSINT2REG);
-- write_icu2(0xffff, MGIUINTHREG);
-+ if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
-+ release_mem_region(icu1_start, ICU1_SIZE);
-+ return -EBUSY;
-+ }
-
-- return 0;
--}
-+ icu1_base = ioremap(icu1_start, ICU1_SIZE);
-+ if (icu1_base == NULL) {
-+ release_mem_region(icu1_start, ICU1_SIZE);
-+ release_mem_region(icu2_start, ICU2_SIZE);
-+ return -ENOMEM;
-+ }
-
--early_initcall(vr41xx_icu_init);
-+ icu2_base = ioremap(icu2_start, ICU2_SIZE);
-+ if (icu2_base == NULL) {
-+ iounmap(icu1_base);
-+ release_mem_region(icu1_start, ICU1_SIZE);
-+ release_mem_region(icu2_start, ICU2_SIZE);
-+ return -ENOMEM;
-+ }
-
--/*=======================================================================*/
-+ icu1_write(MSYSINT1REG, 0);
-+ icu1_write(MGIUINTLREG, 0xffff);
-
--static inline void init_vr41xx_icu_irq(void)
--{
-- int i;
-+ icu2_write(MSYSINT2REG, 0);
-+ icu2_write(MGIUINTHREG, 0xffff);
-
- for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
- irq_desc[i].handler = &sysint1_irq_type;
-@@ -740,18 +730,13 @@ static inline void init_vr41xx_icu_irq(v
- for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
- irq_desc[i].handler = &sysint2_irq_type;
-
-- setup_irq(INT0_CASCADE_IRQ, &icu_cascade);
-- setup_irq(INT1_CASCADE_IRQ, &icu_cascade);
-- setup_irq(INT2_CASCADE_IRQ, &icu_cascade);
-- setup_irq(INT3_CASCADE_IRQ, &icu_cascade);
-- setup_irq(INT4_CASCADE_IRQ, &icu_cascade);
--}
-+ cascade_irq(INT0_IRQ, icu_get_irq);
-+ cascade_irq(INT1_IRQ, icu_get_irq);
-+ cascade_irq(INT2_IRQ, icu_get_irq);
-+ cascade_irq(INT3_IRQ, icu_get_irq);
-+ cascade_irq(INT4_IRQ, icu_get_irq);
-
--void __init arch_init_irq(void)
--{
-- mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
-- init_vr41xx_icu_irq();
-- init_vr41xx_giuint_irq();
--
-- set_except_vector(0, vr41xx_handle_interrupt);
-+ return 0;
- }
-+
-+core_initcall(vr41xx_icu_init);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/int-handler.S linux_HEAD/arch/mips/vr41xx/common/int-handler.S
---- linux-2.6.12/arch/mips/vr41xx/common/int-handler.S 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr41xx/common/int-handler.S 2005-07-01 12:09:20.000000000 +0200
-@@ -71,24 +71,24 @@
-
- andi t1, t0, CAUSEF_IP3 # check for Int1
- bnez t1, handle_int
-- li a0, 1
-+ li a0, 3
-
- andi t1, t0, CAUSEF_IP4 # check for Int2
- bnez t1, handle_int
-- li a0, 2
-+ li a0, 4
-
- andi t1, t0, CAUSEF_IP5 # check for Int3
- bnez t1, handle_int
-- li a0, 3
-+ li a0, 5
-
- andi t1, t0, CAUSEF_IP6 # check for Int4
- bnez t1, handle_int
-- li a0, 4
-+ li a0, 6
-
- 1:
- andi t1, t0, CAUSEF_IP2 # check for Int0
- bnez t1, handle_int
-- li a0, 0
-+ li a0, 2
-
- andi t1, t0, CAUSEF_IP0 # check for IP0
- bnez t1, handle_irq
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/irq.c linux_HEAD/arch/mips/vr41xx/common/irq.c
---- linux-2.6.12/arch/mips/vr41xx/common/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/vr41xx/common/irq.c 2005-06-02 16:37:13.000000000 +0200
-@@ -0,0 +1,86 @@
-+/*
-+ * Interrupt handing routines for NEC VR4100 series.
-+ *
-+ * Copyright (C) 2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/interrupt.h>
-+
-+#include <asm/irq_cpu.h>
-+#include <asm/system.h>
-+#include <asm/vr41xx/vr41xx.h>
-+
-+typedef struct irq_cascade {
-+ int (*get_irq)(unsigned int, struct pt_regs *);
-+} irq_cascade_t;
-+
-+static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
-+
-+static struct irqaction cascade_irqaction = {
-+ .handler = no_action,
-+ .mask = CPU_MASK_NONE,
-+ .name = "cascade",
-+};
-+
-+int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
-+{
-+ int retval = 0;
-+
-+ if (irq >= NR_IRQS)
-+ return -EINVAL;
-+
-+ if (irq_cascade[irq].get_irq != NULL)
-+ free_irq(irq, NULL);
-+
-+ irq_cascade[irq].get_irq = get_irq;
-+
-+ if (get_irq != NULL) {
-+ retval = setup_irq(irq, &cascade_irqaction);
-+ if (retval < 0)
-+ irq_cascade[irq].get_irq = NULL;
-+ }
-+
-+ return retval;
-+}
-+
-+asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
-+{
-+ irq_cascade_t *cascade;
-+
-+ if (irq >= NR_IRQS) {
-+ atomic_inc(&irq_err_count);
-+ return;
-+ }
-+
-+ cascade = irq_cascade + irq;
-+ if (cascade->get_irq != NULL) {
-+ irq = cascade->get_irq(irq, regs);
-+ if (irq < 0)
-+ atomic_inc(&irq_err_count);
-+ else
-+ irq_dispatch(irq, regs);
-+ } else
-+ do_IRQ(irq, regs);
-+}
-+
-+extern asmlinkage void vr41xx_handle_interrupt(void);
-+
-+void __init arch_init_irq(void)
-+{
-+ mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
-+
-+ set_except_vector(0, vr41xx_handle_interrupt);
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/ksyms.c linux_HEAD/arch/mips/vr41xx/common/ksyms.c
---- linux-2.6.12/arch/mips/vr41xx/common/ksyms.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/vr41xx/common/ksyms.c 2005-02-17 21:48:59.000000000 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * ksyms.c, Export NEC VR4100 series specific functions needed for loadable modules.
-+ *
-+ * Copyright (C) 2003 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-+ * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/module.h>
-+
-+#include <asm/vr41xx/vr41xx.h>
-+
-+EXPORT_SYMBOL(vr41xx_get_vtclock_frequency);
-+EXPORT_SYMBOL(vr41xx_get_tclock_frequency);
-+
-+EXPORT_SYMBOL(vr41xx_set_rtclong1_cycle);
-+EXPORT_SYMBOL(vr41xx_read_rtclong1_counter);
-+EXPORT_SYMBOL(vr41xx_set_rtclong2_cycle);
-+EXPORT_SYMBOL(vr41xx_read_rtclong2_counter);
-+EXPORT_SYMBOL(vr41xx_set_tclock_cycle);
-+EXPORT_SYMBOL(vr41xx_read_tclock_counter);
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/common/rtc.c linux_HEAD/arch/mips/vr41xx/common/rtc.c
---- linux-2.6.12/arch/mips/vr41xx/common/rtc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/arch/mips/vr41xx/common/rtc.c 2005-07-01 12:09:20.000000000 +0200
-@@ -0,0 +1,317 @@
-+/*
-+ * rtc.c, RTC(has only timer function) routines for NEC VR4100 series.
-+ *
-+ * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+#include <linux/smp.h>
-+#include <linux/types.h>
-+
-+#include <asm/io.h>
-+#include <asm/time.h>
-+#include <asm/vr41xx/vr41xx.h>
-+
-+static uint32_t rtc1_base;
-+static uint32_t rtc2_base;
-+
-+static uint64_t previous_elapsedtime;
-+static unsigned int remainder_per_sec;
-+static unsigned int cycles_per_sec;
-+static unsigned int cycles_per_jiffy;
-+static unsigned long epoch_time;
-+
-+#define CYCLES_PER_JIFFY (CLOCK_TICK_RATE / HZ)
-+#define REMAINDER_PER_SEC (CLOCK_TICK_RATE - (CYCLES_PER_JIFFY * HZ))
-+#define CYCLES_PER_100USEC ((CLOCK_TICK_RATE + (10000 / 2)) / 10000)
-+
-+#define ETIMELREG_TYPE1 KSEG1ADDR(0x0b0000c0)
-+#define TCLKLREG_TYPE1 KSEG1ADDR(0x0b0001c0)
-+
-+#define ETIMELREG_TYPE2 KSEG1ADDR(0x0f000100)
-+#define TCLKLREG_TYPE2 KSEG1ADDR(0x0f000120)
-+
-+/* RTC 1 registers */
-+#define ETIMELREG 0x00
-+#define ETIMEMREG 0x02
-+#define ETIMEHREG 0x04
-+/* RFU */
-+#define ECMPLREG 0x08
-+#define ECMPMREG 0x0a
-+#define ECMPHREG 0x0c
-+/* RFU */
-+#define RTCL1LREG 0x10
-+#define RTCL1HREG 0x12
-+#define RTCL1CNTLREG 0x14
-+#define RTCL1CNTHREG 0x16
-+#define RTCL2LREG 0x18
-+#define RTCL2HREG 0x1a
-+#define RTCL2CNTLREG 0x1c
-+#define RTCL2CNTHREG 0x1e
-+
-+/* RTC 2 registers */
-+#define TCLKLREG 0x00
-+#define TCLKHREG 0x02
-+#define TCLKCNTLREG 0x04
-+#define TCLKCNTHREG 0x06
-+/* RFU */
-+#define RTCINTREG 0x1e
-+ #define TCLOCK_INT 0x08
-+ #define RTCLONG2_INT 0x04
-+ #define RTCLONG1_INT 0x02
-+ #define ELAPSEDTIME_INT 0x01
-+
-+#define read_rtc1(offset) readw(rtc1_base + (offset))
-+#define write_rtc1(val, offset) writew((val), rtc1_base + (offset))
-+
-+#define read_rtc2(offset) readw(rtc2_base + (offset))
-+#define write_rtc2(val, offset) writew((val), rtc2_base + (offset))
-+
-+static inline uint64_t read_elapsedtime_counter(void)
-+{
-+ uint64_t first, second;
-+ uint32_t first_mid, first_low;
-+ uint32_t second_mid, second_low;
-+
-+ do {
-+ first_low = (uint32_t)read_rtc1(ETIMELREG);
-+ first_mid = (uint32_t)read_rtc1(ETIMEMREG);
-+ first = (uint64_t)read_rtc1(ETIMEHREG);
-+ second_low = (uint32_t)read_rtc1(ETIMELREG);
-+ second_mid = (uint32_t)read_rtc1(ETIMEMREG);
-+ second = (uint64_t)read_rtc1(ETIMEHREG);
-+ } while (first_low != second_low || first_mid != second_mid ||
-+ first != second);
-+
-+ return (first << 32) | (uint64_t)((first_mid << 16) | first_low);
-+}
-+
-+static inline void write_elapsedtime_counter(uint64_t time)
-+{
-+ write_rtc1((uint16_t)time, ETIMELREG);
-+ write_rtc1((uint16_t)(time >> 16), ETIMEMREG);
-+ write_rtc1((uint16_t)(time >> 32), ETIMEHREG);
-+}
-+
-+static inline void write_elapsedtime_compare(uint64_t time)
-+{
-+ write_rtc1((uint16_t)time, ECMPLREG);
-+ write_rtc1((uint16_t)(time >> 16), ECMPMREG);
-+ write_rtc1((uint16_t)(time >> 32), ECMPHREG);
-+}
-+
-+void vr41xx_set_rtclong1_cycle(uint32_t cycles)
-+{
-+ write_rtc1((uint16_t)cycles, RTCL1LREG);
-+ write_rtc1((uint16_t)(cycles >> 16), RTCL1HREG);
-+}
-+
-+uint32_t vr41xx_read_rtclong1_counter(void)
-+{
-+ uint32_t first_high, first_low;
-+ uint32_t second_high, second_low;
-+
-+ do {
-+ first_low = (uint32_t)read_rtc1(RTCL1CNTLREG);
-+ first_high = (uint32_t)read_rtc1(RTCL1CNTHREG);
-+ second_low = (uint32_t)read_rtc1(RTCL1CNTLREG);
-+ second_high = (uint32_t)read_rtc1(RTCL1CNTHREG);
-+ } while (first_low != second_low || first_high != second_high);
-+
-+ return (first_high << 16) | first_low;
-+}
-+
-+void vr41xx_set_rtclong2_cycle(uint32_t cycles)
-+{
-+ write_rtc1((uint16_t)cycles, RTCL2LREG);
-+ write_rtc1((uint16_t)(cycles >> 16), RTCL2HREG);
-+}
-+
-+uint32_t vr41xx_read_rtclong2_counter(void)
-+{
-+ uint32_t first_high, first_low;
-+ uint32_t second_high, second_low;
-+
-+ do {
-+ first_low = (uint32_t)read_rtc1(RTCL2CNTLREG);
-+ first_high = (uint32_t)read_rtc1(RTCL2CNTHREG);
-+ second_low = (uint32_t)read_rtc1(RTCL2CNTLREG);
-+ second_high = (uint32_t)read_rtc1(RTCL2CNTHREG);
-+ } while (first_low != second_low || first_high != second_high);
-+
-+ return (first_high << 16) | first_low;
-+}
-+
-+void vr41xx_set_tclock_cycle(uint32_t cycles)
-+{
-+ write_rtc2((uint16_t)cycles, TCLKLREG);
-+ write_rtc2((uint16_t)(cycles >> 16), TCLKHREG);
-+}
-+
-+uint32_t vr41xx_read_tclock_counter(void)
-+{
-+ uint32_t first_high, first_low;
-+ uint32_t second_high, second_low;
-+
-+ do {
-+ first_low = (uint32_t)read_rtc2(TCLKCNTLREG);
-+ first_high = (uint32_t)read_rtc2(TCLKCNTHREG);
-+ second_low = (uint32_t)read_rtc2(TCLKCNTLREG);
-+ second_high = (uint32_t)read_rtc2(TCLKCNTHREG);
-+ } while (first_low != second_low || first_high != second_high);
-+
-+ return (first_high << 16) | first_low;
-+}
-+
-+static void vr41xx_timer_ack(void)
-+{
-+ uint64_t cur;
-+
-+ write_rtc2(ELAPSEDTIME_INT, RTCINTREG);
-+
-+ previous_elapsedtime += (uint64_t)cycles_per_jiffy;
-+ cycles_per_sec += cycles_per_jiffy;
-+
-+ if (cycles_per_sec >= CLOCK_TICK_RATE) {
-+ cycles_per_sec = 0;
-+ remainder_per_sec = REMAINDER_PER_SEC;
-+ }
-+
-+ cycles_per_jiffy = 0;
-+
-+ do {
-+ cycles_per_jiffy += CYCLES_PER_JIFFY;
-+ if (remainder_per_sec > 0) {
-+ cycles_per_jiffy++;
-+ remainder_per_sec--;
-+ }
-+
-+ cur = read_elapsedtime_counter();
-+ } while (cur >= previous_elapsedtime + (uint64_t)cycles_per_jiffy);
-+
-+ write_elapsedtime_compare(previous_elapsedtime + (uint64_t)cycles_per_jiffy);
-+}
-+
-+static void vr41xx_hpt_init(unsigned int count)
-+{
-+}
-+
-+static unsigned int vr41xx_hpt_read(void)
-+{
-+ uint64_t cur;
-+
-+ cur = read_elapsedtime_counter();
-+
-+ return (unsigned int)cur;
-+}
-+
-+static unsigned long vr41xx_gettimeoffset(void)
-+{
-+ uint64_t cur;
-+ unsigned long gap;
-+
-+ cur = read_elapsedtime_counter();
-+ gap = (unsigned long)(cur - previous_elapsedtime);
-+ gap = gap / CYCLES_PER_100USEC * 100; /* usec */
-+
-+ return gap;
-+}
-+
-+static unsigned long vr41xx_get_time(void)
-+{
-+ uint64_t counts;
-+
-+ counts = read_elapsedtime_counter();
-+ counts >>= 15;
-+
-+ return epoch_time + (unsigned long)counts;
-+
-+}
-+
-+static int vr41xx_set_time(unsigned long sec)
-+{
-+ if (sec < epoch_time)
-+ return -EINVAL;
-+
-+ sec -= epoch_time;
-+
-+ write_elapsedtime_counter((uint64_t)sec << 15);
-+
-+ return 0;
-+}
-+
-+void vr41xx_set_epoch_time(unsigned long time)
-+{
-+ epoch_time = time;
-+}
-+
-+static void __init vr41xx_time_init(void)
-+{
-+ switch (current_cpu_data.cputype) {
-+ case CPU_VR4111:
-+ case CPU_VR4121:
-+ rtc1_base = ETIMELREG_TYPE1;
-+ rtc2_base = TCLKLREG_TYPE1;
-+ break;
-+ case CPU_VR4122:
-+ case CPU_VR4131:
-+ case CPU_VR4133:
-+ rtc1_base = ETIMELREG_TYPE2;
-+ rtc2_base = TCLKLREG_TYPE2;
-+ break;
-+ default:
-+ panic("Unexpected CPU of NEC VR4100 series");
-+ break;
-+ }
-+
-+ mips_timer_ack = vr41xx_timer_ack;
-+
-+ mips_hpt_init = vr41xx_hpt_init;
-+ mips_hpt_read = vr41xx_hpt_read;
-+ mips_hpt_frequency = CLOCK_TICK_RATE;
-+
-+ if (epoch_time == 0)
-+ epoch_time = mktime(1970, 1, 1, 0, 0, 0);
-+
-+ rtc_get_time = vr41xx_get_time;
-+ rtc_set_time = vr41xx_set_time;
-+}
-+
-+static void __init vr41xx_timer_setup(struct irqaction *irq)
-+{
-+ do_gettimeoffset = vr41xx_gettimeoffset;
-+
-+ remainder_per_sec = REMAINDER_PER_SEC;
-+ cycles_per_jiffy = CYCLES_PER_JIFFY;
-+
-+ if (remainder_per_sec > 0) {
-+ cycles_per_jiffy++;
-+ remainder_per_sec--;
-+ }
-+
-+ previous_elapsedtime = read_elapsedtime_counter();
-+ write_elapsedtime_compare(previous_elapsedtime + (uint64_t)cycles_per_jiffy);
-+ write_rtc2(ELAPSEDTIME_INT, RTCINTREG);
-+
-+ setup_irq(ELAPSEDTIME_IRQ, irq);
-+}
-+
-+static void __init vr41xx_rtc_init(void)
-+{
-+ board_time_init = vr41xx_time_init;
-+ board_timer_setup = vr41xx_timer_setup;
-+}
-diff -urpNX dontdiff linux-2.6.12/arch/mips/vr41xx/nec-cmbvr4133/setup.c linux_HEAD/arch/mips/vr41xx/nec-cmbvr4133/setup.c
---- linux-2.6.12/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2005-07-01 12:09:20.000000000 +0200
-@@ -16,6 +16,7 @@
- */
- #include <linux/config.h>
- #include <linux/init.h>
-+#include <linux/console.h>
- #include <linux/ide.h>
- #include <linux/ioport.h>
-
-@@ -36,13 +37,13 @@ static struct mtd_partition cmbvr4133_mt
- .size = 0x1be0000,
- .offset = 0,
- .mask_flags = 0,
-- },
-+ },
- {
- .name = "PMON",
- .size = 0x140000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
-- },
-+ },
- {
- .name = "User FS2",
- .size = MTDPART_SIZ_FULL,
-@@ -56,7 +57,7 @@ static struct mtd_partition cmbvr4133_mt
-
- extern void i8259_init(void);
-
--static int __init nec_cmbvr4133_setup(void)
-+static void __init nec_cmbvr4133_setup(void)
- {
- #ifdef CONFIG_ROCKHOPPER
- extern void disable_pcnet(void);
-@@ -90,7 +91,4 @@ static int __init nec_cmbvr4133_setup(vo
- #ifdef CONFIG_ROCKHOPPER
- i8259_init();
- #endif
-- return 0;
- }
--
--early_initcall(nec_cmbvr4133_setup);
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/abi.h linux_HEAD/include/asm-mips/abi.h
---- linux-2.6.12/include/asm-mips/abi.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/abi.h 2005-05-31 13:49:19.000000000 +0200
-@@ -0,0 +1,25 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005 by Ralf Baechle
-+ * Copyright (C) 2005 MIPS Technologies, Inc.
-+ */
-+#ifndef _ASM_ABI_H
-+#define _ASM_ABI_H
-+
-+#include <asm/signal.h>
-+#include <asm/siginfo.h>
-+
-+struct mips_abi {
-+ int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs);
-+ void (* const setup_frame)(struct k_sigaction * ka,
-+ struct pt_regs *regs, int signr,
-+ sigset_t *set);
-+ void (* const setup_rt_frame)(struct k_sigaction * ka,
-+ struct pt_regs *regs, int signr,
-+ sigset_t *set, siginfo_t *info);
-+};
-+
-+#endif /* _ASM_ABI_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/addrspace.h linux_HEAD/include/asm-mips/addrspace.h
---- linux-2.6.12/include/asm-mips/addrspace.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/addrspace.h 2005-07-10 12:16:34.000000000 +0200
-@@ -20,10 +20,12 @@
- #define _ATYPE_
- #define _ATYPE32_
- #define _ATYPE64_
-+#define _LLCONST_(x) x
- #else
- #define _ATYPE_ __PTRDIFF_TYPE__
- #define _ATYPE32_ int
- #define _ATYPE64_ long long
-+#define _LLCONST_(x) x ## LL
- #endif
-
- /*
-@@ -45,8 +47,9 @@
- /*
- * Returns the physical address of a CKSEGx / XKPHYS address
- */
--#define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff)
--#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff)
-+#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
-+#define XPHYSADDR(a) ((_ACAST64_(a)) & \
-+ _LLCONST_(0x000000ffffffffff))
-
- #ifdef CONFIG_MIPS64
-
-@@ -55,14 +58,14 @@
- * The compatibility segments use the full 64-bit sign extended value. Note
- * the R8000 doesn't have them so don't reference these in generic MIPS code.
- */
--#define XKUSEG 0x0000000000000000
--#define XKSSEG 0x4000000000000000
--#define XKPHYS 0x8000000000000000
--#define XKSEG 0xc000000000000000
--#define CKSEG0 0xffffffff80000000
--#define CKSEG1 0xffffffffa0000000
--#define CKSSEG 0xffffffffc0000000
--#define CKSEG3 0xffffffffe0000000
-+#define XKUSEG _LLCONST_(0x0000000000000000)
-+#define XKSSEG _LLCONST_(0x4000000000000000)
-+#define XKPHYS _LLCONST_(0x8000000000000000)
-+#define XKSEG _LLCONST_(0xc000000000000000)
-+#define CKSEG0 _LLCONST_(0xffffffff80000000)
-+#define CKSEG1 _LLCONST_(0xffffffffa0000000)
-+#define CKSSEG _LLCONST_(0xffffffffc0000000)
-+#define CKSEG3 _LLCONST_(0xffffffffe0000000)
-
- #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
- #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
-@@ -120,54 +123,55 @@
- #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
- #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
- #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
--#define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a))
-+#define PHYS_TO_XKPHYS(cm,a) (_LLCONST_(0x8000000000000000) | \
-+ ((cm)<<59) | (a))
-
- #if defined (CONFIG_CPU_R4300) \
- || defined (CONFIG_CPU_R4X00) \
- || defined (CONFIG_CPU_R5000) \
- || defined (CONFIG_CPU_NEVADA) \
- || defined (CONFIG_CPU_TX49XX) \
-- || defined (CONFIG_CPU_MIPS64)
--#define KUSIZE 0x0000010000000000 /* 2^^40 */
--#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
--#define K0SIZE 0x0000001000000000 /* 2^^36 */
--#define K1SIZE 0x0000001000000000 /* 2^^36 */
--#define K2SIZE 0x000000ff80000000
--#define KSEGSIZE 0x000000ff80000000 /* max syssegsz */
--#define TO_PHYS_MASK 0x0000000fffffffff /* 2^^36 - 1 */
-+ || defined (CONFIG_CPU_MIPS64_R1)
-+#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
-+#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
-+#define K2SIZE _LLCONST_(0x000000ff80000000)
-+#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */
-+#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */
- #endif
-
- #if defined (CONFIG_CPU_R8000)
- /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
--#define KUSIZE 0x0000010000000000 /* 2^^40 */
--#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
--#define K0SIZE 0x0000010000000000 /* 2^^40 */
--#define K1SIZE 0x0000010000000000 /* 2^^40 */
--#define K2SIZE 0x0001000000000000
--#define KSEGSIZE 0x0000010000000000 /* max syssegsz */
--#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */
-+#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K2SIZE _LLCONST_(0x0001000000000000)
-+#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */
-+#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
- #endif
-
- #if defined (CONFIG_CPU_R10000)
--#define KUSIZE 0x0000010000000000 /* 2^^40 */
--#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
--#define K0SIZE 0x0000010000000000 /* 2^^40 */
--#define K1SIZE 0x0000010000000000 /* 2^^40 */
--#define K2SIZE 0x00000fff80000000
--#define KSEGSIZE 0x00000fff80000000 /* max syssegsz */
--#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */
-+#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
-+#define K2SIZE _LLCONST_(0x00000fff80000000)
-+#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */
-+#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
- #endif
-
- /*
- * Further names for SGI source compatibility. These are stolen from
- * IRIX's <sys/mips_addrspace.h>.
- */
--#define KUBASE 0
--#define KUSIZE_32 0x0000000080000000 /* KUSIZE
-+#define KUBASE _LLCONST_(0)
-+#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE
- for a 32 bit proc */
--#define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */
--#define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */
--#define K0BASE_EXL 0xa000000000000000 /* exclusive */
-+#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */
-+#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */
-+#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */
-
- #ifndef CONFIG_CPU_R8000
-
-@@ -176,7 +180,7 @@
- * in order to catch bugs in the source code.
- */
-
--#define COMPAT_K1BASE32 0xffffffffa0000000
-+#define COMPAT_K1BASE32 _LLCONST_(0xffffffffa0000000)
- #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-
- #endif
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/asm.h linux_HEAD/include/asm-mips/asm.h
---- linux-2.6.12/include/asm-mips/asm.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/asm.h 2005-07-01 12:10:27.000000000 +0200
-@@ -107,6 +107,7 @@ symbol = value
- /*
- * Print formatted string
- */
-+#ifdef CONFIG_PRINTK
- #define PRINT(string) \
- .set push; \
- .set reorder; \
-@@ -114,6 +115,9 @@ symbol = value
- jal printk; \
- .set pop; \
- TEXT(string)
-+#else
-+#define PRINT(string)
-+#endif
-
- #define TEXT(msg) \
- .pushsection .data; \
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/atomic.h linux_HEAD/include/asm-mips/atomic.h
---- linux-2.6.12/include/asm-mips/atomic.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/atomic.h 2005-07-01 12:10:27.000000000 +0200
-@@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i,
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
-@@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i,
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
-@@ -136,12 +144,14 @@ static __inline__ int atomic_add_return(
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -149,12 +159,14 @@ static __inline__ int atomic_add_return(
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 1b \n"
- " addu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return(
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return(
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 1b \n"
- " subu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_posi
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_if_positive\n"
- " subu %0, %1, %3 \n"
- " bltz %0, 1f \n"
-@@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_posi
- " beqzl %0, 1b \n"
- " sync \n"
- "1: \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_posi
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_if_positive\n"
- " subu %0, %1, %3 \n"
- " bltz %0, 1f \n"
-@@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_posi
- " beqz %0, 1b \n"
- " sync \n"
- "1: \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " addu %0, %2 \n"
- " scd %0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " addu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
-@@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " subu %0, %2 \n"
- " scd %0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else if (cpu_has_llsc) {
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " subu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
- } else {
-@@ -441,12 +469,14 @@ static __inline__ long atomic64_add_retu
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " addu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -454,12 +484,14 @@ static __inline__ long atomic64_add_retu
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " addu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 1b \n"
- " addu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_retu
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " subu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_retu
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " subu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 1b \n"
- " subu %0, %1, %3 \n"
- " sync \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_p
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_if_positive\n"
- " dsubu %0, %1, %3 \n"
- " bltz %0, 1f \n"
-@@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_p
- " beqzl %0, 1b \n"
- " sync \n"
- "1: \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-@@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_p
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_if_positive\n"
- " dsubu %0, %1, %3 \n"
- " bltz %0, 1f \n"
-@@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_p
- " beqz %0, 1b \n"
- " sync \n"
- "1: \n"
-+ " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/bitops.h linux_HEAD/include/asm-mips/bitops.h
---- linux-2.6.12/include/asm-mips/bitops.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/bitops.h 2005-07-01 12:10:27.000000000 +0200
-@@ -18,14 +18,14 @@
- #if (_MIPS_SZLONG == 32)
- #define SZLONG_LOG 5
- #define SZLONG_MASK 31UL
--#define __LL "ll "
--#define __SC "sc "
-+#define __LL "ll "
-+#define __SC "sc "
- #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
- #elif (_MIPS_SZLONG == 64)
- #define SZLONG_LOG 6
- #define SZLONG_MASK 63UL
--#define __LL "lld "
--#define __SC "scd "
-+#define __LL "lld "
-+#define __SC "scd "
- #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
- #endif
-
-@@ -72,18 +72,22 @@ static inline void set_bit(unsigned long
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
-- " "__SC "%0, %1 \n"
-+ " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
-- " "__SC "%0, %1 \n"
-+ " " __SC "%0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
- } else {
-@@ -132,18 +136,22 @@ static inline void clear_bit(unsigned lo
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
- } else {
-@@ -191,10 +199,12 @@ static inline void change_bit(unsigned l
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
-- " "__SC "%0, %1 \n"
-+ " " __SC "%0, %1 \n"
- " beqzl %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
- } else if (cpu_has_llsc) {
-@@ -202,10 +212,12 @@ static inline void change_bit(unsigned l
- unsigned long temp;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
-- " "__SC "%0, %1 \n"
-+ " " __SC "%0, %1 \n"
- " beqz %0, 1b \n"
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
- } else {
-@@ -253,14 +265,16 @@ static inline int test_and_set_bit(unsig
- unsigned long temp, res;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
-- "sync \n"
-+ " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-@@ -271,16 +285,18 @@ static inline int test_and_set_bit(unsig
- unsigned long temp, res;
-
- __asm__ __volatile__(
-- " .set noreorder # test_and_set_bit \n"
-- "1: " __LL "%0, %1 \n"
-+ " .set push \n"
-+ " .set noreorder \n"
-+ " .set mips3 \n"
-+ "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
-- "sync \n"
-+ " sync \n"
- #endif
-- ".set\treorder"
-+ " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-@@ -343,15 +359,17 @@ static inline int test_and_clear_bit(uns
- unsigned long temp, res;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
-- __SC "%2, %1 \n"
-+ " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-@@ -362,17 +380,19 @@ static inline int test_and_clear_bit(uns
- unsigned long temp, res;
-
- __asm__ __volatile__(
-- " .set noreorder # test_and_clear_bit \n"
-- "1: " __LL "%0, %1 \n"
-+ " .set push \n"
-+ " .set noreorder \n"
-+ " .set mips3 \n"
-+ "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
-- __SC "%2, %1 \n"
-+ " " __SC "%2, %1 \n"
- " beqz %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-- " .set reorder \n"
-+ " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-@@ -435,14 +455,16 @@ static inline int test_and_change_bit(un
- unsigned long temp, res;
-
- __asm__ __volatile__(
-- "1: " __LL " %0, %1 # test_and_change_bit \n"
-+ " .set mips3 \n"
-+ "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
-- " "__SC "%2, %1 \n"
-+ " " __SC "%2, %1 \n"
- " beqzl %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-@@ -453,16 +475,18 @@ static inline int test_and_change_bit(un
- unsigned long temp, res;
-
- __asm__ __volatile__(
-- " .set noreorder # test_and_change_bit \n"
-- "1: " __LL " %0, %1 \n"
-+ " .set push \n"
-+ " .set noreorder \n"
-+ " .set mips3 \n"
-+ "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
-- " "__SC "\t%2, %1 \n"
-+ " " __SC "\t%2, %1 \n"
- " beqz %2, 1b \n"
- " and %2, %0, %3 \n"
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-- " .set reorder \n"
-+ " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
- : "memory");
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/bootinfo.h linux_HEAD/include/asm-mips/bootinfo.h
---- linux-2.6.12/include/asm-mips/bootinfo.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/bootinfo.h 2005-07-08 12:04:09.000000000 +0200
-@@ -77,6 +77,7 @@
- #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
- #define MACH_SGI_IP28 2 /* Indigo2 Impact */
- #define MACH_SGI_IP32 3 /* O2 */
-+#define MACH_SGI_IP30 4 /* Octane, Octane2 */
-
- /*
- * Valid machtype for group COBALT
-@@ -177,6 +178,8 @@
- #define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
- #define MACH_PB1550 8 /* Au1550-based eval board */
- #define MACH_DB1550 9 /* Au1550-based eval board */
-+#define MACH_PB1200 10 /* Au1200-based eval board */
-+#define MACH_DB1200 11 /* Au1200-based eval board */
-
- /*
- * Valid machtype for group NEC_VR41XX
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/break.h linux_HEAD/include/asm-mips/break.h
---- linux-2.6.12/include/asm-mips/break.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/break.h 2005-02-17 21:50:43.000000000 +0100
-@@ -28,6 +28,7 @@
- #define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */
- #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
- #define BRK_BUG 512 /* Used by BUG() */
-+#define BRK_KDB 513 /* Used in KDB_ENTER() */
- #define BRK_MULOVF 1023 /* Multiply overflow */
-
- #endif /* __ASM_BREAK_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/bug.h linux_HEAD/include/asm-mips/bug.h
---- linux-2.6.12/include/asm-mips/bug.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/bug.h 2005-07-01 12:10:27.000000000 +0200
-@@ -1,16 +1,21 @@
- #ifndef __ASM_BUG_H
- #define __ASM_BUG_H
-
--#include <asm/break.h>
-+#include <linux/config.h>
-
- #ifdef CONFIG_BUG
--#define HAVE_ARCH_BUG
-+
-+#include <asm/break.h>
-+
- #define BUG() \
- do { \
- __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \
- } while (0)
-+
-+#define HAVE_ARCH_BUG
-+
- #endif
-
- #include <asm-generic/bug.h>
-
--#endif
-+#endif /* __ASM_BUG_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/bugs.h linux_HEAD/include/asm-mips/bugs.h
---- linux-2.6.12/include/asm-mips/bugs.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/bugs.h 2005-04-13 19:06:39.000000000 +0200
-@@ -8,12 +8,18 @@
- #define _ASM_BUGS_H
-
- #include <linux/config.h>
-+#include <linux/delay.h>
-+#include <asm/cpu.h>
-+#include <asm/cpu-info.h>
-
- extern void check_bugs32(void);
- extern void check_bugs64(void);
-
- static inline void check_bugs(void)
- {
-+ unsigned int cpu = smp_processor_id();
-+
-+ cpu_data[cpu].udelay_val = loops_per_jiffy;
- check_bugs32();
- #ifdef CONFIG_MIPS64
- check_bugs64();
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cacheflush.h linux_HEAD/include/asm-mips/cacheflush.h
---- linux-2.6.12/include/asm-mips/cacheflush.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/cacheflush.h 2005-04-25 13:23:05.000000000 +0200
-@@ -49,17 +49,29 @@ static inline void flush_dcache_page(str
-
- extern void (*flush_icache_page)(struct vm_area_struct *vma,
- struct page *page);
--extern void (*flush_icache_range)(unsigned long start, unsigned long end);
-+extern void (*flush_icache_range)(unsigned long __user start,
-+ unsigned long __user end);
- #define flush_cache_vmap(start, end) flush_cache_all()
- #define flush_cache_vunmap(start, end) flush_cache_all()
-
--#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
--do { \
-- memcpy(dst, (void *) src, len); \
-- flush_icache_page(vma, page); \
--} while (0)
--#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-- memcpy(dst, src, len)
-+static inline void copy_to_user_page(struct vm_area_struct *vma,
-+ struct page *page, unsigned long vaddr, void *dst, const void *src,
-+ unsigned long len)
-+{
-+ if (cpu_has_dc_aliases)
-+ flush_cache_page(vma, vaddr, page_to_pfn(page));
-+ memcpy(dst, src, len);
-+ flush_icache_page(vma, page);
-+}
-+
-+static inline void copy_from_user_page(struct vm_area_struct *vma,
-+ struct page *page, unsigned long vaddr, void *dst, const void *src,
-+ unsigned long len)
-+{
-+ if (cpu_has_dc_aliases)
-+ flush_cache_page(vma, vaddr, page_to_pfn(page));
-+ memcpy(dst, src, len);
-+}
-
- extern void (*flush_cache_sigtramp)(unsigned long addr);
- extern void (*flush_icache_all)(void);
-@@ -78,4 +90,7 @@ extern void (*flush_data_cache_page)(uns
- #define ClearPageDcacheDirty(page) \
- clear_bit(PG_dcache_dirty, &(page)->flags)
-
-+/* Run kernel code uncached, useful for cache probing functions. */
-+unsigned long __init run_uncached(void *func);
-+
- #endif /* _ASM_CACHEFLUSH_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/checksum.h linux_HEAD/include/asm-mips/checksum.h
---- linux-2.6.12/include/asm-mips/checksum.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/checksum.h 2005-07-08 12:02:03.000000000 +0200
-@@ -70,14 +70,15 @@ unsigned int csum_partial_copy_nocheck(c
- static inline unsigned short int csum_fold(unsigned int sum)
- {
- __asm__(
-- ".set\tnoat\t\t\t# csum_fold\n\t"
-- "sll\t$1,%0,16\n\t"
-- "addu\t%0,$1\n\t"
-- "sltu\t$1,%0,$1\n\t"
-- "srl\t%0,%0,16\n\t"
-- "addu\t%0,$1\n\t"
-- "xori\t%0,0xffff\n\t"
-- ".set\tat"
-+ " .set push # csum_fold\n"
-+ " .set noat \n"
-+ " sll $1, %0, 16 \n"
-+ " addu %0, $1 \n"
-+ " sltu $1, %0, $1 \n"
-+ " srl %0, %0, 16 \n"
-+ " addu %0, $1 \n"
-+ " xori %0, 0xffff \n"
-+ " .set pop"
- : "=r" (sum)
- : "0" (sum));
-
-@@ -127,29 +128,30 @@ static inline unsigned int csum_tcpudp_n
- unsigned int sum)
- {
- __asm__(
-- ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
-+ " .set push # csum_tcpudp_nofold\n"
-+ " .set noat \n"
- #ifdef CONFIG_MIPS32
-- "addu\t%0, %2\n\t"
-- "sltu\t$1, %0, %2\n\t"
-- "addu\t%0, $1\n\t"
--
-- "addu\t%0, %3\n\t"
-- "sltu\t$1, %0, %3\n\t"
-- "addu\t%0, $1\n\t"
--
-- "addu\t%0, %4\n\t"
-- "sltu\t$1, %0, %4\n\t"
-- "addu\t%0, $1\n\t"
-+ " addu %0, %2 \n"
-+ " sltu $1, %0, %2 \n"
-+ " addu %0, $1 \n"
-+
-+ " addu %0, %3 \n"
-+ " sltu $1, %0, %3 \n"
-+ " addu %0, $1 \n"
-+
-+ " addu %0, %4 \n"
-+ " sltu $1, %0, %4 \n"
-+ " addu %0, $1 \n"
- #endif
- #ifdef CONFIG_MIPS64
-- "daddu\t%0, %2\n\t"
-- "daddu\t%0, %3\n\t"
-- "daddu\t%0, %4\n\t"
-- "dsll32\t$1, %0, 0\n\t"
-- "daddu\t%0, $1\n\t"
-- "dsrl32\t%0, %0, 0\n\t"
-+ " daddu %0, %2 \n"
-+ " daddu %0, %3 \n"
-+ " daddu %0, %4 \n"
-+ " dsll32 $1, %0, 0 \n"
-+ " daddu %0, $1 \n"
-+ " dsrl32 %0, %0, 0 \n"
- #endif
-- ".set\tat"
-+ " .set pop"
- : "=r" (sum)
- : "0" (daddr), "r"(saddr),
- #ifdef __MIPSEL__
-@@ -192,57 +194,57 @@ static __inline__ unsigned short int csu
- unsigned int sum)
- {
- __asm__(
-- ".set\tpush\t\t\t# csum_ipv6_magic\n\t"
-- ".set\tnoreorder\n\t"
-- ".set\tnoat\n\t"
-- "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"
-- "sltu\t$1, %0, %5\n\t"
-- "addu\t%0, $1\n\t"
--
-- "addu\t%0, %6\t\t\t# csum\n\t"
-- "sltu\t$1, %0, %6\n\t"
-- "lw\t%1, 0(%2)\t\t\t# four words source address\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 4(%2)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 8(%2)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 12(%2)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 0(%3)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 4(%3)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 8(%3)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
--
-- "lw\t%1, 12(%3)\n\t"
-- "addu\t%0, $1\n\t"
-- "addu\t%0, %1\n\t"
-- "sltu\t$1, %0, %1\n\t"
-+ " .set push # csum_ipv6_magic\n"
-+ " .set noreorder \n"
-+ " .set noat \n"
-+ " addu %0, %5 # proto (long in network byte order)\n"
-+ " sltu $1, %0, %5 \n"
-+ " addu %0, $1 \n"
-+
-+ " addu %0, %6 # csum\n"
-+ " sltu $1, %0, %6 \n"
-+ " lw %1, 0(%2) # four words source address\n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 4(%2) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 8(%2) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 12(%2) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 0(%3) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 4(%3) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 8(%3) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-+
-+ " lw %1, 12(%3) \n"
-+ " addu %0, $1 \n"
-+ " addu %0, %1 \n"
-+ " sltu $1, %0, %1 \n"
-
-- "addu\t%0, $1\t\t\t# Add final carry\n\t"
-- ".set\tpop"
-+ " addu %0, $1 # Add final carry\n"
-+ " .set pop"
- : "=r" (sum), "=r" (proto)
- : "r" (saddr), "r" (daddr),
- "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cobalt/cobalt.h linux_HEAD/include/asm-mips/cobalt/cobalt.h
---- linux-2.6.12/include/asm-mips/cobalt/cobalt.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/cobalt/cobalt.h 2005-04-12 15:08:08.000000000 +0200
-@@ -19,18 +19,23 @@
- * 9 - PCI
- * 14 - IDE0
- * 15 - IDE1
-- *
-+ */
-+#define COBALT_QUBE_SLOT_IRQ 9
-+
-+/*
- * CPU IRQs are 16 ... 23
- */
--#define COBALT_TIMER_IRQ 18
--#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */
--#define COBALT_RAQ_SCSI_IRQ 19
--#define COBALT_ETH0_IRQ 19
--#define COBALT_ETH1_IRQ 20
--#define COBALT_SERIAL_IRQ 21
--#define COBALT_SCSI_IRQ 21
--#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */
--#define COBALT_QUBE_SLOT_IRQ 23
-+#define COBALT_CPU_IRQ 16
-+
-+#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
-+#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
-+#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
-+#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
-+#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
-+#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
-+#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
-+#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
-+#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
-
- /*
- * PCI configuration space manifest constants. These are wired into
-@@ -69,16 +74,21 @@
- * Most of this really should go into a separate GT64111 header file.
- */
- #define GT64111_IO_BASE 0x10000000UL
-+#define GT64111_IO_END 0x11ffffffUL
-+#define GT64111_MEM_BASE 0x12000000UL
-+#define GT64111_MEM_END 0x13ffffffUL
- #define GT64111_BASE 0x14000000UL
--#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
-+#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
-
- #define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
- #define GALILEO_OUTL(val, port) \
- do { \
-- *(volatile unsigned int *) GALILEO_REG(port) = (port); \
-+ *(volatile unsigned int *) GALILEO_REG(port) = (val); \
- } while (0)
-
--#define GALILEO_T0EXP 0x0100
-+#define GALILEO_INTR_T0EXP (1 << 8)
-+#define GALILEO_INTR_RETRY_CTR (1 << 20)
-+
- #define GALILEO_ENTC0 0x01
- #define GALILEO_SELTC0 0x02
-
-@@ -86,5 +96,21 @@ do { \
- GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
- (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
-
-+#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
-+# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
-+# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
-+# define COBALT_LED_WEB (1 << 2) /* RaQ */
-+# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */
-+# define COBALT_LED_RESET 0x0f
-+
-+#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
-+# define COBALT_KEY_CLEAR (1 << 1)
-+# define COBALT_KEY_LEFT (1 << 2)
-+# define COBALT_KEY_UP (1 << 3)
-+# define COBALT_KEY_DOWN (1 << 4)
-+# define COBALT_KEY_RIGHT (1 << 5)
-+# define COBALT_KEY_ENTER (1 << 6)
-+# define COBALT_KEY_SELECT (1 << 7)
-+# define COBALT_KEY_MASK 0xfe
-
- #endif /* __ASM_COBALT_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cobalt/mach-gt64120.h linux_HEAD/include/asm-mips/cobalt/mach-gt64120.h
---- linux-2.6.12/include/asm-mips/cobalt/mach-gt64120.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/cobalt/mach-gt64120.h 2005-02-21 17:24:02.000000000 +0100
-@@ -0,0 +1 @@
-+/* there's something here ... in the dark */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cpu-features.h linux_HEAD/include/asm-mips/cpu-features.h
---- linux-2.6.12/include/asm-mips/cpu-features.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/cpu-features.h 2005-07-01 12:10:27.000000000 +0200
-@@ -4,6 +4,7 @@
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
-+ * Copyright (C) 2004 Maciej W. Rozycki
- */
- #ifndef __ASM_CPU_FEATURES_H
- #define __ASM_CPU_FEATURES_H
-@@ -39,9 +40,6 @@
- #ifndef cpu_has_watch
- #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
- #endif
--#ifndef cpu_has_mips16
--#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
--#endif
- #ifndef cpu_has_divec
- #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
- #endif
-@@ -66,6 +64,18 @@
- #ifndef cpu_has_llsc
- #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
- #endif
-+#ifndef cpu_has_mips16
-+#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
-+#endif
-+#ifndef cpu_has_mdmx
-+#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
-+#endif
-+#ifndef cpu_has_mips3d
-+#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
-+#endif
-+#ifndef cpu_has_smartmips
-+#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
-+#endif
- #ifndef cpu_has_vtag_icache
- #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
- #endif
-@@ -95,15 +105,8 @@
- #endif
- #endif
-
--/*
-- * Certain CPUs may throw bizarre exceptions if not the whole cacheline
-- * contains valid instructions. For these we ensure proper alignment of
-- * signal trampolines and pad them to the size of a full cache lines with
-- * nops. This is also used in structure definitions so can't be a test macro
-- * like the others.
-- */
--#ifndef PLAT_TRAMPOLINE_STUFF_LINE
--#define PLAT_TRAMPOLINE_STUFF_LINE 0UL
-+#ifndef cpu_has_dsp
-+#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
- #endif
-
- #ifdef CONFIG_MIPS32
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cpu-info.h linux_HEAD/include/asm-mips/cpu-info.h
---- linux-2.6.12/include/asm-mips/cpu-info.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/cpu-info.h 2005-05-09 13:21:09.000000000 +0200
-@@ -7,6 +7,7 @@
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
-+ * Copyright (C) 2004 Maciej W. Rozycki
- */
- #ifndef __ASM_CPU_INFO_H
- #define __ASM_CPU_INFO_H
-@@ -61,6 +62,7 @@ struct cpuinfo_mips {
- * Capability and feature descriptor structure for MIPS CPU
- */
- unsigned long options;
-+ unsigned long ases;
- unsigned int processor_id;
- unsigned int fpu_id;
- unsigned int cputype;
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/cpu.h linux_HEAD/include/asm-mips/cpu.h
---- linux-2.6.12/include/asm-mips/cpu.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/cpu.h 2005-07-01 12:10:27.000000000 +0200
-@@ -3,6 +3,7 @@
- * various MIPS cpu types.
- *
- * Copyright (C) 1996 David S. Miller (dm at engr.sgi.com)
-+ * Copyright (C) 2004 Maciej W. Rozycki
- */
- #ifndef _ASM_CPU_H
- #define _ASM_CPU_H
-@@ -22,12 +23,17 @@
- spec.
- */
-
--#define PRID_COMP_LEGACY 0x000000
--#define PRID_COMP_MIPS 0x010000
--#define PRID_COMP_BROADCOM 0x020000
--#define PRID_COMP_ALCHEMY 0x030000
--#define PRID_COMP_SIBYTE 0x040000
--#define PRID_COMP_SANDCRAFT 0x050000
-+#define PRID_COMP_LEGACY 0x000000
-+#define PRID_COMP_MIPS 0x010000
-+#define PRID_COMP_BROADCOM 0x020000
-+#define PRID_COMP_ALCHEMY 0x030000
-+#define PRID_COMP_SIBYTE 0x040000
-+#define PRID_COMP_SANDCRAFT 0x050000
-+#define PRID_COMP_PHILIPS 0x060000
-+#define PRID_COMP_TOSHIBA 0x070000
-+#define PRID_COMP_LSI 0x080000
-+#define PRID_COMP_LEXRA 0x0b0000
-+
-
- /*
- * Assigned values for the product ID register. In order to detect a
-@@ -71,6 +77,7 @@
- #define PRID_IMP_4KEMPR2 0x9100
- #define PRID_IMP_4KSD 0x9200
- #define PRID_IMP_24K 0x9300
-+#define PRID_IMP_24KE 0x9600
-
- #define PRID_IMP_UNKNOWN 0xff00
-
-@@ -177,7 +184,8 @@
- #define CPU_VR4133 56
- #define CPU_AU1550 57
- #define CPU_24K 58
--#define CPU_LAST 58
-+#define CPU_AU1200 59
-+#define CPU_LAST 59
-
- /*
- * ISA Level encodings
-@@ -207,7 +215,6 @@
- #define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
- #define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
- #define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
--#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
- #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
- #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
- #define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
-@@ -219,4 +226,13 @@
- #define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
- #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
-
-+/*
-+ * CPU ASE encodings
-+ */
-+#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
-+#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
-+#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
-+#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
-+#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
-+
- #endif /* _ASM_CPU_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/ecc.h linux_HEAD/include/asm-mips/dec/ecc.h
---- linux-2.6.12/include/asm-mips/dec/ecc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/ecc.h 2005-07-01 12:10:28.000000000 +0200
-@@ -49,7 +49,8 @@ struct pt_regs;
-
- extern void dec_ecc_be_init(void);
- extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
--extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs);
- #endif
-
- #endif /* __ASM_MIPS_DEC_ECC_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/ioasic_addrs.h linux_HEAD/include/asm-mips/dec/ioasic_addrs.h
---- linux-2.6.12/include/asm-mips/dec/ioasic_addrs.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/ioasic_addrs.h 2005-07-03 16:44:37.000000000 +0200
-@@ -45,7 +45,8 @@
-
-
- /*
-- * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
-+ * Offsets for I/O ASIC registers
-+ * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
- */
- /* all systems */
- #define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/kn01.h linux_HEAD/include/asm-mips/dec/kn01.h
---- linux-2.6.12/include/asm-mips/dec/kn01.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/kn01.h 2005-07-03 16:44:37.000000000 +0200
-@@ -8,14 +8,12 @@
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
-- * Copyright (C) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- */
- #ifndef __ASM_MIPS_DEC_KN01_H
- #define __ASM_MIPS_DEC_KN01_H
-
--#include <asm/addrspace.h>
--
--#define KN01_SLOT_BASE KSEG1ADDR(0x10000000)
-+#define KN01_SLOT_BASE 0x10000000
- #define KN01_SLOT_SIZE 0x01000000
-
- /*
-@@ -41,17 +39,9 @@
-
-
- /*
-- * Some port addresses...
-- */
--#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
--#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
--#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
--
--
--/*
- * Frame buffer memory address.
- */
--#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000)
-+#define KN01_VFB_MEM 0x0fc00000
-
- /*
- * CPU interrupt bits.
-@@ -80,4 +70,22 @@
- #define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
- #define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
-
-+
-+#ifndef __ASSEMBLY__
-+
-+#include <linux/interrupt.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+struct pt_regs;
-+
-+extern u16 cached_kn01_csr;
-+extern spinlock_t kn01_lock;
-+
-+extern void dec_kn01_be_init(void);
-+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
-+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs);
-+#endif
-+
- #endif /* __ASM_MIPS_DEC_KN01_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/kn02.h linux_HEAD/include/asm-mips/dec/kn02.h
---- linux-2.6.12/include/asm-mips/dec/kn02.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/kn02.h 2005-07-03 16:44:37.000000000 +0200
-@@ -8,21 +8,12 @@
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
-- * Copyright (C) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- */
- #ifndef __ASM_MIPS_DEC_KN02_H
- #define __ASM_MIPS_DEC_KN02_H
-
--#ifndef __ASSEMBLY__
--#include <linux/spinlock.h>
--#include <linux/types.h>
--#endif
--
--#include <asm/addrspace.h>
--#include <asm/dec/ecc.h>
--
--
--#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000)
-+#define KN02_SLOT_BASE 0x1fc00000
- #define KN02_SLOT_SIZE 0x00080000
-
- /*
-@@ -39,22 +30,14 @@
-
-
- /*
-- * Some port addresses...
-- */
--#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
--#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
--#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
--
--
--/*
- * System Control & Status Register bits.
- */
- #define KN02_CSR_RES_28 (0xf<<28) /* unused */
- #define KN02_CSR_PSU (1<<27) /* power supply unit warning */
- #define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
- #define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
--#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
--#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
-+#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
-+#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
- #define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
- #define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
- #define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
-@@ -63,8 +46,8 @@
- #define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
- #define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
- #define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
--#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
--#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
-+#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
-+#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
-
-
- /*
-@@ -98,6 +81,10 @@
-
-
- #ifndef __ASSEMBLY__
-+
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
- extern u32 cached_kn02_csr;
- extern spinlock_t kn02_lock;
- extern void init_kn02_irqs(int base);
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/kn02xa.h linux_HEAD/include/asm-mips/dec/kn02xa.h
---- linux-2.6.12/include/asm-mips/dec/kn02xa.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/kn02xa.h 2005-07-03 16:44:37.000000000 +0200
-@@ -9,7 +9,7 @@
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
-- * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
- *
- * These are addresses which have to be known early in the boot process.
- * For other addresses refer to tc.h, ioasic_addrs.h and friends.
-@@ -17,31 +17,23 @@
- #ifndef __ASM_MIPS_DEC_KN02XA_H
- #define __ASM_MIPS_DEC_KN02XA_H
-
--#include <asm/addrspace.h>
- #include <asm/dec/ioasic_addrs.h>
-
--#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000)
--
--/*
-- * Some port addresses...
-- */
--#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
--#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
--
-+#define KN02XA_SLOT_BASE 0x1c000000
-
- /*
- * Memory control ASIC registers.
- */
--#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */
--#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */
-+#define KN02XA_MER 0x0c400000 /* memory error register */
-+#define KN02XA_MSR 0x0c800000 /* memory size register */
-
- /*
- * CPU control ASIC registers.
- */
--#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */
--#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */
--#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */
--#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
-+#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
-+#define KN02XA_EAR 0x0e000004 /* error address register */
-+#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
-+#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
-
- /*
- * Memory Error Register bits, common definitions.
-@@ -52,8 +44,13 @@
- #define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
- #define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
- #define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
--#define KN02XA_MER_RES_12 (0x3<<12) /* unused */
--#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */
-+#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
-+#define KN02XA_MER_RES_12 (1<<12) /* unused */
-+#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
-+#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
-+#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
-+#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
-+#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
- #define KN02XA_MER_RES_0 (0xff<<0) /* unused */
-
- /*
-@@ -72,4 +69,17 @@
- #define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
- #define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
-
-+
-+#ifndef __ASSEMBLY__
-+
-+#include <linux/interrupt.h>
-+
-+struct pt_regs;
-+
-+extern void dec_kn02xa_be_init(void);
-+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
-+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs);
-+#endif
-+
- #endif /* __ASM_MIPS_DEC_KN02XA_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/kn03.h linux_HEAD/include/asm-mips/dec/kn03.h
---- linux-2.6.12/include/asm-mips/dec/kn03.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/kn03.h 2005-07-03 16:44:37.000000000 +0200
-@@ -10,24 +10,15 @@
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
-- * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
- */
- #ifndef __ASM_MIPS_DEC_KN03_H
- #define __ASM_MIPS_DEC_KN03_H
-
--#include <asm/addrspace.h>
- #include <asm/dec/ecc.h>
- #include <asm/dec/ioasic_addrs.h>
-
--#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000)
--
--/*
-- * Some port addresses...
-- */
--#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
--#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
--#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
--
-+#define KN03_SLOT_BASE 0x1f800000
-
- /*
- * CPU interrupt bits.
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/kn05.h linux_HEAD/include/asm-mips/dec/kn05.h
---- linux-2.6.12/include/asm-mips/dec/kn05.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/kn05.h 2005-07-03 16:44:37.000000000 +0200
-@@ -1,10 +1,12 @@
- /*
- * include/asm-mips/dec/kn05.h
- *
-- * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
-+ * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
-+ * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
-+ * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
- * definitions.
- *
-- * Copyright (C) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
-@@ -13,8 +15,8 @@
- *
- * WARNING! All this information is pure guesswork based on the
- * ROM. It is provided here in hope it will give someone some
-- * food for thought. No documentation for the KN05 module has
-- * been located so far.
-+ * food for thought. No documentation for the KN05 nor the KN04
-+ * module has been located so far.
- */
- #ifndef __ASM_MIPS_DEC_KN05_H
- #define __ASM_MIPS_DEC_KN05_H
-@@ -24,48 +26,50 @@
- /*
- * The oncard MB (Memory Buffer) ASIC provides an additional address
- * decoder. Certain address ranges within the "high" 16 slots are
-- * passed to the I/O ASIC's decoder like with the KN03. Others are
-- * handled locally. "Low" slots are always passed.
-+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
-+ * Others are handled locally. "Low" slots are always passed.
- */
--#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */
--#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */
--#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
--#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
--#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */
--#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */
--#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */
--#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */
--#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */
--#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */
--#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_SLOT_BASE 0x1fc00000
-+
-+#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
-+#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
-+#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
-+#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
-+#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
-+#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
-+#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
-+#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
-+#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
-+#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
-+#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
-
- /*
- * Bits for the MB interrupt register.
- * The register appears read-only.
- */
--#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */
--#define KN05_MB_INT_RTC (1<<1) /* RTC? */
--#define KN05_MB_INT_MT (1<<3) /* ??? */
-+#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
-+#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
-+#define KN4K_MB_INT_MT (1<<3) /* ??? */
-
- /*
- * Bits for the MB control & status register.
- * Set to 0x00bf8001 on my system by the ROM.
- */
--#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */
--#define KN05_MB_CSR_F (1<<1) /* ??? */
--#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */
--#define KN05_MB_CSR_OD (1<<10) /* ??? */
--#define KN05_MB_CSR_CP (1<<11) /* ??? */
--#define KN05_MB_CSR_UNC (1<<12) /* ??? */
--#define KN05_MB_CSR_IM (1<<13) /* ??? */
--#define KN05_MB_CSR_NC (1<<14) /* ??? */
--#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
--#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */
--#define KN05_MB_CSR_FW (1<<21) /* ??? */
-+#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
-+#define KN4K_MB_CSR_F (1<<1) /* ??? */
-+#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
-+#define KN4K_MB_CSR_OD (1<<10) /* ??? */
-+#define KN4K_MB_CSR_CP (1<<11) /* ??? */
-+#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
-+#define KN4K_MB_CSR_IM (1<<13) /* ??? */
-+#define KN4K_MB_CSR_NC (1<<14) /* ??? */
-+#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
-+#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
-+#define KN4K_MB_CSR_FW (1<<21) /* ??? */
-
- #endif /* __ASM_MIPS_DEC_KN05_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/prom.h linux_HEAD/include/asm-mips/dec/prom.h
---- linux-2.6.12/include/asm-mips/dec/prom.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/prom.h 2005-07-01 12:10:28.000000000 +0200
-@@ -24,7 +24,7 @@
- * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
- * Many of these will work for MIPSen as well!
- */
--#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000)
-+#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
- /* Prom base address */
-
- #define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
-@@ -111,19 +111,21 @@ extern int (*__pmax_close)(int);
- * On MIPS64 we have to call PROM functions via a helper
- * dispatcher to accomodate ABI incompatibilities.
- */
--#define __DEC_PROM_O32 __attribute__((alias("call_o32")))
-+#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
-+ __asm__(#fun " = call_o32")
-
--int _rex_bootinit(int (*)(void)) __DEC_PROM_O32;
--int _rex_bootread(int (*)(void)) __DEC_PROM_O32;
--int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32;
--unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32;
--void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32;
--int _rex_getsysid(int (*)(void)) __DEC_PROM_O32;
--void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32;
--
--int _prom_getchar(int (*)(void)) __DEC_PROM_O32;
--char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32;
--int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
-+int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
-+int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
-+int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
-+unsigned long *__DEC_PROM_O32(_rex_slot_address,
-+ (unsigned long *(*)(int), int));
-+void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
-+int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
-+void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
-+
-+int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
-+char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
-+int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
-
-
- #define rex_bootinit() _rex_bootinit(__rex_bootinit)
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/system.h linux_HEAD/include/asm-mips/dec/system.h
---- linux-2.6.12/include/asm-mips/dec/system.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/dec/system.h 2005-07-01 18:11:02.000000000 +0200
-@@ -0,0 +1,18 @@
-+/*
-+ * include/asm-mips/dec/system.h
-+ *
-+ * Generic DECstation/DECsystem bits.
-+ *
-+ * Copyright (C) 2005 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+#ifndef __ASM_DEC_SYSTEM_H
-+#define __ASM_DEC_SYSTEM_H
-+
-+extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
-+
-+#endif /* __ASM_DEC_SYSTEM_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dec/tc.h linux_HEAD/include/asm-mips/dec/tc.h
---- linux-2.6.12/include/asm-mips/dec/tc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dec/tc.h 2005-07-03 16:44:37.000000000 +0200
-@@ -7,10 +7,8 @@
- *
- * Copyright (c) 1998 Harald Koerfgen
- */
--#ifndef ASM_TC_H
--#define ASM_TC_H
--
--extern unsigned long system_base;
-+#ifndef __ASM_DEC_TC_H
-+#define __ASM_DEC_TC_H
-
- /*
- * Search for a TURBOchannel Option Module
-@@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(in
- */
- extern unsigned long get_tc_irq_nr(int);
- /*
-- * Return TURBOchannel clock frequency in hz
-+ * Return TURBOchannel clock frequency in Hz
- */
- extern unsigned long get_tc_speed(void);
-
--#endif
-+#endif /* __ASM_DEC_TC_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/delay.h linux_HEAD/include/asm-mips/delay.h
---- linux-2.6.12/include/asm-mips/delay.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/delay.h 2005-04-20 16:48:08.000000000 +0200
-@@ -12,11 +12,9 @@
-
- #include <linux/config.h>
- #include <linux/param.h>
--
-+#include <linux/smp.h>
- #include <asm/compiler.h>
-
--extern unsigned long loops_per_jiffy;
--
- static inline void __delay(unsigned long loops)
- {
- if (sizeof(long) == 4)
-@@ -82,11 +80,7 @@ static inline void __udelay(unsigned lon
- __delay(usecs);
- }
-
--#ifdef CONFIG_SMP
- #define __udelay_val cpu_data[smp_processor_id()].udelay_val
--#else
--#define __udelay_val loops_per_jiffy
--#endif
-
- #define udelay(usecs) __udelay((usecs),__udelay_val)
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dma-mapping.h linux_HEAD/include/asm-mips/dma-mapping.h
---- linux-2.6.12/include/asm-mips/dma-mapping.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/dma-mapping.h 2005-04-08 22:41:30.000000000 +0200
-@@ -5,13 +5,13 @@
- #include <asm/cache.h>
-
- void *dma_alloc_noncoherent(struct device *dev, size_t size,
-- dma_addr_t *dma_handle, int flag);
-+ dma_addr_t *dma_handle, unsigned int __nocast flag);
-
- void dma_free_noncoherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
-
- void *dma_alloc_coherent(struct device *dev, size_t size,
-- dma_addr_t *dma_handle, int flag);
-+ dma_addr_t *dma_handle, unsigned int __nocast flag);
-
- void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/dsp.h linux_HEAD/include/asm-mips/dsp.h
---- linux-2.6.12/include/asm-mips/dsp.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/dsp.h 2005-05-31 13:49:19.000000000 +0200
-@@ -0,0 +1,83 @@
-+/*
-+ * Copyright (C) 2005 Mips Technologies
-+ * Author: Chris Dearman, chris at mips.com derived from fpu.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+#ifndef _ASM_DSP_H
-+#define _ASM_DSP_H
-+
-+#include <asm/cpu.h>
-+#include <asm/cpu-features.h>
-+#include <asm/hazards.h>
-+#include <asm/mipsregs.h>
-+
-+#define DSP_DEFAULT 0x00000000
-+#define DSP_MASK 0x1f
-+
-+#define __enable_dsp_hazard() \
-+do { \
-+ asm("_ehb"); \
-+} while (0)
-+
-+static inline void __init_dsp(void)
-+{
-+ mthi1(0);
-+ mtlo1(0);
-+ mthi2(0);
-+ mtlo2(0);
-+ mthi3(0);
-+ mtlo3(0);
-+ wrdsp(DSP_DEFAULT, DSP_MASK);
-+}
-+
-+static inline void init_dsp(void)
-+{
-+ if (cpu_has_dsp)
-+ __init_dsp();
-+}
-+
-+#define __save_dsp(tsk) \
-+do { \
-+ tsk->thread.dsp.dspr[0] = mfhi1(); \
-+ tsk->thread.dsp.dspr[1] = mflo1(); \
-+ tsk->thread.dsp.dspr[2] = mfhi2(); \
-+ tsk->thread.dsp.dspr[3] = mflo2(); \
-+ tsk->thread.dsp.dspr[4] = mfhi3(); \
-+ tsk->thread.dsp.dspr[5] = mflo3(); \
-+} while (0)
-+
-+#define save_dsp(tsk) \
-+do { \
-+ if (cpu_has_dsp) \
-+ __save_dsp(tsk); \
-+} while (0)
-+
-+#define __restore_dsp(tsk) \
-+do { \
-+ mthi1(tsk->thread.dsp.dspr[0]); \
-+ mtlo1(tsk->thread.dsp.dspr[1]); \
-+ mthi2(tsk->thread.dsp.dspr[2]); \
-+ mtlo2(tsk->thread.dsp.dspr[3]); \
-+ mthi3(tsk->thread.dsp.dspr[4]); \
-+ mtlo3(tsk->thread.dsp.dspr[5]); \
-+} while (0)
-+
-+#define restore_dsp(tsk) \
-+do { \
-+ if (cpu_has_dsp) \
-+ __restore_dsp(tsk); \
-+} while (0)
-+
-+#define __get_dsp_regs(tsk) \
-+({ \
-+ if (tsk == current) \
-+ __save_dsp(current); \
-+ \
-+ tsk->thread.dsp.dspr; \
-+})
-+
-+#endif /* _ASM_DSP_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/elf.h linux_HEAD/include/asm-mips/elf.h
---- linux-2.6.12/include/asm-mips/elf.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/elf.h 2005-07-01 12:10:27.000000000 +0200
-@@ -193,50 +193,92 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N
-
- #ifdef __KERNEL__
-
-+struct mips_abi;
-+
-+extern struct mips_abi mips_abi;
-+extern struct mips_abi mips_abi_32;
-+extern struct mips_abi mips_abi_n32;
-+
- #ifdef CONFIG_MIPS32
-
--#define SET_PERSONALITY(ex, ibcs2) \
--do { \
-- if (ibcs2) \
-- set_personality(PER_SVR4); \
-- set_personality(PER_LINUX); \
-+#define SET_PERSONALITY(ex, ibcs2) \
-+do { \
-+ if (ibcs2) \
-+ set_personality(PER_SVR4); \
-+ set_personality(PER_LINUX); \
-+ \
-+ current->thread.abi = &mips_abi; \
- } while (0)
-
- #endif /* CONFIG_MIPS32 */
-
- #ifdef CONFIG_MIPS64
-
--#define SET_PERSONALITY(ex, ibcs2) \
--do { current->thread.mflags &= ~MF_ABI_MASK; \
-- if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \
-- if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
-- ((ex).e_flags & EF_MIPS_ABI) == 0) \
-- current->thread.mflags |= MF_N32; \
-- else \
-- current->thread.mflags |= MF_O32; \
-- } else \
-- current->thread.mflags |= MF_N64; \
-- if (ibcs2) \
-- set_personality(PER_SVR4); \
-- else if (current->personality != PER_LINUX32) \
-- set_personality(PER_LINUX); \
-+#ifdef CONFIG_MIPS32_N32
-+#define __SET_PERSONALITY32_N32() \
-+ do { \
-+ current->thread.mflags |= MF_N32; \
-+ current->thread.abi = &mips_abi_n32; \
-+ } while (0)
-+#else
-+#define __SET_PERSONALITY32_N32() \
-+ do { } while (0)
-+#endif
-+
-+#ifdef CONFIG_MIPS32_O32
-+#define __SET_PERSONALITY32_O32() \
-+ do { \
-+ current->thread.mflags |= MF_O32; \
-+ current->thread.abi = &mips_abi_32; \
-+ } while (0)
-+#else
-+#define __SET_PERSONALITY32_O32() \
-+ do { } while (0)
-+#endif
-+
-+#ifdef CONFIG_MIPS32_COMPAT
-+#define __SET_PERSONALITY32(ex) \
-+do { \
-+ if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
-+ ((ex).e_flags & EF_MIPS_ABI) == 0) \
-+ __SET_PERSONALITY32_N32(); \
-+ else \
-+ __SET_PERSONALITY32_O32(); \
-+} while (0)
-+#else
-+#define __SET_PERSONALITY32(ex) do { } while (0)
-+#endif
-+
-+#define SET_PERSONALITY(ex, ibcs2) \
-+do { \
-+ current->thread.mflags &= ~MF_ABI_MASK; \
-+ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
-+ __SET_PERSONALITY32(ex); \
-+ else { \
-+ current->thread.mflags |= MF_N64; \
-+ current->thread.abi = &mips_abi; \
-+ } \
-+ \
-+ if (ibcs2) \
-+ set_personality(PER_SVR4); \
-+ else if (current->personality != PER_LINUX32) \
-+ set_personality(PER_LINUX); \
- } while (0)
-
- #endif /* CONFIG_MIPS64 */
-
- extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
-+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
- extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
-
- #define ELF_CORE_COPY_REGS(elf_regs, regs) \
- dump_regs((elf_greg_t *)&(elf_regs), regs);
-+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
- #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
- dump_task_fpu(tsk, elf_fpregs)
-
- #endif /* __KERNEL__ */
-
--/* This one accepts IRIX binaries. */
--#define irix_elf_check_arch(hdr) ((hdr)->e_flags & RHF_SGI_ONLY)
--
- #define USE_ELF_CORE_DUMP
- #define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/errno.h linux_HEAD/include/asm-mips/errno.h
---- linux-2.6.12/include/asm-mips/errno.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/errno.h 2004-10-27 02:15:14.000000000 +0200
-@@ -115,10 +115,6 @@
- #define EKEYREVOKED 163 /* Key has been revoked */
- #define EKEYREJECTED 164 /* Key was rejected by service */
-
--/* for robust mutexes */
--#define EOWNERDEAD 165 /* Owner died */
--#define ENOTRECOVERABLE 166 /* State not recoverable */
--
- #define EDQUOT 1133 /* Quota exceeded */
-
- #ifdef __KERNEL__
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/fixmap.h linux_HEAD/include/asm-mips/fixmap.h
---- linux-2.6.12/include/asm-mips/fixmap.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/fixmap.h 2005-02-17 21:50:43.000000000 +0100
-@@ -107,4 +107,11 @@ static inline unsigned long virt_to_fix(
- return __virt_to_fix(vaddr);
- }
-
-+/*
-+ * Called from pgtable_init()
-+ */
-+extern void fixrange_init(unsigned long start, unsigned long end,
-+ pgd_t *pgd_base);
-+
-+
- #endif
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/fpu.h linux_HEAD/include/asm-mips/fpu.h
---- linux-2.6.12/include/asm-mips/fpu.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/fpu.h 2005-05-14 14:38:52.000000000 +0200
-@@ -80,9 +80,14 @@ do { \
-
- #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
-
-+static inline int __is_fpu_owner(void)
-+{
-+ return test_thread_flag(TIF_USEDFPU);
-+}
-+
- static inline int is_fpu_owner(void)
- {
-- return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
-+ return cpu_has_fpu && __is_fpu_owner();
- }
-
- static inline void own_fpu(void)
-@@ -127,7 +132,7 @@ static inline void restore_fp(struct tas
- static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
- {
- if (cpu_has_fpu) {
-- if ((tsk == current) && is_fpu_owner())
-+ if ((tsk == current) && __is_fpu_owner())
- _save_fp(current);
- return tsk->thread.fpu.hard.fpr;
- }
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/fpu_emulator.h linux_HEAD/include/asm-mips/fpu_emulator.h
---- linux-2.6.12/include/asm-mips/fpu_emulator.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/fpu_emulator.h 2005-05-14 14:38:52.000000000 +0200
-@@ -23,16 +23,15 @@
- #ifndef _ASM_FPU_EMULATOR_H
- #define _ASM_FPU_EMULATOR_H
-
--struct mips_fpu_emulator_private {
-- unsigned int eir;
-- struct {
-- unsigned int emulated;
-- unsigned int loads;
-- unsigned int stores;
-- unsigned int cp1ops;
-- unsigned int cp1xops;
-- unsigned int errors;
-- } stats;
-+struct mips_fpu_emulator_stats {
-+ unsigned int emulated;
-+ unsigned int loads;
-+ unsigned int stores;
-+ unsigned int cp1ops;
-+ unsigned int cp1xops;
-+ unsigned int errors;
- };
-
-+extern struct mips_fpu_emulator_stats fpuemustats;
-+
- #endif /* _ASM_FPU_EMULATOR_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/hazards.h linux_HEAD/include/asm-mips/hazards.h
---- linux-2.6.12/include/asm-mips/hazards.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/hazards.h 2005-03-03 21:03:38.000000000 +0100
-@@ -107,6 +107,7 @@ __asm__(
- " .endm \n\t");
-
- #ifdef CONFIG_CPU_RM9000
-+
- /*
- * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
-@@ -124,6 +125,9 @@ __asm__(
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
-+
-+#define back_to_back_c0_hazard() do { } while (0)
-+
- #else
-
- /*
-@@ -170,6 +174,10 @@ __asm__(
- __asm__ __volatile__( \
- "_ehb\t\t\t\t# irq_disable_hazard")
-
-+#define back_to_back_c0_hazard() \
-+ __asm__ __volatile__( \
-+ "_ehb\t\t\t\t# back_to_back_c0_hazard")
-+
- #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
-
- /*
-@@ -186,6 +194,8 @@ __asm__(
- #define irq_enable_hazard() do { } while (0)
- #define irq_disable_hazard() do { } while (0)
-
-+#define back_to_back_c0_hazard() do { } while (0)
-+
- #else
-
- /*
-@@ -210,6 +220,12 @@ __asm__(
- __asm__ __volatile__( \
- "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
-
-+#define back_to_back_c0_hazard() \
-+ __asm__ __volatile__( \
-+ " .set noreorder \n" \
-+ " nop; nop; nop \n" \
-+ " .set reorder \n")
-+
- #endif
-
- #endif /* __ASSEMBLY__ */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/hp-lj/asic.h linux_HEAD/include/asm-mips/hp-lj/asic.h
---- linux-2.6.12/include/asm-mips/hp-lj/asic.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/hp-lj/asic.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,7 +0,0 @@
--
--typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId;
--
--AsicId GetAsicId(void);
--
--const char* const GetAsicName(void);
--
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/inst.h linux_HEAD/include/asm-mips/inst.h
---- linux-2.6.12/include/asm-mips/inst.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/inst.h 2005-07-01 12:10:27.000000000 +0200
-@@ -28,7 +28,7 @@ enum major_op {
- sdl_op, sdr_op, swr_op, cache_op,
- ll_op, lwc1_op, lwc2_op, pref_op,
- lld_op, ldc1_op, ldc2_op, ld_op,
-- sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
-+ sc_op, swc1_op, swc2_op, rdhwr_op,
- scd_op, sdc1_op, sdc2_op, sd_op
- };
-
-@@ -62,10 +62,10 @@ enum rt_op {
- spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
- tgei_op, tgeiu_op, tlti_op, tltiu_op,
- teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
-- bltzal_op, bgezal_op, bltzall_op, bgezall_op
-- /*
-- * The others (0x14 - 0x1f) are unused.
-- */
-+ bltzal_op, bgezal_op, bltzall_op, bgezall_op,
-+ rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
-+ rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
-+ bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
- };
-
- /*
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/inventory.h linux_HEAD/include/asm-mips/inventory.h
---- linux-2.6.12/include/asm-mips/inventory.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/inventory.h 2005-03-17 22:20:30.000000000 +0100
-@@ -4,6 +4,8 @@
- #ifndef __ASM_INVENTORY_H
- #define __ASM_INVENTORY_H
-
-+#include <linux/compiler.h>
-+
- typedef struct inventory_s {
- struct inventory_s *inv_next;
- int inv_class;
-@@ -14,7 +16,9 @@ typedef struct inventory_s {
- } inventory_t;
-
- extern int inventory_items;
--void add_to_inventory (int class, int type, int controller, int unit, int state);
--int dump_inventory_to_user (void *userbuf, int size);
-+
-+extern void add_to_inventory (int class, int type, int controller, int unit, int state);
-+extern int dump_inventory_to_user (void __user *userbuf, int size);
-+extern int __init init_inventory(void);
-
- #endif /* __ASM_INVENTORY_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/io.h linux_HEAD/include/asm-mips/io.h
---- linux-2.6.12/include/asm-mips/io.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/io.h 2005-07-01 12:10:27.000000000 +0200
-@@ -26,6 +26,7 @@
- #include <asm/pgtable-bits.h>
- #include <asm/processor.h>
-
-+#include <ioremap.h>
- #include <mangle-port.h>
-
- /*
-@@ -34,7 +35,7 @@
- #undef CONF_SLOWDOWN_IO
-
- /*
-- * Raw operations are never swapped in software. Otoh values that raw
-+ * Raw operations are never swapped in software. OTOH values that raw
- * operations are working on may or may not have been swapped by the bus
- * hardware. An example use would be for flash memory that's used for
- * execute in place.
-@@ -43,45 +44,53 @@
- # define __raw_ioswabw(x) (x)
- # define __raw_ioswabl(x) (x)
- # define __raw_ioswabq(x) (x)
-+# define ____raw_ioswabq(x) (x)
-
- /*
- * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
- * less sane hardware forces software to fiddle with this...
-+ *
-+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
-+ * you can't have the numerical value of data and byte addresses within
-+ * multibyte quantities both preserved at the same time. Hence two
-+ * variations of functions: non-prefixed ones that preserve the value
-+ * and prefixed ones that preserve byte addresses. The latters are
-+ * typically used for moving raw data between a peripheral and memory (cf.
-+ * string I/O functions), hence the "mem_" prefix.
- */
- #if defined(CONFIG_SWAP_IO_SPACE)
-
- # define ioswabb(x) (x)
-+# define mem_ioswabb(x) (x)
- # ifdef CONFIG_SGI_IP22
- /*
- * IP22 seems braindead enough to swap 16bits values in hardware, but
- * not 32bits. Go figure... Can't tell without documentation.
- */
- # define ioswabw(x) (x)
-+# define mem_ioswabw(x) le16_to_cpu(x)
- # else
- # define ioswabw(x) le16_to_cpu(x)
-+# define mem_ioswabw(x) (x)
- # endif
- # define ioswabl(x) le32_to_cpu(x)
-+# define mem_ioswabl(x) (x)
- # define ioswabq(x) le64_to_cpu(x)
-+# define mem_ioswabq(x) (x)
-
- #else
-
- # define ioswabb(x) (x)
-+# define mem_ioswabb(x) (x)
- # define ioswabw(x) (x)
-+# define mem_ioswabw(x) cpu_to_le16(x)
- # define ioswabl(x) (x)
-+# define mem_ioswabl(x) cpu_to_le32(x)
- # define ioswabq(x) (x)
-+# define mem_ioswabq(x) cpu_to_le32(x)
-
- #endif
-
--/*
-- * Native bus accesses never swapped.
-- */
--#define bus_ioswabb(x) (x)
--#define bus_ioswabw(x) (x)
--#define bus_ioswabl(x) (x)
--#define bus_ioswabq(x) (x)
--
--#define __bus_ioswabq bus_ioswabq
--
- #define IO_SPACE_LIMIT 0xffff
-
- /*
-@@ -200,6 +209,8 @@ extern void __iounmap(volatile void __io
- static inline void * __ioremap_mode(phys_t offset, unsigned long size,
- unsigned long flags)
- {
-+#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
-+
- if (cpu_has_64bit_addresses) {
- u64 base = UNCAC_BASE;
-
-@@ -210,9 +221,30 @@ static inline void * __ioremap_mode(phys
- if (flags == _CACHE_UNCACHED)
- base = (u64) IO_BASE;
- return (void *) (unsigned long) (base + offset);
-+ } else if (__builtin_constant_p(offset) &&
-+ __builtin_constant_p(size) && __builtin_constant_p(flags)) {
-+ phys_t phys_addr, last_addr;
-+
-+ phys_addr = fixup_bigphys_addr(offset, size);
-+
-+ /* Don't allow wraparound or zero size. */
-+ last_addr = phys_addr + size - 1;
-+ if (!size || last_addr < phys_addr)
-+ return NULL;
-+
-+ /*
-+ * Map uncached objects in the low 512MB of address
-+ * space using KSEG1.
-+ */
-+ if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
-+ flags == _CACHE_UNCACHED)
-+ return (void *)CKSEG1ADDR(phys_addr);
-+
- }
-
- return __ioremap(offset, size, flags);
-+
-+#undef __IS_LOW512
- }
-
- /*
-@@ -264,12 +296,16 @@ static inline void * __ioremap_mode(phys
-
- static inline void iounmap(volatile void __iomem *addr)
- {
-- if (cpu_has_64bit_addresses)
-+#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
-+
-+ if (cpu_has_64bit_addresses ||
-+ (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
- return;
-
- __iounmap(addr);
--}
-
-+#undef __IS_KSEG1
-+}
-
- #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
- \
-@@ -319,7 +355,8 @@ static inline type pfx##read##bwlq(volat
- else if (cpu_has_64bits) { \
- unsigned long __flags; \
- \
-- local_irq_save(__flags); \
-+ if (irq) \
-+ local_irq_save(__flags); \
- __asm__ __volatile__( \
- ".set mips3" "\t\t# __readq" "\n\t" \
- "ld %L0, %1" "\n\t" \
-@@ -328,7 +365,8 @@ static inline type pfx##read##bwlq(volat
- ".set mips0" "\n" \
- : "=r" (__val) \
- : "m" (*__mem)); \
-- local_irq_restore(__flags); \
-+ if (irq) \
-+ local_irq_restore(__flags); \
- } else { \
- __val = 0; \
- BUG(); \
-@@ -386,15 +424,15 @@ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _
-
- #define BUILDIO(bwlq, type) \
- \
--__BUILD_MEMORY_PFX(, bwlq, type) \
- __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
--__BUILD_MEMORY_PFX(bus_, bwlq, type) \
-+__BUILD_MEMORY_PFX(, bwlq, type) \
-+__BUILD_MEMORY_PFX(mem_, bwlq, type) \
- __BUILD_IOPORT_PFX(, bwlq, type) \
--__BUILD_IOPORT_PFX(__raw_, bwlq, type)
-+__BUILD_IOPORT_PFX(mem_, bwlq, type)
-
- #define __BUILDIO(bwlq, type) \
- \
--__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
-+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
-
- BUILDIO(b, u8)
- BUILDIO(w, u16)
-@@ -422,7 +460,7 @@ static inline void writes##bwlq(volatile
- volatile type *__addr = addr; \
- \
- while (count--) { \
-- __raw_write##bwlq(*__addr, mem); \
-+ mem_write##bwlq(*__addr, mem); \
- __addr++; \
- } \
- } \
-@@ -433,20 +471,20 @@ static inline void reads##bwlq(volatile
- volatile type *__addr = addr; \
- \
- while (count--) { \
-- *__addr = __raw_read##bwlq(mem); \
-+ *__addr = mem_read##bwlq(mem); \
- __addr++; \
- } \
- }
-
- #define __BUILD_IOPORT_STRING(bwlq, type) \
- \
--static inline void outs##bwlq(unsigned long port, void *addr, \
-+static inline void outs##bwlq(unsigned long port, const void *addr, \
- unsigned int count) \
- { \
-- volatile type *__addr = addr; \
-+ const volatile type *__addr = addr; \
- \
- while (count--) { \
-- __raw_out##bwlq(*__addr, port); \
-+ mem_out##bwlq(*__addr, port); \
- __addr++; \
- } \
- } \
-@@ -457,7 +495,7 @@ static inline void ins##bwlq(unsigned lo
- volatile type *__addr = addr; \
- \
- while (count--) { \
-- *__addr = __raw_in##bwlq(port); \
-+ *__addr = mem_in##bwlq(port); \
- __addr++; \
- } \
- }
-@@ -481,34 +519,6 @@ BUILDSTRING(q, u64)
- #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-
- /*
-- * Memory Mapped I/O
-- */
--#define ioread8(addr) readb(addr)
--#define ioread16(addr) readw(addr)
--#define ioread32(addr) readl(addr)
--
--#define iowrite8(b,addr) writeb(b,addr)
--#define iowrite16(w,addr) writew(w,addr)
--#define iowrite32(l,addr) writel(l,addr)
--
--#define ioread8_rep(a,b,c) readsb(a,b,c)
--#define ioread16_rep(a,b,c) readsw(a,b,c)
--#define ioread32_rep(a,b,c) readsl(a,b,c)
--
--#define iowrite8_rep(a,b,c) writesb(a,b,c)
--#define iowrite16_rep(a,b,c) writesw(a,b,c)
--#define iowrite32_rep(a,b,c) writesl(a,b,c)
--
--/* Create a virtual mapping cookie for an IO port range */
--extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
--extern void ioport_unmap(void __iomem *);
--
--/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
--struct pci_dev;
--extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
--extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
--
--/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/irq.h linux_HEAD/include/asm-mips/irq.h
---- linux-2.6.12/include/asm-mips/irq.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/irq.h 2005-03-01 22:49:44.000000000 +0100
-@@ -24,11 +24,9 @@ static inline int irq_canonicalize(int i
-
- struct pt_regs;
-
--#ifdef CONFIG_PREEMPT
--
- extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
-
--#else
-+#ifdef CONFIG_PREEMPT
-
- /*
- * do_IRQ handles all normal device IRQ's (the special
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/jmr3927/jmr3927.h linux_HEAD/include/asm-mips/jmr3927/jmr3927.h
---- linux-2.6.12/include/asm-mips/jmr3927/jmr3927.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/jmr3927/jmr3927.h 2005-03-04 20:36:14.000000000 +0100
-@@ -202,20 +202,6 @@ static inline int jmr3927_have_isac(void
- #endif /* !__ASSEMBLY__ */
-
- /*
-- * UART defines for serial.h
-- */
--
--/* use Pre-scaler T0 (1/2) */
--#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
--
--#define UART0_ADDR 0xfffef300
--#define UART1_ADDR 0xfffef400
--#define UART0_INT JMR3927_IRQ_IRC_SIO0
--#define UART1_INT JMR3927_IRQ_IRC_SIO1
--#define UART0_FLAGS ASYNC_BOOT_AUTOCONF
--#define UART1_FLAGS 0
--
--/*
- * IRQ mappings
- */
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-au1x00/au1000.h linux_HEAD/include/asm-mips/mach-au1x00/au1000.h
---- linux-2.6.12/include/asm-mips/mach-au1x00/au1000.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-au1x00/au1000.h 2005-04-25 13:27:29.000000000 +0200
-@@ -60,34 +60,34 @@ void static inline au_sync_delay(int ms)
- mdelay(ms);
- }
-
--void static inline au_writeb(u8 val, int reg)
-+void static inline au_writeb(u8 val, unsigned long reg)
- {
- *(volatile u8 *)(reg) = val;
- }
-
--void static inline au_writew(u16 val, int reg)
-+void static inline au_writew(u16 val, unsigned long reg)
- {
- *(volatile u16 *)(reg) = val;
- }
-
--void static inline au_writel(u32 val, int reg)
-+void static inline au_writel(u32 val, unsigned long reg)
- {
- *(volatile u32 *)(reg) = val;
- }
-
--static inline u8 au_readb(unsigned long port)
-+static inline u8 au_readb(unsigned long reg)
- {
-- return (*(volatile u8 *)port);
-+ return (*(volatile u8 *)reg);
- }
-
--static inline u16 au_readw(unsigned long port)
-+static inline u16 au_readw(unsigned long reg)
- {
-- return (*(volatile u16 *)port);
-+ return (*(volatile u16 *)reg);
- }
-
--static inline u32 au_readl(unsigned long port)
-+static inline u32 au_readl(unsigned long reg)
- {
-- return (*(volatile u32 *)port);
-+ return (*(volatile u32 *)reg);
- }
-
- /* These next three functions should be a generic part of the MIPS
-@@ -162,28 +162,293 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
- #endif
-
--/* SDRAM Controller */
-+/*
-+ * SDRAM Register Offsets
-+ */
- #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
--#define MEM_SDMODE0 0xB4000000
--#define MEM_SDMODE1 0xB4000004
--#define MEM_SDMODE2 0xB4000008
--
--#define MEM_SDADDR0 0xB400000C
--#define MEM_SDADDR1 0xB4000010
--#define MEM_SDADDR2 0xB4000014
--
--#define MEM_SDREFCFG 0xB4000018
--#define MEM_SDPRECMD 0xB400001C
--#define MEM_SDAUTOREF 0xB4000020
--
--#define MEM_SDWRMD0 0xB4000024
--#define MEM_SDWRMD1 0xB4000028
--#define MEM_SDWRMD2 0xB400002C
-+#define MEM_SDMODE0 (0x0000)
-+#define MEM_SDMODE1 (0x0004)
-+#define MEM_SDMODE2 (0x0008)
-+#define MEM_SDADDR0 (0x000C)
-+#define MEM_SDADDR1 (0x0010)
-+#define MEM_SDADDR2 (0x0014)
-+#define MEM_SDREFCFG (0x0018)
-+#define MEM_SDPRECMD (0x001C)
-+#define MEM_SDAUTOREF (0x0020)
-+#define MEM_SDWRMD0 (0x0024)
-+#define MEM_SDWRMD1 (0x0028)
-+#define MEM_SDWRMD2 (0x002C)
-+#define MEM_SDSLEEP (0x0030)
-+#define MEM_SDSMCKE (0x0034)
-+
-+/*
-+ * MEM_SDMODE register content definitions
-+ */
-+#define MEM_SDMODE_F (1<<22)
-+#define MEM_SDMODE_SR (1<<21)
-+#define MEM_SDMODE_BS (1<<20)
-+#define MEM_SDMODE_RS (3<<18)
-+#define MEM_SDMODE_CS (7<<15)
-+#define MEM_SDMODE_TRAS (15<<11)
-+#define MEM_SDMODE_TMRD (3<<9)
-+#define MEM_SDMODE_TWR (3<<7)
-+#define MEM_SDMODE_TRP (3<<5)
-+#define MEM_SDMODE_TRCD (3<<3)
-+#define MEM_SDMODE_TCL (7<<0)
-+
-+#define MEM_SDMODE_BS_2Bank (0<<20)
-+#define MEM_SDMODE_BS_4Bank (1<<20)
-+#define MEM_SDMODE_RS_11Row (0<<18)
-+#define MEM_SDMODE_RS_12Row (1<<18)
-+#define MEM_SDMODE_RS_13Row (2<<18)
-+#define MEM_SDMODE_RS_N(N) ((N)<<18)
-+#define MEM_SDMODE_CS_7Col (0<<15)
-+#define MEM_SDMODE_CS_8Col (1<<15)
-+#define MEM_SDMODE_CS_9Col (2<<15)
-+#define MEM_SDMODE_CS_10Col (3<<15)
-+#define MEM_SDMODE_CS_11Col (4<<15)
-+#define MEM_SDMODE_CS_N(N) ((N)<<15)
-+#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
-+#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
-+#define MEM_SDMODE_TWR_N(N) ((N)<<7)
-+#define MEM_SDMODE_TRP_N(N) ((N)<<5)
-+#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
-+#define MEM_SDMODE_TCL_N(N) ((N)<<0)
-+
-+/*
-+ * MEM_SDADDR register contents definitions
-+ */
-+#define MEM_SDADDR_E (1<<20)
-+#define MEM_SDADDR_CSBA (0x03FF<<10)
-+#define MEM_SDADDR_CSMASK (0x03FF<<0)
-+#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
-+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
-+
-+/*
-+ * MEM_SDREFCFG register content definitions
-+ */
-+#define MEM_SDREFCFG_TRC (15<<28)
-+#define MEM_SDREFCFG_TRPM (3<<26)
-+#define MEM_SDREFCFG_E (1<<25)
-+#define MEM_SDREFCFG_RE (0x1ffffff<<0)
-+#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
-+#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
-+#define MEM_SDREFCFG_REF_N(N) (N)
-+#endif
-+
-+/***********************************************************************/
-
--#define MEM_SDSLEEP 0xB4000030
--#define MEM_SDSMCKE 0xB4000034
-+/*
-+ * Au1550 SDRAM Register Offsets
-+ */
-+
-+/***********************************************************************/
-+
-+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-+#define MEM_SDMODE0 (0x0800)
-+#define MEM_SDMODE1 (0x0808)
-+#define MEM_SDMODE2 (0x0810)
-+#define MEM_SDADDR0 (0x0820)
-+#define MEM_SDADDR1 (0x0828)
-+#define MEM_SDADDR2 (0x0830)
-+#define MEM_SDCONFIGA (0x0840)
-+#define MEM_SDCONFIGB (0x0848)
-+#define MEM_SDSTAT (0x0850)
-+#define MEM_SDERRADDR (0x0858)
-+#define MEM_SDSTRIDE0 (0x0860)
-+#define MEM_SDSTRIDE1 (0x0868)
-+#define MEM_SDSTRIDE2 (0x0870)
-+#define MEM_SDWRMD0 (0x0880)
-+#define MEM_SDWRMD1 (0x0888)
-+#define MEM_SDWRMD2 (0x0890)
-+#define MEM_SDPRECMD (0x08C0)
-+#define MEM_SDAUTOREF (0x08C8)
-+#define MEM_SDSREF (0x08D0)
-+#define MEM_SDSLEEP MEM_SDSREF
-+
-+#endif
-+
-+/*
-+ * Physical base addresses for integrated peripherals
-+ */
-+
-+#ifdef CONFIG_SOC_AU1000
-+#define MEM_PHYS_ADDR 0x14000000
-+#define STATIC_MEM_PHYS_ADDR 0x14001000
-+#define DMA0_PHYS_ADDR 0x14002000
-+#define DMA1_PHYS_ADDR 0x14002100
-+#define DMA2_PHYS_ADDR 0x14002200
-+#define DMA3_PHYS_ADDR 0x14002300
-+#define DMA4_PHYS_ADDR 0x14002400
-+#define DMA5_PHYS_ADDR 0x14002500
-+#define DMA6_PHYS_ADDR 0x14002600
-+#define DMA7_PHYS_ADDR 0x14002700
-+#define IC0_PHYS_ADDR 0x10400000
-+#define IC1_PHYS_ADDR 0x11800000
-+#define AC97_PHYS_ADDR 0x10000000
-+#define USBH_PHYS_ADDR 0x10100000
-+#define USBD_PHYS_ADDR 0x10200000
-+#define IRDA_PHYS_ADDR 0x10300000
-+#define MAC0_PHYS_ADDR 0x10500000
-+#define MAC1_PHYS_ADDR 0x10510000
-+#define MACEN_PHYS_ADDR 0x10520000
-+#define MACDMA0_PHYS_ADDR 0x14004000
-+#define MACDMA1_PHYS_ADDR 0x14004200
-+#define I2S_PHYS_ADDR 0x11000000
-+#define UART0_PHYS_ADDR 0x11100000
-+#define UART1_PHYS_ADDR 0x11200000
-+#define UART2_PHYS_ADDR 0x11300000
-+#define UART3_PHYS_ADDR 0x11400000
-+#define SSI0_PHYS_ADDR 0x11600000
-+#define SSI1_PHYS_ADDR 0x11680000
-+#define SYS_PHYS_ADDR 0x11900000
-+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
- #endif
-
-+/********************************************************************/
-+
-+#ifdef CONFIG_SOC_AU1500
-+#define MEM_PHYS_ADDR 0x14000000
-+#define STATIC_MEM_PHYS_ADDR 0x14001000
-+#define DMA0_PHYS_ADDR 0x14002000
-+#define DMA1_PHYS_ADDR 0x14002100
-+#define DMA2_PHYS_ADDR 0x14002200
-+#define DMA3_PHYS_ADDR 0x14002300
-+#define DMA4_PHYS_ADDR 0x14002400
-+#define DMA5_PHYS_ADDR 0x14002500
-+#define DMA6_PHYS_ADDR 0x14002600
-+#define DMA7_PHYS_ADDR 0x14002700
-+#define IC0_PHYS_ADDR 0x10400000
-+#define IC1_PHYS_ADDR 0x11800000
-+#define AC97_PHYS_ADDR 0x10000000
-+#define USBH_PHYS_ADDR 0x10100000
-+#define USBD_PHYS_ADDR 0x10200000
-+#define PCI_PHYS_ADDR 0x14005000
-+#define MAC0_PHYS_ADDR 0x11500000
-+#define MAC1_PHYS_ADDR 0x11510000
-+#define MACEN_PHYS_ADDR 0x11520000
-+#define MACDMA0_PHYS_ADDR 0x14004000
-+#define MACDMA1_PHYS_ADDR 0x14004200
-+#define I2S_PHYS_ADDR 0x11000000
-+#define UART0_PHYS_ADDR 0x11100000
-+#define UART3_PHYS_ADDR 0x11400000
-+#define GPIO2_PHYS_ADDR 0x11700000
-+#define SYS_PHYS_ADDR 0x11900000
-+#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-+#define PCI_IO_PHYS_ADDR 0x500000000ULL
-+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-+#endif
-+
-+/********************************************************************/
-+
-+#ifdef CONFIG_SOC_AU1100
-+#define MEM_PHYS_ADDR 0x14000000
-+#define STATIC_MEM_PHYS_ADDR 0x14001000
-+#define DMA0_PHYS_ADDR 0x14002000
-+#define DMA1_PHYS_ADDR 0x14002100
-+#define DMA2_PHYS_ADDR 0x14002200
-+#define DMA3_PHYS_ADDR 0x14002300
-+#define DMA4_PHYS_ADDR 0x14002400
-+#define DMA5_PHYS_ADDR 0x14002500
-+#define DMA6_PHYS_ADDR 0x14002600
-+#define DMA7_PHYS_ADDR 0x14002700
-+#define IC0_PHYS_ADDR 0x10400000
-+#define SD0_PHYS_ADDR 0x10600000
-+#define SD1_PHYS_ADDR 0x10680000
-+#define IC1_PHYS_ADDR 0x11800000
-+#define AC97_PHYS_ADDR 0x10000000
-+#define USBH_PHYS_ADDR 0x10100000
-+#define USBD_PHYS_ADDR 0x10200000
-+#define IRDA_PHYS_ADDR 0x10300000
-+#define MAC0_PHYS_ADDR 0x10500000
-+#define MACEN_PHYS_ADDR 0x10520000
-+#define MACDMA0_PHYS_ADDR 0x14004000
-+#define MACDMA1_PHYS_ADDR 0x14004200
-+#define I2S_PHYS_ADDR 0x11000000
-+#define UART0_PHYS_ADDR 0x11100000
-+#define UART1_PHYS_ADDR 0x11200000
-+#define UART3_PHYS_ADDR 0x11400000
-+#define SSI0_PHYS_ADDR 0x11600000
-+#define SSI1_PHYS_ADDR 0x11680000
-+#define GPIO2_PHYS_ADDR 0x11700000
-+#define SYS_PHYS_ADDR 0x11900000
-+#define LCD_PHYS_ADDR 0x15000000
-+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-+#endif
-+
-+/***********************************************************************/
-+
-+#ifdef CONFIG_SOC_AU1550
-+#define MEM_PHYS_ADDR 0x14000000
-+#define STATIC_MEM_PHYS_ADDR 0x14001000
-+#define IC0_PHYS_ADDR 0x10400000
-+#define IC1_PHYS_ADDR 0x11800000
-+#define USBH_PHYS_ADDR 0x14020000
-+#define USBD_PHYS_ADDR 0x10200000
-+#define PCI_PHYS_ADDR 0x14005000
-+#define MAC0_PHYS_ADDR 0x10500000
-+#define MAC1_PHYS_ADDR 0x10510000
-+#define MACEN_PHYS_ADDR 0x10520000
-+#define MACDMA0_PHYS_ADDR 0x14004000
-+#define MACDMA1_PHYS_ADDR 0x14004200
-+#define UART0_PHYS_ADDR 0x11100000
-+#define UART1_PHYS_ADDR 0x11200000
-+#define UART3_PHYS_ADDR 0x11400000
-+#define GPIO2_PHYS_ADDR 0x11700000
-+#define SYS_PHYS_ADDR 0x11900000
-+#define DDMA_PHYS_ADDR 0x14002000
-+#define PE_PHYS_ADDR 0x14008000
-+#define PSC0_PHYS_ADDR 0x11A00000
-+#define PSC1_PHYS_ADDR 0x11B00000
-+#define PSC2_PHYS_ADDR 0x10A00000
-+#define PSC3_PHYS_ADDR 0x10B00000
-+#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-+#define PCI_IO_PHYS_ADDR 0x500000000ULL
-+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-+#endif
-+
-+/***********************************************************************/
-+
-+#ifdef CONFIG_SOC_AU1200
-+#define MEM_PHYS_ADDR 0x14000000
-+#define STATIC_MEM_PHYS_ADDR 0x14001000
-+#define AES_PHYS_ADDR 0x10300000
-+#define CIM_PHYS_ADDR 0x14004000
-+#define IC0_PHYS_ADDR 0x10400000
-+#define IC1_PHYS_ADDR 0x11800000
-+#define USBM_PHYS_ADDR 0x14020000
-+#define USBH_PHYS_ADDR 0x14020100
-+#define UART0_PHYS_ADDR 0x11100000
-+#define UART1_PHYS_ADDR 0x11200000
-+#define GPIO2_PHYS_ADDR 0x11700000
-+#define SYS_PHYS_ADDR 0x11900000
-+#define DDMA_PHYS_ADDR 0x14002000
-+#define PSC0_PHYS_ADDR 0x11A00000
-+#define PSC1_PHYS_ADDR 0x11B00000
-+#define SD0_PHYS_ADDR 0x10600000
-+#define SD1_PHYS_ADDR 0x10680000
-+#define LCD_PHYS_ADDR 0x15000000
-+#define SWCNT_PHYS_ADDR 0x1110010C
-+#define MAEFE_PHYS_ADDR 0x14012000
-+#define MAEBE_PHYS_ADDR 0x14010000
-+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-+#endif
-+
-+
- /* Static Bus Controller */
- #define MEM_STCFG0 0xB4001000
- #define MEM_STTIME0 0xB4001004
-@@ -369,7 +634,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1000_MAC0_ENABLE 0xB0520000
- #define AU1000_MAC1_ENABLE 0xB0520004
- #define NUM_ETH_INTERFACES 2
--#endif // CONFIG_SOC_AU1000
-+#endif /* CONFIG_SOC_AU1000 */
-
- /* Au1500 */
- #ifdef CONFIG_SOC_AU1500
-@@ -429,6 +694,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1500_GPIO_207 62
- #define AU1500_GPIO_208_215 63
-
-+/* shortcuts */
-+#define INTA AU1000_PCI_INTA
-+#define INTB AU1000_PCI_INTB
-+#define INTC AU1000_PCI_INTC
-+#define INTD AU1000_PCI_INTD
-+
- #define UART0_ADDR 0xB1100000
- #define UART3_ADDR 0xB1400000
-
-@@ -440,7 +711,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1500_MAC0_ENABLE 0xB1520000
- #define AU1500_MAC1_ENABLE 0xB1520004
- #define NUM_ETH_INTERFACES 2
--#endif // CONFIG_SOC_AU1500
-+#endif /* CONFIG_SOC_AU1500 */
-
- /* Au1100 */
- #ifdef CONFIG_SOC_AU1100
-@@ -485,6 +756,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1000_GPIO_13 45
- #define AU1000_GPIO_14 46
- #define AU1000_GPIO_15 47
-+#define AU1000_GPIO_16 48
-+#define AU1000_GPIO_17 49
-+#define AU1000_GPIO_18 50
-+#define AU1000_GPIO_19 51
-+#define AU1000_GPIO_20 52
-+#define AU1000_GPIO_21 53
-+#define AU1000_GPIO_22 54
-+#define AU1000_GPIO_23 55
-+#define AU1000_GPIO_24 56
-+#define AU1000_GPIO_25 57
-+#define AU1000_GPIO_26 58
-+#define AU1000_GPIO_27 59
-+#define AU1000_GPIO_28 60
-+#define AU1000_GPIO_29 61
-+#define AU1000_GPIO_30 62
-+#define AU1000_GPIO_31 63
-
- #define UART0_ADDR 0xB1100000
- #define UART1_ADDR 0xB1200000
-@@ -496,7 +783,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1100_ETH0_BASE 0xB0500000
- #define AU1100_MAC0_ENABLE 0xB0520000
- #define NUM_ETH_INTERFACES 1
--#endif // CONFIG_SOC_AU1100
-+#endif /* CONFIG_SOC_AU1100 */
-
- #ifdef CONFIG_SOC_AU1550
- #define AU1550_UART0_INT 0
-@@ -513,14 +800,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1550_PSC1_INT 11
- #define AU1550_PSC2_INT 12
- #define AU1550_PSC3_INT 13
--#define AU1550_TOY_INT 14
--#define AU1550_TOY_MATCH0_INT 15
--#define AU1550_TOY_MATCH1_INT 16
--#define AU1550_TOY_MATCH2_INT 17
--#define AU1550_RTC_INT 18
--#define AU1550_RTC_MATCH0_INT 19
--#define AU1550_RTC_MATCH1_INT 20
--#define AU1550_RTC_MATCH2_INT 21
-+#define AU1000_TOY_INT 14
-+#define AU1000_TOY_MATCH0_INT 15
-+#define AU1000_TOY_MATCH1_INT 16
-+#define AU1000_TOY_MATCH2_INT 17
-+#define AU1000_RTC_INT 18
-+#define AU1000_RTC_MATCH0_INT 19
-+#define AU1000_RTC_MATCH1_INT 20
-+#define AU1000_RTC_MATCH2_INT 21
- #define AU1550_NAND_INT 23
- #define AU1550_USB_DEV_REQ_INT 24
- #define AU1550_USB_DEV_SUS_INT 25
-@@ -563,6 +850,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1500_GPIO_207 62
- #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
-
-+/* shortcuts */
-+#define INTA AU1550_PCI_INTA
-+#define INTB AU1550_PCI_INTB
-+#define INTC AU1550_PCI_INTC
-+#define INTD AU1550_PCI_INTD
-+
- #define UART0_ADDR 0xB1100000
- #define UART1_ADDR 0xB1200000
- #define UART3_ADDR 0xB1400000
-@@ -575,7 +868,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1550_MAC0_ENABLE 0xB0520000
- #define AU1550_MAC1_ENABLE 0xB0520004
- #define NUM_ETH_INTERFACES 2
--#endif // CONFIG_SOC_AU1550
-+#endif /* CONFIG_SOC_AU1550 */
-
- #ifdef CONFIG_SOC_AU1200
- #define AU1200_UART0_INT 0
-@@ -592,14 +885,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1200_PSC1_INT 11
- #define AU1200_AES_INT 12
- #define AU1200_CAMERA_INT 13
--#define AU1200_TOY_INT 14
--#define AU1200_TOY_MATCH0_INT 15
--#define AU1200_TOY_MATCH1_INT 16
--#define AU1200_TOY_MATCH2_INT 17
--#define AU1200_RTC_INT 18
--#define AU1200_RTC_MATCH0_INT 19
--#define AU1200_RTC_MATCH1_INT 20
--#define AU1200_RTC_MATCH2_INT 21
-+#define AU1000_TOY_INT 14
-+#define AU1000_TOY_MATCH0_INT 15
-+#define AU1000_TOY_MATCH1_INT 16
-+#define AU1000_TOY_MATCH2_INT 17
-+#define AU1000_RTC_INT 18
-+#define AU1000_RTC_MATCH0_INT 19
-+#define AU1000_RTC_MATCH1_INT 20
-+#define AU1000_RTC_MATCH2_INT 21
- #define AU1200_NAND_INT 23
- #define AU1200_GPIO_204 24
- #define AU1200_GPIO_205 25
-@@ -607,6 +900,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define AU1200_GPIO_207 27
- #define AU1200_GPIO_208_215 28 // Logical OR of 208:215
- #define AU1200_USB_INT 29
-+#define AU1000_USB_HOST_INT AU1200_USB_INT
- #define AU1200_LCD_INT 30
- #define AU1200_MAE_BOTH_INT 31
- #define AU1000_GPIO_0 32
-@@ -645,20 +939,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define UART0_ADDR 0xB1100000
- #define UART1_ADDR 0xB1200000
-
--#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
--#define USB_HOST_CONFIG 0xB4027ffc
-+#define USB_UOC_BASE 0x14020020
-+#define USB_UOC_LEN 0x20
-+#define USB_OHCI_BASE 0x14020100
-+#define USB_OHCI_LEN 0x100
-+#define USB_EHCI_BASE 0x14020200
-+#define USB_EHCI_LEN 0x100
-+#define USB_UDC_BASE 0x14022000
-+#define USB_UDC_LEN 0x2000
-+#define USB_MSR_BASE 0xB4020000
-+#define USB_MSR_MCFG 4
-+#define USBMSRMCFG_OMEMEN 0
-+#define USBMSRMCFG_OBMEN 1
-+#define USBMSRMCFG_EMEMEN 2
-+#define USBMSRMCFG_EBMEN 3
-+#define USBMSRMCFG_DMEMEN 4
-+#define USBMSRMCFG_DBMEN 5
-+#define USBMSRMCFG_GMEMEN 6
-+#define USBMSRMCFG_OHCCLKEN 16
-+#define USBMSRMCFG_EHCCLKEN 17
-+#define USBMSRMCFG_UDCCLKEN 18
-+#define USBMSRMCFG_PHYPLLEN 19
-+#define USBMSRMCFG_RDCOMB 30
-+#define USBMSRMCFG_PFEN 31
-
--// these are here for prototyping on au1550 (do not exist on au1200)
--#define AU1200_ETH0_BASE 0xB0500000
--#define AU1200_ETH1_BASE 0xB0510000
--#define AU1200_MAC0_ENABLE 0xB0520000
--#define AU1200_MAC1_ENABLE 0xB0520004
--#define NUM_ETH_INTERFACES 2
--#endif // CONFIG_SOC_AU1200
-+#endif /* CONFIG_SOC_AU1200 */
-
- #define AU1000_LAST_INTC0_INT 31
-+#define AU1000_LAST_INTC1_INT 63
- #define AU1000_MAX_INTR 63
--
-+#define INTX 0xFF /* not valid */
-
- /* Programmable Counters 0 and 1 */
- #define SYS_BASE 0xB1900000
-@@ -730,6 +1040,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define I2S_CONTROL_D (1<<1)
- #define I2S_CONTROL_CE (1<<0)
-
-+#ifndef CONFIG_SOC_AU1200
-+
- /* USB Host Controller */
- #define USB_OHCI_LEN 0x00100000
-
-@@ -775,6 +1087,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define USBDEV_ENABLE (1<<1)
- #define USBDEV_CE (1<<0)
-
-+#endif /* !CONFIG_SOC_AU1200 */
-+
- /* Ethernet Controllers */
-
- /* 4 byte offsets from AU1000_ETH_BASE */
-@@ -1173,6 +1487,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define SYS_PF_PSC1_S1 (1 << 1)
- #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
-
-+/* Au1200 Only */
-+#ifdef CONFIG_SOC_AU1200
-+#define SYS_PINFUNC_DMA (1<<31)
-+#define SYS_PINFUNC_S0A (1<<30)
-+#define SYS_PINFUNC_S1A (1<<29)
-+#define SYS_PINFUNC_LP0 (1<<28)
-+#define SYS_PINFUNC_LP1 (1<<27)
-+#define SYS_PINFUNC_LD16 (1<<26)
-+#define SYS_PINFUNC_LD8 (1<<25)
-+#define SYS_PINFUNC_LD1 (1<<24)
-+#define SYS_PINFUNC_LD0 (1<<23)
-+#define SYS_PINFUNC_P1A (3<<21)
-+#define SYS_PINFUNC_P1B (1<<20)
-+#define SYS_PINFUNC_FS3 (1<<19)
-+#define SYS_PINFUNC_P0A (3<<17)
-+#define SYS_PINFUNC_CS (1<<16)
-+#define SYS_PINFUNC_CIM (1<<15)
-+#define SYS_PINFUNC_P1C (1<<14)
-+#define SYS_PINFUNC_U1T (1<<12)
-+#define SYS_PINFUNC_U1R (1<<11)
-+#define SYS_PINFUNC_EX1 (1<<10)
-+#define SYS_PINFUNC_EX0 (1<<9)
-+#define SYS_PINFUNC_U0R (1<<8)
-+#define SYS_PINFUNC_MC (1<<7)
-+#define SYS_PINFUNC_S0B (1<<6)
-+#define SYS_PINFUNC_S0C (1<<5)
-+#define SYS_PINFUNC_P0B (1<<4)
-+#define SYS_PINFUNC_U0T (1<<3)
-+#define SYS_PINFUNC_S1B (1<<2)
-+#endif
-+
- #define SYS_TRIOUTRD 0xB1900100
- #define SYS_TRIOUTCLR 0xB1900100
- #define SYS_OUTPUTRD 0xB1900108
-@@ -1239,6 +1584,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
- #define SYS_CS_DI2 (1<<16)
- #define SYS_CS_CI2 (1<<15)
-+#ifdef CONFIG_SOC_AU1100
-+ #define SYS_CS_ML_BIT 7
-+ #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
-+ #define SYS_CS_DL (1<<6)
-+ #define SYS_CS_CL (1<<5)
-+#else
- #define SYS_CS_MUH_BIT 12
- #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
- #define SYS_CS_DUH (1<<11)
-@@ -1247,6 +1598,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
- #define SYS_CS_DUD (1<<6)
- #define SYS_CS_CUD (1<<5)
-+#endif
- #define SYS_CS_MIR_BIT 2
- #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
- #define SYS_CS_DIR (1<<1)
-@@ -1300,7 +1652,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- #define SD1_XMIT_FIFO 0xB0680000
- #define SD1_RECV_FIFO 0xB0680004
-
--
- #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
- /* Au1500 PCI Controller */
- #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
-@@ -1363,36 +1714,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]
- _ctl_; })
-
-
--#else /* Au1000 and Au1100 */
-+#else /* Au1000 and Au1100 and Au1200 */
-
- /* don't allow any legacy ports probing */
--#define IOPORT_RESOURCE_START 0x10000000;
-+#define IOPORT_RESOURCE_START 0x10000000
- #define IOPORT_RESOURCE_END 0xffffffff
- #define IOMEM_RESOURCE_START 0x10000000
- #define IOMEM_RESOURCE_END 0xffffffff
-
--#ifdef CONFIG_MIPS_PB1000
--#define PCI_IO_START 0x10000000
--#define PCI_IO_END 0x1000ffff
--#define PCI_MEM_START 0x18000000
--#define PCI_MEM_END 0x18ffffff
--#define PCI_FIRST_DEVFN 0
--#define PCI_LAST_DEVFN 1
--#else
--/* no PCI bus controller */
- #define PCI_IO_START 0
- #define PCI_IO_END 0
- #define PCI_MEM_START 0
--#define PCI_MEM_END 0
-+#define PCI_MEM_END 0
- #define PCI_FIRST_DEVFN 0
- #define PCI_LAST_DEVFN 0
--#endif
-
- #endif
-
-+#ifndef _LANGUAGE_ASSEMBLY
-+typedef volatile struct
-+{
-+ /* 0x0000 */ u32 toytrim;
-+ /* 0x0004 */ u32 toywrite;
-+ /* 0x0008 */ u32 toymatch0;
-+ /* 0x000C */ u32 toymatch1;
-+ /* 0x0010 */ u32 toymatch2;
-+ /* 0x0014 */ u32 cntrctrl;
-+ /* 0x0018 */ u32 scratch0;
-+ /* 0x001C */ u32 scratch1;
-+ /* 0x0020 */ u32 freqctrl0;
-+ /* 0x0024 */ u32 freqctrl1;
-+ /* 0x0028 */ u32 clksrc;
-+ /* 0x002C */ u32 pinfunc;
-+ /* 0x0030 */ u32 reserved0;
-+ /* 0x0034 */ u32 wakemsk;
-+ /* 0x0038 */ u32 endian;
-+ /* 0x003C */ u32 powerctrl;
-+ /* 0x0040 */ u32 toyread;
-+ /* 0x0044 */ u32 rtctrim;
-+ /* 0x0048 */ u32 rtcwrite;
-+ /* 0x004C */ u32 rtcmatch0;
-+ /* 0x0050 */ u32 rtcmatch1;
-+ /* 0x0054 */ u32 rtcmatch2;
-+ /* 0x0058 */ u32 rtcread;
-+ /* 0x005C */ u32 wakesrc;
-+ /* 0x0060 */ u32 cpupll;
-+ /* 0x0064 */ u32 auxpll;
-+ /* 0x0068 */ u32 reserved1;
-+ /* 0x006C */ u32 reserved2;
-+ /* 0x0070 */ u32 reserved3;
-+ /* 0x0074 */ u32 reserved4;
-+ /* 0x0078 */ u32 slppwr;
-+ /* 0x007C */ u32 sleep;
-+ /* 0x0080 */ u32 reserved5[32];
-+ /* 0x0100 */ u32 trioutrd;
-+#define trioutclr trioutrd
-+ /* 0x0104 */ u32 reserved6;
-+ /* 0x0108 */ u32 outputrd;
-+#define outputset outputrd
-+ /* 0x010C */ u32 outputclr;
-+ /* 0x0110 */ u32 pinstaterd;
-+#define pininputen pinstaterd
-+
-+} AU1X00_SYS;
-+
-+static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
-+
-+#endif
- /* Processor information base on prid.
- * Copied from PowerPC.
- */
-+#ifndef _LANGUAGE_ASSEMBLY
- struct cpu_spec {
- /* CPU is matched via (PRID & prid_mask) == prid_value */
- unsigned int prid_mask;
-@@ -1406,3 +1798,6 @@ struct cpu_spec {
- extern struct cpu_spec cpu_specs[];
- extern struct cpu_spec *cur_cpu_spec[];
- #endif
-+
-+#endif
-+
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-au1x00/au1xxx_dbdma.h linux_HEAD/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
---- linux-2.6.12/include/asm-mips/mach-au1x00/au1xxx_dbdma.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-au1x00/au1xxx_dbdma.h 2005-03-01 15:00:58.000000000 +0100
-@@ -45,7 +45,7 @@
- #define DDMA_GLOBAL_BASE 0xb4003000
- #define DDMA_CHANNEL_BASE 0xb4002000
-
--typedef struct dbdma_global {
-+typedef volatile struct dbdma_global {
- u32 ddma_config;
- u32 ddma_intstat;
- u32 ddma_throttle;
-@@ -62,7 +62,7 @@ typedef struct dbdma_global {
-
- /* The structure of a DMA Channel.
- */
--typedef struct au1xxx_dma_channel {
-+typedef volatile struct au1xxx_dma_channel {
- u32 ddma_cfg; /* See below */
- u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
- u32 ddma_statptr; /* word aligned pointer to status word */
-@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
- /* "Standard" DDMA Descriptor.
- * Must be 32-byte aligned.
- */
--typedef struct au1xxx_ddma_desc {
-+typedef volatile struct au1xxx_ddma_desc {
- u32 dscr_cmd0; /* See below */
- u32 dscr_cmd1; /* See below */
- u32 dscr_source0; /* source phys address */
-@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
- u32 dscr_dest1; /* See below */
- u32 dscr_stat; /* completion status */
- u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
-+ /* First 32bytes are HW specific!!!
-+ Lets have some SW data following.. make sure its 32bytes
-+ */
-+ u32 sw_status;
-+ u32 sw_context;
-+ u32 sw_reserved[6];
- } au1x_ddma_desc_t;
-
- #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
-@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
- #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
- #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
-
-+#define SW_STATUS_INUSE (1<<0)
-+
- /* Command 0 device IDs.
- */
-+#ifdef CONFIG_SOC_AU1550
- #define DSCR_CMD0_UART0_TX 0
- #define DSCR_CMD0_UART0_RX 1
- #define DSCR_CMD0_UART3_TX 2
-@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
- #define DSCR_CMD0_MAC0_TX 25
- #define DSCR_CMD0_MAC1_RX 26
- #define DSCR_CMD0_MAC1_TX 27
-+#endif /* CONFIG_SOC_AU1550 */
-+
-+#ifdef CONFIG_SOC_AU1200
-+#define DSCR_CMD0_UART0_TX 0
-+#define DSCR_CMD0_UART0_RX 1
-+#define DSCR_CMD0_UART1_TX 2
-+#define DSCR_CMD0_UART1_RX 3
-+#define DSCR_CMD0_DMA_REQ0 4
-+#define DSCR_CMD0_DMA_REQ1 5
-+#define DSCR_CMD0_MAE_BE 6
-+#define DSCR_CMD0_MAE_FE 7
-+#define DSCR_CMD0_SDMS_TX0 8
-+#define DSCR_CMD0_SDMS_RX0 9
-+#define DSCR_CMD0_SDMS_TX1 10
-+#define DSCR_CMD0_SDMS_RX1 11
-+#define DSCR_CMD0_AES_TX 13
-+#define DSCR_CMD0_AES_RX 12
-+#define DSCR_CMD0_PSC0_TX 14
-+#define DSCR_CMD0_PSC0_RX 15
-+#define DSCR_CMD0_PSC1_TX 16
-+#define DSCR_CMD0_PSC1_RX 17
-+#define DSCR_CMD0_CIM_RXA 18
-+#define DSCR_CMD0_CIM_RXB 19
-+#define DSCR_CMD0_CIM_RXC 20
-+#define DSCR_CMD0_MAE_BOTH 21
-+#define DSCR_CMD0_LCD 22
-+#define DSCR_CMD0_NAND_FLASH 23
-+#define DSCR_CMD0_PSC0_SYNC 24
-+#define DSCR_CMD0_PSC1_SYNC 25
-+#define DSCR_CMD0_CIM_SYNC 26
-+#endif /* CONFIG_SOC_AU1200 */
-+
- #define DSCR_CMD0_THROTTLE 30
- #define DSCR_CMD0_ALWAYS 31
- #define DSCR_NDEV_IDS 32
-+/* THis macro is used to find/create custom device types */
-+#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
-+#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
-+
-
- #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
- #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
-@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
- */
- #define NUM_DBDMA_CHANS 16
-
-+/*
-+ * Ddma API definitions
-+ * FIXME: may not fit to this header file
-+ */
-+typedef struct dbdma_device_table {
-+ u32 dev_id;
-+ u32 dev_flags;
-+ u32 dev_tsize;
-+ u32 dev_devwidth;
-+ u32 dev_physaddr; /* If FIFO */
-+ u32 dev_intlevel;
-+ u32 dev_intpolarity;
-+} dbdev_tab_t;
-+
-+
-+typedef struct dbdma_chan_config {
-+ spinlock_t lock;
-+
-+ u32 chan_flags;
-+ u32 chan_index;
-+ dbdev_tab_t *chan_src;
-+ dbdev_tab_t *chan_dest;
-+ au1x_dma_chan_t *chan_ptr;
-+ au1x_ddma_desc_t *chan_desc_base;
-+ au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
-+ void *chan_callparam;
-+ void (*chan_callback)(int, void *, struct pt_regs *);
-+} chan_tab_t;
-+
-+#define DEV_FLAGS_INUSE (1 << 0)
-+#define DEV_FLAGS_ANYUSE (1 << 1)
-+#define DEV_FLAGS_OUT (1 << 2)
-+#define DEV_FLAGS_IN (1 << 3)
-+#define DEV_FLAGS_BURSTABLE (1 << 4)
-+#define DEV_FLAGS_SYNC (1 << 5)
-+/* end Ddma API definitions */
-+
- /* External functions for drivers to use.
- */
- /* Use this to allocate a dbdma channel. The device ids are one of the
-@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u
-
- #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
-
--/* ACK! These should be in a board specific description file.
--*/
--#ifdef CONFIG_MIPS_PB1550
--#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
--#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
--#endif
--#ifdef CONFIG_MIPS_DB1550
--#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
--#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
--#endif
--
--
- /* Set the device width of a in/out fifo.
- */
- u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
-@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid,
-
- /* Put buffers on source/destination descriptors.
- */
--u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
--u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
-+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
-+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
-
- /* Get a buffer from the destination descriptor.
- */
-@@ -295,5 +365,25 @@ u32 au1xxx_get_dma_residue(u32 chanid);
- void au1xxx_dbdma_chan_free(u32 chanid);
- void au1xxx_dbdma_dump(u32 chanid);
-
-+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
-+
-+u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
-+
-+/*
-+ Some compatibilty macros --
-+ Needed to make changes to API without breaking existing drivers
-+*/
-+#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
-+#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
-+
-+#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
-+#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
-+
-+/*
-+ * Flags for the put_source/put_dest functions.
-+ */
-+#define DDMA_FLAGS_IE (1<<0)
-+#define DDMA_FLAGS_NOIE (1<<1)
-+
- #endif /* _LANGUAGE_ASSEMBLY */
- #endif /* _AU1000_DBDMA_H_ */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-au1x00/au1xxx_psc.h linux_HEAD/include/asm-mips/mach-au1x00/au1xxx_psc.h
---- linux-2.6.12/include/asm-mips/mach-au1x00/au1xxx_psc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-au1x00/au1xxx_psc.h 2005-04-14 16:40:18.000000000 +0200
-@@ -33,6 +33,8 @@
- #ifndef _AU1000_PSC_H_
- #define _AU1000_PSC_H_
-
-+#include <linux/config.h>
-+
- /* The PSC base addresses. */
- #ifdef CONFIG_SOC_AU1550
- #define PSC0_BASE_ADDR 0xb1a00000
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-au1x00/ioremap.h linux_HEAD/include/asm-mips/mach-au1x00/ioremap.h
---- linux-2.6.12/include/asm-mips/mach-au1x00/ioremap.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/mach-au1x00/ioremap.h 2005-06-30 12:48:46.000000000 +0200
-@@ -0,0 +1,29 @@
-+/*
-+ * include/asm-mips/mach-au1x00/ioremap.h
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+#ifndef __ASM_MACH_AU1X00_IOREMAP_H
-+#define __ASM_MACH_AU1X00_IOREMAP_H
-+
-+#include <linux/types.h>
-+
-+#ifndef CONFIG_64BIT_PHYS_ADDR
-+static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-+{
-+ return phys_addr;
-+}
-+#endif
-+
-+/*
-+ * Allow physical addresses to be fixed up to help 36-bit peripherals.
-+ */
-+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-+{
-+ return __fixup_bigphys_addr(phys_addr, size);
-+}
-+
-+#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-db1x00/db1200.h linux_HEAD/include/asm-mips/mach-db1x00/db1200.h
---- linux-2.6.12/include/asm-mips/mach-db1x00/db1200.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/mach-db1x00/db1200.h 2005-04-14 16:40:18.000000000 +0200
-@@ -0,0 +1,214 @@
-+/*
-+ * AMD Alchemy DB1200 Referrence Board
-+ * Board Registers defines.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ *
-+ */
-+#ifndef __ASM_DB1200_H
-+#define __ASM_DB1200_H
-+
-+#include <linux/types.h>
-+
-+// This is defined in au1000.h with bogus value
-+#undef AU1X00_EXTERNAL_INT
-+
-+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-+
-+/* SPI and SMB are muxed on the Pb1200 board.
-+ Refer to board documentation.
-+ */
-+#define SPI_PSC_BASE PSC0_BASE_ADDR
-+#define SMBUS_PSC_BASE PSC0_BASE_ADDR
-+/* AC97 and I2S are muxed on the Pb1200 board.
-+ Refer to board documentation.
-+ */
-+#define AC97_PSC_BASE PSC1_BASE_ADDR
-+#define I2S_PSC_BASE PSC1_BASE_ADDR
-+
-+#define BCSR_KSEG1_ADDR 0xB9800000
-+
-+typedef volatile struct
-+{
-+ /*00*/ u16 whoami;
-+ u16 reserved0;
-+ /*04*/ u16 status;
-+ u16 reserved1;
-+ /*08*/ u16 switches;
-+ u16 reserved2;
-+ /*0C*/ u16 resets;
-+ u16 reserved3;
-+
-+ /*10*/ u16 pcmcia;
-+ u16 reserved4;
-+ /*14*/ u16 board;
-+ u16 reserved5;
-+ /*18*/ u16 disk_leds;
-+ u16 reserved6;
-+ /*1C*/ u16 system;
-+ u16 reserved7;
-+
-+ /*20*/ u16 intclr;
-+ u16 reserved8;
-+ /*24*/ u16 intset;
-+ u16 reserved9;
-+ /*28*/ u16 intclr_mask;
-+ u16 reserved10;
-+ /*2C*/ u16 intset_mask;
-+ u16 reserved11;
-+
-+ /*30*/ u16 sig_status;
-+ u16 reserved12;
-+ /*34*/ u16 int_status;
-+ u16 reserved13;
-+ /*38*/ u16 reserved14;
-+ u16 reserved15;
-+ /*3C*/ u16 reserved16;
-+ u16 reserved17;
-+
-+} BCSR;
-+
-+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-+
-+/*
-+ * Register bit definitions for the BCSRs
-+ */
-+#define BCSR_WHOAMI_DCID 0x000F
-+#define BCSR_WHOAMI_CPLD 0x00F0
-+#define BCSR_WHOAMI_BOARD 0x0F00
-+
-+#define BCSR_STATUS_PCMCIA0VS 0x0003
-+#define BCSR_STATUS_PCMCIA1VS 0x000C
-+#define BCSR_STATUS_SWAPBOOT 0x0040
-+#define BCSR_STATUS_FLASHBUSY 0x0100
-+#define BCSR_STATUS_IDECBLID 0x0200
-+#define BCSR_STATUS_SD0WP 0x0400
-+#define BCSR_STATUS_U0RXD 0x1000
-+#define BCSR_STATUS_U1RXD 0x2000
-+
-+#define BCSR_SWITCHES_OCTAL 0x00FF
-+#define BCSR_SWITCHES_DIP_1 0x0080
-+#define BCSR_SWITCHES_DIP_2 0x0040
-+#define BCSR_SWITCHES_DIP_3 0x0020
-+#define BCSR_SWITCHES_DIP_4 0x0010
-+#define BCSR_SWITCHES_DIP_5 0x0008
-+#define BCSR_SWITCHES_DIP_6 0x0004
-+#define BCSR_SWITCHES_DIP_7 0x0002
-+#define BCSR_SWITCHES_DIP_8 0x0001
-+#define BCSR_SWITCHES_ROTARY 0x0F00
-+
-+#define BCSR_RESETS_ETH 0x0001
-+#define BCSR_RESETS_CAMERA 0x0002
-+#define BCSR_RESETS_DC 0x0004
-+#define BCSR_RESETS_IDE 0x0008
-+#define BCSR_RESETS_TV 0x0010
-+/* not resets but in the same register */
-+#define BCSR_RESETS_PWMR1mUX 0x0800
-+#define BCSR_RESETS_PCS0MUX 0x1000
-+#define BCSR_RESETS_PCS1MUX 0x2000
-+#define BCSR_RESETS_SPISEL 0x4000
-+
-+#define BCSR_PCMCIA_PC0VPP 0x0003
-+#define BCSR_PCMCIA_PC0VCC 0x000C
-+#define BCSR_PCMCIA_PC0DRVEN 0x0010
-+#define BCSR_PCMCIA_PC0RST 0x0080
-+#define BCSR_PCMCIA_PC1VPP 0x0300
-+#define BCSR_PCMCIA_PC1VCC 0x0C00
-+#define BCSR_PCMCIA_PC1DRVEN 0x1000
-+#define BCSR_PCMCIA_PC1RST 0x8000
-+
-+#define BCSR_BOARD_LCDVEE 0x0001
-+#define BCSR_BOARD_LCDVDD 0x0002
-+#define BCSR_BOARD_LCDBL 0x0004
-+#define BCSR_BOARD_CAMSNAP 0x0010
-+#define BCSR_BOARD_CAMPWR 0x0020
-+#define BCSR_BOARD_SD0PWR 0x0040
-+
-+#define BCSR_LEDS_DECIMALS 0x0003
-+#define BCSR_LEDS_LED0 0x0100
-+#define BCSR_LEDS_LED1 0x0200
-+#define BCSR_LEDS_LED2 0x0400
-+#define BCSR_LEDS_LED3 0x0800
-+
-+#define BCSR_SYSTEM_POWEROFF 0x4000
-+#define BCSR_SYSTEM_RESET 0x8000
-+
-+/* Bit positions for the different interrupt sources */
-+#define BCSR_INT_IDE 0x0001
-+#define BCSR_INT_ETH 0x0002
-+#define BCSR_INT_PC0 0x0004
-+#define BCSR_INT_PC0STSCHG 0x0008
-+#define BCSR_INT_PC1 0x0010
-+#define BCSR_INT_PC1STSCHG 0x0020
-+#define BCSR_INT_DC 0x0040
-+#define BCSR_INT_FLASHBUSY 0x0080
-+#define BCSR_INT_PC0INSERT 0x0100
-+#define BCSR_INT_PC0EJECT 0x0200
-+#define BCSR_INT_PC1INSERT 0x0400
-+#define BCSR_INT_PC1EJECT 0x0800
-+#define BCSR_INT_SD0INSERT 0x1000
-+#define BCSR_INT_SD0EJECT 0x2000
-+
-+#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300)
-+#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT
-+
-+#define AU1XXX_ATA_PHYS_ADDR (0x18800000)
-+#define AU1XXX_ATA_PHYS_LEN (0x100)
-+#define AU1XXX_ATA_REG_OFFSET (5)
-+#define AU1XXX_ATA_INT DB1200_IDE_INT
-+#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
-+#define AU1XXX_ATA_RQSIZE 128
-+
-+#define NAND_PHYS_ADDR 0x20000000
-+
-+/*
-+ * External Interrupts for Pb1200 as of 8/6/2004.
-+ * Bit positions in the CPLD registers can be calculated by taking
-+ * the interrupt define and subtracting the DB1200_INT_BEGIN value.
-+ * *example: IDE bis pos is = 64 - 64
-+ ETH bit pos is = 65 - 64
-+ */
-+#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
-+#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
-+#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
-+#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
-+#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
-+#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
-+#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
-+#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
-+#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
-+#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
-+#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
-+#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
-+#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
-+#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
-+#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
-+
-+#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
-+
-+/* For drivers/pcmcia/au1000_db1x00.c */
-+#define BOARD_PC0_INT DB1200_PC0_INT
-+#define BOARD_PC1_INT DB1200_PC1_INT
-+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
-+
-+#endif /* __ASM_DB1200_H */
-+
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-dec/mc146818rtc.h linux_HEAD/include/asm-mips/mach-dec/mc146818rtc.h
---- linux-2.6.12/include/asm-mips/mach-dec/mc146818rtc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-dec/mc146818rtc.h 2005-07-03 16:44:38.000000000 +0200
-@@ -3,7 +3,7 @@
- *
- * Copyright (C) 1998, 2001 by Ralf Baechle
- * Copyright (C) 1998 by Harald Koerfgen
-- * Copyright (C) 2002 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2005 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
-@@ -14,23 +14,18 @@
- #define __ASM_MIPS_DEC_RTC_DEC_H
-
- #include <linux/types.h>
--
- #include <asm/addrspace.h>
-+#include <asm/dec/system.h>
-
- extern volatile u8 *dec_rtc_base;
--extern unsigned long dec_kn_slot_size;
-
--#define RTC_PORT(x) CPHYSADDR(dec_rtc_base)
-+#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
- #define RTC_IO_EXTENT dec_kn_slot_size
- #define RTC_IOMAPPED 0
- #undef RTC_IRQ
-
- #define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
-
--#include <linux/mc146818rtc.h>
--#include <linux/module.h>
--#include <linux/types.h>
--
- static inline unsigned char CMOS_READ(unsigned long addr)
- {
- return dec_rtc_base[addr * 4];
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-generic/ide.h linux_HEAD/include/asm-mips/mach-generic/ide.h
---- linux-2.6.12/include/asm-mips/mach-generic/ide.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-generic/ide.h 2005-04-20 16:48:09.000000000 +0200
-@@ -18,6 +18,7 @@
- #include <linux/config.h>
- #include <linux/pci.h>
- #include <linux/stddef.h>
-+#include <asm/processor.h>
-
- #ifndef MAX_HWIFS
- # ifdef CONFIG_BLK_DEV_IDEPCI
-@@ -104,15 +105,71 @@ static __inline__ unsigned long ide_defa
-
- /* MIPS port and memory-mapped I/O string operations. */
-
--#define __ide_insw insw
--#define __ide_insl insl
--#define __ide_outsw outsw
--#define __ide_outsl outsl
--
--#define __ide_mm_insw readsw
--#define __ide_mm_insl readsl
--#define __ide_mm_outsw writesw
--#define __ide_mm_outsl writesl
-+static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
-+{
-+ if (cpu_has_dc_aliases) {
-+ unsigned long end = addr + size;
-+ for (; addr < end; addr += PAGE_SIZE)
-+ flush_dcache_page(virt_to_page(addr));
-+ }
-+}
-+
-+static inline void __ide_insw(unsigned long port, void *addr,
-+ unsigned int count)
-+{
-+ insw(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 2);
-+}
-+
-+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
-+{
-+ insl(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 4);
-+}
-+
-+static inline void __ide_outsw(unsigned long port, const void *addr,
-+ unsigned long count)
-+{
-+ outsw(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 2);
-+}
-+
-+static inline void __ide_outsl(unsigned long port, const void *addr,
-+ unsigned long count)
-+{
-+ outsl(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 4);
-+}
-+
-+static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
-+{
-+ readsw(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 2);
-+}
-+
-+static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
-+{
-+ readsl(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 4);
-+}
-+
-+static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
-+{
-+ writesw(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 2);
-+}
-+
-+static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
-+{
-+ writesl(port, addr, count);
-+ __ide_flush_dcache_range((unsigned long)addr, count * 4);
-+}
-+
-+/* ide_insw calls insw, not __ide_insw. Why? */
-+#undef insw
-+#undef insl
-+#define insw(port, addr, count) __ide_insw(port, addr, count)
-+#define insl(port, addr, count) __ide_insl(port, addr, count)
-
- #endif /* __KERNEL__ */
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-generic/ioremap.h linux_HEAD/include/asm-mips/mach-generic/ioremap.h
---- linux-2.6.12/include/asm-mips/mach-generic/ioremap.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/mach-generic/ioremap.h 2005-06-30 12:48:48.000000000 +0200
-@@ -0,0 +1,23 @@
-+/*
-+ * include/asm-mips/mach-generic/ioremap.h
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
-+#define __ASM_MACH_GENERIC_IOREMAP_H
-+
-+#include <linux/types.h>
-+
-+/*
-+ * Allow physical addresses to be fixed up to help peripherals located
-+ * outside the low 32-bit range -- generic pass-through version.
-+ */
-+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-+{
-+ return phys_addr;
-+}
-+
-+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ip22/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-ip22/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-ip22/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ip22/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -23,6 +23,8 @@
- #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
- #define cpu_has_ic_fills_f_dc 0
-
-+#define cpu_has_dsp 0
-+
- #define cpu_has_nofpuex 0
- #define cpu_has_64bits 1
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ip27/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-ip27/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -25,6 +25,7 @@
- #define cpu_has_vtag_icache 0
- #define cpu_has_dc_aliases 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_icache_snoops_remote_store 1
-
- #define cpu_has_nofpuex 0
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ip27/mmzone.h linux_HEAD/include/asm-mips/mach-ip27/mmzone.h
---- linux-2.6.12/include/asm-mips/mach-ip27/mmzone.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ip27/mmzone.h 2005-06-18 17:49:34.000000000 +0200
-@@ -10,7 +10,6 @@
- #define LEVELS_PER_SLICE 128
-
- struct slice_data {
-- unsigned long irq_alloc_mask[2];
- unsigned long irq_enable_mask[2];
- int level_to_irq[LEVELS_PER_SLICE];
- };
-@@ -20,6 +19,7 @@ struct hub_data {
- DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
- cpumask_t h_cpus;
- unsigned long slice_map;
-+ unsigned long irq_alloc_mask[2];
- struct slice_data slice[2];
- };
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ip27/spaces.h linux_HEAD/include/asm-mips/mach-ip27/spaces.h
---- linux-2.6.12/include/asm-mips/mach-ip27/spaces.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ip27/spaces.h 2005-02-21 22:17:46.000000000 +0100
-@@ -20,6 +20,7 @@
- #define IO_BASE 0x9200000000000000
- #define MSPEC_BASE 0x9400000000000000
- #define UNCAC_BASE 0x9600000000000000
-+#define MAP_BASE 0xc000000000000000
-
- #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
- #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ip32/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-ip32/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-ip32/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ip32/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -37,5 +37,6 @@
- #define cpu_has_ejtag 0
- #define cpu_has_vtag_icache 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
-
- #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ja/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-ja/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-ja/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ja/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -25,6 +25,7 @@
- #define cpu_has_vtag_icache 0
- #define cpu_has_dc_aliases 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_icache_snoops_remote_store 0
-
- #define cpu_has_nofpuex 0
-@@ -36,10 +37,4 @@
- #define cpu_icache_line_size() 32
- #define cpu_scache_line_size() 32
-
--/*
-- * On the RM9000 we need to ensure that I-cache lines being fetches only
-- * contain valid instructions are funny things will happen.
-- */
--#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
--
- #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-mips/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-mips/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-mips/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-mips/cpu-feature-overrides.h 2005-07-07 11:23:06.000000000 +0200
-@@ -39,7 +39,7 @@
- /* #define cpu_has_subset_pcaches ? */
- #endif
-
--#ifdef CONFIG_CPU_MIPS64
-+#ifdef CONFIG_CPU_MIPS64_R1
- #define cpu_has_tlb 1
- #define cpu_has_4kex 1
- #define cpu_has_4ktlb 1
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -28,6 +28,7 @@
- #define cpu_has_vtag_icache 0
- #define cpu_has_dc_aliases 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_icache_snoops_remote_store 0
-
- #define cpu_has_nofpuex 0
-@@ -39,10 +40,4 @@
- #define cpu_icache_line_size() 32
- #define cpu_scache_line_size() 32
-
--/*
-- * On the RM9000 we need to ensure that I-cache lines being fetches only
-- * contain valid instructions are funny things will happen.
-- */
--#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
--
- #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-pb1x00/pb1200.h linux_HEAD/include/asm-mips/mach-pb1x00/pb1200.h
---- linux-2.6.12/include/asm-mips/mach-pb1x00/pb1200.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/asm-mips/mach-pb1x00/pb1200.h 2005-04-14 16:40:18.000000000 +0200
-@@ -0,0 +1,244 @@
-+/*
-+ * AMD Alchemy PB1200 Referrence Board
-+ * Board Registers defines.
-+ *
-+ * ########################################################################
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * ########################################################################
-+ *
-+ *
-+ */
-+#ifndef __ASM_PB1200_H
-+#define __ASM_PB1200_H
-+
-+#include <linux/types.h>
-+
-+// This is defined in au1000.h with bogus value
-+#undef AU1X00_EXTERNAL_INT
-+
-+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-+
-+/* SPI and SMB are muxed on the Pb1200 board.
-+ Refer to board documentation.
-+ */
-+#define SPI_PSC_BASE PSC0_BASE_ADDR
-+#define SMBUS_PSC_BASE PSC0_BASE_ADDR
-+/* AC97 and I2S are muxed on the Pb1200 board.
-+ Refer to board documentation.
-+ */
-+#define AC97_PSC_BASE PSC1_BASE_ADDR
-+#define I2S_PSC_BASE PSC1_BASE_ADDR
-+
-+#define BCSR_KSEG1_ADDR 0xAD800000
-+
-+typedef volatile struct
-+{
-+ /*00*/ u16 whoami;
-+ u16 reserved0;
-+ /*04*/ u16 status;
-+ u16 reserved1;
-+ /*08*/ u16 switches;
-+ u16 reserved2;
-+ /*0C*/ u16 resets;
-+ u16 reserved3;
-+
-+ /*10*/ u16 pcmcia;
-+ u16 reserved4;
-+ /*14*/ u16 board;
-+ u16 reserved5;
-+ /*18*/ u16 disk_leds;
-+ u16 reserved6;
-+ /*1C*/ u16 system;
-+ u16 reserved7;
-+
-+ /*20*/ u16 intclr;
-+ u16 reserved8;
-+ /*24*/ u16 intset;
-+ u16 reserved9;
-+ /*28*/ u16 intclr_mask;
-+ u16 reserved10;
-+ /*2C*/ u16 intset_mask;
-+ u16 reserved11;
-+
-+ /*30*/ u16 sig_status;
-+ u16 reserved12;
-+ /*34*/ u16 int_status;
-+ u16 reserved13;
-+ /*38*/ u16 reserved14;
-+ u16 reserved15;
-+ /*3C*/ u16 reserved16;
-+ u16 reserved17;
-+
-+} BCSR;
-+
-+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-+
-+/*
-+ * Register bit definitions for the BCSRs
-+ */
-+#define BCSR_WHOAMI_DCID 0x000F
-+#define BCSR_WHOAMI_CPLD 0x00F0
-+#define BCSR_WHOAMI_BOARD 0x0F00
-+
-+#define BCSR_STATUS_PCMCIA0VS 0x0003
-+#define BCSR_STATUS_PCMCIA1VS 0x000C
-+#define BCSR_STATUS_SWAPBOOT 0x0040
-+#define BCSR_STATUS_FLASHBUSY 0x0100
-+#define BCSR_STATUS_IDECBLID 0x0200
-+#define BCSR_STATUS_SD0WP 0x0400
-+#define BCSR_STATUS_SD1WP 0x0800
-+#define BCSR_STATUS_U0RXD 0x1000
-+#define BCSR_STATUS_U1RXD 0x2000
-+
-+#define BCSR_SWITCHES_OCTAL 0x00FF
-+#define BCSR_SWITCHES_DIP_1 0x0080
-+#define BCSR_SWITCHES_DIP_2 0x0040
-+#define BCSR_SWITCHES_DIP_3 0x0020
-+#define BCSR_SWITCHES_DIP_4 0x0010
-+#define BCSR_SWITCHES_DIP_5 0x0008
-+#define BCSR_SWITCHES_DIP_6 0x0004
-+#define BCSR_SWITCHES_DIP_7 0x0002
-+#define BCSR_SWITCHES_DIP_8 0x0001
-+#define BCSR_SWITCHES_ROTARY 0x0F00
-+
-+#define BCSR_RESETS_ETH 0x0001
-+#define BCSR_RESETS_CAMERA 0x0002
-+#define BCSR_RESETS_DC 0x0004
-+#define BCSR_RESETS_IDE 0x0008
-+/* not resets but in the same register */
-+#define BCSR_RESETS_WSCFSM 0x0800
-+#define BCSR_RESETS_PCS0MUX 0x1000
-+#define BCSR_RESETS_PCS1MUX 0x2000
-+#define BCSR_RESETS_SPISEL 0x4000
-+#define BCSR_RESETS_SD1MUX 0x8000
-+
-+#define BCSR_PCMCIA_PC0VPP 0x0003
-+#define BCSR_PCMCIA_PC0VCC 0x000C
-+#define BCSR_PCMCIA_PC0DRVEN 0x0010
-+#define BCSR_PCMCIA_PC0RST 0x0080
-+#define BCSR_PCMCIA_PC1VPP 0x0300
-+#define BCSR_PCMCIA_PC1VCC 0x0C00
-+#define BCSR_PCMCIA_PC1DRVEN 0x1000
-+#define BCSR_PCMCIA_PC1RST 0x8000
-+
-+#define BCSR_BOARD_LCDVEE 0x0001
-+#define BCSR_BOARD_LCDVDD 0x0002
-+#define BCSR_BOARD_LCDBL 0x0004
-+#define BCSR_BOARD_CAMSNAP 0x0010
-+#define BCSR_BOARD_CAMPWR 0x0020
-+#define BCSR_BOARD_SD0PWR 0x0040
-+#define BCSR_BOARD_SD1PWR 0x0080
-+
-+#define BCSR_LEDS_DECIMALS 0x00FF
-+#define BCSR_LEDS_LED0 0x0100
-+#define BCSR_LEDS_LED1 0x0200
-+#define BCSR_LEDS_LED2 0x0400
-+#define BCSR_LEDS_LED3 0x0800
-+
-+#define BCSR_SYSTEM_VDDI 0x001F
-+#define BCSR_SYSTEM_POWEROFF 0x4000
-+#define BCSR_SYSTEM_RESET 0x8000
-+
-+/* Bit positions for the different interrupt sources */
-+#define BCSR_INT_IDE 0x0001
-+#define BCSR_INT_ETH 0x0002
-+#define BCSR_INT_PC0 0x0004
-+#define BCSR_INT_PC0STSCHG 0x0008
-+#define BCSR_INT_PC1 0x0010
-+#define BCSR_INT_PC1STSCHG 0x0020
-+#define BCSR_INT_DC 0x0040
-+#define BCSR_INT_FLASHBUSY 0x0080
-+#define BCSR_INT_PC0INSERT 0x0100
-+#define BCSR_INT_PC0EJECT 0x0200
-+#define BCSR_INT_PC1INSERT 0x0400
-+#define BCSR_INT_PC1EJECT 0x0800
-+#define BCSR_INT_SD0INSERT 0x1000
-+#define BCSR_INT_SD0EJECT 0x2000
-+#define BCSR_INT_SD1INSERT 0x4000
-+#define BCSR_INT_SD1EJECT 0x8000
-+
-+#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
-+#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
-+
-+#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
-+#define AU1XXX_ATA_PHYS_LEN (0x100)
-+#define AU1XXX_ATA_REG_OFFSET (5)
-+#define AU1XXX_ATA_INT PB1200_IDE_INT
-+#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
-+#define AU1XXX_ATA_RQSIZE 128
-+
-+#define NAND_PHYS_ADDR 0x1C000000
-+
-+/* Timing values as described in databook, * ns value stripped of
-+ * lower 2 bits.
-+ * These defines are here rather than an SOC1200 generic file because
-+ * the parts chosen on another board may be different and may require
-+ * different timings.
-+ */
-+#define NAND_T_H (18 >> 2)
-+#define NAND_T_PUL (30 >> 2)
-+#define NAND_T_SU (30 >> 2)
-+#define NAND_T_WH (30 >> 2)
-+
-+/* Bitfield shift amounts */
-+#define NAND_T_H_SHIFT 0
-+#define NAND_T_PUL_SHIFT 4
-+#define NAND_T_SU_SHIFT 8
-+#define NAND_T_WH_SHIFT 12
-+
-+#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
-+ ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-+ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
-+ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
-+
-+
-+/*
-+ * External Interrupts for Pb1200 as of 8/6/2004.
-+ * Bit positions in the CPLD registers can be calculated by taking
-+ * the interrupt define and subtracting the PB1200_INT_BEGIN value.
-+ * *example: IDE bis pos is = 64 - 64
-+ ETH bit pos is = 65 - 64
-+ */
-+#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
-+#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0)
-+#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1)
-+#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2)
-+#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3)
-+#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4)
-+#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5)
-+#define PB1200_DC_INT (PB1200_INT_BEGIN + 6)
-+#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7)
-+#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8)
-+#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9)
-+#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10)
-+#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11)
-+#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12)
-+#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13)
-+#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14)
-+#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15)
-+
-+#define PB1200_INT_END (PB1200_INT_BEGIN + 15)
-+
-+/* For drivers/pcmcia/au1000_db1x00.c */
-+#define BOARD_PC0_INT PB1200_PC0_INT
-+#define BOARD_PC1_INT PB1200_PC1_INT
-+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
-+
-+#endif /* __ASM_PB1200_H */
-+
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-rm200/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-rm200/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-rm200/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-rm200/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -31,6 +31,7 @@
- #define cpu_has_vtag_icache 0
- #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_has_nofpuex 0
- #define cpu_has_64bits 1
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-sibyte/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-sibyte/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-sibyte/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -25,6 +25,7 @@
- #define cpu_has_vtag_icache 1
- #define cpu_has_dc_aliases 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_icache_snoops_remote_store 0
-
- #define cpu_has_nofpuex 0
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mach-yosemite/cpu-feature-overrides.h linux_HEAD/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
---- linux-2.6.12/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2005-07-01 12:10:28.000000000 +0200
-@@ -25,6 +25,7 @@
- #define cpu_has_vtag_icache 0
- #define cpu_has_dc_aliases 0
- #define cpu_has_ic_fills_f_dc 0
-+#define cpu_has_dsp 0
- #define cpu_icache_snoops_remote_store 0
-
- #define cpu_has_nofpuex 0
-@@ -36,10 +37,4 @@
- #define cpu_icache_line_size() 32
- #define cpu_scache_line_size() 32
-
--/*
-- * On the RM9000 we need to ensure that I-cache lines being fetches only
-- * contain valid instructions are funny things will happen.
-- */
--#define PLAT_TRAMPOLINE_STUFF_LINE 32UL
--
- #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mips-boards/generic.h linux_HEAD/include/asm-mips/mips-boards/generic.h
---- linux-2.6.12/include/asm-mips/mips-boards/generic.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mips-boards/generic.h 2005-07-01 12:10:28.000000000 +0200
-@@ -79,4 +79,10 @@
-
- extern unsigned int mips_revision_corid;
-
-+#ifdef CONFIG_PCI
-+extern void mips_pcibios_init(void);
-+#else
-+#define mips_pcibios_init() do { } while (0)
-+#endif
-+
- #endif /* __ASM_MIPS_BOARDS_GENERIC_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mips-boards/msc01_pci.h linux_HEAD/include/asm-mips/mips-boards/msc01_pci.h
---- linux-2.6.12/include/asm-mips/mips-boards/msc01_pci.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mips-boards/msc01_pci.h 2005-07-10 12:28:27.000000000 +0200
-@@ -1,8 +1,9 @@
- /*
- * PCI Register definitions for the MIPS System Controller.
- *
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
-@@ -167,29 +168,29 @@
- #define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
-
- /* The defines below are ONLY valid for a MEM bar! */
--#define MSC01_PCI_BAR0_SIZE_SHF 4
--#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
--#define MSC01_PCI_BAR0_P_SHF 3
--#define MSC01_PCI_BAR0_P_MSK 0x00000008
--#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
--#define MSC01_PCI_BAR0_D_SHF 1
--#define MSC01_PCI_BAR0_D_MSK 0x00000006
--#define MSC01_PCI_BAR0_T_SHF 0
--#define MSC01_PCI_BAR0_T_MSK 0x00000001
--#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
--
--
--#define MSC01_PCI_CFG_RA_SHF 17
--#define MSC01_PCI_CFG_RA_MSK 0x00020000
--#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
--#define MSC01_PCI_CFG_G_SHF 16
--#define MSC01_PCI_CFG_G_MSK 0x00010000
--#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
--#define MSC01_PCI_CFG_EN_SHF 15
--#define MSC01_PCI_CFG_EN_MSK 0x00008000
--#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
--#define MSC01_PCI_CFG_MAXRTRY_SHF 0
--#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff
-+#define MSC01_PCI_BAR0_SIZE_SHF 4
-+#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
-+#define MSC01_PCI_BAR0_P_SHF 3
-+#define MSC01_PCI_BAR0_P_MSK 0x00000008
-+#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
-+#define MSC01_PCI_BAR0_D_SHF 1
-+#define MSC01_PCI_BAR0_D_MSK 0x00000006
-+#define MSC01_PCI_BAR0_T_SHF 0
-+#define MSC01_PCI_BAR0_T_MSK 0x00000001
-+#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
-+
-+
-+#define MSC01_PCI_CFG_RA_SHF 17
-+#define MSC01_PCI_CFG_RA_MSK 0x00020000
-+#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
-+#define MSC01_PCI_CFG_G_SHF 16
-+#define MSC01_PCI_CFG_G_MSK 0x00010000
-+#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
-+#define MSC01_PCI_CFG_EN_SHF 15
-+#define MSC01_PCI_CFG_EN_MSK 0x00008000
-+#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
-+#define MSC01_PCI_CFG_MAXRTRY_SHF 0
-+#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
-
- #define MSC01_PCI_SWAP_IO_SHF 18
- #define MSC01_PCI_SWAP_IO_MSK 0x000c0000
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mipsregs.h linux_HEAD/include/asm-mips/mipsregs.h
---- linux-2.6.12/include/asm-mips/mipsregs.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mipsregs.h 2005-07-01 12:10:27.000000000 +0200
-@@ -8,7 +8,7 @@
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, kevink at mips.com and Carsten Langgaard, carstenl at mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
-- * Copyright (C) 2003 Maciej W. Rozycki
-+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
- */
- #ifndef _ASM_MIPSREGS_H
- #define _ASM_MIPSREGS_H
-@@ -281,6 +281,11 @@
- #define ST0_DL (_ULCAST_(1) << 24)
-
- /*
-+ * Enable the MIPS DSP ASE
-+ */
-+#define ST0_MX 0x01000000
-+
-+/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
- #define TX39_CONF_ICS_SHIFT 19
-@@ -433,6 +438,14 @@
- #define R5K_CONF_SE (_ULCAST_(1) << 12)
- #define R5K_CONF_SS (_ULCAST_(3) << 20)
-
-+/* Bits specific to the RM7000. */
-+#define RM7K_CONF_SE (_ULCAST_(1) << 3)
-+#define RM7K_CONF_TE (_ULCAST_(1) << 12)
-+#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
-+#define RM7K_CONF_TC (_ULCAST_(1) << 17)
-+#define RM7K_CONF_SI (_ULCAST_(3) << 20)
-+#define RM7K_CONF_SC (_ULCAST_(1) << 31)
-+
- /* Bits specific to the R10000. */
- #define R10K_CONF_DN (_ULCAST_(3) << 3)
- #define R10K_CONF_CT (_ULCAST_(1) << 5)
-@@ -475,6 +488,52 @@
- #define MIPS_CONF_M (_ULCAST_(1) << 31)
-
- /*
-+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
-+ */
-+#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
-+#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
-+#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
-+#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
-+#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
-+#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
-+#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
-+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
-+#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
-+#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
-+#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
-+#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
-+#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
-+#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
-+
-+#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
-+#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
-+#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
-+#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
-+#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
-+#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
-+#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
-+#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
-+
-+#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
-+#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
-+#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
-+#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
-+#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
-+#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
-+#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
-+
-+/*
-+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
-+ */
-+#define MIPS_FPIR_S (_ULCAST_(1) << 16)
-+#define MIPS_FPIR_D (_ULCAST_(1) << 17)
-+#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
-+#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
-+#define MIPS_FPIR_W (_ULCAST_(1) << 20)
-+#define MIPS_FPIR_L (_ULCAST_(1) << 21)
-+#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
-+
-+/*
- * R10000 performance counter definitions.
- *
- * FIXME: The R10000 performance counter opens a nice way to implement CPU
-@@ -790,10 +849,18 @@ do { \
- #define read_c0_config1() __read_32bit_c0_register($16, 1)
- #define read_c0_config2() __read_32bit_c0_register($16, 2)
- #define read_c0_config3() __read_32bit_c0_register($16, 3)
-+#define read_c0_config4() __read_32bit_c0_register($16, 4)
-+#define read_c0_config5() __read_32bit_c0_register($16, 5)
-+#define read_c0_config6() __read_32bit_c0_register($16, 6)
-+#define read_c0_config7() __read_32bit_c0_register($16, 7)
- #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
- #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
- #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
- #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
-+#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
-+#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
-+#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
-+#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
-
- /*
- * The WatchLo register. There may be upto 8 of them.
-@@ -930,6 +997,284 @@ do { \
- : "=r" (__res)); \
- __res;})
-
-+#define rddsp(mask) \
-+({ \
-+ unsigned int __res; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # rddsp $1, %x1 \n" \
-+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__res) \
-+ : "i" (mask)); \
-+ __res; \
-+})
-+
-+#define wrdsp(val, mask) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # wrdsp $1, %x1 \n" \
-+ " .word 0x7c2004f8 | (%x1 << 15) \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (val), "i" (mask)); \
-+} while (0)
-+
-+#if 0 /* Need DSP ASE capable assembler ... */
-+#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
-+#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
-+#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
-+#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
-+
-+#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
-+#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
-+#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
-+#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
-+
-+#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
-+#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
-+#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
-+#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
-+
-+#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
-+#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
-+#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
-+#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
-+
-+#else
-+
-+#define mfhi0() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mfhi %0, $ac0 \n" \
-+ " .word 0x00000810 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mfhi1() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mfhi %0, $ac1 \n" \
-+ " .word 0x00200810 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mfhi2() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mfhi %0, $ac2 \n" \
-+ " .word 0x00400810 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mfhi3() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mfhi %0, $ac3 \n" \
-+ " .word 0x00600810 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mflo0() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mflo %0, $ac0 \n" \
-+ " .word 0x00000812 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mflo1() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mflo %0, $ac1 \n" \
-+ " .word 0x00200812 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mflo2() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mflo %0, $ac2 \n" \
-+ " .word 0x00400812 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mflo3() \
-+({ \
-+ unsigned long __treg; \
-+ \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " # mflo %0, $ac3 \n" \
-+ " .word 0x00600812 \n" \
-+ " move %0, $1 \n" \
-+ " .set pop \n" \
-+ : "=r" (__treg)); \
-+ __treg; \
-+})
-+
-+#define mthi0(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mthi $1, $ac0 \n" \
-+ " .word 0x00200011 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mthi1(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mthi $1, $ac1 \n" \
-+ " .word 0x00200811 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mthi2(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mthi $1, $ac2 \n" \
-+ " .word 0x00201011 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mthi3(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mthi $1, $ac3 \n" \
-+ " .word 0x00201811 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mtlo0(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mtlo $1, $ac0 \n" \
-+ " .word 0x00200013 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mtlo1(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mtlo $1, $ac1 \n" \
-+ " .word 0x00200813 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mtlo2(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mtlo $1, $ac2 \n" \
-+ " .word 0x00201013 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#define mtlo3(x) \
-+do { \
-+ __asm__ __volatile__( \
-+ " .set push \n" \
-+ " .set noat \n" \
-+ " move $1, %0 \n" \
-+ " # mtlo $1, $ac3 \n" \
-+ " .word 0x00201813 \n" \
-+ " .set pop \n" \
-+ : \
-+ : "r" (x)); \
-+} while (0)
-+
-+#endif
-+
- /*
- * TLB operations.
- *
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/mmu_context.h linux_HEAD/include/asm-mips/mmu_context.h
---- linux-2.6.12/include/asm-mips/mmu_context.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/mmu_context.h 2005-07-08 12:04:09.000000000 +0200
-@@ -30,7 +30,7 @@ extern unsigned long pgd_current[];
-
- #ifdef CONFIG_MIPS32
- #define TLBMISS_HANDLER_SETUP() \
-- write_c0_context((unsigned long) smp_processor_id() << 23); \
-+ write_c0_context((unsigned long) smp_processor_id() << 25); \
- TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
- #endif
- #if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
-@@ -40,7 +40,7 @@ extern unsigned long pgd_current[];
- #endif
- #if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
- #define TLBMISS_HANDLER_SETUP() \
-- write_c0_context((unsigned long) smp_processor_id() << 23); \
-+ write_c0_context((unsigned long) smp_processor_id() << 26); \
- TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
- #endif
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/module.h linux_HEAD/include/asm-mips/module.h
---- linux-2.6.12/include/asm-mips/module.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/module.h 2005-01-31 02:45:43.000000000 +0100
-@@ -14,15 +14,23 @@ struct mod_arch_specific {
-
- typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
-
--typedef struct
--{
-- Elf64_Addr r_offset; /* Address of relocation. */
-- Elf64_Word r_sym; /* Symbol index. */
-- Elf64_Byte r_ssym; /* Special symbol. */
-- Elf64_Byte r_type3; /* Third relocation. */
-- Elf64_Byte r_type2; /* Second relocation. */
-- Elf64_Byte r_type; /* First relocation. */
-- Elf64_Sxword r_addend; /* Addend. */
-+typedef struct {
-+ Elf64_Addr r_offset; /* Address of relocation. */
-+ Elf64_Word r_sym; /* Symbol index. */
-+ Elf64_Byte r_ssym; /* Special symbol. */
-+ Elf64_Byte r_type3; /* Third relocation. */
-+ Elf64_Byte r_type2; /* Second relocation. */
-+ Elf64_Byte r_type; /* First relocation. */
-+} Elf64_Mips_Rel;
-+
-+typedef struct {
-+ Elf64_Addr r_offset; /* Address of relocation. */
-+ Elf64_Word r_sym; /* Symbol index. */
-+ Elf64_Byte r_ssym; /* Special symbol. */
-+ Elf64_Byte r_type3; /* Third relocation. */
-+ Elf64_Byte r_type2; /* Second relocation. */
-+ Elf64_Byte r_type; /* First relocation. */
-+ Elf64_Sxword r_addend; /* Addend. */
- } Elf64_Mips_Rela;
-
- #ifdef CONFIG_MIPS32
-@@ -30,6 +38,13 @@ typedef struct
- #define Elf_Shdr Elf32_Shdr
- #define Elf_Sym Elf32_Sym
- #define Elf_Ehdr Elf32_Ehdr
-+#define Elf_Addr Elf32_Addr
-+
-+#define Elf_Mips_Rel Elf32_Rel
-+#define Elf_Mips_Rela Elf32_Rela
-+
-+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
-+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
-
- #endif
-
-@@ -38,6 +53,13 @@ typedef struct
- #define Elf_Shdr Elf64_Shdr
- #define Elf_Sym Elf64_Sym
- #define Elf_Ehdr Elf64_Ehdr
-+#define Elf_Addr Elf64_Addr
-+
-+#define Elf_Mips_Rel Elf64_Mips_Rel
-+#define Elf_Mips_Rela Elf64_Mips_Rela
-+
-+#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
-+#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
-
- #endif
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/paccess.h linux_HEAD/include/asm-mips/paccess.h
---- linux-2.6.12/include/asm-mips/paccess.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/paccess.h 2005-03-04 21:13:41.000000000 +0100
-@@ -52,7 +52,7 @@ struct __large_pstruct { unsigned long b
- })
-
- #define __get_dbe_asm(insn) \
--({ \
-+{ \
- __asm__ __volatile__( \
- "1:\t" insn "\t%1,%2\n\t" \
- "move\t%0,$0\n" \
-@@ -67,7 +67,7 @@ struct __large_pstruct { unsigned long b
- ".previous" \
- :"=r" (__gu_err), "=r" (__gu_val) \
- :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \
--})
-+}
-
- extern void __get_dbe_unknown(void);
-
-@@ -90,7 +90,7 @@ extern void __get_dbe_unknown(void);
- })
-
- #define __put_dbe_asm(insn) \
--({ \
-+{ \
- __asm__ __volatile__( \
- "1:\t" insn "\t%1,%2\n\t" \
- "move\t%0,$0\n" \
-@@ -104,7 +104,7 @@ extern void __get_dbe_unknown(void);
- ".previous" \
- : "=r" (__pu_err) \
- : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \
--})
-+}
-
- extern void __put_dbe_unknown(void);
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/page.h linux_HEAD/include/asm-mips/page.h
---- linux-2.6.12/include/asm-mips/page.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/page.h 2005-07-07 11:23:06.000000000 +0200
-@@ -76,7 +76,7 @@ static inline void copy_user_page(void *
- * These are used to make use of C type-checking..
- */
- #ifdef CONFIG_64BIT_PHYS_ADDR
-- #ifdef CONFIG_CPU_MIPS32
-+ #ifdef CONFIG_CPU_MIPS32_R1
- typedef struct { unsigned long pte_low, pte_high; } pte_t;
- #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
- #else
-@@ -87,21 +87,48 @@ static inline void copy_user_page(void *
- typedef struct { unsigned long pte; } pte_t;
- #define pte_val(x) ((x).pte)
- #endif
-+#define __pte(x) ((pte_t) { (x) } )
-
--typedef struct { unsigned long pmd; } pmd_t;
--typedef struct { unsigned long pgd; } pgd_t;
--typedef struct { unsigned long pgprot; } pgprot_t;
-+/*
-+ * For 3-level pagetables we defines these ourselves, for 2-level the
-+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
-+ */
-+#ifdef CONFIG_MIPS64
-
-+typedef struct { unsigned long pmd; } pmd_t;
- #define pmd_val(x) ((x).pmd)
-+#define __pmd(x) ((pmd_t) { (x) } )
-+
-+#endif
-+
-+/*
-+ * Right now we don't support 4-level pagetables, so all pud-related
-+ * definitions come from <asm-generic/pgtable-nopud.h>.
-+ */
-+
-+/*
-+ * Finall the top of the hierarchy, the pgd
-+ */
-+typedef struct { unsigned long pgd; } pgd_t;
- #define pgd_val(x) ((x).pgd)
-+#define __pgd(x) ((pgd_t) { (x) } )
-+
-+/*
-+ * Manipulate page protection bits
-+ */
-+typedef struct { unsigned long pgprot; } pgprot_t;
- #define pgprot_val(x) ((x).pgprot)
-+#define __pgprot(x) ((pgprot_t) { (x) } )
-
-+/*
-+ * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
-+ * pair of pages we only have a single global bit per pair of pages. When
-+ * writing to the TLB make sure we always have the bit set for both pages
-+ * or none. This macro is used to access the `buddy' of the pte we're just
-+ * working on.
-+ */
- #define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
-
--#define __pte(x) ((pte_t) { (x) } )
--#define __pmd(x) ((pmd_t) { (x) } )
--#define __pgd(x) ((pgd_t) { (x) } )
--#define __pgprot(x) ((pgprot_t) { (x) } )
-
- /* Pure 2^n version of get_order */
- static __inline__ int get_order(unsigned long size)
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/pgalloc.h linux_HEAD/include/asm-mips/pgalloc.h
---- linux-2.6.12/include/asm-mips/pgalloc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/pgalloc.h 2005-02-17 21:50:43.000000000 +0100
-@@ -26,10 +26,22 @@ static inline void pmd_populate(struct m
- }
-
- /*
-+ * Initialize a new pmd table with invalid pointers.
-+ */
-+extern void pmd_init(unsigned long page, unsigned long pagetable);
-+
-+#ifdef CONFIG_MIPS64
-+
-+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-+{
-+ set_pud(pud, __pud((unsigned long)pmd));
-+}
-+#endif
-+
-+/*
- * Initialize a new pgd / pmd table with invalid pointers.
- */
- extern void pgd_init(unsigned long page);
--extern void pmd_init(unsigned long page, unsigned long pagetable);
-
- static inline pgd_t *pgd_alloc(struct mm_struct *mm)
- {
-@@ -86,21 +98,18 @@ static inline void pte_free(struct page
- #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
-
- #ifdef CONFIG_MIPS32
--#define pgd_populate(mm, pmd, pte) BUG()
-
- /*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
--#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
- #define pmd_free(x) do { } while (0)
- #define __pmd_free_tlb(tlb,x) do { } while (0)
-+
- #endif
-
- #ifdef CONFIG_MIPS64
-
--#define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd))
--
- static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
- {
- pmd_t *pmd;
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/pgtable-32.h linux_HEAD/include/asm-mips/pgtable-32.h
---- linux-2.6.12/include/asm-mips/pgtable-32.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/pgtable-32.h 2005-07-07 11:23:06.000000000 +0200
-@@ -17,6 +17,8 @@
- #include <asm/cachectl.h>
- #include <asm/fixmap.h>
-
-+#include <asm-generic/pgtable-nopmd.h>
-+
- /*
- * - add_wired_entry() add a fixed TLB entry, and move wired register
- */
-@@ -41,42 +43,38 @@ extern int add_temporary_entry(unsigned
- * works even with the cache aliasing problem the R4k and above have.
- */
-
--/* PMD_SHIFT determines the size of the area a second-level page table can map */
-+/* PGDIR_SHIFT determines what a third-level page table entry can map */
- #ifdef CONFIG_64BIT_PHYS_ADDR
--#define PMD_SHIFT 21
-+#define PGDIR_SHIFT 21
- #else
--#define PMD_SHIFT 22
-+#define PGDIR_SHIFT 22
- #endif
--#define PMD_SIZE (1UL << PMD_SHIFT)
--#define PMD_MASK (~(PMD_SIZE-1))
--
--/* PGDIR_SHIFT determines what a third-level page table entry can map */
--#define PGDIR_SHIFT PMD_SHIFT
- #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
- #define PGDIR_MASK (~(PGDIR_SIZE-1))
-
- /*
- * Entries per page directory level: we use two-level, so
-- * we don't really have any PMD directory physically.
-+ * we don't really have any PUD/PMD directory physically.
- */
- #ifdef CONFIG_64BIT_PHYS_ADDR
- #define PGD_ORDER 1
--#define PMD_ORDER 0
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
-+#define PMD_ORDER 1
- #define PTE_ORDER 0
- #else
- #define PGD_ORDER 0
--#define PMD_ORDER 0
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
-+#define PMD_ORDER 1
- #define PTE_ORDER 0
- #endif
-
- #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
--#define PTRS_PER_PMD 1
- #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-
- #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
- #define FIRST_USER_ADDRESS 0
-
--#define VMALLOC_START KSEG2
-+#define VMALLOC_START MAP_BASE
-
- #ifdef CONFIG_HIGHMEM
- # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
-@@ -91,8 +89,6 @@ extern int add_temporary_entry(unsigned
- #define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
- #endif
--#define pmd_ERROR(e) \
-- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
- #define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-@@ -120,17 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp
- pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
- }
-
--/*
-- * The "pgd_xxx()" functions here are trivial for a folded two-level
-- * setup: the pgd is never bad, and a pmd always exists (as it's folded
-- * into the pgd entry)
-- */
--static inline int pgd_none(pgd_t pgd) { return 0; }
--static inline int pgd_bad(pgd_t pgd) { return 0; }
--static inline int pgd_present(pgd_t pgd) { return 1; }
--static inline void pgd_clear(pgd_t *pgdp) { }
--
--#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- #define pte_page(x) pfn_to_page(pte_pfn(x))
- #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
- static inline pte_t
-@@ -153,25 +139,20 @@ pfn_pte(unsigned long pfn, pgprot_t prot
- #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
- #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
- #endif
--#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
-+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
-
- #define __pgd_offset(address) pgd_index(address)
-+#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
- #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
- /* to find an entry in a kernel page-table-directory */
- #define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
--#define pgd_index(address) ((address) >> PGDIR_SHIFT)
-+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
- /* to find an entry in a page-table-directory */
- #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
-
--/* Find an entry in the second-level page table.. */
--static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
--{
-- return (pmd_t *) dir;
--}
--
- /* Find an entry in the third-level page table.. */
- #define __pte_offset(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-@@ -221,7 +202,7 @@ static inline pmd_t *pmd_offset(pgd_t *d
- */
- #define PTE_FILE_MAX_BITS 27
-
--#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- /* fixme */
- #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
- #define pgoff_to_pte(off) \
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/pgtable-64.h linux_HEAD/include/asm-mips/pgtable-64.h
---- linux-2.6.12/include/asm-mips/pgtable-64.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/pgtable-64.h 2005-04-30 15:33:58.000000000 +0200
-@@ -16,13 +16,15 @@
- #include <asm/page.h>
- #include <asm/cachectl.h>
-
-+#include <asm-generic/pgtable-nopud.h>
-+
- /*
- * Each address space has 2 4K pages as its page directory, giving 1024
- * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
-- * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to
-- * page tables. Each page table is a single 4K page, giving 512 (==
-- * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to
-- * invalid_pmd_table, each pmde is initialized to point to
-+ * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
-+ * tables. Each page table is also a single 4K page, giving 512 (==
-+ * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
-+ * invalid_pmd_table, each pmd entry is initialized to point to
- * invalid_pte_table, each pte is initialized to 0. When memory is low,
- * and a pmd table or a page table allocation fails, empty_bad_pmd_table
- * and empty_bad_page_table is returned back to higher layer code, so
-@@ -36,17 +38,17 @@
- */
-
- /* PMD_SHIFT determines the size of the area a second-level page table can map */
--#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
-+#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
- #define PMD_SIZE (1UL << PMD_SHIFT)
- #define PMD_MASK (~(PMD_SIZE-1))
-
- /* PGDIR_SHIFT determines what a third-level page table entry can map */
--#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3))
-+#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
- #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
- #define PGDIR_MASK (~(PGDIR_SIZE-1))
-
- /*
-- * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which
-+ * For 4kB page size we use a 3 level page tree and an 8kB pud, which
- * permits us mapping 40 bits of virtual address space.
- *
- * We used to implement 41 bits by having an order 1 pmd level but that seemed
-@@ -57,7 +59,7 @@
- * two levels would be easy to implement.
- *
- * For 16kB page size we use a 2 level page tree which permits a total of
-- * 36 bits of virtual address space. We could add a third leve. but it seems
-+ * 36 bits of virtual address space. We could add a third level but it seems
- * like at the moment there's no need for this.
- *
- * For 64kB page size we use a 2 level page table tree for a total of 42 bits
-@@ -65,21 +67,25 @@
- */
- #ifdef CONFIG_PAGE_SIZE_4KB
- #define PGD_ORDER 1
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
- #define PMD_ORDER 0
- #define PTE_ORDER 0
- #endif
- #ifdef CONFIG_PAGE_SIZE_8KB
- #define PGD_ORDER 0
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
- #define PMD_ORDER 0
- #define PTE_ORDER 0
- #endif
- #ifdef CONFIG_PAGE_SIZE_16KB
- #define PGD_ORDER 0
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
- #define PMD_ORDER 0
- #define PTE_ORDER 0
- #endif
- #ifdef CONFIG_PAGE_SIZE_64KB
- #define PGD_ORDER 0
-+#define PUD_ORDER aieeee_attempt_to_allocate_pud
- #define PMD_ORDER 0
- #define PTE_ORDER 0
- #endif
-@@ -91,7 +97,7 @@
- #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
- #define FIRST_USER_ADDRESS 0
-
--#define VMALLOC_START XKSEG
-+#define VMALLOC_START MAP_BASE
- #define VMALLOC_END \
- (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
-
-@@ -102,13 +108,13 @@
- #define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
-
--extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
--extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
--extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
--extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
-+extern pte_t invalid_pte_table[PTRS_PER_PTE];
-+extern pte_t empty_bad_page_table[PTRS_PER_PTE];
-+extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
-+extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
-
- /*
-- * Empty pmd entries point to the invalid_pte_table.
-+ * Empty pgd/pmd entries point to the invalid_pte_table.
- */
- static inline int pmd_none(pmd_t pmd)
- {
-@@ -128,26 +134,30 @@ static inline void pmd_clear(pmd_t *pmdp
- }
-
- /*
-- * Empty pgd entries point to the invalid_pmd_table.
-+ * Empty pud entries point to the invalid_pmd_table.
- */
--static inline int pgd_none(pgd_t pgd)
-+static inline int pud_none(pud_t pud)
- {
-- return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
-+ return pud_val(pud) == (unsigned long) invalid_pmd_table;
- }
-
--#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK)
-+static inline int pud_bad(pud_t pud)
-+{
-+ return pud_val(pud) & ~PAGE_MASK;
-+}
-
--static inline int pgd_present(pgd_t pgd)
-+static inline int pud_present(pud_t pud)
- {
-- return pgd_val(pgd) != (unsigned long) invalid_pmd_table;
-+ return pud_val(pud) != (unsigned long) invalid_pmd_table;
- }
-
--static inline void pgd_clear(pgd_t *pgdp)
-+static inline void pud_clear(pud_t *pudp)
- {
-- pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
-+ pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
- }
-
--#define pte_page(x) pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
-+#define pte_page(x) pfn_to_page(pte_pfn(x))
-+
- #ifdef CONFIG_CPU_VR41XX
- #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
- #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
-@@ -157,26 +167,28 @@ static inline void pgd_clear(pgd_t *pgdp
- #endif
-
- #define __pgd_offset(address) pgd_index(address)
-+#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
-+#define __pmd_offset(address) pmd_index(address)
- #define page_pte(page) page_pte_prot(page, __pgprot(0))
-
- /* to find an entry in a kernel page-table-directory */
- #define pgd_offset_k(address) pgd_offset(&init_mm, 0)
-
--#define pgd_index(address) ((address) >> PGDIR_SHIFT)
-+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-+#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
- /* to find an entry in a page-table-directory */
- #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
-
--static inline unsigned long pgd_page(pgd_t pgd)
-+static inline unsigned long pud_page(pud_t pud)
- {
-- return pgd_val(pgd);
-+ return pud_val(pud);
- }
-
- /* Find an entry in the second-level page table.. */
--static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
-+static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
- {
-- return (pmd_t *) pgd_page(*dir) +
-- ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
-+ return (pmd_t *) pud_page(*pud) + pmd_index(address);
- }
-
- /* Find an entry in the third-level page table.. */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/pgtable-bits.h linux_HEAD/include/asm-mips/pgtable-bits.h
---- linux-2.6.12/include/asm-mips/pgtable-bits.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/pgtable-bits.h 2005-07-07 11:23:06.000000000 +0200
-@@ -33,7 +33,7 @@
- * unpredictable things. The code (when it is written) to deal with
- * this problem will be in the update_mmu_cache() code for the r4k.
- */
--#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
-+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
-
- #define _PAGE_PRESENT (1<<6) /* implemented in software */
- #define _PAGE_READ (1<<7) /* implemented in software */
-@@ -123,7 +123,7 @@
-
- #endif
- #endif
--#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
-+#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
-
- #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
- #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-@@ -140,7 +140,7 @@
- #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
- #endif
-
--#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
-+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
- #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
- #else
- #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/pgtable.h linux_HEAD/include/asm-mips/pgtable.h
---- linux-2.6.12/include/asm-mips/pgtable.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/pgtable.h 2005-07-07 11:23:06.000000000 +0200
-@@ -8,8 +8,6 @@
- #ifndef _ASM_PGTABLE_H
- #define _ASM_PGTABLE_H
-
--#include <asm-generic/4level-fixup.h>
--
- #include <linux/config.h>
- #ifdef CONFIG_MIPS32
- #include <asm/pgtable-32.h>
-@@ -82,7 +80,7 @@ extern void paging_init(void);
- #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
- #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
-
--#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- static inline void set_pte(pte_t *ptep, pte_t pte)
- {
- ptep->pte_high = pte.pte_high;
-@@ -146,11 +144,18 @@ static inline void pte_clear(struct mm_s
- #endif
-
- /*
-- * (pmds are folded into pgds so this doesn't get actually called,
-+ * (pmds are folded into puds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
- #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
--#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0)
-+
-+#ifdef CONFIG_MIPS64
-+/*
-+ * (puds are folded into pgds so this doesn't get actually called,
-+ * but the define is needed for a generic inline function.)
-+ */
-+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
-+#endif
-
- #define PGD_T_LOG2 ffz(~sizeof(pgd_t))
- #define PMD_T_LOG2 ffz(~sizeof(pmd_t))
-@@ -163,7 +168,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD
- * Undefined behaviour if not..
- */
- static inline int pte_user(pte_t pte) { BUG(); return 0; }
--#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; }
- static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; }
- static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; }
-@@ -322,7 +327,7 @@ static inline pgprot_t pgprot_noncached(
- */
- #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-
--#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
- {
- pte.pte_low &= _PAGE_CHG_MASK;
-@@ -375,7 +380,7 @@ static inline int io_remap_pfn_range(str
- pgprot_t prot)
- {
- phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-- return remap_pfn_range(vma, vaddr, pfn, size, prot);
-+ return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
- }
- #else
- #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/processor.h linux_HEAD/include/asm-mips/processor.h
---- linux-2.6.12/include/asm-mips/processor.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/processor.h 2005-07-01 12:10:27.000000000 +0200
-@@ -96,12 +96,26 @@ union mips_fpu_union {
- {{0,},} \
- }
-
-+#define NUM_DSP_REGS 6
-+
-+typedef __u32 dspreg_t;
-+
-+struct mips_dsp_state {
-+ dspreg_t dspr[NUM_DSP_REGS];
-+ unsigned int dspcontrol;
-+ unsigned short used_dsp;
-+};
-+
-+#define INIT_DSP {{0,},}
-+
- typedef struct {
- unsigned long seg;
- } mm_segment_t;
-
- #define ARCH_MIN_TASKALIGN 8
-
-+struct mips_abi;
-+
- /*
- * If you change thread_struct remember to change the #defines below too!
- */
-@@ -117,6 +131,9 @@ struct thread_struct {
- /* Saved fpu/fpu emulator stuff. */
- union mips_fpu_union fpu;
-
-+ /* Saved state of the DSP ASE, if available. */
-+ struct mips_dsp_state dsp;
-+
- /* Other stuff associated with the thread. */
- unsigned long cp0_badvaddr; /* Last user fault */
- unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
-@@ -129,6 +146,7 @@ struct thread_struct {
- unsigned long mflags;
- unsigned long irix_trampoline; /* Wheee... */
- unsigned long irix_oldctx;
-+ struct mips_abi *abi;
- };
-
- #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
-@@ -151,6 +169,10 @@ struct thread_struct {
- */ \
- INIT_FPU, \
- /* \
-+ * saved dsp/dsp emulator stuff \
-+ */ \
-+ INIT_DSP, \
-+ /* \
- * Other stuff associated with the process \
- */ \
- 0, 0, 0, 0, \
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/ptrace.h linux_HEAD/include/asm-mips/ptrace.h
---- linux-2.6.12/include/asm-mips/ptrace.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/ptrace.h 2005-07-01 12:10:27.000000000 +0200
-@@ -22,6 +22,8 @@
- #define MMLO 68
- #define FPC_CSR 69
- #define FPC_EIR 70
-+#define DSP_BASE 71 /* 3 more hi / lo register pairs */
-+#define DSP_CONTROL 77
-
- /*
- * This struct defines the way the registers are stored on the stack during a
-@@ -38,8 +40,8 @@ struct pt_regs {
-
- /* Saved special registers. */
- unsigned long cp0_status;
-- unsigned long lo;
- unsigned long hi;
-+ unsigned long lo;
- unsigned long cp0_badvaddr;
- unsigned long cp0_cause;
- unsigned long cp0_epc;
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/serial.h linux_HEAD/include/asm-mips/serial.h
---- linux-2.6.12/include/asm-mips/serial.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/serial.h 2005-03-04 20:36:14.000000000 +0100
-@@ -78,16 +78,6 @@
- #define JAZZ_SERIAL_PORT_DEFNS
- #endif
-
--#ifdef CONFIG_MIPS_COBALT
--#include <asm/cobalt/cobalt.h>
--#define COBALT_BASE_BAUD (18432000 / 16)
--#define COBALT_SERIAL_PORT_DEFNS \
-- /* UART CLK PORT IRQ FLAGS */ \
-- { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
--#else
--#define COBALT_SERIAL_PORT_DEFNS
--#endif
--
- /*
- * Both Galileo boards have the same UART mappings.
- */
-@@ -139,17 +129,6 @@
- #define IVR_SERIAL_PORT_DEFNS
- #endif
-
--#ifdef CONFIG_TOSHIBA_JMR3927
--#include <asm/jmr3927/jmr3927.h>
--#define TXX927_SERIAL_PORT_DEFNS \
-- { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
-- .flags = UART0_FLAGS, .type = 1 }, \
-- { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
-- .flags = UART1_FLAGS, .type = 1 },
--#else
--#define TXX927_SERIAL_PORT_DEFNS
--#endif
--
- #ifdef CONFIG_SERIAL_AU1X00
- #include <asm/mach-au1x00/au1000.h>
- #ifdef CONFIG_SOC_AU1000
-@@ -309,9 +288,9 @@
- #define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
-
- #define _JAGUAR_ATX_SERIAL_INIT(int, base) \
-- { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
-- flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
-- iomem_base: (u8 *) base, iomem_reg_shift: 2, \
-+ { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
-+ .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
-+ .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
- io_type: SERIAL_IO_MEM }
- #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
- _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
-@@ -325,9 +304,9 @@
- #define OCELOT_3_SERIAL_BASE (signed)0xfd000020
-
- #define _OCELOT_3_SERIAL_INIT(int, base) \
-- { baud_base: OCELOT_3_BASE_BAUD, irq: int, \
-- flags: STD_COM_FLAGS, \
-- iomem_base: (u8 *) base, iomem_reg_shift: 2, \
-+ { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
-+ .flags = STD_COM_FLAGS, \
-+ .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
- io_type: SERIAL_IO_MEM }
-
- #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
-@@ -424,7 +403,6 @@
- #endif /* CONFIG_SGI_IP32 */
-
- #define SERIAL_PORT_DFNS \
-- COBALT_SERIAL_PORT_DEFNS \
- DDB5477_SERIAL_PORT_DEFNS \
- EV96100_SERIAL_PORT_DEFNS \
- EXTRA_SERIAL_PORT_DEFNS \
-@@ -438,7 +416,6 @@
- MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
- MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
- MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
-- TXX927_SERIAL_PORT_DEFNS \
- AU1000_SERIAL_PORT_DEFNS
-
- #endif /* _ASM_SERIAL_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/sibyte/board.h linux_HEAD/include/asm-mips/sibyte/board.h
---- linux-2.6.12/include/asm-mips/sibyte/board.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/sibyte/board.h 2005-02-17 21:50:45.000000000 +0100
-@@ -21,8 +21,6 @@
-
- #include <linux/config.h>
-
--#ifdef CONFIG_SIBYTE_BOARD
--
- #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
- defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
- defined(CONFIG_SIBYTE_LITTLESUR)
-@@ -54,16 +52,6 @@
- #define setleds(t0,t1,c0,c1,c2,c3)
- #endif /* LEDS_PHYS */
-
--#else
--
--#ifdef LEDS_PHYS
--extern void setleds(char *str);
--#else
--#define setleds(s) do { } while (0)
--#endif /* LEDS_PHYS */
--
- #endif /* __ASSEMBLY__ */
-
--#endif /* CONFIG_SIBYTE_BOARD */
--
- #endif /* _SIBYTE_BOARD_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/sibyte/sb1250.h linux_HEAD/include/asm-mips/sibyte/sb1250.h
---- linux-2.6.12/include/asm-mips/sibyte/sb1250.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/sibyte/sb1250.h 2005-02-24 00:13:20.000000000 +0100
-@@ -58,6 +58,6 @@ extern void prom_printf(char *fmt, ...);
-
- #endif
-
--#define IOADDR(a) (IO_BASE + (a))
-+#define IOADDR(a) ((void *)(IO_BASE + (a)))
-
- #endif
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/sigcontext.h linux_HEAD/include/asm-mips/sigcontext.h
---- linux-2.6.12/include/asm-mips/sigcontext.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/sigcontext.h 2005-07-01 12:10:27.000000000 +0200
-@@ -27,14 +27,15 @@ struct sigcontext {
- unsigned int sc_fpc_csr;
- unsigned int sc_fpc_eir; /* Unused */
- unsigned int sc_used_math;
-- unsigned int sc_ssflags; /* Unused */
-+ unsigned int sc_dsp; /* dsp status, was sc_ssflags */
- unsigned long long sc_mdhi;
- unsigned long long sc_mdlo;
--
-- unsigned int sc_cause; /* Unused */
-- unsigned int sc_badvaddr; /* Unused */
--
-- unsigned long sc_sigset[4]; /* kernel's sigset_t */
-+ unsigned long sc_hi1; /* Was sc_cause */
-+ unsigned long sc_lo1; /* Was sc_badvaddr */
-+ unsigned long sc_hi2; /* Was sc_sigset[4] */
-+ unsigned long sc_lo2;
-+ unsigned long sc_hi3;
-+ unsigned long sc_lo3;
- };
-
- #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-@@ -48,19 +49,19 @@ struct sigcontext {
- * Warning: this structure illdefined with sc_badvaddr being just an unsigned
- * int so it was changed to unsigned long in 2.6.0-test1. This may break
- * binary compatibility - no prisoners.
-+ * DSP ASE in 2.6.12-rc4. Turn sc_mdhi and sc_mdlo into an array of four
-+ * entries, add sc_dsp and sc_reserved for padding. No prisoners.
- */
- struct sigcontext {
- unsigned long sc_regs[32];
- unsigned long sc_fpregs[32];
-- unsigned long sc_mdhi;
-- unsigned long sc_mdlo;
-+ unsigned long sc_hi[4];
-+ unsigned long sc_lo[4];
- unsigned long sc_pc;
-- unsigned long sc_badvaddr;
-- unsigned int sc_status;
- unsigned int sc_fpc_csr;
-- unsigned int sc_fpc_eir;
- unsigned int sc_used_math;
-- unsigned int sc_cause;
-+ unsigned int sc_dsp;
-+ unsigned int sc_reserved;
- };
-
- #ifdef __KERNEL__
-@@ -68,23 +69,24 @@ struct sigcontext {
- #include <linux/posix_types.h>
-
- struct sigcontext32 {
-- __u32 sc_regmask; /* Unused */
-- __u32 sc_status;
-- __u64 sc_pc;
-- __u64 sc_regs[32];
-- __u64 sc_fpregs[32];
-- __u32 sc_ownedfp; /* Unused */
-- __u32 sc_fpc_csr;
-- __u32 sc_fpc_eir; /* Unused */
-- __u32 sc_used_math;
-- __u32 sc_ssflags; /* Unused */
-- __u64 sc_mdhi;
-- __u64 sc_mdlo;
--
-- __u32 sc_cause; /* Unused */
-- __u32 sc_badvaddr; /* Unused */
--
-- __u32 sc_sigset[4]; /* kernel's sigset_t */
-+ __u32 sc_regmask; /* Unused */
-+ __u32 sc_status;
-+ __u64 sc_pc;
-+ __u64 sc_regs[32];
-+ __u64 sc_fpregs[32];
-+ __u32 sc_ownedfp; /* Unused */
-+ __u32 sc_fpc_csr;
-+ __u32 sc_fpc_eir; /* Unused */
-+ __u32 sc_used_math;
-+ __u32 sc_dsp; /* dsp status, was sc_ssflags */
-+ __u64 sc_mdhi;
-+ __u64 sc_mdlo;
-+ __u32 sc_hi1; /* Was sc_cause */
-+ __u32 sc_lo1; /* Was sc_badvaddr */
-+ __u32 sc_hi2; /* Was sc_sigset[4] */
-+ __u32 sc_lo2;
-+ __u32 sc_hi3;
-+ __u32 sc_lo3;
- };
- #endif /* __KERNEL__ */
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/siginfo.h linux_HEAD/include/asm-mips/siginfo.h
---- linux-2.6.12/include/asm-mips/siginfo.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/siginfo.h 2005-07-01 12:10:27.000000000 +0200
-@@ -11,6 +11,7 @@
-
- #include <linux/config.h>
-
-+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
- #undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */
-
- #define HAVE_ARCH_SIGINFO_T
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/signal.h linux_HEAD/include/asm-mips/signal.h
---- linux-2.6.12/include/asm-mips/signal.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/signal.h 2005-07-01 12:10:27.000000000 +0200
-@@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t; /*
- #define MINSIGSTKSZ 2048
- #define SIGSTKSZ 8192
-
-+#ifdef __KERNEL__
-+
-+/*
-+ * These values of sa_flags are used only by the kernel as part of the
-+ * irq handling routines.
-+ *
-+ * SA_INTERRUPT is also used by the irq handling routines.
-+ * SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
-+ */
-+#define SA_SAMPLE_RANDOM SA_RESTART
-+
-+#ifdef CONFIG_TRAD_SIGNALS
-+#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO)
-+#else
-+#define sig_uses_siginfo(ka) (1)
-+#endif
-+
-+#endif /* __KERNEL__ */
-+
- #define SIG_BLOCK 1 /* for blocking signals */
- #define SIG_UNBLOCK 2 /* for unblocking signals */
- #define SIG_SETMASK 3 /* for setting the signal mask */
- #define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility:
- set only the low 32 bit of the sigset. */
--#include <asm-generic/signal.h>
-+
-+/* Type of a signal handler. */
-+typedef void __signalfn_t(int);
-+typedef __signalfn_t __user *__sighandler_t;
-+
-+/* Fake signal functions */
-+#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
-+#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
-+#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
-
- struct sigaction {
- unsigned int sa_flags;
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/spinlock.h linux_HEAD/include/asm-mips/spinlock.h
---- linux-2.6.12/include/asm-mips/spinlock.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/spinlock.h 2005-04-15 15:04:44.000000000 +0200
-@@ -140,6 +140,18 @@ typedef struct {
-
- #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
-
-+/*
-+ * read_can_lock - would read_trylock() succeed?
-+ * @lock: the rwlock in question.
-+ */
-+#define read_can_lock(rw) ((rw)->lock >= 0)
-+
-+/*
-+ * write_can_lock - would write_trylock() succeed?
-+ * @lock: the rwlock in question.
-+ */
-+#define write_can_lock(rw) (!(rw)->lock)
-+
- static inline void _raw_read_lock(rwlock_t *rw)
- {
- unsigned int tmp;
-@@ -218,8 +230,7 @@ static inline void _raw_write_lock(rwloc
- " lui %1, 0x8000 \n"
- " sc %1, %0 \n"
- " beqzl %1, 1b \n"
-- " nop \n"
-- " sync \n"
-+ " sync \n"
- " .set reorder \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
-@@ -232,8 +243,7 @@ static inline void _raw_write_lock(rwloc
- " lui %1, 0x8000 \n"
- " sc %1, %0 \n"
- " beqz %1, 1b \n"
-- " nop \n"
-- " sync \n"
-+ " sync \n"
- " .set reorder \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
-@@ -267,8 +277,7 @@ static inline int _raw_write_trylock(rwl
- " lui %1, 0x8000 \n"
- " sc %1, %0 \n"
- " beqzl %1, 1b \n"
-- " nop \n"
-- " sync \n"
-+ " sync \n"
- " li %2, 1 \n"
- " .set reorder \n"
- "2: \n"
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/stackframe.h linux_HEAD/include/asm-mips/stackframe.h
---- linux-2.6.12/include/asm-mips/stackframe.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/stackframe.h 2005-07-08 12:02:03.000000000 +0200
-@@ -60,7 +60,6 @@
- mfc0 k0, CP0_CONTEXT
- lui k1, %hi(kernelsp)
- srl k0, k0, 23
-- sll k0, k0, 2
- addu k1, k0
- LONG_L k1, %lo(kernelsp)(k1)
- #endif
-@@ -76,9 +75,14 @@
- #endif
- #if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
- MFC0 k1, CP0_CONTEXT
-+ lui k0, %highest(kernelsp)
- dsrl k1, 23
-- dsll k1, k1, 3
-- LONG_L k1, kernelsp(k1)
-+ daddiu k0, %higher(kernelsp)
-+ dsll k0, k0, 16
-+ daddiu k0, %hi(kernelsp)
-+ dsll k0, k0, 16
-+ daddu k1, k1, k0
-+ LONG_L k1, %lo(kernelsp)(k1)
- #endif
- .endm
-
-@@ -86,25 +90,28 @@
- #ifdef CONFIG_MIPS32
- mfc0 \temp, CP0_CONTEXT
- srl \temp, 23
-- sll \temp, 2
-- LONG_S \stackp, kernelsp(\temp)
- #endif
- #if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
- lw \temp, TI_CPU(gp)
- dsll \temp, 3
-- lui \temp2, %hi(kernelsp)
-- daddu \temp, \temp2
-- LONG_S \stackp, %lo(kernelsp)(\temp)
- #endif
- #if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
-- lw \temp, TI_CPU(gp)
-- dsll \temp, 3
-- LONG_S \stackp, kernelsp(\temp)
-+ MFC0 \temp, CP0_CONTEXT
-+ dsrl \temp, 23
- #endif
-+ LONG_S \stackp, kernelsp(\temp)
- .endm
- #else
- .macro get_saved_sp /* Uniprocessor variation */
-+#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
-+ lui k1, %highest(kernelsp)
-+ daddiu k1, %higher(kernelsp)
-+ dsll k1, k1, 16
-+ daddiu k1, %hi(kernelsp)
-+ dsll k1, k1, 16
-+#else
- lui k1, %hi(kernelsp)
-+#endif
- LONG_L k1, %lo(kernelsp)(k1)
- .endm
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/system.h linux_HEAD/include/asm-mips/system.h
---- linux-2.6.12/include/asm-mips/system.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/system.h 2005-07-01 12:10:28.000000000 +0200
-@@ -17,6 +17,7 @@
-
- #include <asm/addrspace.h>
- #include <asm/cpu-features.h>
-+#include <asm/dsp.h>
- #include <asm/ptrace.h>
- #include <asm/war.h>
- #include <asm/interrupt.h>
-@@ -154,9 +155,13 @@ extern asmlinkage void *resume(void *las
-
- struct task_struct;
-
--#define switch_to(prev,next,last) \
--do { \
-- (last) = resume(prev, next, next->thread_info); \
-+#define switch_to(prev,next,last) \
-+do { \
-+ if (cpu_has_dsp) \
-+ __save_dsp(prev); \
-+ (last) = resume(prev, next, next->thread_info); \
-+ if (cpu_has_dsp) \
-+ __restore_dsp(current); \
- } while(0)
-
- #define ROT_IN_PIECES \
-@@ -171,14 +176,18 @@ static inline unsigned long __xchg_u32(v
- unsigned long dummy;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %3 # xchg_u32 \n"
-+ " .set mips0 \n"
- " move %2, %z4 \n"
-+ " .set mips3 \n"
- " sc %2, %1 \n"
- " beqzl %2, 1b \n"
- ROT_IN_PIECES
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
-@@ -186,13 +195,17 @@ static inline unsigned long __xchg_u32(v
- unsigned long dummy;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: ll %0, %3 # xchg_u32 \n"
-+ " .set mips0 \n"
- " move %2, %z4 \n"
-+ " .set mips3 \n"
- " sc %2, %1 \n"
- " beqz %2, 1b \n"
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
-@@ -217,6 +230,7 @@ static inline __u64 __xchg_u64(volatile
- unsigned long dummy;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %3 # xchg_u64 \n"
- " move %2, %z4 \n"
- " scd %2, %1 \n"
-@@ -225,6 +239,7 @@ static inline __u64 __xchg_u64(volatile
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
-@@ -232,6 +247,7 @@ static inline __u64 __xchg_u64(volatile
- unsigned long dummy;
-
- __asm__ __volatile__(
-+ " .set mips3 \n"
- "1: lld %0, %3 # xchg_u64 \n"
- " move %2, %z4 \n"
- " scd %2, %1 \n"
-@@ -239,6 +255,7 @@ static inline __u64 __xchg_u64(volatile
- #ifdef CONFIG_SMP
- " sync \n"
- #endif
-+ " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
-@@ -286,7 +303,9 @@ static inline unsigned long __cmpxchg_u3
-
- if (cpu_has_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__(
-+ " .set push \n"
- " .set noat \n"
-+ " .set mips3 \n"
- "1: ll %0, %2 # __cmpxchg_u32 \n"
- " bne %0, %z3, 2f \n"
- " move $1, %z4 \n"
-@@ -297,13 +316,15 @@ static inline unsigned long __cmpxchg_u3
- " sync \n"
- #endif
- "2: \n"
-- " .set at \n"
-+ " .set pop \n"
- : "=&r" (retval), "=m" (*m)
- : "R" (*m), "Jr" (old), "Jr" (new)
- : "memory");
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
-+ " .set push \n"
- " .set noat \n"
-+ " .set mips3 \n"
- "1: ll %0, %2 # __cmpxchg_u32 \n"
- " bne %0, %z3, 2f \n"
- " move $1, %z4 \n"
-@@ -313,7 +334,7 @@ static inline unsigned long __cmpxchg_u3
- " sync \n"
- #endif
- "2: \n"
-- " .set at \n"
-+ " .set pop \n"
- : "=&r" (retval), "=m" (*m)
- : "R" (*m), "Jr" (old), "Jr" (new)
- : "memory");
-@@ -338,7 +359,9 @@ static inline unsigned long __cmpxchg_u6
-
- if (cpu_has_llsc) {
- __asm__ __volatile__(
-+ " .set push \n"
- " .set noat \n"
-+ " .set mips3 \n"
- "1: lld %0, %2 # __cmpxchg_u64 \n"
- " bne %0, %z3, 2f \n"
- " move $1, %z4 \n"
-@@ -349,13 +372,15 @@ static inline unsigned long __cmpxchg_u6
- " sync \n"
- #endif
- "2: \n"
-- " .set at \n"
-+ " .set pop \n"
- : "=&r" (retval), "=m" (*m)
- : "R" (*m), "Jr" (old), "Jr" (new)
- : "memory");
- } else if (cpu_has_llsc) {
- __asm__ __volatile__(
-+ " .set push \n"
- " .set noat \n"
-+ " .set mips3 \n"
- "1: lld %0, %2 # __cmpxchg_u64 \n"
- " bne %0, %z3, 2f \n"
- " move $1, %z4 \n"
-@@ -365,7 +390,7 @@ static inline unsigned long __cmpxchg_u6
- " sync \n"
- #endif
- "2: \n"
-- " .set at \n"
-+ " .set pop \n"
- : "=&r" (retval), "=m" (*m)
- : "R" (*m), "Jr" (old), "Jr" (new)
- : "memory");
-@@ -410,7 +435,7 @@ extern void *set_except_vector(int n, vo
- extern void per_cpu_trap_init(void);
-
- extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
-- const char *func, unsigned long line);
-+ const char *func, unsigned long line) ATTRIB_NORET;
- extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
- const char *func, unsigned long line);
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/thread_info.h linux_HEAD/include/asm-mips/thread_info.h
---- linux-2.6.12/include/asm-mips/thread_info.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/thread_info.h 2005-04-13 19:06:39.000000000 +0200
-@@ -26,6 +26,7 @@ struct thread_info {
- struct task_struct *task; /* main task structure */
- struct exec_domain *exec_domain; /* execution domain */
- unsigned long flags; /* low level flags */
-+ unsigned long tp_value; /* thread pointer */
- __u32 cpu; /* current CPU */
- __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
-
-@@ -114,6 +115,7 @@ register struct thread_info *__current_t
- #define TIF_SIGPENDING 2 /* signal pending */
- #define TIF_NEED_RESCHED 3 /* rescheduling necessary */
- #define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */
-+#define TIF_SECCOMP 5 /* secure computing */
- #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
- #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
- #define TIF_MEMDIE 18
-@@ -124,13 +126,14 @@ register struct thread_info *__current_t
- #define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
- #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
- #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
-+#define _TIF_SECCOMP (1<<TIF_SECCOMP)
- #define _TIF_USEDFPU (1<<TIF_USEDFPU)
- #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
-
--#define _TIF_WORK_MASK 0x0000ffef /* work to do on
-- interrupt/exception return */
--#define _TIF_ALLWORK_MASK 0x8000ffff /* work to do on any return to
-- u-space */
-+/* work to do on interrupt/exception return */
-+#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
-+/* work to do on any return to u-space */
-+#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP)
-
- #endif /* __KERNEL__ */
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/uaccess.h linux_HEAD/include/asm-mips/uaccess.h
---- linux-2.6.12/include/asm-mips/uaccess.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/uaccess.h 2005-03-21 20:04:59.000000000 +0100
-@@ -129,7 +129,8 @@
- *
- * See access_ok() for more details.
- */
--static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-+static inline int __deprecated verify_area(int type, const void __user * addr,
-+ unsigned long size)
- {
- return access_ok(type, addr, size) ? 0 : -EFAULT;
- }
-@@ -219,63 +220,58 @@ static inline int __deprecated verify_ar
- __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
-
- struct __large_struct { unsigned long buf[100]; };
--#define __m(x) (*(struct __large_struct *)(x))
-+#define __m(x) (*(struct __large_struct __user *)(x))
-
- /*
- * Yuck. We need two variants, one for 64bit operation and one
- * for 32 bit mode and old iron.
- */
- #ifdef __mips64
--#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err)
-+#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr)
- #else
--#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err)
-+#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr)
- #endif
-
- #define __get_user_nocheck(x,ptr,size) \
- ({ \
-- __typeof(*(ptr)) __gu_val = 0; \
-- long __gu_addr; \
-+ __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \
- long __gu_err = 0; \
- \
- might_sleep(); \
-- __gu_addr = (long) (ptr); \
- switch (size) { \
-- case 1: __get_user_asm("lb", __gu_err); break; \
-- case 2: __get_user_asm("lh", __gu_err); break; \
-- case 4: __get_user_asm("lw", __gu_err); break; \
-- case 8: __GET_USER_DW(__gu_err); break; \
-+ case 1: __get_user_asm("lb", ptr); break; \
-+ case 2: __get_user_asm("lh", ptr); break; \
-+ case 4: __get_user_asm("lw", ptr); break; \
-+ case 8: __GET_USER_DW(ptr); break; \
- default: __get_user_unknown(); break; \
- } \
-- x = (__typeof__(*(ptr))) __gu_val; \
-+ (x) = (__typeof__(*(ptr))) __gu_val; \
- __gu_err; \
- })
-
- #define __get_user_check(x,ptr,size) \
- ({ \
-+ const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \
- __typeof__(*(ptr)) __gu_val = 0; \
-- long __gu_addr; \
-- long __gu_err; \
-+ long __gu_err = -EFAULT; \
- \
- might_sleep(); \
-- __gu_addr = (long) (ptr); \
-- __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size) \
-- ? 0 : -EFAULT; \
- \
-- if (likely(!__gu_err)) { \
-+ if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \
- switch (size) { \
-- case 1: __get_user_asm("lb", __gu_err); break; \
-- case 2: __get_user_asm("lh", __gu_err); break; \
-- case 4: __get_user_asm("lw", __gu_err); break; \
-- case 8: __GET_USER_DW(__gu_err); break; \
-+ case 1: __get_user_asm("lb", __gu_addr); break; \
-+ case 2: __get_user_asm("lh", __gu_addr); break; \
-+ case 4: __get_user_asm("lw", __gu_addr); break; \
-+ case 8: __GET_USER_DW(__gu_addr); break; \
- default: __get_user_unknown(); break; \
- } \
- } \
-- x = (__typeof__(*(ptr))) __gu_val; \
-+ (x) = (__typeof__(*(ptr))) __gu_val; \
- __gu_err; \
- })
-
--#define __get_user_asm(insn,__gu_err) \
--({ \
-+#define __get_user_asm(insn, addr) \
-+{ \
- __asm__ __volatile__( \
- "1: " insn " %1, %3 \n" \
- "2: \n" \
-@@ -287,20 +283,20 @@ struct __large_struct { unsigned long bu
- " "__UA_ADDR "\t1b, 3b \n" \
- " .previous \n" \
- : "=r" (__gu_err), "=r" (__gu_val) \
-- : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT)); \
--})
-+ : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \
-+}
-
- /*
- * Get a long long 64 using 32 bit registers.
- */
--#define __get_user_asm_ll32(__gu_err) \
--({ \
-+#define __get_user_asm_ll32(addr) \
-+{ \
- __asm__ __volatile__( \
-- "1: lw %1, %3 \n" \
-- "2: lw %D1, %4 \n" \
-+ "1: lw %1, (%3) \n" \
-+ "2: lw %D1, 4(%3) \n" \
- " move %0, $0 \n" \
- "3: .section .fixup,\"ax\" \n" \
-- "4: li %0, %5 \n" \
-+ "4: li %0, %4 \n" \
- " move %1, $0 \n" \
- " move %D1, $0 \n" \
- " j 3b \n" \
-@@ -310,9 +306,8 @@ struct __large_struct { unsigned long bu
- " " __UA_ADDR " 2b, 4b \n" \
- " .previous \n" \
- : "=r" (__gu_err), "=&r" (__gu_val) \
-- : "0" (__gu_err), "o" (__m(__gu_addr)), \
-- "o" (__m(__gu_addr + 4)), "i" (-EFAULT)); \
--})
-+ : "0" (0), "r" (addr), "i" (-EFAULT)); \
-+}
-
- extern void __get_user_unknown(void);
-
-@@ -321,25 +316,23 @@ extern void __get_user_unknown(void);
- * for 32 bit mode and old iron.
- */
- #ifdef __mips64
--#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val)
-+#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
- #else
--#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val)
-+#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
- #endif
-
- #define __put_user_nocheck(x,ptr,size) \
- ({ \
- __typeof__(*(ptr)) __pu_val; \
-- long __pu_addr; \
- long __pu_err = 0; \
- \
- might_sleep(); \
- __pu_val = (x); \
-- __pu_addr = (long) (ptr); \
- switch (size) { \
-- case 1: __put_user_asm("sb", __pu_val); break; \
-- case 2: __put_user_asm("sh", __pu_val); break; \
-- case 4: __put_user_asm("sw", __pu_val); break; \
-- case 8: __PUT_USER_DW(__pu_val); break; \
-+ case 1: __put_user_asm("sb", ptr); break; \
-+ case 2: __put_user_asm("sh", ptr); break; \
-+ case 4: __put_user_asm("sw", ptr); break; \
-+ case 8: __PUT_USER_DW(ptr); break; \
- default: __put_user_unknown(); break; \
- } \
- __pu_err; \
-@@ -347,30 +340,26 @@ extern void __get_user_unknown(void);
-
- #define __put_user_check(x,ptr,size) \
- ({ \
-- __typeof__(*(ptr)) __pu_val; \
-- long __pu_addr; \
-- long __pu_err; \
-+ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
-+ __typeof__(*(ptr)) __pu_val = (x); \
-+ long __pu_err = -EFAULT; \
- \
- might_sleep(); \
-- __pu_val = (x); \
-- __pu_addr = (long) (ptr); \
-- __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size) \
-- ? 0 : -EFAULT; \
- \
-- if (likely(!__pu_err)) { \
-+ if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
- switch (size) { \
-- case 1: __put_user_asm("sb", __pu_val); break; \
-- case 2: __put_user_asm("sh", __pu_val); break; \
-- case 4: __put_user_asm("sw", __pu_val); break; \
-- case 8: __PUT_USER_DW(__pu_val); break; \
-+ case 1: __put_user_asm("sb", __pu_addr); break; \
-+ case 2: __put_user_asm("sh", __pu_addr); break; \
-+ case 4: __put_user_asm("sw", __pu_addr); break; \
-+ case 8: __PUT_USER_DW(__pu_addr); break; \
- default: __put_user_unknown(); break; \
- } \
- } \
- __pu_err; \
- })
-
--#define __put_user_asm(insn, __pu_val) \
--({ \
-+#define __put_user_asm(insn, ptr) \
-+{ \
- __asm__ __volatile__( \
- "1: " insn " %z2, %3 # __put_user_asm\n" \
- "2: \n" \
-@@ -382,18 +371,18 @@ extern void __get_user_unknown(void);
- " " __UA_ADDR " 1b, 3b \n" \
- " .previous \n" \
- : "=r" (__pu_err) \
-- : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)), \
-+ : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)), \
- "i" (-EFAULT)); \
--})
-+}
-
--#define __put_user_asm_ll32(__pu_val) \
--({ \
-+#define __put_user_asm_ll32(ptr) \
-+{ \
- __asm__ __volatile__( \
-- "1: sw %2, %3 # __put_user_asm_ll32 \n" \
-- "2: sw %D2, %4 \n" \
-+ "1: sw %2, (%3) # __put_user_asm_ll32 \n" \
-+ "2: sw %D2, 4(%3) \n" \
- "3: \n" \
- " .section .fixup,\"ax\" \n" \
-- "4: li %0, %5 \n" \
-+ "4: li %0, %4 \n" \
- " j 3b \n" \
- " .previous \n" \
- " .section __ex_table,\"a\" \n" \
-@@ -401,9 +390,9 @@ extern void __get_user_unknown(void);
- " " __UA_ADDR " 2b, 4b \n" \
- " .previous" \
- : "=r" (__pu_err) \
-- : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)), \
-- "o" (__m(__pu_addr + 4)), "i" (-EFAULT)); \
--})
-+ : "0" (0), "r" (__pu_val), "r" (ptr), \
-+ "i" (-EFAULT)); \
-+}
-
- extern void __put_user_unknown(void);
-
-@@ -426,7 +415,7 @@ extern size_t __copy_user(void *__to, co
-
- #define __invoke_copy_to_user(to,from,n) \
- ({ \
-- register void *__cu_to_r __asm__ ("$4"); \
-+ register void __user *__cu_to_r __asm__ ("$4"); \
- register const void *__cu_from_r __asm__ ("$5"); \
- register long __cu_len_r __asm__ ("$6"); \
- \
-@@ -458,7 +447,7 @@ extern size_t __copy_user(void *__to, co
- */
- #define __copy_to_user(to,from,n) \
- ({ \
-- void *__cu_to; \
-+ void __user __user *__cu_to; \
- const void *__cu_from; \
- long __cu_len; \
- \
-@@ -488,7 +477,7 @@ extern size_t __copy_user(void *__to, co
- */
- #define copy_to_user(to,from,n) \
- ({ \
-- void *__cu_to; \
-+ void __user *__cu_to; \
- const void *__cu_from; \
- long __cu_len; \
- \
-@@ -505,7 +494,7 @@ extern size_t __copy_user(void *__to, co
- #define __invoke_copy_from_user(to,from,n) \
- ({ \
- register void *__cu_to_r __asm__ ("$4"); \
-- register const void *__cu_from_r __asm__ ("$5"); \
-+ register const void __user *__cu_from_r __asm__ ("$5"); \
- register long __cu_len_r __asm__ ("$6"); \
- \
- __cu_to_r = (to); \
-@@ -544,7 +533,7 @@ extern size_t __copy_user(void *__to, co
- #define __copy_from_user(to,from,n) \
- ({ \
- void *__cu_to; \
-- const void *__cu_from; \
-+ const void __user *__cu_from; \
- long __cu_len; \
- \
- might_sleep(); \
-@@ -575,7 +564,7 @@ extern size_t __copy_user(void *__to, co
- #define copy_from_user(to,from,n) \
- ({ \
- void *__cu_to; \
-- const void *__cu_from; \
-+ const void __user *__cu_from; \
- long __cu_len; \
- \
- might_sleep(); \
-@@ -592,8 +581,8 @@ extern size_t __copy_user(void *__to, co
-
- #define copy_in_user(to,from,n) \
- ({ \
-- void *__cu_to; \
-- const void *__cu_from; \
-+ void __user *__cu_to; \
-+ const void __user *__cu_from; \
- long __cu_len; \
- \
- might_sleep(); \
-@@ -619,7 +608,7 @@ extern size_t __copy_user(void *__to, co
- * On success, this will be zero.
- */
- static inline __kernel_size_t
--__clear_user(void *addr, __kernel_size_t size)
-+__clear_user(void __user *addr, __kernel_size_t size)
- {
- __kernel_size_t res;
-
-@@ -639,7 +628,7 @@ __clear_user(void *addr, __kernel_size_t
-
- #define clear_user(addr,n) \
- ({ \
-- void * __cl_addr = (addr); \
-+ void __user * __cl_addr = (addr); \
- unsigned long __cl_size = (n); \
- if (__cl_size && access_ok(VERIFY_WRITE, \
- ((unsigned long)(__cl_addr)), __cl_size)) \
-@@ -668,7 +657,7 @@ __clear_user(void *addr, __kernel_size_t
- * and returns @count.
- */
- static inline long
--__strncpy_from_user(char *__to, const char *__from, long __len)
-+__strncpy_from_user(char *__to, const char __user *__from, long __len)
- {
- long res;
-
-@@ -705,7 +694,7 @@ __strncpy_from_user(char *__to, const ch
- * and returns @count.
- */
- static inline long
--strncpy_from_user(char *__to, const char *__from, long __len)
-+strncpy_from_user(char *__to, const char __user *__from, long __len)
- {
- long res;
-
-@@ -724,7 +713,7 @@ strncpy_from_user(char *__to, const char
- }
-
- /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
--static inline long __strlen_user(const char *s)
-+static inline long __strlen_user(const char __user *s)
- {
- long res;
-
-@@ -754,7 +743,7 @@ static inline long __strlen_user(const c
- * If there is a limit on the length of a valid string, you may wish to
- * consider using strnlen_user() instead.
- */
--static inline long strlen_user(const char *s)
-+static inline long strlen_user(const char __user *s)
- {
- long res;
-
-@@ -771,7 +760,7 @@ static inline long strlen_user(const cha
- }
-
- /* Returns: 0 if bad, string length+1 (memory size) of string if ok */
--static inline long __strnlen_user(const char *s, long n)
-+static inline long __strnlen_user(const char __user *s, long n)
- {
- long res;
-
-@@ -802,7 +791,7 @@ static inline long __strnlen_user(const
- * If there is a limit on the length of a valid string, you may wish to
- * consider using strnlen_user() instead.
- */
--static inline long strnlen_user(const char *s, long n)
-+static inline long strnlen_user(const char __user *s, long n)
- {
- long res;
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/unistd.h linux_HEAD/include/asm-mips/unistd.h
---- linux-2.6.12/include/asm-mips/unistd.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/unistd.h 2005-04-13 19:06:39.000000000 +0200
-@@ -303,16 +303,17 @@
- #define __NR_add_key (__NR_Linux + 280)
- #define __NR_request_key (__NR_Linux + 281)
- #define __NR_keyctl (__NR_Linux + 282)
-+#define __NR_set_thread_area (__NR_Linux + 283)
-
- /*
- * Offset of the last Linux o32 flavoured syscall
- */
--#define __NR_Linux_syscalls 282
-+#define __NR_Linux_syscalls 283
-
- #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
- #define __NR_O32_Linux 4000
--#define __NR_O32_Linux_syscalls 282
-+#define __NR_O32_Linux_syscalls 283
-
- #if _MIPS_SIM == _MIPS_SIM_ABI64
-
-@@ -562,16 +563,17 @@
- #define __NR_add_key (__NR_Linux + 239)
- #define __NR_request_key (__NR_Linux + 240)
- #define __NR_keyctl (__NR_Linux + 241)
-+#define __NR_set_thread_area (__NR_Linux + 242)
-
- /*
- * Offset of the last Linux 64-bit flavoured syscall
- */
--#define __NR_Linux_syscalls 241
-+#define __NR_Linux_syscalls 242
-
- #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
-
- #define __NR_64_Linux 5000
--#define __NR_64_Linux_syscalls 241
-+#define __NR_64_Linux_syscalls 242
-
- #if _MIPS_SIM == _MIPS_SIM_NABI32
-
-@@ -825,16 +827,17 @@
- #define __NR_add_key (__NR_Linux + 243)
- #define __NR_request_key (__NR_Linux + 244)
- #define __NR_keyctl (__NR_Linux + 245)
-+#define __NR_set_thread_area (__NR_Linux + 246)
-
- /*
- * Offset of the last N32 flavoured syscall
- */
--#define __NR_Linux_syscalls 245
-+#define __NR_Linux_syscalls 246
-
- #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
-
- #define __NR_N32_Linux 6000
--#define __NR_N32_Linux_syscalls 245
-+#define __NR_N32_Linux_syscalls 246
-
- #ifndef __ASSEMBLY__
-
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/vr4181/irq.h linux_HEAD/include/asm-mips/vr4181/irq.h
---- linux-2.6.12/include/asm-mips/vr4181/irq.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/vr4181/irq.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,122 +0,0 @@
--/*
-- * Macros for vr4181 IRQ numbers.
-- *
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun at mvista.com or jsun at junsun.net
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- */
--
--/*
-- * Strategy:
-- *
-- * Vr4181 has conceptually three levels of interrupt controllers:
-- * 1. the CPU itself with 8 intr level.
-- * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
-- * 3. GPIO interrupts : forwarding external interrupts to sys intr controller
-- */
--
--/* decide the irq block assignment */
--#define VR4181_NUM_CPU_IRQ 8
--#define VR4181_NUM_SYS_IRQ 32
--#define VR4181_NUM_GPIO_IRQ 16
--
--#define VR4181_IRQ_BASE 0
--
--#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE
--#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
--#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
--
--/* CPU interrupts */
--
--/*
-- IP0 - Software interrupt
-- IP1 - Software interrupt
-- IP2 - All but battery, high speed modem, and real time clock
-- IP3 - RTC Long1 (system timer)
-- IP4 - RTC Long2
-- IP5 - High Speed Modem (unused on VR4181)
-- IP6 - Unused
-- IP7 - Timer interrupt from CPO_COMPARE
--*/
--
--#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0)
--#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1)
--#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2)
--#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3)
--#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4)
--#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5)
--#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6)
--#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7)
--
--
--/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
--
--/*
-- IP2 - same as VR4181_IRQ_INT1
-- IP8 - This is a cascade to GPIO IRQ's. Do not use.
-- IP16 - same as VR4181_IRQ_INT2
-- IP18 - CompactFlash
--*/
--
--#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0)
--#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1)
--#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2)
--#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3)
--#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4)
--#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5)
--#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6)
--#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7)
--#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8)
--#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9)
--#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10)
--#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11)
--#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12)
--#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13)
--#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14)
--#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15)
--#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16)
--#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17)
--#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18)
--#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19)
--#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20)
--#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21)
--#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22)
--#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23)
--#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24)
--#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25)
--#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26)
--#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27)
--#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28)
--#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29)
--#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30)
--#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31)
--
--/* Cascaded from VR4181_IRQ_GIU */
--#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0)
--#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1)
--#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2)
--#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3)
--#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4)
--#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5)
--#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6)
--#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7)
--#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8)
--#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9)
--#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10)
--#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11)
--#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12)
--#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13)
--#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14)
--#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15)
--
--
--// Alternative to above GPIO IRQ defines
--#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
--
--#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
-- VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/vr4181/vr4181.h linux_HEAD/include/asm-mips/vr4181/vr4181.h
---- linux-2.6.12/include/asm-mips/vr4181/vr4181.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/vr4181/vr4181.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,413 +0,0 @@
--/*
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License. See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- * Copyright (C) 1999 by Michael Klar
-- *
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: jsun at mvista.com or jsun at junsun.net
-- *
-- */
--#ifndef __ASM_VR4181_VR4181_H
--#define __ASM_VR4181_VR4181_H
--
--#include <asm/addrspace.h>
--
--#include <asm/vr4181/irq.h>
--
--#ifndef __ASSEMBLY__
--#define __preg8 (volatile unsigned char*)
--#define __preg16 (volatile unsigned short*)
--#define __preg32 (volatile unsigned int*)
--#else
--#define __preg8
--#define __preg16
--#define __preg32
--#endif
--
--// Embedded CPU peripheral registers
--// Note that many of the registers have different physical address for VR4181
--
--// Bus Control Unit (BCU)
--#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */
--#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */
--#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040
--#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020
--#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010
--#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008
--#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004
--#define VR4181_CMUCLKMSK_MSKADU18M 0x0002
--#define VR4181_CMUCLKMSK_MSKUSB 0x0001
--#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M
--#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */
--#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */
--#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */
--#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */
--#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */
--#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */
--#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */
--#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */
--
--// DMA Control Unit (DCU)
--#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */
--#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */
--#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */
--#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */
--#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */
--#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */
--#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */
--#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */
--#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */
--#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */
--#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */
--#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */
--#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */
--#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */
--#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */
--#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */
--#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */
--#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */
--#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */
--#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */
--#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */
--#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */
--#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */
--#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */
--#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */
--#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */
--#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */
--#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */
--#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */
--#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */
--#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */
--#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */
--#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */
--#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */
--#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */
--#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */
--#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */
--
--// ISA Bridge
--#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */
--#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */
--#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */
--
--// Clocked Serial Interface (CSI)
--#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */
--#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */
--#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */
--#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */
--#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */
--#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */
--#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */
--#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */
--
--// Interrupt Control Unit (ICU)
--#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */
--#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */
--#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */
--#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */
--#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */
--#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */
--#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */
--#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */
--#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */
--#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */
--#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */
--#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */
--
--// Power Management Unit (PMU)
--#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */
--#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */
--#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */
--#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */
--#define VR4181_PMUINT_RESET 0x8 /* Reset switch */
--#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */
--#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */
--#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */
--#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */
--#define VR4181_PMUINT_DCD 0x400 /* DCD# */
--#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */
--#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */
--#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */
--#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */
--
--#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */
--#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */
--#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */
--#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */
--
--// Real Time Clock Unit (RTC)
--#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */
--#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */
--#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */
--#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */
--#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */
--#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */
--#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */
--#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */
--#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */
--#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */
--#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */
--#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */
--#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */
--#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */
--#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */
--
--// Deadman's Switch Unit (DSU)
--#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */
--#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */
--#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */
--#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */
--
--// General Purpose I/O Unit (GIU)
--#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */
--#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */
--#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */
--#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */
--#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */
--#define VR4181_GPDATHREG_GPIO16 0x0001
--#define VR4181_GPDATHREG_GPIO17 0x0002
--#define VR4181_GPDATHREG_GPIO18 0x0004
--#define VR4181_GPDATHREG_GPIO19 0x0008
--#define VR4181_GPDATHREG_GPIO20 0x0010
--#define VR4181_GPDATHREG_GPIO21 0x0020
--#define VR4181_GPDATHREG_GPIO22 0x0040
--#define VR4181_GPDATHREG_GPIO23 0x0080
--#define VR4181_GPDATHREG_GPIO24 0x0100
--#define VR4181_GPDATHREG_GPIO25 0x0200
--#define VR4181_GPDATHREG_GPIO26 0x0400
--#define VR4181_GPDATHREG_GPIO27 0x0800
--#define VR4181_GPDATHREG_GPIO28 0x1000
--#define VR4181_GPDATHREG_GPIO29 0x2000
--#define VR4181_GPDATHREG_GPIO30 0x4000
--#define VR4181_GPDATHREG_GPIO31 0x8000
--#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */
--#define VR4181_GPDATLREG_GPIO0 0x0001
--#define VR4181_GPDATLREG_GPIO1 0x0002
--#define VR4181_GPDATLREG_GPIO2 0x0004
--#define VR4181_GPDATLREG_GPIO3 0x0008
--#define VR4181_GPDATLREG_GPIO4 0x0010
--#define VR4181_GPDATLREG_GPIO5 0x0020
--#define VR4181_GPDATLREG_GPIO6 0x0040
--#define VR4181_GPDATLREG_GPIO7 0x0080
--#define VR4181_GPDATLREG_GPIO8 0x0100
--#define VR4181_GPDATLREG_GPIO9 0x0200
--#define VR4181_GPDATLREG_GPIO10 0x0400
--#define VR4181_GPDATLREG_GPIO11 0x0800
--#define VR4181_GPDATLREG_GPIO12 0x1000
--#define VR4181_GPDATLREG_GPIO13 0x2000
--#define VR4181_GPDATLREG_GPIO14 0x4000
--#define VR4181_GPDATLREG_GPIO15 0x8000
--#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */
--#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */
--#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */
--#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */
--#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */
--#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */
--#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */
--#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */
--#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */
--#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */
--#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */
--#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */
--#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */
--#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */
--#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */
--#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */
--#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */
--#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
--#define VR4181_SECIRQMASKL VR4181_GPINTEN
--// No SECIRQMASKH for VR4181
--
--// Touch Panel Interface Unit (PIU)
--#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */
--#define VR4181_PIUCNTREG_PIUSEQEN 0x0004
--#define VR4181_PIUCNTREG_PIUPWR 0x0002
--#define VR4181_PIUCNTREG_PADRST 0x0001
--
--#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */
--#define VR4181_PIUINTREG_OVP 0x8000
--#define VR4181_PIUINTREG_PADCMD 0x0040
--#define VR4181_PIUINTREG_PADADP 0x0020
--#define VR4181_PIUINTREG_PADPAGE1 0x0010
--#define VR4181_PIUINTREG_PADPAGE0 0x0008
--#define VR4181_PIUINTREG_PADDLOST 0x0004
--#define VR4181_PIUINTREG_PENCHG 0x0001
--
--#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */
--#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */
--#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */
--#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */
--#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */
--#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */
--#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */
--#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */
--#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */
--#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */
--#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */
--#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */
--#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */
--#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */
--#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */
--#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */
--#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */
--#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */
--#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */
--#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */
--
--// Audio Interface Unit (AIU)
--#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */
--#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */
--#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */
--#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */
--#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */
--#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */
--#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */
--#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */
--#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */
--#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */
--#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */
--#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */
--#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */
--#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */
--
--// Keyboard Interface Unit (KIU)
--#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */
--#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */
--#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */
--#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */
--#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */
--#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */
--#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */
--#define VR4181_KIUSCANREP_KEYEN 0x8000
--#define VR4181_KIUSCANREP_SCANSTP 0x0008
--#define VR4181_KIUSCANREP_SCANSTART 0x0004
--#define VR4181_KIUSCANREP_ATSTP 0x0002
--#define VR4181_KIUSCANREP_ATSCAN 0x0001
--#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */
--#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */
--#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */
--#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */
--#define VR4181_KIUINT_KDATLOST 0x0004
--#define VR4181_KIUINT_KDATRDY 0x0002
--#define VR4181_KIUINT_SCANINT 0x0001
--#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */
--#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */
--
--// CompactFlash Controller
--#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */
--#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */
--#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */
--#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */
--#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */
--
--// LED Control Unit (LED)
--#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */
--#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */
--#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */
--#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */
--#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */
--
--// Serial Interface Unit (SIU / SIU1 and SIU2)
--#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */
--#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */
--#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
--#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */
--#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
--#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */
--#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */
--#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */
--#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */
--#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */
--#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */
--#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */
--#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */
--#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */
--#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */
--#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */
--#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */
--#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */
--#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */
--#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
--#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */
--#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */
--#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */
--#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */
--#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */
--#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */
--#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */
--#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */
--#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */
--#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */
--#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */
--#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */
--
--
--// USB Module
--#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */
--#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
--#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */
--#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */
--#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */
--#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */
--#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */
--
--// LCD Controller
--#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */
--#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */
--#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */
--#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */
--#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */
--#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */
--#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */
--#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */
--#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */
--#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */
--#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */
--#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */
--#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */
--#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */
--#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */
--#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */
--#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */
--#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */
--#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */
--#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */
--#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */
--#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */
--#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */
--
--// physical address spaces
--#define VR4181_LCD 0x0a000000
--#define VR4181_INTERNAL_IO_2 0x0b000000
--#define VR4181_INTERNAL_IO_1 0x0c000000
--#define VR4181_ISA_MEM 0x10000000
--#define VR4181_ISA_IO 0x14000000
--#define VR4181_ROM 0x18000000
--
--// This is the base address for IO port decoding to which the 16 bit IO port address
--// is added. Defining it to 0 will usually cause a kernel oops any time port IO is
--// attempted, which can be handy for turning up parts of the kernel that make
--// incorrect architecture assumptions (by assuming that everything acts like a PC),
--// but we need it correctly defined to use the PCMCIA/CF controller:
--#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO)
--#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM)
--
--#endif /* __ASM_VR4181_VR4181_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/vr41xx/siu.h linux_HEAD/include/asm-mips/vr41xx/siu.h
---- linux-2.6.12/include/asm-mips/vr41xx/siu.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/vr41xx/siu.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,50 +0,0 @@
--/*
-- * Include file for NEC VR4100 series Serial Interface Unit.
-- *
-- * Copyright (C) 2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#ifndef __NEC_VR41XX_SIU_H
--#define __NEC_VR41XX_SIU_H
--
--typedef enum {
-- SIU_INTERFACE_RS232C,
-- SIU_INTERFACE_IRDA,
--} siu_interface_t;
--
--extern void vr41xx_select_siu_interface(siu_interface_t interface);
--
--typedef enum {
-- SIU_USE_IRDA,
-- FIR_USE_IRDA,
--} irda_use_t;
--
--extern void vr41xx_use_irda(irda_use_t use);
--
--typedef enum {
-- SHARP_IRDA,
-- TEMIC_IRDA,
-- HP_IRDA,
--} irda_module_t;
--
--typedef enum {
-- IRDA_TX_1_5MBPS,
-- IRDA_TX_4MBPS,
--} irda_speed_t;
--
--extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
--
--#endif /* __NEC_VR41XX_SIU_H */
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/vr41xx/vr41xx.h linux_HEAD/include/asm-mips/vr41xx/vr41xx.h
---- linux-2.6.12/include/asm-mips/vr41xx/vr41xx.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/vr41xx/vr41xx.h 2005-07-01 12:10:28.000000000 +0200
-@@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clo
- #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
- #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
- #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
--#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2)
--#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3)
--#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4)
--#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5)
--#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6)
-+#define INT0_IRQ MIPS_CPU_IRQ(2)
-+#define INT1_IRQ MIPS_CPU_IRQ(3)
-+#define INT2_IRQ MIPS_CPU_IRQ(4)
-+#define INT3_IRQ MIPS_CPU_IRQ(5)
-+#define INT4_IRQ MIPS_CPU_IRQ(6)
- #define TIMER_IRQ MIPS_CPU_IRQ(7)
-
- /* SYINT1 Interrupt Numbers */
-@@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clo
- #define PIU_IRQ SYSINT1_IRQ(5)
- #define AIU_IRQ SYSINT1_IRQ(6)
- #define KIU_IRQ SYSINT1_IRQ(7)
--#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8)
-+#define GIUINT_IRQ SYSINT1_IRQ(8)
- #define SIU_IRQ SYSINT1_IRQ(9)
- #define BUSERR_IRQ SYSINT1_IRQ(10)
- #define SOFTINT_IRQ SYSINT1_IRQ(11)
-@@ -129,7 +129,7 @@ extern void vr41xx_mask_clock(vr41xx_clo
- #define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */
-
- extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
--extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
-+extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
-
- #define PIUINT_COMMAND 0x0040
- #define PIUINT_DATA 0x0020
-diff -urpNX dontdiff linux-2.6.12/include/asm-mips/war.h linux_HEAD/include/asm-mips/war.h
---- linux-2.6.12/include/asm-mips/war.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/asm-mips/war.h 2005-07-01 12:10:28.000000000 +0200
-@@ -177,6 +177,17 @@
- #endif
-
- /*
-+ * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
-+ * where invalid instructions in the same I-cache line worth of instructions
-+ * being fetched may case spurious exceptions.
-+ */
-+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
-+ defined(CONFIG_PMC_YOSEMITE)
-+#define ICACHE_REFILLS_WORKAROUND_WAR 1
-+#endif
-+
-+
-+/*
- * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
- * may cause ll / sc and lld / scd sequences to execute non-atomically.
- */
-@@ -187,6 +198,9 @@
- /*
- * Workarounds default to off
- */
-+#ifndef ICACHE_REFILLS_WORKAROUND_WAR
-+#define ICACHE_REFILLS_WORKAROUND_WAR 0
-+#endif
- #ifndef R4600_V1_INDEX_ICACHEOP_WAR
- #define R4600_V1_INDEX_ICACHEOP_WAR 0
- #endif
-diff -urpNX dontdiff linux-2.6.12/drivers/char/Kconfig linux_HEAD/drivers/char/Kconfig
---- linux-2.6.12/drivers/char/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/Kconfig 2005-07-10 12:16:37.000000000 +0200
-@@ -331,23 +331,68 @@ config ISTALLION
- To compile this driver as a module, choose M here: the
- module will be called istallion.
-
--config AU1000_UART
-- bool "Enable Au1000 UART Support"
-- depends on SERIAL_NONSTANDARD && MIPS
-- help
-- If you have an Alchemy AU1000 processor (MIPS based) and you want
-- to use serial ports, say Y. Otherwise, say N.
--
--config AU1000_SERIAL_CONSOLE
-- bool "Enable Au1000 serial console"
-- depends on AU1000_UART
-+config AU1X00_GPIO
-+ tristate "Alchemy Au1000 GPIO device support"
-+ depends on MIPS && SOC_AU1X00
-+
-+config TS_AU1X00_ADS7846
-+ tristate "Au1000/ADS7846 touchscreen support"
-+ depends on MIPS && SOC_AU1X00
-+
-+config AU1X00_USB_TTY
-+ tristate "Au1000 USB TTY Device support"
-+ depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE
-+
-+config AU1X00_USB_RAW
-+ tristate "Au1000 USB Raw Device support"
-+ depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE
-+
-+config SIBYTE_SB1250_DUART
-+ bool "Support for BCM1xxx onchip DUART"
-+ depends on MIPS && SIBYTE_SB1xxx_SOC=y
-+
-+config SIBYTE_SB1250_DUART_CONSOLE
-+ bool "Console on BCM1xxx DUART"
-+ depends on SIBYTE_SB1250_DUART
-+
-+config SERIAL_DEC
-+ bool "DECstation serial support"
-+ depends on MACH_DECSTATION
-+ default y
-+ help
-+ This selects whether you want to be asked about drivers for
-+ DECstation serial ports.
-+
-+ Note that the answer to this question won't directly affect the
-+ kernel: saying N will just cause the configurator to skip all
-+ the questions about DECstation serial ports.
-+
-+ If unsure, say Y.
-+
-+config SERIAL_DEC_CONSOLE
-+ bool "Support for console on a DECstation serial port"
-+ depends on SERIAL_DEC
-+ default y
- help
-- If you have an Alchemy AU1000 processor (MIPS based) and you want
-- to use a console on a serial port, say Y. Otherwise, say N.
-+ If you say Y here, it will be possible to use a serial port as the
-+ system console (the system console is the device which receives all
-+ kernel messages and warnings and which allows logins in single user
-+ mode). Note that the firmware uses ttyS0 as the serial console on
-+ the Maxine and ttyS2 on the others.
-+
-+ If unsure, say Y.
-+
-+config ZS
-+ bool "Z85C30 Serial Support"
-+ depends on SERIAL_DEC
-+ default y
-+ help
-+ Documentation on the Zilog 85C350 serial communications controller
-+ is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
-
- config QTRONIX_KEYBOARD
- bool "Enable Qtronix 990P Keyboard Support"
-- depends on IT8712
-+ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
- help
- Images of Qtronix keyboards are at
- <http://www.qtronix.com/keyboard.html>.
-@@ -359,7 +404,7 @@ config IT8172_CIR
-
- config IT8172_SCR0
- bool "Enable Smart Card Reader 0 Support "
-- depends on IT8712
-+ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
- help
- Say Y here to support smart-card reader 0 (SCR0) on the Integrated
- Technology Express, Inc. ITE8172 SBC. Vendor page at
-@@ -368,13 +413,17 @@ config IT8172_SCR0
-
- config IT8172_SCR1
- bool "Enable Smart Card Reader 1 Support "
-- depends on IT8712
-+ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) && MIPS_ITE8172
- help
- Say Y here to support smart-card reader 1 (SCR1) on the Integrated
- Technology Express, Inc. ITE8172 SBC. Vendor page at
- <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
- board at <http://www.mvista.com/partners/semiconductor/ite.html>.
-
-+config ITE_GPIO
-+ tristate "ITE GPIO"
-+ depends on MIPS && MIPS_ITE8172
-+
- config A2232
- tristate "Commodore A2232 serial support (EXPERIMENTAL)"
- depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
-@@ -779,10 +828,6 @@ config S3C2410_RTC
- Samsung S3C2410. This can provide periodic interrupt rates
- from 1Hz to 64Hz for user programs, and wakeup from Alarm.
-
--config RTC_VR41XX
-- tristate "NEC VR4100 series Real Time Clock Support"
-- depends on CPU_VR41XX
--
- config COBALT_LCD
- bool "Support for Cobalt LCD"
- depends on MIPS_COBALT
-diff -urpNX dontdiff linux-2.6.12/drivers/char/Makefile linux_HEAD/drivers/char/Makefile
---- linux-2.6.12/drivers/char/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/Makefile 2005-07-10 12:16:37.000000000 +0200
-@@ -31,6 +31,7 @@ obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
- obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
- obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
- obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
-+obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
- obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
- obj-$(CONFIG_RISCOM8) += riscom8.o
- obj-$(CONFIG_ISI) += isicom.o
-@@ -48,6 +49,7 @@ obj-$(CONFIG_VIOCONS) += viocons.o
- obj-$(CONFIG_VIOTAPE) += viotape.o
- obj-$(CONFIG_HVCS) += hvcs.o
- obj-$(CONFIG_SGI_MBCS) += mbcs.o
-+obj-$(CONFIG_SERIAL_DEC) += decserial.o
-
- obj-$(CONFIG_PRINTER) += lp.o
- obj-$(CONFIG_TIPAR) += tipar.o
-@@ -64,7 +66,6 @@ obj-$(CONFIG_SGI_DS1286) += ds1286.o
- obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
- obj-$(CONFIG_DS1302) += ds1302.o
- obj-$(CONFIG_S3C2410_RTC) += s3c2410-rtc.o
--obj-$(CONFIG_RTC_VR41XX) += vr41xx_rtc.o
- ifeq ($(CONFIG_GENERIC_NVRAM),y)
- obj-$(CONFIG_NVRAM) += generic_nvram.o
- else
-@@ -76,11 +77,14 @@ obj-$(CONFIG_DS1620) += ds1620.o
- obj-$(CONFIG_HW_RANDOM) += hw_random.o
- obj-$(CONFIG_FTAPE) += ftape/
- obj-$(CONFIG_COBALT_LCD) += lcd.o
-+obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
-+obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o
-+obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o
-+obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o
- obj-$(CONFIG_PPDEV) += ppdev.o
- obj-$(CONFIG_NWBUTTON) += nwbutton.o
- obj-$(CONFIG_NWFLASH) += nwflash.o
- obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
--obj-$(CONFIG_TANBAC_TB0219) += tb0219.o
-
- obj-$(CONFIG_WATCHDOG) += watchdog/
- obj-$(CONFIG_MWAVE) += mwave/
-@@ -92,7 +96,7 @@ obj-$(CONFIG_IPMI_HANDLER) += ipmi/
- obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
- obj-$(CONFIG_TCG_TPM) += tpm/
- # Files generated that shall be removed upon make clean
--clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c
-+clean-files := consolemap_deftbl.c defkeymap.c qtronixmap.c ibm_workpad_keymap.c
-
- quiet_cmd_conmk = CONMK $@
- cmd_conmk = scripts/conmakehash $< > $@
-@@ -104,6 +108,8 @@ $(obj)/defkeymap.o: $(obj)/defkeymap.c
-
- $(obj)/qtronixmap.o: $(obj)/qtronixmap.c
-
-+$(obj)/ibm_workpad_keymap.o: $(obj)/ibm_workpad_keymap.c
-+
- # Uncomment if you're changing the keymap and have an appropriate
- # loadkeys version for the map. By default, we'll use the shipped
- # versions.
-@@ -111,7 +117,8 @@ $(obj)/qtronixmap.o: $(obj)/qtronixmap.c
-
- ifdef GENERATE_KEYMAP
-
--$(obj)/defkeymap.c $(obj)/qtronixmap.c: $(obj)/%.c: $(src)/%.map
-+$(obj)/defkeymap.c $(obj)/qtronixmap.c $(obj)/ibm_workpad_keymap.c: \
-+ $(obj)/%.c: $(src)/%.map
- loadkeys --mktable $< > $@.tmp
- sed -e 's/^static *//' $@.tmp > $@
- rm $@.tmp
-diff -urpNX dontdiff linux-2.6.12/drivers/char/au1000_gpio.c linux_HEAD/drivers/char/au1000_gpio.c
---- linux-2.6.12/drivers/char/au1000_gpio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/au1000_gpio.c 2005-02-28 16:56:48.000000000 +0100
-@@ -0,0 +1,266 @@
-+/*
-+ * FILE NAME au1000_gpio.c
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * Driver for Alchemy Au1000 GPIO.
-+ *
-+ * Author: MontaVista Software, Inc. <source at mvista.com>
-+ * Steve Longerbeam <stevel at mvista.com>
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/config.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/miscdevice.h>
-+#include <linux/init.h>
-+#include <asm/uaccess.h>
-+#include <asm/io.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_gpio.h>
-+
-+#define VERSION "0.01"
-+
-+static const struct {
-+ u32 active_hi;
-+ u32 avail_mask;
-+} pinfunc_to_avail[15] = {
-+ {1, 0x7<<16}, // 0 = SSI0 / GPIO[18:16]
-+ {-1, 0}, // 1 = AC97 / SSI1
-+ {1, 1<<19}, // 2 = IRDA / GPIO19
-+ {1, 1<<20}, // 3 = UART0 / GPIO20
-+ {1, 0x1f<<24}, // 4 = NIC2 / GPIO[28:24]
-+ {1, 0x7<<29}, // 5 = I2S / GPIO[31:29]
-+ {0, 1<<8}, // 6 = I2SDI / GPIO8
-+ {0, 0x3f<<9}, // 7 = UART3 / GPIO[14:9]
-+ {0, 1<<15}, // 8 = IRFIRSEL / GPIO15
-+ {0, 1<<2}, // 9 = EXTCLK0 or OSC / GPIO2
-+ {0, 1<<3}, // 10 = EXTCLK1 / GPIO3
-+ {0, 1<<6}, // 11 = SMROMCKE / GPIO6
-+ {1, 1<<21}, // 12 = UART1 / GPIO21
-+ {1, 1<<22}, // 13 = UART2 / GPIO22
-+ {1, 1<<23} // 14 = UART3 / GPIO23
-+};
-+
-+
-+u32 get_au1000_avail_gpio_mask(void)
-+{
-+ int i;
-+ u32 pinfunc = inl(SYS_PINFUNC);
-+ u32 avail_mask = 0; // start with no gpio available
-+
-+ // first, check for GPIO's reprogrammed as peripheral pins
-+ for (i=0; i<15; i++) {
-+ if (pinfunc_to_avail[i].active_hi < 0)
-+ continue;
-+ if (!(pinfunc_to_avail[i].active_hi ^
-+ ((pinfunc & (1<<i)) ? 1:0)))
-+ avail_mask |= pinfunc_to_avail[i].avail_mask;
-+ }
-+
-+ // check for GPIO's used as interrupt sources
-+ avail_mask &= ~(inl(IC1_MASKRD) &
-+ (inl(IC1_CFG0RD) | inl(IC1_CFG1RD)));
-+
-+#ifdef CONFIG_USB_OHCI
-+ avail_mask &= ~((1<<4) | (1<<11));
-+#ifndef CONFIG_AU1X00_USB_DEVICE
-+ avail_mask &= ~((1<<5) | (1<<13));
-+#endif
-+#endif
-+
-+ return avail_mask;
-+}
-+
-+
-+/*
-+ * Tristate the requested GPIO pins specified in data.
-+ * Only available GPIOs will be tristated.
-+ */
-+int au1000gpio_tristate(u32 data)
-+{
-+ data &= get_au1000_avail_gpio_mask();
-+
-+ if (data)
-+ outl(data, SYS_TRIOUTCLR);
-+
-+ return 0;
-+}
-+
-+
-+/*
-+ * Return the pin state. Pins configured as outputs will return
-+ * the output state, and pins configured as inputs (tri-stated)
-+ * will return input pin state.
-+ */
-+int au1000gpio_in(u32 *data)
-+{
-+ *data = inl(SYS_PINSTATERD);
-+ return 0;
-+}
-+
-+
-+/*
-+ * Set/clear GPIO pins. Only available GPIOs will be affected.
-+ */
-+int au1000gpio_set(u32 data)
-+{
-+ data &= get_au1000_avail_gpio_mask();
-+
-+ if (data)
-+ outl(data, SYS_OUTPUTSET);
-+ return 0;
-+}
-+
-+int au1000gpio_clear(u32 data)
-+{
-+ data &= get_au1000_avail_gpio_mask();
-+
-+ if (data)
-+ outl(data, SYS_OUTPUTCLR);
-+ return 0;
-+}
-+
-+/*
-+ * Output data to GPIO pins. Only available GPIOs will be affected.
-+ */
-+int au1000gpio_out(u32 data)
-+{
-+ au1000gpio_set(data);
-+ au1000gpio_clear(~data);
-+ return 0;
-+}
-+
-+
-+EXPORT_SYMBOL(get_au1000_avail_gpio_mask);
-+EXPORT_SYMBOL(au1000gpio_tristate);
-+EXPORT_SYMBOL(au1000gpio_in);
-+EXPORT_SYMBOL(au1000gpio_set);
-+EXPORT_SYMBOL(au1000gpio_clear);
-+EXPORT_SYMBOL(au1000gpio_out);
-+
-+
-+static int au1000gpio_open(struct inode *inode, struct file *file)
-+{
-+ return 0;
-+}
-+
-+
-+static int au1000gpio_release(struct inode *inode, struct file *file)
-+{
-+ return 0;
-+}
-+
-+
-+static int au1000gpio_ioctl(struct inode *inode, struct file *file,
-+ unsigned int cmd, unsigned long arg)
-+{
-+ int status;
-+ u32 val;
-+
-+ switch(cmd) {
-+ case AU1000GPIO_IN:
-+
-+ status = au1000gpio_in(&val);
-+ if (status != 0)
-+ return status;
-+
-+ return put_user(val, (u32 *)arg);
-+
-+ case AU1000GPIO_OUT:
-+
-+ if (get_user(val, (u32 *)arg))
-+ return -EFAULT;
-+
-+ return au1000gpio_out(val);
-+
-+ case AU1000GPIO_SET:
-+
-+ if (get_user(val, (u32 *)arg))
-+ return -EFAULT;
-+
-+ return au1000gpio_set(val);
-+
-+ case AU1000GPIO_CLEAR:
-+
-+ if (get_user(val, (u32 *)arg))
-+ return -EFAULT;
-+
-+ return au1000gpio_clear(val);
-+
-+ case AU1000GPIO_TRISTATE:
-+
-+ if (get_user(val, (u32 *)arg))
-+ return -EFAULT;
-+
-+ return au1000gpio_tristate(val);
-+
-+ case AU1000GPIO_AVAIL_MASK:
-+
-+ return put_user(get_au1000_avail_gpio_mask(),
-+ (u32 *)arg);
-+
-+ default:
-+ return -ENOIOCTLCMD;
-+
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static struct file_operations au1000gpio_fops =
-+{
-+ .owner = THIS_MODULE,
-+ .ioctl = au1000gpio_ioctl,
-+ .open = au1000gpio_open,
-+ .release = au1000gpio_release,
-+};
-+
-+
-+static struct miscdevice au1000gpio_miscdev =
-+{
-+ MISC_DYNAMIC_MINOR,
-+ "au1000_gpio",
-+ &au1000gpio_fops
-+};
-+
-+
-+int __init au1000gpio_init(void)
-+{
-+ misc_register(&au1000gpio_miscdev);
-+ printk("Au1000 gpio driver, version %s\n", VERSION);
-+ return 0;
-+}
-+
-+
-+void __exit au1000gpio_exit(void)
-+{
-+ misc_deregister(&au1000gpio_miscdev);
-+}
-+
-+
-+module_init(au1000gpio_init);
-+module_exit(au1000gpio_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/au1000_ts.c linux_HEAD/drivers/char/au1000_ts.c
---- linux-2.6.12/drivers/char/au1000_ts.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/au1000_ts.c 2005-02-28 16:56:48.000000000 +0100
-@@ -0,0 +1,677 @@
-+/*
-+ * au1000_ts.c -- Touch screen driver for the Alchemy Au1000's
-+ * SSI Port 0 talking to the ADS7846 touch screen
-+ * controller.
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or source at mvista.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ * Notes:
-+ *
-+ * Revision history
-+ * 06.27.2001 Initial version
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/version.h>
-+
-+#include <linux/init.h>
-+#include <linux/fs.h>
-+#include <linux/delay.h>
-+#include <linux/poll.h>
-+#include <linux/string.h>
-+#include <linux/ioport.h> /* request_region */
-+#include <linux/interrupt.h> /* mark_bh */
-+#include <asm/uaccess.h> /* get_user,copy_to_user */
-+#include <asm/io.h>
-+#include <asm/au1000.h>
-+
-+#define TS_NAME "au1000-ts"
-+#define TS_MAJOR 11
-+
-+#define PFX TS_NAME
-+#define AU1000_TS_DEBUG 1
-+
-+#ifdef AU1000_TS_DEBUG
-+#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
-+#else
-+#define dbg(format, arg...) do {} while (0)
-+#endif
-+#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
-+#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
-+#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
-+
-+
-+// SSI Status register bit defines
-+#define SSISTAT_BF (1<<4)
-+#define SSISTAT_OF (1<<3)
-+#define SSISTAT_UF (1<<2)
-+#define SSISTAT_DONE (1<<1)
-+#define SSISTAT_BUSY (1<<0)
-+
-+// SSI Interrupt Pending and Enable register bit defines
-+#define SSIINT_OI (1<<3)
-+#define SSIINT_UI (1<<2)
-+#define SSIINT_DI (1<<1)
-+
-+// SSI Address/Data register bit defines
-+#define SSIADAT_D (1<<24)
-+#define SSIADAT_ADDR_BIT 16
-+#define SSIADAT_ADDR_MASK (0xff<<SSIADAT_ADDR_BIT)
-+#define SSIADAT_DATA_BIT 0
-+#define SSIADAT_DATA_MASK (0xfff<<SSIADAT_DATA_BIT)
-+
-+// SSI Enable register bit defines
-+#define SSIEN_CD (1<<1)
-+#define SSIEN_E (1<<0)
-+
-+// SSI Config register bit defines
-+#define SSICFG_AO (1<<24)
-+#define SSICFG_DO (1<<23)
-+#define SSICFG_ALEN_BIT 20
-+#define SSICFG_ALEN_MASK (0x7<<SSICFG_ALEN_BIT)
-+#define SSICFG_DLEN_BIT 16
-+#define SSICFG_DLEN_MASK (0xf<<SSICFG_DLEN_BIT)
-+#define SSICFG_DD (1<<11)
-+#define SSICFG_AD (1<<10)
-+#define SSICFG_BM_BIT 8
-+#define SSICFG_BM_MASK (0x3<<SSICFG_BM_BIT)
-+#define SSICFG_CE (1<<7)
-+#define SSICFG_DP (1<<6)
-+#define SSICFG_DL (1<<5)
-+#define SSICFG_EP (1<<4)
-+
-+// Bus Turnaround Selection
-+#define SCLK_HOLD_HIGH 0
-+#define SCLK_HOLD_LOW 1
-+#define SCLK_CYCLE 2
-+
-+/*
-+ * Default config for SSI0:
-+ *
-+ * - transmit MSBit first
-+ * - expect MSBit first on data receive
-+ * - address length 7 bits
-+ * - expect data length 12 bits
-+ * - do not disable Direction bit
-+ * - do not disable Address bits
-+ * - SCLK held low during bus turnaround
-+ * - Address and Data bits clocked out on falling edge of SCLK
-+ * - Direction bit high is a read, low is a write
-+ * - Direction bit precedes Address bits
-+ * - Active low enable signal
-+ */
-+
-+#define DEFAULT_SSI_CONFIG \
-+ (SSICFG_AO | SSICFG_DO | (6<<SSICFG_ALEN_BIT) | (11<<SSICFG_DLEN_BIT) |\
-+ (SCLK_HOLD_LOW<<SSICFG_BM_BIT) | SSICFG_DP | SSICFG_EP)
-+
-+
-+// ADS7846 Control Byte bit defines
-+#define ADS7846_ADDR_BIT 4
-+#define ADS7846_ADDR_MASK (0x7<<ADS7846_ADDR_BIT)
-+#define ADS7846_MEASURE_X (0x5<<ADS7846_ADDR_BIT)
-+#define ADS7846_MEASURE_Y (0x1<<ADS7846_ADDR_BIT)
-+#define ADS7846_MEASURE_Z1 (0x3<<ADS7846_ADDR_BIT)
-+#define ADS7846_MEASURE_Z2 (0x4<<ADS7846_ADDR_BIT)
-+#define ADS7846_8BITS (1<<3)
-+#define ADS7846_12BITS 0
-+#define ADS7846_SER (1<<2)
-+#define ADS7846_DFR 0
-+#define ADS7846_PWR_BIT 0
-+#define ADS7846_PD 0
-+#define ADS7846_ADC_ON (0x1<<ADS7846_PWR_BIT)
-+#define ADS7846_REF_ON (0x2<<ADS7846_PWR_BIT)
-+#define ADS7846_REF_ADC_ON (0x3<<ADS7846_PWR_BIT)
-+
-+#define MEASURE_12BIT_X \
-+ (ADS7846_MEASURE_X | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Y \
-+ (ADS7846_MEASURE_Y | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Z1 \
-+ (ADS7846_MEASURE_Z1 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Z2 \
-+ (ADS7846_MEASURE_Z2 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+
-+typedef enum {
-+ IDLE = 0,
-+ ACQ_X,
-+ ACQ_Y,
-+ ACQ_Z1,
-+ ACQ_Z2
-+} acq_state_t;
-+
-+/* +++++++++++++ Lifted from include/linux/h3600_ts.h ++++++++++++++*/
-+typedef struct {
-+ unsigned short pressure; // touch pressure
-+ unsigned short x; // calibrated X
-+ unsigned short y; // calibrated Y
-+ unsigned short millisecs; // timestamp of this event
-+} TS_EVENT;
-+
-+typedef struct {
-+ int xscale;
-+ int xtrans;
-+ int yscale;
-+ int ytrans;
-+ int xyswap;
-+} TS_CAL;
-+
-+/* Use 'f' as magic number */
-+#define IOC_MAGIC 'f'
-+
-+#define TS_GET_RATE _IO(IOC_MAGIC, 8)
-+#define TS_SET_RATE _IO(IOC_MAGIC, 9)
-+#define TS_GET_CAL _IOR(IOC_MAGIC, 10, TS_CAL)
-+#define TS_SET_CAL _IOW(IOC_MAGIC, 11, TS_CAL)
-+
-+/* +++++++++++++ Done lifted from include/linux/h3600_ts.h +++++++++*/
-+
-+
-+#define EVENT_BUFSIZE 128
-+
-+/*
-+ * Which pressure equation to use from ADS7846 datasheet.
-+ * The first equation requires knowing only the X plate
-+ * resistance, but needs 4 measurements (X, Y, Z1, Z2).
-+ * The second equation requires knowing both X and Y plate
-+ * resistance, but only needs 3 measurements (X, Y, Z1).
-+ * The second equation is preferred because of the shorter
-+ * acquisition time required.
-+ */
-+enum {
-+ PRESSURE_EQN_1 = 0,
-+ PRESSURE_EQN_2
-+};
-+
-+
-+/*
-+ * The touch screen's X and Y plate resistances, used by
-+ * pressure equations.
-+ */
-+#define DEFAULT_X_PLATE_OHMS 580
-+#define DEFAULT_Y_PLATE_OHMS 580
-+
-+/*
-+ * Pen up/down pressure resistance thresholds.
-+ *
-+ * FIXME: these are bogus and will have to be found empirically.
-+ *
-+ * These are hysteresis points. If pen state is up and pressure
-+ * is greater than pen-down threshold, pen transitions to down.
-+ * If pen state is down and pressure is less than pen-up threshold,
-+ * pen transitions to up. If pressure is in-between, pen status
-+ * doesn't change.
-+ *
-+ * This wouldn't be needed if PENIRQ* from the ADS7846 were
-+ * routed to an interrupt line on the Au1000. This would issue
-+ * an interrupt when the panel is touched.
-+ */
-+#define DEFAULT_PENDOWN_THRESH_OHMS 100
-+#define DEFAULT_PENUP_THRESH_OHMS 80
-+
-+typedef struct {
-+ int baudrate;
-+ u32 clkdiv;
-+ acq_state_t acq_state; // State of acquisition state machine
-+ int x_raw, y_raw, z1_raw, z2_raw; // The current raw acquisition values
-+ TS_CAL cal; // Calibration values
-+ // The X and Y plate resistance, needed to calculate pressure
-+ int x_plate_ohms, y_plate_ohms;
-+ // pressure resistance at which pen is considered down/up
-+ int pendown_thresh_ohms;
-+ int penup_thresh_ohms;
-+ int pressure_eqn; // eqn to use for pressure calc
-+ int pendown; // 1 = pen is down, 0 = pen is up
-+ TS_EVENT event_buf[EVENT_BUFSIZE];// The event queue
-+ int nextIn, nextOut;
-+ int event_count;
-+ struct fasync_struct *fasync; // asynch notification
-+ struct timer_list acq_timer; // Timer for triggering acquisitions
-+ wait_queue_head_t wait; // read wait queue
-+ spinlock_t lock;
-+ struct tq_struct chug_tq;
-+} au1000_ts_t;
-+
-+static au1000_ts_t au1000_ts;
-+
-+
-+static inline u32
-+calc_clkdiv(int baud)
-+{
-+ u32 sys_busclk =
-+ (get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
-+ return (sys_busclk / (2 * baud)) - 1;
-+}
-+
-+static inline int
-+calc_baudrate(u32 clkdiv)
-+{
-+ u32 sys_busclk =
-+ (get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
-+ return sys_busclk / (2 * (clkdiv + 1));
-+}
-+
-+
-+/*
-+ * This is a bottom-half handler that is scheduled after
-+ * raw X,Y,Z1,Z2 coordinates have been acquired, and does
-+ * the following:
-+ *
-+ * - computes touch screen pressure resistance
-+ * - if pressure is above a threshold considered to be pen-down:
-+ * - compute calibrated X and Y coordinates
-+ * - queue a new TS_EVENT
-+ * - signal asynchronously and wake up any read
-+ */
-+static void
-+chug_raw_data(void* private)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)private;
-+ TS_EVENT event;
-+ int Rt, Xcal, Ycal;
-+ unsigned long flags;
-+
-+ // timestamp this new event.
-+ event.millisecs = jiffies;
-+
-+ // Calculate touch pressure resistance
-+ if (ts->pressure_eqn == PRESSURE_EQN_2) {
-+ Rt = (ts->x_plate_ohms * ts->x_raw *
-+ (4096 - ts->z1_raw)) / ts->z1_raw;
-+ Rt -= (ts->y_plate_ohms * ts->y_raw);
-+ Rt = (Rt + 2048) >> 12; // round up to nearest ohm
-+ } else {
-+ Rt = (ts->x_plate_ohms * ts->x_raw *
-+ (ts->z2_raw - ts->z1_raw)) / ts->z1_raw;
-+ Rt = (Rt + 2048) >> 12; // round up to nearest ohm
-+ }
-+
-+ // hysteresis
-+ if (!ts->pendown && Rt > ts->pendown_thresh_ohms)
-+ ts->pendown = 1;
-+ else if (ts->pendown && Rt < ts->penup_thresh_ohms)
-+ ts->pendown = 0;
-+
-+ if (ts->pendown) {
-+ // Pen is down
-+ // Calculate calibrated X,Y
-+ Xcal = ((ts->cal.xscale * ts->x_raw) >> 8) + ts->cal.xtrans;
-+ Ycal = ((ts->cal.yscale * ts->y_raw) >> 8) + ts->cal.ytrans;
-+
-+ event.x = (unsigned short)Xcal;
-+ event.y = (unsigned short)Ycal;
-+ event.pressure = (unsigned short)Rt;
-+
-+ // add this event to the event queue
-+ spin_lock_irqsave(&ts->lock, flags);
-+ ts->event_buf[ts->nextIn++] = event;
-+ if (ts->nextIn == EVENT_BUFSIZE)
-+ ts->nextIn = 0;
-+ if (ts->event_count < EVENT_BUFSIZE) {
-+ ts->event_count++;
-+ } else {
-+ // throw out the oldest event
-+ if (++ts->nextOut == EVENT_BUFSIZE)
-+ ts->nextOut = 0;
-+ }
-+ spin_unlock_irqrestore(&ts->lock, flags);
-+
-+ // async notify
-+ if (ts->fasync)
-+ kill_fasync(&ts->fasync, SIGIO, POLL_IN);
-+ // wake up any read call
-+ if (waitqueue_active(&ts->wait))
-+ wake_up_interruptible(&ts->wait);
-+ }
-+}
-+
-+
-+/*
-+ * Raw X,Y,pressure acquisition timer function. This triggers
-+ * the start of a new acquisition. Its duration between calls
-+ * is the touch screen polling rate.
-+ */
-+static void
-+au1000_acq_timer(unsigned long data)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)data;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ts->lock, flags);
-+
-+ // start acquisition with X coordinate
-+ ts->acq_state = ACQ_X;
-+ // start me up
-+ outl(SSIADAT_D | (MEASURE_12BIT_X << SSIADAT_ADDR_BIT), SSI0_ADATA);
-+
-+ // schedule next acquire
-+ ts->acq_timer.expires = jiffies + HZ / 100;
-+ add_timer(&ts->acq_timer);
-+
-+ spin_unlock_irqrestore(&ts->lock, flags);
-+}
-+
-+static void
-+ssi0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+ au1000_ts_t *ts = (au1000_ts_t*)dev_id;
-+ u32 stat, int_stat, data;
-+
-+ spin_lock(&ts->lock);
-+
-+ stat = inl(SSI0_STATUS);
-+ // clear sticky status bits
-+ outl(stat & (SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE), SSI0_STATUS);
-+
-+ int_stat = inl(SSI0_INT);
-+ // clear sticky intr status bits
-+ outl(int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI), SSI0_INT);
-+
-+ if ((int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI)) != SSIINT_DI) {
-+ if (int_stat & SSIINT_OI)
-+ err("overflow");
-+ if (int_stat & SSIINT_UI)
-+ err("underflow");
-+ spin_unlock(&ts->lock);
-+ return;
-+ }
-+
-+ data = inl(SSI0_ADATA) & SSIADAT_DATA_MASK;
-+
-+ switch (ts->acq_state) {
-+ case IDLE:
-+ break;
-+ case ACQ_X:
-+ ts->x_raw = data;
-+ ts->acq_state = ACQ_Y;
-+ // trigger Y acq
-+ outl(SSIADAT_D | (MEASURE_12BIT_Y << SSIADAT_ADDR_BIT),
-+ SSI0_ADATA);
-+ break;
-+ case ACQ_Y:
-+ ts->y_raw = data;
-+ ts->acq_state = ACQ_Z1;
-+ // trigger Z1 acq
-+ outl(SSIADAT_D | (MEASURE_12BIT_Z1 << SSIADAT_ADDR_BIT),
-+ SSI0_ADATA);
-+ break;
-+ case ACQ_Z1:
-+ ts->z1_raw = data;
-+ if (ts->pressure_eqn == PRESSURE_EQN_2) {
-+ // don't acq Z2, using 2nd eqn for touch pressure
-+ ts->acq_state = IDLE;
-+ // got the raw stuff, now mark BH
-+ queue_task(&ts->chug_tq, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+ } else {
-+ ts->acq_state = ACQ_Z2;
-+ // trigger Z2 acq
-+ outl(SSIADAT_D | (MEASURE_12BIT_Z2<<SSIADAT_ADDR_BIT),
-+ SSI0_ADATA);
-+ }
-+ break;
-+ case ACQ_Z2:
-+ ts->z2_raw = data;
-+ ts->acq_state = IDLE;
-+ // got the raw stuff, now mark BH
-+ queue_task(&ts->chug_tq, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+ break;
-+ }
-+
-+ spin_unlock(&ts->lock);
-+}
-+
-+
-+/* +++++++++++++ File operations ++++++++++++++*/
-+
-+static int
-+au1000_fasync(int fd, struct file *filp, int mode)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+ return fasync_helper(fd, filp, mode, &ts->fasync);
-+}
-+
-+static int
-+au1000_ioctl(struct inode * inode, struct file *filp,
-+ unsigned int cmd, unsigned long arg)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+
-+ switch(cmd) {
-+ case TS_GET_RATE: /* TODO: what is this? */
-+ break;
-+ case TS_SET_RATE: /* TODO: what is this? */
-+ break;
-+ case TS_GET_CAL:
-+ copy_to_user((char *)arg, (char *)&ts->cal, sizeof(TS_CAL));
-+ break;
-+ case TS_SET_CAL:
-+ copy_from_user((char *)&ts->cal, (char *)arg, sizeof(TS_CAL));
-+ break;
-+ default:
-+ err("unknown cmd %04x", cmd);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static unsigned int
-+au1000_poll(struct file * filp, poll_table * wait)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+ poll_wait(filp, &ts->wait, wait);
-+ if (ts->event_count)
-+ return POLLIN | POLLRDNORM;
-+ return 0;
-+}
-+
-+static ssize_t
-+au1000_read(struct file * filp, char * buf, size_t count, loff_t * l)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+ unsigned long flags;
-+ TS_EVENT event;
-+ int i;
-+
-+ if (ts->event_count == 0) {
-+ if (filp->f_flags & O_NONBLOCK)
-+ return -EAGAIN;
-+ interruptible_sleep_on(&ts->wait);
-+ if (signal_pending(current))
-+ return -ERESTARTSYS;
-+ }
-+
-+ for (i = count;
-+ i >= sizeof(TS_EVENT);
-+ i -= sizeof(TS_EVENT), buf += sizeof(TS_EVENT)) {
-+ if (ts->event_count == 0)
-+ break;
-+ spin_lock_irqsave(&ts->lock, flags);
-+ event = ts->event_buf[ts->nextOut++];
-+ if (ts->nextOut == EVENT_BUFSIZE)
-+ ts->nextOut = 0;
-+ if (ts->event_count)
-+ ts->event_count--;
-+ spin_unlock_irqrestore(&ts->lock, flags);
-+ copy_to_user(buf, &event, sizeof(TS_EVENT));
-+ }
-+
-+ return count - i;
-+}
-+
-+
-+static int
-+au1000_open(struct inode * inode, struct file * filp)
-+{
-+ au1000_ts_t* ts;
-+ unsigned long flags;
-+
-+ filp->private_data = ts = &au1000_ts;
-+
-+ spin_lock_irqsave(&ts->lock, flags);
-+
-+ // setup SSI0 config
-+ outl(DEFAULT_SSI_CONFIG, SSI0_CONFIG);
-+
-+ // clear out SSI0 status bits
-+ outl(SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE, SSI0_STATUS);
-+ // clear out SSI0 interrupt pending bits
-+ outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT);
-+
-+ // enable SSI0 interrupts
-+ outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT_ENABLE);
-+
-+ /*
-+ * init bh handler that chugs the raw data (calibrates and
-+ * calculates touch pressure).
-+ */
-+ ts->chug_tq.routine = chug_raw_data;
-+ ts->chug_tq.data = ts;
-+ ts->pendown = 0; // pen up
-+
-+ // flush event queue
-+ ts->nextIn = ts->nextOut = ts->event_count = 0;
-+
-+ // Start acquisition timer function
-+ init_timer(&ts->acq_timer);
-+ ts->acq_timer.function = au1000_acq_timer;
-+ ts->acq_timer.data = (unsigned long)ts;
-+ ts->acq_timer.expires = jiffies + HZ / 100;
-+ add_timer(&ts->acq_timer);
-+
-+ spin_unlock_irqrestore(&ts->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+au1000_release(struct inode * inode, struct file * filp)
-+{
-+ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+ unsigned long flags;
-+
-+ au1000_fasync(-1, filp, 0);
-+ del_timer_sync(&ts->acq_timer);
-+
-+ spin_lock_irqsave(&ts->lock, flags);
-+ // disable SSI0 interrupts
-+ outl(0, SSI0_INT_ENABLE);
-+ spin_unlock_irqrestore(&ts->lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+static struct file_operations ts_fops = {
-+ .read = au1000_read,
-+ .poll = au1000_poll,
-+ .ioctl = au1000_ioctl,
-+ .fasync = au1000_fasync,
-+ .open = au1000_open,
-+ .release = au1000_release,
-+};
-+
-+/* +++++++++++++ End File operations ++++++++++++++*/
-+
-+
-+int __init
-+au1000ts_init_module(void)
-+{
-+ au1000_ts_t* ts = &au1000_ts;
-+ int ret;
-+
-+ /* register our character device */
-+ if ((ret = register_chrdev(TS_MAJOR, TS_NAME, &ts_fops)) < 0) {
-+ err("can't get major number");
-+ return ret;
-+ }
-+ info("registered");
-+
-+ memset(ts, 0, sizeof(au1000_ts_t));
-+ init_waitqueue_head(&ts->wait);
-+ spin_lock_init(&ts->lock);
-+
-+ if (!request_region(virt_to_phys((void*)SSI0_STATUS), 0x100, TS_NAME)) {
-+ err("SSI0 ports in use");
-+ return -ENXIO;
-+ }
-+
-+ if ((ret = request_irq(AU1000_SSI0_INT, ssi0_interrupt,
-+ SA_SHIRQ | SA_INTERRUPT, TS_NAME, ts))) {
-+ err("could not get IRQ");
-+ return ret;
-+ }
-+
-+ // initial calibration values
-+ ts->cal.xscale = -93;
-+ ts->cal.xtrans = 346;
-+ ts->cal.yscale = -64;
-+ ts->cal.ytrans = 251;
-+
-+ // init pen up/down hysteresis points
-+ ts->pendown_thresh_ohms = DEFAULT_PENDOWN_THRESH_OHMS;
-+ ts->penup_thresh_ohms = DEFAULT_PENUP_THRESH_OHMS;
-+ ts->pressure_eqn = PRESSURE_EQN_2;
-+ // init X and Y plate resistances
-+ ts->x_plate_ohms = DEFAULT_X_PLATE_OHMS;
-+ ts->y_plate_ohms = DEFAULT_Y_PLATE_OHMS;
-+
-+ // set GPIO to SSI0 function
-+ outl(inl(PIN_FUNCTION) & ~1, PIN_FUNCTION);
-+
-+ // enable SSI0 clock and bring SSI0 out of reset
-+ outl(0, SSI0_CONTROL);
-+ udelay(1000);
-+ outl(SSIEN_E, SSI0_CONTROL);
-+ udelay(100);
-+
-+ // FIXME: is this a working baudrate?
-+ ts->clkdiv = 0;
-+ ts->baudrate = calc_baudrate(ts->clkdiv);
-+ outl(ts->clkdiv, SSI0_CLKDIV);
-+
-+ info("baudrate = %d Hz", ts->baudrate);
-+
-+ return 0;
-+}
-+
-+void
-+au1000ts_cleanup_module(void)
-+{
-+ // disable clocks and hold in reset
-+ outl(SSIEN_CD, SSI0_CONTROL);
-+ free_irq(AU1000_SSI0_INT, &au1000_ts);
-+ release_region(virt_to_phys((void*)SSI0_STATUS), 0x100);
-+ unregister_chrdev(TS_MAJOR, TS_NAME);
-+}
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1000/ADS7846 Touch Screen Driver");
-+
-+module_init(au1000ts_init_module);
-+module_exit(au1000ts_cleanup_module);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/au1000_usbraw.c linux_HEAD/drivers/char/au1000_usbraw.c
---- linux-2.6.12/drivers/char/au1000_usbraw.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/au1000_usbraw.c 2005-02-28 16:56:48.000000000 +0100
-@@ -0,0 +1,573 @@
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ * Au1x00 USB Device-Side Raw Block Driver (function layer)
-+ *
-+ * Copyright 2001-2002 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or source at mvista.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/signal.h>
-+#include <linux/errno.h>
-+#include <linux/poll.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/fcntl.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/list.h>
-+#include <linux/smp_lock.h>
-+#undef DEBUG
-+#include <linux/usb.h>
-+
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/irq.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_usbdev.h>
-+
-+#define USBRAW_MAJOR 190 // FIXME: need a legal major
-+#define USBRAW_NAME "usbraw"
-+
-+#define MAX_NUM_PORTS 2
-+
-+#define IN_MAX_PACKET_SIZE 64
-+#define OUT_MAX_PACKET_SIZE 64
-+
-+// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
-+#define NUM_PORTS 1
-+#define NUM_EP 2*NUM_PORTS
-+
-+#define CONFIG_DESC_LEN \
-+ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
-+
-+/* must be power of two */
-+#define READ_BUF_SIZE (1<<12)
-+
-+struct usb_raw_port {
-+ unsigned char number;
-+ spinlock_t port_lock;
-+
-+ struct usb_endpoint_descriptor* out_desc;
-+ struct usb_endpoint_descriptor* in_desc;
-+
-+ int out_ep_addr; /* endpoint address of OUT endpoint */
-+ int in_ep_addr; /* endpoint address of IN endpoint */
-+
-+ __u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages
-+ int read_nextin, read_nextout;
-+ int read_count;
-+
-+ wait_queue_head_t wait;
-+ struct fasync_struct *fasync; // asynch notification
-+
-+ int active; /* someone has this device open */
-+ int open_count; /* number of times this port has been opened */
-+};
-+
-+static struct usb_serial {
-+ struct usb_device_descriptor* dev_desc;
-+ struct usb_config_descriptor* config_desc;
-+ struct usb_interface_descriptor* if_desc;
-+ struct usb_string_descriptor * str_desc[6];
-+ void* str_desc_buf;
-+
-+ usbdev_state_t dev_state;
-+
-+ struct usb_raw_port port[NUM_PORTS];
-+} usbraw;
-+
-+static struct usb_device_descriptor dev_desc = {
-+ bLength:USB_DT_DEVICE_SIZE,
-+ bDescriptorType:USB_DT_DEVICE,
-+ bcdUSB:USBDEV_REV, //usb rev
-+ bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
-+ bDeviceSubClass:0x00, //subclass (none)
-+ bDeviceProtocol:0x00, //protocol (none)
-+ bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
-+ idVendor:0x6d04, //vendor id
-+ idProduct:0x0bc0, //product id
-+ bcdDevice:0x0001, //BCD rev 0.1
-+ iManufacturer:0x01, //manufactuer string index
-+ iProduct:0x02, //product string index
-+ iSerialNumber:0x03, //serial# string index
-+ bNumConfigurations:0x01 //num configurations
-+};
-+
-+static struct usb_endpoint_descriptor ep_desc[] = {
-+ {
-+ // Bulk IN for Port 0
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_IN,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk OUT for Port 0
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_OUT,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk IN for Port 1
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_IN,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk OUT for Port 1
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_OUT,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ }
-+};
-+
-+static struct usb_interface_descriptor if_desc = {
-+ bLength:USB_DT_INTERFACE_SIZE,
-+ bDescriptorType:USB_DT_INTERFACE,
-+ bInterfaceNumber:0x00,
-+ bAlternateSetting:0x00,
-+ bNumEndpoints:NUM_EP,
-+ bInterfaceClass:0xff,
-+ bInterfaceSubClass:0xab,
-+ bInterfaceProtocol:0x00,
-+ iInterface:0x05
-+};
-+
-+static struct usb_config_descriptor config_desc = {
-+ bLength:USB_DT_CONFIG_SIZE,
-+ bDescriptorType:USB_DT_CONFIG,
-+ wTotalLength:CONFIG_DESC_LEN,
-+ bNumInterfaces:0x01,
-+ bConfigurationValue:0x01,
-+ iConfiguration:0x04, // configuration string
-+ bmAttributes:0xc0, // self-powered
-+ MaxPower:20 // 40 mA
-+};
-+
-+// String[0] is a list of Language IDs supported by this device
-+static struct usb_string_descriptor string_desc0 = {
-+ bLength:4,
-+ bDescriptorType:USB_DT_STRING,
-+ wData:{0x0409} // English, US
-+};
-+
-+// These strings will be converted to Unicode in string_desc[]
-+static char *strings[5] = {
-+ "Alchemy Semiconductor", // iManufacturer
-+ "USB Raw Block Device", // iProduct
-+ "0.1", // iSerialNumber
-+ "USB Raw Config", // iConfiguration
-+ "USB Raw Interface" // iInterface
-+};
-+
-+
-+static void
-+receive_callback(struct usb_raw_port *port)
-+{
-+ int i, pkt_size;
-+ usbdev_pkt_t* pkt;
-+
-+ if ((pkt_size = usbdev_receive_packet(port->out_ep_addr,
-+ &pkt)) <= 0) {
-+ dbg(__FUNCTION__ ": usbdev_receive_packet returns %d",
-+ pkt_size);
-+ return;
-+ }
-+
-+ dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size);
-+
-+ spin_lock(&port->port_lock);
-+ for (i=0; i < pkt_size; i++) {
-+ port->read_buf[port->read_nextin++] = pkt->payload[i];
-+ port->read_nextin &= (READ_BUF_SIZE - 1);
-+ if (++port->read_count == READ_BUF_SIZE)
-+ break;
-+ }
-+ spin_unlock(&port->port_lock);
-+
-+ /* free the packet */
-+ kfree(pkt);
-+
-+ // async notify
-+ if (port->fasync)
-+ kill_fasync(&port->fasync, SIGIO, POLL_IN);
-+ // wake up any read call
-+ if (waitqueue_active(&port->wait))
-+ wake_up_interruptible(&port->wait);
-+}
-+
-+static void
-+transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt)
-+{
-+ dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
-+ /* just free the returned packet */
-+ kfree(pkt);
-+}
-+
-+
-+static void
-+usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
-+{
-+ usbdev_pkt_t* pkt;
-+ int i;
-+
-+ switch (cb_type) {
-+ case CB_NEW_STATE:
-+ usbraw.dev_state = (usbdev_state_t)arg;
-+ break;
-+ case CB_PKT_COMPLETE:
-+ pkt = (usbdev_pkt_t*)arg;
-+ for (i=0; i<NUM_PORTS; i++) {
-+ struct usb_raw_port *port = &usbraw.port[i];
-+ if (pkt->ep_addr == port->in_ep_addr) {
-+ transmit_callback(port, pkt);
-+ break;
-+ } else if (pkt->ep_addr == port->out_ep_addr) {
-+ receive_callback(port);
-+ break;
-+ }
-+ }
-+ break;
-+ }
-+}
-+
-+/*****************************************************************************
-+ * Here begins the driver interface functions
-+ *****************************************************************************/
-+
-+static unsigned int usbraw_poll(struct file * filp, poll_table * wait)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+ unsigned long flags;
-+ int count;
-+
-+ poll_wait(filp, &port->wait, wait);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+ count = port->read_count;
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+ if (count > 0) {
-+ dbg(__FUNCTION__ ": count=%d", count);
-+ return POLLIN | POLLRDNORM;
-+ }
-+
-+ return 0;
-+}
-+
-+static int usbraw_fasync(int fd, struct file *filp, int mode)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+ return fasync_helper(fd, filp, mode, &port->fasync);
-+}
-+
-+static int usbraw_open(struct inode * inode, struct file *filp)
-+{
-+ int portNumber;
-+ struct usb_raw_port *port;
-+ unsigned long flags;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbraw.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ /* set up our port structure making the tty driver remember
-+ our port object, and us it */
-+ portNumber = MINOR(inode->i_rdev);
-+ port = &usbraw.port[portNumber];
-+ filp->private_data = port;
-+
-+ dbg(__FUNCTION__ ": port %d", port->number);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+
-+ ++port->open_count;
-+
-+ if (!port->active) {
-+ port->active = 1;
-+ }
-+
-+ /* flush read buffer */
-+ port->read_nextin = port->read_nextout = port->read_count = 0;
-+
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+ return 0;
-+}
-+
-+static int usbraw_release(struct inode * inode, struct file * filp)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+ unsigned long flags;
-+
-+ dbg(__FUNCTION__ ": port %d", port->number);
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not opened");
-+ return -ENODEV;
-+ }
-+
-+ usbraw_fasync(-1, filp, 0);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+
-+ --port->open_count;
-+
-+ if (port->open_count <= 0) {
-+ port->active = 0;
-+ port->open_count = 0;
-+ }
-+
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+static ssize_t usbraw_read(struct file * filp, char * buf,
-+ size_t count, loff_t * l)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+ unsigned long flags;
-+ int i, cnt;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbraw.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ do {
-+ spin_lock_irqsave(&port->port_lock, flags);
-+ cnt = port->read_count;
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+ if (cnt == 0) {
-+ if (filp->f_flags & O_NONBLOCK)
-+ return -EAGAIN;
-+ interruptible_sleep_on(&port->wait);
-+ if (signal_pending(current))
-+ return -ERESTARTSYS;
-+ }
-+ } while (cnt == 0);
-+
-+ count = (count > cnt) ? cnt : count;
-+
-+ for (i=0; i<count; i++) {
-+ put_user(port->read_buf[port->read_nextout++], &buf[i]);
-+ port->read_nextout &= (READ_BUF_SIZE - 1);
-+ spin_lock_irqsave(&port->port_lock, flags);
-+ port->read_count--;
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+ if (port->read_count == 0)
-+ break;
-+ }
-+
-+ return i+1;
-+}
-+
-+static ssize_t usbraw_write(struct file * filp, const char * buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+ usbdev_pkt_t* pkt;
-+ int ret, max_pkt_sz;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbraw.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not opened");
-+ return -EINVAL;
-+ }
-+
-+ if (count == 0) {
-+ dbg(__FUNCTION__ ": write request of 0 bytes");
-+ return (0);
-+ }
-+
-+ max_pkt_sz = port->in_desc->wMaxPacketSize;
-+ count = (count > max_pkt_sz) ? max_pkt_sz : count;
-+
-+ if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0)
-+ return ret;
-+
-+ copy_from_user(pkt->payload, buf, count);
-+
-+ return usbdev_send_packet(port->in_ep_addr, pkt);
-+}
-+
-+static int usbraw_ioctl(struct inode *inode, struct file *filp,
-+ unsigned int cmd, unsigned long arg)
-+{
-+ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not open");
-+ return -ENODEV;
-+ }
-+ // FIXME: need any IOCTLs?
-+
-+ return -ENOIOCTLCMD;
-+}
-+
-+
-+static struct file_operations usbraw_fops = {
-+ .owner = THIS_MODULE,
-+ .write = usbraw_write,
-+ .read = usbraw_read,
-+ .poll = usbraw_poll,
-+ .ioctl = usbraw_ioctl,
-+ .fasync = usbraw_fasync,
-+ .open = usbraw_open,
-+ .release = usbraw_release,
-+};
-+
-+void usbfn_raw_exit(void)
-+{
-+ /* kill the device layer */
-+ usbdev_exit();
-+
-+ unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME);
-+
-+ if (usbraw.str_desc_buf)
-+ kfree(usbraw.str_desc_buf);
-+}
-+
-+
-+int usbfn_raw_init(void)
-+{
-+ int ret = 0, i, str_desc_len;
-+
-+ /* register our character device */
-+ if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME,
-+ &usbraw_fops)) < 0) {
-+ err("can't get major number");
-+ return ret;
-+ }
-+ info("registered");
-+
-+ /*
-+ * initialize pointers to descriptors
-+ */
-+ usbraw.dev_desc = &dev_desc;
-+ usbraw.config_desc = &config_desc;
-+ usbraw.if_desc = &if_desc;
-+
-+ /*
-+ * initialize the string descriptors
-+ */
-+
-+ /* alloc buffer big enough for all string descriptors */
-+ str_desc_len = string_desc0.bLength;
-+ for (i = 0; i < 5; i++)
-+ str_desc_len += 2 + 2 * strlen(strings[i]);
-+ usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
-+ if (!usbraw.str_desc_buf) {
-+ err(__FUNCTION__ ": failed to alloc string descriptors");
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ usbraw.str_desc[0] =
-+ (struct usb_string_descriptor *)usbraw.str_desc_buf;
-+ memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength);
-+ usbraw.str_desc[1] = (struct usb_string_descriptor *)
-+ (usbraw.str_desc_buf + string_desc0.bLength);
-+ for (i = 1; i < 6; i++) {
-+ struct usb_string_descriptor *desc = usbraw.str_desc[i];
-+ char *str = strings[i - 1];
-+ int j, str_len = strlen(str);
-+
-+ desc->bLength = 2 + 2 * str_len;
-+ desc->bDescriptorType = USB_DT_STRING;
-+ for (j = 0; j < str_len; j++) {
-+ desc->wData[j] = (u16) str[j];
-+ }
-+ if (i < 5)
-+ usbraw.str_desc[i + 1] =
-+ (struct usb_string_descriptor *)
-+ ((u8 *) desc + desc->bLength);
-+ }
-+
-+ /*
-+ * start the device layer. The device layer assigns us
-+ * our endpoint addresses
-+ */
-+ if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
-+ usbraw.str_desc, usbraw_callback, NULL))) {
-+ err(__FUNCTION__ ": device-layer init failed");
-+ goto out;
-+ }
-+
-+ /* initialize the devfs nodes for this device and let the user
-+ know what ports we are bound to */
-+ for (i = 0; i < NUM_PORTS; ++i) {
-+ struct usb_raw_port *port = &usbraw.port[i];
-+
-+ port->number = i;
-+ port->in_desc = &ep_desc[NUM_PORTS*i];
-+ port->out_desc = &ep_desc[NUM_PORTS*i + 1];
-+ port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
-+ port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
-+ init_waitqueue_head(&port->wait);
-+ spin_lock_init(&port->port_lock);
-+ }
-+
-+ out:
-+ if (ret)
-+ usbfn_raw_exit();
-+ return ret;
-+}
-+
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(usbfn_raw_init);
-+module_exit(usbfn_raw_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/au1000_usbtty.c linux_HEAD/drivers/char/au1000_usbtty.c
---- linux-2.6.12/drivers/char/au1000_usbtty.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/au1000_usbtty.c 2005-02-28 16:56:48.000000000 +0100
-@@ -0,0 +1,761 @@
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ * Au1x00 USB Device-Side Serial TTY Driver (function layer)
-+ *
-+ * Copyright 2001-2002 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or source at mvista.com
-+ *
-+ * Derived from drivers/usb/serial/usbserial.c:
-+ *
-+ * Copyright (C) 1999 - 2001 Greg Kroah-Hartman (greg at kroah.com)
-+ * Copyright (c) 2000 Peter Berger (pberger at brimson.com)
-+ * Copyright (c) 2000 Al Borchers (borchers at steinerpoint.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/signal.h>
-+#include <linux/errno.h>
-+#include <linux/poll.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/fcntl.h>
-+#include <linux/tty.h>
-+#include <linux/tty_driver.h>
-+#include <linux/tty_flip.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/list.h>
-+#include <linux/smp_lock.h>
-+#undef DEBUG
-+#include <linux/usb.h>
-+
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/irq.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_usbdev.h>
-+
-+
-+/* local function prototypes */
-+static int serial_open(struct tty_struct *tty, struct file *filp);
-+static void serial_close(struct tty_struct *tty, struct file *filp);
-+static int serial_write(struct tty_struct *tty, int from_user,
-+ const unsigned char *buf, int count);
-+static int serial_write_room(struct tty_struct *tty);
-+static int serial_chars_in_buffer(struct tty_struct *tty);
-+static void serial_throttle(struct tty_struct *tty);
-+static void serial_unthrottle(struct tty_struct *tty);
-+static int serial_ioctl(struct tty_struct *tty, struct file *file,
-+ unsigned int cmd, unsigned long arg);
-+static void serial_set_termios (struct tty_struct *tty, struct termios * old);
-+
-+#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major
-+
-+#define MAX_NUM_PORTS 2
-+
-+#define IN_MAX_PACKET_SIZE 32
-+#define OUT_MAX_PACKET_SIZE 32
-+
-+// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
-+#define NUM_PORTS 2
-+#define NUM_EP 2*NUM_PORTS
-+
-+#define CONFIG_DESC_LEN \
-+ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
-+
-+struct usb_serial_port {
-+ struct tty_struct *tty; /* the coresponding tty for this port */
-+ unsigned char number;
-+ spinlock_t port_lock;
-+
-+ struct usb_endpoint_descriptor* out_desc;
-+ struct usb_endpoint_descriptor* in_desc;
-+
-+ int out_ep_addr; /* endpoint address of OUT endpoint */
-+ int in_ep_addr; /* endpoint address of IN endpoint */
-+
-+ /* task queue for line discipline waking up on send packet complete */
-+ struct tq_struct send_complete_tq;
-+ /* task queue for line discipline wakeup on receive packet complete */
-+ struct tq_struct receive_complete_tq;
-+
-+ int active; /* someone has this device open */
-+ int writing; /* a packet write is in progress */
-+ int open_count; /* number of times this port has been opened */
-+
-+};
-+
-+static struct usb_serial {
-+ usbdev_state_t dev_state; // current state of device layer
-+ struct usb_device_descriptor* dev_desc;
-+ struct usb_config_descriptor* config_desc;
-+ struct usb_interface_descriptor* if_desc;
-+ struct usb_string_descriptor * str_desc[6];
-+ void* str_desc_buf;
-+
-+ struct usb_serial_port port[NUM_PORTS];
-+} usbtty;
-+
-+static int serial_refcount;
-+static struct tty_driver serial_tty_driver;
-+static struct tty_struct * serial_tty[NUM_PORTS];
-+static struct termios * serial_termios[NUM_PORTS];
-+static struct termios * serial_termios_locked[NUM_PORTS];
-+
-+static struct usb_device_descriptor dev_desc = {
-+ bLength:USB_DT_DEVICE_SIZE,
-+ bDescriptorType:USB_DT_DEVICE,
-+ bcdUSB:USBDEV_REV, //usb rev
-+ bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
-+ bDeviceSubClass:0x00, //subclass (none)
-+ bDeviceProtocol:0x00, //protocol (none)
-+ bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
-+ idVendor:0x6d04, //vendor id
-+ idProduct:0x0bc0, //product id
-+ bcdDevice:0x0001, //BCD rev 0.1
-+ iManufacturer:0x01, //manufactuer string index
-+ iProduct:0x02, //product string index
-+ iSerialNumber:0x03, //serial# string index
-+ bNumConfigurations:0x01 //num configurations
-+};
-+
-+static struct usb_endpoint_descriptor ep_desc[] = {
-+ {
-+ // Bulk IN for Port 0
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_IN,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk OUT for Port 0
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_OUT,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk IN for Port 1
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_IN,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ },
-+ {
-+ // Bulk OUT for Port 1
-+ bLength:USB_DT_ENDPOINT_SIZE,
-+ bDescriptorType:USB_DT_ENDPOINT,
-+ bEndpointAddress:USB_DIR_OUT,
-+ bmAttributes:USB_ENDPOINT_XFER_BULK,
-+ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+ bInterval:0x00 // ignored for bulk
-+ }
-+};
-+
-+static struct usb_interface_descriptor if_desc = {
-+ bLength:USB_DT_INTERFACE_SIZE,
-+ bDescriptorType:USB_DT_INTERFACE,
-+ bInterfaceNumber:0x00,
-+ bAlternateSetting:0x00,
-+ bNumEndpoints:NUM_EP,
-+ bInterfaceClass:0xff,
-+ bInterfaceSubClass:0xab,
-+ bInterfaceProtocol:0x00,
-+ iInterface:0x05
-+};
-+
-+static struct usb_config_descriptor config_desc = {
-+ bLength:USB_DT_CONFIG_SIZE,
-+ bDescriptorType:USB_DT_CONFIG,
-+ wTotalLength:CONFIG_DESC_LEN,
-+ bNumInterfaces:0x01,
-+ bConfigurationValue:0x01,
-+ iConfiguration:0x04, // configuration string
-+ bmAttributes:0xc0, // self-powered
-+ MaxPower:20 // 40 mA
-+};
-+
-+// String[0] is a list of Language IDs supported by this device
-+static struct usb_string_descriptor string_desc0 = {
-+ bLength:4,
-+ bDescriptorType:USB_DT_STRING,
-+ wData:{0x0409} // English, US
-+};
-+
-+// These strings will be converted to Unicode in string_desc[]
-+static char *strings[5] = {
-+ "Alchemy Semiconductor", // iManufacturer
-+ "WutzAMattaU", // iProduct
-+ "1.0.doh!", // iSerialNumber
-+ "Au1000 TTY Config", // iConfiguration
-+ "Au1000 TTY Interface" // iInterface
-+};
-+
-+static inline int
-+port_paranoia_check(struct usb_serial_port *port, const char *function)
-+{
-+ if (!port) {
-+ err("%s: port is NULL", function);
-+ return -1;
-+ }
-+ if (!port->tty) {
-+ err("%s: port->tty is NULL", function);
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static void
-+port_rx_callback(struct usb_serial_port *port)
-+{
-+ dbg(__FUNCTION__ ": ep%d", port->out_ep_addr);
-+ // mark a bh to push this data up to the tty
-+ queue_task(&port->receive_complete_tq, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+}
-+
-+static void
-+port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt)
-+{
-+ dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
-+ // mark a bh to wakeup any tty write system call on the port.
-+ queue_task(&port->send_complete_tq, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+
-+ /* free the returned packet */
-+ kfree(pkt);
-+}
-+
-+static void
-+usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
-+{
-+ usbdev_pkt_t* pkt;
-+ int i;
-+
-+ switch (cb_type) {
-+ case CB_NEW_STATE:
-+ dbg(__FUNCTION__ ": new dev_state=%d", (int)arg);
-+ usbtty.dev_state = (usbdev_state_t)arg;
-+ break;
-+ case CB_PKT_COMPLETE:
-+ pkt = (usbdev_pkt_t*)arg;
-+ for (i=0; i<NUM_PORTS; i++) {
-+ struct usb_serial_port *port = &usbtty.port[i];
-+ if (pkt->ep_addr == port->in_ep_addr) {
-+ port_tx_callback(port, pkt);
-+ break;
-+ } else if (pkt->ep_addr == port->out_ep_addr) {
-+ port_rx_callback(port);
-+ break;
-+ }
-+ }
-+ break;
-+ }
-+}
-+
-+
-+/*****************************************************************************
-+ * Here begins the tty driver interface functions
-+ *****************************************************************************/
-+
-+static int serial_open(struct tty_struct *tty, struct file *filp)
-+{
-+ int portNumber;
-+ struct usb_serial_port *port;
-+ unsigned long flags;
-+
-+ /* initialize the pointer incase something fails */
-+ tty->driver_data = NULL;
-+
-+ /* set up our port structure making the tty driver remember
-+ our port object, and us it */
-+ portNumber = MINOR(tty->device);
-+ port = &usbtty.port[portNumber];
-+ tty->driver_data = port;
-+ port->tty = tty;
-+
-+ if (usbtty.dev_state != CONFIGURED ||
-+ port_paranoia_check(port, __FUNCTION__)) {
-+ /*
-+ * the device-layer must be in the configured state before
-+ * the function layer can operate.
-+ */
-+ return -ENODEV;
-+ }
-+
-+ dbg(__FUNCTION__ ": port %d", port->number);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+
-+ ++port->open_count;
-+
-+ if (!port->active) {
-+ port->active = 1;
-+
-+ /*
-+ * force low_latency on so that our tty_push actually forces
-+ * the data through, otherwise it is scheduled, and with high
-+ * data rates (like with OHCI) data can get lost.
-+ */
-+ port->tty->low_latency = 1;
-+
-+ }
-+
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+static void serial_close(struct tty_struct *tty, struct file *filp)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+ unsigned long flags;
-+
-+ dbg(__FUNCTION__ ": port %d", port->number);
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not opened");
-+ return;
-+ }
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+
-+ --port->open_count;
-+
-+ if (port->open_count <= 0) {
-+ port->active = 0;
-+ port->open_count = 0;
-+ }
-+
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+ MOD_DEC_USE_COUNT;
-+}
-+
-+
-+static int serial_write(struct tty_struct *tty, int from_user,
-+ const unsigned char *buf, int count)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+ usbdev_pkt_t* pkt;
-+ int max_pkt_sz, ret;
-+ unsigned long flags;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbtty.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not open");
-+ return -EINVAL;
-+ }
-+
-+ if (count == 0) {
-+ dbg(__FUNCTION__ ": request of 0 bytes");
-+ return (0);
-+ }
-+
-+#if 0
-+ if (port->writing) {
-+ dbg(__FUNCTION__ ": already writing");
-+ return 0;
-+ }
-+#endif
-+
-+ max_pkt_sz = port->in_desc->wMaxPacketSize;
-+ count = (count > max_pkt_sz) ? max_pkt_sz : count;
-+
-+ if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)))
-+ return ret;
-+
-+ if (from_user)
-+ copy_from_user(pkt->payload, buf, count);
-+ else
-+ memcpy(pkt->payload, buf, count);
-+
-+ ret = usbdev_send_packet(port->in_ep_addr, pkt);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+ port->writing = 1;
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+ return ret;
-+}
-+
-+
-+static int serial_write_room(struct tty_struct *tty)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+ int room = 0;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbtty.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not open");
-+ return -EINVAL;
-+ }
-+
-+ //room = port->writing ? 0 : port->in_desc->wMaxPacketSize;
-+ room = port->in_desc->wMaxPacketSize;
-+
-+ dbg(__FUNCTION__ ": %d", room);
-+ return room;
-+}
-+
-+
-+static int serial_chars_in_buffer(struct tty_struct *tty)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+ int chars = 0;
-+
-+ /*
-+ * the device-layer must be in the configured state before the
-+ * function layer can operate.
-+ */
-+ if (usbtty.dev_state != CONFIGURED)
-+ return -ENODEV;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not open");
-+ return -EINVAL;
-+ }
-+
-+ //chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0;
-+ chars = usbdev_get_byte_count(port->in_ep_addr);
-+
-+ dbg(__FUNCTION__ ": %d", chars);
-+ return chars;
-+}
-+
-+
-+static void serial_throttle(struct tty_struct *tty)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+
-+ if (!port->active || usbtty.dev_state != CONFIGURED) {
-+ err(__FUNCTION__ ": port not open");
-+ return;
-+ }
-+
-+ // FIXME: anything to do?
-+ dbg(__FUNCTION__);
-+}
-+
-+
-+static void serial_unthrottle(struct tty_struct *tty)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+
-+ if (!port->active || usbtty.dev_state != CONFIGURED) {
-+ err(__FUNCTION__ ": port not open");
-+ return;
-+ }
-+
-+ // FIXME: anything to do?
-+ dbg(__FUNCTION__);
-+}
-+
-+
-+static int serial_ioctl(struct tty_struct *tty, struct file *file,
-+ unsigned int cmd, unsigned long arg)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+
-+ if (!port->active) {
-+ err(__FUNCTION__ ": port not open");
-+ return -ENODEV;
-+ }
-+ // FIXME: need any IOCTLs?
-+ dbg(__FUNCTION__);
-+
-+ return -ENOIOCTLCMD;
-+}
-+
-+
-+static void serial_set_termios(struct tty_struct *tty, struct termios *old)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+
-+ if (!port->active || usbtty.dev_state != CONFIGURED) {
-+ err(__FUNCTION__ ": port not open");
-+ return;
-+ }
-+
-+ dbg(__FUNCTION__);
-+ // FIXME: anything to do?
-+}
-+
-+
-+static void serial_break(struct tty_struct *tty, int break_state)
-+{
-+ struct usb_serial_port *port =
-+ (struct usb_serial_port *) tty->driver_data;
-+
-+ if (!port->active || usbtty.dev_state != CONFIGURED) {
-+ err(__FUNCTION__ ": port not open");
-+ return;
-+ }
-+
-+ dbg(__FUNCTION__);
-+ // FIXME: anything to do?
-+}
-+
-+
-+static void port_send_complete(void *private)
-+{
-+ struct usb_serial_port *port = (struct usb_serial_port *) private;
-+ struct tty_struct *tty;
-+ unsigned long flags;
-+
-+ dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr);
-+
-+ tty = port->tty;
-+ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+ tty->ldisc.write_wakeup) {
-+ dbg(__FUNCTION__ ": write wakeup call.");
-+ (tty->ldisc.write_wakeup) (tty);
-+ }
-+
-+ wake_up_interruptible(&tty->write_wait);
-+
-+ spin_lock_irqsave(&port->port_lock, flags);
-+ port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1;
-+ spin_unlock_irqrestore(&port->port_lock, flags);
-+}
-+
-+
-+static void port_receive_complete(void *private)
-+{
-+ struct usb_serial_port *port = (struct usb_serial_port *) private;
-+ struct tty_struct *tty = port->tty;
-+ usbdev_pkt_t* pkt = NULL;
-+ int i, count;
-+
-+ /* while there is a packet available */
-+ while ((count = usbdev_receive_packet(port->out_ep_addr,
-+ &pkt)) != -ENODATA) {
-+ if (count < 0) {
-+ if (pkt)
-+ kfree(pkt);
-+ break; /* exit if error other than ENODATA */
-+ }
-+
-+ dbg(__FUNCTION__ ": port %d, ep%d, size=%d",
-+ port->number, port->out_ep_addr, count);
-+
-+ for (i = 0; i < count; i++) {
-+ /* if we insert more than TTY_FLIPBUF_SIZE characters,
-+ we drop them. */
-+ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
-+ tty_flip_buffer_push(tty);
-+ }
-+ /* this doesn't actually push the data through
-+ unless tty->low_latency is set */
-+ tty_insert_flip_char(tty, pkt->payload[i], 0);
-+ }
-+ tty_flip_buffer_push(tty);
-+
-+ kfree(pkt); /* make sure we free the packet */
-+ }
-+
-+}
-+
-+
-+static struct tty_driver serial_tty_driver = {
-+ .magic= TTY_DRIVER_MAGIC,
-+ .driver_name= "usbfn-tty",
-+ .name= "usb/ttsdev/%d",
-+ .major= SERIAL_TTY_MAJOR,
-+ .minor_start= 0,
-+ .num= NUM_PORTS,
-+ .type= TTY_DRIVER_TYPE_SERIAL,
-+ .subtype= SERIAL_TYPE_NORMAL,
-+ .flags= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
-+ .refcount= &serial_refcount,
-+ .table= serial_tty,
-+ .termios= serial_termios,
-+ .termios_locked= serial_termios_locked,
-+
-+ .open= serial_open,
-+ .close= serial_close,
-+ .write= serial_write,
-+ .write_room= serial_write_room,
-+ .ioctl= serial_ioctl,
-+ .set_termios= serial_set_termios,
-+ .throttle= serial_throttle,
-+ .unthrottle= serial_unthrottle,
-+ .break_ctl= serial_break,
-+ .chars_in_buffer= serial_chars_in_buffer,
-+};
-+
-+
-+void usbfn_tty_exit(void)
-+{
-+ int i;
-+
-+ /* kill the device layer */
-+ usbdev_exit();
-+
-+ for (i=0; i < NUM_PORTS; i++) {
-+ tty_unregister_devfs(&serial_tty_driver, i);
-+ info("usb serial converter now disconnected from ttyUSBdev%d",
-+ i);
-+ }
-+
-+ tty_unregister_driver(&serial_tty_driver);
-+
-+ if (usbtty.str_desc_buf)
-+ kfree(usbtty.str_desc_buf);
-+}
-+
-+
-+int usbfn_tty_init(void)
-+{
-+ int ret = 0, i, str_desc_len;
-+
-+ /* register the tty driver */
-+ serial_tty_driver.init_termios = tty_std_termios;
-+ serial_tty_driver.init_termios.c_cflag =
-+ B9600 | CS8 | CREAD | HUPCL | CLOCAL;
-+
-+ if (tty_register_driver(&serial_tty_driver)) {
-+ err(__FUNCTION__ ": failed to register tty driver");
-+ ret = -ENXIO;
-+ goto out;
-+ }
-+
-+ /*
-+ * initialize pointers to descriptors
-+ */
-+ usbtty.dev_desc = &dev_desc;
-+ usbtty.config_desc = &config_desc;
-+ usbtty.if_desc = &if_desc;
-+
-+ /*
-+ * initialize the string descriptors
-+ */
-+
-+ /* alloc buffer big enough for all string descriptors */
-+ str_desc_len = string_desc0.bLength;
-+ for (i = 0; i < 5; i++)
-+ str_desc_len += 2 + 2 * strlen(strings[i]);
-+ usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
-+ if (!usbtty.str_desc_buf) {
-+ err(__FUNCTION__ ": failed to alloc string descriptors");
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ usbtty.str_desc[0] =
-+ (struct usb_string_descriptor *)usbtty.str_desc_buf;
-+ memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength);
-+ usbtty.str_desc[1] = (struct usb_string_descriptor *)
-+ (usbtty.str_desc_buf + string_desc0.bLength);
-+ for (i = 1; i < 6; i++) {
-+ struct usb_string_descriptor *desc = usbtty.str_desc[i];
-+ char *str = strings[i - 1];
-+ int j, str_len = strlen(str);
-+
-+ desc->bLength = 2 + 2 * str_len;
-+ desc->bDescriptorType = USB_DT_STRING;
-+ for (j = 0; j < str_len; j++) {
-+ desc->wData[j] = (u16) str[j];
-+ }
-+ if (i < 5)
-+ usbtty.str_desc[i + 1] =
-+ (struct usb_string_descriptor *)
-+ ((u8 *) desc + desc->bLength);
-+ }
-+
-+ /*
-+ * start the device layer. The device layer assigns us
-+ * our endpoint addresses
-+ */
-+ if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
-+ usbtty.str_desc, usbtty_callback, NULL))) {
-+ err(__FUNCTION__ ": device-layer init failed");
-+ goto out;
-+ }
-+
-+ /* initialize the devfs nodes for this device and let the user
-+ know what ports we are bound to */
-+ for (i = 0; i < NUM_PORTS; ++i) {
-+ struct usb_serial_port *port;
-+ tty_register_devfs(&serial_tty_driver, 0, i);
-+ info("usbdev serial attached to ttyUSBdev%d "
-+ "(or devfs usb/ttsdev/%d)", i, i);
-+ port = &usbtty.port[i];
-+ port->number = i;
-+ port->in_desc = &ep_desc[NUM_PORTS*i];
-+ port->out_desc = &ep_desc[NUM_PORTS*i + 1];
-+ port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
-+ port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
-+ port->send_complete_tq.routine = port_send_complete;
-+ port->send_complete_tq.data = port;
-+ port->receive_complete_tq.routine = port_receive_complete;
-+ port->receive_complete_tq.data = port;
-+ spin_lock_init(&port->port_lock);
-+ }
-+
-+ out:
-+ if (ret)
-+ usbfn_tty_exit();
-+ return ret;
-+}
-+
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(usbfn_tty_init);
-+module_exit(usbfn_tty_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/decserial.c linux_HEAD/drivers/char/decserial.c
---- linux-2.6.12/drivers/char/decserial.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/decserial.c 2004-09-21 13:10:14.000000000 +0200
-@@ -14,87 +14,85 @@
- * device. Added support for PROM console in drivers/char/tty_io.c
- * instead. Although it may work to enable more than one
- * console device I strongly recommend to use only one.
-+ *
-+ * Copyright (C) 2004 Maciej W. Rozycki
- */
-
- #include <linux/config.h>
-+#include <linux/errno.h>
- #include <linux/init.h>
--#include <asm/dec/machtype.h>
--
--#ifdef CONFIG_ZS
--extern int zs_init(void);
--#endif
-
--#ifdef CONFIG_DZ
--extern int dz_init(void);
--#endif
-+#include <asm/dec/machtype.h>
-+#include <asm/dec/serial.h>
-
--#ifdef CONFIG_SERIAL_CONSOLE
-+extern int register_zs_hook(unsigned int channel,
-+ struct dec_serial_hook *hook);
-+extern int unregister_zs_hook(unsigned int channel);
-
-+int register_dec_serial_hook(unsigned int channel,
-+ struct dec_serial_hook *hook)
-+{
- #ifdef CONFIG_ZS
--extern void zs_serial_console_init(void);
--#endif
--
--#ifdef CONFIG_DZ
--extern void dz_serial_console_init(void);
-+ if (IOASIC)
-+ return register_zs_hook(channel, hook);
- #endif
-+ return 0;
-+}
-
-+int unregister_dec_serial_hook(unsigned int channel)
-+{
-+#ifdef CONFIG_ZS
-+ if (IOASIC)
-+ return unregister_zs_hook(channel);
- #endif
-+ return 0;
-+}
-
--/* rs_init - starts up the serial interface -
-- handle normal case of starting up the serial interface */
-
--#ifdef CONFIG_SERIAL
-+extern int zs_init(void);
-+extern int dz_init(void);
-
-+/*
-+ * rs_init - starts up the serial interface -
-+ * handle normal case of starting up the serial interface
-+ */
- int __init rs_init(void)
- {
--
--#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
-- if (IOASIC)
-- return zs_init();
-- else
-- return dz_init();
--#else
--
- #ifdef CONFIG_ZS
-- return zs_init();
-+ if (IOASIC)
-+ return zs_init();
- #endif
--
- #ifdef CONFIG_DZ
-- return dz_init();
--#endif
--
-+ if (!IOASIC)
-+ return dz_init();
- #endif
-+ return -ENXIO;
- }
-
- __initcall(rs_init);
-
--#endif
-
--#ifdef CONFIG_SERIAL_CONSOLE
-+#ifdef CONFIG_SERIAL_DEC_CONSOLE
-+
-+extern void zs_serial_console_init(void);
-+extern void dz_serial_console_init(void);
-
--/* serial_console_init handles the special case of starting
-- * up the console on the serial port
-+/*
-+ * dec_serial_console_init handles the special case of starting
-+ * up the console on the serial port
- */
--static int __init decserial_console_init(void)
-+static int __init dec_serial_console_init(void)
- {
--#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
-- if (IOASIC)
-- zs_serial_console_init();
-- else
-- dz_serial_console_init();
--#else
--
- #ifdef CONFIG_ZS
-- zs_serial_console_init();
-+ if (IOASIC)
-+ zs_serial_console_init();
- #endif
--
- #ifdef CONFIG_DZ
-- dz_serial_console_init();
--#endif
--
-+ if (!IOASIC)
-+ dz_serial_console_init();
- #endif
- return 0;
- }
--console_initcall(decserial_console_init);
-+console_initcall(dec_serial_console_init);
-
- #endif
-diff -urpNX dontdiff linux-2.6.12/drivers/char/generic_serial.c linux_HEAD/drivers/char/generic_serial.c
---- linux-2.6.12/drivers/char/generic_serial.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/generic_serial.c 2005-04-08 22:40:55.000000000 +0200
-@@ -21,6 +21,7 @@
-
- #include <linux/module.h>
- #include <linux/kernel.h>
-+#include <linux/interrupt.h>
- #include <linux/tty.h>
- #include <linux/serial.h>
- #include <linux/mm.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/char/ibm_workpad_keymap.map linux_HEAD/drivers/char/ibm_workpad_keymap.map
---- linux-2.6.12/drivers/char/ibm_workpad_keymap.map 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/ibm_workpad_keymap.map 2003-12-20 15:18:07.000000000 +0100
-@@ -0,0 +1,343 @@
-+# Keymap for IBM Workpad z50
-+# US Mapping
-+#
-+# by Michael Klar <wyldfier at iname.com>
-+#
-+# This is a great big mess on account of how the Caps Lock key is handled as
-+# LeftShift-RightShift. Right shift key had to be broken out, so don't use
-+# use this map file as a basis for other keyboards that don't do the same
-+# thing with Caps Lock.
-+#
-+# This file is subject to the terms and conditions of the GNU General Public
-+# License. See the file "COPYING" in the main directory of this archive
-+# for more details.
-+
-+keymaps 0-2,4-5,8,12,32-33,36-37
-+strings as usual
-+
-+keycode 0 = F1 F11 Console_13
-+ shiftr keycode 0 = F11
-+ shift shiftr keycode 0 = F11
-+ control keycode 0 = F1
-+ alt keycode 0 = Console_1
-+ control alt keycode 0 = Console_1
-+keycode 1 = F3 F13 Console_15
-+ shiftr keycode 1 = F13
-+ shift shiftr keycode 1 = F13
-+ control keycode 1 = F3
-+ alt keycode 1 = Console_3
-+ control alt keycode 1 = Console_3
-+keycode 2 = F5 F15 Console_17
-+ shiftr keycode 2 = F15
-+ shift shiftr keycode 2 = F15
-+ control keycode 2 = F5
-+ alt keycode 2 = Console_5
-+ control alt keycode 2 = Console_5
-+keycode 3 = F7 F17 Console_19
-+ shiftr keycode 3 = F17
-+ shift shiftr keycode 3 = F17
-+ control keycode 3 = F7
-+ alt keycode 3 = Console_7
-+ control alt keycode 3 = Console_7
-+keycode 4 = F9 F19 Console_21
-+ shiftr keycode 4 = F19
-+ shift shiftr keycode 4 = F19
-+ control keycode 4 = F9
-+ alt keycode 4 = Console_9
-+ control alt keycode 4 = Console_9
-+#keycode 5 is contrast down
-+#keycode 6 is contrast up
-+keycode 7 = F11 F11 Console_23
-+ shiftr keycode 7 = F11
-+ shift shiftr keycode 7 = F11
-+ control keycode 7 = F11
-+ alt keycode 7 = Console_11
-+ control alt keycode 7 = Console_11
-+keycode 8 = F2 F12 Console_14
-+ shiftr keycode 8 = F12
-+ shift shiftr keycode 8 = F12
-+ control keycode 8 = F2
-+ alt keycode 8 = Console_2
-+ control alt keycode 8 = Console_2
-+keycode 9 = F4 F14 Console_16
-+ shiftr keycode 9 = F14
-+ shift shiftr keycode 9 = F14
-+ control keycode 9 = F4
-+ alt keycode 9 = Console_4
-+ control alt keycode 9 = Console_4
-+keycode 10 = F6 F16 Console_18
-+ shiftr keycode 10 = F16
-+ shift shiftr keycode 10 = F16
-+ control keycode 10 = F6
-+ alt keycode 10 = Console_6
-+ control alt keycode 10 = Console_6
-+keycode 11 = F8 F18 Console_20
-+ shiftr keycode 11 = F18
-+ shift shiftr keycode 11 = F18
-+ control keycode 11 = F8
-+ alt keycode 11 = Console_8
-+ control alt keycode 11 = Console_8
-+keycode 12 = F10 F20 Console_22
-+ shiftr keycode 12 = F20
-+ shift shiftr keycode 12 = F20
-+ control keycode 12 = F10
-+ alt keycode 12 = Console_10
-+ control alt keycode 12 = Console_10
-+#keycode 13 is brightness down
-+#keycode 14 is brightness up
-+keycode 15 = F12 F12 Console_24
-+ shiftr keycode 15 = F12
-+ shift shiftr keycode 15 = F12
-+ control keycode 15 = F12
-+ alt keycode 15 = Console_12
-+ control alt keycode 15 = Console_12
-+keycode 16 = apostrophe quotedbl
-+ shiftr keycode 16 = quotedbl
-+ shift shiftr keycode 16 = quotedbl
-+ control keycode 16 = Control_g
-+ alt keycode 16 = Meta_apostrophe
-+keycode 17 = bracketleft braceleft
-+ shiftr keycode 17 = braceleft
-+ shift shiftr keycode 17 = braceleft
-+ control keycode 17 = Escape
-+ alt keycode 17 = Meta_bracketleft
-+keycode 18 = minus underscore backslash
-+ shiftr keycode 18 = underscore
-+ shift shiftr keycode 18 = underscore
-+ control keycode 18 = Control_underscore
-+ shift control keycode 18 = Control_underscore
-+ shiftr control keycode 18 = Control_underscore
-+ shift shiftr control keycode 18 = Control_underscore
-+ alt keycode 18 = Meta_minus
-+keycode 19 = zero parenright braceright
-+ shiftr keycode 19 = parenright
-+ shift shiftr keycode 19 = parenright
-+ alt keycode 19 = Meta_zero
-+keycode 20 = p
-+ shiftr keycode 20 = +P
-+ shift shiftr keycode 20 = +p
-+keycode 21 = semicolon colon
-+ shiftr keycode 21 = colon
-+ shift shiftr keycode 21 = colon
-+ alt keycode 21 = Meta_semicolon
-+keycode 22 = Up Scroll_Backward
-+ shiftr keycode 22 = Scroll_Backward
-+ shift shiftr keycode 22 = Scroll_Backward
-+ alt keycode 22 = Prior
-+keycode 23 = slash question
-+ shiftr keycode 23 = question
-+ shift shiftr keycode 23 = question
-+ control keycode 23 = Delete
-+ alt keycode 23 = Meta_slash
-+
-+keycode 27 = nine parenleft bracketright
-+ shiftr keycode 27 = parenleft
-+ shift shiftr keycode 27 = parenleft
-+ alt keycode 27 = Meta_nine
-+keycode 28 = o
-+ shiftr keycode 28 = +O
-+ shift shiftr keycode 28 = +o
-+keycode 29 = l
-+ shiftr keycode 29 = +L
-+ shift shiftr keycode 29 = +l
-+keycode 30 = period greater
-+ shiftr keycode 30 = greater
-+ shift shiftr keycode 30 = greater
-+ control keycode 30 = Compose
-+ alt keycode 30 = Meta_period
-+
-+keycode 32 = Left Decr_Console
-+ shiftr keycode 32 = Decr_Console
-+ shift shiftr keycode 32 = Decr_Console
-+ alt keycode 32 = Home
-+keycode 33 = bracketright braceright asciitilde
-+ shiftr keycode 33 = braceright
-+ shift shiftr keycode 33 = braceright
-+ control keycode 33 = Control_bracketright
-+ alt keycode 33 = Meta_bracketright
-+keycode 34 = equal plus
-+ shiftr keycode 34 = plus
-+ shift shiftr keycode 34 = plus
-+ alt keycode 34 = Meta_equal
-+keycode 35 = eight asterisk bracketleft
-+ shiftr keycode 35 = asterisk
-+ shift shiftr keycode 35 = asterisk
-+ control keycode 35 = Delete
-+ alt keycode 35 = Meta_eight
-+keycode 36 = i
-+ shiftr keycode 36 = +I
-+ shift shiftr keycode 36 = +i
-+keycode 37 = k
-+ shiftr keycode 37 = +K
-+ shift shiftr keycode 37 = +k
-+keycode 38 = comma less
-+ shiftr keycode 38 = less
-+ shift shiftr keycode 38 = less
-+ alt keycode 38 = Meta_comma
-+
-+keycode 40 = h
-+ shiftr keycode 40 = +H
-+ shift shiftr keycode 40 = +h
-+keycode 41 = y
-+ shiftr keycode 41 = +Y
-+ shift shiftr keycode 41 = +y
-+keycode 42 = six asciicircum
-+ shiftr keycode 42 = asciicircum
-+ shift shiftr keycode 42 = asciicircum
-+ control keycode 42 = Control_asciicircum
-+ alt keycode 42 = Meta_six
-+keycode 43 = seven ampersand braceleft
-+ shiftr keycode 43 = ampersand
-+ shift shiftr keycode 43 = ampersand
-+ control keycode 43 = Control_underscore
-+ alt keycode 43 = Meta_seven
-+keycode 44 = u
-+ shiftr keycode 44 = +U
-+ shift shiftr keycode 44 = +u
-+keycode 45 = j
-+ shiftr keycode 45 = +J
-+ shift shiftr keycode 45 = +j
-+keycode 46 = m
-+ shiftr keycode 46 = +M
-+ shift shiftr keycode 46 = +m
-+keycode 47 = n
-+ shiftr keycode 47 = +N
-+ shift shiftr keycode 47 = +n
-+
-+# This is the "Backspace" key:
-+keycode 49 = Delete Delete
-+ shiftr keycode 49 = Delete
-+ shift shiftr keycode 49 = Delete
-+ control keycode 49 = BackSpace
-+ alt keycode 49 = Meta_Delete
-+keycode 50 = Num_Lock
-+ shift keycode 50 = Bare_Num_Lock
-+ shiftr keycode 50 = Bare_Num_Lock
-+ shift shiftr keycode 50 = Bare_Num_Lock
-+# This is the "Delete" key:
-+keycode 51 = Remove
-+ control alt keycode 51 = Boot
-+
-+keycode 53 = backslash bar
-+ shiftr keycode 53 = bar
-+ shift shiftr keycode 53 = bar
-+ control keycode 53 = Control_backslash
-+ alt keycode 53 = Meta_backslash
-+keycode 54 = Return
-+ alt keycode 54 = Meta_Control_m
-+keycode 55 = space space
-+ shiftr keycode 55 = space
-+ shift shiftr keycode 55 = space
-+ control keycode 55 = nul
-+ alt keycode 55 = Meta_space
-+keycode 56 = g
-+ shiftr keycode 56 = +G
-+ shift shiftr keycode 56 = +g
-+keycode 57 = t
-+ shiftr keycode 57 = +T
-+ shift shiftr keycode 57 = +t
-+keycode 58 = five percent
-+ shiftr keycode 58 = percent
-+ shift shiftr keycode 58 = percent
-+ control keycode 58 = Control_bracketright
-+ alt keycode 58 = Meta_five
-+keycode 59 = four dollar dollar
-+ shiftr keycode 59 = dollar
-+ shift shiftr keycode 59 = dollar
-+ control keycode 59 = Control_backslash
-+ alt keycode 59 = Meta_four
-+keycode 60 = r
-+ shiftr keycode 60 = +R
-+ shift shiftr keycode 60 = +r
-+keycode 61 = f
-+ shiftr keycode 61 = +F
-+ shift shiftr keycode 61 = +f
-+ altgr keycode 61 = Hex_F
-+keycode 62 = v
-+ shiftr keycode 62 = +V
-+ shift shiftr keycode 62 = +v
-+keycode 63 = b
-+ shiftr keycode 63 = +B
-+ shift shiftr keycode 63 = +b
-+ altgr keycode 63 = Hex_B
-+
-+keycode 67 = three numbersign
-+ shiftr keycode 67 = numbersign
-+ shift shiftr keycode 67 = numbersign
-+ control keycode 67 = Escape
-+ alt keycode 67 = Meta_three
-+keycode 68 = e
-+ shiftr keycode 68 = +E
-+ shift shiftr keycode 68 = +e
-+ altgr keycode 68 = Hex_E
-+keycode 69 = d
-+ shiftr keycode 69 = +D
-+ shift shiftr keycode 69 = +d
-+ altgr keycode 69 = Hex_D
-+keycode 70 = c
-+ shiftr keycode 70 = +C
-+ shift shiftr keycode 70 = +c
-+ altgr keycode 70 = Hex_C
-+keycode 71 = Right Incr_Console
-+ shiftr keycode 71 = Incr_Console
-+ shift shiftr keycode 71 = Incr_Console
-+ alt keycode 71 = End
-+
-+keycode 75 = two at at
-+ shiftr keycode 75 = at
-+ shift shiftr keycode 75 = at
-+ control keycode 75 = nul
-+ shift control keycode 75 = nul
-+ shiftr control keycode 75 = nul
-+ shift shiftr control keycode 75 = nul
-+ alt keycode 75 = Meta_two
-+keycode 76 = w
-+ shiftr keycode 76 = +W
-+ shift shiftr keycode 76 = +w
-+keycode 77 = s
-+ shiftr keycode 77 = +S
-+ shift shiftr keycode 77 = +s
-+keycode 78 = x
-+ shiftr keycode 78 = +X
-+ shift shiftr keycode 78 = +x
-+keycode 79 = Down Scroll_Forward
-+ shiftr keycode 79 = Scroll_Forward
-+ shift shiftr keycode 79 = Scroll_Forward
-+ alt keycode 79 = Next
-+keycode 80 = Escape Escape
-+ shiftr keycode 80 = Escape
-+ shift shiftr keycode 80 = Escape
-+ alt keycode 80 = Meta_Escape
-+keycode 81 = Tab Tab
-+ shiftr keycode 81 = Tab
-+ shift shiftr keycode 81 = Tab
-+ alt keycode 81 = Meta_Tab
-+keycode 82 = grave asciitilde
-+ shiftr keycode 82 = asciitilde
-+ shift shiftr keycode 82 = asciitilde
-+ control keycode 82 = nul
-+ alt keycode 82 = Meta_grave
-+keycode 83 = one exclam
-+ shiftr keycode 83 = exclam
-+ shift shiftr keycode 83 = exclam
-+ alt keycode 83 = Meta_one
-+keycode 84 = q
-+ shiftr keycode 84 = +Q
-+ shift shiftr keycode 84 = +q
-+keycode 85 = a
-+ shiftr keycode 85 = +A
-+ shift shiftr keycode 85 = +a
-+ altgr keycode 85 = Hex_A
-+keycode 86 = z
-+ shiftr keycode 86 = +Z
-+ shift shiftr keycode 86 = +z
-+
-+# This is the windows key:
-+keycode 88 = Decr_Console
-+keycode 89 = Shift
-+keycode 90 = Control
-+keycode 91 = Control
-+keycode 92 = Alt
-+keycode 93 = AltGr
-+keycode 94 = ShiftR
-+ shift keycode 94 = Caps_Lock
-diff -urpNX dontdiff linux-2.6.12/drivers/char/lcd.c linux_HEAD/drivers/char/lcd.c
---- linux-2.6.12/drivers/char/lcd.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/lcd.c 2005-02-21 22:17:44.000000000 +0100
-@@ -575,8 +575,8 @@ static inline int button_pressed(void)
-
- static int lcd_waiters = 0;
-
--static long lcd_read(struct inode *inode, struct file *file, char *buf,
-- unsigned long count)
-+static ssize_t lcd_read(struct file *file, char *buf,
-+ size_t count, loff_t *ofs)
- {
- long buttons_now;
-
-diff -urpNX dontdiff linux-2.6.12/drivers/char/lcd.h linux_HEAD/drivers/char/lcd.h
---- linux-2.6.12/drivers/char/lcd.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/lcd.h 2005-02-21 22:17:44.000000000 +0100
-@@ -22,7 +22,7 @@ static int timeout(volatile unsigned lon
- #define MAX_IDLE_TIME 120
-
- struct lcd_display {
-- unsigned long buttons;
-+ unsigned buttons;
- int size1;
- int size2;
- unsigned char line1[LCD_CHARS_PER_LINE];
-diff -urpNX dontdiff linux-2.6.12/drivers/char/qtronix.c linux_HEAD/drivers/char/qtronix.c
---- linux-2.6.12/drivers/char/qtronix.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/qtronix.c 2005-03-11 18:48:13.000000000 +0100
-@@ -535,8 +535,7 @@ repeat:
- i--;
- }
- if (count-i) {
-- struct inode *inode = file->f_dentry->d_inode;
-- inode->i_atime = current_fs_time(inode->i_sb);
-+ file->f_dentry->d_inode->i_atime = get_seconds();
- return count-i;
- }
- if (signal_pending(current))
-@@ -591,6 +590,11 @@ static int __init psaux_init(void)
- return retval;
-
- queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL);
-+ if (!queue) {
-+ misc_deregister(&psaux_mouse);
-+ return -ENOMEM;
-+ }
-+
- memset(queue, 0, sizeof(*queue));
- queue->head = queue->tail = 0;
- init_waitqueue_head(&queue->proc_list);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/rtc.c linux_HEAD/drivers/char/rtc.c
---- linux-2.6.12/drivers/char/rtc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/rtc.c 2005-03-21 20:04:04.000000000 +0100
-@@ -35,23 +35,21 @@
- * 1.09a Pete Zaitcev: Sun SPARC
- * 1.09b Jeff Garzik: Modularize, init cleanup
- * 1.09c Jeff Garzik: SMP cleanup
-- * 1.10 Paul Barton-Davis: add support for async I/O
-+ * 1.10 Paul Barton-Davis: add support for async I/O
- * 1.10a Andrea Arcangeli: Alpha updates
- * 1.10b Andrew Morton: SMP lock fix
- * 1.10c Cesar Barros: SMP locking fixes and cleanup
- * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
- * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness.
-- * 1.11 Takashi Iwai: Kernel access functions
-+ * 1.11 Takashi Iwai: Kernel access functions
- * rtc_register/rtc_unregister/rtc_control
- * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
-- * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
-+ * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
- * CONFIG_HPET_EMULATE_RTC
-- *
-+ * 1.12a Maciej W. Rozycki: Handle memory-mapped chips properly.
- */
-
--#define RTC_VERSION "1.12"
--
--#define RTC_IO_EXTENT 0x8
-+#define RTC_VERSION "1.12a"
-
- /*
- * Note that *all* calls to CMOS_READ and CMOS_WRITE are done with
-@@ -323,7 +321,15 @@ static ssize_t rtc_read(struct file *fil
- if (rtc_has_irq == 0)
- return -EIO;
-
-- if (count < sizeof(unsigned))
-+ /*
-+ * Historically this function used to assume that sizeof(unsigned long)
-+ * is the same in userspace and kernelspace. This lead to problems
-+ * for configurations with multiple ABIs such a the MIPS o32 and 64
-+ * ABIs supported on the same kernel. So now we support read of both
-+ * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the
-+ * userspace ABI.
-+ */
-+ if (count != sizeof(unsigned int) && count != sizeof(unsigned long))
- return -EINVAL;
-
- add_wait_queue(&rtc_wait, &wait);
-@@ -354,10 +360,12 @@ static ssize_t rtc_read(struct file *fil
- schedule();
- } while (1);
-
-- if (count < sizeof(unsigned long))
-- retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int);
-+ if (count == sizeof(unsigned int))
-+ retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int);
- else
- retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long);
-+ if (!retval)
-+ retval = count;
- out:
- current->state = TASK_RUNNING;
- remove_wait_queue(&rtc_wait, &wait);
-@@ -905,6 +913,9 @@ static int __init rtc_init(void)
- struct sparc_isa_device *isa_dev;
- #endif
- #endif
-+#ifndef __sparc__
-+ void *r;
-+#endif
-
- #ifdef __sparc__
- for_each_ebus(ebus) {
-@@ -951,8 +962,13 @@ found:
- }
- no_irq:
- #else
-- if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) {
-- printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0));
-+ if (RTC_IOMAPPED)
-+ r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
-+ else
-+ r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
-+ if (!r) {
-+ printk(KERN_ERR "rtc: I/O resource %lx is not free.\n",
-+ (long)(RTC_PORT(0)));
- return -EIO;
- }
-
-@@ -966,7 +982,10 @@ no_irq:
- if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) {
- /* Yeah right, seeing as irq 8 doesn't even hit the bus. */
- printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ);
-- release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+ if (RTC_IOMAPPED)
-+ release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+ else
-+ release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
- return -EIO;
- }
- hpet_rtc_timer_init();
-@@ -1070,7 +1089,10 @@ static void __exit rtc_exit (void)
- if (rtc_has_irq)
- free_irq (rtc_irq, &rtc_port);
- #else
-- release_region (RTC_PORT (0), RTC_IO_EXTENT);
-+ if (RTC_IOMAPPED)
-+ release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+ else
-+ release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
- #ifdef RTC_IRQ
- if (rtc_has_irq)
- free_irq (RTC_IRQ, NULL);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/sb1250_duart.c linux_HEAD/drivers/char/sb1250_duart.c
---- linux-2.6.12/drivers/char/sb1250_duart.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/char/sb1250_duart.c 2005-02-28 16:56:48.000000000 +0100
-@@ -0,0 +1,899 @@
-+/*
-+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+ * Driver support for the on-chip sb1250 dual-channel serial port,
-+ * running in asynchronous mode. Also, support for doing a serial console
-+ * on one of those ports
-+ */
-+#include <linux/config.h>
-+#include <linux/types.h>
-+#include <linux/serial.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/kdev_t.h>
-+#include <linux/major.h>
-+#include <linux/termios.h>
-+#include <linux/spinlock.h>
-+#include <linux/irq.h>
-+#include <linux/errno.h>
-+#include <linux/tty.h>
-+#include <linux/sched.h>
-+#include <linux/tty_flip.h>
-+#include <linux/timer.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <asm/delay.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/sibyte/swarm.h>
-+#include <asm/sibyte/sb1250_regs.h>
-+#include <asm/sibyte/sb1250_uart.h>
-+#include <asm/sibyte/sb1250_int.h>
-+#include <asm/sibyte/sb1250.h>
-+#include <asm/war.h>
-+
-+/* Toggle spewing of debugging output */
-+#undef DUART_SPEW
-+
-+#define DEFAULT_CFLAGS (CS8 | B115200)
-+
-+#define TX_INTEN 1
-+#define DUART_INITIALIZED 2
-+
-+#ifndef MIN
-+#define MIN(a,b) ((a) < (b) ? (a) : (b))
-+#endif
-+
-+#define DUART_MAX_LINE 2
-+char sb1250_duart_present[DUART_MAX_LINE] = {1,1};
-+EXPORT_SYMBOL(sb1250_duart_present);
-+
-+/*
-+ * Still not sure what the termios structures set up here are for,
-+ * but we have to supply pointers to them to register the tty driver
-+ */
-+static struct tty_driver *sb1250_duart_driver; //, sb1250_duart_callout_driver;
-+
-+/*
-+ * This lock protects both the open flags for all the uart states as
-+ * well as the reference count for the module
-+ */
-+static DEFINE_SPINLOCK(open_lock);
-+
-+typedef struct {
-+ unsigned char outp_buf[SERIAL_XMIT_SIZE];
-+ unsigned int outp_head;
-+ unsigned int outp_tail;
-+ unsigned int outp_count;
-+ spinlock_t outp_lock;
-+ unsigned int open;
-+ unsigned int line;
-+ unsigned int last_cflags;
-+ unsigned long flags;
-+ struct tty_struct *tty;
-+ /* CSR addresses */
-+ u32 *status;
-+ u32 *imr;
-+ u32 *tx_hold;
-+ u32 *rx_hold;
-+ u32 *mode_1;
-+ u32 *mode_2;
-+ u32 *clk_sel;
-+ u32 *cmd;
-+} uart_state_t;
-+
-+static uart_state_t uart_states[DUART_MAX_LINE];
-+
-+/*
-+ * Inline functions local to this module
-+ */
-+
-+/*
-+ * In bug 1956, we get glitches that can mess up uart registers. This
-+ * "write-mode-1 after any register access" is the accepted
-+ * workaround.
-+ */
-+#if SIBYTE_1956_WAR
-+static unsigned int last_mode1[DUART_MAX_LINE];
-+#endif
-+
-+static inline u32 READ_SERCSR(u32 *addr, int line)
-+{
-+ u32 val = csr_in32(addr);
-+#if SIBYTE_1956_WAR
-+ csr_out32(last_mode1[line], uart_states[line].mode_1);
-+#endif
-+ return val;
-+}
-+
-+static inline void WRITE_SERCSR(u32 val, u32 *addr, int line)
-+{
-+ csr_out32(val, addr);
-+#if SIBYTE_1956_WAR
-+ csr_out32(last_mode1[line], uart_states[line].mode_1);
-+#endif
-+}
-+
-+static void init_duart_port(uart_state_t *port, int line)
-+{
-+ if (!(port->flags & DUART_INITIALIZED)) {
-+ port->line = line;
-+ port->status = IOADDR(A_DUART_CHANREG(line, R_DUART_STATUS));
-+ port->imr = IOADDR(A_DUART_IMRREG(line));
-+ port->tx_hold = IOADDR(A_DUART_CHANREG(line, R_DUART_TX_HOLD));
-+ port->rx_hold = IOADDR(A_DUART_CHANREG(line, R_DUART_RX_HOLD));
-+ port->mode_1 = IOADDR(A_DUART_CHANREG(line,
-+ R_DUART_MODE_REG_1));
-+ port->mode_2 = IOADDR(A_DUART_CHANREG(line,
-+ R_DUART_MODE_REG_2));
-+ port->clk_sel = IOADDR(A_DUART_CHANREG(line, R_DUART_CLK_SEL));
-+ port->cmd = IOADDR(A_DUART_CHANREG(line, R_DUART_CMD));
-+ port->flags |= DUART_INITIALIZED;
-+ }
-+}
-+
-+/*
-+ * Mask out the passed interrupt lines at the duart level. This should be
-+ * called while holding the associated outp_lock.
-+ */
-+static inline void duart_mask_ints(unsigned int line, unsigned int mask)
-+{
-+ uart_state_t *port = uart_states + line;
-+ u64 tmp = READ_SERCSR(port->imr, line);
-+ WRITE_SERCSR(tmp & ~mask, port->imr, line);
-+}
-+
-+
-+/* Unmask the passed interrupt lines at the duart level */
-+static inline void duart_unmask_ints(unsigned int line, unsigned int mask)
-+{
-+ uart_state_t *port = uart_states + line;
-+ u64 tmp = READ_SERCSR(port->imr, line);
-+ WRITE_SERCSR(tmp | mask, port->imr, line);
-+}
-+
-+static inline void transmit_char_pio(uart_state_t *us)
-+{
-+ struct tty_struct *tty = us->tty;
-+ int blocked = 0;
-+
-+ if (spin_trylock(&us->outp_lock)) {
-+ for (;;) {
-+ if (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_RDY))
-+ break;
-+ if (us->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
-+ break;
-+ } else {
-+ WRITE_SERCSR(us->outp_buf[us->outp_head],
-+ us->tx_hold, us->line);
-+ us->outp_head = (us->outp_head + 1) & (SERIAL_XMIT_SIZE-1);
-+ if (--us->outp_count <= 0)
-+ break;
-+ }
-+ udelay(10);
-+ }
-+ spin_unlock(&us->outp_lock);
-+ } else {
-+ blocked = 1;
-+ }
-+
-+ if (!us->outp_count || tty->stopped ||
-+ tty->hw_stopped || blocked) {
-+ us->flags &= ~TX_INTEN;
-+ duart_mask_ints(us->line, M_DUART_IMR_TX);
-+ }
-+
-+ if (us->open &&
-+ (us->outp_count < (SERIAL_XMIT_SIZE/2))) {
-+ /*
-+ * We told the discipline at one point that we had no
-+ * space, so it went to sleep. Wake it up when we hit
-+ * half empty
-+ */
-+ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+ tty->ldisc.write_wakeup)
-+ tty->ldisc.write_wakeup(tty);
-+ wake_up_interruptible(&tty->write_wait);
-+ }
-+}
-+
-+/*
-+ * Generic interrupt handler for both channels. dev_id is a pointer
-+ * to the proper uart_states structure, so from that we can derive
-+ * which port interrupted
-+ */
-+
-+static irqreturn_t duart_int(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+ uart_state_t *us = (uart_state_t *)dev_id;
-+ struct tty_struct *tty = us->tty;
-+ unsigned int status = READ_SERCSR(us->status, us->line);
-+
-+#ifdef DUART_SPEW
-+ printk("DUART INT\n");
-+#endif
-+
-+ if (status & M_DUART_RX_RDY) {
-+ int counter = 2048;
-+ unsigned int ch;
-+
-+ if (status & M_DUART_OVRUN_ERR)
-+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
-+ if (status & M_DUART_PARITY_ERR) {
-+ printk("Parity error!\n");
-+ } else if (status & M_DUART_FRM_ERR) {
-+ printk("Frame error!\n");
-+ }
-+
-+ while (counter > 0) {
-+ if (!(READ_SERCSR(us->status, us->line) & M_DUART_RX_RDY))
-+ break;
-+ ch = READ_SERCSR(us->rx_hold, us->line);
-+ if (tty->flip.count < TTY_FLIPBUF_SIZE) {
-+ *tty->flip.char_buf_ptr++ = ch;
-+ *tty->flip.flag_buf_ptr++ = 0;
-+ tty->flip.count++;
-+ }
-+ udelay(1);
-+ counter--;
-+ }
-+ tty_flip_buffer_push(tty);
-+ }
-+
-+ if (status & M_DUART_TX_RDY) {
-+ transmit_char_pio(us);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/*
-+ * Actual driver functions
-+ */
-+
-+/* Return the number of characters we can accomodate in a write at this instant */
-+static int duart_write_room(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ int retval;
-+
-+ retval = SERIAL_XMIT_SIZE - us->outp_count;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_write_room called, returning %i\n", retval);
-+#endif
-+
-+ return retval;
-+}
-+
-+/* memcpy the data from src to destination, but take extra care if the
-+ data is coming from user space */
-+static inline int copy_buf(char *dest, const char *src, int size, int from_user)
-+{
-+ if (from_user) {
-+ (void) copy_from_user(dest, src, size);
-+ } else {
-+ memcpy(dest, src, size);
-+ }
-+ return size;
-+}
-+
-+/*
-+ * Buffer up to count characters from buf to be written. If we don't have
-+ * other characters buffered, enable the tx interrupt to start sending
-+ */
-+static int duart_write(struct tty_struct *tty, const unsigned char *buf,
-+ int count)
-+{
-+ uart_state_t *us;
-+ int c, t, total = 0;
-+ unsigned long flags;
-+
-+ if (!tty) return 0;
-+
-+ us = tty->driver_data;
-+ if (!us) return 0;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_write called for %i chars by %i (%s)\n", count, current->pid, current->comm);
-+#endif
-+
-+ spin_lock_irqsave(&us->outp_lock, flags);
-+
-+ for (;;) {
-+ c = count;
-+
-+ t = SERIAL_XMIT_SIZE - us->outp_tail;
-+ if (t < c) c = t;
-+
-+ t = SERIAL_XMIT_SIZE - 1 - us->outp_count;
-+ if (t < c) c = t;
-+
-+ if (c <= 0) break;
-+
-+ memcpy(us->outp_buf + us->outp_tail, buf, c);
-+
-+ us->outp_count += c;
-+ us->outp_tail = (us->outp_tail + c) & (SERIAL_XMIT_SIZE - 1);
-+ buf += c;
-+ count -= c;
-+ total += c;
-+ }
-+
-+ spin_unlock_irqrestore(&us->outp_lock, flags);
-+
-+ if (us->outp_count && !tty->stopped &&
-+ !tty->hw_stopped && !(us->flags & TX_INTEN)) {
-+ us->flags |= TX_INTEN;
-+ duart_unmask_ints(us->line, M_DUART_IMR_TX);
-+ }
-+
-+ return total;
-+}
-+
-+
-+/* Buffer one character to be written. If there's not room for it, just drop
-+ it on the floor. This is used for echo, among other things */
-+static void duart_put_char(struct tty_struct *tty, u_char ch)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ unsigned long flags;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_put_char called. Char is %x (%c)\n", (int)ch, ch);
-+#endif
-+
-+ spin_lock_irqsave(&us->outp_lock, flags);
-+
-+ if (us->outp_count == SERIAL_XMIT_SIZE) {
-+ spin_unlock_irqrestore(&us->outp_lock, flags);
-+ return;
-+ }
-+
-+ us->outp_buf[us->outp_tail] = ch;
-+ us->outp_tail = (us->outp_tail + 1) &(SERIAL_XMIT_SIZE-1);
-+ us->outp_count++;
-+
-+ spin_unlock_irqrestore(&us->outp_lock, flags);
-+}
-+
-+static void duart_flush_chars(struct tty_struct * tty)
-+{
-+ uart_state_t *port;
-+
-+ if (!tty) return;
-+
-+ port = tty->driver_data;
-+
-+ if (!port) return;
-+
-+ if (port->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
-+ return;
-+ }
-+
-+ port->flags |= TX_INTEN;
-+ duart_unmask_ints(port->line, M_DUART_IMR_TX);
-+}
-+
-+/* Return the number of characters in the output buffer that have yet to be
-+ written */
-+static int duart_chars_in_buffer(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ int retval;
-+
-+ retval = us->outp_count;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_chars_in_buffer returning %i\n", retval);
-+#endif
-+ return retval;
-+}
-+
-+/* Kill everything we haven't yet shoved into the FIFO. Turn off the
-+ transmit interrupt since we've nothing more to transmit */
-+static void duart_flush_buffer(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ unsigned long flags;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_flush_buffer called\n");
-+#endif
-+ spin_lock_irqsave(&us->outp_lock, flags);
-+ us->outp_head = us->outp_tail = us->outp_count = 0;
-+ spin_unlock_irqrestore(&us->outp_lock, flags);
-+
-+ wake_up_interruptible(&us->tty->write_wait);
-+ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+ tty->ldisc.write_wakeup)
-+ tty->ldisc.write_wakeup(tty);
-+}
-+
-+
-+/* See sb1250 user manual for details on these registers */
-+static inline void duart_set_cflag(unsigned int line, unsigned int cflag)
-+{
-+ unsigned int mode_reg1 = 0, mode_reg2 = 0;
-+ unsigned int clk_divisor;
-+ uart_state_t *port = uart_states + line;
-+
-+ switch (cflag & CSIZE) {
-+ case CS7:
-+ mode_reg1 |= V_DUART_BITS_PER_CHAR_7;
-+
-+ default:
-+ /* We don't handle CS5 or CS6...is there a way we're supposed to flag this?
-+ right now we just force them to CS8 */
-+ mode_reg1 |= 0x0;
-+ break;
-+ }
-+ if (cflag & CSTOPB) {
-+ mode_reg2 |= M_DUART_STOP_BIT_LEN_2;
-+ }
-+ if (!(cflag & PARENB)) {
-+ mode_reg1 |= V_DUART_PARITY_MODE_NONE;
-+ }
-+ if (cflag & PARODD) {
-+ mode_reg1 |= M_DUART_PARITY_TYPE_ODD;
-+ }
-+
-+ /* Formula for this is (5000000/baud)-1, but we saturate
-+ at 12 bits, which means we can't actually do anything less
-+ that 1200 baud */
-+ switch (cflag & CBAUD) {
-+ case B200:
-+ case B300:
-+ case B1200: clk_divisor = 4095; break;
-+ case B1800: clk_divisor = 2776; break;
-+ case B2400: clk_divisor = 2082; break;
-+ case B4800: clk_divisor = 1040; break;
-+ default:
-+ case B9600: clk_divisor = 519; break;
-+ case B19200: clk_divisor = 259; break;
-+ case B38400: clk_divisor = 129; break;
-+ case B57600: clk_divisor = 85; break;
-+ case B115200: clk_divisor = 42; break;
-+ }
-+ WRITE_SERCSR(mode_reg1, port->mode_1, port->line);
-+ WRITE_SERCSR(mode_reg2, port->mode_2, port->line);
-+ WRITE_SERCSR(clk_divisor, port->clk_sel, port->line);
-+ port->last_cflags = cflag;
-+}
-+
-+
-+/* Handle notification of a termios change. */
-+static void duart_set_termios(struct tty_struct *tty, struct termios *old)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_set_termios called by %i (%s)\n", current->pid, current->comm);
-+#endif
-+ if (old && tty->termios->c_cflag == old->c_cflag)
-+ return;
-+ duart_set_cflag(us->line, tty->termios->c_cflag);
-+}
-+
-+static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) {
-+
-+ struct serial_struct tmp;
-+
-+ memset(&tmp, 0, sizeof(tmp));
-+
-+ tmp.type=PORT_SB1250;
-+ tmp.line=us->line;
-+ tmp.port=A_DUART_CHANREG(tmp.line,0);
-+ tmp.irq=K_INT_UART_0 + tmp.line;
-+ tmp.xmit_fifo_size=16; /* fixed by hw */
-+ tmp.baud_base=5000000;
-+ tmp.io_type=SERIAL_IO_MEM;
-+
-+ if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
-+ return -EFAULT;
-+
-+ return 0;
-+}
-+
-+static int duart_ioctl(struct tty_struct *tty, struct file * file,
-+ unsigned int cmd, unsigned long arg)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+/* if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
-+ return -ENODEV;*/
-+ switch (cmd) {
-+ case TIOCMGET:
-+ printk("Ignoring TIOCMGET\n");
-+ break;
-+ case TIOCMBIS:
-+ printk("Ignoring TIOCMBIS\n");
-+ break;
-+ case TIOCMBIC:
-+ printk("Ignoring TIOCMBIC\n");
-+ break;
-+ case TIOCMSET:
-+ printk("Ignoring TIOCMSET\n");
-+ break;
-+ case TIOCGSERIAL:
-+ return get_serial_info(us,(struct serial_struct *) arg);
-+ case TIOCSSERIAL:
-+ printk("Ignoring TIOCSSERIAL\n");
-+ break;
-+ case TIOCSERCONFIG:
-+ printk("Ignoring TIOCSERCONFIG\n");
-+ break;
-+ case TIOCSERGETLSR: /* Get line status register */
-+ printk("Ignoring TIOCSERGETLSR\n");
-+ break;
-+ case TIOCSERGSTRUCT:
-+ printk("Ignoring TIOCSERGSTRUCT\n");
-+ break;
-+ case TIOCMIWAIT:
-+ printk("Ignoring TIOCMIWAIT\n");
-+ break;
-+ case TIOCGICOUNT:
-+ printk("Ignoring TIOCGICOUNT\n");
-+ break;
-+ case TIOCSERGWILD:
-+ printk("Ignoring TIOCSERGWILD\n");
-+ break;
-+ case TIOCSERSWILD:
-+ printk("Ignoring TIOCSERSWILD\n");
-+ break;
-+ default:
-+ break;
-+ }
-+// printk("Ignoring IOCTL %x from pid %i (%s)\n", cmd, current->pid, current->comm);
-+ return -ENOIOCTLCMD;
-+}
-+
-+/* XXXKW locking? */
-+static void duart_start(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_start called\n");
-+#endif
-+
-+ if (us->outp_count && !(us->flags & TX_INTEN)) {
-+ us->flags |= TX_INTEN;
-+ duart_unmask_ints(us->line, M_DUART_IMR_TX);
-+ }
-+}
-+
-+/* XXXKW locking? */
-+static void duart_stop(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_stop called\n");
-+#endif
-+
-+ if (us->outp_count && (us->flags & TX_INTEN)) {
-+ us->flags &= ~TX_INTEN;
-+ duart_mask_ints(us->line, M_DUART_IMR_TX);
-+ }
-+}
-+
-+/* Not sure on the semantics of this; are we supposed to wait until the stuff
-+ already in the hardware FIFO drains, or are we supposed to wait until
-+ we've drained the output buffer, too? I'm assuming the former, 'cause thats
-+ what the other drivers seem to assume
-+*/
-+
-+static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ unsigned long orig_jiffies;
-+
-+ orig_jiffies = jiffies;
-+#ifdef DUART_SPEW
-+ printk("duart_wait_until_sent(%d)+\n", timeout);
-+#endif
-+ while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) {
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ schedule_timeout(1);
-+ if (signal_pending(current))
-+ break;
-+ if (timeout && time_after(jiffies, orig_jiffies + timeout))
-+ break;
-+ }
-+#ifdef DUART_SPEW
-+ printk("duart_wait_until_sent()-\n");
-+#endif
-+}
-+
-+/*
-+ * duart_hangup() --- called by tty_hangup() when a hangup is signaled.
-+ */
-+static void duart_hangup(struct tty_struct *tty)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+ duart_flush_buffer(tty);
-+ us->open = 0;
-+ us->tty = 0;
-+}
-+
-+/*
-+ * Open a tty line. Note that this can be called multiple times, so ->open can
-+ * be >1. Only set up the tty struct if this is a "new" open, e.g. ->open was
-+ * zero
-+ */
-+static int duart_open(struct tty_struct *tty, struct file *filp)
-+{
-+ uart_state_t *us;
-+ unsigned int line = tty->index;
-+ unsigned long flags;
-+
-+ if ((line >= tty->driver->num) || !sb1250_duart_present[line])
-+ return -ENODEV;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_open called by %i (%s), tty is %p, rw is %p, ww is %p\n",
-+ current->pid, current->comm, tty, tty->read_wait,
-+ tty->write_wait);
-+#endif
-+
-+ us = uart_states + line;
-+ tty->driver_data = us;
-+
-+ spin_lock_irqsave(&open_lock, flags);
-+ if (!us->open) {
-+ us->tty = tty;
-+ us->tty->termios->c_cflag = us->last_cflags;
-+ }
-+ us->open++;
-+ us->flags &= ~TX_INTEN;
-+ duart_unmask_ints(line, M_DUART_IMR_RX);
-+ spin_unlock_irqrestore(&open_lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+/*
-+ * Close a reference count out. If reference count hits zero, null the
-+ * tty, kill the interrupts. The tty_io driver is responsible for making
-+ * sure we've cleared out our internal buffers before calling close()
-+ */
-+static void duart_close(struct tty_struct *tty, struct file *filp)
-+{
-+ uart_state_t *us = (uart_state_t *) tty->driver_data;
-+ unsigned long flags;
-+
-+#ifdef DUART_SPEW
-+ printk("duart_close called by %i (%s)\n", current->pid, current->comm);
-+#endif
-+
-+ if (!us || !us->open)
-+ return;
-+
-+ spin_lock_irqsave(&open_lock, flags);
-+ if (tty_hung_up_p(filp)) {
-+ spin_unlock_irqrestore(&open_lock, flags);
-+ return;
-+ }
-+
-+ if (--us->open < 0) {
-+ us->open = 0;
-+ printk(KERN_ERR "duart: bad open count: %d\n", us->open);
-+ }
-+ if (us->open) {
-+ spin_unlock_irqrestore(&open_lock, flags);
-+ return;
-+ }
-+
-+ spin_unlock_irqrestore(&open_lock, flags);
-+
-+ tty->closing = 1;
-+
-+ /* Stop accepting input */
-+ duart_mask_ints(us->line, M_DUART_IMR_RX);
-+ /* Wait for FIFO to drain */
-+ while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT))
-+ ;
-+
-+ if (tty->driver->flush_buffer)
-+ tty->driver->flush_buffer(tty);
-+ if (tty->ldisc.flush_buffer)
-+ tty->ldisc.flush_buffer(tty);
-+ tty->closing = 0;
-+}
-+
-+
-+static struct tty_operations duart_ops = {
-+ .open = duart_open,
-+ .close = duart_close,
-+ .write = duart_write,
-+ .put_char = duart_put_char,
-+ .flush_chars = duart_flush_chars,
-+ .write_room = duart_write_room,
-+ .chars_in_buffer = duart_chars_in_buffer,
-+ .flush_buffer = duart_flush_buffer,
-+ .ioctl = duart_ioctl,
-+// .throttle = duart_throttle,
-+// .unthrottle = duart_unthrottle,
-+ .set_termios = duart_set_termios,
-+ .stop = duart_stop,
-+ .start = duart_start,
-+ .hangup = duart_hangup,
-+ .wait_until_sent = duart_wait_until_sent,
-+};
-+
-+/* Set up the driver and register it, register the 2 1250 UART interrupts. This
-+ is called from tty_init, or as a part of the module init */
-+static int __init sb1250_duart_init(void)
-+{
-+ int i;
-+
-+ sb1250_duart_driver = alloc_tty_driver(DUART_MAX_LINE);
-+ if (!sb1250_duart_driver)
-+ return -ENOMEM;
-+
-+ sb1250_duart_driver->owner = THIS_MODULE;
-+ sb1250_duart_driver->name = "duart";
-+ sb1250_duart_driver->devfs_name = "duart/";
-+ sb1250_duart_driver->major = TTY_MAJOR;
-+ sb1250_duart_driver->minor_start = SB1250_DUART_MINOR_BASE;
-+ sb1250_duart_driver->type = TTY_DRIVER_TYPE_SERIAL;
-+ sb1250_duart_driver->subtype = SERIAL_TYPE_NORMAL;
-+ sb1250_duart_driver->init_termios = tty_std_termios;
-+ sb1250_duart_driver->flags = TTY_DRIVER_REAL_RAW;
-+ tty_set_operations(sb1250_duart_driver, &duart_ops);
-+
-+ for (i=0; i<DUART_MAX_LINE; i++) {
-+ uart_state_t *port = uart_states + i;
-+
-+ if (!sb1250_duart_present[i])
-+ continue;
-+
-+ init_duart_port(port, i);
-+ spin_lock_init(&port->outp_lock);
-+ duart_mask_ints(i, M_DUART_IMR_ALL);
-+ if (request_irq(K_INT_UART_0+i, duart_int, 0, "uart", port)) {
-+ panic("Couldn't get uart0 interrupt line");
-+ }
-+ __raw_writeq(M_DUART_RX_EN|M_DUART_TX_EN,
-+ IOADDR(A_DUART_CHANREG(i, R_DUART_CMD)));
-+ duart_set_cflag(i, DEFAULT_CFLAGS);
-+ }
-+
-+ /* Interrupts are now active, our ISR can be called. */
-+
-+ if (tty_register_driver(sb1250_duart_driver)) {
-+ printk(KERN_ERR "Couldn't register sb1250 duart serial driver\n");
-+ put_tty_driver(sb1250_duart_driver);
-+ return 1;
-+ }
-+ return 0;
-+}
-+
-+/* Unload the driver. Unregister stuff, get ready to go away */
-+static void __exit sb1250_duart_fini(void)
-+{
-+ unsigned long flags;
-+ int i;
-+
-+ local_irq_save(flags);
-+ tty_unregister_driver(sb1250_duart_driver);
-+ put_tty_driver(sb1250_duart_driver);
-+
-+ for (i=0; i<DUART_MAX_LINE; i++) {
-+ if (!sb1250_duart_present[i])
-+ continue;
-+ free_irq(K_INT_UART_0+i, &uart_states[i]);
-+ disable_irq(K_INT_UART_0+i);
-+ }
-+ local_irq_restore(flags);
-+}
-+
-+module_init(sb1250_duart_init);
-+module_exit(sb1250_duart_fini);
-+MODULE_DESCRIPTION("SB1250 Duart serial driver");
-+MODULE_AUTHOR("Justin Carlson, Broadcom Corp.");
-+
-+#ifdef CONFIG_SIBYTE_SB1250_DUART_CONSOLE
-+
-+/*
-+ * Serial console stuff. Very basic, polling driver for doing serial
-+ * console output. The console_sem is held by the caller, so we
-+ * shouldn't be interrupted for more console activity.
-+ * XXXKW What about getting interrupted by uart driver activity?
-+ */
-+
-+void serial_outc(unsigned char c, int line)
-+{
-+ uart_state_t *port = uart_states + line;
-+ while (!(READ_SERCSR(port->status, line) & M_DUART_TX_RDY)) ;
-+ WRITE_SERCSR(c, port->tx_hold, line);
-+ while (!(READ_SERCSR(port->status, port->line) & M_DUART_TX_EMT)) ;
-+}
-+
-+static void ser_console_write(struct console *cons, const char *s,
-+ unsigned int count)
-+{
-+ int line = cons->index;
-+ uart_state_t *port = uart_states + line;
-+ u32 imr;
-+
-+ imr = READ_SERCSR(port->imr, line);
-+ WRITE_SERCSR(0, port->imr, line);
-+ while (count--) {
-+ if (*s == '\n')
-+ serial_outc('\r', line);
-+ serial_outc(*s++, line);
-+ }
-+ WRITE_SERCSR(imr, port->imr, line);
-+}
-+
-+static struct tty_driver *ser_console_device(struct console *c, int *index)
-+{
-+ *index = c->index;
-+ return sb1250_duart_driver;
-+}
-+
-+static int ser_console_setup(struct console *cons, char *str)
-+{
-+ int i;
-+
-+ for (i=0; i<DUART_MAX_LINE; i++) {
-+ uart_state_t *port = uart_states + i;
-+
-+ if (!sb1250_duart_present[i])
-+ continue;
-+
-+ init_duart_port(port, i);
-+#if SIBYTE_1956_WAR
-+ last_mode1[i] = V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8;
-+#endif
-+ WRITE_SERCSR(V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8,
-+ port->mode_1, i);
-+ WRITE_SERCSR(M_DUART_STOP_BIT_LEN_1,
-+ port->mode_2, i);
-+ WRITE_SERCSR(V_DUART_BAUD_RATE(115200),
-+ port->clk_sel, i);
-+ WRITE_SERCSR(M_DUART_RX_EN|M_DUART_TX_EN,
-+ port->cmd, i);
-+ }
-+ return 0;
-+}
-+
-+static struct console sb1250_ser_cons = {
-+ .name = "duart",
-+ .write = ser_console_write,
-+ .device = ser_console_device,
-+ .setup = ser_console_setup,
-+ .flags = CON_PRINTBUFFER,
-+ .index = -1,
-+};
-+
-+static int __init sb1250_serial_console_init(void)
-+{
-+ register_console(&sb1250_ser_cons);
-+ return 0;
-+}
-+
-+console_initcall(sb1250_serial_console_init);
-+
-+#endif /* CONFIG_SIBYTE_SB1250_DUART_CONSOLE */
-diff -urpNX dontdiff linux-2.6.12/drivers/char/tb0219.c linux_HEAD/drivers/char/tb0219.c
---- linux-2.6.12/drivers/char/tb0219.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/tb0219.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,347 +0,0 @@
--/*
-- * Driver for TANBAC TB0219 base board.
-- *
-- * Copyright (C) 2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#include <linux/device.h>
--#include <linux/fs.h>
--#include <linux/init.h>
--#include <linux/module.h>
--
--#include <asm/io.h>
--#include <asm/reboot.h>
--
--MODULE_AUTHOR("Yoichi Yuasa <yuasa at hh.iij4u.or.jp>");
--MODULE_DESCRIPTION("TANBAC TB0219 base board driver");
--MODULE_LICENSE("GPL");
--
--static int major; /* default is dynamic major device number */
--module_param(major, int, 0);
--MODULE_PARM_DESC(major, "Major device number");
--
--static void (*old_machine_restart)(char *command);
--static void __iomem *tb0219_base;
--static spinlock_t tb0219_lock;
--
--#define tb0219_read(offset) readw(tb0219_base + (offset))
--#define tb0219_write(offset, value) writew((value), tb0219_base + (offset))
--
--#define TB0219_START 0x0a000000UL
--#define TB0219_SIZE 0x20UL
--
--#define TB0219_LED 0x00
--#define TB0219_GPIO_INPUT 0x02
--#define TB0219_GPIO_OUTPUT 0x04
--#define TB0219_DIP_SWITCH 0x06
--#define TB0219_MISC 0x08
--#define TB0219_RESET 0x0e
--#define TB0219_PCI_SLOT1_IRQ_STATUS 0x10
--#define TB0219_PCI_SLOT2_IRQ_STATUS 0x12
--#define TB0219_PCI_SLOT3_IRQ_STATUS 0x14
--
--typedef enum {
-- TYPE_LED,
-- TYPE_GPIO_OUTPUT,
--} tb0219_type_t;
--
--/*
-- * Minor device number
-- * 0 = 7 segment LED
-- *
-- * 16 = GPIO IN 0
-- * 17 = GPIO IN 1
-- * 18 = GPIO IN 2
-- * 19 = GPIO IN 3
-- * 20 = GPIO IN 4
-- * 21 = GPIO IN 5
-- * 22 = GPIO IN 6
-- * 23 = GPIO IN 7
-- *
-- * 32 = GPIO OUT 0
-- * 33 = GPIO OUT 1
-- * 34 = GPIO OUT 2
-- * 35 = GPIO OUT 3
-- * 36 = GPIO OUT 4
-- * 37 = GPIO OUT 5
-- * 38 = GPIO OUT 6
-- * 39 = GPIO OUT 7
-- *
-- * 48 = DIP switch 1
-- * 49 = DIP switch 2
-- * 50 = DIP switch 3
-- * 51 = DIP switch 4
-- * 52 = DIP switch 5
-- * 53 = DIP switch 6
-- * 54 = DIP switch 7
-- * 55 = DIP switch 8
-- */
--
--static inline char get_led(void)
--{
-- return (char)tb0219_read(TB0219_LED);
--}
--
--static inline char get_gpio_input_pin(unsigned int pin)
--{
-- uint16_t values;
--
-- values = tb0219_read(TB0219_GPIO_INPUT);
-- if (values & (1 << pin))
-- return '1';
--
-- return '0';
--}
--
--static inline char get_gpio_output_pin(unsigned int pin)
--{
-- uint16_t values;
--
-- values = tb0219_read(TB0219_GPIO_OUTPUT);
-- if (values & (1 << pin))
-- return '1';
--
-- return '0';
--}
--
--static inline char get_dip_switch(unsigned int pin)
--{
-- uint16_t values;
--
-- values = tb0219_read(TB0219_DIP_SWITCH);
-- if (values & (1 << pin))
-- return '1';
--
-- return '0';
--}
--
--static inline int set_led(char command)
--{
-- tb0219_write(TB0219_LED, command);
--
-- return 0;
--}
--
--static inline int set_gpio_output_pin(unsigned int pin, char command)
--{
-- unsigned long flags;
-- uint16_t value;
--
-- if (command != '0' && command != '1')
-- return -EINVAL;
--
-- spin_lock_irqsave(&tb0219_lock, flags);
-- value = tb0219_read(TB0219_GPIO_OUTPUT);
-- if (command == '0')
-- value &= ~(1 << pin);
-- else
-- value |= 1 << pin;
-- tb0219_write(TB0219_GPIO_OUTPUT, value);
-- spin_unlock_irqrestore(&tb0219_lock, flags);
--
-- return 0;
--
--}
--
--static ssize_t tanbac_tb0219_read(struct file *file, char __user *buf, size_t len,
-- loff_t *ppos)
--{
-- unsigned int minor;
-- char value;
--
-- minor = iminor(file->f_dentry->d_inode);
-- switch (minor) {
-- case 0:
-- value = get_led();
-- break;
-- case 16 ... 23:
-- value = get_gpio_input_pin(minor - 16);
-- break;
-- case 32 ... 39:
-- value = get_gpio_output_pin(minor - 32);
-- break;
-- case 48 ... 55:
-- value = get_dip_switch(minor - 48);
-- break;
-- default:
-- return -EBADF;
-- }
--
-- if (len <= 0)
-- return -EFAULT;
--
-- if (put_user(value, buf))
-- return -EFAULT;
--
-- return 1;
--}
--
--static ssize_t tanbac_tb0219_write(struct file *file, const char __user *data,
-- size_t len, loff_t *ppos)
--{
-- unsigned int minor;
-- tb0219_type_t type;
-- size_t i;
-- int retval = 0;
-- char c;
--
-- minor = iminor(file->f_dentry->d_inode);
-- switch (minor) {
-- case 0:
-- type = TYPE_LED;
-- break;
-- case 32 ... 39:
-- type = TYPE_GPIO_OUTPUT;
-- break;
-- default:
-- return -EBADF;
-- }
--
-- for (i = 0; i < len; i++) {
-- if (get_user(c, data + i))
-- return -EFAULT;
--
-- switch (type) {
-- case TYPE_LED:
-- retval = set_led(c);
-- break;
-- case TYPE_GPIO_OUTPUT:
-- retval = set_gpio_output_pin(minor - 32, c);
-- break;
-- }
--
-- if (retval < 0)
-- break;
-- }
--
-- return i;
--}
--
--static int tanbac_tb0219_open(struct inode *inode, struct file *file)
--{
-- unsigned int minor;
--
-- minor = iminor(inode);
-- switch (minor) {
-- case 0:
-- case 16 ... 23:
-- case 32 ... 39:
-- case 48 ... 55:
-- return nonseekable_open(inode, file);
-- default:
-- break;
-- }
--
-- return -EBADF;
--}
--
--static int tanbac_tb0219_release(struct inode *inode, struct file *file)
--{
-- return 0;
--}
--
--static struct file_operations tb0219_fops = {
-- .owner = THIS_MODULE,
-- .read = tanbac_tb0219_read,
-- .write = tanbac_tb0219_write,
-- .open = tanbac_tb0219_open,
-- .release = tanbac_tb0219_release,
--};
--
--static void tb0219_restart(char *command)
--{
-- tb0219_write(TB0219_RESET, 0);
--}
--
--static int tb0219_probe(struct device *dev)
--{
-- int retval;
--
-- if (request_mem_region(TB0219_START, TB0219_SIZE, "TB0219") == NULL)
-- return -EBUSY;
--
-- tb0219_base = ioremap(TB0219_START, TB0219_SIZE);
-- if (tb0219_base == NULL) {
-- release_mem_region(TB0219_START, TB0219_SIZE);
-- return -ENOMEM;
-- }
--
-- retval = register_chrdev(major, "TB0219", &tb0219_fops);
-- if (retval < 0) {
-- iounmap(tb0219_base);
-- tb0219_base = NULL;
-- release_mem_region(TB0219_START, TB0219_SIZE);
-- return retval;
-- }
--
-- spin_lock_init(&tb0219_lock);
--
-- old_machine_restart = _machine_restart;
-- _machine_restart = tb0219_restart;
--
-- if (major == 0) {
-- major = retval;
-- printk(KERN_INFO "TB0219: major number %d\n", major);
-- }
--
-- return 0;
--}
--
--static int tb0219_remove(struct device *dev)
--{
-- _machine_restart = old_machine_restart;
--
-- iounmap(tb0219_base);
-- tb0219_base = NULL;
--
-- release_mem_region(TB0219_START, TB0219_SIZE);
--
-- return 0;
--}
--
--static struct platform_device *tb0219_platform_device;
--
--static struct device_driver tb0219_device_driver = {
-- .name = "TB0219",
-- .bus = &platform_bus_type,
-- .probe = tb0219_probe,
-- .remove = tb0219_remove,
--};
--
--static int __devinit tanbac_tb0219_init(void)
--{
-- int retval;
--
-- tb0219_platform_device = platform_device_register_simple("TB0219", -1, NULL, 0);
-- if (IS_ERR(tb0219_platform_device))
-- return PTR_ERR(tb0219_platform_device);
--
-- retval = driver_register(&tb0219_device_driver);
-- if (retval < 0)
-- platform_device_unregister(tb0219_platform_device);
--
-- return retval;
--}
--
--static void __devexit tanbac_tb0219_exit(void)
--{
-- driver_unregister(&tb0219_device_driver);
--
-- platform_device_unregister(tb0219_platform_device);
--}
--
--module_init(tanbac_tb0219_init);
--module_exit(tanbac_tb0219_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/char/vr41xx_rtc.c linux_HEAD/drivers/char/vr41xx_rtc.c
---- linux-2.6.12/drivers/char/vr41xx_rtc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/char/vr41xx_rtc.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,709 +0,0 @@
--/*
-- * Driver for NEC VR4100 series Real Time Clock unit.
-- *
-- * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#include <linux/device.h>
--#include <linux/fs.h>
--#include <linux/init.h>
--#include <linux/ioport.h>
--#include <linux/irq.h>
--#include <linux/mc146818rtc.h>
--#include <linux/miscdevice.h>
--#include <linux/module.h>
--#include <linux/poll.h>
--#include <linux/rtc.h>
--#include <linux/spinlock.h>
--#include <linux/types.h>
--#include <linux/wait.h>
--
--#include <asm/div64.h>
--#include <asm/io.h>
--#include <asm/time.h>
--#include <asm/uaccess.h>
--#include <asm/vr41xx/vr41xx.h>
--
--MODULE_AUTHOR("Yoichi Yuasa <yuasa at hh.iij4u.or.jp>");
--MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
--MODULE_LICENSE("GPL");
--
--#define RTC1_TYPE1_START 0x0b0000c0UL
--#define RTC1_TYPE1_END 0x0b0000dfUL
--#define RTC2_TYPE1_START 0x0b0001c0UL
--#define RTC2_TYPE1_END 0x0b0001dfUL
--
--#define RTC1_TYPE2_START 0x0f000100UL
--#define RTC1_TYPE2_END 0x0f00011fUL
--#define RTC2_TYPE2_START 0x0f000120UL
--#define RTC2_TYPE2_END 0x0f00013fUL
--
--#define RTC1_SIZE 0x20
--#define RTC2_SIZE 0x20
--
--/* RTC 1 registers */
--#define ETIMELREG 0x00
--#define ETIMEMREG 0x02
--#define ETIMEHREG 0x04
--/* RFU */
--#define ECMPLREG 0x08
--#define ECMPMREG 0x0a
--#define ECMPHREG 0x0c
--/* RFU */
--#define RTCL1LREG 0x10
--#define RTCL1HREG 0x12
--#define RTCL1CNTLREG 0x14
--#define RTCL1CNTHREG 0x16
--#define RTCL2LREG 0x18
--#define RTCL2HREG 0x1a
--#define RTCL2CNTLREG 0x1c
--#define RTCL2CNTHREG 0x1e
--
--/* RTC 2 registers */
--#define TCLKLREG 0x00
--#define TCLKHREG 0x02
--#define TCLKCNTLREG 0x04
--#define TCLKCNTHREG 0x06
--/* RFU */
--#define RTCINTREG 0x1e
-- #define TCLOCK_INT 0x08
-- #define RTCLONG2_INT 0x04
-- #define RTCLONG1_INT 0x02
-- #define ELAPSEDTIME_INT 0x01
--
--#define RTC_FREQUENCY 32768
--#define MAX_PERIODIC_RATE 6553
--#define MAX_USER_PERIODIC_RATE 64
--
--static void __iomem *rtc1_base;
--static void __iomem *rtc2_base;
--
--#define rtc1_read(offset) readw(rtc1_base + (offset))
--#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
--
--#define rtc2_read(offset) readw(rtc2_base + (offset))
--#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
--
--static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
--
--static spinlock_t rtc_task_lock;
--static wait_queue_head_t rtc_wait;
--static unsigned long rtc_irq_data;
--static struct fasync_struct *rtc_async_queue;
--static rtc_task_t *rtc_callback;
--static char rtc_name[] = "RTC";
--static unsigned long periodic_frequency;
--static unsigned long periodic_count;
--
--typedef enum {
-- RTC_RELEASE,
-- RTC_OPEN,
--} rtc_status_t;
--
--static rtc_status_t rtc_status;
--
--typedef enum {
-- FUNCTION_RTC_IOCTL,
-- FUNCTION_RTC_CONTROL,
--} rtc_callfrom_t;
--
--struct resource rtc_resource[2] = {
-- { .name = rtc_name,
-- .flags = IORESOURCE_MEM, },
-- { .name = rtc_name,
-- .flags = IORESOURCE_MEM, },
--};
--
--#define RTC_NUM_RESOURCES sizeof(rtc_resource) / sizeof(struct resource)
--
--static inline unsigned long read_elapsed_second(void)
--{
-- unsigned long first_low, first_mid, first_high;
-- unsigned long second_low, second_mid, second_high;
--
-- do {
-- first_low = rtc1_read(ETIMELREG);
-- first_mid = rtc1_read(ETIMEMREG);
-- first_high = rtc1_read(ETIMEHREG);
-- second_low = rtc1_read(ETIMELREG);
-- second_mid = rtc1_read(ETIMEMREG);
-- second_high = rtc1_read(ETIMEHREG);
-- } while (first_low != second_low || first_mid != second_mid ||
-- first_high != second_high);
--
-- return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
--}
--
--static inline void write_elapsed_second(unsigned long sec)
--{
-- spin_lock_irq(&rtc_lock);
--
-- rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
-- rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
-- rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
--
-- spin_unlock_irq(&rtc_lock);
--}
--
--static void set_alarm(struct rtc_time *time)
--{
-- unsigned long alarm_sec;
--
-- alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
-- time->tm_hour, time->tm_min, time->tm_sec);
--
-- spin_lock_irq(&rtc_lock);
--
-- rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
-- rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
-- rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
--
-- spin_unlock_irq(&rtc_lock);
--}
--
--static void read_alarm(struct rtc_time *time)
--{
-- unsigned long low, mid, high;
--
-- spin_lock_irq(&rtc_lock);
--
-- low = rtc1_read(ECMPLREG);
-- mid = rtc1_read(ECMPMREG);
-- high = rtc1_read(ECMPHREG);
--
-- spin_unlock_irq(&rtc_lock);
--
-- to_tm((high << 17) | (mid << 1) | (low >> 15), time);
-- time->tm_year -= 1900;
--}
--
--static void read_time(struct rtc_time *time)
--{
-- unsigned long epoch_sec, elapsed_sec;
--
-- epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
-- elapsed_sec = read_elapsed_second();
--
-- to_tm(epoch_sec + elapsed_sec, time);
-- time->tm_year -= 1900;
--}
--
--static void set_time(struct rtc_time *time)
--{
-- unsigned long epoch_sec, current_sec;
--
-- epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
-- current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
-- time->tm_hour, time->tm_min, time->tm_sec);
--
-- write_elapsed_second(current_sec - epoch_sec);
--}
--
--static ssize_t rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
--{
-- DECLARE_WAITQUEUE(wait, current);
-- unsigned long irq_data;
-- int retval = 0;
--
-- if (count != sizeof(unsigned int) && count != sizeof(unsigned long))
-- return -EINVAL;
--
-- add_wait_queue(&rtc_wait, &wait);
--
-- do {
-- __set_current_state(TASK_INTERRUPTIBLE);
--
-- spin_lock_irq(&rtc_lock);
-- irq_data = rtc_irq_data;
-- rtc_irq_data = 0;
-- spin_unlock_irq(&rtc_lock);
--
-- if (irq_data != 0)
-- break;
--
-- if (file->f_flags & O_NONBLOCK) {
-- retval = -EAGAIN;
-- break;
-- }
--
-- if (signal_pending(current)) {
-- retval = -ERESTARTSYS;
-- break;
-- }
-- } while (1);
--
-- if (retval == 0) {
-- if (count == sizeof(unsigned int)) {
-- retval = put_user(irq_data, (unsigned int __user *)buf);
-- if (retval == 0)
-- retval = sizeof(unsigned int);
-- } else {
-- retval = put_user(irq_data, (unsigned long __user *)buf);
-- if (retval == 0)
-- retval = sizeof(unsigned long);
-- }
--
-- }
--
-- __set_current_state(TASK_RUNNING);
-- remove_wait_queue(&rtc_wait, &wait);
--
-- return retval;
--}
--
--static unsigned int rtc_poll(struct file *file, struct poll_table_struct *table)
--{
-- poll_wait(file, &rtc_wait, table);
--
-- if (rtc_irq_data != 0)
-- return POLLIN | POLLRDNORM;
--
-- return 0;
--}
--
--static int rtc_do_ioctl(unsigned int cmd, unsigned long arg, rtc_callfrom_t from)
--{
-- struct rtc_time time;
-- unsigned long count;
--
-- switch (cmd) {
-- case RTC_AIE_ON:
-- enable_irq(ELAPSEDTIME_IRQ);
-- break;
-- case RTC_AIE_OFF:
-- disable_irq(ELAPSEDTIME_IRQ);
-- break;
-- case RTC_PIE_ON:
-- enable_irq(RTCLONG1_IRQ);
-- break;
-- case RTC_PIE_OFF:
-- disable_irq(RTCLONG1_IRQ);
-- break;
-- case RTC_ALM_SET:
-- if (copy_from_user(&time, (struct rtc_time __user *)arg,
-- sizeof(struct rtc_time)))
-- return -EFAULT;
--
-- set_alarm(&time);
-- break;
-- case RTC_ALM_READ:
-- memset(&time, 0, sizeof(struct rtc_time));
-- read_alarm(&time);
-- break;
-- case RTC_RD_TIME:
-- memset(&time, 0, sizeof(struct rtc_time));
-- read_time(&time);
-- if (copy_to_user((void __user *)arg, &time, sizeof(struct rtc_time)))
-- return -EFAULT;
-- break;
-- case RTC_SET_TIME:
-- if (capable(CAP_SYS_TIME) == 0)
-- return -EACCES;
--
-- if (copy_from_user(&time, (struct rtc_time __user *)arg,
-- sizeof(struct rtc_time)))
-- return -EFAULT;
--
-- set_time(&time);
-- break;
-- case RTC_IRQP_READ:
-- return put_user(periodic_frequency, (unsigned long __user *)arg);
-- break;
-- case RTC_IRQP_SET:
-- if (arg > MAX_PERIODIC_RATE)
-- return -EINVAL;
--
-- if (from == FUNCTION_RTC_IOCTL && arg > MAX_USER_PERIODIC_RATE &&
-- capable(CAP_SYS_RESOURCE) == 0)
-- return -EACCES;
--
-- periodic_frequency = arg;
--
-- count = RTC_FREQUENCY;
-- do_div(count, arg);
--
-- periodic_count = count;
--
-- spin_lock_irq(&rtc_lock);
--
-- rtc1_write(RTCL1LREG, count);
-- rtc1_write(RTCL1HREG, count >> 16);
--
-- spin_unlock_irq(&rtc_lock);
-- break;
-- case RTC_EPOCH_READ:
-- return put_user(epoch, (unsigned long __user *)arg);
-- case RTC_EPOCH_SET:
-- /* Doesn't support before 1900 */
-- if (arg < 1900)
-- return -EINVAL;
--
-- if (capable(CAP_SYS_TIME) == 0)
-- return -EACCES;
--
-- epoch = arg;
-- break;
-- default:
-- return -EINVAL;
-- }
--
-- return 0;
--}
--
--static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-- unsigned long arg)
--{
-- return rtc_do_ioctl(cmd, arg, FUNCTION_RTC_IOCTL);
--}
--
--static int rtc_open(struct inode *inode, struct file *file)
--{
-- spin_lock_irq(&rtc_lock);
--
-- if (rtc_status == RTC_OPEN) {
-- spin_unlock_irq(&rtc_lock);
-- return -EBUSY;
-- }
--
-- rtc_status = RTC_OPEN;
-- rtc_irq_data = 0;
--
-- spin_unlock_irq(&rtc_lock);
--
-- return 0;
--}
--
--static int rtc_release(struct inode *inode, struct file *file)
--{
-- if (file->f_flags & FASYNC)
-- (void)fasync_helper(-1, file, 0, &rtc_async_queue);
--
-- spin_lock_irq(&rtc_lock);
--
-- rtc1_write(ECMPLREG, 0);
-- rtc1_write(ECMPMREG, 0);
-- rtc1_write(ECMPHREG, 0);
-- rtc1_write(RTCL1LREG, 0);
-- rtc1_write(RTCL1HREG, 0);
--
-- rtc_status = RTC_RELEASE;
--
-- spin_unlock_irq(&rtc_lock);
--
-- disable_irq(ELAPSEDTIME_IRQ);
-- disable_irq(RTCLONG1_IRQ);
--
-- return 0;
--}
--
--static int rtc_fasync(int fd, struct file *file, int on)
--{
-- return fasync_helper(fd, file, on, &rtc_async_queue);
--}
--
--static struct file_operations rtc_fops = {
-- .owner = THIS_MODULE,
-- .llseek = no_llseek,
-- .read = rtc_read,
-- .poll = rtc_poll,
-- .ioctl = rtc_ioctl,
-- .open = rtc_open,
-- .release = rtc_release,
-- .fasync = rtc_fasync,
--};
--
--static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id, struct pt_regs *regs)
--{
-- spin_lock(&rtc_lock);
-- rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
--
-- rtc_irq_data += 0x100;
-- rtc_irq_data &= ~0xff;
-- rtc_irq_data |= RTC_AF;
-- spin_unlock(&rtc_lock);
--
-- spin_lock(&rtc_lock);
-- if (rtc_callback)
-- rtc_callback->func(rtc_callback->private_data);
-- spin_unlock(&rtc_lock);
--
-- wake_up_interruptible(&rtc_wait);
--
-- kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
--
-- return IRQ_HANDLED;
--}
--
--static irqreturn_t rtclong1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
--{
-- unsigned long count = periodic_count;
--
-- spin_lock(&rtc_lock);
-- rtc2_write(RTCINTREG, RTCLONG1_INT);
--
-- rtc1_write(RTCL1LREG, count);
-- rtc1_write(RTCL1HREG, count >> 16);
--
-- rtc_irq_data += 0x100;
-- rtc_irq_data &= ~0xff;
-- rtc_irq_data |= RTC_PF;
-- spin_unlock(&rtc_lock);
--
-- spin_lock(&rtc_task_lock);
-- if (rtc_callback)
-- rtc_callback->func(rtc_callback->private_data);
-- spin_unlock(&rtc_task_lock);
--
-- wake_up_interruptible(&rtc_wait);
--
-- kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
--
-- return IRQ_HANDLED;
--}
--
--int rtc_register(rtc_task_t *task)
--{
-- if (task == NULL || task->func == NULL)
-- return -EINVAL;
--
-- spin_lock_irq(&rtc_lock);
-- if (rtc_status == RTC_OPEN) {
-- spin_unlock_irq(&rtc_lock);
-- return -EBUSY;
-- }
--
-- spin_lock(&rtc_task_lock);
-- if (rtc_callback != NULL) {
-- spin_unlock(&rtc_task_lock);
-- spin_unlock_irq(&rtc_task_lock);
-- return -EBUSY;
-- }
--
-- rtc_callback = task;
-- spin_unlock(&rtc_task_lock);
--
-- rtc_status = RTC_OPEN;
--
-- spin_unlock_irq(&rtc_lock);
--
-- return 0;
--}
--
--EXPORT_SYMBOL_GPL(rtc_register);
--
--int rtc_unregister(rtc_task_t *task)
--{
-- spin_lock_irq(&rtc_task_lock);
-- if (task == NULL || rtc_callback != task) {
-- spin_unlock_irq(&rtc_task_lock);
-- return -ENXIO;
-- }
--
-- spin_lock(&rtc_lock);
--
-- rtc1_write(ECMPLREG, 0);
-- rtc1_write(ECMPMREG, 0);
-- rtc1_write(ECMPHREG, 0);
-- rtc1_write(RTCL1LREG, 0);
-- rtc1_write(RTCL1HREG, 0);
--
-- rtc_status = RTC_RELEASE;
--
-- spin_unlock(&rtc_lock);
--
-- rtc_callback = NULL;
--
-- spin_unlock_irq(&rtc_task_lock);
--
-- disable_irq(ELAPSEDTIME_IRQ);
-- disable_irq(RTCLONG1_IRQ);
--
-- return 0;
--}
--
--EXPORT_SYMBOL_GPL(rtc_unregister);
--
--int rtc_control(rtc_task_t *task, unsigned int cmd, unsigned long arg)
--{
-- int retval = 0;
--
-- spin_lock_irq(&rtc_task_lock);
--
-- if (rtc_callback != task)
-- retval = -ENXIO;
-- else
-- rtc_do_ioctl(cmd, arg, FUNCTION_RTC_CONTROL);
--
-- spin_unlock_irq(&rtc_task_lock);
--
-- return retval;
--}
--
--EXPORT_SYMBOL_GPL(rtc_control);
--
--static struct miscdevice rtc_miscdevice = {
-- .minor = RTC_MINOR,
-- .name = rtc_name,
-- .fops = &rtc_fops,
--};
--
--static int rtc_probe(struct device *dev)
--{
-- struct platform_device *pdev;
-- unsigned int irq;
-- int retval;
--
-- pdev = to_platform_device(dev);
-- if (pdev->num_resources != 2)
-- return -EBUSY;
--
-- rtc1_base = ioremap(pdev->resource[0].start, RTC1_SIZE);
-- if (rtc1_base == NULL)
-- return -EBUSY;
--
-- rtc2_base = ioremap(pdev->resource[1].start, RTC2_SIZE);
-- if (rtc2_base == NULL) {
-- iounmap(rtc1_base);
-- rtc1_base = NULL;
-- return -EBUSY;
-- }
--
-- retval = misc_register(&rtc_miscdevice);
-- if (retval < 0) {
-- iounmap(rtc1_base);
-- iounmap(rtc2_base);
-- rtc1_base = NULL;
-- rtc2_base = NULL;
-- return retval;
-- }
--
-- spin_lock_irq(&rtc_lock);
--
-- rtc1_write(ECMPLREG, 0);
-- rtc1_write(ECMPMREG, 0);
-- rtc1_write(ECMPHREG, 0);
-- rtc1_write(RTCL1LREG, 0);
-- rtc1_write(RTCL1HREG, 0);
--
-- rtc_status = RTC_RELEASE;
-- rtc_irq_data = 0;
--
-- spin_unlock_irq(&rtc_lock);
--
-- init_waitqueue_head(&rtc_wait);
--
-- irq = ELAPSEDTIME_IRQ;
-- retval = request_irq(irq, elapsedtime_interrupt, SA_INTERRUPT,
-- "elapsed_time", NULL);
-- if (retval == 0) {
-- irq = RTCLONG1_IRQ;
-- retval = request_irq(irq, rtclong1_interrupt, SA_INTERRUPT,
-- "rtclong1", NULL);
-- }
--
-- if (retval < 0) {
-- printk(KERN_ERR "rtc: IRQ%d is busy\n", irq);
-- if (irq == RTCLONG1_IRQ)
-- free_irq(ELAPSEDTIME_IRQ, NULL);
-- iounmap(rtc1_base);
-- iounmap(rtc2_base);
-- rtc1_base = NULL;
-- rtc2_base = NULL;
-- return retval;
-- }
--
-- disable_irq(ELAPSEDTIME_IRQ);
-- disable_irq(RTCLONG1_IRQ);
--
-- spin_lock_init(&rtc_task_lock);
--
-- printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
--
-- return 0;
--}
--
--static int rtc_remove(struct device *dev)
--{
-- int retval;
--
-- retval = misc_deregister(&rtc_miscdevice);
-- if (retval < 0)
-- return retval;
--
-- free_irq(ELAPSEDTIME_IRQ, NULL);
-- free_irq(RTCLONG1_IRQ, NULL);
-- if (rtc1_base != NULL)
-- iounmap(rtc1_base);
-- if (rtc2_base != NULL)
-- iounmap(rtc2_base);
--
-- return 0;
--}
--
--static struct platform_device *rtc_platform_device;
--
--static struct device_driver rtc_device_driver = {
-- .name = rtc_name,
-- .bus = &platform_bus_type,
-- .probe = rtc_probe,
-- .remove = rtc_remove,
--};
--
--static int __devinit vr41xx_rtc_init(void)
--{
-- int retval;
--
-- switch (current_cpu_data.cputype) {
-- case CPU_VR4111:
-- case CPU_VR4121:
-- rtc_resource[0].start = RTC1_TYPE1_START;
-- rtc_resource[0].end = RTC1_TYPE1_END;
-- rtc_resource[1].start = RTC2_TYPE1_START;
-- rtc_resource[1].end = RTC2_TYPE1_END;
-- break;
-- case CPU_VR4122:
-- case CPU_VR4131:
-- case CPU_VR4133:
-- rtc_resource[0].start = RTC1_TYPE2_START;
-- rtc_resource[0].end = RTC1_TYPE2_END;
-- rtc_resource[1].start = RTC2_TYPE2_START;
-- rtc_resource[1].end = RTC2_TYPE2_END;
-- break;
-- default:
-- return -ENODEV;
-- break;
-- }
--
-- rtc_platform_device = platform_device_register_simple("RTC", -1, rtc_resource, RTC_NUM_RESOURCES);
-- if (IS_ERR(rtc_platform_device))
-- return PTR_ERR(rtc_platform_device);
--
-- retval = driver_register(&rtc_device_driver);
-- if (retval < 0)
-- platform_device_unregister(rtc_platform_device);
--
-- return retval;
--}
--
--static void __devexit vr41xx_rtc_exit(void)
--{
-- driver_unregister(&rtc_device_driver);
--
-- platform_device_unregister(rtc_platform_device);
--}
--
--module_init(vr41xx_rtc_init);
--module_exit(vr41xx_rtc_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/i2c/busses/i2c-au1550.c linux_HEAD/drivers/i2c/busses/i2c-au1550.c
---- linux-2.6.12/drivers/i2c/busses/i2c-au1550.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/i2c/busses/i2c-au1550.c 2005-07-10 12:28:27.000000000 +0200
-@@ -27,7 +27,6 @@
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
--#include <linux/config.h>
- #include <linux/delay.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/i2c/busses/i2c-sibyte.c linux_HEAD/drivers/i2c/busses/i2c-sibyte.c
---- linux-2.6.12/drivers/i2c/busses/i2c-sibyte.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/i2c/busses/i2c-sibyte.c 2005-01-11 18:55:08.000000000 +0100
-@@ -24,8 +24,8 @@
- #include <asm/sibyte/sb1250_smbus.h>
-
- static struct i2c_algo_sibyte_data sibyte_board_data[2] = {
-- { NULL, 0, (void *) (KSEG1+A_SMB_BASE(0)) },
-- { NULL, 1, (void *) (KSEG1+A_SMB_BASE(1)) }
-+ { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) },
-+ { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) }
- };
-
- static struct i2c_adapter sibyte_board_adapter[2] = {
-diff -urpNX dontdiff linux-2.6.12/drivers/ide/Kconfig linux_HEAD/drivers/ide/Kconfig
---- linux-2.6.12/drivers/ide/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/ide/Kconfig 2005-03-21 20:04:08.000000000 +0100
-@@ -771,6 +771,10 @@ config BLK_DEV_IDE_PMAC_BLINK
- This option enables the use of the sleep LED as a hard drive
- activity LED.
-
-+config BLK_DEV_IDE_SWARM
-+ bool "IDE for Sibyte evaluation boards"
-+ depends on SIBYTE_SB1xxx_SOC
-+
- config IDE_ARM
- def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
-
-diff -urpNX dontdiff linux-2.6.12/drivers/ide/Makefile linux_HEAD/drivers/ide/Makefile
---- linux-2.6.12/drivers/ide/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/ide/Makefile 2005-04-08 22:40:57.000000000 +0200
-@@ -49,6 +49,6 @@ obj-$(CONFIG_BLK_DEV_IDECD) += ide-cd.o
- obj-$(CONFIG_BLK_DEV_IDETAPE) += ide-tape.o
- obj-$(CONFIG_BLK_DEV_IDEFLOPPY) += ide-floppy.o
-
--obj-$(CONFIG_BLK_DEV_IDE) += legacy/ arm/
-+obj-$(CONFIG_BLK_DEV_IDE) += legacy/ arm/ mips/
- obj-$(CONFIG_BLK_DEV_HD) += legacy/
- obj-$(CONFIG_ETRAX_IDE) += cris/
-diff -urpNX dontdiff linux-2.6.12/drivers/ide/ide.c linux_HEAD/drivers/ide/ide.c
---- linux-2.6.12/drivers/ide/ide.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/ide/ide.c 2005-07-01 12:09:38.000000000 +0200
-@@ -1843,6 +1843,12 @@ static void __init probe_for_hwifs (void
- q40ide_init();
- }
- #endif /* CONFIG_BLK_DEV_Q40IDE */
-+#ifdef CONFIG_BLK_DEV_IDE_SWARM
-+ {
-+ extern void swarm_ide_probe(void);
-+ swarm_ide_probe();
-+ }
-+#endif /* CONFIG_BLK_DEV_IDE_SWARM */
- #ifdef CONFIG_BLK_DEV_BUDDHA
- {
- extern void buddha_init(void);
-diff -urpNX dontdiff linux-2.6.12/drivers/ide/mips/Makefile linux_HEAD/drivers/ide/mips/Makefile
---- linux-2.6.12/drivers/ide/mips/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/ide/mips/Makefile 2004-09-21 13:10:22.000000000 +0200
-@@ -0,0 +1,3 @@
-+obj-$(CONFIG_BLK_DEV_IDE_SWARM) += swarm.o
-+
-+EXTRA_CFLAGS := -I../
-diff -urpNX dontdiff linux-2.6.12/drivers/ide/mips/swarm.c linux_HEAD/drivers/ide/mips/swarm.c
---- linux-2.6.12/drivers/ide/mips/swarm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/ide/mips/swarm.c 2005-02-24 00:13:18.000000000 +0100
-@@ -0,0 +1,123 @@
-+/*
-+ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
-+ * Copyright (C) 2004 MontaVista Software Inc.
-+ * Author: Manish Lachwani, mlachwani at mvista.com
-+ * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved.
-+ * Author: Maciej W. Rozycki <macro at mips.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+ * Derived loosely from ide-pmac.c, so:
-+ * Copyright (C) 1998 Paul Mackerras.
-+ * Copyright (C) 1995-1998 Mark Lord
-+ */
-+
-+/*
-+ * Boards with SiByte processors so far have supported IDE devices via
-+ * the Generic Bus, PCI bus, and built-in PCMCIA interface. In all
-+ * cases, byte-swapping must be avoided for these devices (whereas
-+ * other PCI devices, for example, will require swapping). Any
-+ * SiByte-targetted kernel including IDE support will include this
-+ * file. Probing of a Generic Bus for an IDE device is controlled by
-+ * the definition of "SIBYTE_HAVE_IDE", which is provided by
-+ * <asm/sibyte/board.h> for Broadcom boards.
-+ */
-+
-+#include <linux/ide.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+#include <asm/io.h>
-+
-+#include <asm/sibyte/board.h>
-+#include <asm/sibyte/sb1250_genbus.h>
-+#include <asm/sibyte/sb1250_regs.h>
-+
-+#define DRV_NAME "ide-swarm"
-+
-+static struct resource swarm_ide_resource = {
-+ .name = "SWARM GenBus IDE",
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+/*
-+ * swarm_ide_probe - if the board header indicates the existence of
-+ * Generic Bus IDE, allocate a HWIF for it.
-+ */
-+void __init swarm_ide_probe(void)
-+{
-+ ide_hwif_t *hwif;
-+ u8 __iomem *base;
-+ phys_t offset, size;
-+ int i;
-+
-+ if (!SIBYTE_HAVE_IDE)
-+ return;
-+
-+ /* Find an empty slot. */
-+ for (i = 0; i < MAX_HWIFS; i++)
-+ if (!ide_hwifs[i].io_ports[IDE_DATA_OFFSET])
-+ break;
-+ if (i >= MAX_HWIFS) {
-+ printk(KERN_ERR DRV_NAME ": no free slot for interface\n");
-+ return;
-+ }
-+ hwif = ide_hwifs + i;
-+
-+ base = ioremap(A_IO_EXT_BASE, 0x800);
-+ offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
-+ size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
-+ iounmap(base);
-+
-+ offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE;
-+ size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE;
-+ if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) {
-+ printk(KERN_INFO DRV_NAME
-+ ": IDE interface at GenBus disabled\n");
-+ return;
-+ }
-+
-+ printk(KERN_INFO DRV_NAME ": IDE interface at GenBus slot %i\n",
-+ IDE_CS);
-+
-+ swarm_ide_resource.start = offset;
-+ swarm_ide_resource.end = offset + size - 1;
-+ if (request_resource(&iomem_resource, &swarm_ide_resource)) {
-+ printk(KERN_ERR DRV_NAME
-+ ": can't request I/O memory resource\n");
-+ return;
-+ }
-+
-+ base = ioremap(offset, size);
-+
-+ /* Setup MMIO ops. */
-+ default_hwif_mmiops(hwif);
-+ /* Prevent resource map manipulation. */
-+ hwif->mmio = 2;
-+ hwif->noprobe = 0;
-+
-+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
-+ hwif->hw.io_ports[i] =
-+ (unsigned long)(base + ((0x1f0 + i) << 5));
-+ hwif->hw.io_ports[IDE_CONTROL_OFFSET] =
-+ (unsigned long)(base + (0x3f6 << 5));
-+ hwif->hw.irq = K_INT_GB_IDE;
-+
-+ memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
-+ hwif->irq = hwif->hw.irq;
-+}
-diff -urpNX dontdiff linux-2.6.12/drivers/media/video/Kconfig linux_HEAD/drivers/media/video/Kconfig
---- linux-2.6.12/drivers/media/video/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/media/video/Kconfig 2005-07-01 12:09:44.000000000 +0200
-@@ -82,6 +82,14 @@ config VIDEO_W9966
- Check out <file:Documentation/video4linux/w9966.txt> for more
- information.
-
-+config VIDEO_SWARM_7114H
-+ tristate "Philips SAA7114H for SiByte BCM91250A"
-+ depends on SIBYTE_SWARM && VIDEO_DEV && I2C_ALGO_SIBYTE
-+ help
-+ Say Y or M to build the video4linux driver for the Philips
-+ SAA7114H video decoder on Broadcom SWARM board (BCM91250A).
-+ The decoder chip is on the BCM1250's "E2" 8-bit FIFO port.
-+
- config VIDEO_CPIA
- tristate "CPiA Video For Linux"
- depends on VIDEO_DEV
-diff -urpNX dontdiff linux-2.6.12/drivers/media/video/Makefile linux_HEAD/drivers/media/video/Makefile
---- linux-2.6.12/drivers/media/video/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/media/video/Makefile 2005-03-21 20:04:18.000000000 +0100
-@@ -51,6 +51,9 @@ obj-$(CONFIG_VIDEO_BUF_DVB) += video-buf
- obj-$(CONFIG_VIDEO_BTCX) += btcx-risc.o
- obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
-
-+obj-$(CONFIG_VIDEO_SWARM_7114H) += swarm_saa7114h.o
-+obj-$(CONFIG_TUNER_3036) += tuner-3036.o
-+
- obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o
-
- EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core
-diff -urpNX dontdiff linux-2.6.12/drivers/media/video/swarm_saa7114h.c linux_HEAD/drivers/media/video/swarm_saa7114h.c
---- linux-2.6.12/drivers/media/video/swarm_saa7114h.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/media/video/swarm_saa7114h.c 2005-02-25 14:59:27.000000000 +0100
-@@ -0,0 +1,1691 @@
-+/*
-+ saa7114h - Philips SAA7114H video decoder driver
-+
-+ Copyright (C) 2001,2002,2003 Broadcom Corporation
-+
-+ From saa7111.c:
-+ Copyright (C) 1998 Dave Perks <dperks at ibm.net>
-+ From cpia.c:
-+ (C) Copyright 1999-2000 Peter Pregler
-+ (C) Copyright 1999-2000 Scott J. Bertin
-+ (C) Copyright 1999-2000 Johannes Erdfelt <johannes at erdfelt.com>
-+
-+ This program is free software; you can redistribute it and/or modify
-+ it under the terms of the GNU General Public License as published by
-+ the Free Software Foundation; either version 2 of the License, or
-+ (at your option) any later version.
-+
-+ This program is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ GNU General Public License for more details.
-+
-+ You should have received a copy of the GNU General Public License
-+ along with this program; if not, write to the Free Software
-+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+/*
-+ * Important note: this driver is reasonably functional, and has been
-+ * tested with the "camserv" v4l application. But it primarily a
-+ * proof-of-concept, and example for setting up FIFO-mode.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/errno.h>
-+#include <linux/ctype.h>
-+#include <linux/fs.h>
-+#include <linux/vmalloc.h>
-+#include <linux/kernel.h>
-+#include <linux/major.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/pci.h>
-+#include <linux/signal.h>
-+#include <linux/proc_fs.h>
-+#include <asm/io.h>
-+#include <asm/pgtable.h>
-+#include <asm/page.h>
-+#include <linux/sched.h>
-+#include <asm/segment.h>
-+#include <linux/types.h>
-+#include <linux/wrapper.h>
-+#include <linux/smp_lock.h>
-+#include <asm/hardirq.h>
-+
-+#include <linux/i2c.h>
-+#include <linux/videodev.h>
-+#include <linux/version.h>
-+#include <asm/uaccess.h>
-+
-+#include <linux/i2c-algo-sibyte.h>
-+
-+#include <asm/sibyte/sb1250_regs.h>
-+#include <asm/sibyte/sb1250_int.h>
-+#include <asm/sibyte/sb1250_mac.h>
-+#include <asm/sibyte/sb1250_dma.h>
-+
-+#define SAA_BRIGHTNESS 0x0a
-+#define SAA_CONTRAST 0x0b
-+#define SAA_SATURATION 0x0c
-+#define SAA_HUE 0x0d
-+
-+#define DECODER_STATUS 0x1f
-+#define SLICER_STATUS_0 0x60
-+#define SLICER_STATUS_1 0x61
-+#define SLICER_STATUS_2 0x62
-+#define SCALER_STATUS 0x8f
-+
-+#define NUM_FRAME 2
-+#define MAX_HORIZ 720
-+#define MAX_VERT 480
-+#define MIN_HORIZ 180
-+#define MIN_VERT 120
-+#define MAX_PER_PIXEL 3
-+#define MAX_FRAME_SIZE (MAX_HORIZ*MAX_VERT*MAX_PER_PIXEL)
-+#define MAX_MMAP_SIZE (PAGE_ALIGN(MAX_FRAME_SIZE*NUM_FRAME))
-+#define RAW_PER_PIXEL 2
-+#define RAW_LINE_PAD 8
-+#define RAW_LINE_SIZE (((MAX_HORIZ*RAW_PER_PIXEL)+RAW_LINE_PAD+0x1f) & ~0x1f)
-+#define RAW_FRAME_SIZE (RAW_LINE_SIZE*MAX_VERT)
-+
-+#define NUM_DESCR 64
-+#define INTR_PKT_CNT 8
-+
-+/* Extensions to videodev.h IOCTL definitions */
-+#define VIDIOREADREG _IOR('v', 50, int)
-+#define VIDIOWRITEREG _IOW('v', 50, int)
-+#define VIDIOGRABFRAME _IOR('v', 51, int)
-+#define VIDIOSHOWEAV _IOR('v', 52, int)
-+
-+#define IF_NAME "saa7114h"
-+
-+#define MAC2_CSR(r) (KSEG1 + A_MAC_REGISTER(2, r))
-+#define MAC2_DMARX0_CSR(r) (KSEG1 + A_MAC_DMA_REGISTER(2, DMA_RX, 0, r))
-+
-+/* Options */
-+#define DMA_DEINTERLACE 1
-+#define LAZY_READ 1
-+#define NULL_DMA 0
-+
-+/* Debug filters */
-+#define DBG_NULL 0x0000
-+#define DBG_IO 0x0001
-+#define DBG_DESCR 0x0002
-+#define DBG_INTR 0x0004
-+#define DBG_CONVERT 0x0008
-+#define DBG_FRAMING 0x0010
-+#define DBG_REGISTER 0x0020
-+#define DBG_CALL 0x0040
-+#define DBG_FRAMING_LOUD 0x0080
-+
-+/* XXXKW make this settable through /proc... */
-+#define DEBUG_LVL (DBG_NULL)
-+
-+#if DEBUG_LVL
-+#define DBG(l, p) do { if (DEBUG_LVL & l) p; } while (0)
-+#else
-+#define DBG(l, p)
-+#endif
-+
-+/* ----------------------------------------------------------------------- */
-+
-+enum {
-+ FRAME_READY, /* Ready to grab into */
-+ FRAME_GRABBING, /* In the process of being grabbed into */
-+ FRAME_DONE, /* Finished grabbing, but not been synced yet */
-+ FRAME_UNUSED, /* Unused (belongs to driver, but can't be used) */
-+};
-+
-+struct saa_frame {
-+ uint8_t *data;
-+ uint8_t *pos;
-+ int width;
-+ int height;
-+ uint32_t size;
-+ volatile int state;
-+ wait_queue_head_t read_wait;
-+};
-+
-+typedef struct fifo_descr_s {
-+ uint64_t descr_a;
-+ uint64_t descr_b;
-+} fifo_descr_t;
-+
-+typedef unsigned long paddr_t;
-+
-+typedef struct fifo_s {
-+ unsigned ringsz;
-+ fifo_descr_t *descrtab;
-+ fifo_descr_t *descrtab_end;
-+ fifo_descr_t *next_descr;
-+ paddr_t descrtab_phys;
-+ void *dma_buf; /* DMA buffer */
-+} fifo_t;
-+
-+struct saa7114h {
-+ struct i2c_client *client;
-+ struct video_device *vd;
-+ struct video_window vw;
-+ struct video_picture vp;
-+ uint8_t reg[256];
-+
-+ fifo_t ff;
-+ void *frame_buf; /* hold frames for the client */
-+ struct saa_frame frame[NUM_FRAME]; /* point into frame_buf */
-+ int hwframe;
-+ int swframe;
-+
-+ uint16_t depth;
-+ uint16_t palette;
-+ uint8_t bright;
-+ uint8_t contrast;
-+ uint8_t hue;
-+ uint8_t sat;
-+
-+ struct proc_dir_entry *proc_entry;
-+ struct semaphore param_lock;
-+ struct semaphore busy_lock;
-+
-+ int dma_enable;
-+ int opened;
-+ int irq;
-+ int interlaced;
-+};
-+
-+static int saa7114h_probe(struct i2c_adapter *adap);
-+static int saa7114h_detach(struct i2c_client *device);
-+
-+struct i2c_driver i2c_driver_saa7114h =
-+{
-+ name: "saa7114h", /* name */
-+ id: I2C_DRIVERID_SAA7114H, /* ID */
-+ flags: I2C_DF_NOTIFY, /* XXXKW do I care? */
-+ attach_adapter: saa7114h_probe,
-+ detach_client: saa7114h_detach
-+};
-+
-+/* -----------------------------------------------------------------------
-+ * VM assist for MMAPed space
-+ * ----------------------------------------------------------------------- */
-+
-+/* Given PGD from the address space's page table, return the kernel
-+ * virtual mapping of the physical memory mapped at ADR.
-+ */
-+static inline unsigned long uvirt_to_kva(pgd_t *pgd, unsigned long adr)
-+{
-+ unsigned long ret = 0UL;
-+ pmd_t *pmd;
-+ pte_t *ptep, pte;
-+
-+ if (!pgd_none(*pgd)) {
-+ pmd = pmd_offset(pgd, adr);
-+ if (!pmd_none(*pmd)) {
-+ ptep = pte_offset(pmd, adr);
-+ pte = *ptep;
-+ if (pte_present(pte)) {
-+ ret = (unsigned long) page_address(pte_page(pte));
-+ ret |= (adr & (PAGE_SIZE-1));
-+ }
-+ }
-+ }
-+ return ret;
-+}
-+
-+/* Here we want the physical address of the memory.
-+ * This is used when initializing the contents of the
-+ * area and marking the pages as reserved.
-+ */
-+static inline unsigned long kvirt_to_pa(unsigned long adr)
-+{
-+ unsigned long va, kva, ret;
-+
-+ va = VMALLOC_VMADDR(adr);
-+ kva = uvirt_to_kva(pgd_offset_k(va), va);
-+ ret = __pa(kva);
-+ return ret;
-+}
-+
-+static void *rvmalloc(unsigned long size)
-+{
-+ void *mem;
-+ unsigned long adr, page;
-+
-+ /* Round it off to PAGE_SIZE */
-+ size += (PAGE_SIZE - 1);
-+ size &= ~(PAGE_SIZE - 1);
-+
-+ mem = vmalloc_32(size);
-+ if (!mem)
-+ return NULL;
-+
-+ memset(mem, 0, size); /* Clear the ram out, no junk to the user */
-+ adr = (unsigned long) mem;
-+ while (size > 0) {
-+ page = kvirt_to_pa(adr);
-+ mem_map_reserve(virt_to_page(__va(page)));
-+ adr += PAGE_SIZE;
-+ if (size > PAGE_SIZE)
-+ size -= PAGE_SIZE;
-+ else
-+ size = 0;
-+ }
-+
-+ return mem;
-+}
-+
-+static void rvfree(void *mem, unsigned long size)
-+{
-+ unsigned long adr, page;
-+
-+ if (!mem)
-+ return;
-+
-+ size += (PAGE_SIZE - 1);
-+ size &= ~(PAGE_SIZE - 1);
-+
-+ adr = (unsigned long) mem;
-+ while (size > 0) {
-+ page = kvirt_to_pa(adr);
-+ mem_map_unreserve(virt_to_page(__va(page)));
-+ adr += PAGE_SIZE;
-+ if (size > PAGE_SIZE)
-+ size -= PAGE_SIZE;
-+ else
-+ size = 0;
-+ }
-+ vfree(mem);
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * Control interface (i2c)
-+ * ----------------------------------------------------------------------- */
-+
-+static int saa7114h_reg_read(struct saa7114h *dev, unsigned char subaddr)
-+{
-+ return i2c_smbus_read_byte_data(dev->client, subaddr);
-+}
-+
-+static int saa7114h_reg_write(struct saa7114h *dev, unsigned char subaddr, int data)
-+{
-+ return i2c_smbus_write_byte_data(dev->client, subaddr, data & 0xff);
-+}
-+
-+static int saa7114h_reg_init(struct saa7114h *dev, unsigned const char *data, unsigned int len)
-+{
-+ int rc = 0;
-+ int val;
-+
-+ while (len && !rc) {
-+ dev->reg[data[0]] = data[1];
-+ rc = saa7114h_reg_write(dev, data[0], data[1]);
-+ if (!rc && (data[0] != 0)) {
-+ val = saa7114h_reg_read(dev, data[0]);
-+ if ((val < 0) || (val != data[1])) {
-+ printk(KERN_ERR
-+ IF_NAME ": init readback mismatch reg %02x = %02x (should be %02x)\n",
-+ data[0], val, data[1]);
-+ }
-+ }
-+ len -= 2;
-+ data += 2;
-+ }
-+ return rc;
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * /proc interface
-+ * ----------------------------------------------------------------------- */
-+
-+#ifdef CONFIG_PROC_FS
-+static struct proc_dir_entry *saa7114h_proc_root=NULL;
-+
-+static int decoder_read_proc(char *page, char **start, off_t off,
-+ int count, int *eof, void *data)
-+{
-+ char *out = page;
-+ int len, status;
-+ struct saa7114h *decoder = data;
-+
-+ out += sprintf(out, " SWARM saa7114h\n------------------\n");
-+ status = saa7114h_reg_read(decoder, DECODER_STATUS);
-+ out += sprintf(out, " Decoder status = %02x\n", status);
-+ if (status & 0x80)
-+ out += sprintf(out, " interlaced\n");
-+ if (status & 0x40)
-+ out += sprintf(out, " not locked\n");
-+ if (status & 0x02)
-+ out += sprintf(out, " Macrovision detected\n");
-+ if (status & 0x01)
-+ out += sprintf(out, " color\n");
-+ out += sprintf(out, " Brightness = %02x\n", decoder->bright);
-+ out += sprintf(out, " Contrast = %02x\n", decoder->contrast);
-+ out += sprintf(out, " Saturation = %02x\n", decoder->sat);
-+ out += sprintf(out, " Hue = %02x\n\n", decoder->hue);
-+
-+ out += sprintf(out, " Scaler status = %02x\n",
-+ (int)saa7114h_reg_read(decoder, SCALER_STATUS));
-+
-+ len = out - page;
-+ len -= off;
-+ if (len < count) {
-+ *eof = 1;
-+ if (len <= 0) return 0;
-+ } else
-+ len = count;
-+
-+ *start = page + off;
-+ return len;
-+}
-+
-+static int decoder_write_proc(struct file *file, const char *buffer,
-+ unsigned long count, void *data)
-+{
-+ struct saa7114h *d = data;
-+ int retval;
-+ unsigned int cmd, reg, reg_val;
-+
-+ if (down_interruptible(&d->param_lock))
-+ return -ERESTARTSYS;
-+
-+#define VALUE \
-+ ({ \
-+ char *_p; \
-+ unsigned long int _ret; \
-+ while (count && isspace(*buffer)) { \
-+ buffer++; \
-+ count--; \
-+ } \
-+ _ret = simple_strtoul(buffer, &_p, 16); \
-+ if (_p == buffer) \
-+ retval = -EINVAL; \
-+ else { \
-+ count -= _p - buffer; \
-+ buffer = _p; \
-+ } \
-+ _ret; \
-+ })
-+
-+ retval = 0;
-+ while (count && !retval) {
-+ cmd = VALUE;
-+ if (retval)
-+ break;
-+ switch (cmd) {
-+ case 1:
-+ reg = VALUE;
-+ if (retval)
-+ break;
-+ reg_val = VALUE;
-+ if (retval)
-+ break;
-+ printk(IF_NAME ": write reg %x <- %x\n", reg, reg_val);
-+ if (saa7114h_reg_write(d, reg, reg_val) == -1)
-+ retval = -EINVAL;
-+ break;
-+ case 2:
-+ reg = VALUE;
-+ if (retval)
-+ break;
-+ reg_val = saa7114h_reg_read(d, reg);
-+ if (reg_val == -1)
-+ retval = -EINVAL;
-+ else
-+ printk(IF_NAME ": read reg %x -> %x\n", reg, reg_val);
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+ up(&d->param_lock);
-+
-+ return retval;
-+}
-+
-+static void create_proc_decoder(struct saa7114h *decoder)
-+{
-+ char name[8];
-+ struct proc_dir_entry *ent;
-+
-+ if (!saa7114h_proc_root || !decoder)
-+ return;
-+
-+ sprintf(name, "video%d", decoder->vd->minor);
-+
-+ ent = create_proc_entry(name, S_IFREG|S_IRUGO|S_IWUSR, saa7114h_proc_root);
-+ if (!ent) {
-+ printk(KERN_INFO IF_NAME ": Unable to initialize /proc/saa7114h/%s\n", name);
-+ return;
-+ }
-+
-+ ent->data = decoder;
-+ ent->read_proc = decoder_read_proc;
-+ ent->write_proc = decoder_write_proc;
-+ ent->size = 3626; /* XXXKW ??? */
-+ decoder->proc_entry = ent;
-+}
-+
-+static void destroy_proc_decoder(struct saa7114h *decoder)
-+{
-+ char name[7];
-+
-+ if (!decoder || !decoder->proc_entry)
-+ return;
-+
-+ sprintf(name, "video%d", decoder->vd->minor);
-+ remove_proc_entry(name, saa7114h_proc_root);
-+ decoder->proc_entry = NULL;
-+}
-+
-+static void proc_saa7114h_create(void)
-+{
-+ saa7114h_proc_root = create_proc_entry("saa7114h", S_IFDIR, 0);
-+
-+ if (saa7114h_proc_root)
-+ saa7114h_proc_root->owner = THIS_MODULE;
-+ else
-+ printk(KERN_INFO IF_NAME ": Unable to initialize /proc/saa7114h\n");
-+}
-+
-+static void proc_saa7114h_destroy(void)
-+{
-+ remove_proc_entry("saa7114h", 0);
-+}
-+#endif /* CONFIG_PROC_FS */
-+
-+
-+/* -----------------------------------------------------------------------
-+ * Initialization
-+ * ----------------------------------------------------------------------- */
-+
-+static int dma_setup(struct saa7114h *d)
-+{
-+ int i;
-+ void *curbuf;
-+
-+ /* Reset the port */
-+ __raw_writeq(M_MAC_PORT_RESET, MAC2_CSR(R_MAC_ENABLE));
-+ __raw_readq(MAC2_CSR(R_MAC_ENABLE));
-+
-+ /* Zero everything out, disable filters */
-+ __raw_writeq(0, MAC2_CSR(R_MAC_TXD_CTL));
-+ __raw_writeq(M_MAC_ALLPKT_EN, MAC2_CSR(R_MAC_ADFILTER_CFG));
-+ __raw_writeq(V_MAC_RX_RD_THRSH(4) | V_MAC_RX_RL_THRSH(4),
-+ MAC2_CSR(R_MAC_THRSH_CFG));
-+ for (i=0; i<MAC_CHMAP_COUNT; i++) {
-+ __raw_writeq(0, MAC2_CSR(R_MAC_CHLO0_BASE+(i*8)));
-+ __raw_writeq(0, MAC2_CSR(R_MAC_CHUP0_BASE+(i*8)));
-+ }
-+ for (i=0; i<MAC_HASH_COUNT; i++) {
-+ __raw_writeq(0, MAC2_CSR(R_MAC_HASH_BASE+(i*8)));
-+ }
-+ for (i=0; i<MAC_ADDR_COUNT; i++) {
-+ __raw_writeq(0, MAC2_CSR(R_MAC_ADDR_BASE+(i*8)));
-+ }
-+
-+ __raw_writeq(V_MAC_MAX_FRAMESZ(16*1024) | V_MAC_MIN_FRAMESZ(0),
-+ MAC2_CSR(R_MAC_FRAMECFG));
-+
-+ /* Select bypass mode */
-+ __raw_writeq((M_MAC_BYPASS_SEL | V_MAC_BYPASS_CFG(K_MAC_BYPASS_EOP) |
-+ M_MAC_FC_SEL | M_MAC_SS_EN | V_MAC_SPEED_SEL_1000MBPS),
-+ MAC2_CSR(R_MAC_CFG));
-+
-+ /* Set up the descriptor table */
-+ d->ff.descrtab = kmalloc(NUM_DESCR * sizeof(fifo_descr_t), GFP_KERNEL);
-+ d->ff.descrtab_phys = __pa(d->ff.descrtab);
-+ d->ff.descrtab_end = d->ff.descrtab + NUM_DESCR;
-+ d->ff.next_descr = d->ff.descrtab;
-+ d->ff.ringsz = NUM_DESCR;
-+#if 0
-+ /* XXXKW this won't work because the physical may not be
-+ contiguous; how do I handle a bigger alloc then? */
-+ d->ff.dma_buf = rvmalloc(RAW_LINE_SIZE*NUM_DESCR);
-+ printk(KERN_DEBUG IF_NAME ": DMA buffer allocated (%p)\n",
-+ d->ff.dma_buf);
-+#else
-+ d->ff.dma_buf = kmalloc(RAW_LINE_SIZE*NUM_DESCR, GFP_KERNEL);
-+#endif
-+ if (!d->ff.dma_buf) {
-+ printk(KERN_ERR IF_NAME ": couldn't allocate DMA buffer\n");
-+ return -ENOMEM;
-+ }
-+ memset(d->ff.dma_buf, 0, RAW_LINE_SIZE*NUM_DESCR);
-+
-+ for (i=0, curbuf=d->ff.dma_buf; i<d->ff.ringsz; i++, curbuf+=RAW_LINE_SIZE) {
-+ d->ff.descrtab[i].descr_a = (__pa(curbuf) |
-+ V_DMA_DSCRA_A_SIZE(RAW_LINE_SIZE >> 5));
-+ d->ff.descrtab[i].descr_b = 0;
-+ }
-+
-+ __raw_writeq(V_DMA_INT_PKTCNT(INTR_PKT_CNT) | M_DMA_EOP_INT_EN |
-+ V_DMA_RINGSZ(d->ff.ringsz) | M_DMA_TDX_EN,
-+ MAC2_DMARX0_CSR(R_MAC_DMA_CONFIG0));
-+ __raw_writeq(M_DMA_L2CA, MAC2_DMARX0_CSR(R_MAC_DMA_CONFIG1));
-+ __raw_writeq(d->ff.descrtab_phys, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_BASE));
-+
-+ /* Enable interrupts and DMA */
-+ __raw_writeq(M_MAC_INT_EOP_COUNT<<S_MAC_RX_CH0, MAC2_CSR(R_MAC_INT_MASK));
-+ __raw_writeq(M_MAC_RXDMA_EN0 | M_MAC_BYP_RX_ENABLE, MAC2_CSR(R_MAC_ENABLE));
-+
-+ return 0;
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * v4linux helpers - color conversion, etc (taken from cpia.c)
-+ * ----------------------------------------------------------------------- */
-+
-+#define LIMIT(x) ((((x)>0xffffff)?0xff0000:(((x)<=0xffff)?0:(x)&0xff0000))>>16)
-+
-+static void yuvconvert_inplace(uint8_t *data, uint32_t in_uyvy, int out_fmt, int mmap)
-+{
-+ int y, u, v, r, g, b, y1;
-+ uint8_t *src, *dst;
-+
-+ if (out_fmt == VIDEO_PALETTE_RGB24) {
-+ src = (uint8_t *)((int)data + in_uyvy);
-+ dst = (uint8_t *)((int)data + in_uyvy + (in_uyvy >> 1));
-+ DBG(DBG_CONVERT, printk(KERN_DEBUG "inplace: %p %p %p\n", data, src, dst));
-+ while (src > data) {
-+ if ((int)(src-data) < 4)
-+ break;
-+ //printk("freaky %p %p\n", src, data);
-+ y1 = (*(--src) - 16) * 76310;
-+ v = *(--src) - 128;
-+ y = (*(--src) - 16) * 76310;
-+ u = *(--src) - 128;
-+ r = 104635 * v;
-+ g = -25690 * u + -53294 * v;
-+ b = 132278 * u;
-+ /* XXXKW what on earth is up with mmap? */
-+ if (mmap) {
-+ *(--dst) = LIMIT(r+y1);
-+ *(--dst) = LIMIT(g+y1);
-+ *(--dst) = LIMIT(b+y1);
-+ *(--dst) = LIMIT(r+y);
-+ *(--dst) = LIMIT(g+y);
-+ *(--dst) = LIMIT(b+y);
-+ } else {
-+ *(--dst) = LIMIT(b+y1);
-+ *(--dst) = LIMIT(g+y1);
-+ *(--dst) = LIMIT(r+y1);
-+ *(--dst) = LIMIT(b+y);
-+ *(--dst) = LIMIT(g+y);
-+ *(--dst) = LIMIT(r+y);
-+ }
-+ }
-+ }
-+}
-+
-+static int saa7114h_get_cparams(struct saa7114h *decoder)
-+{
-+ /* XXX check for error code */
-+ decoder->bright = saa7114h_reg_read(decoder, SAA_BRIGHTNESS);
-+ decoder->contrast = saa7114h_reg_read(decoder, SAA_CONTRAST);
-+ decoder->sat = saa7114h_reg_read(decoder, SAA_SATURATION);
-+ decoder->hue = saa7114h_reg_read(decoder, SAA_HUE);
-+
-+ decoder->vp.brightness = (uint16_t)decoder->bright << 8;
-+ decoder->vp.contrast = (uint16_t)decoder->contrast << 9;
-+ decoder->vp.colour = decoder->sat << 9;
-+ decoder->vp.hue = ((int16_t)decoder->hue + 128) << 8;
-+ return 0;
-+}
-+
-+static int saa7114h_set_cparams(struct saa7114h *decoder)
-+{
-+ decoder->bright = decoder->vp.brightness >> 8;
-+ decoder->contrast = decoder->vp.contrast >> 9;
-+ decoder->sat = decoder->vp.colour >> 9;
-+ decoder->hue = (uint8_t)((int8_t)(decoder->vp.hue >> 8) - 128);
-+
-+ return (saa7114h_reg_write(decoder, SAA_BRIGHTNESS, decoder->bright) ||
-+ saa7114h_reg_write(decoder, SAA_CONTRAST, decoder->contrast) ||
-+ saa7114h_reg_write(decoder, SAA_SATURATION, decoder->sat) ||
-+ saa7114h_reg_write(decoder, SAA_HUE, decoder->hue));
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * Custom IOCTL support
-+ * ----------------------------------------------------------------------- */
-+
-+unsigned char eav[625][2];
-+static int grab_frame(struct saa7114h *d, void *user_buf, int print_eav)
-+{
-+ int cur_idx = 0;
-+ int to_go = 625;
-+ int delta;
-+ int i, len, eav_val, sav_val;
-+ int started = 0;
-+ uint8_t *buf;
-+ fifo_descr_t *cur_d;
-+ int swptr = d->ff.next_descr - d->ff.descrtab;
-+ int hwptr;
-+
-+ DBG(DBG_CALL, printk(IF_NAME ": grabbing frame\n"));
-+
-+ /* Check for Macrovision -- if it's on, DMA won't happen */
-+ if (saa7114h_reg_read(d, DECODER_STATUS) & 0x2)
-+ return -EACCES;
-+
-+ __raw_writeq(d->ff.ringsz, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ do {
-+ hwptr = (unsigned) (((__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_CUR_DSCRADDR)) &
-+ M_DMA_CURDSCR_ADDR) -
-+ d->ff.descrtab_phys) /
-+ sizeof(fifo_descr_t));
-+ delta = (hwptr + d->ff.ringsz - swptr) % d->ff.ringsz;
-+
-+ if (delta == 0) {
-+#if 0
-+ uint64_t val = __raw_readq(MAC2_DMARX0_CSR(R_MAC_STATUS));
-+ printk("mac status: %08x%08x\n",
-+ (u32)(val >> 32), (u32)(val&0xffffffff));
-+#endif
-+ }
-+
-+ for (i=0; i<delta; i++) {
-+ cur_d = d->ff.next_descr;
-+ if (++d->ff.next_descr == d->ff.descrtab_end)
-+ d->ff.next_descr = d->ff.descrtab;
-+
-+ if (!(cur_d->descr_a & M_DMA_ETHRX_SOP)) {
-+ printk("bogus RX\n");
-+ continue;
-+ }
-+ cur_d->descr_a &= ~M_DMA_ETHRX_SOP;
-+ len = G_DMA_DSCRB_PKT_SIZE(cur_d->descr_b);
-+ buf = (uint8_t *)__va(cur_d->descr_a & M_DMA_DSCRA_A_ADDR);
-+ if (len != (d->vw.width*RAW_PER_PIXEL)+RAW_LINE_PAD) {
-+ printk("funny size %d\n", len);
-+ continue;
-+ }
-+ eav_val = buf[1];
-+ sav_val = buf[5];
-+ if (eav_val == 0xf1) { /* end of field 2, V-blank */
-+ if (started) {
-+ started = 0;
-+ delta = to_go = 0;
-+ /* just let DMA finish in background */
-+ } else {
-+ started = 1;
-+ }
-+ }
-+ if (started) {
-+ eav[cur_idx][0] = eav_val;
-+ eav[cur_idx++][1] = sav_val;
-+ if (copy_to_user(user_buf, &buf[6], 1440))
-+ return -EFAULT;
-+ user_buf += 1440;
-+ }
-+ }
-+ swptr = hwptr;
-+ if (delta) {
-+ if (started)
-+ to_go -= delta;
-+ if (delta > to_go)
-+ delta = to_go;
-+ __raw_writeq(delta, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ }
-+ } while (to_go);
-+
-+ if (print_eav) {
-+ for (i=0; i<cur_idx; i++) {
-+ printk("%3d: %02x | %02x\n", i, eav[i][0], eav[i][1]);
-+ }
-+ }
-+
-+ return cur_idx;
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * Interrupt handler
-+ * ----------------------------------------------------------------------- */
-+
-+unsigned long int_count = 0;
-+
-+static void saa7114h_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+ struct saa7114h *d = dev_id;
-+ uint64_t status_val;
-+ fifo_descr_t *cur_d;
-+ int i, delta, len;
-+ uint8_t *buf, eav_val;
-+ int swptr = d->ff.next_descr - d->ff.descrtab;
-+ int hwptr;
-+
-+ status_val = __raw_readq(MAC2_CSR(R_MAC_STATUS));
-+
-+ /* Process finished decsriptors */
-+ hwptr = (unsigned) (((__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_CUR_DSCRADDR)) &
-+ M_DMA_CURDSCR_ADDR) - d->ff.descrtab_phys) /
-+ sizeof(fifo_descr_t));
-+ delta = (hwptr + d->ff.ringsz - swptr) % d->ff.ringsz;
-+ if (!delta) {
-+ if (status_val & M_MAC_INT_EOP_SEEN<<S_MAC_RX_CH0) {
-+ /* Must have wrapped since the last interrupt */
-+ delta = d->ff.ringsz;
-+ } else {
-+ /* XXXKW why would this happen? */
-+ return;
-+ }
-+ }
-+
-+ for (i=0; i<delta; i++) {
-+ cur_d = d->ff.next_descr;
-+ if (++d->ff.next_descr == d->ff.descrtab_end)
-+ d->ff.next_descr = d->ff.descrtab;
-+
-+ if (!(cur_d->descr_a & M_DMA_ETHRX_SOP)) {
-+ printk(KERN_DEBUG "bogus RX\n");
-+ continue;
-+ }
-+ cur_d->descr_a &= ~M_DMA_ETHRX_SOP;
-+ if (!d->dma_enable)
-+ continue;
-+
-+ len = G_DMA_DSCRB_PKT_SIZE(cur_d->descr_b);
-+ buf = (uint8_t *)__va(cur_d->descr_a & M_DMA_DSCRA_A_ADDR);
-+ if (len != (d->vw.width*RAW_PER_PIXEL)+RAW_LINE_PAD) {
-+ printk(KERN_DEBUG "funny size %d\n", len);
-+// continue;
-+ }
-+ len -= RAW_LINE_PAD;
-+ eav_val = buf[1];
-+ DBG(DBG_FRAMING_LOUD,
-+ printk(KERN_DEBUG "eav: %02x len: %d\n", eav_val, len));
-+ if (eav_val == 0xf1) { /* end of field 2, V-blank: start-of-frame */
-+ switch (d->frame[d->hwframe].state) {
-+ case FRAME_UNUSED:
-+ DBG(DBG_FRAMING,
-+ printk(KERN_ERR "capture to unused frame %d\n",
-+ d->hwframe));
-+ break;
-+ case FRAME_READY:
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame started %d\n",
-+ d->hwframe));
-+ /* start this frame (skip eav/sav) */
-+ memcpy(d->frame[d->hwframe].pos, &buf[6], len);
-+#if DMA_DEINTERLACE
-+ if (!d->interlaced)
-+ memcpy(d->frame[d->hwframe].pos-len, &buf[6], len);
-+ d->frame[d->hwframe].pos += len*2;
-+#else
-+ d->frame[d->hwframe].pos += len;
-+#endif
-+ d->frame[d->hwframe].state = FRAME_GRABBING;
-+ /* XXXKW check pos overflow */
-+ break;
-+ case FRAME_GRABBING:
-+ /* kick over to new frame */
-+ d->frame[d->hwframe].size = d->frame[d->hwframe].pos -
-+ d->frame[d->hwframe].data;
-+ d->frame[d->hwframe].state = FRAME_DONE;
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame finished %d\n",
-+ d->frame[d->hwframe].size));
-+ /* wake up a waiting reader */
-+ DBG(DBG_IO, printk(KERN_DEBUG "wakeup\n"));
-+ wake_up(&d->frame[d->hwframe].read_wait);
-+ d->hwframe = (d->hwframe + 1) % NUM_FRAME;
-+ if (d->frame[d->hwframe].state == FRAME_READY) {
-+ /* start this frame */
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame bumped %d\n",
-+ d->hwframe));
-+ memcpy(d->frame[d->hwframe].pos, &buf[6], len);
-+#if DMA_DEINTERLACE
-+ if (!d->interlaced)
-+ memcpy(d->frame[d->hwframe].pos-len, &buf[6], len);
-+ d->frame[d->hwframe].pos += len*2;
-+#else
-+ d->frame[d->hwframe].pos += len;
-+#endif
-+ d->frame[d->hwframe].state = FRAME_GRABBING;
-+ } else {
-+ /* drop on the floor,
-+ note that we've stopped DMA'ing */
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame capture halted\n"));
-+ d->dma_enable = 0;
-+ }
-+ break;
-+ case FRAME_DONE:
-+ /* drop on the floor (must be waiting for sw) */
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame capture halted\n"));
-+ d->dma_enable = 0;
-+ break;
-+ }
-+ } else {
-+ switch (d->frame[d->hwframe].state) {
-+ case FRAME_UNUSED:
-+ DBG(DBG_FRAMING,
-+ printk(KERN_ERR "capture to unused frame %d\n",
-+ d->hwframe));
-+ break;
-+ case FRAME_READY:
-+ /* drop on the floor (must have dropped something) */
-+ DBG(DBG_FRAMING_LOUD,
-+ printk(KERN_DEBUG "missed SOF\n"));
-+ break;
-+ case FRAME_DONE:
-+ /* drop on the floor (must be waiting for sw) */
-+ DBG(DBG_FRAMING,
-+ printk(KERN_DEBUG "frame overflow\n"));
-+ d->dma_enable = 0;
-+ break;
-+ case FRAME_GRABBING:
-+#if DMA_DEINTERLACE
-+ if (eav_val == 0xb6) {
-+ d->frame[d->hwframe].pos = d->frame[d->hwframe].data;
-+ }
-+ memcpy(d->frame[d->hwframe].pos, &buf[6], len);
-+ if (!d->interlaced)
-+ memcpy(d->frame[d->hwframe].pos-len, &buf[6], len);
-+ d->frame[d->hwframe].pos += len*2;
-+#else
-+ memcpy(d->frame[d->hwframe].pos, &buf[6], len);
-+ d->frame[d->hwframe].pos += len;
-+#endif
-+ /* XXXKW check pos overflow */
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (d->dma_enable) {
-+ __raw_writeq(delta, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ DBG(DBG_DESCR,
-+ printk(KERN_DEBUG IF_NAME ": interrupt adds %d -> %d descrs\n",
-+ delta, (int)__raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT))));
-+ }
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * /dev/video interface
-+ * ----------------------------------------------------------------------- */
-+
-+static int saa7114h_open(struct video_device *vd, int nb)
-+{
-+ struct saa7114h *d = vd->priv;
-+ uint32_t status;
-+
-+ if (!d || d->opened)
-+ return -EBUSY;
-+
-+ d->opened = 1;
-+ DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ": open\n"));
-+
-+ /* XXKW Should check this periodically!? */
-+ status = saa7114h_reg_read(d, DECODER_STATUS);
-+ d->interlaced = ((status & 0x80) != 0);
-+
-+#if !NULL_DMA
-+ if (d->dma_enable) {
-+ printk(IF_NAME ": open found DMA on?!\n");
-+#if LAZY_READ
-+ }
-+#else
-+ } else {
-+ int descr;
-+ d->dma_enable = 1;
-+ DBG(DBG_DESCR, printk(IF_NAME ": open enabling DMA\n"));
-+ /* Force capture to start into frame buffer 0 */
-+ descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ DBG(DBG_DESCR,
-+ printk(IF_NAME ": open adds %d -> %d descrs\n",
-+ d->ff.ringsz-desc, descr));
-+ __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ }
-+#endif
-+#endif
-+
-+ return 0;
-+}
-+
-+static void saa7114h_release(struct video_device *vd)
-+{
-+ struct saa7114h *d = vd->priv;
-+
-+ DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ": release\n"));
-+ d->opened = 0;
-+ d->dma_enable = 0;
-+
-+ /* XXXKW do a clean drain of outstanding DMAs? toss leftover
-+ buffer contents to avoid stale pictures? */
-+
-+ return;
-+}
-+
-+static long saa7114h_read(struct video_device *vd, char *buf,
-+ unsigned long count, int noblock)
-+{
-+ struct saa7114h *d = vd->priv;
-+ int descr, status;
-+
-+ if (!d)
-+ return -ENODEV;
-+
-+ /* XXKW Should check this periodically!? */
-+ status = saa7114h_reg_read(d, DECODER_STATUS);
-+// d->interlaced = ((status & 0x80) != 0);
-+
-+#if !NULL_DMA
-+#if LAZY_READ
-+ if (!d->dma_enable) {
-+ DBG(DBG_DESCR, printk(KERN_DEBUG IF_NAME ": enabling DMA\n"));
-+ /* Give the buffer to the DMA engine (force ptr reset) */
-+ d->swframe = d->hwframe;
-+ d->frame[d->swframe].state = FRAME_READY;
-+#if DMA_DEINTERLACE
-+ d->frame[d->swframe].pos = d->frame[d->swframe].data+d->vw.width*RAW_PER_PIXEL;
-+#else
-+ d->frame[d->swframe].pos = d->frame[d->swframe].data;
-+#endif
-+ /* Fire up the DMA engine again if it stopped */
-+ d->dma_enable = 1;
-+ descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ }
-+#endif
-+#endif
-+
-+ /* XXXKW mmap/read mixture could break the swframe sequence */
-+
-+ if (d->frame[d->swframe].state != FRAME_DONE) {
-+ if (noblock)
-+ return -EAGAIN;
-+ else {
-+ DBG(DBG_IO,
-+ printk(KERN_DEBUG IF_NAME ": sleeping for frame\n"));
-+ interruptible_sleep_on(&d->frame[d->swframe].read_wait);
-+ DBG(DBG_IO,
-+ printk(KERN_DEBUG IF_NAME ": awakened\n"));
-+ if (signal_pending(current))
-+ return -ERESTARTSYS;
-+ }
-+ }
-+
-+ if (count < d->frame[d->swframe].size)
-+ return -EFAULT;
-+
-+ count = d->frame[d->swframe].size;
-+ yuvconvert_inplace(d->frame[d->swframe].data, d->frame[d->swframe].size, d->vp.palette, 0);
-+ copy_to_user(buf, d->frame[d->swframe].data, d->frame[d->swframe].size);
-+ d->swframe = (d->swframe + 1) % NUM_FRAME;
-+ /* XXXKW doesn't do format conversion!!! */
-+#if !NULL_DMA
-+#if !LAZY_READ
-+ /* XXXKW Fire up the DMA engine again if it stopped ??? */
-+ if (!d->dma_enable) {
-+ DBG(DBG_DESCR, printk(KERN_DEBUG IF_NAME ": enabling DMA\n"));
-+ /* Fire up the DMA engine again if it stopped */
-+ d->dma_enable = 1;
-+ descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ }
-+#endif
-+#endif
-+
-+ return count;
-+}
-+
-+static int saa7114h_ioctl(struct video_device *vd, unsigned int cmd, void *arg)
-+{
-+ struct saa7114h *d = vd->priv;
-+ int val, reg, retval = 0;
-+
-+ if (!d)
-+ return -ENODEV;
-+
-+ switch (cmd) {
-+ case VIDIOCGCHAN:
-+ {
-+ struct video_channel v;
-+
-+ if (copy_from_user(&v, arg, sizeof(v))) {
-+ retval = -EFAULT;
-+ break;
-+ }
-+ if (v.channel != 0) {
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ v.channel = 0;
-+ strcpy(v.name, "Camera");
-+ v.tuners = 0;
-+ v.flags = 0;
-+ v.type = VIDEO_TYPE_CAMERA;
-+ v.norm = 0;
-+
-+ if (copy_to_user(arg, &v, sizeof(v)))
-+ retval = -EFAULT;
-+ break;
-+ }
-+
-+ case VIDIOCSCHAN:
-+ {
-+ int v;
-+
-+ if (copy_from_user(&v, arg, sizeof(v)))
-+ retval = -EFAULT;
-+
-+ if (retval == 0 && v != 0)
-+ retval = -EINVAL;
-+
-+ break;
-+ }
-+
-+ case VIDIOCGCAP:
-+ {
-+ struct video_capability b;
-+
-+ strcpy(b.name, "Philips SAA7114H Decoder");
-+ b.type = VID_TYPE_CAPTURE /* | VID_TYPE_TELETEXT */ | VID_TYPE_SCALES;
-+ b.channels = 1;
-+ b.audios = 0;
-+ b.maxwidth = MAX_HORIZ;
-+ b.maxheight = MAX_VERT;
-+ /* XXXKW find real values */
-+ b.minwidth = 48;
-+ b.minheight = 48;
-+
-+ if (copy_to_user(arg, &b, sizeof(b)))
-+ retval = -EFAULT;
-+
-+ break;
-+ }
-+
-+ /* image properties */
-+ case VIDIOCGPICT:
-+ if (copy_to_user(arg, &d->vp, sizeof(struct video_picture)))
-+ retval = -EFAULT;
-+ break;
-+
-+ case VIDIOCSPICT:
-+ {
-+ struct video_picture vp;
-+
-+ /* copy_from_user */
-+ if (copy_from_user(&vp, arg, sizeof(vp))) {
-+ retval = -EFAULT;
-+ break;
-+ }
-+
-+ down(&d->param_lock);
-+ /* brightness, colour, contrast need not check 0-65535 */
-+ memcpy( &d->vp, &vp, sizeof(vp) );
-+ /* update cam->params.colourParams */
-+ saa7114h_set_cparams(d);
-+ up(&d->param_lock);
-+ break;
-+ }
-+
-+ /* get/set capture window */
-+ case VIDIOCGWIN:
-+ if (copy_to_user(arg, &d->vw, sizeof(struct video_window)))
-+ retval = -EFAULT;
-+ break;
-+
-+ case VIDIOCSWIN:
-+ {
-+ /* copy_from_user, check validity, copy to internal structure */
-+ struct video_window vw;
-+ if (copy_from_user(&vw, arg, sizeof(vw))) {
-+ retval = -EFAULT;
-+ break;
-+ }
-+
-+ if (vw.clipcount != 0) { /* clipping not supported */
-+ retval = -EINVAL;
-+ break;
-+ }
-+ if (vw.clips != NULL) { /* clipping not supported */
-+ retval = -EINVAL;
-+ break;
-+ }
-+ if ((vw.width > MAX_HORIZ || vw.width < MIN_HORIZ) ||
-+ (vw.height > MAX_VERT || vw.height < MIN_VERT)) {
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ /* we set the video window to something smaller or equal to what
-+ * is requested by the user???
-+ */
-+ down(&d->param_lock);
-+ if (vw.width != d->vw.width || vw.height != d->vw.height) {
-+ uint32_t scale_factor;
-+ /* XXXKW base percentage on input stream, not MAX? */
-+
-+ /* Assert scaler reset */
-+ saa7114h_reg_write(d, 0x88, 0x98);
-+
-+ /* Vertical scaling */
-+ scale_factor = (MAX_VERT*1024) / vw.height;
-+ saa7114h_reg_write(d, 0x9e, vw.height & 0xff);
-+ saa7114h_reg_write(d, 0x9f, (vw.height >> 8) & 0xf);
-+ saa7114h_reg_write(d, 0xb0, scale_factor & 0xff);
-+ saa7114h_reg_write(d, 0xb1, (scale_factor >> 8) & 0xff);
-+ saa7114h_reg_write(d, 0xb2, scale_factor & 0xff);
-+ saa7114h_reg_write(d, 0xb3, (scale_factor >> 8) & 0xff);
-+ /* Horizontal scaling */
-+ scale_factor = (MAX_HORIZ*1024) / vw.width;
-+ saa7114h_reg_write(d, 0x9c, vw.width & 0xff);
-+ saa7114h_reg_write(d, 0x9d, (vw.width >> 8) & 0xf);
-+ saa7114h_reg_write(d, 0xa8, scale_factor & 0xff);
-+ saa7114h_reg_write(d, 0xa9, (scale_factor >> 8) & 0xff);
-+ saa7114h_reg_write(d, 0xac, (scale_factor >> 1) & 0xff);
-+ saa7114h_reg_write(d, 0xad, (scale_factor >> 9) & 0xff);
-+#if 0
-+ /* prescaler
-+ saa7114h_reg_write(d, 0xa0, 2);
-+ saa7114h_reg_write(d, 0xa1, 1);
-+ saa7114h_reg_write(d, 0xa2, 1);
-+ */
-+#endif
-+
-+ /* Release scaler reset */
-+ saa7114h_reg_write(d, 0x88, 0xb8);
-+ d->vw.width = vw.width;
-+ d->vw.height = vw.height;
-+ }
-+ up(&d->param_lock);
-+ break;
-+ }
-+
-+ /* mmap interface */
-+ case VIDIOCGMBUF:
-+ {
-+ struct video_mbuf vm;
-+ int i;
-+
-+ memset(&vm, 0, sizeof(vm));
-+ vm.size = MAX_FRAME_SIZE*NUM_FRAME;
-+ vm.frames = NUM_FRAME;
-+ for (i = 0; i < NUM_FRAME; i++)
-+ vm.offsets[i] = MAX_FRAME_SIZE * i;
-+
-+ if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-+ retval = -EFAULT;
-+
-+ break;
-+ }
-+
-+ case VIDIOCMCAPTURE:
-+ {
-+ struct video_mmap vm;
-+ int descr, status;
-+
-+ if (copy_from_user((void *)&vm, (void *)arg, sizeof(vm))) {
-+ retval = -EFAULT;
-+ break;
-+ }
-+ if (vm.frame<0||vm.frame>NUM_FRAME) {
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ DBG(DBG_CALL,
-+ printk(KERN_DEBUG IF_NAME ":ioctl MCAPTURE %d\n", vm.frame));
-+
-+ d->vp.palette = vm.format;
-+ /* XXXKW set depth? */
-+ /* XXXKW match/update for vm.width, vm.height */
-+
-+ /* XXKW Should check this periodically!? */
-+ status = saa7114h_reg_read(d, DECODER_STATUS);
-+// d->interlaced = ((status & 0x80) != 0);
-+
-+ /* Give the buffer to the DMA engine */
-+ /* XXXKW vm.frame vs d->swframe!! mmap/read mismatch */
-+#if DMA_DEINTERLACE
-+ d->frame[vm.frame].pos = d->frame[vm.frame].data + d->vw.width*RAW_PER_PIXEL;
-+#else
-+ d->frame[vm.frame].pos = d->frame[vm.frame].data;
-+#endif
-+#if !NULL_DMA
-+ d->frame[vm.frame].state = FRAME_READY;
-+ /* Fire up the DMA engine again if it stopped */
-+ if (!d->dma_enable) {
-+ d->dma_enable = 1;
-+ d->hwframe = d->swframe = vm.frame;
-+ descr = __raw_readq(MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ DBG(DBG_DESCR,
-+ printk(KERN_DEBUG IF_NAME ": capture adds %d -> %d descrs\n",
-+ d->ff.ringsz-descr, descr));
-+ __raw_writeq(d->ff.ringsz-descr, MAC2_DMARX0_CSR(R_MAC_DMA_DSCR_CNT));
-+ }
-+#endif
-+ break;
-+ }
-+
-+ case VIDIOCSYNC:
-+ {
-+ int frame;
-+
-+ if (copy_from_user((void *)&frame, arg, sizeof(int))) {
-+ retval = -EFAULT;
-+ break;
-+ }
-+
-+ if (frame<0 || frame >= NUM_FRAME) {
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ DBG(DBG_CALL, printk(KERN_DEBUG IF_NAME ":ioctl CSYNC %d\n", frame));
-+
-+ switch (d->frame[frame].state) {
-+ case FRAME_UNUSED:
-+ DBG(DBG_IO,
-+ printk(KERN_ERR IF_NAME ":sync to unused frame %d\n", frame));
-+ retval = -EINVAL;
-+ break;
-+
-+ case FRAME_READY:
-+ case FRAME_GRABBING:
-+ DBG(DBG_IO,
-+ printk(KERN_DEBUG IF_NAME ": sleeping for frame %d\n", frame));
-+ interruptible_sleep_on(&d->frame[frame].read_wait);
-+ DBG(DBG_IO,
-+ printk(KERN_DEBUG IF_NAME ": awakened\n"));
-+ if (signal_pending(current))
-+ return -ERESTARTSYS;
-+ case FRAME_DONE:
-+#if !NULL_DMA
-+ yuvconvert_inplace(d->frame[frame].data,
-+ d->frame[frame].size,
-+ d->vp.palette, 1);
-+ d->frame[frame].state = FRAME_UNUSED;
-+#endif
-+ DBG(DBG_IO,
-+ printk(KERN_DEBUG IF_NAME ": sync finished %d\n",
-+ frame));
-+ break;
-+ }
-+ break;
-+ }
-+
-+ case VIDIOREADREG:
-+ reg = *(int *)arg;
-+ DBG(DBG_REGISTER, printk(KERN_DEBUG IF_NAME ": read of %02x\n", reg));
-+ if ((reg > 0xEF) || (reg < 0))
-+ return -EINVAL;
-+ val = saa7114h_reg_read((struct saa7114h *)vd->priv, reg);
-+ if (val == -1)
-+ return -EIO;
-+ *(int *)arg = val;
-+ break;
-+ case VIDIOWRITEREG:
-+ if (copy_from_user(®, arg, sizeof(int)) ||
-+ copy_from_user(&val, arg+sizeof(int), sizeof(int)))
-+ return -EFAULT;
-+ DBG(DBG_REGISTER, printk(KERN_DEBUG IF_NAME ": write of %02x <- %02x\n", reg, val));
-+ if ((reg > 0xEF) || (reg < 0))
-+ return -EINVAL;
-+ val = saa7114h_reg_write((struct saa7114h *)vd->priv, reg, val);
-+ if (val == -1)
-+ return -EIO;
-+ break;
-+ case VIDIOGRABFRAME:
-+ return grab_frame((struct saa7114h *)vd->priv, arg, 0);
-+ case VIDIOSHOWEAV:
-+ return grab_frame((struct saa7114h *)vd->priv, arg, 1);
-+ default:
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+static int saa7114h_mmap(struct video_device *vd, const char *adr,
-+ unsigned long size)
-+{
-+ struct saa7114h *d = vd->priv;
-+ unsigned long start = (unsigned long)adr;
-+ unsigned long page, pos;
-+
-+ if (!d)
-+ return -ENODEV;
-+
-+ if (size > MAX_MMAP_SIZE) {
-+ printk("mmap: bad size %lu > %lu\n", size, MAX_MMAP_SIZE);
-+ return -EINVAL;
-+ }
-+
-+ /* make this _really_ smp-safe */
-+ if (down_interruptible(&d->busy_lock))
-+ return -EINTR;
-+
-+ pos = (unsigned long)(d->frame_buf);
-+ while (size > 0) {
-+ page = kvirt_to_pa(pos);
-+ if (remap_page_range(start, page, PAGE_SIZE, PAGE_SHARED)) {
-+ up(&d->busy_lock);
-+ return -EAGAIN;
-+ }
-+ start += PAGE_SIZE;
-+ pos += PAGE_SIZE;
-+ if (size > PAGE_SIZE)
-+ size -= PAGE_SIZE;
-+ else
-+ size = 0;
-+ }
-+ up(&d->busy_lock);
-+
-+ return 0;
-+}
-+
-+/* -----------------------------------------------------------------------
-+ * Device probing and initialization
-+ * ----------------------------------------------------------------------- */
-+
-+/* Default values to program into SAA7114H */
-+static const unsigned char reg_init[] = {
-+ 0x00, 0x00, /* 00 - ID byte */
-+
-+ /*front end */
-+ 0x01, 0x08, /* 01 - Horizontal increment -> recommended delay */
-+ 0x02, 0xC4, /* 02 - AI Control 1 (CVBS AI23) */
-+ 0x03, 0x10, /* 03 - AI Control 2 */
-+ 0x04, 0x90, /* 04 - AI Control 3 (Gain ch 1) */
-+ 0x05, 0x90, /* 05 - AI Control 4 (Gain ch 2) */
-+
-+ /* decoder */
-+ 0x06, 0xEB, /* 06 - Horiz sync start */
-+ 0x07, 0xE0, /* 07 - Horiz sync stop */
-+ 0x08, 0x98, /* 08 - Sync control */
-+ 0x09, 0x40, /* 09 - L Control */
-+ 0x0a, 0x80, /* 0a - L Brightness */
-+ 0x0b, 0x44, /* 0b - L Contrast */
-+ 0x0c, 0x40, /* 0c - C Saturation */
-+ 0x0d, 0x00, /* 0d - C Hue */
-+ 0x0e, 0x89, /* 0e - C Control 1 */
-+ 0x0f, 0x0f, /* 0f - C Gain (??? 0x2A recommended) */
-+ 0x10, 0x0E, /* 10 - C Control 2 */
-+ 0x11, 0x00, /* 11 - Mode/Delay */
-+ 0x12, 0x00, /* 12 - RT signal control */
-+ 0x13, 0x00, /* 13 - RT/X output */
-+ 0x14, 0x00, /* 14 - Analog, Compat */
-+ 0x15, 0x11, /* 15 - VGATE start */
-+ 0x16, 0xFE, /* 16 - VGATE stop */
-+ 0x17, 0x40, /* 17 - Misc VGATE (disable LLC2) */
-+ 0x18, 0x40, /* 18 - Raw data gain - 128 */
-+ 0x19, 0x80, /* 19 - Raw data offset - 0 */
-+
-+ /* Global settings */
-+ 0x88, 0x98, /* 88 - AI1x on, AI2x off; decoder/slicer off; ACLK gen off */
-+ 0x83, 0x00, /* 83 - X-port output disabled */
-+ 0x84, 0xF0, /* 84 - I-port V/G output framing, IGP1=0=IGP0=0 */
-+ 0x85, 0x00, /* 85 - I-port default polarities, X-port signals */
-+ 0x86, 0x40, /* 86 - more IGP1/0, FIFO level, only video transmitted */
-+ 0x87, 0x01, /* 87 - ICK default, IDQ default, I-port output enabled */
-+
-+ /* Task A: scaler input config and output format */
-+ 0x90, 0x00, /* 90 - Task handling */
-+ 0x91, 0x08, /* 91 - Scalar input and format */
-+ 0x92, 0x10, /* 92 - Reference signal def */
-+ 0x93, 0x80, /* 93 - I-port output */
-+
-+ /* Task B */
-+ 0xc0, 0x42, /* 90 - Task handling */
-+ 0xc1, 0x08, /* 91 - Scalar input and format */
-+ 0xc2, 0x10, /* 92 - Reference signal def */
-+ 0xc3, 0x80, /* 93 - I-port output */
-+
-+ /* Input and Output windows */
-+ 0x94, 0x10, /* - */
-+ 0x95, 0x00, /* - */
-+ 0x96, 0xD0, /* - */
-+ 0x97, 0x02, /* - */
-+ 0x98, 0x0A, /* - */
-+ 0x99, 0x00, /* - */
-+ 0x9a, 0xF2, /* - */
-+ 0x9b, 0x00, /* - */
-+ 0x9c, 0xD0, /* - */
-+ 0x9d, 0x02, /* - */
-+ 0xc4, 0x10, /* - */
-+ 0xc5, 0x00, /* - */
-+ 0xc6, 0xD0, /* - */
-+ 0xc7, 0x02, /* - */
-+ 0xc8, 0x0A, /* - */
-+ 0xc9, 0x00, /* - */
-+ 0xca, 0xF2, /* - */
-+ 0xcb, 0x00, /* - */
-+ 0xcc, 0xD0, /* - */
-+ 0xcd, 0x02, /* - */
-+
-+ 0x9e, 0xf0, /* - */
-+ 0x9f, 0x00, /* - */
-+ 0xce, 0xf0, /* - */
-+ 0xcf, 0x00, /* - */
-+
-+ /* Prefiltering and prescaling */
-+ 0xa0, 0x01, /* - */
-+ 0xa1, 0x00, /* - */
-+ 0xa2, 0x00, /* - */
-+ 0xa4, 0x80, /* - */
-+ 0xa5, 0x40, /* - */
-+ 0xa6, 0x40, /* - */
-+ 0xd4, 0x80, /* - */
-+ 0xd5, 0x40, /* - */
-+ 0xd6, 0x40, /* - */
-+
-+ /* Horizontal phase scaling */
-+ 0xa8, 0x00, /* - */
-+ 0xa9, 0x04, /* - */
-+ 0xaa, 0x00, /* - */
-+ 0xd8, 0x00, /* - */
-+ 0xd9, 0x04, /* - */
-+ 0xda, 0x00, /* - */
-+
-+ 0xac, 0x00, /* - */
-+ 0xad, 0x02, /* - */
-+ 0xae, 0x00, /* - */
-+ 0xdc, 0x00, /* - */
-+ 0xdd, 0x02, /* - */
-+ 0xde, 0x00, /* - */
-+
-+ /* Vertical phase scaling */
-+ 0xb0, 0x00, /* - */
-+ 0xb1, 0x04, /* - */
-+ 0xb2, 0x00, /* - */
-+ 0xb3, 0x04, /* - */
-+ 0xe0, 0x00, /* - */
-+ 0xe1, 0x04, /* - */
-+ 0xe2, 0x00, /* - */
-+ 0xe3, 0x04, /* - */
-+ 0xb4, 0x00, /* b4 - vscale mode control */
-+ 0xe4, 0x00, /* b4 - vscale mode control */
-+
-+ /* Task enables */
-+ 0x80, 0x10, /* 80 - LLC->ICLK, dq->IDQ, scaler->F/V timing, task enables */
-+
-+ /* Reset the slicer */
-+ 0x88, 0xb8, /* 88 - AI1x on, AI2x off; decoder/slicer on; ACLK gen off */
-+};
-+
-+static int saa7114h_attach(struct i2c_adapter *adap, int addr, unsigned short flags, int kind)
-+{
-+ struct i2c_client *client;
-+ struct video_device *vd;
-+ struct saa7114h *decoder;
-+ int err;
-+ int val, i;
-+
-+ client = kmalloc(sizeof(*client), GFP_KERNEL);
-+ if (client == NULL)
-+ return -ENOMEM;
-+ client->adapter = adap;
-+ client->addr = addr;
-+ client->driver = &i2c_driver_saa7114h;
-+ strcpy(client->name, IF_NAME);
-+
-+ decoder = kmalloc(sizeof(*decoder), GFP_KERNEL);
-+ if (decoder == NULL) {
-+ kfree(client);
-+ return -ENOMEM;
-+ }
-+ memset(decoder, 0, sizeof(struct saa7114h));
-+ decoder->client = client;
-+ decoder->dma_enable = 0;
-+ decoder->palette = VIDEO_PALETTE_UYVY;
-+ decoder->depth = 16;
-+ decoder->vw.width = MAX_HORIZ;
-+ decoder->vw.height = MAX_VERT;
-+ decoder->frame_buf = rvmalloc(MAX_FRAME_SIZE*NUM_FRAME);
-+ if (!decoder->frame_buf) {
-+ kfree(decoder);
-+ kfree(client);
-+ return -ENOMEM;
-+ }
-+ /* XXXKW use clear_page? */
-+ memset(decoder->frame_buf, 0, MAX_FRAME_SIZE*NUM_FRAME);
-+ printk("saa7114h_attach: frame_buf = (fb=%8p / %08lx)\n",
-+ decoder->frame_buf, kvirt_to_pa((int)decoder->frame_buf));
-+ for (i=0; i<NUM_FRAME; i++) {
-+ decoder->frame[i].data = decoder->frame_buf+i*MAX_FRAME_SIZE;
-+#if NULL_DMA
-+ decoder->frame[i].state = FRAME_DONE;
-+#else
-+ decoder->frame[i].state = FRAME_UNUSED;
-+#endif
-+ init_waitqueue_head(&decoder->frame[i].read_wait);
-+ }
-+ decoder->irq = K_INT_MAC_2;
-+ if (request_irq
-+ (decoder->irq, saa7114h_interrupt, 0, "Philips SAA7114h", decoder)) {
-+ rvfree(decoder->frame_buf, MAX_FRAME_SIZE*NUM_FRAME);
-+ kfree(decoder);
-+ kfree(client);
-+ return -ENOMEM;
-+ }
-+ init_MUTEX(&decoder->param_lock);
-+ init_MUTEX(&decoder->busy_lock);
-+
-+ if ((err = i2c_attach_client(client)) < 0) {
-+ kfree(client);
-+ kfree(decoder);
-+ return err;
-+ }
-+
-+ if (saa7114h_reg_init(decoder, reg_init, sizeof(reg_init)) ||
-+ saa7114h_get_cparams(decoder)) {
-+ i2c_detach_client(client);
-+ kfree(client);
-+ kfree(decoder);
-+ return -ENODEV;
-+ }
-+
-+ vd = kmalloc(sizeof(*vd), GFP_KERNEL);
-+ memset(vd, 0, sizeof(*vd));
-+ if (vd == NULL) {
-+ i2c_detach_client(client);
-+ kfree(client);
-+ kfree(decoder);
-+ return -ENOMEM;
-+ }
-+ vd->priv = decoder;
-+ strcpy(vd->name, IF_NAME);
-+ vd->type = VID_TYPE_CAPTURE;
-+ vd->hardware = VID_HARDWARE_SAA7114H;
-+ vd->open = saa7114h_open;
-+ vd->close = saa7114h_release;
-+ vd->read = saa7114h_read;
-+ vd->ioctl = saa7114h_ioctl;
-+ vd->mmap = saa7114h_mmap;
-+
-+ if ((err = video_register_device(vd, VFL_TYPE_GRABBER, -1)) < 0) {
-+ i2c_detach_client(client);
-+ kfree(client);
-+ kfree(decoder);
-+ kfree(vd);
-+ return err;
-+ }
-+
-+ client->data = vd;
-+ decoder->vd = vd;
-+
-+ /* Turn on the ITRDY - preserve the GENO pin for syncser */
-+ val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO));
-+ __raw_writeq(M_MAC_MDIO_OUT | (val & M_MAC_GENC),
-+ KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO));
-+
-+ if ((err = dma_setup(decoder))) {
-+ i2c_detach_client(client);
-+ kfree(client);
-+ kfree(decoder);
-+ kfree(vd);
-+ return err;
-+ }
-+
-+ printk("saa7114h_attach successful\n");
-+
-+#ifdef CONFIG_PROC_FS
-+ proc_saa7114h_create();
-+ create_proc_decoder(vd->priv);
-+#endif
-+
-+ return 0;
-+}
-+
-+/* Addresses to scan */
-+static unsigned short normal_i2c[] = {I2C_CLIENT_END};
-+static unsigned short normal_i2c_range[] = {0x20, 0x21, I2C_CLIENT_END};
-+static unsigned short probe[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
-+static unsigned short probe_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
-+static unsigned short ignore[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
-+static unsigned short ignore_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
-+static unsigned short force[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
-+
-+static struct i2c_client_address_data addr_data = {
-+ normal_i2c, normal_i2c_range,
-+ probe, probe_range,
-+ ignore, ignore_range,
-+ force
-+};
-+
-+static int saa7114h_probe(struct i2c_adapter *adap)
-+{
-+ /* Look for this device on the given adapter (bus) */
-+ if (adap->id == (I2C_ALGO_SIBYTE | I2C_HW_SIBYTE))
-+ return i2c_probe(adap, &addr_data, &saa7114h_attach);
-+ else
-+ return 0;
-+}
-+
-+static int saa7114h_detach(struct i2c_client *device)
-+{
-+#if 0
-+ kfree(device->data);
-+#endif
-+#ifdef CONFIG_PROC_FS
-+ destroy_proc_decoder(((struct video_device *)device->data)->priv);
-+ proc_saa7114h_destroy();
-+#endif
-+ return 0;
-+}
-+
-+/* ----------------------------------------------------------------------- */
-+
-+static int __init swarm_7114h_init(void)
-+{
-+ return i2c_add_driver(&i2c_driver_saa7114h);
-+}
-+
-+static void __exit swarm_7114h_cleanup(void)
-+{
-+}
-+
-+MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
-+MODULE_DESCRIPTION("Philips SAA7114H Driver for Broadcom SWARM board");
-+
-+module_init(swarm_7114h_init);
-+module_exit(swarm_7114h_cleanup);
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/devices/Kconfig linux_HEAD/drivers/mtd/devices/Kconfig
---- linux-2.6.12/drivers/mtd/devices/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/devices/Kconfig 2005-02-17 21:49:45.000000000 +0100
-@@ -47,6 +47,11 @@ config MTD_MS02NV
- accelerator. Say Y here if you have a DECstation 5000/2x0 or a
- DECsystem 5900 equipped with such a module.
-
-+ If you want to compile this driver as a module ( = code which can be
-+ inserted in and removed from the running kernel whenever you want),
-+ say M here and read <file:Documentation/modules.txt>. The module will
-+ be called ms02-nv.o.
-+
- config MTD_SLRAM
- tristate "Uncached system RAM"
- depends on MTD
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/devices/docprobe.c linux_HEAD/drivers/mtd/devices/docprobe.c
---- linux-2.6.12/drivers/mtd/devices/docprobe.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/devices/docprobe.c 2005-02-17 21:49:45.000000000 +0100
-@@ -84,10 +84,10 @@ static unsigned long __initdata doc_loca
- 0xe4000000,
- #elif defined(CONFIG_MOMENCO_OCELOT)
- 0x2f000000,
-- 0xff000000,
-+ 0xff000000,
- #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
-- 0xff000000,
--##else
-+ 0xff000000,
-+#else
- #warning Unknown architecture for DiskOnChip. No default probe locations defined
- #endif
- 0xffffffff };
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/devices/ms02-nv.c linux_HEAD/drivers/mtd/devices/ms02-nv.c
---- linux-2.6.12/drivers/mtd/devices/ms02-nv.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/devices/ms02-nv.c 2005-07-03 16:44:31.000000000 +0200
-@@ -99,8 +99,8 @@ static inline uint ms02nv_probe_one(ulon
- * The firmware writes MS02NV_ID at MS02NV_MAGIC and also
- * a diagnostic status at MS02NV_DIAG.
- */
-- ms02nv_diagp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_DIAG));
-- ms02nv_magicp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_MAGIC));
-+ ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG));
-+ ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC));
- err = get_dbe(ms02nv_magic, ms02nv_magicp);
- if (err)
- return 0;
-@@ -233,7 +233,7 @@ static int __init ms02nv_init_one(ulong
- goto err_out_csr_res;
- }
-
-- printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %uMiB.\n",
-+ printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %zuMiB.\n",
- mtd->index, ms02nv_name, addr, size >> 20);
-
- mp->next = root_ms02nv_mtd;
-@@ -293,13 +293,13 @@ static int __init ms02nv_init(void)
-
- switch (mips_machtype) {
- case MACH_DS5000_200:
-- csr = (volatile u32 *)KN02_CSR_BASE;
-+ csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
- if (*csr & KN02_CSR_BNK32M)
- stride = 2;
- break;
- case MACH_DS5000_2X0:
- case MACH_DS5900:
-- csr = (volatile u32 *)KN03_MCR_BASE;
-+ csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
- if (*csr & KN03_MCR_BNK32M)
- stride = 2;
- break;
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/Kconfig linux_HEAD/drivers/mtd/maps/Kconfig
---- linux-2.6.12/drivers/mtd/maps/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/Kconfig 2005-03-21 20:04:22.000000000 +0100
-@@ -201,87 +201,12 @@ config MTD_TSUNAMI
- help
- Support for the flash chip on Tsunami TIG bus.
-
--config MTD_LASAT
-- tristate "Flash chips on LASAT board"
-- depends on LASAT
-- help
-- Support for the flash chips on the Lasat 100 and 200 boards.
--
- config MTD_NETtel
- tristate "CFI flash device on SnapGear/SecureEdge"
- depends on X86 && MTD_PARTITIONS && MTD_JEDECPROBE
- help
- Support for flash chips on NETtel/SecureEdge/SnapGear boards.
-
--config MTD_PB1XXX
-- tristate "Flash devices on Alchemy PB1xxx boards"
-- depends on MIPS && ( MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 )
-- help
-- Flash memory access on Alchemy Pb1000/Pb1100/Pb1500 boards
--
--config MTD_PB1XXX_BOOT
-- bool "PB1x00 boot flash device"
-- depends on MTD_PB1XXX && ( MIPS_PB1100 || MIPS_PB1500 )
-- help
-- Use the first of the two 32MiB flash banks on Pb1100/Pb1500 board.
-- You can say 'Y' to both this and 'MTD_PB1XXX_USER' below, to use
-- both banks.
--
--config MTD_PB1XXX_USER
-- bool "PB1x00 user flash device"
-- depends on MTD_PB1XXX && ( MIPS_PB1100 || MIPS_PB1500 )
-- default y if MTD_PB1XX_BOOT = n
-- help
-- Use the second of the two 32MiB flash banks on Pb1100/Pb1500 board.
-- You can say 'Y' to both this and 'MTD_PB1XXX_BOOT' above, to use
-- both banks.
--
--config MTD_PB1550
-- tristate "Flash devices on Alchemy PB1550 board"
-- depends on MIPS && MIPS_PB1550
-- help
-- Flash memory access on Alchemy Pb1550 board
--
--config MTD_PB1550_BOOT
-- bool "PB1550 boot flash device"
-- depends on MTD_PB1550
-- help
-- Use the first of the two 64MiB flash banks on Pb1550 board.
-- You can say 'Y' to both this and 'MTD_PB1550_USER' below, to use
-- both banks.
--
--config MTD_PB1550_USER
-- bool "PB1550 user flash device"
-- depends on MTD_PB1550
-- default y if MTD_PB1550_BOOT = n
-- help
-- Use the second of the two 64MiB flash banks on Pb1550 board.
-- You can say 'Y' to both this and 'MTD_PB1550_BOOT' above, to use
-- both banks.
--
--config MTD_DB1550
-- tristate "Flash devices on Alchemy DB1550 board"
-- depends on MIPS && MIPS_DB1550
-- help
-- Flash memory access on Alchemy Db1550 board
--
--config MTD_DB1550_BOOT
-- bool "DB1550 boot flash device"
-- depends on MTD_DB1550
-- help
-- Use the first of the two 64MiB flash banks on Db1550 board.
-- You can say 'Y' to both this and 'MTD_DB1550_USER' below, to use
-- both banks.
--
--config MTD_DB1550_USER
-- bool "DB1550 user flash device"
-- depends on MTD_DB1550
-- default y if MTD_DB1550_BOOT = n
-- help
-- Use the second of the two 64MiB flash banks on Db1550 board.
-- You can say 'Y' to both this and 'MTD_DB1550_BOOT' above, to use
-- both banks.
--
- config MTD_DILNETPC
- tristate "CFI Flash device mapped on DIL/Net PC"
- depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
-@@ -357,6 +282,24 @@ config MTD_CFI_FLAGADM
- Mapping for the Flaga digital module. If you don't have one, ignore
- this setting.
-
-+config MTD_ALCHEMY
-+ tristate ' AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support'
-+ depends on MIPS && SOC_AU1X00
-+ help
-+ Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
-+
-+config MTD_XXS1500
-+ tristate "MyCable XXS1500 Flash device"
-+ depends on MIPS && MIPS_XXS1500
-+ help
-+ Flash memory access on MyCable XXS1500 Board
-+
-+config MTD_MTX1
-+ tristate "4-G Systems MTX-1 Flash device"
-+ depends on MIPS && MIPS_MTX1
-+ help
-+ Flash memory access on 4-G Systems MTX-1 Board
-+
- config MTD_BEECH
- tristate "CFI Flash device mapped on IBM 405LP Beech"
- depends on MTD_CFI && PPC32 && 40x && BEECH
-@@ -457,6 +400,12 @@ config MTD_OCELOT
- NVRAM on the Momenco Ocelot board. If you have one of these boards
- and would like access to either of these, say 'Y'.
-
-+config MTD_LASAT
-+ tristate "LASAT flash device"
-+ depends on LASAT && MTD_CFI
-+ help
-+ Support for the flash chips on the Lasat 100 and 200 boards.
-+
- config MTD_SOLUTIONENGINE
- tristate "CFI Flash device mapped on Hitachi SolutionEngine"
- depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/Makefile linux_HEAD/drivers/mtd/maps/Makefile
---- linux-2.6.12/drivers/mtd/maps/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/Makefile 2005-03-21 20:04:22.000000000 +0100
-@@ -44,11 +44,9 @@ obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.
- obj-$(CONFIG_MTD_OCELOT) += ocelot.o
- obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
- obj-$(CONFIG_MTD_PCI) += pci.o
--obj-$(CONFIG_MTD_PB1XXX) += pb1xxx-flash.o
--obj-$(CONFIG_MTD_DB1X00) += db1x00-flash.o
--obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o
--obj-$(CONFIG_MTD_DB1550) += db1550-flash.o
- obj-$(CONFIG_MTD_LASAT) += lasat.o
-+obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o
-+obj-$(CONFIG_MTD_DB1550) += db1550-flash.o
- obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
- obj-$(CONFIG_MTD_EDB7312) += edb7312.o
- obj-$(CONFIG_MTD_IMPA7) += impa7.o
-@@ -70,4 +68,4 @@ obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
- obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
- obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
- obj-$(CONFIG_MTD_DMV182) += dmv182.o
--obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o
-+obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/alchemy-flash.c linux_HEAD/drivers/mtd/maps/alchemy-flash.c
---- linux-2.6.12/drivers/mtd/maps/alchemy-flash.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/mtd/maps/alchemy-flash.c 2005-02-27 23:03:20.000000000 +0100
-@@ -0,0 +1,192 @@
-+/*
-+ * Flash memory access on AMD Alchemy evaluation boards
-+ *
-+ * $Id: alchemy-flash.c,v 1.1 2005/02/27 22:03:20 ppopov Exp $
-+ *
-+ * (C) 2003, 2004 Pete Popov <ppopov at embeddedalley.com>
-+ *
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/map.h>
-+#include <linux/mtd/partitions.h>
-+
-+#include <asm/io.h>
-+
-+#ifdef DEBUG_RW
-+#define DBG(x...) printk(x)
-+#else
-+#define DBG(x...)
-+#endif
-+
-+#ifdef CONFIG_MIPS_PB1000
-+#define BOARD_MAP_NAME "Pb1000 Flash"
-+#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_PB1500
-+#define BOARD_MAP_NAME "Pb1500 Flash"
-+#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_PB1100
-+#define BOARD_MAP_NAME "Pb1100 Flash"
-+#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_PB1550
-+#define BOARD_MAP_NAME "Pb1550 Flash"
-+#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_PB1200
-+#define BOARD_MAP_NAME "Pb1200 Flash"
-+#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
-+#define BOARD_FLASH_WIDTH 2 /* 16-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1000
-+#define BOARD_MAP_NAME "Db1000 Flash"
-+#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1500
-+#define BOARD_MAP_NAME "Db1500 Flash"
-+#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1100
-+#define BOARD_MAP_NAME "Db1100 Flash"
-+#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1550
-+#define BOARD_MAP_NAME "Db1550 Flash"
-+#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_DB1200
-+#define BOARD_MAP_NAME "Db1200 Flash"
-+#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
-+#define BOARD_FLASH_WIDTH 2 /* 16-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_HYDROGEN3
-+#define BOARD_MAP_NAME "Hydrogen3 Flash"
-+#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#define USE_LOCAL_ACCESSORS /* why? */
-+#endif
-+
-+#ifdef CONFIG_MIPS_BOSPORUS
-+#define BOARD_MAP_NAME "Bosporus Flash"
-+#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
-+#define BOARD_FLASH_WIDTH 2 /* 16-bits */
-+#endif
-+
-+#ifdef CONFIG_MIPS_MIRAGE
-+#define BOARD_MAP_NAME "Mirage Flash"
-+#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
-+#define BOARD_FLASH_WIDTH 4 /* 32-bits */
-+#define USE_LOCAL_ACCESSORS /* why? */
-+#endif
-+
-+static struct map_info alchemy_map = {
-+ .name = BOARD_MAP_NAME,
-+};
-+
-+static struct mtd_partition alchemy_partitions[] = {
-+ {
-+ .name = "User FS",
-+ .size = BOARD_FLASH_SIZE - 0x00400000,
-+ .offset = 0x0000000
-+ },{
-+ .name = "YAMON",
-+ .size = 0x0100000,
-+ .offset = MTDPART_OFS_APPEND,
-+ .mask_flags = MTD_WRITEABLE
-+ },{
-+ .name = "raw kernel",
-+ .size = (0x300000 - 0x40000), /* last 256KB is yamon env */
-+ .offset = MTDPART_OFS_APPEND,
-+ }
-+};
-+
-+#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
-+
-+static struct mtd_info *mymtd;
-+
-+int __init alchemy_mtd_init(void)
-+{
-+ struct mtd_partition *parts;
-+ int nb_parts = 0;
-+ unsigned long window_addr;
-+ unsigned long window_size;
-+
-+ /* Default flash buswidth */
-+ alchemy_map.bankwidth = BOARD_FLASH_WIDTH;
-+
-+ window_addr = 0x20000000 - BOARD_FLASH_SIZE;
-+ window_size = BOARD_FLASH_SIZE;
-+#ifdef CONFIG_MIPS_MIRAGE_WHY
-+ /* Boot ROM flash bank only; no user bank */
-+ window_addr = 0x1C000000;
-+ window_size = 0x04000000;
-+ /* USERFS from 0x1C00 0000 to 0x1FC00000 */
-+ alchemy_partitions[0].size = 0x03C00000;
-+#endif
-+
-+ /*
-+ * Static partition definition selection
-+ */
-+ parts = alchemy_partitions;
-+ nb_parts = NB_OF(alchemy_partitions);
-+ alchemy_map.size = window_size;
-+
-+ /*
-+ * Now let's probe for the actual flash. Do it here since
-+ * specific machine settings might have been set above.
-+ */
-+ printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n",
-+ alchemy_map.bankwidth*8);
-+ alchemy_map.virt = ioremap(window_addr, window_size);
-+ mymtd = do_map_probe("cfi_probe", &alchemy_map);
-+ if (!mymtd) {
-+ iounmap(alchemy_map.virt);
-+ return -ENXIO;
-+ }
-+ mymtd->owner = THIS_MODULE;
-+
-+ add_mtd_partitions(mymtd, parts, nb_parts);
-+ return 0;
-+}
-+
-+static void __exit alchemy_mtd_cleanup(void)
-+{
-+ if (mymtd) {
-+ del_mtd_partitions(mymtd);
-+ map_destroy(mymtd);
-+ iounmap(alchemy_map.virt);
-+ }
-+}
-+
-+module_init(alchemy_mtd_init);
-+module_exit(alchemy_mtd_cleanup);
-+
-+MODULE_AUTHOR("Embedded Alley Solutions, Inc");
-+MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver");
-+MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/db1550-flash.c linux_HEAD/drivers/mtd/maps/db1550-flash.c
---- linux-2.6.12/drivers/mtd/maps/db1550-flash.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/db1550-flash.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,187 +0,0 @@
--/*
-- * Flash memory access on Alchemy Db1550 board
-- *
-- * $Id: db1550-flash.c,v 1.7 2004/11/04 13:24:14 gleixner Exp $
-- *
-- * (C) 2004 Embedded Edge, LLC, based on db1550-flash.c:
-- * (C) 2003, 2004 Pete Popov <ppopov at embeddedalley.com>
-- *
-- */
--
--#include <linux/config.h>
--#include <linux/init.h>
--#include <linux/module.h>
--#include <linux/types.h>
--#include <linux/kernel.h>
--
--#include <linux/mtd/mtd.h>
--#include <linux/mtd/map.h>
--#include <linux/mtd/partitions.h>
--
--#include <asm/io.h>
--
--#ifdef DEBUG_RW
--#define DBG(x...) printk(x)
--#else
--#define DBG(x...)
--#endif
--
--static unsigned long window_addr;
--static unsigned long window_size;
--
--
--static struct map_info db1550_map = {
-- .name = "Db1550 flash",
--};
--
--static unsigned char flash_bankwidth = 4;
--
--/*
-- * Support only 64MB NOR Flash parts
-- */
--
--#if defined(CONFIG_MTD_DB1550_BOOT) && defined(CONFIG_MTD_DB1550_USER)
--#define DB1550_BOTH_BANKS
--#elif defined(CONFIG_MTD_DB1550_BOOT) && !defined(CONFIG_MTD_DB1550_USER)
--#define DB1550_BOOT_ONLY
--#elif !defined(CONFIG_MTD_DB1550_BOOT) && defined(CONFIG_MTD_DB1550_USER)
--#define DB1550_USER_ONLY
--#endif
--
--#ifdef DB1550_BOTH_BANKS
--/* both banks will be used. Combine the first bank and the first
-- * part of the second bank together into a single jffs/jffs2
-- * partition.
-- */
--static struct mtd_partition db1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash
-- * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = (0x1FC00000 - 0x18000000),
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000 - 0x40000), /* last 256KB is yamon env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(DB1550_BOOT_ONLY)
--static struct mtd_partition db1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = 0x03c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000-0x40000), /* last 256KB is yamon env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(DB1550_USER_ONLY)
--static struct mtd_partition db1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = (0x4000000 - 0x200000), /* reserve 2MB for raw kernel */
-- .offset = 0x0000000
-- },{
-- .name = "raw kernel",
-- .size = MTDPART_SIZ_FULL,
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#else
--#error MTD_DB1550 define combo error /* should never happen */
--#endif
--
--#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
--
--static struct mtd_info *mymtd;
--
--/*
-- * Probe the flash density and setup window address and size
-- * based on user CONFIG options. There are times when we don't
-- * want the MTD driver to be probing the boot or user flash,
-- * so having the option to enable only one bank is important.
-- */
--int setup_flash_params(void)
--{
--#if defined(DB1550_BOTH_BANKS)
-- window_addr = 0x18000000;
-- window_size = 0x8000000;
--#elif defined(DB1550_BOOT_ONLY)
-- window_addr = 0x1C000000;
-- window_size = 0x4000000;
--#else /* USER ONLY */
-- window_addr = 0x18000000;
-- window_size = 0x4000000;
--#endif
-- return 0;
--}
--
--int __init db1550_mtd_init(void)
--{
-- struct mtd_partition *parts;
-- int nb_parts = 0;
--
-- /* Default flash bankwidth */
-- db1550_map.bankwidth = flash_bankwidth;
--
-- if (setup_flash_params())
-- return -ENXIO;
--
-- /*
-- * Static partition definition selection
-- */
-- parts = db1550_partitions;
-- nb_parts = NB_OF(db1550_partitions);
-- db1550_map.size = window_size;
--
-- /*
-- * Now let's probe for the actual flash. Do it here since
-- * specific machine settings might have been set above.
-- */
-- printk(KERN_NOTICE "Db1550 flash: probing %d-bit flash bus\n",
-- db1550_map.bankwidth*8);
-- db1550_map.virt = ioremap(window_addr, window_size);
-- mymtd = do_map_probe("cfi_probe", &db1550_map);
-- if (!mymtd) return -ENXIO;
-- mymtd->owner = THIS_MODULE;
--
-- add_mtd_partitions(mymtd, parts, nb_parts);
-- return 0;
--}
--
--static void __exit db1550_mtd_cleanup(void)
--{
-- if (mymtd) {
-- del_mtd_partitions(mymtd);
-- map_destroy(mymtd);
-- iounmap((void *) db1550_map.virt);
-- }
--}
--
--module_init(db1550_mtd_init);
--module_exit(db1550_mtd_cleanup);
--
--MODULE_AUTHOR("Embedded Edge, LLC");
--MODULE_DESCRIPTION("Db1550 mtd map driver");
--MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/db1x00-flash.c linux_HEAD/drivers/mtd/maps/db1x00-flash.c
---- linux-2.6.12/drivers/mtd/maps/db1x00-flash.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/db1x00-flash.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,226 +0,0 @@
--/*
-- * Flash memory access on Alchemy Db1xxx boards
-- *
-- * $Id: db1x00-flash.c,v 1.6 2004/11/04 13:24:14 gleixner Exp $
-- *
-- * (C) 2003 Pete Popov <ppopov at embeddedalley.com>
-- *
-- */
--
--#include <linux/config.h>
--#include <linux/module.h>
--#include <linux/types.h>
--#include <linux/init.h>
--#include <linux/kernel.h>
--
--#include <linux/mtd/mtd.h>
--#include <linux/mtd/map.h>
--#include <linux/mtd/partitions.h>
--
--#include <asm/io.h>
--
--#ifdef DEBUG_RW
--#define DBG(x...) printk(x)
--#else
--#define DBG(x...)
--#endif
--
--/* MTD CONFIG OPTIONS */
--#if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
--#define DB1X00_BOTH_BANKS
--#elif defined(CONFIG_MTD_DB1X00_BOOT) && !defined(CONFIG_MTD_DB1X00_USER)
--#define DB1X00_BOOT_ONLY
--#elif !defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
--#define DB1X00_USER_ONLY
--#endif
--
--static unsigned long window_addr;
--static unsigned long window_size;
--static unsigned long flash_size;
--
--static unsigned short *bcsr = (unsigned short *)0xAE000000;
--static unsigned char flash_bankwidth = 4;
--
--/*
-- * The Db1x boards support different flash densities. We setup
-- * the mtd_partition structures below for default of 64Mbit
-- * flash densities, and override the partitions sizes, if
-- * necessary, after we check the board status register.
-- */
--
--#ifdef DB1X00_BOTH_BANKS
--/* both banks will be used. Combine the first bank and the first
-- * part of the second bank together into a single jffs/jffs2
-- * partition.
-- */
--static struct mtd_partition db1x00_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x1c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000-0x40000), /* last 256KB is env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(DB1X00_BOOT_ONLY)
--static struct mtd_partition db1x00_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x00c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000-0x40000), /* last 256KB is env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(DB1X00_USER_ONLY)
--static struct mtd_partition db1x00_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x0e00000,
-- .offset = 0x0000000
-- },{
-- .name = "raw kernel",
-- .size = MTDPART_SIZ_FULL,
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#else
--#error MTD_DB1X00 define combo error /* should never happen */
--#endif
--#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
--
--#define NAME "Db1x00 Linux Flash"
--
--static struct map_info db1xxx_mtd_map = {
-- .name = NAME,
--};
--
--static struct mtd_partition *parsed_parts;
--static struct mtd_info *db1xxx_mtd;
--
--/*
-- * Probe the flash density and setup window address and size
-- * based on user CONFIG options. There are times when we don't
-- * want the MTD driver to be probing the boot or user flash,
-- * so having the option to enable only one bank is important.
-- */
--int setup_flash_params(void)
--{
-- switch ((bcsr[2] >> 14) & 0x3) {
-- case 0: /* 64Mbit devices */
-- flash_size = 0x800000; /* 8MB per part */
--#if defined(DB1X00_BOTH_BANKS)
-- window_addr = 0x1E000000;
-- window_size = 0x2000000;
--#elif defined(DB1X00_BOOT_ONLY)
-- window_addr = 0x1F000000;
-- window_size = 0x1000000;
--#else /* USER ONLY */
-- window_addr = 0x1E000000;
-- window_size = 0x1000000;
--#endif
-- break;
-- case 1:
-- /* 128 Mbit devices */
-- flash_size = 0x1000000; /* 16MB per part */
--#if defined(DB1X00_BOTH_BANKS)
-- window_addr = 0x1C000000;
-- window_size = 0x4000000;
-- /* USERFS from 0x1C00 0000 to 0x1FC0 0000 */
-- db1x00_partitions[0].size = 0x3C00000;
--#elif defined(DB1X00_BOOT_ONLY)
-- window_addr = 0x1E000000;
-- window_size = 0x2000000;
-- /* USERFS from 0x1E00 0000 to 0x1FC0 0000 */
-- db1x00_partitions[0].size = 0x1C00000;
--#else /* USER ONLY */
-- window_addr = 0x1C000000;
-- window_size = 0x2000000;
-- /* USERFS from 0x1C00 0000 to 0x1DE00000 */
-- db1x00_partitions[0].size = 0x1DE0000;
--#endif
-- break;
-- case 2:
-- /* 256 Mbit devices */
-- flash_size = 0x4000000; /* 64MB per part */
--#if defined(DB1X00_BOTH_BANKS)
-- return 1;
--#elif defined(DB1X00_BOOT_ONLY)
-- /* Boot ROM flash bank only; no user bank */
-- window_addr = 0x1C000000;
-- window_size = 0x4000000;
-- /* USERFS from 0x1C00 0000 to 0x1FC00000 */
-- db1x00_partitions[0].size = 0x3C00000;
--#else /* USER ONLY */
-- return 1;
--#endif
-- break;
-- default:
-- return 1;
-- }
-- db1xxx_mtd_map.size = window_size;
-- db1xxx_mtd_map.bankwidth = flash_bankwidth;
-- db1xxx_mtd_map.phys = window_addr;
-- db1xxx_mtd_map.bankwidth = flash_bankwidth;
-- return 0;
--}
--
--int __init db1x00_mtd_init(void)
--{
-- struct mtd_partition *parts;
-- int nb_parts = 0;
--
-- if (setup_flash_params())
-- return -ENXIO;
--
-- /*
-- * Static partition definition selection
-- */
-- parts = db1x00_partitions;
-- nb_parts = NB_OF(db1x00_partitions);
--
-- /*
-- * Now let's probe for the actual flash. Do it here since
-- * specific machine settings might have been set above.
-- */
-- printk(KERN_NOTICE "Db1xxx flash: probing %d-bit flash bus\n",
-- db1xxx_mtd_map.bankwidth*8);
-- db1xxx_mtd_map.virt = ioremap(window_addr, window_size);
-- db1xxx_mtd = do_map_probe("cfi_probe", &db1xxx_mtd_map);
-- if (!db1xxx_mtd) return -ENXIO;
-- db1xxx_mtd->owner = THIS_MODULE;
--
-- add_mtd_partitions(db1xxx_mtd, parts, nb_parts);
-- return 0;
--}
--
--static void __exit db1x00_mtd_cleanup(void)
--{
-- if (db1xxx_mtd) {
-- del_mtd_partitions(db1xxx_mtd);
-- map_destroy(db1xxx_mtd);
-- if (parsed_parts)
-- kfree(parsed_parts);
-- }
--}
--
--module_init(db1x00_mtd_init);
--module_exit(db1x00_mtd_cleanup);
--
--MODULE_AUTHOR("Pete Popov");
--MODULE_DESCRIPTION("Db1x00 mtd map driver");
--MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/lasat.c linux_HEAD/drivers/mtd/maps/lasat.c
---- linux-2.6.12/drivers/mtd/maps/lasat.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/lasat.c 2004-12-04 20:57:27.000000000 +0100
-@@ -7,7 +7,7 @@
- * modify it under the terms of the GNU General Public License version
- * 2 as published by the Free Software Foundation.
- *
-- * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $
-+ * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $
- *
- */
-
-@@ -50,7 +50,7 @@ static int __init init_lasat(void)
- ENABLE_VPP((&lasat_map));
-
- lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER);
-- lasat_map.virt = ioremap_nocache(
-+ lasat_map.virt = (unsigned long)ioremap_nocache(
- lasat_map.phys, lasat_board_info.li_flash_size);
- lasat_map.size = lasat_board_info.li_flash_size;
-
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/pb1550-flash.c linux_HEAD/drivers/mtd/maps/pb1550-flash.c
---- linux-2.6.12/drivers/mtd/maps/pb1550-flash.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/pb1550-flash.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,203 +0,0 @@
--/*
-- * Flash memory access on Alchemy Pb1550 board
-- *
-- * $Id: pb1550-flash.c,v 1.6 2004/11/04 13:24:15 gleixner Exp $
-- *
-- * (C) 2004 Embedded Edge, LLC, based on pb1550-flash.c:
-- * (C) 2003 Pete Popov <ppopov at pacbell.net>
-- *
-- */
--
--#include <linux/config.h>
--#include <linux/init.h>
--#include <linux/module.h>
--#include <linux/types.h>
--#include <linux/kernel.h>
--
--#include <linux/mtd/mtd.h>
--#include <linux/mtd/map.h>
--#include <linux/mtd/partitions.h>
--
--#include <asm/io.h>
--#include <asm/au1000.h>
--#include <asm/pb1550.h>
--
--#ifdef DEBUG_RW
--#define DBG(x...) printk(x)
--#else
--#define DBG(x...)
--#endif
--
--static unsigned long window_addr;
--static unsigned long window_size;
--
--
--static struct map_info pb1550_map = {
-- .name = "Pb1550 flash",
--};
--
--static unsigned char flash_bankwidth = 4;
--
--/*
-- * Support only 64MB NOR Flash parts
-- */
--
--#ifdef PB1550_BOTH_BANKS
--/* both banks will be used. Combine the first bank and the first
-- * part of the second bank together into a single jffs/jffs2
-- * partition.
-- */
--static struct mtd_partition pb1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash
-- * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = (0x1FC00000 - 0x18000000),
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000 - 0x40000), /* last 256KB is yamon env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(PB1550_BOOT_ONLY)
--static struct mtd_partition pb1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1C00 0000 1FFF FFFF CE0 64MB Boot NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = 0x03c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = MTDPART_OFS_APPEND,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = (0x300000-0x40000), /* last 256KB is yamon env */
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#elif defined(PB1550_USER_ONLY)
--static struct mtd_partition pb1550_partitions[] = {
-- /* assume boot[2:0]:swap is '0000' or '1000', which translates to:
-- * 1800 0000 1BFF FFFF CE0 64MB Param NOR Flash
-- */
-- {
-- .name = "User FS",
-- .size = (0x4000000 - 0x200000), /* reserve 2MB for raw kernel */
-- .offset = 0x0000000
-- },{
-- .name = "raw kernel",
-- .size = MTDPART_SIZ_FULL,
-- .offset = MTDPART_OFS_APPEND,
-- }
--};
--#else
--#error MTD_PB1550 define combo error /* should never happen */
--#endif
--
--#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
--
--static struct mtd_info *mymtd;
--
--/*
-- * Probe the flash density and setup window address and size
-- * based on user CONFIG options. There are times when we don't
-- * want the MTD driver to be probing the boot or user flash,
-- * so having the option to enable only one bank is important.
-- */
--int setup_flash_params(void)
--{
-- u16 boot_swapboot;
-- boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) |
-- ((bcsr->status >> 6) & 0x1);
-- printk("Pb1550 MTD: boot:swap %d\n", boot_swapboot);
--
-- switch (boot_swapboot) {
-- case 0: /* 512Mbit devices, both enabled */
-- case 1:
-- case 8:
-- case 9:
--#if defined(PB1550_BOTH_BANKS)
-- window_addr = 0x18000000;
-- window_size = 0x8000000;
--#elif defined(PB1550_BOOT_ONLY)
-- window_addr = 0x1C000000;
-- window_size = 0x4000000;
--#else /* USER ONLY */
-- window_addr = 0x1E000000;
-- window_size = 0x4000000;
--#endif
-- break;
-- case 0xC:
-- case 0xD:
-- case 0xE:
-- case 0xF:
-- /* 64 MB Boot NOR Flash is disabled */
-- /* and the start address is moved to 0x0C00000 */
-- window_addr = 0x0C000000;
-- window_size = 0x4000000;
-- default:
-- printk("Pb1550 MTD: unsupported boot:swap setting\n");
-- return 1;
-- }
-- return 0;
--}
--
--int __init pb1550_mtd_init(void)
--{
-- struct mtd_partition *parts;
-- int nb_parts = 0;
--
-- /* Default flash bankwidth */
-- pb1550_map.bankwidth = flash_bankwidth;
--
-- if (setup_flash_params())
-- return -ENXIO;
--
-- /*
-- * Static partition definition selection
-- */
-- parts = pb1550_partitions;
-- nb_parts = NB_OF(pb1550_partitions);
-- pb1550_map.size = window_size;
--
-- /*
-- * Now let's probe for the actual flash. Do it here since
-- * specific machine settings might have been set above.
-- */
-- printk(KERN_NOTICE "Pb1550 flash: probing %d-bit flash bus\n",
-- pb1550_map.bankwidth*8);
-- pb1550_map.virt = ioremap(window_addr, window_size);
-- mymtd = do_map_probe("cfi_probe", &pb1550_map);
-- if (!mymtd) return -ENXIO;
-- mymtd->owner = THIS_MODULE;
--
-- add_mtd_partitions(mymtd, parts, nb_parts);
-- return 0;
--}
--
--static void __exit pb1550_mtd_cleanup(void)
--{
-- if (mymtd) {
-- del_mtd_partitions(mymtd);
-- map_destroy(mymtd);
-- }
--}
--
--module_init(pb1550_mtd_init);
--module_exit(pb1550_mtd_cleanup);
--
--MODULE_AUTHOR("Embedded Edge, LLC");
--MODULE_DESCRIPTION("Pb1550 mtd map driver");
--MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/maps/pb1xxx-flash.c linux_HEAD/drivers/mtd/maps/pb1xxx-flash.c
---- linux-2.6.12/drivers/mtd/maps/pb1xxx-flash.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/maps/pb1xxx-flash.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,178 +0,0 @@
--/*
-- * Flash memory access on Alchemy Pb1xxx boards
-- *
-- * (C) 2001 Pete Popov <ppopov at mvista.com>
-- *
-- * $Id: pb1xxx-flash.c,v 1.14 2004/11/04 13:24:15 gleixner Exp $
-- */
--
--#include <linux/config.h>
--#include <linux/module.h>
--#include <linux/types.h>
--#include <linux/init.h>
--#include <linux/kernel.h>
--
--#include <linux/mtd/mtd.h>
--#include <linux/mtd/map.h>
--#include <linux/mtd/partitions.h>
--
--#include <asm/io.h>
--
--#ifdef DEBUG_RW
--#define DBG(x...) printk(x)
--#else
--#define DBG(x...)
--#endif
--
--#ifdef CONFIG_MIPS_PB1000
--
--#define WINDOW_ADDR 0x1F800000
--#define WINDOW_SIZE 0x800000
--
--static struct mtd_partition pb1xxx_partitions[] = {
-- {
-- .name = "yamon env",
-- .size = 0x00020000,
-- .offset = 0,
-- .mask_flags = MTD_WRITEABLE},
-- {
-- .name = "User FS",
-- .size = 0x003e0000,
-- .offset = 0x20000,},
-- {
-- .name = "boot code",
-- .size = 0x100000,
-- .offset = 0x400000,
-- .mask_flags = MTD_WRITEABLE},
-- {
-- .name = "raw/kernel",
-- .size = 0x300000,
-- .offset = 0x500000}
--};
--
--#elif defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100)
--
--#if defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER)
--/* both 32MB banks will be used. Combine the first 32MB bank and the
-- * first 28MB of the second bank together into a single jffs/jffs2
-- * partition.
-- */
--#define WINDOW_ADDR 0x1C000000
--#define WINDOW_SIZE 0x4000000
--static struct mtd_partition pb1xxx_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x3c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = 0x3c00000,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = 0x02c0000,
-- .offset = 0x3d00000
-- }
--};
--#elif defined(CONFIG_MTD_PB1500_BOOT) && !defined(CONFIG_MTD_PB1500_USER)
--#define WINDOW_ADDR 0x1E000000
--#define WINDOW_SIZE 0x2000000
--static struct mtd_partition pb1xxx_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x1c00000,
-- .offset = 0x0000000
-- },{
-- .name = "yamon",
-- .size = 0x0100000,
-- .offset = 0x1c00000,
-- .mask_flags = MTD_WRITEABLE
-- },{
-- .name = "raw kernel",
-- .size = 0x02c0000,
-- .offset = 0x1d00000
-- }
--};
--#elif !defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER)
--#define WINDOW_ADDR 0x1C000000
--#define WINDOW_SIZE 0x2000000
--static struct mtd_partition pb1xxx_partitions[] = {
-- {
-- .name = "User FS",
-- .size = 0x1e00000,
-- .offset = 0x0000000
-- },{
-- .name = "raw kernel",
-- .size = 0x0200000,
-- .offset = 0x1e00000,
-- }
--};
--#else
--#error MTD_PB1500 define combo error /* should never happen */
--#endif
--#else
--#error Unsupported board
--#endif
--
--#define NAME "Pb1x00 Linux Flash"
--#define PADDR WINDOW_ADDR
--#define BUSWIDTH 4
--#define SIZE WINDOW_SIZE
--#define PARTITIONS 4
--
--static struct map_info pb1xxx_mtd_map = {
-- .name = NAME,
-- .size = SIZE,
-- .bankwidth = BUSWIDTH,
-- .phys = PADDR,
--};
--
--static struct mtd_info *pb1xxx_mtd;
--
--int __init pb1xxx_mtd_init(void)
--{
-- struct mtd_partition *parts;
-- int nb_parts = 0;
-- char *part_type;
--
-- /*
-- * Static partition definition selection
-- */
-- part_type = "static";
-- parts = pb1xxx_partitions;
-- nb_parts = ARRAY_SIZE(pb1xxx_partitions);
--
-- /*
-- * Now let's probe for the actual flash. Do it here since
-- * specific machine settings might have been set above.
-- */
-- printk(KERN_NOTICE "Pb1xxx flash: probing %d-bit flash bus\n",
-- BUSWIDTH*8);
-- pb1xxx_mtd_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE);
--
-- simple_map_init(&pb1xxx_mtd_map);
--
-- pb1xxx_mtd = do_map_probe("cfi_probe", &pb1xxx_mtd_map);
-- if (!pb1xxx_mtd) return -ENXIO;
-- pb1xxx_mtd->owner = THIS_MODULE;
--
-- add_mtd_partitions(pb1xxx_mtd, parts, nb_parts);
-- return 0;
--}
--
--static void __exit pb1xxx_mtd_cleanup(void)
--{
-- if (pb1xxx_mtd) {
-- del_mtd_partitions(pb1xxx_mtd);
-- map_destroy(pb1xxx_mtd);
-- iounmap((void *) pb1xxx_mtd_map.virt);
-- }
--}
--
--module_init(pb1xxx_mtd_init);
--module_exit(pb1xxx_mtd_cleanup);
--
--MODULE_AUTHOR("Pete Popov");
--MODULE_DESCRIPTION("Pb1xxx CFI map driver");
--MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/mtd/nand/au1550nd.c linux_HEAD/drivers/mtd/nand/au1550nd.c
---- linux-2.6.12/drivers/mtd/nand/au1550nd.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/mtd/nand/au1550nd.c 2005-04-14 16:40:15.000000000 +0200
-@@ -11,6 +11,7 @@
- *
- */
-
-+#include <linux/config.h>
- #include <linux/slab.h>
- #include <linux/init.h>
- #include <linux/module.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/net/Kconfig linux_HEAD/drivers/net/Kconfig
---- linux-2.6.12/drivers/net/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/Kconfig 2005-07-10 12:16:38.000000000 +0200
-@@ -425,6 +425,14 @@ config MIPS_JAZZ_SONIC
- This is the driver for the onboard card of MIPS Magnum 4000,
- Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
-
-+config GALILEO_64240_ETH
-+ tristate "Galileo GT64240 Ethernet support"
-+ depends on NET_ETHERNET && MOMENCO_OCELOT_G
-+ select MII
-+ help
-+ This is the driver for the ethernet interfaces integrated into
-+ the Galileo (now Marvell) GT64240 chipset.
-+
- config MIPS_GT96100ETH
- bool "MIPS GT96100 Ethernet support"
- depends on NET_ETHERNET && MIPS_GT96100
-@@ -439,10 +447,6 @@ config MIPS_AU1X00_ENET
- If you have an Alchemy Semi AU1X00 based system
- say Y. Otherwise, say N.
-
--config NET_SB1250_MAC
-- tristate "SB1250 Ethernet support"
-- depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC
--
- config SGI_IOC3_ETH
- bool "SGI IOC3 Ethernet"
- depends on NET_ETHERNET && PCI && SGI_IP27
-@@ -1923,6 +1927,10 @@ config R8169_NAPI
-
- If in doubt, say N.
-
-+config NET_SB1250_MAC
-+ tristate "SB1250 Ethernet support"
-+ depends on SIBYTE_SB1xxx_SOC
-+
- config R8169_VLAN
- bool "VLAN support"
- depends on R8169 && VLAN_8021Q
-@@ -2057,8 +2065,8 @@ config MV643XX_ETH
- depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM
- help
- This driver supports the gigabit Ethernet on the Marvell MV643XX
-- chipset which is used in the Momenco Ocelot C and Jaguar ATX and
-- Pegasos II, amongst other PPC and MIPS boards.
-+ chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX
-+ and Pegasos II, amongst other PPC and MIPS boards.
-
- config MV643XX_ETH_0
- bool "MV-643XX Port 0"
-@@ -2081,6 +2089,20 @@ config MV643XX_ETH_2
- This enables support for Port 2 of the Marvell MV643XX Gigabit
- Ethernet.
-
-+config BIG_SUR_FE
-+ bool "PMC-Sierra TITAN Fast Ethernet Support"
-+ depends on NET_ETHERNET && PMC_BIG_SUR
-+ help
-+ This enables support for the the integrated ethernet of
-+ PMC-Sierra's Big Sur SoC.
-+
-+config TITAN_GE
-+ bool "PMC-Sierra TITAN Gigabit Ethernet Support"
-+ depends on PMC_YOSEMITE
-+ help
-+ This enables support for the the integrated ethernet of
-+ PMC-Sierra's Titan SoC.
-+
- endmenu
-
- #
-diff -urpNX dontdiff linux-2.6.12/drivers/net/Makefile linux_HEAD/drivers/net/Makefile
---- linux-2.6.12/drivers/net/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/Makefile 2005-07-01 12:09:45.000000000 +0200
-@@ -100,6 +100,11 @@ obj-$(CONFIG_NE_H8300) += ne-h8300.o 839
-
- obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
-
-+obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o
-+obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o
-+obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o
-+obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
-+
- obj-$(CONFIG_PPP) += ppp_generic.o slhc.o
- obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
- obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
-diff -urpNX dontdiff linux-2.6.12/drivers/net/au1000_eth.c linux_HEAD/drivers/net/au1000_eth.c
---- linux-2.6.12/drivers/net/au1000_eth.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/au1000_eth.c 2005-04-14 16:40:17.000000000 +0200
-@@ -32,6 +32,7 @@
- *
- */
-
-+#include <linux/config.h>
- #include <linux/module.h>
- #include <linux/kernel.h>
- #include <linux/sched.h>
-@@ -151,13 +152,6 @@ struct au1000_private *au_macs[NUM_ETH_I
- SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
- SUPPORTED_Autoneg
-
--static char *phy_link[] =
--{ "unknown",
-- "10Base2", "10BaseT",
-- "AUI",
-- "100BaseT", "100BaseTX", "100BaseFX"
--};
--
- int bcm_5201_init(struct net_device *dev, int phy_addr)
- {
- s16 data;
-@@ -785,6 +779,7 @@ static struct mii_chip_info {
- {"Broadcom BCM5201 10/100 BaseT PHY",0x0040,0x6212, &bcm_5201_ops,0},
- {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0},
- {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1},
-+ {"NS DP83847 PHY", 0x2000, 0x5c30, &bcm_5201_ops ,0},
- {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0},
- {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0},
- {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0},
-@@ -1045,7 +1040,7 @@ found:
- #endif
-
- if (aup->mii->chip_info == NULL) {
-- printk(KERN_ERR "%s: Au1x No MII transceivers found!\n",
-+ printk(KERN_ERR "%s: Au1x No known MII transceivers found!\n",
- dev->name);
- return -1;
- }
-@@ -1546,6 +1541,9 @@ au1000_probe(u32 ioaddr, int irq, int po
- printk(KERN_ERR "%s: out of memory\n", dev->name);
- goto err_out;
- }
-+ aup->mii->next = NULL;
-+ aup->mii->chip_info = NULL;
-+ aup->mii->status = 0;
- aup->mii->mii_control_reg = 0;
- aup->mii->mii_data_reg = 0;
-
-diff -urpNX dontdiff linux-2.6.12/drivers/net/big_sur_ge.c linux_HEAD/drivers/net/big_sur_ge.c
---- linux-2.6.12/drivers/net/big_sur_ge.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/big_sur_ge.c 2005-02-17 21:49:47.000000000 +0100
-@@ -0,0 +1,2005 @@
-+/*
-+ * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
-+ * Copyright (C) 2003 Ralf Baechle (ralf at linux-mips.org)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ */
-+
-+/*************************************************************************
-+ * Description :
-+ *
-+ * The driver has three modes of operation: FIFO non-DMA, Simple DMA
-+ * and SG DMA. There is also a Polled mode and an Interrupt mode of
-+ * operation. SG DMA should do zerocopy and check offload. Probably,
-+ * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy
-+ * case on the Tx and the Rx.
-+ *
-+ * We turn on Simple DMA and interrupt mode. Although, support has been
-+ * added for the SG mode also but not for the polled mode. This is a
-+ * Fast Ethernet driver although there will be support for Gigabit soon.
-+ *
-+ * The driver is divided into two parts: Hardware dependent and a
-+ * Hardware independent. There is currently no support for checksum offload
-+ * zerocopy and Rx NAPI. There is support for Interrupt Mitigation.
-+ ****************************************************************************/
-+
-+/*************************************************************
-+ * Hardware Indepenent Part of the driver
-+ *************************************************************/
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/mii.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+
-+#include "big_sur_ge.h"
-+
-+#define TX_TIMEOUT (60*HZ) /* Transmission timeout is 60 seconds. */
-+
-+static struct net_device *dev_list = NULL;
-+static DEFINE_SPINLOCK(dev_lock);
-+
-+typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
-+
-+/* Big Sur Ethernet MAC structure */
-+struct big_sur_ge_enet {
-+ struct net_device_stats stats; /* Statistics for this device */
-+ struct net_device *next_dev; /* The next device in dev_list */
-+ struct timer_list phy_timer; /* PHY monitoring timer */
-+ u32 index; /* Which interface is this */
-+ u32 save_base_address; /* Saved physical base address */
-+ struct sk_buff *saved_skb; /* skb being transmitted */
-+ spinlock_t lock; /* For atomic access to saved_skb */
-+ u8 mii_addr; /* The MII address of the PHY */
-+ big_sur_ge emac; /* GE driver structure */
-+};
-+
-+/* Manish : For testing purposes only */
-+static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55";
-+
-+/*********************************************************************
-+ * Function Prototypes (whole bunch of them)
-+ *********************************************************************/
-+unsigned long big_sur_ge_dma_control(xdma_channel *);
-+void big_sur_ge_dma_reset(xdma_channel *);
-+static void handle_fifo_intr(big_sur_ge *);
-+void big_sur_ge_check_fifo_recv_error(big_sur_ge *);
-+void big_sur_ge_check_fifo_send_error(big_sur_ge *);
-+static int big_sur_ge_config_fifo(big_sur_ge *);
-+big_sur_ge_config *big_sur_ge_lookup_config(unsigned int);
-+static int big_sur_ge_config_dma(big_sur_ge *);
-+void big_sur_ge_enet_reset(big_sur_ge *);
-+void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
-+
-+/*********************************************************************
-+ * DMA Channel Initialization
-+ **********************************************************************/
-+static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address)
-+{
-+ dma->reg_base_address = base_address;
-+ dma->get_ptr = NULL;
-+ dma->put_ptr = NULL;
-+ dma->commit_ptr = NULL;
-+ dma->last_ptr = NULL;
-+ dma->total_desc_count = (unsigned long) NULL;
-+ dma->active_desc_count = (unsigned long) NULL;
-+ dma->ready = 1; /* DMA channel is ready */
-+
-+ big_sur_ge_dma_reset(dma);
-+
-+ return 0;
-+}
-+
-+/*********************************************************************
-+ * Is the DMA channel ready yet ?
-+ **********************************************************************/
-+static int big_sur_ge_dma_ready(xdma_channel * dma)
-+{
-+ return dma->ready == 1;
-+}
-+
-+/*********************************************************************
-+ * Perform the self test on the DMA channel
-+ **********************************************************************/
-+#define BIG_SUR_GE_CONTROL_REG_RESET_MASK 0x98000000
-+
-+static int big_sur_ge_dma_self_test(xdma_channel * dma)
-+{
-+ unsigned long reg_data;
-+
-+ big_sur_ge_dma_reset(dma);
-+
-+ reg_data = big_sur_ge_dma_control(dma);
-+ if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
-+ printk(KERN_ERR "DMA Channel Self Test Failed \n");
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+/*********************************************************************
-+ * Reset the DMA channel
-+ **********************************************************************/
-+static void big_sur_ge_dma_reset(xdma_channel * dma)
-+{
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
-+ BIG_SUR_GE_RESET_MASK);
-+}
-+
-+/*********************************************************************
-+ * Get control of the DMA channel
-+ **********************************************************************/
-+static unsigned long big_sur_ge_dma_control(xdma_channel * dma)
-+{
-+ return BIG_SUR_GE_READ(dma->reg_base_address +
-+ BIG_SUR_GE_DMAC_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set control of the DMA channel
-+ **********************************************************************/
-+static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control)
-+{
-+ BIG_SUR_GE_WRITE(dma->reg_base_address +
-+ BIG_SUR_GE_DMAC_REG_OFFSET, control);
-+}
-+
-+/*********************************************************************
-+ * Get the status of the DMA channel
-+ *********************************************************************/
-+static unsigned long big_sur_ge_dma_status(xdma_channel * dma)
-+{
-+ return BIG_SUR_GE_READ(dma->reg_base_address +
-+ BIG_SUR_GE_DMAS_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set the interrupt status of the DMA channel
-+ *********************************************************************/
-+static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status)
-+{
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET,
-+ status);
-+}
-+
-+/*********************************************************************
-+ * Get the interrupt status of the DMA channel
-+ *********************************************************************/
-+static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma)
-+{
-+ return BIG_SUR_GE_READ(dma->reg_base_address +
-+ BIG_SUR_GE_IS_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set the Interrupt Enable
-+ *********************************************************************/
-+static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable)
-+{
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET,
-+ enable);
-+}
-+
-+/*********************************************************************
-+ * Get the Interrupt Enable field to make a check
-+ *********************************************************************/
-+static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma)
-+{
-+ return BIG_SUR_GE_READ(dma->reg_base_address +
-+ BIG_SUR_GE_IE_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Transfer the data over the DMA channel
-+ *********************************************************************/
-+static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source,
-+ unsigned long *dest, unsigned long length)
-+{
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
-+ (unsigned long) source);
-+
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
-+ (unsigned long) dest);
-+
-+ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
-+ length);
-+}
-+
-+/*********************************************************************
-+ * Get the DMA descriptor
-+ *********************************************************************/
-+static int big_sur_ge_get_descriptor(xdma_channel * dma,
-+ xbuf_descriptor ** buffer_desc)
-+{
-+ unsigned long reg_data;
-+
-+ reg_data = xbuf_descriptor_GetControl(dma->get_ptr);
-+ xbuf_descriptor_SetControl(dma->get_ptr, reg_data |
-+ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+ *buffer_desc = dma->get_ptr;
-+
-+ dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr);
-+ dma->active_desc_count--;
-+
-+ return 0;
-+}
-+
-+/*********************************************************************
-+ * Get the packet count
-+ *********************************************************************/
-+static int big_sur_ge_get_packet_count(xdma_channel * dma)
-+{
-+ return (BIG_SUR_GE_READ
-+ (dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET));
-+}
-+
-+/*********************************************************************
-+ * Descrement the packet count
-+ *********************************************************************/
-+static void big_sur_ge_decr_packet_count(xdma_channel * dma)
-+{
-+ unsigned long reg_data;
-+
-+ reg_data =
-+ BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET);
-+ if (reg_data > 0)
-+ BIG_SUR_GE_WRITE(dma->base_address +
-+ BIG_SUR_GE_UPC_REG_OFFSET, 1);
-+}
-+
-+/****************************************************************************
-+ * Start of the code that deals with the Packet Fifo
-+ *****************************************************************************/
-+
-+/****************************************************************************
-+ * Init the packet fifo
-+ ****************************************************************************/
-+static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data)
-+{
-+ fifo->reg_base_addr = reg;
-+ fifo->data_base_address = data;
-+ fifo->ready_status = 1;
-+
-+ BIG_SUR_GE_FIFO_RESET(fifo);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+ * Packet fifo self test
-+ ****************************************************************************/
-+static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type)
-+{
-+ unsigned long reg_data;
-+
-+ BIG_SUR_GE_FIFO_RESET(fifo);
-+ reg_data =
-+ BIG_SUR_GE_READ(fifo->reg_base_addr +
-+ BIG_SUR_GE_COUNT_STATUS_REG_OFFSET);
-+
-+ if (type == BIG_SUR_GE_READ_FIFO_TYPE) {
-+ if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) {
-+ printk(KERN_ERR "Read FIFO not empty \n");
-+ return -1;
-+ }
-+ } else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) {
-+ printk(KERN_ERR "Write FIFO is full \n");
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+ * Packet FIFO read
-+ ****************************************************************************/
-+static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
-+{
-+ unsigned long fifo_count, word_count, extra_byte;
-+ unsigned long *buffer_data = (unsigned long *) buffer;
-+
-+ fifo_count =
-+ BIG_SUR_GE_READ(fifo->reg_base_addr +
-+ BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
-+ fifo_count &= BIG_SUR_GE_COUNT_MASK;
-+
-+ if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
-+ return -1;
-+
-+ word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+ extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+
-+ for (fifo_count = 0; fifo_count < word_count; fifo_count++)
-+ buffer_data[fifo_count] =
-+ BIG_SUR_GE_READ(fifo->reg_base_addr);
-+
-+ if (extra_byte > 0) {
-+ unsigned long last_word;
-+ int *extra_buffer_data =
-+ (int *) (buffer_data + word_count);
-+
-+ last_word = BIG_SUR_GE_READ(fifo->data_base_address);
-+ if (extra_byte == 1)
-+ extra_buffer_data[0] = (int) (last_word << 24);
-+ else if (extra_byte == 2) {
-+ extra_buffer_data[0] = (int) (last_word << 24);
-+ extra_buffer_data[1] = (int) (last_word << 16);
-+ } else if (extra_byte == 3) {
-+ extra_buffer_data[0] = (int) (last_word << 24);
-+ extra_buffer_data[1] = (int) (last_word << 16);
-+ extra_buffer_data[2] = (int) (last_word << 8);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/*****************************************************************************
-+ * Write the data into the packet fifo
-+ *****************************************************************************/
-+static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
-+{
-+ unsigned long fifo_count, word_count, extra_byte;
-+ unsigned long *buffer_data = (unsigned long *) buffer;
-+
-+ fifo_count =
-+ BIG_SUR_GE_READ(fifo->reg_base_addr +
-+ BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
-+ fifo_count &= BIG_SUR_GE_COUNT_MASK;
-+
-+ word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+ extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+
-+ /* You should see what the ppc driver does here. It just slobbers */
-+ if (extra_byte > 0)
-+ if (fifo_count > (word_count + 1)) {
-+ printk(KERN_ERR
-+ "No room in the packet send fifo \n");
-+ return -1;
-+ }
-+
-+ for (fifo_count = 0; fifo_count < word_count; fifo_count++)
-+ BIG_SUR_GE_WRITE(fifo->data_base_address,
-+ buffer_data[fifo_count]);
-+
-+
-+ if (extra_byte > 0) {
-+ unsigned long last_word = 0;
-+ int *extra_buffer_data =
-+ (int *) (buffer_data + word_count);
-+
-+ if (extra_byte == 1)
-+ last_word = extra_buffer_data[0] << 24;
-+ else if (extra_byte == 2)
-+ last_word = (extra_buffer_data[0] << 24 |
-+ extra_buffer_data[1] << 16);
-+
-+ else if (extra_byte == 3)
-+ last_word = (extra_buffer_data[0] << 24 |
-+ extra_buffer_data[1] << 16 |
-+ extra_buffer_data[2] << 8);
-+
-+
-+ BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
-+ }
-+
-+ return 0;
-+}
-+
-+
-+/*****************************************************************************
-+ * Interrupt handlers: We handle any errors associated with the FIFO.
-+ * FIFO is for simple dma case and we do want to handle the simple DMA
-+ * case. We dont handle the Scatter Gather DMA for now since it is not working.
-+ ******************************************************************************/
-+
-+/*********************************************************************************
-+ * FIFO send for Simple DMA with Interrupts
-+ **********************************************************************************/
-+static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer,
-+ unsigned long byte_cnt)
-+{
-+ unsigned long int_status, reg_data;
-+
-+ /* Silly checks here that we really dont need */
-+ if (!emac->started)
-+ return -1;
-+
-+ if (emac->polled)
-+ return -1;
-+
-+ if (emac->dma_sg)
-+ return -1;
-+
-+ int_status =
-+ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+ if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
-+ printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
-+ return -1;
-+ }
-+
-+ /*
-+ * Write the data to the FIFO in the hardware
-+ */
-+ if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) *
-+ sizeof(unsigned long)) < byte_cnt) {
-+ printk(KERN_ERR "Send FIFO on chip is full \n");
-+ return -1;
-+ }
-+
-+ if (big_sur_ge_dma_status(&emac->send_channel) &
-+ BIG_SUR_GE_DMASR_BUSY_MASK) {
-+ printk(KERN_ERR "Send channel FIFO engine busy \n");
-+ return -1;
-+ }
-+
-+ big_sur_ge_set_dma_control(&emac->send_channel,
-+ BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
-+ BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
-+ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+ big_sur_ge_dma_transfer(&emac->send_channel,
-+ (unsigned long *) buffer,
-+ (unsigned long *) (emac->base_address +
-+ BIG_SUR_GE_PFIFO_TXDATA_OFFSET),
-+ byte_cnt);
-+
-+ reg_data = big_sur_ge_dma_status(&emac->send_channel);
-+ while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
-+ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+ if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
-+ break;
-+ }
-+
-+ if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
-+ (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
-+ printk(KERN_ERR "Send side DMA error \n");
-+ return -1;
-+ }
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET,
-+ byte_cnt);
-+
-+ return 0;
-+}
-+
-+/*************************************************************************
-+ * FIFO receive for Simple DMA case
-+ *************************************************************************/
-+static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer,
-+ unsigned long *byte_cnt)
-+{
-+ unsigned long int_status, reg_data;
-+
-+ /* Silly checks here that we really dont need */
-+ if (!emac->started)
-+ return -1;
-+
-+ if (emac->polled)
-+ return -1;
-+
-+ if (emac->dma_sg)
-+ return -1;
-+
-+ if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
-+ return -1;
-+
-+ int_status =
-+ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+ if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_IISR_OFFSET,
-+ BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
-+ return -1;
-+ }
-+
-+ if (big_sur_ge_dma_status(&emac->recv_channel) &
-+ BIG_SUR_GE_DMASR_BUSY_MASK) {
-+ printk(KERN_ERR "Rx side DMA Engine busy \n");
-+ return -1;
-+ }
-+
-+ if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) ==
-+ 0) {
-+ printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
-+ return -1;
-+ }
-+
-+ /* For the simple DMA case only */
-+ big_sur_ge_set_dma_control(&emac->recv_channel,
-+ BIG_SUR_GE_DMACR_DEST_INCR_MASK |
-+ BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
-+ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+ if (packet_fifo_read(&emac->recv_fifo, buffer,
-+ BIG_SUR_GE_READ(emac->base_address +
-+ BIG_SUR_GE_RPLR_OFFSET)) ==
-+ -1) {
-+ printk(KERN_ERR "Not enough space in the FIFO \n");
-+ return -1;
-+ }
-+
-+ big_sur_ge_dma_transfer(&emac->recv_channel,
-+ (unsigned long *) (emac->base_address +
-+ BIG_SUR_GE_PFIFO_RXDATA_OFFSET),
-+ (unsigned long *)
-+ buffer,
-+ BIG_SUR_GE_READ(emac->base_address +
-+ BIG_SUR_GE_RPLR_OFFSET));
-+
-+ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+ while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
-+ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+ if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
-+ break;
-+ }
-+
-+ if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
-+ (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
-+ printk(KERN_ERR "DMA Bus Error \n");
-+ return -1;
-+ }
-+
-+ *byte_cnt =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
-+
-+ return 0;
-+}
-+
-+static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id,
-+ struct pt_regs *regs)
-+{
-+ struct net_device *netdev = dev_id;
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ big_sur_ge *emac = (big_sur_ge *)emac_ptr;
-+ void *emac_ptr = &lp->emac;
-+ unsigned long int_status;
-+
-+ int_status =
-+ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET);
-+ if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
-+ handle_fifo_intr(emac);
-+
-+ if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+ big_sur_ge_check_fifo_recv_error(emac);
-+
-+ if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
-+ big_sur_ge_check_fifo_send_error(emac);
-+
-+ if (int_status & XIIF_V123B_ERROR_MASK)
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_DISR_OFFSET,
-+ XIIF_V123B_ERROR_MASK);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/****************************************************************************
-+ * Set the FIFO send handler
-+ ***************************************************************************/
-+static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back,
-+ big_sur_fifo_handler function)
-+{
-+ emac->big_sur_ge_fifo_send_handler = function;
-+ emac->fifo_send_ref = call_back;
-+}
-+
-+/****************************************************************************
-+ * Set the FIFO recv handler
-+ ***************************************************************************/
-+static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back,
-+ big_sur_fifo_handler function)
-+{
-+ emac->big_sur_ge_fifo_recv_handler = function;
-+ emac->fifo_recv_ref = call_back;
-+}
-+
-+/****************************************************************************
-+ * Main Fifo intr handler
-+ ***************************************************************************/
-+static void handle_fifo_intr(big_sur_ge * emac)
-+{
-+ unsigned long int_status;
-+
-+ /* Ack the interrupts asap */
-+ int_status =
-+ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
-+ int_status);
-+
-+ /* Process the Rx side */
-+ if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
-+ emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref);
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_IISR_OFFSET,
-+ BIG_SUR_GE_EIR_RECV_DONE_MASK);
-+ }
-+
-+ if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
-+ /* We dont collect stats and hence we dont need to get status */
-+
-+ emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref);
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_IISR_OFFSET,
-+ BIG_SUR_GE_EIR_XMIT_DONE_MASK);
-+ }
-+
-+ big_sur_ge_check_mac_error(emac, int_status);
-+}
-+
-+/******************************************************************
-+ * Handle the Receive side DMA interrupts. The PPC driver has
-+ * callbacks all over the place. This has been eliminated here by
-+ * using the following approach:
-+ *
-+ * The ISR is set to the main interrrupt handler. This will handle
-+ * all the interrupts including the ones for DMA. In this main isr,
-+ * we determine if we need to call recv or send side intr functions.
-+ * Pretty complex but thats the way it is now.
-+ *******************************************************************/
-+static void big_sur_ge_handle_recv_intr(big_sur_ge * emac)
-+{
-+ unsigned long int_status;
-+
-+ int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
-+ if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
-+ BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
-+ u32 num_packets;
-+ u32 num_processed;
-+ u32 num_buffers;
-+ u32 num_bytes;
-+ xbuf_descriptor *first_desc_ptr = NULL;
-+ xbuf_descriptor *buffer_desc;
-+ int is_last = 0;
-+
-+ /* The number of packets we need to process on the Rx */
-+ num_packets =
-+ big_sur_ge_get_packet_count(&emac->recv_channel);
-+
-+ for (num_processed = 0; num_processed < num_packets;
-+ num_processed++) {
-+ while (!is_last) {
-+ if (big_sur_ge_get_descriptor
-+ (&emac->recv_channel,
-+ &buffer_desc) == -1)
-+ break;
-+
-+ if (first_desc_ptr == NULL)
-+ first_desc_ptr = buffer_desc;
-+
-+ num_bytes +=
-+ xbuf_descriptor_GetLength(buffer_desc);
-+
-+ if (xbuf_descriptor_IsLastStatus
-+ (buffer_desc)) {
-+ is_last = 1;
-+ }
-+
-+ num_buffers++;
-+ }
-+
-+ /* Number of buffers is always 1 since we dont do SG */
-+
-+ /*
-+ * Only for SG DMA which is currently not supported. In the
-+ * future, as we have SG channel working, we will code this
-+ * receive side routine. For now, do nothing. This is never
-+ * called from FIFO mode - Manish
-+ */
-+ big_sur_ge_decr_packet_count(&emac->recv_channel);
-+ }
-+ }
-+
-+ /* Ack the interrupts */
-+ big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
-+
-+ if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
-+ /* We need a reset here */
-+ }
-+
-+ big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
-+}
-+
-+/****************************************************************
-+ * Handle the send side DMA interrupt
-+ ****************************************************************/
-+static void big_sur_ge_handle_send_intr(big_sur_ge * emac)
-+{
-+ unsigned long int_status;
-+
-+ int_status = big_sur_ge_get_intr_status(&emac->send_channel);
-+
-+ if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
-+ BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
-+ unsigned long num_frames = 0;
-+ unsigned long num_processed = 0;
-+ unsigned long num_buffers = 0;
-+ unsigned long num_bytes = 0;
-+ unsigned long is_last = 0;
-+ xbuf_descriptor *first_desc_ptr = NULL;
-+ xbuf_descriptor *buffer_desc;
-+
-+ num_frames =
-+ big_sur_ge_get_packet_count(&emac->send_channel);
-+
-+ for (num_processed = 0; num_processed < num_frames;
-+ num_processed++) {
-+ while (!is_last) {
-+ if (big_sur_ge_get_descriptor
-+ (&emac->send_channel, &buffer_desc)
-+ == -1) {
-+ break;
-+ }
-+
-+ if (first_desc_ptr == NULL)
-+ first_desc_ptr = buffer_desc;
-+
-+ num_bytes +=
-+ xbuf_descriptor_GetLength(buffer_desc);
-+ if (xbuf_descriptor_IsLastControl
-+ (buffer_desc))
-+ is_last = 1;
-+
-+ num_buffers++;
-+ }
-+
-+ /*
-+ * Only for SG DMA which is currently not supported. In the
-+ * future, as we have SG channel working, we will code this
-+ * receive side routine. For now, do nothing. This is never
-+ * called from FIFO mode - Manish
-+ */
-+ big_sur_ge_decr_packet_count(&emac->send_channel);
-+ }
-+ }
-+
-+ /* Ack the interrupts and reset DMA channel if necessary */
-+ big_sur_ge_set_intr_status(&emac->send_channel, int_status);
-+ if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
-+ /* Manish : need reset */
-+ }
-+
-+ big_sur_ge_set_intr_status(&emac->send_channel, int_status);
-+}
-+
-+/*****************************************************************
-+ * For now, the MAC address errors dont trigger a update of the
-+ * stats. There is no stats framework in place. Hence, we just
-+ * check for the errors below and do a reset if needed.
-+ *****************************************************************/
-+static void big_sur_ge_check_mac_error(big_sur_ge * emac,
-+ unsigned long int_status)
-+{
-+ if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
-+ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
-+ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
-+ BIG_SUR_GE_EIR_RECV_ERROR_MASK |
-+ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
-+ BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
-+ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
-+ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
-+ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
-+ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
-+ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
-+ BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
-+ BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
-+ BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
-+ BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) {
-+
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_IIER_OFFSET, 0);
-+ /*
-+ * Manish Reset the MAC here
-+ */
-+ }
-+}
-+
-+/*****************************************************************
-+ * Check for FIFO Recv errors
-+ *****************************************************************/
-+static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac)
-+{
-+ if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
-+ unsigned long intr_enable;
-+
-+ intr_enable =
-+ BIG_SUR_GE_READ(emac->base_address +
-+ XIIF_V123B_DIER_OFFSET);
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_DIER_OFFSET,
-+ intr_enable &
-+ ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
-+
-+ }
-+}
-+
-+/*****************************************************************
-+ * Check for FIFO Send errors
-+ *****************************************************************/
-+static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac)
-+{
-+ if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
-+ unsigned long intr_enable;
-+
-+ intr_enable =
-+ BIG_SUR_GE_READ(emac->base_address +
-+ XIIF_V123B_DIER_OFFSET);
-+ BIG_SUR_GE_WRITE(emac->base_address +
-+ XIIF_V123B_DIER_OFFSET,
-+ intr_enable &
-+ ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
-+ }
-+}
-+
-+/*****************************************************************
-+ * GE unit init
-+ ****************************************************************/
-+static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id)
-+{
-+ unsigned long reg_data;
-+ big_sur_ge_config *config;
-+ int err;
-+
-+ /* Assume that the device has been stopped */
-+
-+ config = big_sur_ge_lookup_config(device_id);
-+ if (config == NULL)
-+ return -1;
-+
-+ emac->ready = 0;
-+ emac->started = 0;
-+ emac->dma_sg = 0; /* This MAC has no support for Scatter Gather DMA */
-+ emac->has_mii = config->has_mii;
-+ emac->has_mcast_hash_table = 0;
-+ emac->dma_config = config->dma_config;
-+
-+ /*
-+ * Initialize the FIFO send and recv handlers to the stub handlers.
-+ * We only deal with the FIFO mode of operation since SG is not supported.
-+ * Also, there is no error handler. We try to handle as much of error as
-+ * possible and then return. No error codes also.
-+ */
-+
-+ emac->base_address = config->base_address;
-+
-+ if (big_sur_ge_config_dma(emac) == -1)
-+ return -1;
-+
-+ err = big_sur_ge_config_fifo(emac);
-+ if (err == -1)
-+ return err;
-+
-+ /* Now, we know that the FIFO initialized successfully. So, set the ready flag */
-+ emac->ready = 1;
-+
-+ /* Do we need a PHY reset here also. It did cause problems on some boards */
-+ big_sur_ge_enet_reset(emac);
-+
-+ /* PHY reset code. Remove if causes a problem on the board */
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+ reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+ reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+
-+ return 0;
-+}
-+
-+/*******************************************************************
-+ * Start the GE unit for Tx, Rx and Interrupts
-+ *******************************************************************/
-+static int big_sur_ge_start(big_sur_ge * emac)
-+{
-+ unsigned long reg_data;
-+
-+ /*
-+ * Basic mode of operation is polled and interrupt mode. We disable the polled
-+ * mode for good. We may use the polled mode for Rx NAPI but that does not
-+ * require all the interrupts to be disabled
-+ */
-+
-+ emac->polled = 0;
-+
-+ /*
-+ * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working
-+ * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may
-+ * not use FIFO at all. So, we enable the interrupts below
-+ */
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
-+ BIG_SUR_GE_IPIF_FIFO_DFT_MASK |
-+ XIIF_V123B_ERROR_MASK);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
-+ BIG_SUR_GE_EIR_DFT_FIFO_MASK);
-+
-+ /* Toggle the started flag */
-+ emac->started = 1;
-+
-+ /* Start the Tx and Rx units respectively */
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+ reg_data &=
-+ ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK |
-+ BIG_SUR_GE_ECR_RECV_RESET_MASK);
-+ reg_data |=
-+ (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
-+ BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+
-+ return 0;
-+}
-+
-+/**************************************************************************
-+ * Stop the GE unit
-+ **************************************************************************/
-+static int big_sur_ge_stop(big_sur_ge * emac)
-+{
-+ unsigned long reg_data;
-+
-+ /* We assume that the device is not already stopped */
-+ if (!emac->started)
-+ return 0;
-+
-+ /* Disable the Tx and Rx unit respectively */
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+ reg_data &=
-+ ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
-+ BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+
-+ /* Disable the interrupts */
-+ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
-+
-+ /* Toggle the started flag */
-+ emac->started = 0;
-+
-+ return 0;
-+}
-+
-+/************************************************************************
-+ * Reset the GE MAC unit
-+ *************************************************************************/
-+static void big_sur_ge_enet_reset(big_sur_ge * emac)
-+{
-+ unsigned long reg_data;
-+
-+ (void) big_sur_ge_stop(emac);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
-+ XIIF_V123B_RESET_MASK);
-+
-+ /*
-+ * For now, configure the receiver to not strip off FCS and padding since
-+ * this is not currently supported. In the future, just take the default
-+ * and provide the option for the user to change this behavior.
-+ */
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+ reg_data &=
-+ ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK |
-+ BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
-+ reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+}
-+
-+/*************************************************************************
-+ * Set the MAC address of the GE mac unit
-+ *************************************************************************/
-+static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr)
-+{
-+ unsigned long mac_addr = 0;
-+
-+ /* Device is started and so mac address must be set */
-+ if (emac->started == 1)
-+ return 0;
-+
-+ mac_addr = ((addr[0] << 8) | addr[1]);
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET,
-+ mac_addr);
-+
-+ mac_addr |= ((addr[2] << 24) | (addr[3] << 16) |
-+ (addr[4] << 8) | addr[5]);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET,
-+ mac_addr);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+ * Get the MAC address of the GE MAC unit
-+ ***************************************************************************/
-+static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr)
-+{
-+ unsigned long mac_addr_hi, mac_addr_lo;
-+
-+ mac_addr_hi =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
-+ mac_addr_lo =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
-+
-+ addr[0] = (mac_addr_hi >> 8);
-+ addr[1] = mac_addr_hi;
-+
-+ addr[2] = (mac_addr_lo >> 24);
-+ addr[3] = (mac_addr_lo >> 16);
-+ addr[4] = (mac_addr_lo >> 8);
-+ addr[5] = mac_addr_lo;
-+}
-+
-+/*********************************************************************************
-+ * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple
-+ *********************************************************************************/
-+static int big_sur_ge_config_dma(big_sur_ge * emac)
-+{
-+ if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
-+ BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
-+ printk(KERN_ERR "Could not initialize the DMA unit \n");
-+ return -1;
-+ }
-+
-+ if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
-+ BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
-+ printk(KERN_ERR "Could not initialize the DMA unit \n");
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+/******************************************************************************
-+ * Configure the FIFO for simple DMA
-+ ******************************************************************************/
-+static int big_sur_ge_config_fifo(big_sur_ge * emac)
-+{
-+ int err = 0;
-+
-+ err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
-+ BIG_SUR_GE_PFIFO_RXREG_OFFSET,
-+ emac->base_address +
-+ BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
-+
-+ if (err == -1) {
-+ printk(KERN_ERR
-+ "Could not initialize Rx packet FIFO for Simple DMA \n");
-+ return err;
-+ }
-+
-+ err = packet_fifo_init(&emac->send_fifo, emac->base_address +
-+ BIG_SUR_GE_PFIFO_TXREG_OFFSET,
-+ emac->base_address +
-+ BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
-+
-+ if (err == -1) {
-+ printk(KERN_ERR
-+ "Could not initialize Tx packet FIFO for Simple DMA \n");
-+ }
-+
-+ return err;
-+}
-+
-+#define BIG_SUR_GE_NUM_INSTANCES 2
-+
-+
-+/**********************************************************************************
-+ * Look up the config of the MAC
-+ **********************************************************************************/
-+static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id)
-+{
-+ big_sur_ge_config *config = NULL;
-+ int i = 0;
-+
-+ for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) {
-+ /* Manish : Init the config here */
-+ break;
-+ }
-+
-+ return config;
-+}
-+
-+typedef struct {
-+ unsigned long option;
-+ unsigned long mask;
-+} option_map;
-+
-+static option_map option_table[] = {
-+ {BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
-+ {BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
-+ {BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
-+ {BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
-+ {BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
-+ {BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
-+ {BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
-+ {BIG_SUR_GE_INSERT_PAD_OPTION,
-+ BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
-+ {BIG_SUR_GE_INSERT_FCS_OPTION,
-+ BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
-+ {BIG_SUR_GE_INSERT_ADDR_OPTION,
-+ BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
-+ {BIG_SUR_GE_OVWRT_ADDR_OPTION,
-+ BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
-+ {BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
-+ {BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
-+ {BIG_SUR_GE_STRIP_PAD_FCS_OPTION,
-+ BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
-+};
-+
-+#define BIG_SUR_GE_NUM_OPTIONS (sizeof(option_table) / sizeof(option_map))
-+
-+/**********************************************************************
-+ * Set the options for the GE
-+ **********************************************************************/
-+static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag)
-+{
-+ unsigned long reg_data;
-+ unsigned int index;
-+
-+ /* Assume that the device is stopped before calling this function */
-+
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+ for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
-+ if (option_flag & option_table[index].option)
-+ reg_data |= option_table[index].mask;
-+ else
-+ reg_data &= ~(option_table[index].mask);
-+
-+ }
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+ reg_data);
-+
-+ /* No polled option */
-+ emac->polled = 0;
-+
-+ return 0;
-+}
-+
-+/*******************************************************
-+ * Get the options from the GE
-+ *******************************************************/
-+static unsigned long big_sur_ge_get_options(big_sur_ge * emac)
-+{
-+ unsigned long option_flag = 0, reg_data;
-+ unsigned int index;
-+
-+ reg_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+
-+ for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
-+ if (option_flag & option_table[index].option)
-+ reg_data |= option_table[index].mask;
-+ }
-+
-+ /* No polled mode */
-+
-+ return option_flag;
-+}
-+
-+/********************************************************
-+ * Set the Inter frame gap
-+ ********************************************************/
-+static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2)
-+{
-+ unsigned long config;
-+
-+ /* Assume that the device is stopped before calling this */
-+
-+ config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
-+ (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT));
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET,
-+ config);
-+
-+ return 0;
-+}
-+
-+/********************************************************
-+ * Get the Inter frame gap
-+ ********************************************************/
-+static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2)
-+{
-+ unsigned long config;
-+
-+ config =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
-+ *part1 =
-+ ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >>
-+ BIG_SUR_GE_IFGP_PART1_SHIFT);
-+ *part2 =
-+ ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >>
-+ BIG_SUR_GE_IFGP_PART2_SHIFT);
-+}
-+
-+/*******************************************************************
-+ * PHY specific functions for the MAC
-+ *******************************************************************/
-+#define BIG_SUR_GE_MAX_PHY_ADDR 32
-+#define BIG_SUR_GE_MAX_PHY_REG 32
-+
-+/*******************************************************************
-+ * Read the PHY reg
-+ *******************************************************************/
-+static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr,
-+ unsigned long reg_num, unsigned int *data)
-+{
-+ unsigned long mii_control, mii_data;
-+
-+ if (!emac->has_mii)
-+ return -1;
-+
-+ mii_control =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
-+ if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
-+ printk(KERN_ERR "PHY busy \n");
-+ return -1;
-+ }
-+
-+ mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
-+ mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
-+ mii_control |=
-+ (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
-+ BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
-+ mii_control);
-+
-+ while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
-+ if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
-+ break;
-+
-+ mii_data =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
-+ *data = (unsigned int) mii_data;
-+
-+ return 0;
-+}
-+
-+/**********************************************************************
-+ * Write to the PHY register
-+ **********************************************************************/
-+static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr,
-+ unsigned long reg_num, unsigned int data)
-+{
-+ unsigned long mii_control;
-+
-+ if (!emac->has_mii)
-+ return -1;
-+
-+ mii_control =
-+ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
-+ if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
-+ printk(KERN_ERR "PHY busy \n");
-+ return -1;
-+ }
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET,
-+ (unsigned long) data);
-+
-+ mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
-+ mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
-+ mii_control |=
-+ (BIG_SUR_GE_MGTCR_START_MASK |
-+ BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
-+
-+ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
-+ mii_control);
-+
-+ while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
-+ if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
-+ break;
-+
-+ return 0;
-+}
-+
-+
-+
-+
-+
-+
-+/********************************************************************
-+ * The hardware dependent part of the driver begins here
-+ ********************************************************************/
-+
-+
-+/*******************************************************************
-+ * Reset the GE system
-+ *******************************************************************/
-+static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ struct sk_buff *skb;
-+ unsigned long options;
-+ int ifcfg1, ifcfg2;
-+
-+ /* Stop the queue */
-+ netif_stop_queue(netdev);
-+
-+ big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2);
-+ options = big_sur_ge_get_options(&lp->emac);
-+ switch (duplex) {
-+ case HALF_DUPLEX:
-+ options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
-+ break;
-+
-+ case FULL_DUPLEX:
-+ options |= BIG_SUR_GE_FDUPLEX_OPTION;
-+ break;
-+
-+ case UNKNOWN:
-+ break;
-+ }
-+
-+ /* There is no support for SG DMA in a 100 Mpbs NIC */
-+
-+ big_sur_ge_enet_reset(&lp->emac);
-+
-+ /* Set the necessary options for the MAC unit */
-+ big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr);
-+ big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2);
-+ big_sur_ge_set_options(&lp->emac, options);
-+
-+ (void) big_sur_ge_start(&lp->emac);
-+
-+ spin_lock_irq(&lp->lock);
-+ skb = lp->saved_skb;
-+ lp->saved_skb = NULL;
-+ spin_unlock_irq(&lp->lock);
-+
-+ if (skb)
-+ dev_kfree_skb(skb);
-+
-+ /* Wake the queue */
-+ netif_wake_queue(netdev);
-+}
-+
-+/********************************************************************
-+ * Get the PHY status
-+ *******************************************************************/
-+static int big_sur_ge_get_phy_status(struct net_device *netdev,
-+ DUPLEX * duplex, int *linkup)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ unsigned int reg_data;
-+ int err = 0;
-+
-+ err =
-+ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR,
-+ ®_data);
-+ if (err == -1) {
-+ printk(KERN_ERR "%s: Could not read PHY control register",
-+ netdev->name);
-+ return err;
-+ }
-+
-+ if (!(reg_data & BMCR_ANENABLE)) {
-+ if (reg_data & BMCR_FULLDPLX)
-+ *duplex = FULL_DUPLEX;
-+ else
-+ *duplex = HALF_DUPLEX;
-+ } else {
-+ unsigned int advertise, partner, neg;
-+
-+ err =
-+ big_sur_ge_phy_read(&lp->emac, lp->mii_addr,
-+ MII_ADVERTISE, &advertise);
-+ if (err == -1) {
-+ printk(KERN_ERR
-+ "%s: Could not read PHY control register",
-+ netdev->name);
-+ return err;
-+ }
-+
-+ err =
-+ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA,
-+ &partner);
-+ if (err == -1) {
-+ printk(KERN_ERR
-+ "%s: Could not read PHY control register",
-+ netdev->name);
-+ return err;
-+ }
-+
-+ neg = advertise & partner & ADVERTISE_ALL;
-+ if (neg & ADVERTISE_100FULL)
-+ *duplex = FULL_DUPLEX;
-+ else if (neg & ADVERTISE_100HALF)
-+ *duplex = HALF_DUPLEX;
-+ else if (neg & ADVERTISE_10FULL)
-+ *duplex = FULL_DUPLEX;
-+ else
-+ *duplex = HALF_DUPLEX;
-+
-+ err =
-+ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR,
-+ ®_data);
-+ if (err == -1) {
-+ printk(KERN_ERR
-+ "%s: Could not read PHY control register",
-+ netdev->name);
-+ return err;
-+ }
-+
-+ *linkup = (reg_data & BMSR_LSTATUS) != 0;
-+
-+ }
-+ return 0;
-+}
-+
-+/************************************************************
-+ * Poll the MII for duplex and link status
-+ ***********************************************************/
-+static void big_sur_ge_poll_mii(unsigned long data)
-+{
-+ struct net_device *netdev = (struct net_device *) data;
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ unsigned long options;
-+ DUPLEX mac_duplex, phy_duplex;
-+ int phy_carrier, netif_carrier;
-+
-+ if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) ==
-+ -1) {
-+ printk(KERN_ERR "%s: Terminating link monitoring.\n",
-+ netdev->name);
-+ return;
-+ }
-+
-+ options = big_sur_ge_get_options(&lp->emac);
-+ if (options & BIG_SUR_GE_FDUPLEX_OPTION)
-+ mac_duplex = FULL_DUPLEX;
-+ else
-+ mac_duplex = HALF_DUPLEX;
-+
-+ if (mac_duplex != phy_duplex) {
-+ disable_irq(netdev->irq);
-+ big_sur_ge_reset(netdev, phy_duplex);
-+ enable_irq(netdev->irq);
-+ }
-+
-+ netif_carrier = netif_carrier_ok(netdev) != 0;
-+
-+ if (phy_carrier != netif_carrier) {
-+ if (phy_carrier) {
-+ printk(KERN_INFO "%s: Link carrier restored.\n",
-+ netdev->name);
-+ netif_carrier_on(netdev);
-+ } else {
-+ printk(KERN_INFO "%s: Link carrier lost.\n",
-+ netdev->name);
-+ netif_carrier_off(netdev);
-+ }
-+ }
-+
-+ /* Set up the timer so we'll get called again in 2 seconds. */
-+ lp->phy_timer.expires = jiffies + 2 * HZ;
-+ add_timer(&lp->phy_timer);
-+}
-+
-+/**************************************************************
-+ * Open the network interface
-+ *************************************************************/
-+static int big_sur_ge_open(struct net_device *netdev)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ unsigned long options;
-+ DUPLEX phy_duplex, mac_duplex;
-+ int phy_carrier, retval;
-+
-+ (void) big_sur_ge_stop(&lp->emac);
-+
-+ if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
-+ printk(KERN_ERR "%s: Could not set MAC address.\n",
-+ netdev->name);
-+ return -EIO;
-+ }
-+
-+ options = big_sur_ge_get_options(&lp->emac);
-+
-+ retval =
-+ request_irq(netdev->irq, &big_sur_ge_int_handler, 0,
-+ netdev->name, netdev);
-+ if (retval) {
-+ printk(KERN_ERR
-+ "%s: Could not allocate interrupt %d.\n",
-+ netdev->name, netdev->irq);
-+
-+ return retval;
-+ }
-+
-+ if (!
-+ (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier)))
-+ {
-+ if (options & BIG_SUR_GE_FDUPLEX_OPTION)
-+ mac_duplex = FULL_DUPLEX;
-+ else
-+ mac_duplex = HALF_DUPLEX;
-+
-+ if (mac_duplex != phy_duplex) {
-+ switch (phy_duplex) {
-+ case HALF_DUPLEX:
-+ options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
-+ break;
-+ case FULL_DUPLEX:
-+ options |= BIG_SUR_GE_FDUPLEX_OPTION;
-+ break;
-+ case UNKNOWN:
-+ break;
-+ }
-+
-+ big_sur_ge_set_options(&lp->emac, options);
-+ }
-+ }
-+
-+ if (big_sur_ge_start(&lp->emac) == -1) {
-+ printk(KERN_ERR "%s: Could not start device.\n",
-+ netdev->name);
-+ free_irq(netdev->irq, netdev);
-+ return -EBUSY;
-+ }
-+
-+ netif_start_queue(netdev);
-+
-+ lp->phy_timer.expires = jiffies + 2 * HZ;
-+ lp->phy_timer.data = (unsigned long) netdev;
-+ lp->phy_timer.function = &big_sur_ge_poll_mii;
-+ add_timer(&lp->phy_timer);
-+
-+ return 0;
-+}
-+
-+/*********************************************************************
-+ * Close the network device interface
-+ *********************************************************************/
-+static int big_sur_ge_close(struct net_device *netdev)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+
-+ del_timer_sync(&lp->phy_timer);
-+ netif_stop_queue(netdev);
-+
-+ free_irq(netdev->irq, netdev);
-+
-+ if (big_sur_ge_stop(&lp->emac) == -1) {
-+ printk(KERN_ERR "%s: Could not stop device.\n",
-+ netdev->name);
-+ return -EBUSY;
-+ }
-+
-+ return 0;
-+}
-+
-+/*********************************************************************
-+ * Get the network device stats. For now, do nothing
-+ *********************************************************************/
-+static struct net_device_stats *big_sur_ge_get_stats(struct net_device
-+ *netdev)
-+{
-+ /* Do nothing */
-+ return (struct net_device_stats *) 0;
-+}
-+
-+/********************************************************************
-+ * FIFO send for a packet that needs to be transmitted
-+ ********************************************************************/
-+static int big_sur_ge_fifo_send(struct sk_buff *orig_skb,
-+ struct net_device *netdev)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ struct sk_buff *new_skb;
-+ unsigned int len, align;
-+
-+ netif_stop_queue(netdev);
-+ len = orig_skb->len;
-+
-+ if (!(new_skb = dev_alloc_skb(len + 4))) {
-+ dev_kfree_skb(orig_skb);
-+ printk(KERN_ERR
-+ "%s: Could not allocate transmit buffer.\n",
-+ netdev->name);
-+ netif_wake_queue(netdev);
-+ return -EBUSY;
-+ }
-+
-+ align = 4 - ((unsigned long) new_skb->data & 3);
-+ if (align != 4)
-+ skb_reserve(new_skb, align);
-+
-+ skb_put(new_skb, len);
-+ memcpy(new_skb->data, orig_skb->data, len);
-+
-+ dev_kfree_skb(orig_skb);
-+
-+ lp->saved_skb = new_skb;
-+ if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len)
-+ == -1) {
-+ spin_lock_irq(&lp->lock);
-+ new_skb = lp->saved_skb;
-+ lp->saved_skb = NULL;
-+ spin_unlock_irq(&lp->lock);
-+
-+ dev_kfree_skb(new_skb);
-+ printk(KERN_ERR "%s: Could not transmit buffer.\n",
-+ netdev->name);
-+ netif_wake_queue(netdev);
-+ return -EIO;
-+ }
-+ return 0;
-+}
-+
-+/**********************************************************************
-+ * Call the fifo send handler
-+ **********************************************************************/
-+static void big_sur_ge_fifo_send_handler(void *callback)
-+{
-+ struct net_device *netdev = (struct net_device *) callback;
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ struct sk_buff *skb;
-+
-+ spin_lock_irq(&lp->lock);
-+ skb = lp->saved_skb;
-+ lp->saved_skb = NULL;
-+ spin_unlock_irq(&lp->lock);
-+
-+ if (skb)
-+ dev_kfree_skb(skb);
-+
-+ netif_wake_queue(netdev);
-+}
-+
-+/**********************************************************************
-+ * Handle the timeout of the ethernet device
-+ **********************************************************************/
-+static void big_sur_ge_tx_timeout(struct net_device *netdev)
-+{
-+ printk
-+ ("%s: Exceeded transmit timeout of %lu ms. Resetting mac.\n",
-+ netdev->name, TX_TIMEOUT * 1000UL / HZ);
-+
-+ disable_irq(netdev->irq);
-+ big_sur_ge_reset(netdev, UNKNOWN);
-+ enable_irq(netdev->irq);
-+}
-+
-+/*********************************************************************
-+ * When in FIFO mode, the callback function for packets received
-+ *********************************************************************/
-+static void big_sur_ge_fifo_recv_handler(void *callback)
-+{
-+ struct net_device *netdev = (struct net_device *) callback;
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ struct sk_buff *skb;
-+ unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
-+ unsigned int align;
-+
-+ if (!(skb = dev_alloc_skb(len + 4))) {
-+ printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
-+ netdev->name);
-+ return;
-+ }
-+
-+ align = 4 - ((unsigned long) skb->data & 3);
-+ if (align != 4)
-+ skb_reserve(skb, align);
-+
-+ if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) ==
-+ -1) {
-+ dev_kfree_skb(skb);
-+
-+ printk(KERN_ERR "%s: Could not receive buffer \n",
-+ netdev->name);
-+ netdev->tx_timeout = NULL;
-+ big_sur_ge_reset(netdev, UNKNOWN);
-+ netdev->tx_timeout = big_sur_ge_tx_timeout;
-+ }
-+
-+ skb_put(skb, len); /* Tell the skb how much data we got. */
-+ skb->dev = netdev; /* Fill out required meta-data. */
-+ skb->protocol = eth_type_trans(skb, netdev);
-+
-+ netif_rx(skb); /* Send the packet upstream. */
-+}
-+
-+/*********************************************************************
-+ * Set the Multicast Hash list
-+ *********************************************************************/
-+static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ unsigned long options;
-+
-+ disable_irq(netdev->irq);
-+ local_bh_disable();
-+
-+ (void) big_sur_ge_stop(&lp->emac);
-+ options = big_sur_ge_get_options(&lp->emac);
-+ options &=
-+ ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
-+
-+ /* Do nothing for now */
-+
-+ (void) big_sur_ge_start(&lp->emac);
-+ local_bh_enable();
-+ enable_irq(netdev->irq);
-+}
-+
-+/***********************************************************************
-+ * IOCTL support
-+ ***********************************************************************/
-+static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq,
-+ int cmd)
-+{
-+ struct big_sur_ge_enet *lp = netdev->priv;
-+ struct mii_ioctl_data *data =
-+ (struct mii_ioctl_data *) &rq->ifr_data;
-+
-+ switch (cmd) {
-+ case SIOCGMIIPHY: /* Get address of MII PHY in use. */
-+ case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
-+ data->phy_id = lp->mii_addr;
-+
-+ case SIOCGMIIREG: /* Read MII PHY register. */
-+ case SIOCDEVPRIVATE + 1: /* for binary compat, remove in 2.5 */
-+ if (data->phy_id > 31 || data->reg_num > 31)
-+ return -ENXIO;
-+
-+ del_timer_sync(&lp->phy_timer);
-+
-+ if (big_sur_ge_phy_read(&lp->emac, data->phy_id,
-+ data->reg_num,
-+ &data->val_out) == -1) {
-+ printk(KERN_ERR "%s: Could not read from PHY",
-+ netdev->name);
-+ return -EBUSY;
-+ }
-+
-+ lp->phy_timer.expires = jiffies + 2 * HZ;
-+ add_timer(&lp->phy_timer);
-+
-+ return 0;
-+
-+ case SIOCSMIIREG: /* Write MII PHY register. */
-+ case SIOCDEVPRIVATE + 2: /* for binary compat, remove in 2.5 */
-+ if (data->phy_id > 31 || data->reg_num > 31)
-+ return -ENXIO;
-+
-+ del_timer_sync(&lp->phy_timer);
-+
-+ if (big_sur_ge_phy_write
-+ (&lp->emac, data->phy_id, data->reg_num,
-+ data->val_in) == -1) {
-+ printk(KERN_ERR "%s: Could not write to PHY",
-+ netdev->name);
-+ return -EBUSY;
-+ }
-+
-+ lp->phy_timer.expires = jiffies + 2 * HZ;
-+ add_timer(&lp->phy_timer);
-+
-+ return 0;
-+
-+ default:
-+ return -EOPNOTSUPP;
-+ }
-+}
-+
-+/*****************************************************************
-+ * Get the config from the config table
-+ *****************************************************************/
-+static big_sur_ge_config *big_sur_ge_get_config(int index)
-+{
-+ /* Manish */
-+ return (big_sur_ge_config *) 0;
-+}
-+
-+/*****************************************************************
-+ * Release the network device structure
-+ *****************************************************************/
-+static void big_sur_ge_remove_head(void)
-+{
-+ struct net_device *netdev;
-+ struct big_sur_ge_enet *lp;
-+ big_sur_ge_config *config;
-+
-+ spin_lock(&dev_lock);
-+ netdev = dev_list;
-+ lp = netdev->priv;
-+
-+ spin_unlock(&dev_lock);
-+
-+ config = big_sur_ge_get_config(lp->index);
-+ iounmap((void *) config->base_address);
-+ config->base_address = lp->save_base_address;
-+
-+ if (lp->saved_skb)
-+ dev_kfree_skb(lp->saved_skb);
-+ kfree(lp);
-+
-+ unregister_netdev(netdev);
-+ kfree(netdev);
-+}
-+
-+/*****************************************************************
-+ * Initial Function to probe the network interface
-+ *****************************************************************/
-+static int __init big_sur_ge_probe(int index)
-+{
-+ static const unsigned long remap_size =
-+ BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1;
-+ struct net_device *netdev;
-+ struct big_sur_ge_enet *lp;
-+ big_sur_ge_config *config;
-+ unsigned int irq;
-+ unsigned long maddr;
-+ goto err;
-+
-+ switch (index) {
-+ case 0:
-+ irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID);
-+ break;
-+ case 1:
-+ irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID);
-+ break;
-+ case 2:
-+ irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID);
-+ break;
-+ default:
-+ err = -ENODEV;
-+ goto out;
-+ }
-+
-+ config = big_sur_ge_get_config(index);
-+ if (!config) {
-+ err = -ENODEV;
-+ goto out;
-+ }
-+
-+ netdev = alloc_etherdev(sizeof(big_sur_ge_config));
-+
-+ if (!netdev) {
-+ err = -ENOMEM;
-+ goto out;
-+ }
-+
-+ SET_MODULE_OWNER(netdev);
-+
-+ netdev->irq = irq;
-+
-+ lp = (struct big_sur_ge_enet *) netdev->priv;
-+ memset(lp, 0, sizeof(struct big_sur_ge_enet));
-+ spin_lock_init(&lp->lock);
-+ spin_lock(&dev_lock);
-+ lp->next_dev = dev_list;
-+ dev_list = netdev;
-+ spin_unlock(&dev_lock);
-+
-+ lp->save_base_address = config->base_address;
-+ config->base_address =
-+ (unsigned long) ioremap(lp->save_base_address, remap_size);
-+ if (!config->base_address) {
-+ err = -ENOMEM;
-+ goto out_unlock;
-+ }
-+
-+ if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) {
-+ printk(KERN_ERR "%s: Could not initialize device.\n",
-+ netdev->name);
-+ err = -ENODEV;
-+ goto out_unmap;
-+ }
-+
-+ /* Manish: dev_addr value */
-+ memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
-+ if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
-+ printk(KERN_ERR "%s: Could not set MAC address.\n",
-+ netdev->name);
-+ err = -EIO;
-+ goto out_unmap;
-+ }
-+
-+ /*
-+ * There is no Scatter Gather support but there is a Simple DMA support
-+ */
-+ big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev,
-+ big_sur_ge_fifo_recv_handler);
-+ big_sur_ge_set_fifo_send_handler(&lp->emac, netdev,
-+ big_sur_ge_fifo_send_handler);
-+ netdev->hard_start_xmit = big_sur_ge_fifo_send;
-+
-+ lp->mii_addr = 0xFF;
-+
-+ for (maddr = 0; maddr < 31; maddr++) {
-+ unsigned int reg_data;
-+
-+ if (big_sur_ge_phy_read
-+ (&lp->emac, maddr, MII_BMCR, ®_data) == 0) {
-+ lp->mii_addr = maddr;
-+ break;
-+ }
-+ }
-+
-+ if (lp->mii_addr == 0xFF) {
-+ lp->mii_addr = 0;
-+ printk(KERN_WARNING
-+ "%s: No PHY detected. Assuming a PHY at address %d.\n",
-+ netdev->name, lp->mii_addr);
-+ }
-+
-+ netdev->open = big_sur_ge_open;
-+ netdev->stop = big_sur_ge_close;
-+ netdev->get_stats = big_sur_ge_get_stats; /* Does nothing */
-+ netdev->do_ioctl = big_sur_ge_ioctl;
-+ netdev->tx_timeout = big_sur_ge_tx_timeout;
-+ netdev->watchdog_timeo = TX_TIMEOUT;
-+
-+ err = register_netdev(netdev))
-+ if (!err)
-+ goto out_unmap;
-+
-+ printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d at 0x%08X "
-+ "mapped to 0x%08X, irq=%d\n", netdev->name, index,
-+ lp->save_base_address, config->base_address, netdev->irq);
-+
-+ return ret;
-+
-+out_unmap:
-+ iounmap(config->base_address);
-+
-+out_unlock:
-+ big_sur_ge_remove_head();
-+
-+out:
-+ return ret;
-+}
-+
-+static int __init big_sur_ge_init(void)
-+{
-+ int index = 0;
-+
-+ while (big_sur_ge_probe(index++) == 0);
-+
-+ return (index > 1) ? 0 : -ENODEV;
-+}
-+
-+static void __exit big_sur_ge_cleanup(void)
-+{
-+ while (dev_list)
-+ big_sur_ge_remove_head();
-+}
-+
-+module_init(big_sur_ge_init);
-+module_exit(big_sur_ge_cleanup);
-+
-+MODULE_AUTHOR("Manish Lachwani <lachwani at pmc-sierra.com>");
-+MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
-+MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/net/big_sur_ge.h linux_HEAD/drivers/net/big_sur_ge.h
---- linux-2.6.12/drivers/net/big_sur_ge.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/big_sur_ge.h 2005-04-14 16:40:17.000000000 +0200
-@@ -0,0 +1,713 @@
-+/*
-+ * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur
-+ * ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
-+ * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ */
-+
-+#ifndef __BIG_SUR_GE_H__
-+#define __BIG_SUR_GE_H__
-+
-+#include <linux/version.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+#define BIG_SUR_DEVICE_NAME "big sur"
-+#define BIG_SUR_DEVICE_DESC "Big Sur Ethernet 10/100 MAC"
-+
-+#define BIG_SUR_GE_BASE 0xbb000000
-+
-+#define BIG_SUR_GE_WRITE(ofs,data) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data
-+
-+#define BIG_SUR_GE_READ(ofs) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs))
-+
-+/* Manish : Need to fix these defines later */
-+#define BIG_SUR_GE_EMAC_0_HIGHADDR
-+#define BIG_SUR_GE_EMAC_0_BASEADDR
-+#define BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID 1
-+#define BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID 2
-+#define BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID 3
-+#define BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST
-+#define BIG_SUR_GE_EMAC_0_DMA_PRESENT
-+#define BIG_SUR_GE_EMAC_0_MII_EXIST
-+#define BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR
-+#define BIG_SUR_GE_EMAC_0_DEVICE_ID
-+#define BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST
-+#define BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT
-+#define BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST
-+#define BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID
-+
-+#define BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT 4UL
-+/* IPIF specific defines */
-+#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
-+#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
-+#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
-+#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
-+#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
-+#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
-+#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
-+#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
-+#define XIIF_V123B_RESET_MASK 0xAUL
-+#define XIIF_V123B_ERROR_MASK 0x1UL
-+
-+/* defines */
-+#define BIG_SUR_GE_UNICAST_OPTION 0x00000001
-+#define BIG_SUR_GE_BROADCAST_OPTION 0x00000002
-+#define BIG_SUR_GE_PROMISC_OPTION 0x00000004
-+#define BIG_SUR_GE_FDUPLEX_OPTION 0x00000008
-+#define BIG_SUR_GE_POLLED_OPTION 0x00000010
-+#define BIG_SUR_GE_LOOPBACK_OPTION 0x00000020
-+#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080
-+#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100
-+#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200
-+#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400
-+#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800
-+#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION 0x00002000
-+
-+/* Not Supported */
-+#define BIG_SUR_GE_MULTICAST_OPTION 0x00000040
-+#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080
-+#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100
-+#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200
-+#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400
-+#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800
-+#define BIG_SUR_GE_STRIP_PAD_OPTION 0x00001000
-+#define BIG_SUR_GE_STRIP_FCS_OPTION 0x00002000
-+
-+
-+/* Defaults for Interrupt Coalescing in the SG DMA Engine */
-+#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */
-+#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */
-+#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */
-+#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */
-+
-+/* Direction */
-+#define BIG_SUR_GE_SEND 1
-+#define BIG_SUR_GE_RECV 2
-+
-+/* SG DMA */
-+#define BIG_SUR_GE_SGDMA_NODELAY 0 /* start SG DMA immediately */
-+#define BIG_SUR_GE_SGDMA_DELAY 1 /* do not start SG DMA */
-+
-+#define BIG_SUR_GE_CFG_NO_IPIF 0 /* Not supported by the driver */
-+#define BIG_SUR_GE_CFG_NO_DMA 1 /* No DMA */
-+#define BIG_SUR_GE_CFG_SIMPLE_DMA 2 /* Simple DMA */
-+#define BIG_SUR_GE_CFG_DMA_SG 3 /* DMA scatter gather */
-+
-+#define BIG_SUR_GE_MAC_ADDR_SIZE 6 /* six-byte MAC address */
-+#define BIG_SUR_GE_MTU 1500 /* max size of Ethernet frame */
-+#define BIG_SUR_GE_HDR_SIZE 14 /* size of Ethernet header */
-+#define BIG_SUR_GE_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
-+#define BIG_SUR_GE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
-+#define BIG_SUR_GE_MAX_FRAME_SIZE \
-+ (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE)
-+
-+#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE \
-+ (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE)
-+
-+/* Send and Receive buffers */
-+#define BIG_SUR_GE_MIN_RECV_BUFS 32 /* minimum # of recv buffers */
-+#define BIG_SUR_GE_DFT_RECV_BUFS 64 /* default # of recv buffers */
-+
-+#define BIG_SUR_GE_MIN_SEND_BUFS 16 /* minimum # of send buffers */
-+#define BIG_SUR_GE_DFT_SEND_BUFS 32 /* default # of send buffers */
-+
-+#define BIG_SUR_GE_MIN_BUFFERS (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS)
-+#define BIG_SUR_GE_DFT_BUFFERS (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS)
-+
-+/* Send and Receive Descriptors */
-+#define BIG_SUR_GE_MIN_RECV_DESC 16 /* minimum # of recv descriptors */
-+#define BIG_SUR_GE_DFT_RECV_DESC 32 /* default # of recv descriptors */
-+
-+#define BIG_SUR_GE_MIN_SEND_DESC 8 /* minimum # of send descriptors */
-+#define BIG_SUR_GE_DFT_SEND_DESC 16 /* default # of send descriptors */
-+
-+/* FIFO Specific Defines */
-+#define BIG_SUR_GE_READ_FIFO_TYPE 0 /* a read FIFO */
-+#define BIG_SUR_GE_WRITE_FIFO_TYPE 1 /* a write FIFO */
-+#define BIG_SUR_GE_RESET_REG_OFFSET 0UL
-+#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET 0UL
-+#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET 4UL
-+#define BIG_SUR_GE_RESET_FIFO_MASK 0x0000000A
-+#define BIG_SUR_GE_COUNT_MASK 0x0000FFFF
-+#define BIG_SUR_GE_DEADLOCK_MASK 0x20000000
-+#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK 0x40000000
-+#define BIG_SUR_GE_EMPTY_FULL_MASK 0x80000000
-+
-+#define BIG_SUR_GE_FIFO_RESET(fifo) \
-+ BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK)
-+
-+#define BIG_SUR_GE_GET_COUNT(fifo) \
-+ (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_COUNT_MASK)
-+
-+#define BIG_SUR_GE_IS_ALMOST_EMPTY(fifo) \
-+ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_ALMOST_FULL(fifo) \
-+ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_EMPTY(fifo) \
-+ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_FULL(fifo) \
-+ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_DEADLOCKED(fifo) \
-+ (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
-+ BIG_SUR_GE_DEADLOCK_MASK)
-+
-+/* Device Config */
-+typedef struct _big_sur_ge_config {
-+ u16 device_id;
-+ u32 base_address;
-+ u32 has_counters;
-+ u32 has_sg_dma;
-+ u8 dma_config;
-+ u32 has_mii;
-+} big_sur_ge_config;
-+
-+#define BIG_SUR_GE_SIZE_IN_WORDS 10
-+typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS];
-+
-+/* Callback Functions */
-+typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc);
-+typedef void (*big_sur_fifo_handler) (void *callback);
-+typedef void (*big_sur_irq_handler) (void *instance);
-+
-+typedef struct _xdma_channel_tag {
-+ u32 reg_base_address;
-+ u32 base_address;
-+ u32 ready;
-+ xbuf_descriptor *put_ptr;
-+ xbuf_descriptor *get_ptr;
-+ xbuf_descriptor *commit_ptr;
-+ xbuf_descriptor *last_ptr;
-+
-+ u32 total_desc_count;
-+ u32 active_desc_count;
-+} xdma_channel;
-+
-+typedef struct _packet_fifo {
-+ u32 reg_base_addr;
-+ u32 ready_status;
-+ u32 data_base_address;
-+} packet_fifo;
-+
-+
-+/* Big Sur GE driver structure */
-+typedef struct _big_sur_ge {
-+ u32 base_address;
-+ u32 started;
-+ u32 ready;
-+ u32 polled;
-+ u32 dma_sg;
-+
-+ u8 dma_config;
-+ u32 has_mii;
-+ u32 has_mcast_hash_table;
-+
-+ /* For the FIFO and simple DMA case only */
-+ packet_fifo recv_fifo;
-+ packet_fifo send_fifo;
-+
-+ big_sur_fifo_handler big_sur_ge_fifo_recv_handler;
-+ big_sur_fifo_handler big_sur_ge_fifo_send_handler;
-+
-+ void *fifo_send_ref;
-+ void *fifo_recv_ref;
-+
-+ /* For SG DMA only */
-+ xdma_channel recv_channel;
-+ xdma_channel send_channel;
-+} big_sur_ge;
-+
-+/* Offset of the MAC registers from the IPIF base address */
-+#define BIG_SUR_GE_REG_OFFSET 0x1100UL
-+
-+/*
-+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
-+ */
-+#define BIG_SUR_GE_EMIR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x0) /* EMAC Module ID */
-+#define BIG_SUR_GE_ECR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x4) /* MAC Control */
-+#define BIG_SUR_GE_IFGP_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x8) /* Interframe Gap */
-+#define BIG_SUR_GE_SAH_OFFSET (BIG_SUR_GE_REG_OFFSET + 0xC) /* Station addr, high */
-+#define BIG_SUR_GE_SAL_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x10) /* Station addr, low */
-+#define BIG_SUR_GE_MGTCR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x14) /* MII mgmt control */
-+#define BIG_SUR_GE_MGTDR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x18) /* MII mgmt data */
-+#define BIG_SUR_GE_RPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x1C) /* Rx packet length */
-+#define BIG_SUR_GE_TPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x20) /* Tx packet length */
-+#define BIG_SUR_GE_TSR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x24) /* Tx status */
-+#define BIG_SUR_GE_RMFC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x28) /* Rx missed frames */
-+#define BIG_SUR_GE_RCC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x2C) /* Rx collisions */
-+#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30) /* Rx FCS errors */
-+#define BIG_SUR_GE_RAEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x34) /* Rx alignment errors */
-+#define BIG_SUR_GE_TEDC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x38) /* Transmit excess
-+ * deferral cnt */
-+/*
-+ * Register offsets for the IPIF components
-+ */
-+#define BIG_SUR_GE_ISR_OFFSET 0x20UL /* Interrupt status */
-+
-+#define BIG_SUR_GE_DMA_OFFSET 0x2300UL
-+#define BIG_SUR_GE_DMA_SEND_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */
-+#define BIG_SUR_GE_DMA_RECV_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x40) /* DMA recv channel */
-+
-+#define BIG_SUR_GE_PFIFO_OFFSET 0x2000UL
-+#define BIG_SUR_GE_PFIFO_TXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x0) /* Tx registers */
-+#define BIG_SUR_GE_PFIFO_RXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x10) /* Rx registers */
-+#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x100) /* Tx keyhole */
-+#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x200) /* Rx keyhole */
-+
-+/*
-+ * EMAC Module Identification Register (EMIR)
-+ */
-+#define BIG_SUR_GE_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */
-+#define BIG_SUR_GE_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */
-+
-+/*
-+ * EMAC Control Register (ECR)
-+ */
-+#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK 0x80000000 /* Full duplex mode */
-+#define BIG_SUR_GE_ECR_XMIT_RESET_MASK 0x40000000 /* Reset transmitter */
-+#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK 0x20000000 /* Enable transmitter */
-+#define BIG_SUR_GE_ECR_RECV_RESET_MASK 0x10000000 /* Reset receiver */
-+#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK 0x08000000 /* Enable receiver */
-+#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK 0x04000000 /* Enable PHY */
-+#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK 0x02000000 /* Enable xmit pad insert */
-+#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK 0x01000000 /* Enable xmit FCS insert */
-+#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK 0x00800000 /* Enable xmit source addr insertion */
-+#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK 0x00400000 /* Insert xmit error */
-+#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000 /* Enable xmit source addr overwrite */
-+#define BIG_SUR_GE_ECR_LOOPBACK_MASK 0x00100000 /* Enable internal loopback */
-+#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK 0x00080000 /* Enable recv pad strip */
-+#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK 0x00040000 /* Enable recv FCS strip */
-+#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK 0x00080000 /* Enable recv pad/fcs strip */
-+#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK 0x00020000 /* Enable unicast addr */
-+#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK 0x00010000 /* Enable multicast addr */
-+#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK 0x00008000 /* Enable broadcast addr */
-+#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK 0x00004000 /* Enable promiscuous mode */
-+#define BIG_SUR_GE_ECR_RECV_ALL_MASK 0x00002000 /* Receive all frames */
-+#define BIG_SUR_GE_ECR_RESERVED2_MASK 0x00001000 /* Reserved */
-+#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK 0x00000800 /* Enable multicast hash */
-+#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK 0x00000400 /* Interpret pause frames */
-+#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK 0x00000200 /* Clear hash table */
-+#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK 0x00000100 /* Add hash table address */
-+
-+/*
-+ * Interframe Gap Register (IFGR)
-+ */
-+#define BIG_SUR_GE_IFGP_PART1_MASK 0xF8000000 /* Interframe Gap Part1 */
-+#define BIG_SUR_GE_IFGP_PART1_SHIFT 27
-+#define BIG_SUR_GE_IFGP_PART2_MASK 0x07C00000 /* Interframe Gap Part2 */
-+#define BIG_SUR_GE_IFGP_PART2_SHIFT 22
-+
-+/*
-+ * Station Address High Register (SAH)
-+ */
-+#define BIG_SUR_GE_SAH_ADDR_MASK 0x0000FFFF /* Station address high bytes */
-+
-+/*
-+ * Station Address Low Register (SAL)
-+ */
-+#define BIG_SUR_GE_SAL_ADDR_MASK 0xFFFFFFFF /* Station address low bytes */
-+
-+/*
-+ * MII Management Control Register (MGTCR)
-+ */
-+#define BIG_SUR_GE_MGTCR_START_MASK 0x80000000 /* Start/Busy */
-+#define BIG_SUR_GE_MGTCR_RW_NOT_MASK 0x40000000 /* Read/Write Not (direction) */
-+#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK 0x3E000000 /* PHY address */
-+#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */
-+#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK 0x01F00000 /* Register address */
-+#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */
-+#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK 0x00080000 /* Enable MII from EMAC */
-+#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK 0x00040000 /* MII mgmt read error */
-+
-+/*
-+ * MII Management Data Register (MGTDR)
-+ */
-+#define BIG_SUR_GE_MGTDR_DATA_MASK 0x0000FFFF /* MII data */
-+
-+/*
-+ * Receive Packet Length Register (RPLR)
-+ */
-+#define BIG_SUR_GE_RPLR_LENGTH_MASK 0x0000FFFF /* Receive packet length */
-+
-+/*
-+ * Transmit Packet Length Register (TPLR)
-+ */
-+#define BIG_SUR_GE_TPLR_LENGTH_MASK 0x0000FFFF /* Transmit packet length */
-+
-+/*
-+ * Transmit Status Register (TSR)
-+ */
-+#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000 /* Transmit excess deferral */
-+#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK 0x40000000 /* Packet FIFO underrun */
-+#define BIG_SUR_GE_TSR_ATTEMPTS_MASK 0x3E000000 /* Transmission attempts */
-+#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK 0x01000000 /* Transmit late collision */
-+
-+/*
-+ * Receive Missed Frame Count (RMFC)
-+ */
-+#define BIG_SUR_GE_RMFC_DATA_MASK 0x0000FFFF
-+
-+/*
-+ * Receive Collision Count (RCC)
-+ */
-+#define BIG_SUR_GE_RCC_DATA_MASK 0x0000FFFF
-+/*
-+ * Receive FCS Error Count (RFCSEC)
-+ */
-+#define BIG_SUR_GE_RFCSEC_DATA_MASK 0x0000FFFF
-+
-+/*
-+ * Receive Alignment Error Count (RALN)
-+ */
-+#define BIG_SUR_GE_RAEC_DATA_MASK 0x0000FFFF
-+
-+/*
-+ * Transmit Excess Deferral Count (TEDC)
-+ */
-+#define BIG_SUR_GE_TEDC_DATA_MASK 0x0000FFFF
-+
-+/*
-+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
-+ * part of the IPIF IP Interrupt registers
-+ */
-+#define BIG_SUR_GE_EIR_XMIT_DONE_MASK 0x00000001 /* Xmit complete */
-+#define BIG_SUR_GE_EIR_RECV_DONE_MASK 0x00000002 /* Recv complete */
-+#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK 0x00000004 /* Xmit error */
-+#define BIG_SUR_GE_EIR_RECV_ERROR_MASK 0x00000008 /* Recv error */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /* Xmit status fifo empty */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020 /* Recv length fifo empty */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK 0x00000040 /* Xmit length fifo full */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK 0x00000080 /* Recv length fifo overrun */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK 0x00000100 /* Recv length fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK 0x00000200 /* Xmit status fifo overrun */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400 /* Transmit status fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK 0x00000800 /* Transmit length fifo overrun */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000 /* Transmit length fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK 0x00002000 /* Transmit pause pkt received */
-+#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK 0x00004000 /* Receive data fifo overrun */
-+#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000 /* Receive missed frame error */
-+#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK 0x00010000 /* Receive collision error */
-+#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK 0x00020000 /* Receive FCS error */
-+#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK 0x00040000 /* Receive length field error */
-+#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK 0x00080000 /* Receive short frame error */
-+#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK 0x00100000 /* Receive long frame error */
-+#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK 0x00200000 /* Receive alignment error */
-+
-+#define BIG_SUR_GE_READ_REG(base_addr, reg_offset) \
-+ BIG_SUR_GE_READ(base_addr + reg_offset)
-+
-+#define BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data) \
-+ BIG_SUR_GE_WRITE(base_addr + reg_offset, data)
-+
-+#define BIG_SUR_GE_CONTROL_REG(base_addr, mask) \
-+ BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask)
-+
-+/* Set the MAC Address */
-+#define big_sur_ge_set_mac(base_addr, address) \
-+{ \
-+ u32 mac_addr; \
-+ \
-+ mac_addr = ((address[0] << 8) | (address[1]); \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address); \
-+ \
-+ mac_addr = ((address[2] << 24) | (address[3] << 16) | \
-+ (address[4] << 8) | address[5]); \
-+ \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address); \
-+ \
-+}
-+
-+/* Enable the MAC unit */
-+#define big_sur_ge_mac_enable(base_address) \
-+{ \
-+ u32 control; \
-+ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
-+ control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK); \
-+ control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
-+}
-+
-+/* Disable the MAC unit */
-+#define big_sur_ge_mac_disable(base_address) \
-+{ \
-+ u32 control; \
-+ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
-+ control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
-+}
-+
-+/* Check if the Tx is done */
-+#define big_sur_ge_tx_done(base_address) \
-+ (BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK)
-+
-+
-+/* Check if Rx FIFO is empty */
-+#define big_sur_ge_rx_empty(base_address) \
-+ (!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK))
-+
-+/* Reset the MAC PHY */
-+#define big_sur_ge_reset_phy(base_address) \
-+{ \
-+ u32 control; \
-+ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
-+ control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
-+ control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; \
-+ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
-+}
-+
-+/* DMA SG defines */
-+#define BIG_SUR_GE_CONTROL_LAST_BD_MASK 0x02000000
-+#define BIG_SUR_GE_STATUS_LAST_BD_MASK 0x10000000
-+#define BIG_SUR_GE_RST_REG_OFFSET 0 /* reset register */
-+#define BIG_SUR_GE_MI_REG_OFFSET 0 /* module information register */
-+#define BIG_SUR_GE_DMAC_REG_OFFSET 4 /* DMA control register */
-+#define BIG_SUR_GE_SA_REG_OFFSET 8 /* source address register */
-+#define BIG_SUR_GE_DA_REG_OFFSET 12 /* destination address register */
-+#define BIG_SUR_GE_LEN_REG_OFFSET 16 /* length register */
-+#define BIG_SUR_GE_DMAS_REG_OFFSET 20 /* DMA status register */
-+#define BIG_SUR_GE_BDA_REG_OFFSET 24 /* buffer descriptor address register */
-+#define BIG_SUR_GE_SWCR_REG_OFFSET 28 /* software control register */
-+#define BIG_SUR_GE_UPC_REG_OFFSET 32 /* unserviced packet count register */
-+#define BIG_SUR_GE_PCT_REG_OFFSET 36 /* packet count threshold register */
-+#define BIG_SUR_GE_PWB_REG_OFFSET 40 /* packet wait bound register */
-+#define BIG_SUR_GE_IS_REG_OFFSET 44 /* interrupt status register */
-+#define BIG_SUR_GE_IE_REG_OFFSET 48 /* interrupt enable register */
-+
-+#define BIG_SUR_GE_RESET_MASK 0x0000000A
-+
-+/* Buffer Descriptor Control */
-+
-+#define BIG_SUR_GE_DEVICE_STATUS_OFFSET 0
-+#define BIG_SUR_GE_CONTROL_OFFSET 1
-+#define BIG_SUR_GE_SOURCE_OFFSET 2
-+#define BIG_SUR_GE_DESTINATION_OFFSET 3
-+#define BIG_SUR_GE_LENGTH_OFFSET 4
-+#define BIG_SUR_GE_STATUS_OFFSET 5
-+#define BIG_SUR_GE_NEXT_PTR_OFFSET 6
-+#define BIG_SUR_GE_ID_OFFSET 7
-+#define BIG_SUR_GE_FLAGS_OFFSET 8
-+#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET 9
-+
-+#define BIG_SUR_GE_FLAGS_LOCKED_MASK 1
-+
-+#define xbuf_descriptor_init(base) \
-+{ \
-+ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0); \
-+ (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \
-+}
-+
-+#define xbuf_descriptor_GetControl(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET))
-+
-+#define xbuf_descriptor_SetControl(base, Control) \
-+ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control)
-+
-+#define xbuf_descriptor_IsLastControl(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \
-+ BIG_SUR_GE_CONTROL_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_SetLast(base) \
-+ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_GetSrcAddress(base) \
-+ ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET)))
-+
-+#define xbuf_descriptor_SetSrcAddress(base, Source) \
-+ (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source)
-+
-+#define xbuf_descriptor_GetDestAddress(base) \
-+ ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET)))
-+
-+#define xbuf_descriptor_SetDestAddress(base, Destination) \
-+ (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination)
-+
-+#define xbuf_descriptor_GetLength(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) - \
-+ *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET))
-+
-+#define xbuf_descriptor_SetLength(base, Length) \
-+{ \
-+ (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length)); \
-+ (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
-+}
-+
-+#define xbuf_descriptor_GetStatus(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET))
-+
-+#define xbuf_descriptor_SetStatus(base, Status) \
-+ (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status)
-+
-+#define xbuf_descriptor_IsLastStatus(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \
-+ BIG_SUR_GE_STATUS_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_GetDeviceStatus(base) \
-+ ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET)))
-+
-+#define xbuf_descriptor_SetDeviceStatus(base, Status) \
-+ (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status)
-+
-+#define xbuf_descriptor_GetNextPtr(base) \
-+ (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET))
-+
-+#define xbuf_descriptor_SetNextPtr(base, NextPtr) \
-+ (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr)
-+
-+#define xbuf_descriptor_GetId(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET))
-+
-+#define xbuf_descriptor_SetId(base, Id) \
-+ (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id)
-+
-+#define xbuf_descriptor_GetFlags(base) \
-+ (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET))
-+
-+#define xbuf_descriptor_SetFlags(base, Flags) \
-+ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags)
-+
-+#define xbuf_descriptor_Lock(base) \
-+ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define xbuf_descriptor_Unlock(base) \
-+ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define xbuf_descriptor_IsLocked(base) \
-+ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */
-+#define BIG_SUR_GE_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */
-+#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */
-+#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */
-+#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */
-+#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */
-+#define BIG_SUR_GE_DMACR_LAST_BD_MASK BIG_SUR_GE_CONTROL_LAST_BD_MASK /* last buffer */
-+#define BIG_SUR_GE_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */
-+#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */
-+#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */
-+#define BIG_SUR_GE_DMASR_LAST_BD_MASK BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */
-+#define BIG_SUR_GE_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */
-+#define BIG_SUR_GE_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */
-+#define BIG_SUR_GE_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */
-+#define BIG_SUR_GE_IXR_PKT_DONE_MASK 0x4UL /* packet done */
-+#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */
-+#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */
-+#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable
-+ acknowledge occurred */
-+#define BIG_SUR_GEIXR_SG_END_MASK 0x40UL /* last buffer descriptor
-+ disabled scatter gather */
-+#define BIG_SUR_GEIXR_BD_MASK 0x80UL /* buffer descriptor done */
-+
-+/* BD control */
-+#define BIG_SUR_GE_DFT_SEND_BD_MASK (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \
-+ BIG_SUR_GEDMACR_DEST_LOCAL_MASK)
-+#define BIG_SUR_GE_DFT_RECV_BD_MASK (BIG_SUR_GEDMACR_DEST_INCR_MASK | \
-+ BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK)
-+
-+/* Interrupts */
-+#define BIG_SUR_GE_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */
-+#define BIG_SUR_GE_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */
-+#define BIG_SUR_GE_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */
-+#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */
-+#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */
-+
-+#define BIG_SUR_GE_IPIF_DMA_DFT_MASK (BIG_SUR_GE_IPIF_SEND_DMA_MASK | \
-+ BIG_SUR_GE_IPIF_RECV_DMA_MASK | \
-+ BIG_SUR_GE_IPIF_EMAC_MASK | \
-+ BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \
-+ BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+
-+#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK (BIG_SUR_GE_IPIF_EMAC_MASK | \
-+ BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \
-+ BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+
-+#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */
-+
-+/* a mask for all transmit interrupts, used in polled mode */
-+#define BIG_SUR_GE_EIR_XMIT_ALL_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK)
-+
-+/* a mask for all receive interrupts, used in polled mode */
-+#define BIG_SUR_GE_EIR_RECV_ALL_MASK (BIG_SUR_GE_EIR_RECV_DONE_MASK | \
-+ BIG_SUR_GE_EIR_RECV_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \
-+ BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \
-+ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
-+
-+/* a default interrupt mask for scatter-gather DMA operation */
-+#define BIG_SUR_GE_EIR_DFT_SG_MASK (BIG_SUR_GE_EIR_RECV_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \
-+ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \
-+ BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \
-+ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \
-+ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
-+
-+/* a default interrupt mask for non-DMA operation (direct FIFOs) */
-+#define BIG_SUR_GE_EIR_DFT_FIFO_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \
-+ BIG_SUR_GE_EIR_RECV_DONE_MASK | \
-+ BIG_SUR_GE_EIR_DFT_SG_MASK)
-+
-+#define BIG_SUR_GE_DMA_SG_INTR_MASK (BIG_SUR_GEIXR_DMA_ERROR_MASK | \
-+ BIG_SUR_GEIXR_PKT_THRESHOLD_MASK | \
-+ BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK | \
-+ BIG_SUR_GEIXR_SG_END_MASK)
-+
-+#endif
-diff -urpNX dontdiff linux-2.6.12/drivers/net/declance.c linux_HEAD/drivers/net/declance.c
---- linux-2.6.12/drivers/net/declance.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/declance.c 2005-07-03 16:44:31.000000000 +0200
-@@ -5,7 +5,7 @@
- *
- * adopted from sunlance.c by Richard van den Berg
- *
-- * Copyright (C) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- *
- * additional sources:
- * - PMAD-AA TURBOchannel Ethernet Module Functional Specification,
-@@ -57,13 +57,15 @@
- #include <linux/string.h>
-
- #include <asm/addrspace.h>
-+#include <asm/system.h>
-+
- #include <asm/dec/interrupts.h>
- #include <asm/dec/ioasic.h>
- #include <asm/dec/ioasic_addrs.h>
- #include <asm/dec/kn01.h>
- #include <asm/dec/machtype.h>
-+#include <asm/dec/system.h>
- #include <asm/dec/tc.h>
--#include <asm/system.h>
-
- static char version[] __devinitdata =
- "declance.c: v0.009 by Linux MIPS DECstation task force\n";
-@@ -79,10 +81,6 @@ MODULE_LICENSE("GPL");
- #define PMAD_LANCE 2
- #define PMAX_LANCE 3
-
--#ifndef CONFIG_TC
--unsigned long system_base;
--unsigned long dmaptr;
--#endif
-
- #define LE_CSR0 0
- #define LE_CSR1 1
-@@ -237,7 +235,7 @@ struct lance_init_block {
- /*
- * This works *only* for the ring descriptors
- */
--#define LANCE_ADDR(x) (PHYSADDR(x) >> 1)
-+#define LANCE_ADDR(x) (CPHYSADDR(x) >> 1)
-
- struct lance_private {
- struct net_device *next;
-@@ -697,16 +695,17 @@ out:
- spin_unlock(&lp->lock);
- }
-
--static void lance_dma_merr_int(const int irq, void *dev_id,
-- struct pt_regs *regs)
-+static irqreturn_t lance_dma_merr_int(const int irq, void *dev_id,
-+ struct pt_regs *regs)
- {
- struct net_device *dev = (struct net_device *) dev_id;
-
- printk("%s: DMA error\n", dev->name);
-+ return IRQ_HANDLED;
- }
-
--static irqreturn_t
--lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs)
-+static irqreturn_t lance_interrupt(const int irq, void *dev_id,
-+ struct pt_regs *regs)
- {
- struct net_device *dev = (struct net_device *) dev_id;
- struct lance_private *lp = netdev_priv(dev);
-@@ -1026,10 +1025,6 @@ static int __init dec_lance_init(const i
- unsigned long esar_base;
- unsigned char *esar;
-
--#ifndef CONFIG_TC
-- system_base = KN01_LANCE_BASE;
--#endif
--
- if (dec_lance_debug && version_printed++ == 0)
- printk(version);
-
-@@ -1062,16 +1057,16 @@ static int __init dec_lance_init(const i
- switch (type) {
- #ifdef CONFIG_TC
- case ASIC_LANCE:
-- dev->base_addr = system_base + IOASIC_LANCE;
-+ dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE);
-
- /* buffer space for the on-board LANCE shared memory */
- /*
- * FIXME: ugly hack!
- */
-- dev->mem_start = KSEG1ADDR(0x00020000);
-+ dev->mem_start = CKSEG1ADDR(0x00020000);
- dev->mem_end = dev->mem_start + 0x00020000;
- dev->irq = dec_interrupt[DEC_IRQ_LANCE];
-- esar_base = system_base + IOASIC_ESAR;
-+ esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR);
-
- /* Workaround crash with booting KN04 2.1k from Disk */
- memset((void *)dev->mem_start, 0,
-@@ -1101,14 +1096,14 @@ static int __init dec_lance_init(const i
- /* Setup I/O ASIC LANCE DMA. */
- lp->dma_irq = dec_interrupt[DEC_IRQ_LANCE_MERR];
- ioasic_write(IO_REG_LANCE_DMA_P,
-- PHYSADDR(dev->mem_start) << 3);
-+ CPHYSADDR(dev->mem_start) << 3);
-
- break;
-
- case PMAD_LANCE:
- claim_tc_card(slot);
-
-- dev->mem_start = get_tc_base_addr(slot);
-+ dev->mem_start = CKSEG1ADDR(get_tc_base_addr(slot));
- dev->base_addr = dev->mem_start + 0x100000;
- dev->irq = get_tc_irq_nr(slot);
- esar_base = dev->mem_start + 0x1c0002;
-@@ -1137,9 +1132,9 @@ static int __init dec_lance_init(const i
-
- case PMAX_LANCE:
- dev->irq = dec_interrupt[DEC_IRQ_LANCE];
-- dev->base_addr = KN01_LANCE_BASE;
-- dev->mem_start = KN01_LANCE_BASE + 0x01000000;
-- esar_base = KN01_RTC_BASE + 1;
-+ dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE);
-+ dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM);
-+ esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);
- lp->dma_irq = -1;
-
- /*
-@@ -1260,7 +1255,7 @@ static int __init dec_lance_init(const i
- return 0;
-
- err_out_free_dev:
-- kfree(dev);
-+ free_netdev(dev);
-
- err_out:
- return ret;
-@@ -1306,6 +1301,7 @@ static void __exit dec_lance_cleanup(voi
- while (root_lance_dev) {
- struct net_device *dev = root_lance_dev;
- struct lance_private *lp = netdev_priv(dev);
-+
- unregister_netdev(dev);
- #ifdef CONFIG_TC
- if (lp->slot >= 0)
-diff -urpNX dontdiff linux-2.6.12/drivers/net/gt64240eth.c linux_HEAD/drivers/net/gt64240eth.c
---- linux-2.6.12/drivers/net/gt64240eth.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/gt64240eth.c 2004-10-27 02:14:32.000000000 +0200
-@@ -0,0 +1,1672 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2001 Patton Electronics Company
-+ * Copyright (C) 2002 Momentum Computer
-+ *
-+ * Copyright 2000 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or support at mvista.com
-+ *
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
-+ *
-+ * Modified for the Gallileo/Marvell GT-64240 Communication Controller.
-+ *
-+ * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added
-+ * Manish Lachwani (lachwani at pmc-sierra.com) - 09/16/2003
-+ *
-+ * Modified for later version of Linux 2.4 kernel
-+ * Manish Lachwani (lachwani at pmc-sierra.com) - 04/29/2004
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/errno.h>
-+#include <linux/in.h>
-+#include <linux/ioport.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/skbuff.h>
-+#include <linux/delay.h>
-+#include <linux/ctype.h>
-+#include <linux/mii.h>
-+
-+#include <asm/irq.h>
-+#include <asm/bitops.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+
-+#define DESC_DATA_BE 1
-+
-+#include "gt64240eth.h"
-+
-+// enable this port (set hash size to 1/2K)
-+//- #define PORT_CONFIG pcrHS
-+#define PORT_CONFIG (pcrHS | pcrHD)
-+//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1<<pcrLPBKBit);
-+
-+// clear all the MIB ctr regs
-+#define EXT_CONFIG_CLEAR (pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen | pcxrPRIOrxOverride | pcxrRMIIen)
-+
-+/*
-+ * _debug level:
-+ * <= 2 none.
-+ * > 2 some warnings such as queue full, .....
-+ * > 3 lots of change-of-state messages.
-+ * > 4 EXTENSIVE data/descriptor dumps.
-+ */
-+
-+#ifdef GT64240_DEBUG
-+static int gt64240_debug = GT64240_DEBUG;
-+#else
-+static int gt64240_debug = 0;
-+#endif
-+
-+static int debug = -1;
-+
-+#define GT64240_MSG_ENABLE (NETIF_MSG_DRV | \
-+ NETIF_MSG_PROBE | \
-+ NETIF_MSG_LINK)
-+
-+
-+/********************************************************/
-+
-+// prototypes
-+static void gt64240_delay(int msec);
-+static int gt64240_add_hash_entry(struct net_device *dev,
-+ unsigned char *addr);
-+static void read_mib_counters(struct gt64240_private *gp);
-+static void dump_MII(struct net_device *dev);
-+static void dump_tx_desc(struct net_device *dev, int i);
-+static void dump_rx_desc(struct net_device *dev, int i);
-+static void dump_hw_addr(unsigned char *addr_str);
-+static void update_stats(struct gt64240_private *gp);
-+static void abort(struct net_device *dev, u32 abort_bits);
-+static void hard_stop(struct net_device *dev);
-+static void enable_ether_irq(struct net_device *dev);
-+static void disable_ether_irq(struct net_device *dev);
-+static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num);
-+static void reset_tx(struct net_device *dev);
-+static void reset_rx(struct net_device *dev);
-+static int gt64240_init(struct net_device *dev);
-+static int gt64240_open(struct net_device *dev);
-+static int gt64240_close(struct net_device *dev);
-+static int gt64240_tx(struct sk_buff *skb, struct net_device *dev);
-+#ifdef GT64240_NAPI
-+static int gt64240_poll(struct net_device *dev, int *budget);
-+static int gt64240_rx(struct net_device *dev, u32 status, int budget);
-+#else
-+static int gt64240_rx(struct net_device *dev, u32 status);
-+#endif
-+static void gt64240_tx_timeout(struct net_device *dev);
-+static void gt64240_set_rx_mode(struct net_device *dev);
-+static struct net_device_stats *gt64240_get_stats(struct net_device *dev);
-+
-+extern char *__init prom_getcmdline(void);
-+extern int prom_get_mac_addrs(unsigned char
-+ station_addr[NUM_INTERFACES][6]);
-+
-+static char version[] __devinitdata =
-+ "gt64240eth.o: version 0.1, <www.patton.com>\n";
-+
-+// PHY device addresses
-+static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa };
-+
-+// Need real Ethernet addresses -- in parse_mac_addr_options(),
-+// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline().
-+static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = {
-+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05},
-+ {0x01, 0x02, 0x03, 0x04, 0x05, 0x06},
-+ {0x02, 0x03, 0x04, 0x05, 0x06, 0x07}
-+};
-+
-+static int max_interrupt_work = 32;
-+
-+/*
-+ * Base address and interupt of the GT64240 ethernet controllers
-+ */
-+static struct {
-+ unsigned int port;
-+ int irq;
-+} gt64240_iflist[NUM_INTERFACES] = {
-+ {
-+ GT64240_ETH0_BASE, 8}, {
-+ GT64240_ETH1_BASE, 8}, {
-+ GT64240_ETH2_BASE, 8}
-+};
-+
-+static void gt64240_delay(int ms)
-+{
-+ if (in_interrupt())
-+ return;
-+ else {
-+ current->state = TASK_INTERRUPTIBLE;
-+ schedule_timeout(ms * HZ / 1000);
-+ }
-+}
-+
-+unsigned char prom_mac_addr_base[6];
-+
-+int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6])
-+{
-+ memcpy(station_addr[0], prom_mac_addr_base, 6);
-+ memcpy(station_addr[1], prom_mac_addr_base, 6);
-+ memcpy(station_addr[2], prom_mac_addr_base, 6);
-+
-+ station_addr[1][5] += 1;
-+ station_addr[2][5] += 2;
-+
-+ return 0;
-+}
-+
-+void parse_mac_addr_options(void)
-+{
-+ prom_get_mac_addrs(gt64240_station_addr);
-+}
-+
-+static int read_MII(struct net_device *dev, int phy, int reg)
-+{
-+ int timedout = 20;
-+ u32 smir = smirOpCode | (phy << smirPhyAdBit) |
-+ (reg << smirRegAdBit);
-+
-+ // wait for last operation to complete
-+ while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) {
-+ // snooze for 1 msec and check again
-+ gt64240_delay(1);
-+
-+ if (--timedout == 0) {
-+ printk("%s: read_MII busy timeout!!\n", dev->name);
-+ return -1;
-+ }
-+ }
-+
-+ GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
-+
-+ timedout = 20;
-+ // wait for read to complete
-+ while (!
-+ ((smir =
-+ GT64240_READ(GT64240_ETH_SMI_REG)) & smirReadValid)) {
-+ // snooze for 1 msec and check again
-+ gt64240_delay(1);
-+
-+ if (--timedout == 0) {
-+ printk("%s: read_MII timeout!!\n", dev->name);
-+ return -1;
-+ }
-+ }
-+
-+ return (int) (smir & smirDataMask);
-+}
-+
-+static void gp_get_drvinfo (struct net_device *dev,
-+ struct ethtool_drvinfo *info)
-+{
-+ strcpy(info->driver, "gt64260");
-+ strcpy(info->version, version);
-+}
-+
-+static int gp_get_settings(struct net_device *dev,
-+ struct ethtool_cmd *cmd)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int rc;
-+
-+ spin_lock_irq(&gp->lock);
-+ rc = mii_ethtool_gset(&gp->mii_if, cmd);
-+ spin_unlock_irq(&gp->lock);
-+ return rc;
-+}
-+
-+static int gp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int rc;
-+
-+ spin_lock_irq(&gp->lock);
-+ rc = mii_ethtool_sset(&gp->mii_if, cmd);
-+ spin_unlock_irq(&gp->lock);
-+ return rc;
-+}
-+
-+static int gp_nway_reset(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ return mii_nway_restart(&gp->mii_if);
-+}
-+
-+static u32 gp_get_link(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ return mii_link_ok(&gp->mii_if);
-+}
-+
-+static u32 gp_get_msglevel(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ return gp->msg_enable;
-+}
-+
-+static void gp_set_msglevel(struct net_device *dev, u32 value)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ gp->msg_enable = value;
-+}
-+
-+static struct ethtool_ops gp_ethtool_ops = {
-+ .get_drvinfo = gp_get_drvinfo,
-+ .get_settings = gp_get_settings,
-+ .set_settings = gp_set_settings,
-+ .nway_reset = gp_nway_reset,
-+ .get_link = gp_get_link,
-+ .get_msglevel = gp_get_msglevel,
-+ .set_msglevel = gp_set_msglevel,
-+};
-+
-+static int gt64240_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ struct mii_ioctl_data *data =
-+ (struct mii_ioctl_data *) &rq->ifr_data;
-+ int retval;
-+
-+ if (!netif_running(dev))
-+ return -EINVAL;
-+
-+ spin_lock_irq(&gp->lock);
-+ retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL);
-+ spin_unlock_irq(&gp->lock);
-+
-+ return retval;
-+}
-+
-+static void dump_tx_desc(struct net_device *dev, int i)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ gt64240_td_t *td = &gp->tx_ring[i];
-+
-+ printk("%s:tx[%d]: self=%p cmd=%08x, cnt=%4d. bufp=%08x, next=%08x\n",
-+ dev->name, i, td, td->cmdstat, td->byte_cnt, td->buff_ptr,
-+ td->next);
-+}
-+
-+static void dump_rx_desc(struct net_device *dev, int i)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ gt64240_rd_t *rd = &gp->rx_ring[i];
-+
-+ printk("%s:rx_dsc[%d]: self=%p cst=%08x,size=%4d. cnt=%4d. "
-+ "bufp=%08x, next=%08x\n",
-+ dev->name, i, rd, rd->cmdstat, rd->buff_sz, rd->byte_cnt,
-+ rd->buff_ptr, rd->next);
-+}
-+
-+// These routines work, just disabled to avoid compile warnings
-+static void write_MII(struct net_device *dev, int phy, int reg, int data)
-+{
-+ u32 smir = (phy << smirPhyAdBit) | (reg << smirRegAdBit) | data;
-+ int timedout = 20;
-+
-+ // wait for last operation to complete
-+ while (GT64240_READ(GT64240_ETH_SMI_REG) & smirBusy) {
-+ // snooze for 1 msec and check again
-+ gt64240_delay(1);
-+
-+ if (--timedout == 0) {
-+ printk("%s: write_MII busy timeout!!\n",
-+ dev->name);
-+ return;
-+ }
-+ }
-+
-+ GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
-+}
-+
-+static void dump_MII(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int i, val;
-+
-+ for (i = 0; i < 7; i++) {
-+ if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
-+ printk("%s: MII Reg %d=%x\n", dev->name, i, val);
-+ }
-+ for (i = 16; i < 21; i++) {
-+ if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
-+ printk("%s: MII Reg %d=%x\n", dev->name, i, val);
-+ }
-+}
-+
-+
-+static void dump_hw_addr(unsigned char *addr_str)
-+{
-+ int i;
-+ for (i = 0; i < 6; i++) {
-+ printk("%2.2x", addr_str[i]);
-+ printk(i < 5 ? ":" : "\n");
-+ }
-+}
-+
-+static int gt64240_add_hash_entry(struct net_device *dev,
-+ unsigned char *addr)
-+{
-+ static unsigned char swapped[256];
-+ struct gt64240_private *gp;
-+ u32 value1, value0, *entry;
-+ unsigned char hash_ea[6];
-+ static int flag = 0;
-+ u16 hashResult;
-+ int i;
-+
-+ if (flag == 0) { /* Create table to swap bits in a byte */
-+ flag = 1;
-+ for (i = 0; i < 256; i++) {
-+ swapped[i] = (i & 0x01) << 7;
-+ swapped[i] |= (i & 0x02) << 5;
-+ swapped[i] |= (i & 0x04) << 3;
-+ swapped[i] |= (i & 0x08) << 1;
-+ swapped[i] |= (i & 0x10) >> 1;
-+ swapped[i] |= (i & 0x20) >> 3;
-+ swapped[i] |= (i & 0x40) >> 5;
-+ swapped[i] |= (i & 0x80) >> 7;
-+ }
-+ }
-+
-+ for (i = 0; i < 6; i++) { /* swap bits from mac to create hash mac */
-+ hash_ea[i] = swapped[addr[i]];
-+ }
-+
-+ gp = netdev_priv(dev);
-+
-+ /* create hash entry address */
-+ hashResult = (((hash_ea[5] >> 2) & 0x3F) << 9) & 0x7E00;
-+ hashResult |= ((hash_ea[4] & 0x7F) << 2) | (hash_ea[5] & 0x03);
-+ hashResult ^=
-+ ((hash_ea[3] & 0xFF) << 1) | ((hash_ea[4] >> 7) & 0x01);
-+ hashResult ^= ((hash_ea[1] & 0x01) << 8) | (hash_ea[2] & 0xFF);
-+
-+ value0 = hteValid | hteRD; /* Create hash table entry value */
-+ value0 |= (u32) addr[0] << 3;
-+ value0 |= (u32) addr[1] << 11;
-+ value0 |= (u32) addr[2] << 19;
-+ value0 |= ((u32) addr[3] & 0x1f) << 27;
-+
-+ value1 = ((u32) addr[3] >> 5) & 0x07;
-+ value1 |= (u32) addr[4] << 3;
-+ value1 |= (u32) addr[5] << 11;
-+
-+ /* Inset entry value into hash table */
-+ for (i = 0; i < HASH_HOP_NUMBER; i++) {
-+ entry = (u32 *) ((u32) gp->hash_table +
-+ (((u32) hashResult & 0x07ff) << 3));
-+ if ((*entry & hteValid) && !(*entry & hteSkip)) {
-+ hashResult += 2; /* oops, occupied, go to next entry */
-+ } else {
-+#ifdef __LITTLE_ENDIAN
-+ entry[1] = value1;
-+ entry[0] = value0;
-+#else
-+ entry[0] = value1;
-+ entry[1] = value0;
-+#endif
-+ break;
-+ }
-+ }
-+ if (i >= HASH_HOP_NUMBER) {
-+ printk("%s: gt64240_add_hash_entry expired!\n", dev->name);
-+ return (-1);
-+ }
-+ return (0);
-+}
-+
-+
-+static void read_mib_counters(struct gt64240_private *gp)
-+{
-+ u32 *mib_regs = (u32 *) & gp->mib;
-+ int i;
-+
-+ for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++)
-+ mib_regs[i] =
-+ GT64240ETH_READ(gp,
-+ GT64240_ETH_MIB_COUNT_BASE +
-+ i * sizeof(u32));
-+}
-+
-+
-+static void update_stats(struct gt64240_private *gp)
-+{
-+ mib_counters_t *mib = &gp->mib;
-+ struct net_device_stats *stats = &gp->stats;
-+
-+ read_mib_counters(gp);
-+
-+ stats->rx_packets = mib->totalFramesReceived;
-+ stats->tx_packets = mib->framesSent;
-+ stats->rx_bytes = mib->totalByteReceived;
-+ stats->tx_bytes = mib->byteSent;
-+ stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
-+ //the tx error counters are incremented by the ISR
-+ //rx_dropped incremented by gt64240_rx
-+ //tx_dropped incremented by gt64240_tx
-+ stats->multicast = mib->multicastFramesReceived;
-+ // collisions incremented by gt64240_tx_complete
-+ stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
-+ // The RxError condition means the Rx DMA encountered a
-+ // CPU owned descriptor, which, if things are working as
-+ // they should, means the Rx ring has overflowed.
-+ stats->rx_over_errors = mib->macRxError;
-+ stats->rx_crc_errors = mib->cRCError;
-+}
-+
-+static void abort(struct net_device *dev, u32 abort_bits)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int timedout = 100; // wait up to 100 msec for hard stop to complete
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: abort\n", dev->name);
-+
-+ // Return if neither Rx or Tx abort bits are set
-+ if (!(abort_bits & (sdcmrAR | sdcmrAT)))
-+ return;
-+
-+ // make sure only the Rx/Tx abort bits are set
-+ abort_bits &= (sdcmrAR | sdcmrAT);
-+
-+ spin_lock(&gp->lock);
-+
-+ // abort any Rx/Tx DMA immediately
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: abort: SDMA cmd = %x/%x\n",
-+ dev->name, abort_bits, GT64240ETH_READ(gp,
-+ GT64240_ETH_SDMA_COMM));
-+
-+ // wait for abort to complete
-+ while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) {
-+ // snooze for 20 msec and check again
-+ gt64240_delay(1);
-+
-+ if (--timedout == 0) {
-+ printk("%s: abort timeout!!\n", dev->name);
-+ break;
-+ }
-+ }
-+
-+ spin_unlock(&gp->lock);
-+}
-+
-+
-+static void hard_stop(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: hard stop\n", dev->name);
-+
-+ disable_ether_irq(dev);
-+
-+ abort(dev, sdcmrAR | sdcmrAT);
-+
-+ // disable port
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0);
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_hard_stop: Port Config=%x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_PORT_CONFIG));
-+
-+}
-+
-+static void gt64240_tx_complete(struct net_device *dev, u32 status)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int nextOut, cdp;
-+ gt64240_td_t *td;
-+ u32 cmdstat;
-+
-+ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
-+ - gp->tx_ring_dma) / sizeof(gt64240_td_t);
-+
-+ if (gt64240_debug > 3) { /*+prk17aug01 */
-+ nextOut = gp->tx_next_out;
-+ printk
-+ ("%s: tx_complete: TX_PTR0=0x%08x, cdp=%d. nextOut=%d.\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_CURR_TX_DESC_PTR0),
-+ cdp, nextOut);
-+ td = &gp->tx_ring[nextOut];
-+ }
-+
-+/*** NEED to check and CLEAR these errors every time thru here: ***/
-+ if (gt64240_debug > 2) {
-+ if (GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE))
-+ printk
-+ ("%s: gt64240_tx_complete: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
-+ dev->name,
-+ GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
-+ GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
-+ GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
-+ GT64240_WRITE(COMM_UNIT_INTERRUPT_CAUSE, 0);
-+ }
-+ // Continue until we reach the current descriptor pointer
-+ for (nextOut = gp->tx_next_out; nextOut != cdp;
-+ nextOut = (nextOut + 1) % TX_RING_SIZE) {
-+
-+ if (--gp->intr_work_done == 0)
-+ break;
-+
-+ td = &gp->tx_ring[nextOut];
-+ cmdstat = td->cmdstat;
-+
-+ if (cmdstat & (u32) txOwn) {
-+ // DMA is not finished writing descriptor???
-+ // Leave and come back later to pick-up where we left off.
-+ break;
-+ }
-+ // increment Tx error stats
-+ if (cmdstat & (u32) txErrorSummary) {
-+ if (gt64240_debug > 2)
-+ printk
-+ ("%s: tx_complete: Tx error, cmdstat = %x\n",
-+ dev->name, cmdstat);
-+ gp->stats.tx_errors++;
-+ if (cmdstat & (u32) txReTxLimit)
-+ gp->stats.tx_aborted_errors++;
-+ if (cmdstat & (u32) txUnderrun)
-+ gp->stats.tx_fifo_errors++;
-+ if (cmdstat & (u32) txLateCollision)
-+ gp->stats.tx_window_errors++;
-+ }
-+
-+ if (cmdstat & (u32) txCollision)
-+ gp->stats.collisions +=
-+ (unsigned long) ((cmdstat & txReTxCntMask) >>
-+ txReTxCntBit);
-+
-+ // Wake the queue if the ring was full
-+ if (gp->tx_full) {
-+ gp->tx_full = 0;
-+ if (gp->last_psr & psrLink) {
-+ netif_wake_queue(dev);
-+ }
-+ }
-+ // decrement tx ring buffer count
-+ if (gp->tx_count)
-+ gp->tx_count--;
-+
-+ // free the skb
-+ if (gp->tx_skbuff[nextOut]) {
-+ if (gt64240_debug > 3)
-+ printk
-+ ("%s: tx_complete: good Tx, skb=%p\n",
-+ dev->name, gp->tx_skbuff[nextOut]);
-+ dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
-+ gp->tx_skbuff[nextOut] = NULL;
-+ } else {
-+ printk("%s: tx_complete: no skb!\n", dev->name);
-+ }
-+ }
-+
-+ gp->tx_next_out = nextOut;
-+
-+ if ((status & icrTxEndLow) && gp->tx_count != 0) {
-+ // we must restart the DMA
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+ sdcmrERD | sdcmrTXDL);
-+ }
-+}
-+
-+static irqreturn_t gt64240_interrupt(int irq, void *dev_id,
-+ struct pt_regs *regs)
-+{
-+ struct net_device *dev = (struct net_device *) dev_id;
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ u32 status;
-+
-+ if (dev == NULL) {
-+ printk("%s: isr: null dev ptr\n", dev->name);
-+ return IRQ_NONE;
-+ }
-+
-+ spin_lock(&gp->lock);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: isr: entry\n", dev->name);
-+
-+ gp->intr_work_done = max_interrupt_work;
-+
-+ while (gp->intr_work_done > 0) {
-+
-+ status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
-+#ifdef GT64240_NAPI
-+ /* dont ack Rx interrupts */
-+ if (!(status & icrRxBuffer))
-+ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+#else
-+ // ACK interrupts
-+ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+#endif
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: isr: work=%d., icr=%x\n", dev->name,
-+ gp->intr_work_done, status);
-+
-+ if ((status & icrEtherIntSum) == 0) {
-+ if (!(status &
-+ (icrTxBufferLow | icrTxBufferHigh |
-+ icrRxBuffer))) {
-+ /* exit from the while() loop */
-+ break;
-+ }
-+ }
-+
-+ if (status & icrMIIPhySTC) {
-+ u32 psr =
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS);
-+ if (gp->last_psr != psr) {
-+ printk("%s: port status: 0x%08x\n",
-+ dev->name, psr);
-+ printk
-+ ("%s: %s MBit/s, %s-duplex, flow-control %s, link is %s,\n",
-+ dev->name,
-+ psr & psrSpeed ? "100" : "10",
-+ psr & psrDuplex ? "full" : "half",
-+ psr & psrFctl ? "disabled" :
-+ "enabled",
-+ psr & psrLink ? "up" : "down");
-+ printk
-+ ("%s: TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n",
-+ dev->name,
-+ psr & psrTxLow ? "running" :
-+ "stopped",
-+ psr & psrTxHigh ? "running" :
-+ "stopped",
-+ psr & psrTxInProg ? "on" : "off");
-+
-+ if ((psr & psrLink) && !gp->tx_full &&
-+ netif_queue_stopped(dev)) {
-+ printk
-+ ("%s: isr: Link up, waking queue.\n",
-+ dev->name);
-+ netif_wake_queue(dev);
-+ } else if (!(psr & psrLink)
-+ && !netif_queue_stopped(dev)) {
-+ printk
-+ ("%s: isr: Link down, stopping queue.\n",
-+ dev->name);
-+ netif_stop_queue(dev);
-+ }
-+
-+ gp->last_psr = psr;
-+ }
-+ }
-+
-+ if (status & (icrTxBufferLow | icrTxEndLow))
-+ gt64240_tx_complete(dev, status);
-+
-+ if (status & icrRxBuffer) {
-+#ifdef GT64240_NAPI
-+ if (netif_rx_schedule_prep(dev)) {
-+ disable_ether_irq(dev);
-+ __netif_rx_schedule(dev);
-+ }
-+#else
-+ gt64240_rx(dev, status);
-+#endif
-+ }
-+ // Now check TX errors (RX errors were handled in gt64240_rx)
-+ if (status & icrTxErrorLow) {
-+ printk("%s: isr: Tx resource error\n", dev->name);
-+ }
-+
-+ if (status & icrTxUdr) {
-+ printk("%s: isr: Tx underrun error\n", dev->name);
-+ }
-+ }
-+
-+ if (gp->intr_work_done == 0) {
-+ // ACK any remaining pending interrupts
-+ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+ if (gt64240_debug > 3)
-+ printk("%s: isr: hit max work\n", dev->name);
-+ }
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: isr: exit, icr=%x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_INT_CAUSE));
-+
-+ spin_unlock(&gp->lock);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void enable_ether_irq(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ u32 intMask;
-+
-+ intMask =
-+ icrTxBufferLow | icrTxEndLow | icrTxErrorLow |
-+ icrTxBufferHigh | icrTxEndHigh | icrTxErrorHigh | icrTxUdr |
-+ icrRxBuffer | icrRxOVR | icrRxError | icrMIIPhySTC |
-+ icrEtherIntSum;
-+
-+
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */
-+ // unmask device interrupts:
-+ GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask);
-+
-+ // now route ethernet interrupts to GT PCI1 (eth0 and eth1 will be
-+ // sharing it).
-+ intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
-+ intMask |= 1 << gp->port_num;
-+ MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
-+}
-+
-+static void disable_ether_irq(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ u32 intMask;
-+
-+ intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
-+ intMask &= ~(1 << gp->port_num);
-+ MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
-+
-+ // mask all device interrupts:
-+ GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0);
-+}
-+
-+/*
-+ * Probe for a GT64240 ethernet controller.
-+ */
-+static int __init gt64240_probe(void)
-+{
-+ int found = 0;
-+ int i;
-+
-+ parse_mac_addr_options();
-+
-+ for (i = 0; i < NUM_INTERFACES; i++) {
-+ unsigned long base_addr = gt64240_iflist[i].port;
-+
-+ if (check_region(base_addr, GT64240_ETH_IO_SIZE)) {
-+ printk("gt64240_probe: ioaddr 0x%lx taken?\n",
-+ base_addr);
-+ continue;
-+ }
-+
-+ if (gt64240_probe1(base_addr, gt64240_iflist[i].irq, i) == 0) {
-+ /*
-+ * Does not seem to be the "traditional" way folks do
-+ * this, but I want to init both eth ports if at all
-+ * possible!
-+ *
-+ * So, until I find out the "correct" way to do this:
-+ */
-+ if (++found == NUM_INTERFACES) /* That's all of them */
-+ return 0;
-+ }
-+ }
-+
-+ if (found)
-+ return 0; /* as long as we found at least one! */
-+
-+ return -ENODEV;
-+}
-+
-+module_init(gt64240_probe);
-+
-+static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num)
-+{
-+ struct net_device *dev = NULL;
-+ static unsigned version_printed = 0;
-+ struct gt64240_private *gp = NULL;
-+ int retval;
-+ u32 cpuConfig;
-+
-+ dev = alloc_etherdev(sizeof(struct gt64240_private));
-+ if (!dev)
-+ return -ENOMEM;
-+
-+ if (irq < 0) {
-+ printk
-+ ("gt64240_probe1: irq unknown - probing not supported\n");
-+ return -ENODEV;
-+ }
-+#if 1 /* KLUDGE Alert: no check on return value: */
-+ if (!request_region(ioaddr, GT64240_ETH_IO_SIZE, "gt64240eth"))
-+ printk("*** request_region() failed!\n");
-+#endif
-+
-+ cpuConfig = GT64240_READ(CPU_CONFIGURATION);
-+ printk("gt64240_probe1: cpu in %s-endian mode\n",
-+ (cpuConfig & (1 << 12)) ? "little" : "big");
-+
-+ printk("%s: GT64240 found at ioaddr 0x%lx, irq %d.\n",
-+ dev->name, ioaddr, irq);
-+
-+ if (gt64240_debug && version_printed++ == 0)
-+ printk("%s: %s", dev->name, version);
-+
-+ /* private struct aligned and zeroed by init_etherdev */
-+ /* Fill in the 'dev' fields. */
-+ dev->base_addr = ioaddr;
-+ dev->irq = irq;
-+ memcpy(dev->dev_addr, gt64240_station_addr[port_num],
-+ sizeof(dev->dev_addr));
-+
-+ printk("%s: HW Address ", dev->name);
-+ dump_hw_addr(dev->dev_addr);
-+
-+ gp = dev->priv;
-+
-+ gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug);
-+ gp->port_num = port_num;
-+ gp->io_size = GT64240_ETH_IO_SIZE;
-+ gp->port_offset = port_num * GT64240_ETH_IO_SIZE;
-+ gp->phy_addr = gt64240_phy_addr[port_num];
-+
-+ printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num);
-+
-+#ifdef GT64240_NAPI
-+ printk("Rx NAPI supported \n");
-+#endif
-+
-+/* MII Initialization */
-+ gp->mii_if.dev = dev;
-+ gp->mii_if.phy_id = dev->base_addr;
-+ gp->mii_if.mdio_read = read_MII;
-+ gp->mii_if.mdio_write = write_MII;
-+ gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE);
-+
-+ // Allocate Rx and Tx descriptor rings
-+ if (gp->rx_ring == NULL) {
-+ // All descriptors in ring must be 16-byte aligned
-+ gp->rx_ring = dma_alloc_noncoherent(NULL,
-+ sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+ sizeof(gt64240_td_t) * TX_RING_SIZE,
-+ &gp->rx_ring_dma, GFP_KERNEL);
-+ if (gp->rx_ring == NULL) {
-+ retval = -ENOMEM;
-+ goto free_region;
-+ }
-+
-+ gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE);
-+ gp->tx_ring_dma =
-+ gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE;
-+ }
-+ // Allocate the Rx Data Buffers
-+ if (gp->rx_buff == NULL) {
-+ gp->rx_buff = dma_alloc_coherent(NULL,
-+ PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma,
-+ GFP_KERNEL);
-+ if (gp->rx_buff == NULL) {
-+ dma_free_noncoherent(NULL,
-+ sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+ sizeof(gt64240_td_t) * TX_RING_SIZE,
-+ gp->rx_ring, gp->rx_ring_dma);
-+ retval = -ENOMEM;
-+ goto free_region;
-+ }
-+ }
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_probe1, rx_ring=%p, tx_ring=%p\n",
-+ dev->name, gp->rx_ring, gp->tx_ring);
-+
-+ // Allocate Rx Hash Table
-+ if (gp->hash_table == NULL) {
-+ gp->hash_table = dma_alloc_coherent(NULL,
-+ RX_HASH_TABLE_SIZE, &gp->hash_table_dma,
-+ GFP_KERNEL);
-+ if (gp->hash_table == NULL) {
-+ dma_free_noncoherent(NULL,
-+ sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+ sizeof(gt64240_td_t) * TX_RING_SIZE,
-+ gp->rx_ring, gp->rx_ring_dma);
-+ dma_free_noncoherent(NULL, PKT_BUF_SZ * RX_RING_SIZE,
-+ gp->rx_buff, gp->rx_buff_dma);
-+ retval = -ENOMEM;
-+ goto free_region;
-+ }
-+ }
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_probe1, hash=%p\n",
-+ dev->name, gp->hash_table);
-+
-+ spin_lock_init(&gp->lock);
-+
-+ dev->open = gt64240_open;
-+ dev->hard_start_xmit = gt64240_tx;
-+ dev->stop = gt64240_close;
-+ dev->get_stats = gt64240_get_stats;
-+ dev->do_ioctl = gt64240_ioctl;
-+ dev->set_multicast_list = gt64240_set_rx_mode;
-+ dev->tx_timeout = gt64240_tx_timeout;
-+ dev->watchdog_timeo = GT64240ETH_TX_TIMEOUT;
-+
-+#ifdef GT64240_NAPI
-+ dev->poll = gt64240_poll;
-+ dev->weight = 64;
-+#endif
-+ dev->ethtool_ops = &gp_ethtool_ops;
-+
-+ /* Fill in the fields of the device structure with ethernet values. */
-+ return 0;
-+
-+free_region:
-+ release_region(ioaddr, gp->io_size);
-+ unregister_netdev(dev);
-+ free_netdev(dev);
-+ printk("%s: gt64240_probe1 failed. Returns %d\n",
-+ dev->name, retval);
-+ return retval;
-+}
-+
-+
-+static void reset_tx(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int i;
-+
-+ abort(dev, sdcmrAT);
-+
-+ for (i = 0; i < TX_RING_SIZE; i++) {
-+ if (gp->tx_skbuff[i]) {
-+ if (in_interrupt())
-+ dev_kfree_skb_irq(gp->tx_skbuff[i]);
-+ else
-+ dev_kfree_skb(gp->tx_skbuff[i]);
-+ gp->tx_skbuff[i] = NULL;
-+ }
-+//- gp->tx_ring[i].cmdstat = 0; // CPU owns
-+ gp->tx_ring[i].cmdstat =
-+ (u32) (txGenCRC | txEI | txPad | txFirst | txLast);
-+ gp->tx_ring[i].byte_cnt = 0;
-+ gp->tx_ring[i].buff_ptr = 0;
-+ gp->tx_ring[i].next =
-+ gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1);
-+ if (gt64240_debug > 4)
-+ dump_tx_desc(dev, i);
-+ }
-+ /* Wrap the ring. */
-+ gp->tx_ring[i - 1].next = gp->tx_ring_dma;
-+ if (gt64240_debug > 4)
-+ dump_tx_desc(dev, i - 1);
-+
-+ // setup only the lowest priority TxCDP reg
-+ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
-+ gp->tx_ring_dma);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0); /* ROLLINS */
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0])); /* ROLLINS */
-+
-+ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0);
-+
-+ // init Tx indeces and pkt counter
-+ gp->tx_next_in = gp->tx_next_out = 0;
-+ gp->tx_count = 0;
-+}
-+
-+static void reset_rx(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int i;
-+
-+ abort(dev, sdcmrAR);
-+
-+ for (i = 0; i < RX_RING_SIZE; i++) {
-+ gp->rx_ring[i].next =
-+ gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1);
-+ gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ;
-+ gp->rx_ring[i].buff_sz = PKT_BUF_SZ;
-+ gp->rx_ring[i].byte_cnt = 0; /* just for debug printk's */
-+ // Give ownership to device, set first and last, enable interrupt
-+ gp->rx_ring[i].cmdstat =
-+ (uint32_t) (rxFirst | rxLast | rxOwn | rxEI);
-+ if (gt64240_debug > 4)
-+ dump_rx_desc(dev, i);
-+ }
-+ /* Wrap the ring. */
-+ gp->rx_ring[i - 1].next = gp->rx_ring_dma;
-+ if (gt64240_debug > 4)
-+ dump_rx_desc(dev, i - 1);
-+
-+ // Setup only the lowest priority RxFDP and RxCDP regs
-+ for (i = 0; i < 4; i++) {
-+ if (i == 0) {
-+ GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0,
-+ gp->rx_ring_dma);
-+ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0,
-+ gp->rx_ring_dma);
-+ } else {
-+ GT64240ETH_WRITE(gp,
-+ GT64240_ETH_1ST_RX_DESC_PTR0 +
-+ i * 4, 0);
-+ GT64240ETH_WRITE(gp,
-+ GT64240_ETH_CURR_RX_DESC_PTR0 +
-+ i * 4, 0);
-+ }
-+ }
-+
-+ // init Rx NextOut index
-+ gp->rx_next_out = 0;
-+}
-+
-+
-+static int gt64240_init(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+
-+ if (gt64240_debug > 3) {
-+ printk("%s: gt64240_init: dev=%p\n", dev->name, dev);
-+ printk("%s: gt64240_init: scs0_lo=%04x, scs0_hi=%04x\n",
-+ dev->name, GT64240_READ(0x008),
-+ GT64240_READ(0x010));
-+ printk("%s: gt64240_init: scs1_lo=%04x, scs1_hi=%04x\n",
-+ dev->name, GT64240_READ(0x208),
-+ GT64240_READ(0x210));
-+ printk("%s: gt64240_init: scs2_lo=%04x, scs2_hi=%04x\n",
-+ dev->name, GT64240_READ(0x018),
-+ GT64240_READ(0x020));
-+ printk("%s: gt64240_init: scs3_lo=%04x, scs3_hi=%04x\n",
-+ dev->name, GT64240_READ(0x218),
-+ GT64240_READ(0x220));
-+ }
-+ // Stop and disable Port
-+ hard_stop(dev);
-+
-+ GT64240_WRITE(COMM_UNIT_INTERRUPT_MASK, 0x07070777); /*+prk21aug01 */
-+ if (gt64240_debug > 2)
-+ printk
-+ ("%s: gt64240_init: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
-+ dev->name, GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
-+ GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
-+ GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
-+
-+ // Set-up hash table
-+ memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
-+ gp->hash_mode = 0;
-+ // Add a single entry to hash table - our ethernet address
-+ gt64240_add_hash_entry(dev, dev->dev_addr);
-+ // Set-up DMA ptr to hash table
-+ GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma);
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Hash Tbl Ptr=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR));
-+
-+ // Setup Tx
-+ reset_tx(dev);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Curr Tx Desc Ptr0=%x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_CURR_TX_DESC_PTR0));
-+
-+ // Setup Rx
-+ reset_rx(dev);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: 1st/Curr Rx Desc Ptr0=%x/%x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_1ST_RX_DESC_PTR0),
-+ GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0));
-+
-+ if (gt64240_debug > 3)
-+ dump_MII(dev);
-+
-+ /* force a PHY reset -- self-clearing! */
-+ write_MII(dev, gp->phy_addr, 0, 0x8000);
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: PhyAD=%x\n", dev->name,
-+ GT64240_READ(GT64240_ETH_PHY_ADDR_REG));
-+
-+ // setup DMA
-+ // We want the Rx/Tx DMA to write/read data to/from memory in
-+ // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
-+#ifdef DESC_DATA_BE
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG,
-+ (0xf << sdcrRCBit) | sdcrRIFB | (3 <<
-+ sdcrBSZBit));
-+#else
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT |
-+//- (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
-+ (0xf << sdcrRCBit) | sdcrRIFB | (2 <<
-+ sdcrBSZBit));
-+#endif
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: SDMA Config=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG));
-+
-+#if 0
-+ // start Rx DMA
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+#endif
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: SDMA Cmd =%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM));
-+
-+#if 1
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG);
-+#endif
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Port Config=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+
-+ /*
-+ * Disable all Type-of-Service queueing. All Rx packets will be
-+ * treated normally and will be sent to the lowest priority
-+ * queue.
-+ *
-+ * Disable flow-control for now. FIX! support flow control?
-+ */
-+
-+#if 1
-+ // clear all the MIB ctr regs
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
-+ EXT_CONFIG_CLEAR);
-+ read_mib_counters(gp);
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
-+ EXT_CONFIG_CLEAR | pcxrMIBclrMode);
-+
-+#endif
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Port Config Ext=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT));
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Port Command=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND));
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0);
-+
-+ netif_start_queue(dev);
-+
-+ /* enable the port */
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
-+ (PORT_CONFIG | pcrEN));
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_init: Port Config=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+#if 1
-+ // start Rx DMA
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+#endif
-+
-+
-+ // enable interrupts
-+ enable_ether_irq(dev);
-+
-+//--- gp->last_psr |= psrLink; /* KLUDGE ALERT */
-+
-+ // we should now be receiving frames
-+ return 0;
-+}
-+
-+
-+static int gt64240_open(struct net_device *dev)
-+{
-+ int retval;
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_open: dev=%p\n", dev->name, dev);
-+
-+ if ((retval = request_irq(dev->irq, >64240_interrupt,
-+ SA_SHIRQ, dev->name, dev))) {
-+ printk("%s: unable to get IRQ %d\n", dev->name, dev->irq);
-+
-+ return retval;
-+ }
-+ // Initialize and startup the GT-64240 ethernet port
-+ if ((retval = gt64240_init(dev))) {
-+ printk("%s: error in gt64240_open\n", dev->name);
-+ free_irq(dev->irq, dev);
-+
-+ return retval;
-+ }
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_open: Initialization done.\n",
-+ dev->name);
-+
-+ return 0;
-+}
-+
-+static int gt64240_close(struct net_device *dev)
-+{
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_close: dev=%p\n", dev->name, dev);
-+
-+ // stop the device
-+ if (netif_device_present(dev)) {
-+ netif_stop_queue(dev);
-+ hard_stop(dev);
-+ }
-+
-+ free_irq(dev->irq, dev);
-+
-+ return 0;
-+}
-+
-+#ifdef GT64240_NAPI
-+/*
-+ * Function will release Tx skbs which are now complete
-+ */
-+static void gt64240_tx_fill(struct net_device *dev, u32 status)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ int nextOut, cdp;
-+ gt64240_td_t *td;
-+ u32 cmdstat;
-+
-+ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
-+ - gp->tx_ring_dma) / sizeof(gt64240_td_t);
-+
-+ for (nextOut = gp->tx_next_out; nextOut != cdp;
-+ nextOut = (nextOut + 1) % TX_RING_SIZE) {
-+ if (--gp->intr_work_done == 0)
-+ break;
-+
-+ td = &gp->tx_ring[nextOut];
-+ cmdstat = td->cmdstat;
-+
-+ if (cmdstat & (u32) txOwn)
-+ break;
-+
-+ if (gp->tx_full) {
-+ gp->tx_full = 0;
-+ if (gp->last_psr & psrLink) {
-+ netif_wake_queue(dev);
-+ }
-+ }
-+ // decrement tx ring buffer count
-+ if (gp->tx_count)
-+ gp->tx_count--;
-+
-+ // free the skb
-+ if (gp->tx_skbuff[nextOut]) {
-+ dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
-+ gp->tx_skbuff[nextOut] = NULL;
-+ }
-+ }
-+
-+ gp->tx_next_out = nextOut;
-+
-+ if ((status & icrTxEndLow) && gp->tx_count != 0)
-+ // we must restart the DMA
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+ sdcmrERD | sdcmrTXDL);
-+}
-+
-+/*
-+ * Main function for NAPI
-+ */
-+static int gt64240_poll(struct net_device *dev, int *budget)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ unsigned long flags;
-+ int done = 1, orig_budget, work_done;
-+ u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
-+
-+ spin_lock_irqsave(&gp->lock, flags);
-+ gt64240_tx_fill(dev, status);
-+
-+ if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) !=
-+ gp->rx_next_out) {
-+ orig_budget = *budget;
-+ if (orig_budget > dev->quota)
-+ orig_budget = dev->quota;
-+
-+ work_done = gt64240_rx(dev, status, orig_budget);
-+ *budget -= work_done;
-+ dev->quota -= work_done;
-+ if (work_done >= orig_budget)
-+ done = 0;
-+ if (done) {
-+ __netif_rx_complete(dev);
-+ enable_ether_irq(dev);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+
-+ return (done ? 0 : 1);
-+}
-+#endif
-+
-+static int gt64240_tx(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ unsigned long flags;
-+ int nextIn;
-+
-+ spin_lock_irqsave(&gp->lock, flags);
-+
-+ nextIn = gp->tx_next_in;
-+
-+ if (gt64240_debug > 3) {
-+ printk("%s: gt64240_tx: nextIn=%d.\n", dev->name, nextIn);
-+ }
-+
-+ if (gp->tx_count >= TX_RING_SIZE) {
-+ printk("%s: Tx Ring full, pkt dropped.\n", dev->name);
-+ gp->stats.tx_dropped++;
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+ return 1;
-+ }
-+
-+ if (!(gp->last_psr & psrLink)) {
-+ printk("%s: gt64240_tx: Link down, pkt dropped.\n",
-+ dev->name);
-+ gp->stats.tx_dropped++;
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+//--- dump_MII(dev); /* KLUDGE ALERT !!! */
-+ return 1;
-+ }
-+
-+ if (gp->tx_ring[nextIn].cmdstat & txOwn) {
-+ printk
-+ ("%s: gt64240_tx: device owns descriptor, pkt dropped.\n",
-+ dev->name);
-+ gp->stats.tx_dropped++;
-+ // stop the queue, so Tx timeout can fix it
-+ netif_stop_queue(dev);
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+ return 1;
-+ }
-+ // Prepare the Descriptor at tx_next_in
-+ gp->tx_skbuff[nextIn] = skb;
-+ gp->tx_ring[nextIn].byte_cnt = skb->len;
-+ gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data);
-+
-+ // make sure packet gets written back to memory
-+ dma_cache_wback_inv((unsigned long) (skb->data), skb->len);
-+ mb();
-+
-+ // Give ownership to device, set first and last desc, enable interrupt
-+ // Setting of ownership bit must be *last*!
-+ gp->tx_ring[nextIn].cmdstat =
-+ txOwn | txGenCRC | txEI | txPad | txFirst | txLast;
-+
-+ if (gt64240_debug > 5) {
-+ dump_tx_desc(dev, nextIn);
-+ }
-+ // increment tx_next_in with wrap
-+ gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
-+
-+//+prk20aug01:
-+ if (0) { /* ROLLINS */
-+ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
-+ virt_to_phys(&gp->tx_ring[nextIn]));
-+ }
-+
-+ if (gt64240_debug > 3) { /*+prk17aug01 */
-+ printk
-+ ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_CURR_TX_DESC_PTR0),
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
-+ }
-+ // If DMA is stopped, restart
-+ if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) {
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+ sdcmrERD | sdcmrTXDL);
-+ }
-+
-+ if (gt64240_debug > 3) { /*+prk17aug01 */
-+ printk
-+ ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
-+ dev->name, GT64240ETH_READ(gp,
-+ GT64240_ETH_CURR_TX_DESC_PTR0),
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
-+ }
-+ // increment count and stop queue if full
-+ if (++gp->tx_count >= TX_RING_SIZE) {
-+ gp->tx_full = 1;
-+ netif_stop_queue(dev);
-+ }
-+
-+ dev->trans_start = jiffies;
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+
-+ return 0;
-+}
-+
-+
-+static int
-+#ifdef GT64240_NAPI
-+gt64240_rx(struct net_device *dev, u32 status, int budget)
-+#else
-+gt64240_rx(struct net_device *dev, u32 status)
-+#endif
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ struct sk_buff *skb;
-+ int pkt_len, nextOut, cdp;
-+ gt64240_rd_t *rd;
-+ u32 cmdstat;
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_rx: dev=%p, status=%x\n",
-+ dev->name, dev, status);
-+
-+ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)
-+ - gp->rx_ring_dma) / sizeof(gt64240_rd_t);
-+
-+ // Continue until we reach the current descriptor pointer
-+ for (nextOut = gp->rx_next_out; nextOut != cdp;
-+ nextOut = (nextOut + 1) % RX_RING_SIZE) {
-+
-+#ifdef GT64240_NAPI
-+ if (budget <= 0)
-+ break;
-+
-+ budget--;
-+#endif
-+
-+ if (--gp->intr_work_done == 0)
-+ break;
-+
-+ if (gt64240_debug > 4)
-+ dump_rx_desc(dev, nextOut);
-+
-+ rd = &gp->rx_ring[nextOut];
-+ cmdstat = rd->cmdstat;
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: isr: Rx desc cmdstat=%x, nextOut=%d\n",
-+ dev->name, cmdstat, nextOut);
-+
-+ if (cmdstat & (u32) rxOwn) {
-+ if (gt64240_debug > 2)
-+ printk
-+ ("%s: gt64240_rx: device owns descriptor!\n",
-+ dev->name);
-+ // DMA is not finished updating descriptor???
-+ // Leave and come back later to pick-up where we left off.
-+ break;
-+ }
-+ // must be first and last (ie only) buffer of packet
-+ if (!(cmdstat & (u32) rxFirst)
-+ || !(cmdstat & (u32) rxLast)) {
-+ printk
-+ ("%s: gt64240_rx: desc not first and last!\n",
-+ dev->name);
-+ cmdstat |= (u32) rxOwn;
-+ rd->cmdstat = cmdstat;
-+ continue;
-+ }
-+ // Drop this received pkt if there were any errors
-+ if ((cmdstat & (u32) rxErrorSummary)
-+ || (status & icrRxError)) {
-+ // update the detailed rx error counters that are not covered
-+ // by the MIB counters.
-+ if (cmdstat & (u32) rxOverrun)
-+ gp->stats.rx_fifo_errors++;
-+ cmdstat |= (u32) rxOwn;
-+ rd->cmdstat = cmdstat;
-+ continue;
-+ }
-+
-+ pkt_len = rd->byte_cnt;
-+
-+ /* Create new skb. */
-+// skb = dev_alloc_skb(pkt_len+2);
-+ skb = dev_alloc_skb(1538);
-+ if (skb == NULL) {
-+ printk("%s: Memory squeeze, dropping packet.\n",
-+ dev->name);
-+ gp->stats.rx_dropped++;
-+ cmdstat |= (u32) rxOwn;
-+ rd->cmdstat = cmdstat;
-+ continue;
-+ }
-+ skb->dev = dev;
-+ skb_reserve(skb, 2); /* 16 byte IP header align */
-+ memcpy(skb_put(skb, pkt_len),
-+ &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len);
-+ skb->protocol = eth_type_trans(skb, dev);
-+
-+ /* NIC performed some checksum computation */
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef GT64240_NAPI
-+ netif_receive_skb(skb);
-+#else
-+ netif_rx(skb); /* pass the packet to upper layers */
-+#endif
-+
-+ // now we can release ownership of this desc back to device
-+ cmdstat |= (u32) rxOwn;
-+ rd->cmdstat = cmdstat;
-+
-+ dev->last_rx = jiffies;
-+ }
-+
-+ if (gt64240_debug > 3 && nextOut == gp->rx_next_out)
-+ printk("%s: gt64240_rx: RxCDP did not increment?\n",
-+ dev->name);
-+
-+ gp->rx_next_out = nextOut;
-+ return 0;
-+}
-+
-+
-+static void gt64240_tx_timeout(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&gp->lock, flags);
-+
-+
-+ if (!(gp->last_psr & psrLink)) {
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+ } else {
-+ printk("======------> gt64240_tx_timeout: %d jiffies \n",
-+ GT64240ETH_TX_TIMEOUT);
-+
-+ disable_ether_irq(dev);
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+ reset_tx(dev);
-+ enable_ether_irq(dev);
-+
-+ netif_wake_queue(dev);
-+ }
-+}
-+
-+
-+static void gt64240_set_rx_mode(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ unsigned long flags;
-+ struct dev_mc_list *mcptr;
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_set_rx_mode: dev=%p, flags=%x\n",
-+ dev->name, dev, dev->flags);
-+
-+ // stop the Receiver DMA
-+ abort(dev, sdcmrAR);
-+
-+ spin_lock_irqsave(&gp->lock, flags);
-+
-+ if (dev->flags & IFF_PROMISC)
-+ GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
-+ else
-+ GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
-+/*
-+ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
-+ (PORT_CONFIG | pcrPM | pcrEN));
-+*/
-+
-+ memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table
-+ // Add our ethernet address
-+ gt64240_add_hash_entry(dev, dev->dev_addr);
-+ if (dev->mc_count) {
-+ for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
-+ if (gt64240_debug > 2) {
-+ printk("%s: gt64240_set_rx_mode: addr=\n",
-+ dev->name);
-+ dump_hw_addr(mcptr->dmi_addr);
-+ }
-+ gt64240_add_hash_entry(dev, mcptr->dmi_addr);
-+ }
-+ }
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_set_rx: Port Config=%x\n", dev->name,
-+ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+
-+ // restart Rx DMA
-+ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+}
-+
-+static struct net_device_stats *gt64240_get_stats(struct net_device *dev)
-+{
-+ struct gt64240_private *gp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ if (gt64240_debug > 3)
-+ printk("%s: gt64240_get_stats: dev=%p\n", dev->name, dev);
-+
-+ if (netif_device_present(dev)) {
-+ spin_lock_irqsave(&gp->lock, flags);
-+ update_stats(gp);
-+ spin_unlock_irqrestore(&gp->lock, flags);
-+ }
-+
-+ return &gp->stats;
-+}
-diff -urpNX dontdiff linux-2.6.12/drivers/net/gt64240eth.h linux_HEAD/drivers/net/gt64240eth.h
---- linux-2.6.12/drivers/net/gt64240eth.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/gt64240eth.h 2005-02-17 21:49:49.000000000 +0100
-@@ -9,6 +9,7 @@
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * stevel at mvista.com or support at mvista.com
-+ * Copyright 2004, 05 Ralf Baechle (ralf at linux-mips.org)
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -31,6 +32,7 @@
- #ifndef _GT64240ETH_H
- #define _GT64240ETH_H
-
-+#include <linux/config.h>
- #include <asm/gt64240.h>
-
- #define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
-@@ -108,10 +110,10 @@
- #define REV_GT64240A 0x10
-
- #define GT64240ETH_READ(gp, offset) \
-- GT_READ((gp)->port_offset + (offset))
-+ MV_READ((gp)->port_offset + (offset))
-
- #define GT64240ETH_WRITE(gp, offset, data) \
-- GT_WRITE((gp)->port_offset + (offset), (data))
-+ MV_WRITE((gp)->port_offset + (offset), (data))
-
- #define GT64240ETH_SETBIT(gp, offset, bits) \
- GT64240ETH_WRITE((gp), (offset), \
-@@ -121,8 +123,8 @@
- GT64240ETH_WRITE((gp), (offset), \
- GT64240ETH_READ((gp), (offset)) & ~(bits))
-
--#define GT64240_READ(ofs) GT_READ(ofs)
--#define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data))
-+#define GT64240_READ(ofs) MV_READ(ofs)
-+#define GT64240_WRITE(ofs, data) MV_WRITE((ofs), (data))
-
- /* Bit definitions of the SMI Reg */
- enum {
-diff -urpNX dontdiff linux-2.6.12/drivers/net/ioc3-eth.c linux_HEAD/drivers/net/ioc3-eth.c
---- linux-2.6.12/drivers/net/ioc3-eth.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/ioc3-eth.c 2005-07-10 12:16:38.000000000 +0200
-@@ -499,7 +499,7 @@ static int ioc3_mdio_read(struct net_dev
- ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
- while (ioc3_r_micr() & MICR_BUSY);
-
-- return ioc3_r_micr() & MIDR_DATA_MASK;
-+ return ioc3_r_midr_r() & MIDR_DATA_MASK;
- }
-
- static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
-@@ -1291,7 +1291,6 @@ static int ioc3_probe(struct pci_dev *pd
- dev->features = NETIF_F_IP_CSUM;
- #endif
-
-- ioc3_setup_duplex(ip);
- sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
- sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
-
-@@ -1300,6 +1299,7 @@ static int ioc3_probe(struct pci_dev *pd
- goto out_stop;
-
- mii_check_media(&ip->mii, 1, 1);
-+ ioc3_setup_duplex(ip);
-
- vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
- model = (sw_physid2 >> 4) & 0x3f;
-diff -urpNX dontdiff linux-2.6.12/drivers/net/saa9730.c linux_HEAD/drivers/net/saa9730.c
---- linux-2.6.12/drivers/net/saa9730.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/saa9730.c 2005-02-17 21:49:50.000000000 +0100
-@@ -1,8 +1,7 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
-- *
-- * ########################################################################
-+ * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
-@@ -17,15 +16,13 @@
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
-- * ########################################################################
-- *
- * SAA9730 ethernet driver.
- *
- * Changes:
-- * Angelo Dell'Aera <buffer at antifork.org> : Conversion to the new PCI API (pci_driver).
-- * Conversion to spinlocks.
-- * Error handling fixes.
-- *
-+ * Angelo Dell'Aera <buffer at antifork.org> : Conversion to the new PCI API
-+ * (pci_driver).
-+ * Conversion to spinlocks.
-+ * Error handling fixes.
- */
-
- #include <linux/init.h>
-@@ -36,8 +33,11 @@
- #include <linux/skbuff.h>
- #include <linux/pci.h>
- #include <linux/spinlock.h>
-+#include <linux/types.h>
-
- #include <asm/addrspace.h>
-+#include <asm/io.h>
-+
- #include <asm/mips-boards/prom.h>
-
- #include "saa9730.h"
-@@ -51,8 +51,8 @@ int lan_saa9730_debug;
- #define DRV_MODULE_NAME "saa9730"
-
- static struct pci_device_id saa9730_pci_tbl[] = {
-- { PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9370,
-- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-+ { PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
-+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
- { 0, }
- };
-
-@@ -61,8 +61,8 @@ MODULE_DEVICE_TABLE(pci, saa9730_pci_tbl
- /* Non-zero only if the current card is a PCI with BIOS-set IRQ. */
- static unsigned int pci_irq_line;
-
--#define INL(a) inl((unsigned long)a)
--#define OUTL(x,a) outl(x,(unsigned long)a)
-+#define INL(a) readl(a)
-+#define OUTL(x, a) writel(x, a)
-
- static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp)
- {
-@@ -98,13 +98,13 @@ static void evm_saa9730_unblock_lan_int(
- &lp->evm_saa9730_regs->InterruptBlock1);
- }
-
--static void show_saa9730_regs(struct lan_saa9730_private *lp)
-+static void __attribute_used__ show_saa9730_regs(struct lan_saa9730_private *lp)
- {
- int i, j;
-- printk("TxmBufferA = %x\n", lp->TxmBuffer[0][0]);
-- printk("TxmBufferB = %x\n", lp->TxmBuffer[1][0]);
-- printk("RcvBufferA = %x\n", lp->RcvBuffer[0][0]);
-- printk("RcvBufferB = %x\n", lp->RcvBuffer[1][0]);
-+ printk("TxmBufferA = %p\n", lp->TxmBuffer[0][0]);
-+ printk("TxmBufferB = %p\n", lp->TxmBuffer[1][0]);
-+ printk("RcvBufferA = %p\n", lp->RcvBuffer[0][0]);
-+ printk("RcvBufferB = %p\n", lp->RcvBuffer[1][0]);
- for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
- for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) {
- printk("TxmBuffer[%d][%d] = %x\n", i, j,
-@@ -214,88 +214,95 @@ static void lan_saa9730_buffer_init(stru
- }
- }
-
--static int lan_saa9730_allocate_buffers(struct lan_saa9730_private *lp)
-+static void lan_saa9730_free_buffers(struct pci_dev *pdev,
-+ struct lan_saa9730_private *lp)
- {
-- unsigned int mem_size;
-- void *Pa;
-- unsigned int i, j, RcvBufferSize, TxmBufferSize;
-- unsigned int buffer_start;
-+ pci_free_consistent(pdev, lp->buffer_size, lp->buffer_start,
-+ lp->dma_addr);
-+}
-
-- /*
-- * Allocate all RX and TX packets in one chunk.
-- * The Rx and Tx packets must be PACKET_SIZE aligned.
-- */
-- mem_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) *
-- LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) +
-- LAN_SAA9730_PACKET_SIZE;
-- buffer_start =
-- (unsigned int) kmalloc(mem_size, GFP_DMA | GFP_KERNEL);
--
-- if (!buffer_start)
-- return -ENOMEM;
--
-- /*
-- * Set DMA buffer to kseg1 (uncached).
-- * Make sure to flush before using it uncached.
-- */
-- Pa = (void *) KSEG1ADDR((buffer_start + LAN_SAA9730_PACKET_SIZE) &
-- ~(LAN_SAA9730_PACKET_SIZE - 1));
-- dma_cache_wback_inv((unsigned long) Pa, mem_size);
-+static int lan_saa9730_allocate_buffers(struct pci_dev *pdev,
-+ struct lan_saa9730_private *lp)
-+{
-+ void *Pa;
-+ unsigned int i, j, rxoffset, txoffset;
-+ int ret;
-
- /* Initialize buffer space */
-- RcvBufferSize = LAN_SAA9730_PACKET_SIZE;
-- TxmBufferSize = LAN_SAA9730_PACKET_SIZE;
- lp->DmaRcvPackets = LAN_SAA9730_RCV_Q_SIZE;
- lp->DmaTxmPackets = LAN_SAA9730_TXM_Q_SIZE;
-
-+ /* Initialize Rx Buffer Index */
-+ lp->NextRcvPacketIndex = 0;
-+ lp->NextRcvBufferIndex = 0;
-+
-+ /* Set current buffer index & next available packet index */
-+ lp->NextTxmPacketIndex = 0;
-+ lp->NextTxmBufferIndex = 0;
-+ lp->PendingTxmPacketIndex = 0;
-+ lp->PendingTxmBufferIndex = 0;
-+
-+ /*
-+ * Allocate all RX and TX packets in one chunk.
-+ * The Rx and Tx packets must be PACKET_SIZE aligned.
-+ */
-+ lp->buffer_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) *
-+ LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) +
-+ LAN_SAA9730_PACKET_SIZE;
-+ lp->buffer_start = pci_alloc_consistent(pdev, lp->buffer_size,
-+ &lp->dma_addr);
-+ if (!lp->buffer_start) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ Pa = (void *)ALIGN((unsigned long)lp->buffer_start,
-+ LAN_SAA9730_PACKET_SIZE);
-+
-+ rxoffset = Pa - lp->buffer_start;
-+
- /* Init RX buffers */
- for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
- for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) {
- *(unsigned int *) Pa =
- cpu_to_le32(RXSF_READY <<
- RX_STAT_CTL_OWNER_SHF);
-- lp->RcvBuffer[i][j] = (unsigned int) Pa;
-- Pa += RcvBufferSize;
-+ lp->RcvBuffer[i][j] = Pa;
-+ Pa += LAN_SAA9730_PACKET_SIZE;
- }
- }
-
-+ txoffset = Pa - lp->buffer_start;
-+
- /* Init TX buffers */
- for (i = 0; i < LAN_SAA9730_BUFFERS; i++) {
- for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) {
- *(unsigned int *) Pa =
- cpu_to_le32(TXSF_EMPTY <<
- TX_STAT_CTL_OWNER_SHF);
-- lp->TxmBuffer[i][j] = (unsigned int) Pa;
-- Pa += TxmBufferSize;
-+ lp->TxmBuffer[i][j] = Pa;
-+ Pa += LAN_SAA9730_PACKET_SIZE;
- }
- }
-
-- /*
-- * Set rx buffer A and rx buffer B to point to the first two buffer
-+ /*
-+ * Set rx buffer A and rx buffer B to point to the first two buffer
- * spaces.
- */
-- OUTL(PHYSADDR(lp->RcvBuffer[0][0]),
-+ OUTL(lp->dma_addr + rxoffset,
- &lp->lan_saa9730_regs->RxBuffA);
-- OUTL(PHYSADDR(lp->RcvBuffer[1][0]),
-+ OUTL(lp->dma_addr + rxoffset +
-+ LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_RCV_Q_SIZE,
- &lp->lan_saa9730_regs->RxBuffB);
-
-- /* Initialize Buffer Index */
-- lp->NextRcvPacketIndex = 0;
-- lp->NextRcvToUseIsA = 1;
--
-- /* Set current buffer index & next availble packet index */
-- lp->NextTxmPacketIndex = 0;
-- lp->NextTxmBufferIndex = 0;
-- lp->PendingTxmPacketIndex = 0;
-- lp->PendingTxmBufferIndex = 0;
--
-- /*
-+ /*
- * Set txm_buf_a and txm_buf_b to point to the first two buffer
-- * space
-+ * space
- */
-- OUTL(PHYSADDR(lp->TxmBuffer[0][0]),
-+ OUTL(lp->dma_addr + txoffset,
- &lp->lan_saa9730_regs->TxBuffA);
-- OUTL(PHYSADDR(lp->TxmBuffer[1][0]),
-+ OUTL(lp->dma_addr + txoffset +
-+ LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_TXM_Q_SIZE,
- &lp->lan_saa9730_regs->TxBuffB);
-
- /* Set packet number */
-@@ -306,6 +313,9 @@ static int lan_saa9730_allocate_buffers(
- &lp->lan_saa9730_regs->PacketCount);
-
- return 0;
-+
-+out:
-+ return ret;
- }
-
- static int lan_saa9730_cam_load(struct lan_saa9730_private *lp)
-@@ -328,8 +338,7 @@ static int lan_saa9730_cam_load(struct l
-
- static int lan_saa9730_cam_init(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
- unsigned int i;
-
- /* Copy MAC-address into all entries. */
-@@ -469,9 +478,9 @@ static int lan_saa9730_control_init(stru
- OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC,
- &lp->lan_saa9730_regs->CamCtl);
-
-- /*
-+ /*
- * Initialize CAM enable register, only turn on first entry, should
-- * contain own addr.
-+ * contain own addr.
- */
- OUTL(0x0001, &lp->lan_saa9730_regs->CamEnable);
-
-@@ -501,7 +510,7 @@ static int lan_saa9730_stop(struct lan_s
- OUTL(INL(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET,
- &lp->lan_saa9730_regs->MacCtl);
-
-- /*
-+ /*
- * Wait for MAC reset to have finished. The reset bit is auto cleared
- * when the reset is done.
- */
-@@ -536,9 +545,9 @@ static int lan_saa9730_start(struct lan_
-
- /* Initialize Rx Buffer Index */
- lp->NextRcvPacketIndex = 0;
-- lp->NextRcvToUseIsA = 1;
-+ lp->NextRcvBufferIndex = 0;
-
-- /* Set current buffer index & next availble packet index */
-+ /* Set current buffer index & next available packet index */
- lp->NextTxmPacketIndex = 0;
- lp->NextTxmBufferIndex = 0;
- lp->PendingTxmPacketIndex = 0;
-@@ -555,9 +564,8 @@ static int lan_saa9730_start(struct lan_
- OUTL(INL(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN,
- &lp->lan_saa9730_regs->RxCtl);
-
-- /* Set Ok2Use to let hardware owns the buffers */
-- OUTL(OK2USE_RX_A | OK2USE_RX_B | OK2USE_TX_A | OK2USE_TX_B,
-- &lp->lan_saa9730_regs->Ok2Use);
-+ /* Set Ok2Use to let hardware own the buffers. */
-+ OUTL(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use);
-
- return 0;
- }
-@@ -572,8 +580,7 @@ static int lan_saa9730_restart(struct la
-
- static int lan_saa9730_tx(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
- unsigned int *pPacket;
- unsigned int tx_status;
-
-@@ -584,10 +591,8 @@ static int lan_saa9730_tx(struct net_dev
- OUTL(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus);
-
- while (1) {
-- pPacket =
-- (unsigned int *) lp->TxmBuffer[lp->
-- PendingTxmBufferIndex]
-- [lp->PendingTxmPacketIndex];
-+ pPacket = lp->TxmBuffer[lp->PendingTxmBufferIndex]
-+ [lp->PendingTxmPacketIndex];
-
- /* Get status of first packet transmitted. */
- tx_status = le32_to_cpu(*pPacket);
-@@ -605,23 +610,22 @@ static int lan_saa9730_tx(struct net_dev
- lp->stats.tx_errors++;
- if (tx_status &
- (TX_STATUS_EX_COLL << TX_STAT_CTL_STATUS_SHF))
-- lp->stats.tx_aborted_errors++;
-+ lp->stats.tx_aborted_errors++;
- if (tx_status &
-- (TX_STATUS_LATE_COLL <<
-- TX_STAT_CTL_STATUS_SHF)) lp->stats.
-- tx_window_errors++;
-+ (TX_STATUS_LATE_COLL << TX_STAT_CTL_STATUS_SHF))
-+ lp->stats.tx_window_errors++;
- if (tx_status &
- (TX_STATUS_L_CARR << TX_STAT_CTL_STATUS_SHF))
-- lp->stats.tx_carrier_errors++;
-+ lp->stats.tx_carrier_errors++;
- if (tx_status &
- (TX_STATUS_UNDER << TX_STAT_CTL_STATUS_SHF))
-- lp->stats.tx_fifo_errors++;
-+ lp->stats.tx_fifo_errors++;
- if (tx_status &
- (TX_STATUS_SQ_ERR << TX_STAT_CTL_STATUS_SHF))
-- lp->stats.tx_heartbeat_errors++;
-+ lp->stats.tx_heartbeat_errors++;
-
- lp->stats.collisions +=
-- tx_status & TX_STATUS_TX_COLL_MSK;
-+ tx_status & TX_STATUS_TX_COLL_MSK;
- }
-
- /* Free buffer. */
-@@ -636,21 +640,15 @@ static int lan_saa9730_tx(struct net_dev
- }
- }
-
-- /* Make sure A and B are available to hardware. */
-- OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use);
--
-- if (netif_queue_stopped(dev)) {
-- /* The tx buffer is no longer full. */
-- netif_wake_queue(dev);
-- }
-+ /* The tx buffer is no longer full. */
-+ netif_wake_queue(dev);
-
- return 0;
- }
-
- static int lan_saa9730_rx(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
- int len = 0;
- struct sk_buff *skb = 0;
- unsigned int rx_status;
-@@ -667,12 +665,9 @@ static int lan_saa9730_rx(struct net_dev
- DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus);
-
- /* Address next packet */
-- if (lp->NextRcvToUseIsA)
-- BufferIndex = 0;
-- else
-- BufferIndex = 1;
-+ BufferIndex = lp->NextRcvBufferIndex;
- PacketIndex = lp->NextRcvPacketIndex;
-- pPacket = (unsigned int *) lp->RcvBuffer[BufferIndex][PacketIndex];
-+ pPacket = lp->RcvBuffer[BufferIndex][PacketIndex];
- rx_status = le32_to_cpu(*pPacket);
-
- /* Process each packet. */
-@@ -715,51 +710,39 @@ static int lan_saa9730_rx(struct net_dev
- lp->stats.rx_errors++;
- if (rx_status &
- (RX_STATUS_CRC_ERR << RX_STAT_CTL_STATUS_SHF))
-- lp->stats.rx_crc_errors++;
-+ lp->stats.rx_crc_errors++;
- if (rx_status &
-- (RX_STATUS_ALIGN_ERR <<
-- RX_STAT_CTL_STATUS_SHF)) lp->stats.
-- rx_frame_errors++;
-+ (RX_STATUS_ALIGN_ERR << RX_STAT_CTL_STATUS_SHF))
-+ lp->stats.rx_frame_errors++;
- if (rx_status &
- (RX_STATUS_OVERFLOW << RX_STAT_CTL_STATUS_SHF))
-- lp->stats.rx_fifo_errors++;
-+ lp->stats.rx_fifo_errors++;
- if (rx_status &
- (RX_STATUS_LONG_ERR << RX_STAT_CTL_STATUS_SHF))
-- lp->stats.rx_length_errors++;
-+ lp->stats.rx_length_errors++;
- }
-
- /* Indicate we have processed the buffer. */
-- *pPacket =
-- cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF);
-+ *pPacket = cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF);
-+
-+ /* Make sure A or B is available to hardware as appropriate. */
-+ OUTL(BufferIndex ? OK2USE_RX_B : OK2USE_RX_A,
-+ &lp->lan_saa9730_regs->Ok2Use);
-
- /* Go to next packet in sequence. */
- lp->NextRcvPacketIndex++;
- if (lp->NextRcvPacketIndex >= LAN_SAA9730_RCV_Q_SIZE) {
- lp->NextRcvPacketIndex = 0;
-- if (BufferIndex) {
-- lp->NextRcvToUseIsA = 1;
-- } else {
-- lp->NextRcvToUseIsA = 0;
-- }
-+ lp->NextRcvBufferIndex ^= 1;
- }
-- OUTL(OK2USE_RX_A | OK2USE_RX_B,
-- &lp->lan_saa9730_regs->Ok2Use);
-
- /* Address next packet */
-- if (lp->NextRcvToUseIsA)
-- BufferIndex = 0;
-- else
-- BufferIndex = 1;
-+ BufferIndex = lp->NextRcvBufferIndex;
- PacketIndex = lp->NextRcvPacketIndex;
-- pPacket =
-- (unsigned int *) lp->
-- RcvBuffer[BufferIndex][PacketIndex];
-+ pPacket = lp->RcvBuffer[BufferIndex][PacketIndex];
- rx_status = le32_to_cpu(*pPacket);
- }
-
-- /* Make sure A and B are available to hardware. */
-- OUTL(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use);
--
- return 0;
- }
-
-@@ -767,8 +750,7 @@ static irqreturn_t lan_saa9730_interrupt
- struct pt_regs *regs)
- {
- struct net_device *dev = (struct net_device *) dev_id;
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- if (lan_saa9730_debug > 5)
- printk("lan_saa9730_interrupt\n");
-@@ -794,15 +776,9 @@ static irqreturn_t lan_saa9730_interrupt
- return IRQ_HANDLED;
- }
-
--static int lan_saa9730_open_fail(struct net_device *dev)
--{
-- return -ENODEV;
--}
--
- static int lan_saa9730_open(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- /* Associate IRQ with lan_saa9730_interrupt */
- if (request_irq(dev->irq, &lan_saa9730_interrupt, 0, "SAA9730 Eth",
-@@ -834,15 +810,13 @@ static int lan_saa9730_write(struct lan_
- int PacketIndex;
-
- if (lan_saa9730_debug > 5)
-- printk("lan_saa9730_write: skb=%08x\n",
-- (unsigned int) skb);
-+ printk("lan_saa9730_write: skb=%p\n", skb);
-
- BufferIndex = lp->NextTxmBufferIndex;
- PacketIndex = lp->NextTxmPacketIndex;
-
-- tx_status =
-- le32_to_cpu(*(unsigned int *) lp->
-- TxmBuffer[BufferIndex][PacketIndex]);
-+ tx_status = le32_to_cpu(*(unsigned int *)lp->TxmBuffer[BufferIndex]
-+ [PacketIndex]);
- if ((tx_status & TX_STAT_CTL_OWNER_MSK) !=
- (TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF)) {
- if (lan_saa9730_debug > 4)
-@@ -858,29 +832,29 @@ static int lan_saa9730_write(struct lan_
- lp->NextTxmBufferIndex ^= 1;
- }
-
-- pbPacketData =
-- (unsigned char *) lp->TxmBuffer[BufferIndex][PacketIndex];
-+ pbPacketData = lp->TxmBuffer[BufferIndex][PacketIndex];
- pbPacketData += 4;
-
- /* copy the bits */
- memcpy(pbPacketData, pbData, len);
-
- /* Set transmit status for hardware */
-- *(unsigned int *) lp->TxmBuffer[BufferIndex][PacketIndex] =
-- cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) |
-- (TX_STAT_CTL_INT_AFTER_TX << TX_STAT_CTL_FRAME_SHF)
-- | (len << TX_STAT_CTL_LENGTH_SHF));
-+ *(unsigned int *)lp->TxmBuffer[BufferIndex][PacketIndex] =
-+ cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) |
-+ (TX_STAT_CTL_INT_AFTER_TX <<
-+ TX_STAT_CTL_FRAME_SHF) |
-+ (len << TX_STAT_CTL_LENGTH_SHF));
-
-- /* Set hardware tx buffer. */
-- OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use);
-+ /* Make sure A or B is available to hardware as appropriate. */
-+ OUTL(BufferIndex ? OK2USE_TX_B : OK2USE_TX_A,
-+ &lp->lan_saa9730_regs->Ok2Use);
-
- return 0;
- }
-
- static void lan_saa9730_tx_timeout(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- /* Transmitter timeout, serious problems */
- lp->stats.tx_errors++;
-@@ -889,20 +863,19 @@ static void lan_saa9730_tx_timeout(struc
- lan_saa9730_restart(lp);
-
- dev->trans_start = jiffies;
-- netif_start_queue(dev);
-+ netif_wake_queue(dev);
- }
-
- static int lan_saa9730_start_xmit(struct sk_buff *skb,
- struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
- unsigned long flags;
- int skblen;
- int len;
-
- if (lan_saa9730_debug > 4)
-- printk("Send packet: skb=%08x\n", (unsigned int) skb);
-+ printk("Send packet: skb=%p\n", skb);
-
- skblen = skb->len;
-
-@@ -912,8 +885,7 @@ static int lan_saa9730_start_xmit(struct
-
- if (lan_saa9730_write(lp, skb, skblen)) {
- spin_unlock_irqrestore(&lp->lock, flags);
-- printk("Error when writing packet to controller: skb=%08x\n",
-- (unsigned int) skb);
-+ printk("Error when writing packet to controller: skb=%p\n", skb);
- netif_stop_queue(dev);
- return -1;
- }
-@@ -922,7 +894,7 @@ static int lan_saa9730_start_xmit(struct
- lp->stats.tx_packets++;
-
- dev->trans_start = jiffies;
-- netif_start_queue(dev);
-+ netif_wake_queue(dev);
- dev_kfree_skb(skb);
-
- spin_unlock_irqrestore(&lp->lock, flags);
-@@ -932,8 +904,7 @@ static int lan_saa9730_start_xmit(struct
-
- static int lan_saa9730_close(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- if (lan_saa9730_debug > 1)
- printk("lan_saa9730_close:\n");
-@@ -955,16 +926,14 @@ static int lan_saa9730_close(struct net_
- static struct net_device_stats *lan_saa9730_get_stats(struct net_device
- *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- return &lp->stats;
- }
-
- static void lan_saa9730_set_multicast(struct net_device *dev)
- {
-- struct lan_saa9730_private *lp =
-- (struct lan_saa9730_private *) dev->priv;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
- /* Stop the controller */
- lan_saa9730_stop(lp);
-@@ -981,7 +950,7 @@ static void lan_saa9730_set_multicast(st
- CAM_CONTROL_BROAD_ACC,
- &lp->lan_saa9730_regs->CamCtl);
- } else {
-- /*
-+ /*
- * Will handle the multicast stuff later. -carstenl
- */
- }
-@@ -993,94 +962,86 @@ static void lan_saa9730_set_multicast(st
-
- static void __devexit saa9730_remove_one(struct pci_dev *pdev)
- {
-- struct net_device *dev = pci_get_drvdata(pdev);
--
-- if (dev) {
-- unregister_netdev(dev);
--
-- if (dev->priv)
-- kfree(dev->priv);
-+ struct net_device *dev = pci_get_drvdata(pdev);
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
-
-- free_netdev(dev);
-- pci_release_regions(pdev);
-- pci_disable_device(pdev);
-- pci_set_drvdata(pdev, NULL);
-- }
-+ if (dev) {
-+ unregister_netdev(dev);
-+ lan_saa9730_free_buffers(pdev, lp);
-+ iounmap(lp->lan_saa9730_regs);
-+ iounmap(lp->evm_saa9730_regs);
-+ free_netdev(dev);
-+ pci_release_regions(pdev);
-+ pci_disable_device(pdev);
-+ pci_set_drvdata(pdev, NULL);
-+ }
- }
-
-
--static int lan_saa9730_init(struct net_device *dev, int ioaddr, int irq)
-+static int lan_saa9730_init(struct net_device *dev, struct pci_dev *pdev,
-+ unsigned long ioaddr, int irq)
- {
-- struct lan_saa9730_private *lp;
-+ struct lan_saa9730_private *lp = netdev_priv(dev);
- unsigned char ethernet_addr[6];
-- int ret = 0;
-+ int ret;
-
-- dev->open = lan_saa9730_open_fail;
-+ if (get_ethernet_addr(ethernet_addr)) {
-+ ret = -ENODEV;
-+ goto out;
-+ }
-
-- if (get_ethernet_addr(ethernet_addr))
-- return -ENODEV;
--
- memcpy(dev->dev_addr, ethernet_addr, 6);
- dev->base_addr = ioaddr;
- dev->irq = irq;
--
-- /*
-- * Make certain the data structures used by the controller are aligned
-- * and DMAble.
-- */
-- /*
-- * XXX: that is obviously broken - kfree() won't be happy with us.
-- */
-- lp = (struct lan_saa9730_private *) (((unsigned long)
-- kmalloc(sizeof(*lp) + 7,
-- GFP_DMA | GFP_KERNEL)
-- + 7) & ~7);
-
-- if (!lp)
-- return -ENOMEM;
--
-- dev->priv = lp;
-- memset(lp, 0, sizeof(*lp));
-+ lp->pci_dev = pdev;
-
- /* Set SAA9730 LAN base address. */
-- lp->lan_saa9730_regs = (t_lan_saa9730_regmap *) (ioaddr +
-- SAA9730_LAN_REGS_ADDR);
-+ lp->lan_saa9730_regs = ioremap(ioaddr + SAA9730_LAN_REGS_ADDR,
-+ SAA9730_LAN_REGS_SIZE);
-+ if (!lp->lan_saa9730_regs) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-
- /* Set SAA9730 EVM base address. */
-- lp->evm_saa9730_regs = (t_evm_saa9730_regmap *) (ioaddr +
-- SAA9730_EVM_REGS_ADDR);
-+ lp->evm_saa9730_regs = ioremap(ioaddr + SAA9730_EVM_REGS_ADDR,
-+ SAA9730_EVM_REGS_SIZE);
-+ if (!lp->evm_saa9730_regs) {
-+ ret = -ENOMEM;
-+ goto out_iounmap_lan;
-+ }
-
- /* Allocate LAN RX/TX frame buffer space. */
-- /* FIXME: a leak */
-- if ((ret = lan_saa9730_allocate_buffers(lp)))
-- goto out;
-+ if ((ret = lan_saa9730_allocate_buffers(pdev, lp)))
-+ goto out_iounmap;
-
- /* Stop LAN controller. */
-- if ((ret = lan_saa9730_stop(lp)))
-- goto out;
--
-+ if ((ret = lan_saa9730_stop(lp)))
-+ goto out_free_consistent;
-+
- /* Initialize CAM registers. */
- if ((ret = lan_saa9730_cam_init(dev)))
-- goto out;
-+ goto out_free_consistent;
-
- /* Initialize MII registers. */
- if ((ret = lan_saa9730_mii_init(lp)))
-- goto out;
-+ goto out_free_consistent;
-
- /* Initialize control registers. */
-- if ((ret = lan_saa9730_control_init(lp)))
-- goto out;
--
-+ if ((ret = lan_saa9730_control_init(lp)))
-+ goto out_free_consistent;
-+
- /* Load CAM registers. */
-- if ((ret = lan_saa9730_cam_load(lp)))
-- goto out;
--
-+ if ((ret = lan_saa9730_cam_load(lp)))
-+ goto out_free_consistent;
-+
- /* Initialize DMA context registers. */
- if ((ret = lan_saa9730_dma_init(lp)))
-- goto out;
--
-+ goto out_free_consistent;
-+
- spin_lock_init(&lp->lock);
--
-+
- dev->open = lan_saa9730_open;
- dev->hard_start_xmit = lan_saa9730_start_xmit;
- dev->stop = lan_saa9730_close;
-@@ -1089,45 +1050,43 @@ static int lan_saa9730_init(struct net_d
- dev->tx_timeout = lan_saa9730_tx_timeout;
- dev->watchdog_timeo = (HZ >> 1);
- dev->dma = 0;
--
-- ret = register_netdev(dev);
-+
-+ ret = register_netdev (dev);
- if (ret)
-- goto out;
-+ goto out_free_consistent;
-+
- return 0;
-
-- out:
-- if (dev->priv)
-- kfree(dev->priv);
-+out_free_consistent:
-+ lan_saa9730_free_buffers(pdev, lp);
-+out_iounmap:
-+ iounmap(lp->evm_saa9730_regs);
-+out_iounmap_lan:
-+ iounmap(lp->lan_saa9730_regs);
-+out:
- return ret;
- }
-
-
- static int __devinit saa9730_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
- {
-- struct net_device *dev;
-- unsigned int pci_ioaddr;
-+ struct net_device *dev = NULL;
-+ unsigned long pci_ioaddr;
- int err;
-
- if (lan_saa9730_debug > 1)
- printk("saa9730.c: PCI bios is present, checking for devices...\n");
-
-- err = -ENOMEM;
-- dev = alloc_etherdev(0);
-- if (!dev)
-- goto out;
--
-- SET_MODULE_OWNER(dev);
--
- err = pci_enable_device(pdev);
-- if (err) {
-- printk(KERN_ERR "Cannot enable PCI device, aborting.\n");
-- goto out1;
-- }
-+ if (err) {
-+ printk(KERN_ERR "Cannot enable PCI device, aborting.\n");
-+ goto out;
-+ }
-
- err = pci_request_regions(pdev, DRV_MODULE_NAME);
- if (err) {
- printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
-- goto out2;
-+ goto out_disable_pdev;
- }
-
- pci_irq_line = pdev->irq;
-@@ -1136,49 +1095,52 @@ static int __devinit saa9730_init_one(st
- pci_ioaddr = pci_resource_start(pdev, 1);
- pci_set_master(pdev);
-
-- printk("Found SAA9730 (PCI) at %#x, irq %d.\n",
-+ printk("Found SAA9730 (PCI) at %lx, irq %d.\n",
- pci_ioaddr, pci_irq_line);
-
-- err = lan_saa9730_init(dev, pci_ioaddr, pci_irq_line);
-+ dev = alloc_etherdev(sizeof(struct lan_saa9730_private));
-+ if (!dev)
-+ goto out_disable_pdev;
-+
-+ err = lan_saa9730_init(dev, pdev, pci_ioaddr, pci_irq_line);
- if (err) {
-- printk("Lan init failed");
-- goto out2;
-+ printk("LAN init failed");
-+ goto out_free_netdev;
- }
-
- pci_set_drvdata(pdev, dev);
- SET_NETDEV_DEV(dev, &pdev->dev);
- return 0;
--
--out2:
-- pci_disable_device(pdev);
--out1:
-+
-+out_free_netdev:
- free_netdev(dev);
-+out_disable_pdev:
-+ pci_disable_device(pdev);
- out:
-+ pci_set_drvdata(pdev, NULL);
- return err;
- }
-
-
- static struct pci_driver saa9730_driver = {
-- .name = DRV_MODULE_NAME,
-- .id_table = saa9730_pci_tbl,
-- .probe = saa9730_init_one,
-- .remove = __devexit_p(saa9730_remove_one),
-+ .name = DRV_MODULE_NAME,
-+ .id_table = saa9730_pci_tbl,
-+ .probe = saa9730_init_one,
-+ .remove = __devexit_p(saa9730_remove_one),
- };
-
-
- static int __init saa9730_init(void)
- {
-- return pci_module_init(&saa9730_driver);
-+ return pci_module_init(&saa9730_driver);
- }
-
- static void __exit saa9730_cleanup(void)
- {
-- pci_unregister_driver(&saa9730_driver);
-+ pci_unregister_driver(&saa9730_driver);
- }
-
- module_init(saa9730_init);
- module_exit(saa9730_cleanup);
-
--
--
- MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/net/saa9730.h linux_HEAD/drivers/net/saa9730.h
---- linux-2.6.12/drivers/net/saa9730.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/saa9730.h 2005-02-17 21:49:50.000000000 +0100
-@@ -1,6 +1,7 @@
- /*
-- * Carsten Langgaard, carstenl at mips.com
-- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
-+ * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
-+ * Authors: Carsten Langgaard <carstenl at mips.com>
-+ * Maciej W. Rozycki <macro at mips.com>
- *
- * ########################################################################
- *
-@@ -265,6 +266,7 @@
-
- /* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
- #define SAA9730_LAN_REGS_ADDR 0x20400
-+#define SAA9730_LAN_REGS_SIZE 0x00400
-
- struct lan_saa9730_regmap {
- volatile unsigned int TxBuffA; /* 0x20400 */
-@@ -309,6 +311,7 @@ typedef volatile struct lan_saa9730_regm
-
- /* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
- #define SAA9730_EVM_REGS_ADDR 0x02000
-+#define SAA9730_EVM_REGS_SIZE 0x00400
-
- struct evm_saa9730_regmap {
- volatile unsigned int InterruptStatus1; /* 0x2000 */
-@@ -329,16 +332,32 @@ typedef volatile struct evm_saa9730_regm
-
-
- struct lan_saa9730_private {
-+ /*
-+ * Rx/Tx packet buffers.
-+ * The Rx and Tx packets must be PACKET_SIZE aligned.
-+ */
-+ void *buffer_start;
-+ unsigned int buffer_size;
-+
-+ /*
-+ * DMA address of beginning of this object, returned
-+ * by pci_alloc_consistent().
-+ */
-+ dma_addr_t dma_addr;
-+
-+ /* Pointer to the associated pci device structure */
-+ struct pci_dev *pci_dev;
-+
- /* Pointer for the SAA9730 LAN controller register set. */
- t_lan_saa9730_regmap *lan_saa9730_regs;
-
- /* Pointer to the SAA9730 EVM register. */
- t_evm_saa9730_regmap *evm_saa9730_regs;
-
-- /* TRUE if the next buffer to write is RxBuffA, FALSE if RxBuffB. */
-- unsigned char NextRcvToUseIsA;
- /* Rcv buffer Index. */
- unsigned char NextRcvPacketIndex;
-+ /* Next buffer index. */
-+ unsigned char NextRcvBufferIndex;
-
- /* Index of next packet to use in that buffer. */
- unsigned char NextTxmPacketIndex;
-@@ -353,13 +372,8 @@ struct lan_saa9730_private {
- unsigned char DmaRcvPackets;
- unsigned char DmaTxmPackets;
-
-- unsigned char RcvAIndex; /* index into RcvBufferSpace[] for Blk A */
-- unsigned char RcvBIndex; /* index into RcvBufferSpace[] for Blk B */
--
-- unsigned int
-- TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
-- unsigned int
-- RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
-+ void *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
-+ void *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
- unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];
-
- unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];
-diff -urpNX dontdiff linux-2.6.12/drivers/net/sb1250-mac.c linux_HEAD/drivers/net/sb1250-mac.c
---- linux-2.6.12/drivers/net/sb1250-mac.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/sb1250-mac.c 2005-03-21 20:04:26.000000000 +0100
-@@ -2419,6 +2419,11 @@ static int sbmac_init(struct net_device
- if (err)
- goto out_uninit;
-
-+ if (sc->rx_hw_checksum == ENABLE) {
-+ printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
-+ sc->sbm_dev->name);
-+ }
-+
- if (periph_rev >= 2) {
- printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
- sc->sbm_dev->name);
-diff -urpNX dontdiff linux-2.6.12/drivers/net/sgiseeq.c linux_HEAD/drivers/net/sgiseeq.c
---- linux-2.6.12/drivers/net/sgiseeq.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/sgiseeq.c 2005-04-12 16:58:59.000000000 +0200
-@@ -493,11 +493,13 @@ static int sgiseeq_close(struct net_devi
- {
- struct sgiseeq_private *sp = netdev_priv(dev);
- struct sgiseeq_regs *sregs = sp->sregs;
-+ unsigned int irq = dev->irq;
-
- netif_stop_queue(dev);
-
- /* Shutdown the Seeq. */
- reset_hpc3_and_seeq(sp->hregs, sregs);
-+ free_irq(irq, dev);
-
- return 0;
- }
-@@ -734,7 +736,7 @@ static int sgiseeq_init(struct hpc3_regs
- return 0;
-
- err_out_free_page:
-- free_page((unsigned long) sp);
-+ free_page((unsigned long) sp->srings);
- err_out_free_dev:
- kfree(dev);
-
-@@ -754,15 +756,12 @@ static void __exit sgiseeq_exit(void)
- {
- struct net_device *next, *dev;
- struct sgiseeq_private *sp;
-- int irq;
-
- for (dev = root_sgiseeq_dev; dev; dev = next) {
- sp = (struct sgiseeq_private *) netdev_priv(dev);
- next = sp->next_module;
-- irq = dev->irq;
- unregister_netdev(dev);
-- free_irq(irq, dev);
-- free_page((unsigned long) sp);
-+ free_page((unsigned long) sp->srings);
- free_netdev(dev);
- }
- }
-diff -urpNX dontdiff linux-2.6.12/drivers/net/titan_ge.c linux_HEAD/drivers/net/titan_ge.c
---- linux-2.6.12/drivers/net/titan_ge.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/titan_ge.c 2005-07-01 12:09:48.000000000 +0200
-@@ -0,0 +1,2071 @@
-+/*
-+ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+ * The MAC unit of the Titan consists of the following:
-+ *
-+ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
-+ * -> FIFO is where the incoming and outgoing data is placed
-+ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
-+ * the data into the FIFO for Rx
-+ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
-+ * -> AFX is the address filtering block
-+ * -> GMII block to communicate with the PHY
-+ *
-+ * Rx will look like the following:
-+ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
-+ *
-+ * Tx will look like the following:
-+ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
-+ *
-+ * The Titan driver has support for the following performance features:
-+ * -> Rx side checksumming
-+ * -> Jumbo Frames
-+ * -> Interrupt Coalscing
-+ * -> Rx NAPI
-+ * -> SKB Recycling
-+ * -> Transmit/Receive descriptors in SRAM
-+ * -> Fast routing for IP forwarding
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/ioport.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+#include <linux/errno.h>
-+#include <linux/ip.h>
-+#include <linux/init.h>
-+#include <linux/in.h>
-+
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/mii.h>
-+#include <linux/delay.h>
-+#include <linux/skbuff.h>
-+#include <linux/prefetch.h>
-+
-+/* For MII specifc registers, titan_mdio.h should be included */
-+#include <net/ip.h>
-+
-+#include <asm/bitops.h>
-+#include <asm/io.h>
-+#include <asm/types.h>
-+#include <asm/pgtable.h>
-+#include <asm/system.h>
-+#include <asm/titan_dep.h>
-+
-+#include "titan_ge.h"
-+#include "titan_mdio.h"
-+
-+/* Static Function Declarations */
-+static int titan_ge_eth_open(struct net_device *);
-+static void titan_ge_eth_stop(struct net_device *);
-+static struct net_device_stats *titan_ge_get_stats(struct net_device *);
-+static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
-+ unsigned long, unsigned long,
-+ unsigned long);
-+static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
-+ unsigned long, unsigned long);
-+
-+static int titan_ge_open(struct net_device *);
-+static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
-+static int titan_ge_stop(struct net_device *);
-+
-+static unsigned long titan_ge_tx_coal(unsigned long, int);
-+
-+static void titan_ge_port_reset(unsigned int);
-+static int titan_ge_free_tx_queue(titan_ge_port_info *);
-+static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
-+static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
-+
-+static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
-+
-+/*
-+ * Some configuration for the FIFO and the XDMA channel needs
-+ * to be done only once for all the ports. This flag controls
-+ * that
-+ */
-+static unsigned long config_done;
-+
-+/*
-+ * One time out of memory flag
-+ */
-+static unsigned int oom_flag;
-+
-+static int titan_ge_poll(struct net_device *netdev, int *budget);
-+
-+static int titan_ge_receive_queue(struct net_device *, unsigned int);
-+
-+static struct platform_device *titan_ge_device[3];
-+
-+/* MAC Address */
-+extern unsigned char titan_ge_mac_addr_base[6];
-+
-+unsigned long titan_ge_base;
-+static unsigned long titan_ge_sram;
-+
-+static char titan_string[] = "titan";
-+
-+/*
-+ * The Titan GE has two alignment requirements:
-+ * -> skb->data to be cacheline aligned (32 byte)
-+ * -> IP header alignment to 16 bytes
-+ *
-+ * The latter is not implemented. So, that results in an extra copy on
-+ * the Rx. This is a big performance hog. For the former case, the
-+ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
-+ * requested is calculated:
-+ *
-+ * Ethernet Frame Size : 1518
-+ * Ethernet Header : 14
-+ * Future Titan change for IP header alignment : 2
-+ *
-+ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes. For IP header
-+ * alignment, we use skb_reserve().
-+ */
-+
-+#define ALIGNED_RX_SKB_ADDR(addr) \
-+ ((((unsigned long)(addr) + (64UL - 1UL)) \
-+ & ~(64UL - 1UL)) - (unsigned long)(addr))
-+
-+#define titan_ge_alloc_skb(__length, __gfp_flags) \
-+({ struct sk_buff *__skb; \
-+ __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
-+ if(__skb) { \
-+ int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
-+ if(__offset) \
-+ skb_reserve(__skb, __offset); \
-+ } \
-+ __skb; \
-+})
-+
-+/*
-+ * Configure the GMII block of the Titan based on what the PHY tells us
-+ */
-+static void titan_ge_gmii_config(int port_num)
-+{
-+ unsigned int reg_data = 0, phy_reg;
-+ int err;
-+
-+ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
-+
-+ if (err == TITAN_GE_MDIO_ERROR) {
-+ printk(KERN_ERR
-+ "Could not read PHY control register 0x11 \n");
-+ printk(KERN_ERR
-+ "Setting speed to 1000 Mbps and Duplex to Full \n");
-+
-+ return;
-+ }
-+
-+ err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
-+
-+ if (phy_reg & 0x8000) {
-+ if (phy_reg & 0x2000) {
-+ /* Full Duplex and 1000 Mbps */
-+ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+ (port_num << 12)), 0x201);
-+ } else {
-+ /* Half Duplex and 1000 Mbps */
-+ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+ (port_num << 12)), 0x2201);
-+ }
-+ }
-+ if (phy_reg & 0x4000) {
-+ if (phy_reg & 0x2000) {
-+ /* Full Duplex and 100 Mbps */
-+ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+ (port_num << 12)), 0x100);
-+ } else {
-+ /* Half Duplex and 100 Mbps */
-+ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+ (port_num << 12)), 0x2100);
-+ }
-+ }
-+ reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
-+ (port_num << 12));
-+ reg_data |= 0x3;
-+ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
-+ (port_num << 12)), reg_data);
-+}
-+
-+/*
-+ * Enable the TMAC if it is not
-+ */
-+static void titan_ge_enable_tx(unsigned int port_num)
-+{
-+ unsigned long reg_data;
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
-+ if (!(reg_data & 0x8000)) {
-+ printk("TMAC disabled for port %d!! \n", port_num);
-+
-+ reg_data |= 0x0001; /* Enable TMAC */
-+ reg_data |= 0x4000; /* CRC Check Enable */
-+ reg_data |= 0x2000; /* Padding enable */
-+ reg_data |= 0x0800; /* CRC Add enable */
-+ reg_data |= 0x0080; /* PAUSE frame */
-+
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+ (port_num << 12)), reg_data);
-+ }
-+}
-+
-+/*
-+ * Tx Timeout function
-+ */
-+static void titan_ge_tx_timeout(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+ printk(KERN_INFO "%s: TX timeout ", netdev->name);
-+ printk(KERN_INFO "Resetting card \n");
-+
-+ /* Do the reset outside of interrupt context */
-+ schedule_work(&titan_ge_eth->tx_timeout_task);
-+}
-+
-+/*
-+ * Update the AFX tables for UC and MC for slice 0 only
-+ */
-+static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
-+{
-+ int port = titan_ge_eth->port_num;
-+ unsigned int i;
-+ volatile unsigned long reg_data = 0;
-+ u8 p_addr[6];
-+
-+ memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
-+
-+ /* Set the MAC address here for TMAC and RMAC */
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
-+ ((p_addr[5] << 8) | p_addr[4]));
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
-+ ((p_addr[3] << 8) | p_addr[2]));
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
-+ ((p_addr[1] << 8) | p_addr[0]));
-+
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
-+ ((p_addr[5] << 8) | p_addr[4]));
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
-+ ((p_addr[3] << 8) | p_addr[2]));
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
-+ ((p_addr[1] << 8) | p_addr[0]));
-+
-+ TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
-+ /* Configure the eight address filters */
-+ for (i = 0; i < 8; i++) {
-+ /* Select each of the eight filters */
-+ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
-+ (port << 12)), i);
-+
-+ /* Configure the match */
-+ reg_data = 0x9; /* Forward Enable Bit */
-+ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
-+ (port << 12)), reg_data);
-+
-+ /* Finally, AFX Exact Match Address Registers */
-+ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
-+ ((p_addr[1] << 8) | p_addr[0]));
-+ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
-+ ((p_addr[3] << 8) | p_addr[2]));
-+ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
-+ ((p_addr[5] << 8) | p_addr[4]));
-+
-+ /* VLAN id set to 0 */
-+ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
-+ (port << 12)), 0);
-+ }
-+}
-+
-+/*
-+ * Actual Routine to reset the adapter when the timeout occurred
-+ */
-+static void titan_ge_tx_timeout_task(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ int port = titan_ge_eth->port_num;
-+
-+ printk("Titan GE: Transmit timed out. Resetting ... \n");
-+
-+ /* Dump debug info */
-+ printk(KERN_ERR "TRTG cause : %x \n",
-+ TITAN_GE_READ(0x100c + (port << 12)));
-+
-+ /* Fix this for the other ports */
-+ printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
-+ printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
-+ printk(KERN_ERR "XDMA GDI ERROR : %x \n",
-+ TITAN_GE_READ(0x5008 + (port << 8)));
-+ printk(KERN_ERR "CHANNEL ERROR: %x \n",
-+ TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
-+ + (port << 8)));
-+
-+ netif_device_detach(netdev);
-+ titan_ge_port_reset(titan_ge_eth->port_num);
-+ titan_ge_port_start(netdev, titan_ge_eth);
-+ netif_device_attach(netdev);
-+}
-+
-+/*
-+ * Change the MTU of the Ethernet Device
-+ */
-+static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned long flags;
-+
-+ if ((new_mtu > 9500) || (new_mtu < 64))
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+ netdev->mtu = new_mtu;
-+
-+ /* Now we have to reopen the interface so that SKBs with the new
-+ * size will be allocated */
-+
-+ if (netif_running(netdev)) {
-+ titan_ge_eth_stop(netdev);
-+
-+ if (titan_ge_eth_open(netdev) != TITAN_OK) {
-+ printk(KERN_ERR
-+ "%s: Fatal error on opening device\n",
-+ netdev->name);
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+ return -1;
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+ return 0;
-+}
-+
-+/*
-+ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
-+ * only. Once an interrupt is triggered, figure out the port and then check
-+ * the channel.
-+ */
-+static irqreturn_t titan_ge_int_handler(int irq, void *dev_id,
-+ struct pt_regs *regs)
-+{
-+ struct net_device *netdev = (struct net_device *) dev_id;
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ unsigned int reg_data;
-+ unsigned int eth_int_cause_error = 0, is;
-+ unsigned long eth_int_cause1;
-+ int err = 0;
-+#ifdef CONFIG_SMP
-+ unsigned long eth_int_cause2;
-+#endif
-+
-+ /* Ack the CPU interrupt */
-+ switch (port_num) {
-+ case 0:
-+ is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
-+ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
-+
-+#ifdef CONFIG_SMP
-+ is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
-+ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
-+#endif
-+ break;
-+
-+ case 1:
-+ is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
-+ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
-+
-+#ifdef CONFIG_SMP
-+ is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
-+ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
-+#endif
-+ break;
-+
-+ case 2:
-+ is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
-+ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
-+
-+#ifdef CONFIG_SMP
-+ is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
-+ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
-+#endif
-+ }
-+
-+ eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
-+#ifdef CONFIG_SMP
-+ eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
-+#endif
-+
-+ /* Spurious interrupt */
-+#ifdef CONFIG_SMP
-+ if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
-+#else
-+ if (eth_int_cause1 == 0) {
-+#endif
-+ eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
-+ (port_num << 8));
-+
-+ if (eth_int_cause_error == 0)
-+ return IRQ_NONE;
-+ }
-+
-+ /* Handle Tx first. No need to ack interrupts */
-+#ifdef CONFIG_SMP
-+ if ( (eth_int_cause1 & 0x20202) ||
-+ (eth_int_cause2 & 0x20202) )
-+#else
-+ if (eth_int_cause1 & 0x20202)
-+#endif
-+ titan_ge_free_tx_queue(titan_ge_eth);
-+
-+ /* Handle the Rx next */
-+#ifdef CONFIG_SMP
-+ if ( (eth_int_cause1 & 0x10101) ||
-+ (eth_int_cause2 & 0x10101)) {
-+#else
-+ if (eth_int_cause1 & 0x10101) {
-+#endif
-+ if (netif_rx_schedule_prep(netdev)) {
-+ unsigned int ack;
-+
-+ ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+ /* Disable Tx and Rx both */
-+ if (port_num == 0)
-+ ack &= ~(0x3);
-+ if (port_num == 1)
-+ ack &= ~(0x300);
-+
-+ if (port_num == 2)
-+ ack &= ~(0x30000);
-+
-+ /* Interrupts have been disabled */
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
-+
-+ __netif_rx_schedule(netdev);
-+ }
-+ }
-+
-+ /* Handle error interrupts */
-+ if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
-+ printk(KERN_ERR
-+ "XDMA Channel Error : %x on port %d\n",
-+ eth_int_cause_error, port_num);
-+
-+ printk(KERN_ERR
-+ "XDMA GDI Hardware error : %x on port %d\n",
-+ TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
-+
-+ printk(KERN_ERR
-+ "XDMA currently has %d Rx descriptors \n",
-+ TITAN_GE_READ(0x5048 + (port_num << 8)));
-+
-+ printk(KERN_ERR
-+ "XDMA currently has prefetcted %d Rx descriptors \n",
-+ TITAN_GE_READ(0x505c + (port_num << 8)));
-+
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
-+ (port_num << 8)), eth_int_cause_error);
-+ }
-+
-+ /*
-+ * PHY interrupt to inform abt the changes. Reading the
-+ * PHY Status register will clear the interrupt
-+ */
-+ if ((!(eth_int_cause1 & 0x30303)) &&
-+ (eth_int_cause_error == 0)) {
-+ err =
-+ titan_ge_mdio_read(port_num,
-+ TITAN_GE_MDIO_PHY_IS, ®_data);
-+
-+ if (reg_data & 0x0400) {
-+ /* Link status change */
-+ titan_ge_mdio_read(port_num,
-+ TITAN_GE_MDIO_PHY_STATUS, ®_data);
-+ if (!(reg_data & 0x0400)) {
-+ /* Link is down */
-+ netif_carrier_off(netdev);
-+ netif_stop_queue(netdev);
-+ } else {
-+ /* Link is up */
-+ netif_carrier_on(netdev);
-+ netif_wake_queue(netdev);
-+
-+ /* Enable the queue */
-+ titan_ge_enable_tx(port_num);
-+ }
-+ }
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/*
-+ * Multicast and Promiscuous mode set. The
-+ * set_multi entry point is called whenever the
-+ * multicast address list or the network interface
-+ * flags are updated.
-+ */
-+static void titan_ge_set_multi(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ unsigned long reg_data;
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
-+ (port_num << 12));
-+
-+ if (netdev->flags & IFF_PROMISC) {
-+ reg_data |= 0x2;
-+ }
-+ else if (netdev->flags & IFF_ALLMULTI) {
-+ reg_data |= 0x01;
-+ reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
-+ }
-+ else {
-+ reg_data = 0x2;
-+ }
-+
-+ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
-+ (port_num << 12)), reg_data);
-+ if (reg_data & 0x01) {
-+ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
-+ (port_num << 12)), 0xffff);
-+ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
-+ (port_num << 12)), 0xffff);
-+ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
-+ (port_num << 12)), 0xffff);
-+ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
-+ (port_num << 12)), 0xffff);
-+ }
-+}
-+
-+/*
-+ * Open the network device
-+ */
-+static int titan_ge_open(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
-+ int retval;
-+
-+ retval = request_irq(irq, titan_ge_int_handler,
-+ SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
-+
-+ if (retval != 0) {
-+ printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
-+ return -1;
-+ }
-+
-+ netdev->irq = irq;
-+ printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
-+
-+ spin_lock_irq(&(titan_ge_eth->lock));
-+
-+ if (titan_ge_eth_open(netdev) != TITAN_OK) {
-+ spin_unlock_irq(&(titan_ge_eth->lock));
-+ printk("%s: Error opening interface \n", netdev->name);
-+ free_irq(netdev->irq, netdev);
-+ return -EBUSY;
-+ }
-+
-+ spin_unlock_irq(&(titan_ge_eth->lock));
-+
-+ return 0;
-+}
-+
-+/*
-+ * Allocate the SKBs for the Rx ring. Also used
-+ * for refilling the queue
-+ */
-+static int titan_ge_rx_task(struct net_device *netdev,
-+ titan_ge_port_info *titan_ge_port)
-+{
-+ struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
-+ volatile titan_ge_rx_desc *rx_desc;
-+ struct sk_buff *skb;
-+ int rx_used_desc;
-+ int count = 0;
-+
-+ while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
-+
-+ /* First try to get the skb from the recycler */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
-+#else
-+ skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
-+#endif
-+ if (unlikely(!skb)) {
-+ /* OOM, set the flag */
-+ printk("OOM \n");
-+ oom_flag = 1;
-+ break;
-+ }
-+ count++;
-+ skb->dev = netdev;
-+
-+ titan_ge_port->rx_ring_skbs++;
-+
-+ rx_used_desc = titan_ge_port->rx_used_desc_q;
-+ rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ rx_desc->buffer_addr = dma_map_single(device, skb->data,
-+ TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
-+#else
-+ rx_desc->buffer_addr = dma_map_single(device, skb->data,
-+ TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
-+#endif
-+
-+ titan_ge_port->rx_skb[rx_used_desc] = skb;
-+ rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
-+
-+ titan_ge_port->rx_used_desc_q =
-+ (rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
-+ }
-+
-+ return count;
-+}
-+
-+/*
-+ * Actual init of the Tital GE port. There is one register for
-+ * the channel configuration
-+ */
-+static void titan_port_init(struct net_device *netdev,
-+ titan_ge_port_info * titan_ge_eth)
-+{
-+ unsigned long reg_data;
-+
-+ titan_ge_port_reset(titan_ge_eth->port_num);
-+
-+ /* First reset the TMAC */
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+ reg_data |= 0x80000000;
-+ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+ udelay(30);
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+ reg_data &= ~(0xc0000000);
-+ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+ /* Now reset the RMAC */
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+ reg_data |= 0x00080000;
-+ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+ udelay(30);
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+ reg_data &= ~(0x000c0000);
-+ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+}
-+
-+/*
-+ * Start the port. All the hardware specific configuration
-+ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
-+ * go here
-+ */
-+static int titan_ge_port_start(struct net_device *netdev,
-+ titan_ge_port_info * titan_port)
-+{
-+ volatile unsigned long reg_data, reg_data1;
-+ int port_num = titan_port->port_num;
-+ int count = 0;
-+ unsigned long reg_data_1;
-+
-+ if (config_done == 0) {
-+ reg_data = TITAN_GE_READ(0x0004);
-+ reg_data |= 0x100;
-+ TITAN_GE_WRITE(0x0004, reg_data);
-+
-+ reg_data &= ~(0x100);
-+ TITAN_GE_WRITE(0x0004, reg_data);
-+
-+ /* Turn on GMII/MII mode and turn off TBI mode */
-+ reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
-+ reg_data |= 0x00000700;
-+ reg_data &= ~(0x00800000); /* Fencing */
-+
-+ TITAN_GE_WRITE(0x000c, 0x00001100);
-+
-+ TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
-+
-+ /* Set the CPU Resource Limit register */
-+ TITAN_GE_WRITE(0x00f8, 0x8);
-+
-+ /* Be conservative when using the BIU buffers */
-+ TITAN_GE_WRITE(0x0068, 0x4);
-+ }
-+
-+ titan_port->tx_threshold = 0;
-+ titan_port->rx_threshold = 0;
-+
-+ /* We need to write the descriptors for Tx and Rx */
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
-+ (unsigned long) titan_port->tx_dma);
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
-+ (unsigned long) titan_port->rx_dma);
-+
-+ if (config_done == 0) {
-+ /* Step 1: XDMA config */
-+ reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
-+ reg_data &= ~(0x80000000); /* clear reset */
-+ reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */
-+ reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */
-+ reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */
-+ reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */
-+ TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
-+ }
-+
-+ /* IR register for the XDMA */
-+ reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
-+ reg_data |= 0x80068000; /* No Rx_OOD */
-+ TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
-+
-+ /* Start the Tx and Rx XDMA controller */
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
-+ reg_data &= 0x4fffffff; /* Clear tx reset */
-+ reg_data &= 0xfff4ffff; /* Clear rx reset */
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ reg_data |= 0xa0 | 0x30030000;
-+#else
-+ reg_data |= 0x40 | 0x20030000;
-+#endif
-+
-+#ifndef CONFIG_SMP
-+ reg_data &= ~(0x10);
-+ reg_data |= 0x0f; /* All of the packet */
-+#endif
-+
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
-+
-+ /* Rx desc count */
-+ count = titan_ge_rx_task(netdev, titan_port);
-+ TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
-+ count = TITAN_GE_READ(0x5048 + (port_num << 8));
-+
-+ udelay(30);
-+
-+ /*
-+ * Step 2: Configure the SDQPF, i.e. FIFO
-+ */
-+ if (config_done == 0) {
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
-+ reg_data = 0x1;
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+ reg_data &= ~(0x1);
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
-+ reg_data = 0x1;
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+ reg_data &= ~(0x1);
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+ }
-+ /*
-+ * Enable RX FIFO 0, 4 and 8
-+ */
-+ if (port_num == 0) {
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
-+
-+ reg_data |= 0x100000;
-+ reg_data |= (0xff << 10);
-+
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
-+ /*
-+ * BAV2,BAV and DAV settings for the Rx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x4844);
-+ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+ TITAN_GE_WRITE(0x4844, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
-+
-+ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
-+ reg_data |= 0x100000;
-+
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+ reg_data |= (0xff << 10);
-+
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+ /*
-+ * BAV2, BAV and DAV settings for the Tx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x4944);
-+ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+ TITAN_GE_WRITE(0x4944, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+ }
-+
-+ if (port_num == 1) {
-+ reg_data = TITAN_GE_READ(0x4870);
-+
-+ reg_data |= 0x100000;
-+ reg_data |= (0xff << 10) | (0xff + 1);
-+
-+ TITAN_GE_WRITE(0x4870, reg_data);
-+ /*
-+ * BAV2,BAV and DAV settings for the Rx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x4874);
-+ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+ TITAN_GE_WRITE(0x4874, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x4870, reg_data);
-+
-+ reg_data = TITAN_GE_READ(0x494c);
-+ reg_data |= 0x100000;
-+
-+ TITAN_GE_WRITE(0x494c, reg_data);
-+ reg_data |= (0xff << 10) | (0xff + 1);
-+ TITAN_GE_WRITE(0x494c, reg_data);
-+
-+ /*
-+ * BAV2, BAV and DAV settings for the Tx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x4950);
-+ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+ TITAN_GE_WRITE(0x4950, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x494c, reg_data);
-+ }
-+
-+ /*
-+ * Titan 1.2 revision does support port #2
-+ */
-+ if (port_num == 2) {
-+ /*
-+ * Put the descriptors in the SRAM
-+ */
-+ reg_data = TITAN_GE_READ(0x48a0);
-+
-+ reg_data |= 0x100000;
-+ reg_data |= (0xff << 10) | (2*(0xff + 1));
-+
-+ TITAN_GE_WRITE(0x48a0, reg_data);
-+ /*
-+ * BAV2,BAV and DAV settings for the Rx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x48a4);
-+ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+ TITAN_GE_WRITE(0x48a4, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x48a0, reg_data);
-+
-+ reg_data = TITAN_GE_READ(0x4958);
-+ reg_data |= 0x100000;
-+
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+ reg_data |= (0xff << 10) | (2*(0xff + 1));
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+
-+ /*
-+ * BAV2, BAV and DAV settings for the Tx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x495c);
-+ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+ TITAN_GE_WRITE(0x495c, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+ }
-+
-+ if (port_num == 2) {
-+ reg_data = TITAN_GE_READ(0x48a0);
-+
-+ reg_data |= 0x100000;
-+ reg_data |= (0xff << 10) | (2*(0xff + 1));
-+
-+ TITAN_GE_WRITE(0x48a0, reg_data);
-+ /*
-+ * BAV2,BAV and DAV settings for the Rx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x48a4);
-+ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+ TITAN_GE_WRITE(0x48a4, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x48a0, reg_data);
-+
-+ reg_data = TITAN_GE_READ(0x4958);
-+ reg_data |= 0x100000;
-+
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+ reg_data |= (0xff << 10) | (2*(0xff + 1));
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+
-+ /*
-+ * BAV2, BAV and DAV settings for the Tx FIFO
-+ */
-+ reg_data1 = TITAN_GE_READ(0x495c);
-+ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+ TITAN_GE_WRITE(0x495c, reg_data1);
-+
-+ reg_data &= ~(0x00100000);
-+ reg_data |= 0x200000;
-+
-+ TITAN_GE_WRITE(0x4958, reg_data);
-+ }
-+
-+ /*
-+ * Step 3: TRTG block enable
-+ */
-+ reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
-+
-+ /*
-+ * This is the 1.2 revision of the chip. It has fix for the
-+ * IP header alignment. Now, the IP header begins at an
-+ * aligned address and this wont need an extra copy in the
-+ * driver. This performance drawback existed in the previous
-+ * versions of the silicon
-+ */
-+ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
-+ reg_data_1 |= 0x40000000;
-+ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+ reg_data_1 |= 0x04000000;
-+ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+ mdelay(5);
-+
-+ reg_data_1 &= ~(0x04000000);
-+ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+ mdelay(5);
-+
-+ reg_data |= 0x0001;
-+ TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
-+
-+ /*
-+ * Step 4: Start the Tx activity
-+ */
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
-+#endif
-+ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
-+ reg_data |= 0x0001; /* Enable TMAC */
-+ reg_data |= 0x6c70; /* PAUSE also set */
-+
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+ udelay(30);
-+
-+ /* Destination Address drop bit */
-+ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
-+ reg_data |= 0x218; /* DA_DROP bit and pause */
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
-+
-+ TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
-+#endif
-+ /* Start the Rx activity */
-+ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
-+ reg_data |= 0x0001; /* RMAC Enable */
-+ reg_data |= 0x0010; /* CRC Check enable */
-+ reg_data |= 0x0040; /* Min Frame check enable */
-+ reg_data |= 0x4400; /* Max Frame check enable */
-+
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+ udelay(30);
-+
-+ /*
-+ * Enable the Interrupts for Tx and Rx
-+ */
-+ reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+
-+ if (port_num == 0) {
-+ reg_data1 |= 0x3;
-+#ifdef CONFIG_SMP
-+ TITAN_GE_WRITE(0x0038, 0x003);
-+#else
-+ TITAN_GE_WRITE(0x0038, 0x303);
-+#endif
-+ }
-+
-+ if (port_num == 1) {
-+ reg_data1 |= 0x300;
-+ }
-+
-+ if (port_num == 2)
-+ reg_data1 |= 0x30000;
-+
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
-+ TITAN_GE_WRITE(0x003c, 0x300);
-+
-+ if (config_done == 0) {
-+ TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */
-+ TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */
-+ }
-+
-+ /* Priority */
-+ reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
-+ reg_data &= ~(0x00f00000);
-+ TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
-+
-+ /* Step 5: GMII config */
-+ titan_ge_gmii_config(port_num);
-+
-+ if (config_done == 0) {
-+ TITAN_GE_WRITE(0x1a80, 0);
-+ config_done = 1;
-+ }
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Function to queue the packet for the Ethernet device
-+ */
-+static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
-+ struct sk_buff * skb)
-+{
-+ struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
-+ unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
-+ volatile titan_ge_tx_desc *tx_curr;
-+ int port_num = titan_ge_eth->port_num;
-+
-+ tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
-+ tx_curr->buffer_addr =
-+ dma_map_single(device, skb->data, skb_headlen(skb),
-+ DMA_TO_DEVICE);
-+
-+ titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
-+ tx_curr->buffer_len = skb_headlen(skb);
-+
-+ /* Last descriptor enables interrupt and changes ownership */
-+ tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
-+
-+ /* Kick the XDMA to start the transfer from memory to the FIFO */
-+ TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
-+
-+ /* Current descriptor updated */
-+ titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
-+
-+ /* Prefetch the next descriptor */
-+ prefetch((const void *)
-+ &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
-+}
-+
-+/*
-+ * Actually does the open of the Ethernet device
-+ */
-+static int titan_ge_eth_open(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ struct device *device = &titan_ge_device[port_num]->dev;
-+ unsigned long reg_data;
-+ unsigned int phy_reg;
-+ int err = 0;
-+
-+ /* Stop the Rx activity */
-+ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
-+ reg_data &= ~(0x00000001);
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+ /* Clear the port interrupts */
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
-+
-+ if (config_done == 0) {
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
-+ }
-+
-+ /* Set the MAC Address */
-+ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
-+
-+ if (config_done == 0)
-+ titan_port_init(netdev, titan_ge_eth);
-+
-+ titan_ge_update_afx(titan_ge_eth);
-+
-+ /* Allocate the Tx ring now */
-+ titan_ge_eth->tx_ring_skbs = 0;
-+ titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
-+
-+ /* Allocate space in the SRAM for the descriptors */
-+ titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
-+ (titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
-+ titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
-+
-+ if (!titan_ge_eth->tx_desc_area) {
-+ printk(KERN_ERR
-+ "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
-+ netdev->name, TITAN_TX_RING_BYTES, port_num);
-+ return -ENOMEM;
-+ }
-+
-+ memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
-+
-+ /* Now initialize the Tx descriptor ring */
-+ titan_ge_init_tx_desc_ring(titan_ge_eth,
-+ titan_ge_eth->tx_ring_size,
-+ (unsigned long) titan_ge_eth->tx_desc_area,
-+ (unsigned long) titan_ge_eth->tx_dma);
-+
-+ /* Allocate the Rx ring now */
-+ titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
-+ titan_ge_eth->rx_ring_skbs = 0;
-+
-+ titan_ge_eth->rx_desc_area =
-+ (titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
-+
-+ titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
-+
-+ if (!titan_ge_eth->rx_desc_area) {
-+ printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
-+ netdev->name, TITAN_RX_RING_BYTES);
-+
-+ printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
-+ netdev->name);
-+
-+ dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
-+ (void *) titan_ge_eth->tx_desc_area,
-+ titan_ge_eth->tx_dma);
-+
-+ return -ENOMEM;
-+ }
-+
-+ memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
-+
-+ /* Now initialize the Rx ring */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+ if ((titan_ge_init_rx_desc_ring
-+ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
-+ (unsigned long) titan_ge_eth->rx_desc_area, 0,
-+ (unsigned long) titan_ge_eth->rx_dma)) == 0)
-+#else
-+ if ((titan_ge_init_rx_desc_ring
-+ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
-+ (unsigned long) titan_ge_eth->rx_desc_area, 0,
-+ (unsigned long) titan_ge_eth->rx_dma)) == 0)
-+#endif
-+ panic("%s: Error initializing RX Ring\n", netdev->name);
-+
-+ /* Fill the Rx ring with the SKBs */
-+ titan_ge_port_start(netdev, titan_ge_eth);
-+
-+ /*
-+ * Check if Interrupt Coalscing needs to be turned on. The
-+ * values specified in the register is multiplied by
-+ * (8 x 64 nanoseconds) to determine when an interrupt should
-+ * be sent to the CPU.
-+ */
-+
-+ if (TITAN_GE_TX_COAL) {
-+ titan_ge_eth->tx_int_coal =
-+ titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
-+ }
-+
-+ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
-+ if (err == TITAN_GE_MDIO_ERROR) {
-+ printk(KERN_ERR
-+ "Could not read PHY control register 0x11 \n");
-+ return TITAN_ERROR;
-+ }
-+ if (!(phy_reg & 0x0400)) {
-+ netif_carrier_off(netdev);
-+ netif_stop_queue(netdev);
-+ return TITAN_ERROR;
-+ } else {
-+ netif_carrier_on(netdev);
-+ netif_start_queue(netdev);
-+ }
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Queue the packet for Tx. Currently no support for zero copy,
-+ * checksum offload and Scatter Gather. The chip does support
-+ * Scatter Gather only. But, that wont help here since zero copy
-+ * requires support for Tx checksumming also.
-+ */
-+int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned long flags;
-+ struct net_device_stats *stats;
-+//printk("titan_ge_start_xmit\n");
-+
-+ stats = &titan_ge_eth->stats;
-+ spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+ if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
-+ (skb_shinfo(skb)->nr_frags + 1)) {
-+ netif_stop_queue(netdev);
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+ printk(KERN_ERR "Tx OOD \n");
-+ return 1;
-+ }
-+
-+ titan_ge_tx_queue(titan_ge_eth, skb);
-+ titan_ge_eth->tx_ring_skbs++;
-+
-+ if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+ titan_ge_free_tx_queue(titan_ge_eth);
-+ spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+ }
-+
-+ stats->tx_bytes += skb->len;
-+ stats->tx_packets++;
-+
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+ netdev->trans_start = jiffies;
-+
-+ return 0;
-+}
-+
-+/*
-+ * Actually does the Rx. Rx side checksumming supported.
-+ */
-+static int titan_ge_rx(struct net_device *netdev, int port_num,
-+ titan_ge_port_info * titan_ge_port,
-+ titan_ge_packet * packet)
-+{
-+ int rx_curr_desc, rx_used_desc;
-+ volatile titan_ge_rx_desc *rx_desc;
-+
-+ rx_curr_desc = titan_ge_port->rx_curr_desc_q;
-+ rx_used_desc = titan_ge_port->rx_used_desc_q;
-+
-+ if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
-+ return TITAN_ERROR;
-+
-+ rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
-+
-+ if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
-+ return TITAN_ERROR;
-+
-+ packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
-+ packet->len = (rx_desc->cmd_sts & 0x7fff);
-+
-+ /*
-+ * At this point, we dont know if the checksumming
-+ * actually helps relieve CPU. So, keep it for
-+ * port 0 only
-+ */
-+ packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
-+ packet->cmd_sts = rx_desc->cmd_sts;
-+
-+ titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
-+
-+ /* Prefetch the next descriptor */
-+ prefetch((const void *)
-+ &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Free the Tx queue of the used SKBs
-+ */
-+static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
-+{
-+ unsigned long flags;
-+
-+ /* Take the lock */
-+ spin_lock_irqsave(&(titan_ge_eth->lock), flags);
-+
-+ while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
-+ if (titan_ge_eth->tx_ring_skbs != 1)
-+ titan_ge_eth->tx_ring_skbs--;
-+
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Threshold beyond which we do the cleaning of
-+ * Tx queue and new allocation for the Rx
-+ * queue
-+ */
-+#define TX_THRESHOLD 4
-+#define RX_THRESHOLD 10
-+
-+/*
-+ * Receive the packets and send it to the kernel.
-+ */
-+static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ titan_ge_packet packet;
-+ struct net_device_stats *stats;
-+ struct sk_buff *skb;
-+ unsigned long received_packets = 0;
-+ unsigned int ack;
-+
-+ stats = &titan_ge_eth->stats;
-+
-+ while ((--max)
-+ && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
-+ skb = (struct sk_buff *) packet.skb;
-+
-+ titan_ge_eth->rx_ring_skbs--;
-+
-+ if (--titan_ge_eth->rx_work_limit < 0)
-+ break;
-+ received_packets++;
-+
-+ stats->rx_packets++;
-+ stats->rx_bytes += packet.len;
-+
-+ if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
-+ (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
-+ (packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
-+ (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
-+ stats->rx_dropped++;
-+ dev_kfree_skb_any(skb);
-+
-+ continue;
-+ }
-+ /*
-+ * Either support fast path or slow path. Decision
-+ * making can really slow down the performance. The
-+ * idea is to cut down the number of checks and improve
-+ * the fastpath.
-+ */
-+
-+ skb_put(skb, packet.len - 2);
-+
-+ /*
-+ * Increment data pointer by two since thats where
-+ * the MAC starts
-+ */
-+ skb_reserve(skb, 2);
-+ skb->protocol = eth_type_trans(skb, netdev);
-+ netif_receive_skb(skb);
-+
-+ if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
-+ ack = titan_ge_rx_task(netdev, titan_ge_eth);
-+ TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
-+ titan_ge_eth->rx_threshold = 0;
-+ } else
-+ titan_ge_eth->rx_threshold++;
-+
-+ if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
-+ titan_ge_eth->tx_threshold = 0;
-+ titan_ge_free_tx_queue(titan_ge_eth);
-+ }
-+ else
-+ titan_ge_eth->tx_threshold++;
-+
-+ }
-+ return received_packets;
-+}
-+
-+
-+/*
-+ * Enable the Rx side interrupts
-+ */
-+static void titan_ge_enable_int(unsigned int port_num,
-+ titan_ge_port_info *titan_ge_eth,
-+ struct net_device *netdev)
-+{
-+ unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+
-+ if (port_num == 0)
-+ reg_data |= 0x3;
-+ if (port_num == 1)
-+ reg_data |= 0x300;
-+ if (port_num == 2)
-+ reg_data |= 0x30000;
-+
-+ /* Re-enable interrupts */
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
-+}
-+
-+/*
-+ * Main function to handle the polling for Rx side NAPI.
-+ * Receive interrupts have been disabled at this point.
-+ * The poll schedules the transmit followed by receive.
-+ */
-+static int titan_ge_poll(struct net_device *netdev, int *budget)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ int port_num = titan_ge_eth->port_num;
-+ int work_done = 0;
-+ unsigned long flags, status;
-+
-+ titan_ge_eth->rx_work_limit = *budget;
-+ if (titan_ge_eth->rx_work_limit > netdev->quota)
-+ titan_ge_eth->rx_work_limit = netdev->quota;
-+
-+ do {
-+ /* Do the transmit cleaning work here */
-+ titan_ge_free_tx_queue(titan_ge_eth);
-+
-+ /* Ack the Rx interrupts */
-+ if (port_num == 0)
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
-+ if (port_num == 1)
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
-+ if (port_num == 2)
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
-+
-+ work_done += titan_ge_receive_queue(netdev, 0);
-+
-+ /* Out of quota and there is work to be done */
-+ if (titan_ge_eth->rx_work_limit < 0)
-+ goto not_done;
-+
-+ /* Receive alloc_skb could lead to OOM */
-+ if (oom_flag == 1) {
-+ oom_flag = 0;
-+ goto oom;
-+ }
-+
-+ status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
-+ } while (status & 0x30300);
-+
-+ /* If we are here, then no more interrupts to process */
-+ goto done;
-+
-+not_done:
-+ *budget -= work_done;
-+ netdev->quota -= work_done;
-+ return 1;
-+
-+oom:
-+ printk(KERN_ERR "OOM \n");
-+ netif_rx_complete(netdev);
-+ return 0;
-+
-+done:
-+ /*
-+ * No more packets on the poll list. Turn the interrupts
-+ * back on and we should be able to catch the new
-+ * packets in the interrupt handler
-+ */
-+ if (!work_done)
-+ work_done = 1;
-+
-+ *budget -= work_done;
-+ netdev->quota -= work_done;
-+
-+ spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+ /* Remove us from the poll list */
-+ netif_rx_complete(netdev);
-+
-+ /* Re-enable interrupts */
-+ titan_ge_enable_int(port_num, titan_ge_eth, netdev);
-+
-+ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+ return 0;
-+}
-+
-+/*
-+ * Close the network device
-+ */
-+int titan_ge_stop(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+ spin_lock_irq(&(titan_ge_eth->lock));
-+ titan_ge_eth_stop(netdev);
-+ free_irq(netdev->irq, netdev);
-+ spin_unlock_irq(&titan_ge_eth->lock);
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Free the Tx ring
-+ */
-+static void titan_ge_free_tx_rings(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ unsigned int curr;
-+ unsigned long reg_data;
-+
-+ /* Stop the Tx DMA */
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
-+ (port_num << 8));
-+ reg_data |= 0xc0000000;
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
-+ (port_num << 8)), reg_data);
-+
-+ /* Disable the TMAC */
-+ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
-+ (port_num << 12));
-+ reg_data &= ~(0x00000001);
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+ (port_num << 12)), reg_data);
-+
-+ for (curr = 0;
-+ (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
-+ curr++) {
-+ if (titan_ge_eth->tx_skb[curr]) {
-+ dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
-+ titan_ge_eth->tx_ring_skbs--;
-+ }
-+ }
-+
-+ if (titan_ge_eth->tx_ring_skbs != 0)
-+ printk
-+ ("%s: Error on Tx descriptor free - could not free %d"
-+ " descriptors\n", netdev->name,
-+ titan_ge_eth->tx_ring_skbs);
-+
-+#ifndef TITAN_RX_RING_IN_SRAM
-+ dma_free_coherent(&titan_ge_device[port_num]->dev,
-+ titan_ge_eth->tx_desc_area_size,
-+ (void *) titan_ge_eth->tx_desc_area,
-+ titan_ge_eth->tx_dma);
-+#endif
-+}
-+
-+/*
-+ * Free the Rx ring
-+ */
-+static void titan_ge_free_rx_rings(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ unsigned int curr;
-+ unsigned long reg_data;
-+
-+ /* Stop the Rx DMA */
-+ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
-+ (port_num << 8));
-+ reg_data |= 0x000c0000;
-+ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
-+ (port_num << 8)), reg_data);
-+
-+ /* Disable the RMAC */
-+ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
-+ (port_num << 12));
-+ reg_data &= ~(0x00000001);
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
-+ (port_num << 12)), reg_data);
-+
-+ for (curr = 0;
-+ titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
-+ curr++) {
-+ if (titan_ge_eth->rx_skb[curr]) {
-+ dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
-+ titan_ge_eth->rx_ring_skbs--;
-+ }
-+ }
-+
-+ if (titan_ge_eth->rx_ring_skbs != 0)
-+ printk(KERN_ERR
-+ "%s: Error in freeing Rx Ring. %d skb's still"
-+ " stuck in RX Ring - ignoring them\n", netdev->name,
-+ titan_ge_eth->rx_ring_skbs);
-+
-+#ifndef TITAN_RX_RING_IN_SRAM
-+ dma_free_coherent(&titan_ge_device[port_num]->dev,
-+ titan_ge_eth->rx_desc_area_size,
-+ (void *) titan_ge_eth->rx_desc_area,
-+ titan_ge_eth->rx_dma);
-+#endif
-+}
-+
-+/*
-+ * Actually does the stop of the Ethernet device
-+ */
-+static void titan_ge_eth_stop(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+ netif_stop_queue(netdev);
-+
-+ titan_ge_port_reset(titan_ge_eth->port_num);
-+
-+ titan_ge_free_tx_rings(netdev);
-+ titan_ge_free_rx_rings(netdev);
-+
-+ /* Disable the Tx and Rx Interrupts for all channels */
-+ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
-+}
-+
-+/*
-+ * Update the MAC address. Note that we have to write the
-+ * address in three station registers, 16 bits each. And this
-+ * has to be done for TMAC and RMAC
-+ */
-+static void titan_ge_update_mac_address(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+ unsigned int port_num = titan_ge_eth->port_num;
-+ u8 p_addr[6];
-+
-+ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
-+ memcpy(p_addr, netdev->dev_addr, 6);
-+
-+ /* Update the Address Filtering Match tables */
-+ titan_ge_update_afx(titan_ge_eth);
-+
-+ printk("Station MAC : %d %d %d %d %d %d \n",
-+ p_addr[5], p_addr[4], p_addr[3],
-+ p_addr[2], p_addr[1], p_addr[0]);
-+
-+ /* Set the MAC address here for TMAC and RMAC */
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
-+ ((p_addr[5] << 8) | p_addr[4]));
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
-+ ((p_addr[3] << 8) | p_addr[2]));
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
-+ ((p_addr[1] << 8) | p_addr[0]));
-+
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
-+ ((p_addr[5] << 8) | p_addr[4]));
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
-+ ((p_addr[3] << 8) | p_addr[2]));
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
-+ ((p_addr[1] << 8) | p_addr[0]));
-+}
-+
-+/*
-+ * Set the MAC address of the Ethernet device
-+ */
-+static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
-+{
-+ titan_ge_port_info *tp = netdev_priv(dev);
-+ struct sockaddr *sa = addr;
-+
-+ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
-+
-+ spin_lock_irq(&tp->lock);
-+ titan_ge_update_mac_address(dev);
-+ spin_unlock_irq(&tp->lock);
-+
-+ return 0;
-+}
-+
-+/*
-+ * Get the Ethernet device stats
-+ */
-+static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
-+{
-+ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+ return &titan_ge_eth->stats;
-+}
-+
-+/*
-+ * Initialize the Rx descriptor ring for the Titan Ge
-+ */
-+static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
-+ int rx_desc_num,
-+ int rx_buff_size,
-+ unsigned long rx_desc_base_addr,
-+ unsigned long rx_buff_base_addr,
-+ unsigned long rx_dma)
-+{
-+ volatile titan_ge_rx_desc *rx_desc;
-+ unsigned long buffer_addr;
-+ int index;
-+ unsigned long titan_ge_rx_desc_bus = rx_dma;
-+
-+ buffer_addr = rx_buff_base_addr;
-+ rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
-+
-+ /* Check alignment */
-+ if (rx_buff_base_addr & 0xF)
-+ return 0;
-+
-+ /* Check Rx buffer size */
-+ if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
-+ return 0;
-+
-+ /* 64-bit alignment
-+ if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-+ return 0; */
-+
-+ /* Initialize the Rx desc ring */
-+ for (index = 0; index < rx_desc_num; index++) {
-+ titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
-+ rx_desc[index].cmd_sts = 0;
-+ rx_desc[index].buffer_addr = buffer_addr;
-+ titan_eth_port->rx_skb[index] = NULL;
-+ buffer_addr += rx_buff_size;
-+ }
-+
-+ titan_eth_port->rx_curr_desc_q = 0;
-+ titan_eth_port->rx_used_desc_q = 0;
-+
-+ titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
-+ titan_eth_port->rx_desc_area_size =
-+ rx_desc_num * sizeof(titan_ge_rx_desc);
-+
-+ titan_eth_port->rx_dma = rx_dma;
-+
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Initialize the Tx descriptor ring. Descriptors in the SRAM
-+ */
-+static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
-+ int tx_desc_num,
-+ unsigned long tx_desc_base_addr,
-+ unsigned long tx_dma)
-+{
-+ titan_ge_tx_desc *tx_desc;
-+ int index;
-+ unsigned long titan_ge_tx_desc_bus = tx_dma;
-+
-+ if (tx_desc_base_addr & 0xF)
-+ return 0;
-+
-+ tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
-+
-+ for (index = 0; index < tx_desc_num; index++) {
-+ titan_ge_port->tx_dma_array[index] =
-+ (dma_addr_t) titan_ge_tx_desc_bus;
-+ titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
-+ tx_desc[index].cmd_sts = 0x0000;
-+ tx_desc[index].buffer_len = 0;
-+ tx_desc[index].buffer_addr = 0x00000000;
-+ titan_ge_port->tx_skb[index] = NULL;
-+ }
-+
-+ titan_ge_port->tx_curr_desc_q = 0;
-+ titan_ge_port->tx_used_desc_q = 0;
-+
-+ titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
-+ titan_ge_port->tx_desc_area_size =
-+ tx_desc_num * sizeof(titan_ge_tx_desc);
-+
-+ titan_ge_port->tx_dma = tx_dma;
-+ return TITAN_OK;
-+}
-+
-+/*
-+ * Initialize the device as an Ethernet device
-+ */
-+static int __init titan_ge_probe(struct device *device)
-+{
-+ titan_ge_port_info *titan_ge_eth;
-+ struct net_device *netdev;
-+ int port = to_platform_device(device)->id;
-+ int err;
-+
-+ netdev = alloc_etherdev(sizeof(titan_ge_port_info));
-+ if (!netdev) {
-+ err = -ENODEV;
-+ goto out;
-+ }
-+
-+ netdev->open = titan_ge_open;
-+ netdev->stop = titan_ge_stop;
-+ netdev->hard_start_xmit = titan_ge_start_xmit;
-+ netdev->get_stats = titan_ge_get_stats;
-+ netdev->set_multicast_list = titan_ge_set_multi;
-+ netdev->set_mac_address = titan_ge_set_mac_address;
-+
-+ /* Tx timeout */
-+ netdev->tx_timeout = titan_ge_tx_timeout;
-+ netdev->watchdog_timeo = 2 * HZ;
-+
-+ /* Set these to very high values */
-+ netdev->poll = titan_ge_poll;
-+ netdev->weight = 64;
-+
-+ netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
-+ netif_carrier_off(netdev);
-+ netdev->base_addr = 0;
-+
-+ netdev->change_mtu = titan_ge_change_mtu;
-+
-+ titan_ge_eth = netdev_priv(netdev);
-+ /* Allocation of memory for the driver structures */
-+
-+ titan_ge_eth->port_num = port;
-+
-+ /* Configure the Tx timeout handler */
-+ INIT_WORK(&titan_ge_eth->tx_timeout_task,
-+ (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
-+
-+ spin_lock_init(&titan_ge_eth->lock);
-+
-+ /* set MAC addresses */
-+ memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
-+ netdev->dev_addr[5] += port;
-+
-+ err = register_netdev(netdev);
-+
-+ if (err)
-+ goto out_free_netdev;
-+
-+ printk(KERN_NOTICE
-+ "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
-+ netdev->name, port, netdev->dev_addr[0],
-+ netdev->dev_addr[1], netdev->dev_addr[2],
-+ netdev->dev_addr[3], netdev->dev_addr[4],
-+ netdev->dev_addr[5]);
-+
-+ printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
-+
-+ return 0;
-+
-+out_free_netdev:
-+ kfree(netdev);
-+
-+out:
-+ return err;
-+}
-+
-+static void __devexit titan_device_remove(struct device *device)
-+{
-+}
-+
-+/*
-+ * Reset the Ethernet port
-+ */
-+static void titan_ge_port_reset(unsigned int port_num)
-+{
-+ unsigned int reg_data;
-+
-+ /* Stop the Tx port activity */
-+ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
-+ (port_num << 12));
-+ reg_data &= ~(0x0001);
-+ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+ (port_num << 12)), reg_data);
-+
-+ /* Stop the Rx port activity */
-+ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
-+ (port_num << 12));
-+ reg_data &= ~(0x0001);
-+ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
-+ (port_num << 12)), reg_data);
-+
-+ return;
-+}
-+
-+/*
-+ * Return the Tx desc after use by the XDMA
-+ */
-+static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
-+{
-+ int tx_desc_used;
-+ struct sk_buff *skb;
-+
-+ tx_desc_used = titan_ge_eth->tx_used_desc_q;
-+
-+ /* return right away */
-+ if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
-+ return TITAN_ERROR;
-+
-+ /* Now the critical stuff */
-+ skb = titan_ge_eth->tx_skb[tx_desc_used];
-+
-+ dev_kfree_skb_any(skb);
-+
-+ titan_ge_eth->tx_skb[tx_desc_used] = NULL;
-+ titan_ge_eth->tx_used_desc_q =
-+ (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
-+
-+ return 0;
-+}
-+
-+/*
-+ * Coalescing for the Tx path
-+ */
-+static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
-+{
-+ unsigned long rx_delay;
-+
-+ rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
-+ delay = (delay << 16) | rx_delay;
-+
-+ TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
-+ TITAN_GE_WRITE(0x5038, delay);
-+
-+ return delay;
-+}
-+
-+static struct device_driver titan_soc_driver = {
-+ .name = titan_string,
-+ .bus = &platform_bus_type,
-+ .probe = titan_ge_probe,
-+ .remove = __devexit_p(titan_device_remove),
-+};
-+
-+static void titan_platform_release (struct device *device)
-+{
-+ struct platform_device *pldev;
-+
-+ /* free device */
-+ pldev = to_platform_device (device);
-+ kfree (pldev);
-+}
-+
-+/*
-+ * Register the Titan GE with the kernel
-+ */
-+static int __init titan_ge_init_module(void)
-+{
-+ struct platform_device *pldev;
-+ unsigned int version, device;
-+ int i;
-+
-+ printk(KERN_NOTICE
-+ "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
-+
-+ titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
-+ if (!titan_ge_base) {
-+ printk("Mapping Titan GE failed\n");
-+ goto out;
-+ }
-+
-+ device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
-+ version = (device & 0x000f0000) >> 16;
-+ device &= 0x0000ffff;
-+
-+ printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version);
-+
-+#ifdef TITAN_RX_RING_IN_SRAM
-+ titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
-+ TITAN_SRAM_SIZE);
-+ if (!titan_ge_sram) {
-+ printk("Mapping Titan SRAM failed\n");
-+ goto out_unmap_ge;
-+ }
-+#endif
-+
-+ if (driver_register(&titan_soc_driver)) {
-+ printk(KERN_ERR "Driver registration failed\n");
-+ goto out_unmap_sram;
-+ }
-+
-+ for (i = 0; i < 3; i++) {
-+ titan_ge_device[i] = NULL;
-+
-+ if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
-+ continue;
-+
-+ memset (pldev, 0, sizeof (*pldev));
-+ pldev->name = titan_string;
-+ pldev->id = i;
-+ pldev->dev.release = titan_platform_release;
-+ titan_ge_device[i] = pldev;
-+
-+ if (platform_device_register (pldev)) {
-+ kfree (pldev);
-+ titan_ge_device[i] = NULL;
-+ continue;
-+ }
-+
-+ if (!pldev->dev.driver) {
-+ /*
-+ * The driver was not bound to this device, there was
-+ * no hardware at this address. Unregister it, as the
-+ * release fuction will take care of freeing the
-+ * allocated structure
-+ */
-+ titan_ge_device[i] = NULL;
-+ platform_device_unregister (pldev);
-+ }
-+ }
-+
-+ return 0;
-+
-+out_unmap_sram:
-+ iounmap((void *)titan_ge_sram);
-+
-+out_unmap_ge:
-+ iounmap((void *)titan_ge_base);
-+
-+out:
-+ return -ENOMEM;
-+}
-+
-+/*
-+ * Unregister the Titan GE from the kernel
-+ */
-+static void __exit titan_ge_cleanup_module(void)
-+{
-+ int i;
-+
-+ driver_unregister(&titan_soc_driver);
-+
-+ for (i = 0; i < 3; i++) {
-+ if (titan_ge_device[i]) {
-+ platform_device_unregister (titan_ge_device[i]);
-+ titan_ge_device[i] = NULL;
-+ }
-+ }
-+
-+ iounmap((void *)titan_ge_sram);
-+ iounmap((void *)titan_ge_base);
-+}
-+
-+MODULE_AUTHOR("Manish Lachwani <lachwani at pmc-sierra.com>");
-+MODULE_DESCRIPTION("Titan GE Ethernet driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(titan_ge_init_module);
-+module_exit(titan_ge_cleanup_module);
-diff -urpNX dontdiff linux-2.6.12/drivers/net/titan_ge.h linux_HEAD/drivers/net/titan_ge.h
---- linux-2.6.12/drivers/net/titan_ge.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/titan_ge.h 2005-04-14 16:40:17.000000000 +0200
-@@ -0,0 +1,419 @@
-+#ifndef _TITAN_GE_H_
-+#define _TITAN_GE_H_
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/config.h>
-+#include <linux/spinlock.h>
-+#include <asm/byteorder.h>
-+
-+/*
-+ * These functions should be later moved to a more generic location since there
-+ * will be others accessing it also
-+ */
-+
-+/*
-+ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
-+ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
-+ * register.
-+ */
-+
-+#define TITAN_GE_BASE 0xfe000000UL
-+#define TITAN_GE_SIZE 0x10000UL
-+
-+extern unsigned long titan_ge_base;
-+
-+#define TITAN_GE_WRITE(offset, data) \
-+ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
-+
-+#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
-+
-+#ifndef msec_delay
-+#define msec_delay(x) do { if(in_interrupt()) { \
-+ /* Don't mdelay in interrupt context! */ \
-+ BUG(); \
-+ } else { \
-+ set_current_state(TASK_UNINTERRUPTIBLE); \
-+ schedule_timeout((x * HZ)/1000); \
-+ } } while(0)
-+#endif
-+
-+#define TITAN_GE_PORT_0
-+
-+#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
-+#define TITAN_SRAM_SIZE 0x2000UL
-+
-+extern unsigned long titan_ge_sram;
-+
-+/*
-+ * We may need these constants
-+ */
-+#define TITAN_BIT0 0x00000001
-+#define TITAN_BIT1 0x00000002
-+#define TITAN_BIT2 0x00000004
-+#define TITAN_BIT3 0x00000008
-+#define TITAN_BIT4 0x00000010
-+#define TITAN_BIT5 0x00000020
-+#define TITAN_BIT6 0x00000040
-+#define TITAN_BIT7 0x00000080
-+#define TITAN_BIT8 0x00000100
-+#define TITAN_BIT9 0x00000200
-+#define TITAN_BIT10 0x00000400
-+#define TITAN_BIT11 0x00000800
-+#define TITAN_BIT12 0x00001000
-+#define TITAN_BIT13 0x00002000
-+#define TITAN_BIT14 0x00004000
-+#define TITAN_BIT15 0x00008000
-+#define TITAN_BIT16 0x00010000
-+#define TITAN_BIT17 0x00020000
-+#define TITAN_BIT18 0x00040000
-+#define TITAN_BIT19 0x00080000
-+#define TITAN_BIT20 0x00100000
-+#define TITAN_BIT21 0x00200000
-+#define TITAN_BIT22 0x00400000
-+#define TITAN_BIT23 0x00800000
-+#define TITAN_BIT24 0x01000000
-+#define TITAN_BIT25 0x02000000
-+#define TITAN_BIT26 0x04000000
-+#define TITAN_BIT27 0x08000000
-+#define TITAN_BIT28 0x10000000
-+#define TITAN_BIT29 0x20000000
-+#define TITAN_BIT30 0x40000000
-+#define TITAN_BIT31 0x80000000
-+
-+/* Flow Control */
-+#define TITAN_GE_FC_NONE 0x0
-+#define TITAN_GE_FC_FULL 0x1
-+#define TITAN_GE_FC_TX_PAUSE 0x2
-+#define TITAN_GE_FC_RX_PAUSE 0x3
-+
-+/* Duplex Settings */
-+#define TITAN_GE_FULL_DUPLEX 0x1
-+#define TITAN_GE_HALF_DUPLEX 0x2
-+
-+/* Speed settings */
-+#define TITAN_GE_SPEED_1000 0x1
-+#define TITAN_GE_SPEED_100 0x2
-+#define TITAN_GE_SPEED_10 0x3
-+
-+/* Debugging info only */
-+#undef TITAN_DEBUG
-+
-+/* Keep the rings in the Titan's SSRAM */
-+#define TITAN_RX_RING_IN_SRAM
-+
-+#ifdef CONFIG_MIPS64
-+#define TITAN_GE_IE_MASK 0xfffffffffb001b64
-+#define TITAN_GE_IE_STATUS 0xfffffffffb001b60
-+#else
-+#define TITAN_GE_IE_MASK 0xfb001b64
-+#define TITAN_GE_IE_STATUS 0xfb001b60
-+#endif
-+
-+/* Support for Jumbo Frames */
-+#undef TITAN_GE_JUMBO_FRAMES
-+
-+/* Rx buffer size */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+#define TITAN_GE_JUMBO_BUFSIZE 9080
-+#else
-+#define TITAN_GE_STD_BUFSIZE 1580
-+#endif
-+
-+/*
-+ * Tx and Rx Interrupt Coalescing parameter. These values are
-+ * for 1 Ghz processor. Rx coalescing can be taken care of
-+ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
-+ * is not adaptive. Hence, these values need to be adjusted
-+ * based on load, CPU speed etc.
-+ */
-+#define TITAN_GE_RX_COAL 150
-+#define TITAN_GE_TX_COAL 300
-+
-+#if defined(__BIG_ENDIAN)
-+
-+/* Define the Rx descriptor */
-+typedef struct eth_rx_desc {
-+ u32 reserved; /* Unused */
-+ u32 buffer_addr; /* CPU buffer address */
-+ u32 cmd_sts; /* Command and Status */
-+ u32 buffer; /* XDMA buffer address */
-+} titan_ge_rx_desc;
-+
-+/* Define the Tx descriptor */
-+typedef struct eth_tx_desc {
-+ u16 cmd_sts; /* Command, Status and Buffer count */
-+ u16 buffer_len; /* Length of the buffer */
-+ u32 buffer_addr; /* Physical address of the buffer */
-+} titan_ge_tx_desc;
-+
-+#elif defined(__LITTLE_ENDIAN)
-+
-+/* Define the Rx descriptor */
-+typedef struct eth_rx_desc {
-+ u32 buffer_addr; /* CPU buffer address */
-+ u32 reserved; /* Unused */
-+ u32 buffer; /* XDMA buffer address */
-+ u32 cmd_sts; /* Command and Status */
-+} titan_ge_rx_desc;
-+
-+/* Define the Tx descriptor */
-+typedef struct eth_tx_desc {
-+ u32 buffer_addr; /* Physical address of the buffer */
-+ u16 buffer_len; /* Length of the buffer */
-+ u16 cmd_sts; /* Command, Status and Buffer count */
-+} titan_ge_tx_desc;
-+#endif
-+
-+/* Default Tx Queue Size */
-+#define TITAN_GE_TX_QUEUE 128
-+#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
-+
-+/* Default Rx Queue Size */
-+#define TITAN_GE_RX_QUEUE 64
-+#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
-+
-+/* Packet Structure */
-+typedef struct _pkt_info {
-+ unsigned int len;
-+ unsigned int cmd_sts;
-+ unsigned int buffer;
-+ struct sk_buff *skb;
-+ unsigned int checksum;
-+} titan_ge_packet;
-+
-+
-+#define PHYS_CNT 3
-+
-+/* Titan Port specific data structure */
-+typedef struct _eth_port_ctrl {
-+ unsigned int port_num;
-+ u8 port_mac_addr[6];
-+
-+ /* Rx descriptor pointers */
-+ int rx_curr_desc_q, rx_used_desc_q;
-+
-+ /* Tx descriptor pointers */
-+ int tx_curr_desc_q, tx_used_desc_q;
-+
-+ /* Rx descriptor area */
-+ volatile titan_ge_rx_desc *rx_desc_area;
-+ unsigned int rx_desc_area_size;
-+ struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE];
-+
-+ /* Tx Descriptor area */
-+ volatile titan_ge_tx_desc *tx_desc_area;
-+ unsigned int tx_desc_area_size;
-+ struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE];
-+
-+ /* Timeout task */
-+ struct work_struct tx_timeout_task;
-+
-+ /* DMA structures and handles */
-+ dma_addr_t tx_dma;
-+ dma_addr_t rx_dma;
-+ dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE];
-+
-+ /* Device lock */
-+ spinlock_t lock;
-+
-+ unsigned int tx_ring_skbs;
-+ unsigned int rx_ring_size;
-+ unsigned int tx_ring_size;
-+ unsigned int rx_ring_skbs;
-+
-+ struct net_device_stats stats;
-+
-+ /* Tx and Rx coalescing */
-+ unsigned long rx_int_coal;
-+ unsigned long tx_int_coal;
-+
-+ /* Threshold for replenishing the Rx and Tx rings */
-+ unsigned int tx_threshold;
-+ unsigned int rx_threshold;
-+
-+ /* NAPI work limit */
-+ unsigned int rx_work_limit;
-+} titan_ge_port_info;
-+
-+/* Titan specific constants */
-+#define TITAN_ETH_PORT_IRQ 3
-+
-+/* Max Rx buffer */
-+#define TITAN_GE_MAX_RX_BUFFER 65536
-+
-+/* Tx and Rx Error */
-+#define TITAN_GE_ERROR
-+
-+/* Rx Descriptor Command and Status */
-+
-+#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */
-+#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */
-+#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */
-+#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */
-+#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */
-+#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */
-+#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */
-+#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */
-+#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */
-+#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */
-+
-+/* Tx Descriptor Command */
-+#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */
-+#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */
-+
-+/* Return Status */
-+#define TITAN_OK 0x1 /* Good Status */
-+#define TITAN_ERROR 0x2 /* Error Status */
-+
-+/* MIB specific register offset */
-+#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */
-+#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */
-+#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */
-+#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */
-+#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */
-+
-+/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
-+#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040
-+#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050
-+#define TITAN_GE_MSTATX_RXFRAMES 0x0060
-+#define TITAN_GE_MSTATX_RXOCTETS 0x0070
-+#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080
-+#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090
-+#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0
-+#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0
-+#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0
-+#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0
-+#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0
-+#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0
-+#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100
-+#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110
-+#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120
-+#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130
-+#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140
-+#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150
-+#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160
-+#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170
-+#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180
-+#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190
-+#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0
-+#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0
-+#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0
-+#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0
-+#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0
-+#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0
-+#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200
-+#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210
-+#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220
-+#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230
-+#define TITAN_GE_MSTATX_HASHFILTERED 0x0240
-+#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250
-+#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260
-+#define TITAN_GE_MSTATX_TXOCTETS 0x0270
-+#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280
-+#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290
-+#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0
-+#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0
-+#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0
-+#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0
-+#define TITAN_GE_MSTATX_TXMACERROR 0x02E0
-+#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0
-+#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300
-+#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310
-+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320
-+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330
-+#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340
-+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350
-+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360
-+#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370
-+#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380
-+#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390
-+#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0
-+#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0
-+#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0
-+#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0
-+#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0
-+#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0
-+#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400
-+#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410
-+#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420
-+#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430
-+#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440
-+
-+/* Interrupt specific defines */
-+#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */
-+#define TITAN_GE_RESET 0x0004 /* Reset reg */
-+#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */
-+#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */
-+#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */
-+#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/
-+#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/
-+#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */
-+#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */
-+#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/
-+#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */
-+#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/
-+#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */
-+#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */
-+#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */
-+#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */
-+#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */
-+#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */
-+#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */
-+#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */
-+
-+/* Rx MAC defines */
-+#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */
-+#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */
-+#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */
-+#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */
-+#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */
-+#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */
-+#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */
-+
-+/* Tx MAC defines */
-+#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */
-+#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */
-+#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */
-+#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */
-+#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */
-+#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */
-+#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */
-+#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */
-+#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */
-+#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */
-+
-+/* GMII register */
-+#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */
-+#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */
-+#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */
-+
-+/* Tx and Rx XDMA defines */
-+#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */
-+#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */
-+#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */
-+#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */
-+#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */
-+#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */
-+#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */
-+#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */
-+
-+/* AFX (Address Filter Exact) register offsets for Slice 0 */
-+#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/
-+#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/
-+#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */
-+#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */
-+#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */
-+#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */
-+#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */
-+#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */
-+
-+/* Traffic Groomer block */
-+#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */
-+
-+#endif /* _TITAN_GE_H_ */
-+
-diff -urpNX dontdiff linux-2.6.12/drivers/net/titan_mdio.c linux_HEAD/drivers/net/titan_mdio.c
---- linux-2.6.12/drivers/net/titan_mdio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/titan_mdio.c 2004-10-20 17:57:59.000000000 +0200
-@@ -0,0 +1,217 @@
-+/*
-+ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
-+ * on the Titan. No support for the TBI as yet.
-+ *
-+ */
-+
-+#include "titan_mdio.h"
-+
-+#define MDIO_DEBUG
-+
-+/*
-+ * Local constants
-+ */
-+#define MAX_CLKA 1023
-+#define MAX_PHY_DEV 31
-+#define MAX_PHY_REG 31
-+#define WRITEADDRS_OPCODE 0x0
-+#define READ_OPCODE 0x2
-+#define WRITE_OPCODE 0x1
-+#define MAX_MDIO_POLL 100
-+
-+/*
-+ * Titan MDIO and SCMB registers
-+ */
-+#define TITAN_GE_SCMB_CONTROL 0x01c0 /* SCMB Control */
-+#define TITAN_GE_SCMB_CLKA 0x01c4 /* SCMB Clock A */
-+#define TITAN_GE_MDIO_COMMAND 0x01d0 /* MDIO Command */
-+#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO Device and Port addrs */
-+#define TITAN_GE_MDIO_DATA 0x01d8 /* MDIO Data */
-+#define TITAN_GE_MDIO_INTERRUPTS 0x01dC /* MDIO Interrupts */
-+
-+/*
-+ * Function to poll the MDIO
-+ */
-+static int titan_ge_mdio_poll(void)
-+{
-+ int i, val;
-+
-+ for (i = 0; i < MAX_MDIO_POLL; i++) {
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+
-+ if (!(val & 0x8000))
-+ return TITAN_GE_MDIO_GOOD;
-+ }
-+
-+ return TITAN_GE_MDIO_ERROR;
-+}
-+
-+
-+/*
-+ * Initialize and configure the MDIO
-+ */
-+int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
-+{
-+ unsigned long val;
-+
-+ /* Reset the SCMB and program into MDIO mode*/
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
-+
-+ /* CLK A */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
-+ val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
-+
-+ /* Preamble Suppresion */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+ val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+ /* MDIO mode */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+ val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+ return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Set the PHY address in indirect mode
-+ */
-+int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
-+{
-+ volatile unsigned long val;
-+
-+ /* Setup the PHY device */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+ /* Write the new address */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+ val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+ return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Read the MDIO register. This is what the individual parametes mean:
-+ *
-+ * dev_addr : PHY ID
-+ * reg_addr : register offset
-+ *
-+ * See the spec for the Titan MAC. We operate in the Direct Mode.
-+ */
-+
-+#define MAX_RETRIES 2
-+
-+int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
-+{
-+ volatile unsigned long val;
-+ int retries = 0;
-+
-+ /* Setup the PHY device */
-+
-+again:
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+ val |= 0x4000;
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+ udelay(30);
-+
-+ /* Issue the read command */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+ val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+ udelay(30);
-+
-+ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+ return TITAN_GE_MDIO_ERROR;
-+
-+ *pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
-+
-+ udelay(30);
-+
-+ if (val & 0x2) {
-+ if (retries == MAX_RETRIES)
-+ return TITAN_GE_MDIO_ERROR;
-+ else {
-+ retries++;
-+ goto again;
-+ }
-+ }
-+
-+ return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Write to the MDIO register
-+ *
-+ * dev_addr : PHY ID
-+ * reg_addr : register that needs to be written to
-+ *
-+ */
-+int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
-+{
-+ volatile unsigned long val;
-+
-+ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+ return TITAN_GE_MDIO_ERROR;
-+
-+ /* Setup the PHY device */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+ val |= 0x4000;
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+ udelay(30);
-+
-+ /* Setup the data to write */
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
-+
-+ udelay(30);
-+
-+ /* Issue the write command */
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+ val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
-+ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+ udelay(30);
-+
-+ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+ return TITAN_GE_MDIO_ERROR;
-+
-+ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
-+ if (val & 0x2)
-+ return TITAN_GE_MDIO_ERROR;
-+
-+ return TITAN_GE_MDIO_GOOD;
-+}
-+
-diff -urpNX dontdiff linux-2.6.12/drivers/net/titan_mdio.h linux_HEAD/drivers/net/titan_mdio.h
---- linux-2.6.12/drivers/net/titan_mdio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/net/titan_mdio.h 2004-10-20 17:57:59.000000000 +0200
-@@ -0,0 +1,56 @@
-+/*
-+ * MDIO used to interact with the PHY when using GMII/MII
-+ */
-+#ifndef _TITAN_MDIO_H
-+#define _TITAN_MDIO_H
-+
-+#include <linux/netdevice.h>
-+#include <linux/workqueue.h>
-+#include <linux/delay.h>
-+#include "titan_ge.h"
-+
-+
-+#define TITAN_GE_MDIO_ERROR (-9000)
-+#define TITAN_GE_MDIO_GOOD 0
-+
-+#define TITAN_GE_MDIO_BASE titan_ge_base
-+
-+#define TITAN_GE_MDIO_READ(offset) \
-+ *(volatile u32 *)(titan_ge_base + (offset))
-+
-+#define TITAN_GE_MDIO_WRITE(offset, data) \
-+ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
-+
-+
-+/* GMII specific registers */
-+#define TITAN_GE_MARVEL_PHY_ID 0x00
-+#define TITAN_PHY_AUTONEG_ADV 0x04
-+#define TITAN_PHY_LP_ABILITY 0x05
-+#define TITAN_GE_MDIO_MII_CTRL 0x09
-+#define TITAN_GE_MDIO_MII_EXTENDED 0x0f
-+#define TITAN_GE_MDIO_PHY_CTRL 0x10
-+#define TITAN_GE_MDIO_PHY_STATUS 0x11
-+#define TITAN_GE_MDIO_PHY_IE 0x12
-+#define TITAN_GE_MDIO_PHY_IS 0x13
-+#define TITAN_GE_MDIO_PHY_LED 0x18
-+#define TITAN_GE_MDIO_PHY_LED_OVER 0x19
-+#define PHY_ANEG_TIME_WAIT 45 /* 45 seconds wait time */
-+
-+/*
-+ * MDIO Config Structure
-+ */
-+typedef struct {
-+ unsigned int clka;
-+ int mdio_spre;
-+ int mdio_mode;
-+} titan_ge_mdio_config;
-+
-+/*
-+ * Function Prototypes
-+ */
-+int titan_ge_mdio_setup(titan_ge_mdio_config *);
-+int titan_ge_mdio_inaddrs(int, int);
-+int titan_ge_mdio_read(int, int, unsigned int *);
-+int titan_ge_mdio_write(int, int, unsigned int);
-+
-+#endif /* _TITAN_MDIO_H */
-diff -urpNX dontdiff linux-2.6.12/drivers/net/tulip/de2104x.c linux_HEAD/drivers/net/tulip/de2104x.c
---- linux-2.6.12/drivers/net/tulip/de2104x.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/tulip/de2104x.c 2005-04-30 15:33:45.000000000 +0200
-@@ -1787,10 +1787,15 @@ static void __init de21041_get_srom_info
- /* DEC now has a specification but early board makers
- just put the address in the first EEPROM locations. */
- /* This does memcmp(eedata, eedata+16, 8) */
-+
-+#ifndef CONFIG_MIPS_COBALT
-+
- for (i = 0; i < 8; i ++)
- if (ee_data[i] != ee_data[16+i])
- sa_offset = 20;
-
-+#endif
-+
- /* store MAC address */
- for (i = 0; i < 6; i ++)
- de->dev->dev_addr[i] = ee_data[i + sa_offset];
-diff -urpNX dontdiff linux-2.6.12/drivers/net/tulip/eeprom.c linux_HEAD/drivers/net/tulip/eeprom.c
---- linux-2.6.12/drivers/net/tulip/eeprom.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/tulip/eeprom.c 2005-02-21 22:17:44.000000000 +0100
-@@ -63,6 +63,22 @@ static struct eeprom_fixup eeprom_fixups
- */
- { 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 }
- },
-+ {"Cobalt Microserver", 0, 0x10, 0xE0, {0x1e00, /* 0 == controller #, 1e == offset */
-+ 0x0000, /* 0 == high offset, 0 == gap */
-+ 0x0800, /* Default Autoselect */
-+ 0x8001, /* 1 leaf, extended type, bogus len */
-+ 0x0003, /* Type 3 (MII), PHY #0 */
-+ 0x0400, /* 0 init instr, 4 reset instr */
-+ 0x0801, /* Set control mode, GP0 output */
-+ 0x0000, /* Drive GP0 Low (RST is active low) */
-+ 0x0800, /* control mode, GP0 input (undriven) */
-+ 0x0000, /* clear control mode */
-+ 0x7800, /* 100TX FDX + HDX, 10bT FDX + HDX */
-+ 0x01e0, /* Advertise all above */
-+ 0x5000, /* FDX all above */
-+ 0x1800, /* Set fast TTM in 100bt modes */
-+ 0x0000, /* PHY cannot be unplugged */
-+ }},
- {NULL}};
-
-
-diff -urpNX dontdiff linux-2.6.12/drivers/net/tulip/media.c linux_HEAD/drivers/net/tulip/media.c
---- linux-2.6.12/drivers/net/tulip/media.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/tulip/media.c 2005-07-01 12:09:50.000000000 +0200
-@@ -400,6 +400,9 @@ void tulip_select_media(struct net_devic
- }
-
- tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
-+
-+ udelay(1000);
-+
- return;
- }
-
-diff -urpNX dontdiff linux-2.6.12/drivers/net/tulip/tulip_core.c linux_HEAD/drivers/net/tulip/tulip_core.c
---- linux-2.6.12/drivers/net/tulip/tulip_core.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/net/tulip/tulip_core.c 2005-07-01 12:09:50.000000000 +0200
-@@ -1514,8 +1514,8 @@ static int __devinit tulip_init_one (str
- (PCI_SLOT(pdev->devfn) == 12))) {
- /* Cobalt MAC address in first EEPROM locations. */
- sa_offset = 0;
-- /* No media table either */
-- tp->flags &= ~HAS_MEDIA_TABLE;
-+ /* Ensure our media table fixup get's applied */
-+ memcpy(ee_data + 16, ee_data, 8);
- }
- #endif
- #ifdef CONFIG_GSC
-diff -urpNX dontdiff linux-2.6.12/drivers/pci/pci.ids linux_HEAD/drivers/pci/pci.ids
---- linux-2.6.12/drivers/pci/pci.ids 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pci/pci.ids 2005-07-07 11:22:54.000000000 +0200
-@@ -4500,6 +4500,8 @@
- 13c2 1011 Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card
- 13c2 1013 SATELCO Multimedia DVB
- 13c2 1102 Technotrend/Hauppauge DVB card rev2.1
-+ 9730 SAA9730 Integrated Multimedia and Peripheral Controller
-+ 9730 0000 Integrated Multimedia and Peripheral Controller
- 1132 Mitel Corp.
- # This is the new official company name. See disclaimer on www.eicon.com for details!
- 1133 Eicon Networks Corporation
-@@ -7665,7 +7667,8 @@
- 153c ANTAL Electronic
- 153d FILANET Corp
- 153e TECHWELL Inc
--153f MIPS DENMARK
-+153f MIPS Technologies, Inc.
-+ 0001 SOC-it 101 System Controller
- 1540 PROVIDEO MULTIMEDIA Co Ltd
- 1541 MACHONE Communications
- 1542 VIVID Technology Inc
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/Makefile linux_HEAD/drivers/pcmcia/Makefile
---- linux-2.6.12/drivers/pcmcia/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/Makefile 2005-02-17 21:50:00.000000000 +0100
-@@ -28,15 +28,21 @@ obj-$(CONFIG_HD64465_PCMCIA) += hd6446
- obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
- obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
- obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_core.o pxa2xx_cs.o
--obj-$(CONFIG_M32R_PCC) += m32r_pcc.o
--obj-$(CONFIG_M32R_CFC) += m32r_cfc.o
--obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o
- obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o
- obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o
-+obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o
-+
-+pcmcia_core-y += cistpl.o rsrc_mgr.o cs.o socket_sysfs.o
-+pcmcia_core-$(CONFIG_CARDBUS) += cardbus.o
-
- sa11xx_core-y += soc_common.o sa11xx_base.o
- pxa2xx_core-y += soc_common.o pxa2xx_base.o
-
-+sa1111_cs-y += sa1111_generic.o
-+sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o
-+sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o
-+sa1111_cs-$(CONFIG_SA1100_JORNADA720) += sa1100_jornada720.o
-+
- au1x00_ss-y += au1000_generic.o
- au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o
- au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o
-@@ -45,12 +51,7 @@ au1x00_ss-$(CONFIG_MIPS_DB1000) += au1
- au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o
- au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o
- au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o
--au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
--
--sa1111_cs-y += sa1111_generic.o
--sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o
--sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o
--sa1111_cs-$(CONFIG_SA1100_JORNADA720) += sa1100_jornada720.o
-+au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
-
- sa1100_cs-y += sa1100_generic.o
- sa1100_cs-$(CONFIG_SA1100_ASSABET) += sa1100_assabet.o
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/au1000_db1x00.c linux_HEAD/drivers/pcmcia/au1000_db1x00.c
---- linux-2.6.12/drivers/pcmcia/au1000_db1x00.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/au1000_db1x00.c 2005-07-10 12:28:27.000000000 +0200
-@@ -30,6 +30,7 @@
- *
- */
-
-+#include <linux/config.h>
- #include <linux/module.h>
- #include <linux/kernel.h>
- #include <linux/errno.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/au1000_generic.h linux_HEAD/drivers/pcmcia/au1000_generic.h
---- linux-2.6.12/drivers/pcmcia/au1000_generic.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/au1000_generic.h 2005-07-10 12:28:27.000000000 +0200
-@@ -22,6 +22,8 @@
- #define __ASM_AU1000_PCMCIA_H
-
- /* include the world */
-+#include <linux/config.h>
-+
- #include <pcmcia/version.h>
- #include <pcmcia/cs_types.h>
- #include <pcmcia/cs.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/au1000_pb1x00.c linux_HEAD/drivers/pcmcia/au1000_pb1x00.c
---- linux-2.6.12/drivers/pcmcia/au1000_pb1x00.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/au1000_pb1x00.c 2005-04-14 16:40:17.000000000 +0200
-@@ -21,6 +21,7 @@
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-+#include <linux/config.h>
- #include <linux/module.h>
- #include <linux/init.h>
- #include <linux/delay.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/au1000_xxs1500.c linux_HEAD/drivers/pcmcia/au1000_xxs1500.c
---- linux-2.6.12/drivers/pcmcia/au1000_xxs1500.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/au1000_xxs1500.c 2005-07-10 12:28:27.000000000 +0200
-@@ -23,11 +23,10 @@
- *
- * ########################################################################
- *
-- *
-+ *
- */
- #include <linux/module.h>
- #include <linux/init.h>
--#include <linux/config.h>
- #include <linux/delay.h>
- #include <linux/ioport.h>
- #include <linux/kernel.h>
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/vrc4171_card.c linux_HEAD/drivers/pcmcia/vrc4171_card.c
---- linux-2.6.12/drivers/pcmcia/vrc4171_card.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/vrc4171_card.c 2005-04-08 22:41:06.000000000 +0200
-@@ -1,7 +1,7 @@
- /*
- * vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services.
- *
-- * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
-+ * Copyright (C) 2003 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -26,6 +26,7 @@
- #include <linux/types.h>
-
- #include <asm/io.h>
-+#include <asm/vr41xx/vrc4171.h>
-
- #include <pcmcia/ss.h>
-
-@@ -47,6 +48,7 @@ MODULE_LICENSE("GPL");
-
- #define CARD_CONTROLLER_INDEX 0x03e0
- #define CARD_CONTROLLER_DATA 0x03e1
-+#define CARD_CONTROLLER_SIZE 2
- /* Power register */
- #define VPP_GET_VCC 0x01
- #define POWER_ENABLE 0x10
-@@ -67,40 +69,18 @@ MODULE_LICENSE("GPL");
- #define IRQPM_EN 0x08
- #define CLRPMIRQ 0x10
-
--#define INTERRUPT_STATUS 0x05fa
-- #define IRQ_A 0x02
-- #define IRQ_B 0x04
--
--#define CONFIGURATION1 0x05fe
-- #define SLOTB_CONFIG 0xc000
-- #define SLOTB_NONE 0x0000
-- #define SLOTB_PCCARD 0x4000
-- #define SLOTB_CF 0x8000
-- #define SLOTB_FLASHROM 0xc000
+-#
+-# Machine selection
+-#
+-# CONFIG_MIPS_MTX1 is not set
+-# CONFIG_MIPS_BOSPORUS is not set
+-# CONFIG_MIPS_PB1000 is not set
+-# CONFIG_MIPS_PB1100 is not set
+-# CONFIG_MIPS_PB1500 is not set
+-# CONFIG_MIPS_PB1550 is not set
+-# CONFIG_MIPS_PB1200 is not set
+-# CONFIG_MIPS_DB1000 is not set
+-# CONFIG_MIPS_DB1100 is not set
+-# CONFIG_MIPS_DB1500 is not set
+-# CONFIG_MIPS_DB1550 is not set
+-# CONFIG_MIPS_DB1200 is not set
+-# CONFIG_MIPS_MIRAGE is not set
+-# CONFIG_MIPS_COBALT is not set
+-# CONFIG_MACH_DECSTATION is not set
+-# CONFIG_MIPS_EV64120 is not set
+-# CONFIG_MIPS_EV96100 is not set
+-# CONFIG_MIPS_IVR is not set
+-# CONFIG_MIPS_ITE8172 is not set
+-# CONFIG_MACH_JAZZ is not set
+-# CONFIG_LASAT is not set
+-# CONFIG_MIPS_ATLAS is not set
+-# CONFIG_MIPS_MALTA is not set
+-# CONFIG_MIPS_SEAD is not set
+-# CONFIG_MIPS_SIM is not set
+-# CONFIG_MOMENCO_JAGUAR_ATX is not set
+-# CONFIG_MOMENCO_OCELOT is not set
+-# CONFIG_MOMENCO_OCELOT_3 is not set
+-# CONFIG_MOMENCO_OCELOT_C is not set
+-# CONFIG_MOMENCO_OCELOT_G is not set
+-# CONFIG_MIPS_XXS1500 is not set
+-# CONFIG_PNX8550_V2PCI is not set
+-# CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+-# CONFIG_DDB5477 is not set
+-CONFIG_MACH_VR41XX=y
+-# CONFIG_PMC_YOSEMITE is not set
+-# CONFIG_QEMU is not set
+-# CONFIG_SGI_IP22 is not set
+-# CONFIG_SGI_IP27 is not set
+-# CONFIG_SGI_IP32 is not set
+-# CONFIG_SIBYTE_SWARM is not set
+-# CONFIG_SIBYTE_SENTOSA is not set
+-# CONFIG_SIBYTE_RHONE is not set
+-# CONFIG_SIBYTE_CARMEL is not set
+-# CONFIG_SIBYTE_PTSWARM is not set
+-# CONFIG_SIBYTE_LITTLESUR is not set
+-# CONFIG_SIBYTE_CRHINE is not set
+-# CONFIG_SIBYTE_CRHONE is not set
+-# CONFIG_SNI_RM200_PCI is not set
+-# CONFIG_TOSHIBA_JMR3927 is not set
+-# CONFIG_TOSHIBA_RBTX4927 is not set
+-# CONFIG_TOSHIBA_RBTX4938 is not set
+-# CONFIG_CASIO_E55 is not set
+-# CONFIG_IBM_WORKPAD is not set
+-# CONFIG_NEC_CMBVR4133 is not set
+-CONFIG_TANBAC_TB022X=y
+-# CONFIG_TANBAC_TB0226 is not set
+-CONFIG_TANBAC_TB0287=y
+-# CONFIG_VICTOR_MPC30X is not set
+-# CONFIG_ZAO_CAPCELLA is not set
+-CONFIG_PCI_VR41XX=y
+-# CONFIG_VRC4173 is not set
+-CONFIG_RWSEM_GENERIC_SPINLOCK=y
+-CONFIG_GENERIC_CALIBRATE_DELAY=y
+-CONFIG_DMA_NONCOHERENT=y
+-CONFIG_DMA_NEED_PCI_MAP_STATE=y
+-# CONFIG_CPU_BIG_ENDIAN is not set
+-CONFIG_CPU_LITTLE_ENDIAN=y
+-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+-CONFIG_IRQ_CPU=y
+-CONFIG_MIPS_L1_CACHE_SHIFT=5
+-
+-#
+-# CPU selection
+-#
+-# CONFIG_CPU_MIPS32_R1 is not set
+-# CONFIG_CPU_MIPS32_R2 is not set
+-# CONFIG_CPU_MIPS64_R1 is not set
+-# CONFIG_CPU_MIPS64_R2 is not set
+-# CONFIG_CPU_R3000 is not set
+-# CONFIG_CPU_TX39XX is not set
+-CONFIG_CPU_VR41XX=y
+-# CONFIG_CPU_R4300 is not set
+-# CONFIG_CPU_R4X00 is not set
+-# CONFIG_CPU_TX49XX is not set
+-# CONFIG_CPU_R5000 is not set
+-# CONFIG_CPU_R5432 is not set
+-# CONFIG_CPU_R6000 is not set
+-# CONFIG_CPU_NEVADA is not set
+-# CONFIG_CPU_R8000 is not set
+-# CONFIG_CPU_R10000 is not set
+-# CONFIG_CPU_RM7000 is not set
+-# CONFIG_CPU_RM9000 is not set
+-# CONFIG_CPU_SB1 is not set
+-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+-
+-#
+-# Kernel type
+-#
+-CONFIG_32BIT=y
+-# CONFIG_64BIT is not set
+-CONFIG_PAGE_SIZE_4KB=y
+-# CONFIG_PAGE_SIZE_8KB is not set
+-# CONFIG_PAGE_SIZE_16KB is not set
+-# CONFIG_PAGE_SIZE_64KB is not set
+-# CONFIG_MIPS_MT is not set
+-# CONFIG_CPU_ADVANCED is not set
+-CONFIG_CPU_HAS_SYNC=y
+-CONFIG_GENERIC_HARDIRQS=y
+-CONFIG_GENERIC_IRQ_PROBE=y
+-CONFIG_ARCH_FLATMEM_ENABLE=y
+-CONFIG_SELECT_MEMORY_MODEL=y
+-CONFIG_FLATMEM_MANUAL=y
+-# CONFIG_DISCONTIGMEM_MANUAL is not set
+-# CONFIG_SPARSEMEM_MANUAL is not set
+-CONFIG_FLATMEM=y
+-CONFIG_FLAT_NODE_MEM_MAP=y
+-# CONFIG_SPARSEMEM_STATIC is not set
+-CONFIG_SPLIT_PTLOCK_CPUS=4
+-CONFIG_PREEMPT_NONE=y
+-# CONFIG_PREEMPT_VOLUNTARY is not set
+-# CONFIG_PREEMPT is not set
+-
+-#
+-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+-#
+-CONFIG_HW_HAS_PCI=y
+-CONFIG_PCI=y
+-# CONFIG_PCI_LEGACY_PROC is not set
+-CONFIG_MMU=y
+-
+-#
+-# PCCARD (PCMCIA/CardBus) support
+-#
+-# CONFIG_PCCARD is not set
+-
+-#
+-# PCI Hotplug Support
+-#
+-# CONFIG_HOTPLUG_PCI is not set
+-
+-#
+-# Executable file formats
+-#
+-CONFIG_BINFMT_ELF=y
+-# CONFIG_BINFMT_MISC is not set
+-CONFIG_TRAD_SIGNALS=y
+-
+-#
+-# Networking
+-#
+-CONFIG_NET=y
+-
+-#
+-# Networking options
+-#
+-CONFIG_PACKET=y
+-# CONFIG_PACKET_MMAP is not set
+-CONFIG_UNIX=y
+-CONFIG_XFRM=y
+-CONFIG_XFRM_USER=m
+-# CONFIG_NET_KEY is not set
+-CONFIG_INET=y
+-CONFIG_IP_MULTICAST=y
+-CONFIG_IP_ADVANCED_ROUTER=y
+-CONFIG_ASK_IP_FIB_HASH=y
+-# CONFIG_IP_FIB_TRIE is not set
+-CONFIG_IP_FIB_HASH=y
+-CONFIG_IP_MULTIPLE_TABLES=y
+-CONFIG_IP_ROUTE_MULTIPATH=y
+-# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
+-CONFIG_IP_ROUTE_VERBOSE=y
+-CONFIG_IP_PNP=y
+-# CONFIG_IP_PNP_DHCP is not set
+-CONFIG_IP_PNP_BOOTP=y
+-# CONFIG_IP_PNP_RARP is not set
+-CONFIG_NET_IPIP=m
+-CONFIG_NET_IPGRE=m
+-# CONFIG_NET_IPGRE_BROADCAST is not set
+-# CONFIG_IP_MROUTE is not set
+-# CONFIG_ARPD is not set
+-CONFIG_SYN_COOKIES=y
+-# CONFIG_INET_AH is not set
+-# CONFIG_INET_ESP is not set
+-# CONFIG_INET_IPCOMP is not set
+-CONFIG_INET_TUNNEL=m
+-CONFIG_INET_DIAG=y
+-CONFIG_INET_TCP_DIAG=y
+-CONFIG_TCP_CONG_ADVANCED=y
+-
+-#
+-# TCP congestion control
+-#
+-CONFIG_TCP_CONG_BIC=y
+-CONFIG_TCP_CONG_WESTWOOD=m
+-CONFIG_TCP_CONG_HTCP=m
+-# CONFIG_TCP_CONG_HSTCP is not set
+-# CONFIG_TCP_CONG_HYBLA is not set
+-# CONFIG_TCP_CONG_VEGAS is not set
+-# CONFIG_TCP_CONG_SCALABLE is not set
+-# CONFIG_IPV6 is not set
+-# CONFIG_NETFILTER is not set
+-
+-#
+-# DCCP Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_IP_DCCP is not set
+-
+-#
+-# SCTP Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_IP_SCTP is not set
+-# CONFIG_ATM is not set
+-# CONFIG_BRIDGE is not set
+-# CONFIG_VLAN_8021Q is not set
+-# CONFIG_DECNET is not set
+-# CONFIG_LLC2 is not set
+-# CONFIG_IPX is not set
+-# CONFIG_ATALK is not set
+-# CONFIG_X25 is not set
+-# CONFIG_LAPB is not set
+-# CONFIG_NET_DIVERT is not set
+-# CONFIG_ECONET is not set
+-# CONFIG_WAN_ROUTER is not set
+-# CONFIG_NET_SCHED is not set
+-# CONFIG_NET_CLS_ROUTE is not set
+-
+-#
+-# Network testing
+-#
+-# CONFIG_NET_PKTGEN is not set
+-# CONFIG_HAMRADIO is not set
+-# CONFIG_IRDA is not set
+-# CONFIG_BT is not set
+-# CONFIG_IEEE80211 is not set
+-
+-#
+-# Device Drivers
+-#
+-
+-#
+-# Generic Driver Options
+-#
+-CONFIG_STANDALONE=y
+-CONFIG_PREVENT_FIRMWARE_BUILD=y
+-# CONFIG_FW_LOADER is not set
+-
+-#
+-# Connector - unified userspace <-> kernelspace linker
+-#
+-# CONFIG_CONNECTOR is not set
+-
+-#
+-# Memory Technology Devices (MTD)
+-#
+-# CONFIG_MTD is not set
+-
+-#
+-# Parallel port support
+-#
+-# CONFIG_PARPORT is not set
+-
+-#
+-# Plug and Play support
+-#
+-
+-#
+-# Block devices
+-#
+-# CONFIG_BLK_CPQ_DA is not set
+-# CONFIG_BLK_CPQ_CISS_DA is not set
+-# CONFIG_BLK_DEV_DAC960 is not set
+-# CONFIG_BLK_DEV_UMEM is not set
+-# CONFIG_BLK_DEV_COW_COMMON is not set
+-CONFIG_BLK_DEV_LOOP=m
+-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+-CONFIG_BLK_DEV_NBD=m
+-# CONFIG_BLK_DEV_SX8 is not set
+-# CONFIG_BLK_DEV_UB is not set
+-CONFIG_BLK_DEV_RAM=y
+-CONFIG_BLK_DEV_RAM_COUNT=16
+-CONFIG_BLK_DEV_RAM_SIZE=4096
+-# CONFIG_BLK_DEV_INITRD is not set
+-# CONFIG_LBD is not set
+-# CONFIG_BLK_DEV_IO_TRACE is not set
+-# CONFIG_CDROM_PKTCDVD is not set
+-
+-#
+-# IO Schedulers
+-#
+-CONFIG_IOSCHED_NOOP=y
+-CONFIG_IOSCHED_AS=y
+-CONFIG_IOSCHED_DEADLINE=y
+-CONFIG_IOSCHED_CFQ=y
+-CONFIG_DEFAULT_AS=y
+-# CONFIG_DEFAULT_DEADLINE is not set
+-# CONFIG_DEFAULT_CFQ is not set
+-# CONFIG_DEFAULT_NOOP is not set
+-CONFIG_DEFAULT_IOSCHED="anticipatory"
+-# CONFIG_ATA_OVER_ETH is not set
+-
+-#
+-# ATA/ATAPI/MFM/RLL support
+-#
+-CONFIG_IDE=y
+-CONFIG_BLK_DEV_IDE=y
+-
+-#
+-# Please see Documentation/ide.txt for help/info on IDE drives
+-#
+-# CONFIG_BLK_DEV_IDE_SATA is not set
+-CONFIG_BLK_DEV_IDEDISK=y
+-# CONFIG_IDEDISK_MULTI_MODE is not set
+-# CONFIG_BLK_DEV_IDECD is not set
+-# CONFIG_BLK_DEV_IDETAPE is not set
+-# CONFIG_BLK_DEV_IDEFLOPPY is not set
+-# CONFIG_BLK_DEV_IDESCSI is not set
+-# CONFIG_IDE_TASK_IOCTL is not set
+-
+-#
+-# IDE chipset support/bugfixes
+-#
+-CONFIG_IDE_GENERIC=y
+-CONFIG_BLK_DEV_IDEPCI=y
+-# CONFIG_IDEPCI_SHARE_IRQ is not set
+-# CONFIG_BLK_DEV_OFFBOARD is not set
+-# CONFIG_BLK_DEV_GENERIC is not set
+-# CONFIG_BLK_DEV_OPTI621 is not set
+-CONFIG_BLK_DEV_IDEDMA_PCI=y
+-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+-# CONFIG_IDEDMA_PCI_AUTO is not set
+-# CONFIG_BLK_DEV_AEC62XX is not set
+-# CONFIG_BLK_DEV_ALI15X3 is not set
+-# CONFIG_BLK_DEV_AMD74XX is not set
+-# CONFIG_BLK_DEV_CMD64X is not set
+-# CONFIG_BLK_DEV_TRIFLEX is not set
+-# CONFIG_BLK_DEV_CY82C693 is not set
+-# CONFIG_BLK_DEV_CS5520 is not set
+-# CONFIG_BLK_DEV_CS5530 is not set
+-# CONFIG_BLK_DEV_HPT34X is not set
+-# CONFIG_BLK_DEV_HPT366 is not set
+-# CONFIG_BLK_DEV_SC1200 is not set
+-# CONFIG_BLK_DEV_PIIX is not set
+-# CONFIG_BLK_DEV_IT821X is not set
+-# CONFIG_BLK_DEV_NS87415 is not set
+-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+-# CONFIG_BLK_DEV_SVWKS is not set
+-CONFIG_BLK_DEV_SIIMAGE=y
+-# CONFIG_BLK_DEV_SLC90E66 is not set
+-# CONFIG_BLK_DEV_TRM290 is not set
+-# CONFIG_BLK_DEV_VIA82CXXX is not set
+-# CONFIG_IDE_ARM is not set
+-CONFIG_BLK_DEV_IDEDMA=y
+-# CONFIG_IDEDMA_IVB is not set
+-# CONFIG_IDEDMA_AUTO is not set
+-# CONFIG_BLK_DEV_HD is not set
+-
+-#
+-# SCSI device support
+-#
+-# CONFIG_RAID_ATTRS is not set
+-CONFIG_SCSI=y
+-CONFIG_SCSI_PROC_FS=y
+-
+-#
+-# SCSI support type (disk, tape, CD-ROM)
+-#
+-CONFIG_BLK_DEV_SD=y
+-# CONFIG_CHR_DEV_ST is not set
+-# CONFIG_CHR_DEV_OSST is not set
+-# CONFIG_BLK_DEV_SR is not set
+-# CONFIG_CHR_DEV_SG is not set
+-# CONFIG_CHR_DEV_SCH is not set
+-
+-#
+-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+-#
+-# CONFIG_SCSI_MULTI_LUN is not set
+-# CONFIG_SCSI_CONSTANTS is not set
+-# CONFIG_SCSI_LOGGING is not set
+-
+-#
+-# SCSI Transport Attributes
+-#
+-# CONFIG_SCSI_SPI_ATTRS is not set
+-# CONFIG_SCSI_FC_ATTRS is not set
+-# CONFIG_SCSI_ISCSI_ATTRS is not set
+-# CONFIG_SCSI_SAS_ATTRS is not set
+-
+-#
+-# SCSI Transport Layers
+-#
+-# CONFIG_SAS_CLASS is not set
+-
+-#
+-# SCSI low-level drivers
+-#
+-# CONFIG_ISCSI_TCP is not set
+-# CONFIG_SCSI_ARCMSR is not set
+-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+-# CONFIG_SCSI_3W_9XXX is not set
+-# CONFIG_SCSI_ACARD is not set
+-# CONFIG_SCSI_AACRAID is not set
+-# CONFIG_SCSI_AIC7XXX is not set
+-# CONFIG_SCSI_AIC7XXX_OLD is not set
+-# CONFIG_SCSI_AIC79XX is not set
+-# CONFIG_SCSI_DPT_I2O is not set
+-# CONFIG_MEGARAID_NEWGEN is not set
+-# CONFIG_MEGARAID_LEGACY is not set
+-# CONFIG_MEGARAID_SAS is not set
+-# CONFIG_SCSI_SATA is not set
+-# CONFIG_SCSI_DMX3191D is not set
+-# CONFIG_SCSI_FUTURE_DOMAIN is not set
+-# CONFIG_SCSI_IPS is not set
+-# CONFIG_SCSI_INITIO is not set
+-# CONFIG_SCSI_INIA100 is not set
+-# CONFIG_SCSI_SYM53C8XX_2 is not set
+-# CONFIG_SCSI_IPR is not set
+-# CONFIG_SCSI_QLOGIC_FC is not set
+-# CONFIG_SCSI_QLOGIC_1280 is not set
+-CONFIG_SCSI_QLA2XXX=y
+-# CONFIG_SCSI_QLA21XX is not set
+-# CONFIG_SCSI_QLA22XX is not set
+-# CONFIG_SCSI_QLA2300 is not set
+-# CONFIG_SCSI_QLA2322 is not set
+-# CONFIG_SCSI_QLA6312 is not set
+-# CONFIG_SCSI_QLA24XX is not set
+-# CONFIG_SCSI_LPFC is not set
+-# CONFIG_SCSI_DC395x is not set
+-# CONFIG_SCSI_DC390T is not set
+-# CONFIG_SCSI_NSP32 is not set
+-# CONFIG_SCSI_DEBUG is not set
+-
+-#
+-# Multi-device support (RAID and LVM)
+-#
+-# CONFIG_MD is not set
+-
+-#
+-# Fusion MPT device support
+-#
+-# CONFIG_FUSION is not set
+-# CONFIG_FUSION_SPI is not set
+-# CONFIG_FUSION_FC is not set
+-# CONFIG_FUSION_SAS is not set
+-
+-#
+-# IEEE 1394 (FireWire) support
+-#
+-CONFIG_IEEE1394=m
+-
+-#
+-# Subsystem Options
+-#
+-# CONFIG_IEEE1394_VERBOSEDEBUG is not set
+-# CONFIG_IEEE1394_OUI_DB is not set
+-CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y
+-CONFIG_IEEE1394_CONFIG_ROM_IP1394=y
+-# CONFIG_IEEE1394_EXPORT_FULL_API is not set
+-
+-#
+-# Device Drivers
+-#
+-
+-#
+-# Texas Instruments PCILynx requires I2C
+-#
+-CONFIG_IEEE1394_OHCI1394=m
+-
+-#
+-# Protocol Drivers
+-#
+-CONFIG_IEEE1394_VIDEO1394=m
+-CONFIG_IEEE1394_SBP2=m
+-# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
+-CONFIG_IEEE1394_ETH1394=m
+-CONFIG_IEEE1394_DV1394=m
+-CONFIG_IEEE1394_RAWIO=m
+-CONFIG_IEEE1394_CMP=m
+-CONFIG_IEEE1394_AMDTP=m
+-
+-#
+-# I2O device support
+-#
+-# CONFIG_I2O is not set
+-
+-#
+-# Network device support
+-#
+-CONFIG_NETDEVICES=y
+-CONFIG_DUMMY=m
+-# CONFIG_BONDING is not set
+-# CONFIG_EQUALIZER is not set
+-# CONFIG_TUN is not set
+-
+-#
+-# ARCnet devices
+-#
+-# CONFIG_ARCNET is not set
+-
+-#
+-# PHY device support
+-#
+-# CONFIG_PHYLIB is not set
+-
+-#
+-# Ethernet (10 or 100Mbit)
+-#
+-CONFIG_NET_ETHERNET=y
+-CONFIG_MII=y
+-# CONFIG_HAPPYMEAL is not set
+-# CONFIG_SUNGEM is not set
+-# CONFIG_CASSINI is not set
+-# CONFIG_NET_VENDOR_3COM is not set
+-
+-#
+-# Tulip family network device support
+-#
+-# CONFIG_NET_TULIP is not set
+-# CONFIG_HP100 is not set
+-# CONFIG_NET_PCI is not set
+-
+-#
+-# Ethernet (1000 Mbit)
+-#
+-# CONFIG_ACENIC is not set
+-# CONFIG_DL2K is not set
+-# CONFIG_E1000 is not set
+-# CONFIG_NS83820 is not set
+-# CONFIG_HAMACHI is not set
+-# CONFIG_YELLOWFIN is not set
+-CONFIG_R8169=y
+-# CONFIG_R8169_NAPI is not set
+-# CONFIG_SIS190 is not set
+-# CONFIG_SKGE is not set
+-# CONFIG_SKY2 is not set
+-# CONFIG_SK98LIN is not set
+-# CONFIG_TIGON3 is not set
+-# CONFIG_BNX2 is not set
+-
+-#
+-# Ethernet (10000 Mbit)
+-#
+-# CONFIG_CHELSIO_T1 is not set
+-# CONFIG_IXGB is not set
+-# CONFIG_S2IO is not set
+-
+-#
+-# Token Ring devices
+-#
+-# CONFIG_TR is not set
+-
+-#
+-# Wireless LAN (non-hamradio)
+-#
+-# CONFIG_NET_RADIO is not set
+-# CONFIG_HOSTAP is not set
+-
+-#
+-# Wan interfaces
+-#
+-# CONFIG_WAN is not set
+-# CONFIG_FDDI is not set
+-# CONFIG_HIPPI is not set
+-# CONFIG_PPP is not set
+-# CONFIG_SLIP is not set
+-# CONFIG_NET_FC is not set
+-# CONFIG_SHAPER is not set
+-# CONFIG_NETCONSOLE is not set
+-# CONFIG_KGDBOE is not set
+-# CONFIG_NETPOLL is not set
+-# CONFIG_NETPOLL_RX is not set
+-# CONFIG_NETPOLL_TRAP is not set
+-# CONFIG_NET_POLL_CONTROLLER is not set
+-
+-#
+-# ISDN subsystem
+-#
+-# CONFIG_ISDN is not set
+-
+-#
+-# Telephony Support
+-#
+-# CONFIG_PHONE is not set
-
--#define CARD_CONTROLLER_START CARD_CONTROLLER_INDEX
--#define CARD_CONTROLLER_END CARD_CONTROLLER_DATA
+-#
+-# Input device support
+-#
+-CONFIG_INPUT=y
-
- #define IO_MAX_MAPS 2
- #define MEM_MAX_MAPS 5
-
--typedef enum {
-+enum {
- SLOT_PROBE = 0,
- SLOT_NOPROBE_IO,
- SLOT_NOPROBE_MEM,
-- SLOT_NOPROBE_ALL,
-- SLOT_INITIALIZED,
--} vrc4171_slot_t;
+-#
+-# Userland interfaces
+-#
+-# CONFIG_INPUT_MOUSEDEV is not set
+-# CONFIG_INPUT_JOYDEV is not set
+-# CONFIG_INPUT_TSDEV is not set
+-# CONFIG_INPUT_EVDEV is not set
+-# CONFIG_INPUT_EVBUG is not set
-
--typedef enum {
-- SLOTB_IS_NONE,
-- SLOTB_IS_PCCARD,
-- SLOTB_IS_CF,
-- SLOTB_IS_FLASHROM,
--} vrc4171_slotb_t;
-+ SLOT_NOPROBE_ALL
-+};
-
- typedef struct vrc4171_socket {
-- vrc4171_slot_t slot;
-+ int noprobe;
- struct pcmcia_socket pcmcia_socket;
- char name[24];
- int csc_irq;
-@@ -108,65 +88,10 @@ typedef struct vrc4171_socket {
- } vrc4171_socket_t;
-
- static vrc4171_socket_t vrc4171_sockets[CARD_MAX_SLOTS];
--static vrc4171_slotb_t vrc4171_slotb = SLOTB_IS_NONE;
--static char vrc4171_card_name[] = "NEC VRC4171 Card Controller";
-+static int vrc4171_slotb = SLOTB_IS_NONE;
- static unsigned int vrc4171_irq;
- static uint16_t vrc4171_irq_mask = 0xdeb8;
-
--static struct resource vrc4171_card_resource[3] = {
-- { .name = vrc4171_card_name,
-- .start = CARD_CONTROLLER_START,
-- .end = CARD_CONTROLLER_END,
-- .flags = IORESOURCE_IO, },
-- { .name = vrc4171_card_name,
-- .start = INTERRUPT_STATUS,
-- .end = INTERRUPT_STATUS,
-- .flags = IORESOURCE_IO, },
-- { .name = vrc4171_card_name,
-- .start = CONFIGURATION1,
-- .end = CONFIGURATION1,
-- .flags = IORESOURCE_IO, },
--};
+-#
+-# Input Device Drivers
+-#
+-# CONFIG_INPUT_KEYBOARD is not set
+-# CONFIG_INPUT_MOUSE is not set
+-# CONFIG_INPUT_JOYSTICK is not set
+-# CONFIG_INPUT_TOUCHSCREEN is not set
+-# CONFIG_INPUT_MISC is not set
-
--static struct platform_device vrc4171_card_device = {
-- .name = vrc4171_card_name,
-- .id = 0,
-- .num_resources = 3,
-- .resource = vrc4171_card_resource,
--};
+-#
+-# Hardware I/O ports
+-#
+-# CONFIG_SERIO is not set
+-# CONFIG_GAMEPORT is not set
-
--static inline uint16_t vrc4171_get_irq_status(void)
--{
-- return inw(INTERRUPT_STATUS);
--}
+-#
+-# Character devices
+-#
+-CONFIG_VT=y
+-CONFIG_VT_CONSOLE=y
+-CONFIG_HW_CONSOLE=y
+-# CONFIG_SERIAL_NONSTANDARD is not set
-
--static inline void vrc4171_set_multifunction_pin(vrc4171_slotb_t config)
--{
-- uint16_t config1;
+-#
+-# Serial drivers
+-#
+-# CONFIG_SERIAL_8250 is not set
-
-- config1 = inw(CONFIGURATION1);
-- config1 &= ~SLOTB_CONFIG;
+-#
+-# Non-8250 serial port support
+-#
+-CONFIG_SERIAL_CORE=y
+-CONFIG_SERIAL_CORE_CONSOLE=y
+-CONFIG_SERIAL_VR41XX=y
+-CONFIG_SERIAL_VR41XX_CONSOLE=y
+-# CONFIG_SERIAL_JSM is not set
+-CONFIG_UNIX98_PTYS=y
+-CONFIG_LEGACY_PTYS=y
+-CONFIG_LEGACY_PTY_COUNT=256
-
-- switch (config) {
-- case SLOTB_IS_NONE:
-- config1 |= SLOTB_NONE;
-- break;
-- case SLOTB_IS_PCCARD:
-- config1 |= SLOTB_PCCARD;
-- break;
-- case SLOTB_IS_CF:
-- config1 |= SLOTB_CF;
-- break;
-- case SLOTB_IS_FLASHROM:
-- config1 |= SLOTB_FLASHROM;
-- break;
-- default:
-- break;
-- }
+-#
+-# IPMI
+-#
+-# CONFIG_IPMI_HANDLER is not set
-
-- outw(config1, CONFIGURATION1);
--}
+-#
+-# Watchdog Cards
+-#
+-# CONFIG_WATCHDOG is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
+-# CONFIG_RTC_VR41XX is not set
+-# CONFIG_DTLK is not set
+-# CONFIG_R3964 is not set
+-# CONFIG_APPLICOM is not set
+-# CONFIG_TANBAC_TB0219 is not set
-
- static inline uint8_t exca_read_byte(int slot, uint8_t index)
- {
- if (slot == CARD_SLOTB)
-@@ -356,9 +281,9 @@ static int pccard_get_socket(struct pcmc
- if (cscint & I365_CSC_STSCHG)
- state->flags |= SS_STSCHG;
- } else {
-- if (cscint & I365_CSC_BVD1)
-+ if (cscint & I365_CSC_BVD1)
- state->csc_mask |= SS_BATDEAD;
-- if (cscint & I365_CSC_BVD2)
-+ if (cscint & I365_CSC_BVD2)
- state->csc_mask |= SS_BATWARN;
- }
- if (cscint & I365_CSC_READY)
-@@ -495,9 +420,9 @@ static int pccard_set_mem_map(struct pcm
-
- if (sock == NULL || sock->sock >= CARD_MAX_SLOTS ||
- mem == NULL || mem->map >= MEM_MAX_MAPS ||
-- mem->res->start < CARD_MEM_START || mem->res->start > CARD_MEM_END ||
-- mem->res->end < CARD_MEM_START || mem->res->end > CARD_MEM_END ||
-- mem->res->start > mem->res->end ||
-+ mem->sys_start < CARD_MEM_START || mem->sys_start > CARD_MEM_END ||
-+ mem->sys_stop < CARD_MEM_START || mem->sys_stop > CARD_MEM_END ||
-+ mem->sys_start > mem->sys_stop ||
- mem->card_start > CARD_MAX_MEM_OFFSET ||
- mem->speed > CARD_MAX_MEM_SPEED)
- return -EINVAL;
-@@ -511,12 +436,12 @@ static int pccard_set_mem_map(struct pcm
- exca_write_byte(slot, I365_ADDRWIN, addrwin);
- }
-
-- start = (mem->res->start >> 12) & 0x3fff;
-+ start = (mem->sys_start >> 12) & 0x3fff;
- if (mem->flags & MAP_16BIT)
- start |= I365_MEM_16BIT;
- exca_write_word(slot, I365_MEM(map)+I365_W_START, start);
-
-- stop = (mem->res->end >> 12) & 0x3fff;
-+ stop = (mem->sys_stop >> 12) & 0x3fff;
- switch (mem->speed) {
- case 0:
- break;
-@@ -593,7 +518,7 @@ static irqreturn_t pccard_interrupt(int
- status = vrc4171_get_irq_status();
- if (status & IRQ_A) {
- socket = &vrc4171_sockets[CARD_SLOTA];
-- if (socket->slot == SLOT_INITIALIZED) {
-+ if (socket->noprobe == SLOT_PROBE) {
- if (status & (1 << socket->csc_irq)) {
- events = get_events(CARD_SLOTA);
- if (events != 0) {
-@@ -606,7 +531,7 @@ static irqreturn_t pccard_interrupt(int
-
- if (status & IRQ_B) {
- socket = &vrc4171_sockets[CARD_SLOTB];
-- if (socket->slot == SLOT_INITIALIZED) {
-+ if (socket->noprobe == SLOT_PROBE) {
- if (status & (1 << socket->csc_irq)) {
- events = get_events(CARD_SLOTB);
- if (events != 0) {
-@@ -633,71 +558,63 @@ static inline void reserve_using_irq(int
- vrc4171_irq_mask &= ~(1 << irq);
- }
-
--static int __devinit vrc4171_add_sockets(void)
-+static int __devinit vrc4171_add_socket(int slot)
- {
- vrc4171_socket_t *socket;
-- int slot, retval;
-+ int retval;
-
-- for (slot = 0; slot < CARD_MAX_SLOTS; slot++) {
-- if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE)
-- continue;
-+ if (slot >= CARD_MAX_SLOTS)
-+ return -EINVAL;
-
-- socket = &vrc4171_sockets[slot];
-- if (socket->slot != SLOT_PROBE) {
-- uint8_t addrwin;
--
-- switch (socket->slot) {
-- case SLOT_NOPROBE_MEM:
-- addrwin = exca_read_byte(slot, I365_ADDRWIN);
-- addrwin &= 0x1f;
-- exca_write_byte(slot, I365_ADDRWIN, addrwin);
-- break;
-- case SLOT_NOPROBE_IO:
-- addrwin = exca_read_byte(slot, I365_ADDRWIN);
-- addrwin &= 0xc0;
-- exca_write_byte(slot, I365_ADDRWIN, addrwin);
-- break;
-- default:
-- break;
-- }
-+ socket = &vrc4171_sockets[slot];
-+ if (socket->noprobe != SLOT_PROBE) {
-+ uint8_t addrwin;
-
-- reserve_using_irq(slot);
-- continue;
-+ switch (socket->noprobe) {
-+ case SLOT_NOPROBE_MEM:
-+ addrwin = exca_read_byte(slot, I365_ADDRWIN);
-+ addrwin &= 0x1f;
-+ exca_write_byte(slot, I365_ADDRWIN, addrwin);
-+ break;
-+ case SLOT_NOPROBE_IO:
-+ addrwin = exca_read_byte(slot, I365_ADDRWIN);
-+ addrwin &= 0xc0;
-+ exca_write_byte(slot, I365_ADDRWIN, addrwin);
-+ break;
-+ default:
-+ break;
- }
-
-- sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot);
-- socket->pcmcia_socket.dev.dev = &vrc4171_card_device.dev;
-- socket->pcmcia_socket.ops = &vrc4171_pccard_operations;
-- socket->pcmcia_socket.owner = THIS_MODULE;
-+ reserve_using_irq(slot);
-
-- retval = pcmcia_register_socket(&socket->pcmcia_socket);
-- if (retval < 0)
-- return retval;
-+ return 0;
-+ }
-
-- exca_write_byte(slot, I365_ADDRWIN, 0);
-- exca_write_byte(slot, GLOBAL_CONTROL, 0);
-+ sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot);
-
-- socket->slot = SLOT_INITIALIZED;
-- }
-+ socket->pcmcia_socket.ops = &vrc4171_pccard_operations;
-+
-+ retval = pcmcia_register_socket(&socket->pcmcia_socket);
-+ if (retval != 0)
-+ return retval;
-+
-+ exca_write_byte(slot, I365_ADDRWIN, 0);
-+
-+ exca_write_byte(slot, GLOBAL_CONTROL, 0);
-
- return 0;
- }
-
--static void vrc4171_remove_sockets(void)
-+static void vrc4171_remove_socket(int slot)
- {
- vrc4171_socket_t *socket;
-- int slot;
-
-- for (slot = 0; slot < CARD_MAX_SLOTS; slot++) {
-- if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE)
-- continue;
-+ if (slot >= CARD_MAX_SLOTS)
-+ return;
-
-- socket = &vrc4171_sockets[slot];
-- if (socket->slot == SLOT_INITIALIZED)
-- pcmcia_unregister_socket(&socket->pcmcia_socket);
-+ socket = &vrc4171_sockets[slot];
-
-- socket->slot = SLOT_PROBE;
-- }
-+ pcmcia_unregister_socket(&socket->pcmcia_socket);
- }
-
- static int __devinit vrc4171_card_setup(char *options)
-@@ -721,13 +638,13 @@ static int __devinit vrc4171_card_setup(
- options += 6;
- if (*options != '\0') {
- if (strncmp(options, "memnoprobe", 10) == 0) {
-- vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_MEM;
-+ vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_MEM;
- options += 10;
- } else if (strncmp(options, "ionoprobe", 9) == 0) {
-- vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_IO;
-+ vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_IO;
- options += 9;
- } else if ( strncmp(options, "noprobe", 7) == 0) {
-- vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_ALL;
-+ vrc4171_sockets[CARD_SLOTA].noprobe = SLOT_NOPROBE_ALL;
- options += 7;
- }
-
-@@ -761,11 +678,11 @@ static int __devinit vrc4171_card_setup(
- options++;
-
- if (strncmp(options, "memnoprobe", 10) == 0)
-- vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_MEM;
-+ vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_MEM;
- if (strncmp(options, "ionoprobe", 9) == 0)
-- vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_IO;
-+ vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_IO;
- if (strncmp(options, "noprobe", 7) == 0)
-- vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_ALL;
-+ vrc4171_sockets[CARD_SLOTB].noprobe = SLOT_NOPROBE_ALL;
- }
- }
-
-@@ -774,72 +691,47 @@ static int __devinit vrc4171_card_setup(
-
- __setup("vrc4171_card=", vrc4171_card_setup);
-
--static int vrc4171_card_suspend(struct device *dev, pm_message_t state, u32 level)
--{
-- int retval = 0;
+-#
+-# Ftape, the floppy tape device driver
+-#
+-# CONFIG_DRM is not set
+-CONFIG_GPIO_VR41XX=y
+-# CONFIG_RAW_DRIVER is not set
-
-- if (level == SUSPEND_SAVE_STATE)
-- retval = pcmcia_socket_dev_suspend(dev, state);
+-#
+-# TPM devices
+-#
+-# CONFIG_TCG_TPM is not set
+-# CONFIG_TELCLOCK is not set
-
-- return retval;
--}
+-#
+-# I2C support
+-#
+-# CONFIG_I2C is not set
-
--static int vrc4171_card_resume(struct device *dev, u32 level)
--{
-- int retval = 0;
+-#
+-# Dallas's 1-wire bus
+-#
+-# CONFIG_W1 is not set
+-
+-#
+-# Hardware Monitoring support
+-#
+-# CONFIG_HWMON is not set
+-# CONFIG_HWMON_VID is not set
+-
+-#
+-# Misc devices
+-#
+-
+-#
+-# Multimedia Capabilities Port drivers
+-#
+-
+-#
+-# Multimedia devices
+-#
+-# CONFIG_VIDEO_DEV is not set
+-
+-#
+-# Digital Video Broadcasting Devices
+-#
+-# CONFIG_DVB is not set
+-
+-#
+-# Graphics support
+-#
+-# CONFIG_FB is not set
+-
+-#
+-# Console display driver support
+-#
+-# CONFIG_VGA_CONSOLE is not set
+-CONFIG_DUMMY_CONSOLE=y
+-
+-#
+-# Speakup console speech
+-#
+-# CONFIG_SPEAKUP is not set
+-
+-#
+-# Sound
+-#
+-# CONFIG_SOUND is not set
+-
+-#
+-# USB support
+-#
+-CONFIG_USB_ARCH_HAS_HCD=y
+-CONFIG_USB_ARCH_HAS_OHCI=y
+-CONFIG_USB=m
+-# CONFIG_USB_DEBUG is not set
+-
+-#
+-# Miscellaneous USB options
+-#
+-# CONFIG_USB_DEVICEFS is not set
+-# CONFIG_USB_BANDWIDTH is not set
+-# CONFIG_USB_DYNAMIC_MINORS is not set
+-# CONFIG_USB_OTG is not set
-
-- if (level == RESUME_RESTORE_STATE)
-- retval = pcmcia_socket_dev_resume(dev);
+-#
+-# USB Host Controller Drivers
+-#
+-CONFIG_USB_EHCI_HCD=m
+-# CONFIG_USB_EHCI_SPLIT_ISO is not set
+-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+-# CONFIG_USB_ISP116X_HCD is not set
+-CONFIG_USB_OHCI_HCD=m
+-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+-# CONFIG_USB_UHCI_HCD is not set
+-# CONFIG_USB_SL811_HCD is not set
+-
+-#
+-# USB Device Class drivers
+-#
+-# CONFIG_USB_ACM is not set
+-# CONFIG_USB_PRINTER is not set
+-
+-#
+-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+-#
+-
+-#
+-# may also be needed; see USB_STORAGE Help for more information
+-#
+-CONFIG_USB_STORAGE=m
+-# CONFIG_USB_STORAGE_DEBUG is not set
+-# CONFIG_USB_STORAGE_DATAFAB is not set
+-# CONFIG_USB_STORAGE_FREECOM is not set
+-# CONFIG_USB_STORAGE_ISD200 is not set
+-# CONFIG_USB_STORAGE_DPCM is not set
+-# CONFIG_USB_STORAGE_USBAT is not set
+-# CONFIG_USB_STORAGE_SDDR09 is not set
+-# CONFIG_USB_STORAGE_SDDR55 is not set
+-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+-
+-#
+-# USB Input Devices
+-#
+-CONFIG_USB_HID=m
+-CONFIG_USB_HIDINPUT=y
+-# CONFIG_HID_FF is not set
+-# CONFIG_USB_HIDDEV is not set
+-
+-#
+-# USB HID Boot Protocol drivers
+-#
+-# CONFIG_USB_KBD is not set
+-# CONFIG_USB_MOUSE is not set
+-# CONFIG_USB_AIPTEK is not set
+-# CONFIG_USB_WACOM is not set
+-# CONFIG_USB_ACECAD is not set
+-# CONFIG_USB_KBTAB is not set
+-# CONFIG_USB_POWERMATE is not set
+-# CONFIG_USB_MTOUCH is not set
+-# CONFIG_USB_ITMTOUCH is not set
+-# CONFIG_USB_EGALAX is not set
+-# CONFIG_USB_YEALINK is not set
+-# CONFIG_USB_XPAD is not set
+-# CONFIG_USB_ATI_REMOTE is not set
+-# CONFIG_USB_KEYSPAN_REMOTE is not set
+-# CONFIG_USB_APPLETOUCH is not set
+-
+-#
+-# USB Imaging devices
+-#
+-# CONFIG_USB_MDC800 is not set
+-# CONFIG_USB_MICROTEK is not set
+-
+-#
+-# USB Multimedia devices
+-#
+-# CONFIG_USB_DABUSB is not set
+-
+-#
+-# Video4Linux support is needed for USB Multimedia device support
+-#
+-
+-#
+-# USB Network Adapters
+-#
+-# CONFIG_USB_CATC is not set
+-# CONFIG_USB_KAWETH is not set
+-# CONFIG_USB_PEGASUS is not set
+-# CONFIG_USB_RTL8150 is not set
+-# CONFIG_USB_USBNET is not set
+-CONFIG_USB_MON=y
+-
+-#
+-# USB port drivers
+-#
+-
+-#
+-# USB Serial Converter support
+-#
+-# CONFIG_USB_SERIAL is not set
+-
+-#
+-# USB Miscellaneous drivers
+-#
+-# CONFIG_USB_EMI62 is not set
+-# CONFIG_USB_EMI26 is not set
+-# CONFIG_USB_AUERSWALD is not set
+-# CONFIG_USB_RIO500 is not set
+-# CONFIG_USB_LEGOTOWER is not set
+-# CONFIG_USB_LCD is not set
+-# CONFIG_USB_LED is not set
+-# CONFIG_USB_CYTHERM is not set
+-# CONFIG_USB_GOTEMP is not set
+-# CONFIG_USB_PHIDGETKIT is not set
+-# CONFIG_USB_PHIDGETSERVO is not set
+-# CONFIG_USB_IDMOUSE is not set
+-# CONFIG_USB_SISUSBVGA is not set
+-# CONFIG_USB_LD is not set
+-
+-#
+-# USB DSL modem support
+-#
+-
+-#
+-# USB Gadget Support
+-#
+-# CONFIG_USB_GADGET is not set
+-
+-#
+-# MMC/SD Card support
+-#
+-# CONFIG_MMC is not set
+-
+-#
+-# InfiniBand support
+-#
+-# CONFIG_INFINIBAND is not set
+-
+-#
+-# SN Devices
+-#
+-
+-#
+-# EDAC - error detection and reporting (RAS)
+-#
+-# CONFIG_EDAC is not set
+-
+-#
+-# Distributed Lock Manager
+-#
+-# CONFIG_DLM is not set
-
-- return retval;
--}
+-#
+-# File systems
+-#
+-CONFIG_EXT2_FS=y
+-# CONFIG_EXT2_FS_XATTR is not set
+-# CONFIG_EXT2_FS_XIP is not set
+-CONFIG_EXT3_FS=y
+-CONFIG_EXT3_FS_XATTR=y
+-# CONFIG_EXT3_FS_POSIX_ACL is not set
+-# CONFIG_EXT3_FS_SECURITY is not set
+-CONFIG_JBD=y
+-# CONFIG_JBD_DEBUG is not set
+-CONFIG_FS_MBCACHE=y
+-# CONFIG_REISER4_FS is not set
+-# CONFIG_REISERFS_FS is not set
+-# CONFIG_JFS_FS is not set
+-# CONFIG_FS_POSIX_ACL is not set
+-CONFIG_XFS_FS=y
+-CONFIG_XFS_QUOTA=y
+-# CONFIG_XFS_SECURITY is not set
+-CONFIG_XFS_POSIX_ACL=y
+-# CONFIG_XFS_RT is not set
+-# CONFIG_OCFS2_FS is not set
+-# CONFIG_MINIX_FS is not set
+-CONFIG_ROMFS_FS=m
+-CONFIG_INOTIFY=y
+-# CONFIG_QUOTA is not set
+-CONFIG_QUOTACTL=y
+-# CONFIG_DNOTIFY is not set
+-# CONFIG_AUTOFS_FS is not set
+-CONFIG_AUTOFS4_FS=y
+-# CONFIG_FUSE_FS is not set
-
--static struct device_driver vrc4171_card_driver = {
-- .name = vrc4171_card_name,
-- .bus = &platform_bus_type,
-- .suspend = vrc4171_card_suspend,
-- .resume = vrc4171_card_resume,
--};
+-#
+-# CD-ROM/DVD Filesystems
+-#
+-# CONFIG_ISO9660_FS is not set
+-# CONFIG_UDF_FS is not set
-
- static int __devinit vrc4171_card_init(void)
- {
-- int retval;
-+ int retval, slot;
-
-- retval = driver_register(&vrc4171_card_driver);
-- if (retval < 0)
-- return retval;
-+ vrc4171_set_multifunction_pin(vrc4171_slotb);
-
-- retval = platform_device_register(&vrc4171_card_device);
-- if (retval < 0) {
-- driver_unregister(&vrc4171_card_driver);
-- return retval;
-- }
-+ if (request_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE,
-+ "NEC VRC4171 Card Controller") == NULL)
-+ return -EBUSY;
-
-- vrc4171_set_multifunction_pin(vrc4171_slotb);
-+ for (slot = 0; slot < CARD_MAX_SLOTS; slot++) {
-+ if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE)
-+ break;
-
-- retval = vrc4171_add_sockets();
-- if (retval == 0)
-- retval = request_irq(vrc4171_irq, pccard_interrupt, SA_SHIRQ,
-- vrc4171_card_name, vrc4171_sockets);
-+ retval = vrc4171_add_socket(slot);
-+ if (retval != 0)
-+ return retval;
-+ }
-
-+ retval = request_irq(vrc4171_irq, pccard_interrupt, SA_SHIRQ,
-+ "NEC VRC4171 Card Controller", vrc4171_sockets);
- if (retval < 0) {
-- vrc4171_remove_sockets();
-- platform_device_unregister(&vrc4171_card_device);
-- driver_unregister(&vrc4171_card_driver);
-+ for (slot = 0; slot < CARD_MAX_SLOTS; slot++)
-+ vrc4171_remove_socket(slot);
-+
- return retval;
- }
-
-- printk(KERN_INFO "%s, connected to IRQ %d\n", vrc4171_card_driver.name, vrc4171_irq);
-+ printk(KERN_INFO "NEC VRC4171 Card Controller, connected to IRQ %d\n", vrc4171_irq);
-
- return 0;
- }
-
- static void __devexit vrc4171_card_exit(void)
- {
-- free_irq(vrc4171_irq, vrc4171_sockets);
-- vrc4171_remove_sockets();
-- platform_device_unregister(&vrc4171_card_device);
-- driver_unregister(&vrc4171_card_driver);
-+ int slot;
-+
-+ for (slot = 0; slot < CARD_MAX_SLOTS; slot++)
-+ vrc4171_remove_socket(slot);
-+
-+ release_region(CARD_CONTROLLER_INDEX, CARD_CONTROLLER_SIZE);
- }
-
- module_init(vrc4171_card_init);
-diff -urpNX dontdiff linux-2.6.12/drivers/pcmcia/vrc4173_cardu.c linux_HEAD/drivers/pcmcia/vrc4173_cardu.c
---- linux-2.6.12/drivers/pcmcia/vrc4173_cardu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/pcmcia/vrc4173_cardu.c 2005-07-10 12:28:27.000000000 +0200
-@@ -614,4 +614,3 @@ static void __devexit vrc4173_cardu_exit
-
- module_init(vrc4173_cardu_init);
- module_exit(vrc4173_cardu_exit);
--MODULE_DEVICE_TABLE(pci, vrc4173_cardu_id_table);
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/NCR53C9x.h linux_HEAD/drivers/scsi/NCR53C9x.h
---- linux-2.6.12/drivers/scsi/NCR53C9x.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/NCR53C9x.h 2005-02-17 21:50:04.000000000 +0100
-@@ -145,12 +145,7 @@
-
- #ifndef MULTIPLE_PAD_SIZES
-
--#ifdef CONFIG_CPU_HAS_WB
--#include <asm/wbflush.h>
--#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
--#else
--#define esp_write(__reg, __val) ((__reg) = (__val))
--#endif
-+#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0)
- #define esp_read(__reg) (__reg)
-
- struct ESP_regs {
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/dec_esp.c linux_HEAD/drivers/scsi/dec_esp.c
---- linux-2.6.12/drivers/scsi/dec_esp.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/dec_esp.c 2005-07-03 16:44:33.000000000 +0200
-@@ -18,7 +18,7 @@
- * 20001005 - Initialization fixes for 2.4.0-test9
- * Florian Lohoff <flo at rfc822.org>
- *
-- * Copyright (C) 2002, 2003 Maciej W. Rozycki
-+ * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
- */
-
- #include <linux/kernel.h>
-@@ -41,6 +41,7 @@
- #include <asm/dec/ioasic_addrs.h>
- #include <asm/dec/ioasic_ints.h>
- #include <asm/dec/machtype.h>
-+#include <asm/dec/system.h>
- #include <asm/dec/tc.h>
-
- #define DEC_SCSI_SREG 0
-@@ -54,7 +55,7 @@
-
- static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
- static void dma_drain(struct NCR_ESP *esp);
--static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp);
-+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp);
- static void dma_dump_state(struct NCR_ESP *esp);
- static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
- static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length);
-@@ -63,9 +64,9 @@ static void dma_ints_on(struct NCR_ESP *
- static int dma_irq_p(struct NCR_ESP *esp);
- static int dma_ports_p(struct NCR_ESP *esp);
- static void dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write);
--static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp);
--static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp);
--static void dma_advance_sg(struct scsi_cmnd * sp);
-+static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp);
-+static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp);
-+static void dma_advance_sg(Scsi_Cmnd * sp);
-
- static void pmaz_dma_drain(struct NCR_ESP *esp);
- static void pmaz_dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
-@@ -73,7 +74,7 @@ static void pmaz_dma_init_write(struct N
- static void pmaz_dma_ints_off(struct NCR_ESP *esp);
- static void pmaz_dma_ints_on(struct NCR_ESP *esp);
- static void pmaz_dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write);
--static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp);
-+static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp);
-
- #define TC_ESP_RAM_SIZE 0x20000
- #define ESP_TGT_DMA_SIZE ((TC_ESP_RAM_SIZE/7) & ~(sizeof(int)-1))
-@@ -97,7 +98,7 @@ static irqreturn_t scsi_dma_merr_int(int
- static irqreturn_t scsi_dma_err_int(int, void *, struct pt_regs *);
- static irqreturn_t scsi_dma_int(int, void *, struct pt_regs *);
-
--static int dec_esp_detect(struct scsi_host_template * tpnt);
-+int dec_esp_detect(Scsi_Host_Template * tpnt);
-
- static int dec_esp_release(struct Scsi_Host *shost)
- {
-@@ -109,9 +110,9 @@ static int dec_esp_release(struct Scsi_H
- return 0;
- }
-
--static struct scsi_host_template driver_template = {
-+static Scsi_Host_Template driver_template = {
- .proc_name = "dec_esp",
-- .proc_info = esp_proc_info,
-+ .proc_info = &esp_proc_info,
- .name = "NCR53C94",
- .detect = dec_esp_detect,
- .slave_alloc = esp_slave_alloc,
-@@ -132,7 +133,7 @@ static struct scsi_host_template driver_
- #include "scsi_module.c"
-
- /***************************************************************** Detection */
--static int dec_esp_detect(Scsi_Host_Template * tpnt)
-+int dec_esp_detect(Scsi_Host_Template * tpnt)
- {
- struct NCR_ESP *esp;
- struct ConfigDev *esp_dev;
-@@ -183,7 +184,8 @@ static int dec_esp_detect(Scsi_Host_Temp
- esp->dregs = 0;
-
- /* ESP register base */
-- esp->eregs = (struct ESP_regs *) (system_base + IOASIC_SCSI);
-+ esp->eregs = (void *)CKSEG1ADDR(dec_kn_slot_base +
-+ IOASIC_SCSI);
-
- /* Set the command buffer */
- esp->esp_command = (volatile unsigned char *) cmd_buffer;
-@@ -228,10 +230,11 @@ static int dec_esp_detect(Scsi_Host_Temp
- mem_start = get_tc_base_addr(slot);
-
- /* Store base addr into esp struct */
-- esp->slot = PHYSADDR(mem_start);
-+ esp->slot = mem_start;
-
- esp->dregs = 0;
-- esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG);
-+ esp->eregs = (void *)CKSEG1ADDR(mem_start +
-+ DEC_SCSI_SREG);
- esp->do_pio_cmds = 1;
-
- /* Set the command buffer */
-@@ -376,7 +379,7 @@ static void dma_drain(struct NCR_ESP *es
- }
- }
-
--static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp)
-+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp)
- {
- return sp->SCp.this_residual;
- }
-@@ -488,12 +491,12 @@ static void dma_setup(struct NCR_ESP *es
- dma_init_write(esp, addr, count);
- }
-
--static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp)
-+static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp)
- {
- sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer);
- }
-
--static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp)
-+static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp)
- {
- int sz = sp->SCp.buffers_residual;
- struct scatterlist *sg = sp->SCp.buffer;
-@@ -505,7 +508,7 @@ static void dma_mmu_get_scsi_sgl(struct
- sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address);
- }
-
--static void dma_advance_sg(struct scsi_cmnd * sp)
-+static void dma_advance_sg(Scsi_Cmnd * sp)
- {
- sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address);
- }
-@@ -513,14 +516,15 @@ static void dma_advance_sg(struct scsi_c
- static void pmaz_dma_drain(struct NCR_ESP *esp)
- {
- memcpy(phys_to_virt(esp_virt_buffer),
-- (void *)KSEG1ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE),
-- scsi_current_length);
-+ (void *)CKSEG1ADDR(esp->slot + DEC_SCSI_SRAM +
-+ ESP_TGT_DMA_SIZE),
-+ scsi_current_length);
- }
-
- static void pmaz_dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length)
- {
- volatile u32 *dmareg =
-- (volatile u32 *)KSEG1ADDR(esp->slot + DEC_SCSI_DMAREG);
-+ (volatile u32 *)CKSEG1ADDR(esp->slot + DEC_SCSI_DMAREG);
-
- if (length > ESP_TGT_DMA_SIZE)
- length = ESP_TGT_DMA_SIZE;
-@@ -536,9 +540,10 @@ static void pmaz_dma_init_read(struct NC
- static void pmaz_dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length)
- {
- volatile u32 *dmareg =
-- (volatile u32 *)KSEG1ADDR(esp->slot + DEC_SCSI_DMAREG);
-+ (volatile u32 *)CKSEG1ADDR(esp->slot + DEC_SCSI_DMAREG);
-
-- memcpy((void *)KSEG1ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE),
-+ memcpy((void *)CKSEG1ADDR(esp->slot + DEC_SCSI_SRAM +
-+ ESP_TGT_DMA_SIZE),
- phys_to_virt(vaddress), length);
-
- wmb();
-@@ -567,7 +572,7 @@ static void pmaz_dma_setup(struct NCR_ES
- pmaz_dma_init_write(esp, addr, count);
- }
-
--static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp)
-+static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp)
- {
- sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer);
- }
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/jazz_esp.c linux_HEAD/drivers/scsi/jazz_esp.c
---- linux-2.6.12/drivers/scsi/jazz_esp.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/jazz_esp.c 2004-10-27 02:14:48.000000000 +0200
-@@ -28,7 +28,7 @@
- #include <asm/pgtable.h>
-
- static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
--static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp);
-+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
- static void dma_dump_state(struct NCR_ESP *esp);
- static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length);
- static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length);
-@@ -37,11 +37,11 @@ static void dma_ints_on(struct NCR_ESP *
- static int dma_irq_p(struct NCR_ESP *esp);
- static int dma_ports_p(struct NCR_ESP *esp);
- static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
--static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp);
--static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp);
--static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp);
--static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp);
--static void dma_advance_sg (struct scsi_cmnd *sp);
-+static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-+static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-+static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-+static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-+static void dma_advance_sg (Scsi_Cmnd *sp);
- static void dma_led_off(struct NCR_ESP *);
- static void dma_led_on(struct NCR_ESP *);
-
-@@ -87,7 +87,7 @@ static Scsi_Host_Template driver_templat
- #include "scsi_module.c"
-
- /***************************************************************** Detection */
--static int jazz_esp_detect(struct scsi_host_template *tpnt)
-+int jazz_esp_detect(Scsi_Host_Template *tpnt)
- {
- struct NCR_ESP *esp;
- struct ConfigDev *esp_dev;
-@@ -180,7 +180,7 @@ static int dma_bytes_sent(struct NCR_ESP
- return fifo_count;
- }
-
--static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp)
-+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
- {
- /*
- * maximum DMA size is 1MB
-@@ -253,13 +253,13 @@ static void dma_setup(struct NCR_ESP *es
- }
- }
-
--static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp)
-+static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
- {
- sp->SCp.have_data_in = vdma_alloc(CPHYSADDR(sp->SCp.buffer), sp->SCp.this_residual);
- sp->SCp.ptr = (char *)((unsigned long)sp->SCp.have_data_in);
- }
-
--static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp)
-+static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
- {
- int sz = sp->SCp.buffers_residual;
- struct scatterlist *sg = (struct scatterlist *) sp->SCp.buffer;
-@@ -271,12 +271,12 @@ static void dma_mmu_get_scsi_sgl (struct
- sp->SCp.ptr=(char *)(sp->SCp.buffer->dma_address);
- }
-
--static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, struct scsi_cmnd *sp)
-+static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
- {
- vdma_free(sp->SCp.have_data_in);
- }
-
--static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, struct scsi_cmnd *sp)
-+static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
- {
- int sz = sp->use_sg - 1;
- struct scatterlist *sg = (struct scatterlist *)sp->buffer;
-@@ -287,7 +287,7 @@ static void dma_mmu_release_scsi_sgl (st
- }
- }
-
--static void dma_advance_sg (struct scsi_cmnd *sp)
-+static void dma_advance_sg (Scsi_Cmnd *sp)
- {
- sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address);
- }
-@@ -308,22 +308,3 @@ static void dma_led_on(struct NCR_ESP *e
- #endif
- }
-
--static struct scsi_host_template driver_template = {
-- .proc_name = "jazz_esp",
-- .proc_info = esp_proc_info,
-- .name = "ESP 100/100a/200",
-- .detect = jazz_esp_detect,
-- .slave_alloc = esp_slave_alloc,
-- .slave_destroy = esp_slave_destroy,
-- .release = jazz_esp_release,
-- .info = esp_info,
-- .queuecommand = esp_queue,
-- .eh_abort_handler = esp_abort,
-- .eh_bus_reset_handler = esp_reset,
-- .can_queue = 7,
-- .this_id = 7,
-- .sg_tablesize = SG_ALL,
-- .cmd_per_lun = 1,
-- .use_clustering = DISABLE_CLUSTERING,
--};
--#include "scsi_module.c"
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/qla1280.c linux_HEAD/drivers/scsi/qla1280.c
---- linux-2.6.12/drivers/scsi/qla1280.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/qla1280.c 2005-07-03 19:45:14.000000000 +0200
-@@ -996,7 +996,6 @@ qla1280_error_action(struct scsi_cmnd *c
- break;
-
- case ABORT_DEVICE:
-- ha->flags.in_reset = 1;
- if (qla1280_verbose)
- printk(KERN_INFO
- "scsi(%ld:%d:%d:%d): Queueing abort device "
-@@ -1010,7 +1009,6 @@ qla1280_error_action(struct scsi_cmnd *c
- printk(KERN_INFO
- "scsi(%ld:%d:%d:%d): Queueing device reset "
- "command.\n", ha->host_no, bus, target, lun);
-- ha->flags.in_reset = 1;
- if (qla1280_device_reset(ha, bus, target) == 0)
- result = SUCCESS;
- break;
-@@ -1019,7 +1017,6 @@ qla1280_error_action(struct scsi_cmnd *c
- if (qla1280_verbose)
- printk(KERN_INFO "qla1280(%ld:%d): Issuing BUS "
- "DEVICE RESET\n", ha->host_no, bus);
-- ha->flags.in_reset = 1;
- if (qla1280_bus_reset(ha, bus == 0))
- result = SUCCESS;
-
-@@ -1047,7 +1044,6 @@ qla1280_error_action(struct scsi_cmnd *c
-
- if (!list_empty(&ha->done_q))
- qla1280_done(ha);
-- ha->flags.in_reset = 0;
-
- /* If we didn't manage to issue the action, or we have no
- * command to wait for, exit here */
-@@ -1245,6 +1241,22 @@ qla1280_biosparam_old(Disk * disk, kdev_
- return qla1280_biosparam(disk->device, NULL, disk->capacity, geom);
- }
- #endif
-+
-+/* disable risc and host interrupts */
-+static inline void
-+qla1280_disable_intrs(struct scsi_qla_host *ha)
-+{
-+ WRT_REG_WORD(&ha->iobase->ictrl, 0);
-+ RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */
-+}
-+
-+/* enable risc and host interrupts */
-+static inline void
-+qla1280_enable_intrs(struct scsi_qla_host *ha)
-+{
-+ WRT_REG_WORD(&ha->iobase->ictrl, (ISP_EN_INT | ISP_EN_RISC));
-+ RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */
-+}
-
- /**************************************************************************
- * qla1280_intr_handler
-@@ -1266,7 +1278,7 @@ qla1280_intr_handler(int irq, void *dev_
- ha->isr_count++;
- reg = ha->iobase;
-
-- WRT_REG_WORD(®->ictrl, 0); /* disable our interrupt. */
-+ qla1280_disable_intrs(ha);
-
- data = qla1280_debounce_register(®->istatus);
- /* Check for pending interrupts. */
-@@ -1279,8 +1291,7 @@ qla1280_intr_handler(int irq, void *dev_
-
- spin_unlock(HOST_LOCK);
-
-- /* enable our interrupt. */
-- WRT_REG_WORD(®->ictrl, (ISP_EN_INT | ISP_EN_RISC));
-+ qla1280_enable_intrs(ha);
-
- LEAVE_INTR("qla1280_intr_handler");
- return IRQ_RETVAL(handled);
-@@ -1293,7 +1304,7 @@ qla1280_set_target_parameters(struct scs
- uint8_t mr;
- uint16_t mb[MAILBOX_REGISTER_COUNT];
- struct nvram *nv;
-- int status;
-+ int status, lun;
-
- nv = &ha->nvram;
-
-@@ -1301,24 +1312,38 @@ qla1280_set_target_parameters(struct scs
-
- /* Set Target Parameters. */
- mb[0] = MBC_SET_TARGET_PARAMETERS;
-- mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
-- mb[1] <<= 8;
--
-- mb[2] = (nv->bus[bus].target[target].parameter.c << 8);
-+ mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
-+ mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8;
-+ mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9;
-+ mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10;
-+ mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11;
-+ mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12;
-+ mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13;
-+ mb[2] |= nv->bus[bus].target[target].parameter.parity_checking << 14;
-+ mb[2] |= nv->bus[bus].target[target].parameter.disconnect_allowed << 15;
-
- if (IS_ISP1x160(ha)) {
- mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5;
-- mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8) |
-- nv->bus[bus].target[target].sync_period;
-+ mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8);
- mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) |
- nv->bus[bus].target[target].ppr_1x160.flags.ppr_bus_width;
- mr |= BIT_6;
- } else {
-- mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8) |
-- nv->bus[bus].target[target].sync_period;
-+ mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8);
- }
-+ mb[3] |= nv->bus[bus].target[target].sync_period;
-
-- status = qla1280_mailbox_command(ha, mr, &mb[0]);
-+ status = qla1280_mailbox_command(ha, mr, mb);
-+
-+ /* Set Device Queue Parameters. */
-+ for (lun = 0; lun < MAX_LUNS; lun++) {
-+ mb[0] = MBC_SET_DEVICE_QUEUE;
-+ mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
-+ mb[1] |= lun;
-+ mb[2] = nv->bus[bus].max_queue_depth;
-+ mb[3] = nv->bus[bus].target[target].execution_throttle;
-+ status |= qla1280_mailbox_command(ha, 0x0f, mb);
-+ }
-
- if (status)
- printk(KERN_WARNING "scsi(%ld:%i:%i): "
-@@ -1365,19 +1390,19 @@ qla1280_slave_configure(struct scsi_devi
- }
-
- #if LINUX_VERSION_CODE > 0x020500
-- nv->bus[bus].target[target].parameter.f.enable_sync = device->sdtr;
-- nv->bus[bus].target[target].parameter.f.enable_wide = device->wdtr;
-+ nv->bus[bus].target[target].parameter.enable_sync = device->sdtr;
-+ nv->bus[bus].target[target].parameter.enable_wide = device->wdtr;
- nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr = device->ppr;
- #endif
-
- if (driver_setup.no_sync ||
- (driver_setup.sync_mask &&
- (~driver_setup.sync_mask & (1 << target))))
-- nv->bus[bus].target[target].parameter.f.enable_sync = 0;
-+ nv->bus[bus].target[target].parameter.enable_sync = 0;
- if (driver_setup.no_wide ||
- (driver_setup.wide_mask &&
- (~driver_setup.wide_mask & (1 << target))))
-- nv->bus[bus].target[target].parameter.f.enable_wide = 0;
-+ nv->bus[bus].target[target].parameter.enable_wide = 0;
- if (IS_ISP1x160(ha)) {
- if (driver_setup.no_ppr ||
- (driver_setup.ppr_mask &&
-@@ -1386,7 +1411,7 @@ qla1280_slave_configure(struct scsi_devi
- }
-
- spin_lock_irqsave(HOST_LOCK, flags);
-- if (nv->bus[bus].target[target].parameter.f.enable_sync)
-+ if (nv->bus[bus].target[target].parameter.enable_sync)
- status = qla1280_set_target_parameters(ha, bus, target);
- qla1280_get_target_parameters(ha, device);
- spin_unlock_irqrestore(HOST_LOCK, flags);
-@@ -1424,7 +1449,6 @@ qla1280_select_queue_depth(struct Scsi_H
- *
- * Input:
- * ha = adapter block pointer.
-- * done_q = done queue.
- */
- static void
- qla1280_done(struct scsi_qla_host *ha)
-@@ -1498,7 +1522,7 @@ qla1280_return_status(struct response *
- int host_status = DID_ERROR;
- uint16_t comp_status = le16_to_cpu(sts->comp_status);
- uint16_t state_flags = le16_to_cpu(sts->state_flags);
-- uint16_t residual_length = le16_to_cpu(sts->residual_length);
-+ uint16_t residual_length = le32_to_cpu(sts->residual_length);
- uint16_t scsi_status = le16_to_cpu(sts->scsi_status);
- #if DEBUG_QLA1280_INTR
- static char *reason[] = {
-@@ -1558,7 +1582,7 @@ qla1280_return_status(struct response *
-
- case CS_DATA_OVERRUN:
- dprintk(2, "Data overrun 0x%x\n", residual_length);
-- dprintk(2, "qla1280_isr: response packet data\n");
-+ dprintk(2, "qla1280_return_status: response packet data\n");
- qla1280_dump_buffer(2, (char *)sts, RESPONSE_ENTRY_SIZE);
- host_status = DID_ERROR;
- break;
-@@ -1593,40 +1617,6 @@ qla1280_return_status(struct response *
- /* QLogic ISP1280 Hardware Support Functions. */
- /****************************************************************************/
-
-- /*
-- * qla2100_enable_intrs
-- * qla2100_disable_intrs
-- *
-- * Input:
-- * ha = adapter block pointer.
-- *
-- * Returns:
-- * None
-- */
--static inline void
--qla1280_enable_intrs(struct scsi_qla_host *ha)
--{
-- struct device_reg __iomem *reg;
+-#
+-# DOS/FAT/NT Filesystems
+-#
+-# CONFIG_MSDOS_FS is not set
+-# CONFIG_VFAT_FS is not set
+-# CONFIG_NTFS_FS is not set
-
-- reg = ha->iobase;
-- /* enable risc and host interrupts */
-- WRT_REG_WORD(®->ictrl, (ISP_EN_INT | ISP_EN_RISC));
-- RD_REG_WORD(®->ictrl); /* PCI Posted Write flush */
-- ha->flags.ints_enabled = 1;
--}
+-#
+-# Pseudo filesystems
+-#
+-CONFIG_PROC_FS=y
+-CONFIG_PROC_KCORE=y
+-CONFIG_SYSFS=y
+-CONFIG_TMPFS=y
+-# CONFIG_HUGETLB_PAGE is not set
+-CONFIG_RAMFS=y
+-# CONFIG_RELAYFS_FS is not set
+-# CONFIG_CONFIGFS_FS is not set
-
--static inline void
--qla1280_disable_intrs(struct scsi_qla_host *ha)
--{
-- struct device_reg __iomem *reg;
+-#
+-# Miscellaneous filesystems
+-#
+-# CONFIG_ADFS_FS is not set
+-# CONFIG_AFFS_FS is not set
+-# CONFIG_ASFS_FS is not set
+-# CONFIG_HFS_FS is not set
+-# CONFIG_HFSPLUS_FS is not set
+-# CONFIG_BEFS_FS is not set
+-# CONFIG_BFS_FS is not set
+-# CONFIG_EFS_FS is not set
+-CONFIG_CRAMFS=m
+-# CONFIG_VXFS_FS is not set
+-# CONFIG_HPFS_FS is not set
+-# CONFIG_QNX4FS_FS is not set
+-# CONFIG_SYSV_FS is not set
+-# CONFIG_UFS_FS is not set
-
-- reg = ha->iobase;
-- /* disable risc and host interrupts */
-- WRT_REG_WORD(®->ictrl, 0);
-- RD_REG_WORD(®->ictrl); /* PCI Posted Write flush */
-- ha->flags.ints_enabled = 0;
--}
+-#
+-# Network File Systems
+-#
+-CONFIG_NFS_FS=y
+-CONFIG_NFS_V3=y
+-# CONFIG_NFS_V3_ACL is not set
+-# CONFIG_NFS_V4 is not set
+-# CONFIG_NFS_DIRECTIO is not set
+-# CONFIG_NFSD is not set
+-CONFIG_ROOT_NFS=y
+-CONFIG_LOCKD=y
+-CONFIG_LOCKD_V4=y
+-CONFIG_NFS_COMMON=y
+-CONFIG_SUNRPC=y
+-# CONFIG_RPCSEC_GSS_KRB5 is not set
+-# CONFIG_RPCSEC_GSS_SPKM3 is not set
+-# CONFIG_SMB_FS is not set
+-# CONFIG_CIFS is not set
+-# CONFIG_NCP_FS is not set
+-# CONFIG_CODA_FS is not set
+-# CONFIG_AFS_FS is not set
+-# CONFIG_9P_FS is not set
-
- /*
- * qla1280_initialize_adapter
- * Initialize board.
-@@ -1655,7 +1645,6 @@ qla1280_initialize_adapter(struct scsi_q
- ha->flags.reset_active = 0;
- ha->flags.abort_isp_active = 0;
-
-- ha->flags.ints_enabled = 0;
- #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
- if (ia64_platform_is("sn2")) {
- printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA "
-@@ -1734,69 +1723,6 @@ qla1280_initialize_adapter(struct scsi_q
- return status;
- }
-
+-#
+-# Partition Types
+-#
+-# CONFIG_PARTITION_ADVANCED is not set
+-CONFIG_MSDOS_PARTITION=y
-
--/*
-- * ISP Firmware Test
-- * Checks if present version of RISC firmware is older than
-- * driver firmware.
-- *
-- * Input:
-- * ha = adapter block pointer.
-- *
-- * Returns:
-- * 0 = firmware does not need to be loaded.
-- */
--static int
--qla1280_isp_firmware(struct scsi_qla_host *ha)
--{
-- struct nvram *nv = (struct nvram *) ha->response_ring;
-- int status = 0; /* dg 2/27 always loads RISC */
-- uint16_t mb[MAILBOX_REGISTER_COUNT];
--
-- ENTER("qla1280_isp_firmware");
--
-- dprintk(1, "scsi(%li): Determining if RISC is loaded\n", ha->host_no);
--
-- /* Bad NVRAM data, load RISC code. */
-- if (!ha->nvram_valid) {
-- ha->flags.disable_risc_code_load = 0;
-- } else
-- ha->flags.disable_risc_code_load =
-- nv->cntr_flags_1.disable_loading_risc_code;
--
-- if (ha->flags.disable_risc_code_load) {
-- dprintk(3, "qla1280_isp_firmware: Telling RISC to verify "
-- "checksum of loaded BIOS code.\n");
--
-- /* Verify checksum of loaded RISC code. */
-- mb[0] = MBC_VERIFY_CHECKSUM;
-- /* mb[1] = ql12_risc_code_addr01; */
-- mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
--
-- if (!(status =
-- qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]))) {
-- /* Start firmware execution. */
-- dprintk(3, "qla1280_isp_firmware: Startng F/W "
-- "execution.\n");
--
-- mb[0] = MBC_EXECUTE_FIRMWARE;
-- /* mb[1] = ql12_risc_code_addr01; */
-- mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
-- qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-- } else
-- printk(KERN_INFO "qla1280: RISC checksum failed.\n");
-- } else {
-- dprintk(1, "qla1280: NVRAM configured to load RISC load.\n");
-- status = 1;
-- }
+-#
+-# Native Language Support
+-#
+-# CONFIG_NLS is not set
-
-- if (status)
-- dprintk(2, "qla1280_isp_firmware: **** Load RISC code ****\n");
+-#
+-# Profiling support
+-#
+-# CONFIG_PROFILING is not set
-
-- LEAVE("qla1280_isp_firmware");
-- return status;
--}
+-#
+-# Kernel hacking
+-#
+-# CONFIG_PRINTK_TIME is not set
+-# CONFIG_DEBUG_KERNEL is not set
+-CONFIG_LOG_BUF_SHIFT=14
+-CONFIG_CROSSCOMPILE=y
+-CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
-
- /*
- * Chip diagnostics
- * Test chip for proper operation.
-@@ -1982,7 +1908,7 @@ qla1280_load_firmware_dma(struct scsi_ql
- "%d,%d(0x%x)\n",
- risc_code_address, cnt, num, risc_address);
- for(i = 0; i < cnt; i++)
-- ((uint16_t *)ha->request_ring)[i] =
-+ ((__le16 *)ha->request_ring)[i] =
- cpu_to_le16(risc_code_address[i]);
-
- mb[0] = MBC_LOAD_RAM;
-@@ -2061,7 +1987,7 @@ qla1280_start_firmware(struct scsi_qla_h
- mb[1] = *ql1280_board_tbl[ha->devnum].fwstart;
- err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
- if (err) {
-- printk(KERN_ERR "scsi(%li): Failed checksum\n", ha->host_no);
-+ printk(KERN_ERR "scsi(%li): RISC checksum failed.\n", ha->host_no);
- return err;
- }
-
-@@ -2081,14 +2007,7 @@ qla1280_start_firmware(struct scsi_qla_h
- static int
- qla1280_load_firmware(struct scsi_qla_host *ha)
- {
-- int err = -ENODEV;
+-#
+-# Security options
+-#
+-CONFIG_KEYS=y
+-CONFIG_KEYS_DEBUG_PROC_KEYS=y
+-# CONFIG_SECURITY is not set
-
-- /* If firmware needs to be loaded */
-- if (!qla1280_isp_firmware(ha)) {
-- printk(KERN_ERR "scsi(%li): isp_firmware() failed!\n",
-- ha->host_no);
-- goto out;
-- }
-+ int err;
-
- err = qla1280_chip_diag(ha);
- if (err)
-@@ -2222,17 +2141,17 @@ qla1280_set_target_defaults(struct scsi_
- {
- struct nvram *nv = &ha->nvram;
-
-- nv->bus[bus].target[target].parameter.f.renegotiate_on_error = 1;
-- nv->bus[bus].target[target].parameter.f.auto_request_sense = 1;
-- nv->bus[bus].target[target].parameter.f.tag_queuing = 1;
-- nv->bus[bus].target[target].parameter.f.enable_sync = 1;
-+ nv->bus[bus].target[target].parameter.renegotiate_on_error = 1;
-+ nv->bus[bus].target[target].parameter.auto_request_sense = 1;
-+ nv->bus[bus].target[target].parameter.tag_queuing = 1;
-+ nv->bus[bus].target[target].parameter.enable_sync = 1;
- #if 1 /* Some SCSI Processors do not seem to like this */
-- nv->bus[bus].target[target].parameter.f.enable_wide = 1;
-+ nv->bus[bus].target[target].parameter.enable_wide = 1;
- #endif
-- nv->bus[bus].target[target].parameter.f.parity_checking = 1;
-- nv->bus[bus].target[target].parameter.f.disconnect_allowed = 1;
- nv->bus[bus].target[target].execution_throttle =
- nv->bus[bus].max_queue_depth - 1;
-+ nv->bus[bus].target[target].parameter.parity_checking = 1;
-+ nv->bus[bus].target[target].parameter.disconnect_allowed = 1;
-
- if (IS_ISP1x160(ha)) {
- nv->bus[bus].target[target].flags.flags1x160.device_enable = 1;
-@@ -2260,9 +2179,9 @@ qla1280_set_defaults(struct scsi_qla_hos
- /* nv->cntr_flags_1.disable_loading_risc_code = 1; */
- nv->firmware_feature.f.enable_fast_posting = 1;
- nv->firmware_feature.f.disable_synchronous_backoff = 1;
-- nv->termination.f.scsi_bus_0_control = 3;
-- nv->termination.f.scsi_bus_1_control = 3;
-- nv->termination.f.auto_term_support = 1;
-+ nv->termination.scsi_bus_0_control = 3;
-+ nv->termination.scsi_bus_1_control = 3;
-+ nv->termination.auto_term_support = 1;
-
- /*
- * Set default FIFO magic - What appropriate values would be here
-@@ -2272,7 +2191,12 @@ qla1280_set_defaults(struct scsi_qla_hos
- * header file provided by QLogic seems to be bogus or incomplete
- * at best.
- */
-- nv->isp_config.c = ISP_CFG1_BENAB|ISP_CFG1_F128;
-+ nv->isp_config.burst_enable = 1;
-+ if (IS_ISP1040(ha))
-+ nv->isp_config.fifo_threshold |= 3;
-+ else
-+ nv->isp_config.fifo_threshold |= 4;
-+
- if (IS_ISP1x160(ha))
- nv->isp_parameter = 0x01; /* fast memory enable */
-
-@@ -2303,66 +2227,53 @@ qla1280_config_target(struct scsi_qla_ho
- struct nvram *nv = &ha->nvram;
- uint16_t mb[MAILBOX_REGISTER_COUNT];
- int status, lun;
-+ uint16_t flag;
-
- /* Set Target Parameters. */
- mb[0] = MBC_SET_TARGET_PARAMETERS;
-- mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
-- mb[1] <<= 8;
--
-- /*
-- * Do not enable wide, sync, and ppr for the initial
-- * INQUIRY run. We enable this later if we determine
-- * the target actually supports it.
-- */
-- nv->bus[bus].target[target].parameter.f.
-- auto_request_sense = 1;
-- nv->bus[bus].target[target].parameter.f.
-- stop_queue_on_check = 0;
--
-- if (IS_ISP1x160(ha))
-- nv->bus[bus].target[target].ppr_1x160.
-- flags.enable_ppr = 0;
-+ mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
-
- /*
-- * No sync, wide, etc. while probing
-+ * Do not enable sync and ppr for the initial INQUIRY run. We
-+ * enable this later if we determine the target actually
-+ * supports it.
- */
-- mb[2] = (nv->bus[bus].target[target].parameter.c << 8) &
-- ~(TP_SYNC /*| TP_WIDE | TP_PPR*/);
-+ mb[2] = (TP_RENEGOTIATE | TP_AUTO_REQUEST_SENSE | TP_TAGGED_QUEUE
-+ | TP_WIDE | TP_PARITY | TP_DISCONNECT);
-
- if (IS_ISP1x160(ha))
- mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
- else
- mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
- mb[3] |= nv->bus[bus].target[target].sync_period;
+-#
+-# Cryptographic options
+-#
+-# CONFIG_CRYPTO is not set
-
-- status = qla1280_mailbox_command(ha, BIT_3 | BIT_2 | BIT_1 | BIT_0, &mb[0]);
-+ status = qla1280_mailbox_command(ha, 0x0f, mb);
-
- /* Save Tag queuing enable flag. */
-- mb[0] = BIT_0 << target;
-- if (nv->bus[bus].target[target].parameter.f.tag_queuing)
-- ha->bus_settings[bus].qtag_enables |= mb[0];
-+ flag = (BIT_0 << target) & mb[0];
-+ if (nv->bus[bus].target[target].parameter.tag_queuing)
-+ ha->bus_settings[bus].qtag_enables |= flag;
-
- /* Save Device enable flag. */
- if (IS_ISP1x160(ha)) {
- if (nv->bus[bus].target[target].flags.flags1x160.device_enable)
-- ha->bus_settings[bus].device_enables |= mb[0];
-+ ha->bus_settings[bus].device_enables |= flag;
- ha->bus_settings[bus].lun_disables |= 0;
- } else {
- if (nv->bus[bus].target[target].flags.flags1x80.device_enable)
-- ha->bus_settings[bus].device_enables |= mb[0];
-+ ha->bus_settings[bus].device_enables |= flag;
- /* Save LUN disable flag. */
- if (nv->bus[bus].target[target].flags.flags1x80.lun_disable)
-- ha->bus_settings[bus].lun_disables |= mb[0];
-+ ha->bus_settings[bus].lun_disables |= flag;
- }
-
- /* Set Device Queue Parameters. */
- for (lun = 0; lun < MAX_LUNS; lun++) {
- mb[0] = MBC_SET_DEVICE_QUEUE;
-- mb[1] = (uint16_t)(bus ? target | BIT_7 : target);
-- mb[1] = mb[1] << 8 | lun;
-+ mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
-+ mb[1] |= lun;
- mb[2] = nv->bus[bus].max_queue_depth;
- mb[3] = nv->bus[bus].target[target].execution_throttle;
-- status |= qla1280_mailbox_command(ha, 0x0f, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, 0x0f, mb);
- }
-
- return status;
-@@ -2407,7 +2318,6 @@ qla1280_nvram_config(struct scsi_qla_hos
- struct nvram *nv = &ha->nvram;
- int bus, target, status = 0;
- uint16_t mb[MAILBOX_REGISTER_COUNT];
-- uint16_t mask;
-
- ENTER("qla1280_nvram_config");
-
-@@ -2415,7 +2325,7 @@ qla1280_nvram_config(struct scsi_qla_hos
- /* Always force AUTO sense for LINUX SCSI */
- for (bus = 0; bus < MAX_BUSES; bus++)
- for (target = 0; target < MAX_TARGETS; target++) {
-- nv->bus[bus].target[target].parameter.f.
-+ nv->bus[bus].target[target].parameter.
- auto_request_sense = 1;
- }
- } else {
-@@ -2433,31 +2343,40 @@ qla1280_nvram_config(struct scsi_qla_hos
-
- hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK;
-
-- cfg1 = RD_REG_WORD(®->cfg_1);
-+ cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6);
- cdma_conf = RD_REG_WORD(®->cdma_cfg);
- ddma_conf = RD_REG_WORD(®->ddma_cfg);
-
- /* Busted fifo, says mjacob. */
-- if (hwrev == ISP_CFG0_1040A)
-- WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64);
-- else
-- WRT_REG_WORD(®->cfg_1, cfg1 | ISP_CFG1_F64 | ISP_CFG1_BENAB);
-+ if (hwrev != ISP_CFG0_1040A)
-+ cfg1 |= nv->isp_config.fifo_threshold << 4;
-+
-+ cfg1 |= nv->isp_config.burst_enable << 2;
-+ WRT_REG_WORD(®->cfg_1, cfg1);
-
- WRT_REG_WORD(®->cdma_cfg, cdma_conf | CDMA_CONF_BENAB);
- WRT_REG_WORD(®->ddma_cfg, cdma_conf | DDMA_CONF_BENAB);
- } else {
-+ uint16_t cfg1, term;
-+
- /* Set ISP hardware DMA burst */
-- mb[0] = nv->isp_config.c;
-+ cfg1 = nv->isp_config.fifo_threshold << 4;
-+ cfg1 |= nv->isp_config.burst_enable << 2;
- /* Enable DMA arbitration on dual channel controllers */
- if (ha->ports > 1)
-- mb[0] |= BIT_13;
-- WRT_REG_WORD(®->cfg_1, mb[0]);
-+ cfg1 |= BIT_13;
-+ WRT_REG_WORD(®->cfg_1, cfg1);
-
- /* Set SCSI termination. */
-- WRT_REG_WORD(®->gpio_enable, (BIT_3 + BIT_2 + BIT_1 + BIT_0));
-- mb[0] = nv->termination.c & (BIT_3 + BIT_2 + BIT_1 + BIT_0);
-- WRT_REG_WORD(®->gpio_data, mb[0]);
-+ WRT_REG_WORD(®->gpio_enable,
-+ BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
-+ term = nv->termination.scsi_bus_1_control;
-+ term |= nv->termination.scsi_bus_0_control << 2;
-+ term |= nv->termination.auto_term_support << 7;
-+ RD_REG_WORD(®->id_l); /* Flush PCI write */
-+ WRT_REG_WORD(®->gpio_data, term);
- }
-+ RD_REG_WORD(®->id_l); /* Flush PCI write */
-
- /* ISP parameter word. */
- mb[0] = MBC_SET_SYSTEM_PARAMETER;
-@@ -2473,16 +2392,17 @@ qla1280_nvram_config(struct scsi_qla_hos
-
- /* Firmware feature word. */
- mb[0] = MBC_SET_FIRMWARE_FEATURES;
-- mask = BIT_5 | BIT_1 | BIT_0;
-- mb[1] = le16_to_cpu(nv->firmware_feature.w) & (mask);
-+ mb[1] = nv->firmware_feature.f.enable_fast_posting;
-+ mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1;
-+ mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5;
- #if defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_SGI_SN2)
- if (ia64_platform_is("sn2")) {
- printk(KERN_INFO "scsi(%li): Enabling SN2 PCI DMA "
- "workaround\n", ha->host_no);
-- mb[1] |= BIT_9;
-+ mb[1] |= nv->firmware_feature.f.unused_9 << 9; /* XXX */
- }
- #endif
-- status |= qla1280_mailbox_command(ha, mask, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
-
- /* Retry count and delay. */
- mb[0] = MBC_SET_RETRY_COUNT;
-@@ -2511,27 +2431,27 @@ qla1280_nvram_config(struct scsi_qla_hos
- mb[2] |= BIT_5;
- if (nv->bus[1].config_2.data_line_active_negation)
- mb[2] |= BIT_4;
-- status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
-
- mb[0] = MBC_SET_DATA_OVERRUN_RECOVERY;
- mb[1] = 2; /* Reset SCSI bus and return all outstanding IO */
-- status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
-
- /* thingy */
- mb[0] = MBC_SET_PCI_CONTROL;
-- mb[1] = 2; /* Data DMA Channel Burst Enable */
-- mb[2] = 2; /* Command DMA Channel Burst Enable */
-- status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
-+ mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
-+ mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
-+ status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
-
- mb[0] = MBC_SET_TAG_AGE_LIMIT;
- mb[1] = 8;
-- status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
-
- /* Selection timeout. */
- mb[0] = MBC_SET_SELECTION_TIMEOUT;
- mb[1] = nv->bus[0].selection_timeout;
- mb[2] = nv->bus[1].selection_timeout;
-- status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
-+ status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
-
- for (bus = 0; bus < ha->ports; bus++)
- status |= qla1280_config_bus(ha, bus);
-@@ -3042,7 +2962,7 @@ qla1280_64bit_start_scsi(struct scsi_qla
- struct scsi_cmnd *cmd = sp->cmd;
- cmd_a64_entry_t *pkt;
- struct scatterlist *sg = NULL;
-- u32 *dword_ptr;
-+ __le32 *dword_ptr;
- dma_addr_t dma_handle;
- int status = 0;
- int cnt;
-@@ -3080,10 +3000,13 @@ qla1280_64bit_start_scsi(struct scsi_qla
- REQUEST_ENTRY_CNT - (ha->req_ring_index - cnt);
- }
-
-+ dprintk(3, "Number of free entries=(%d) seg_cnt=0x%x\n",
-+ ha->req_q_cnt, seg_cnt);
-+
- /* If room for request in request ring. */
- if ((req_cnt + 2) >= ha->req_q_cnt) {
- status = 1;
-- dprintk(2, "qla1280_64bit_start_scsi: in-ptr=0x%x req_q_cnt="
-+ dprintk(2, "qla1280_start_scsi: in-ptr=0x%x req_q_cnt="
- "0x%xreq_cnt=0x%x", ha->req_ring_index, ha->req_q_cnt,
- req_cnt);
- goto out;
-@@ -3095,7 +3018,7 @@ qla1280_64bit_start_scsi(struct scsi_qla
-
- if (cnt >= MAX_OUTSTANDING_COMMANDS) {
- status = 1;
-- dprintk(2, "qla1280_64bit_start_scsi: NO ROOM IN "
-+ dprintk(2, "qla1280_start_scsi: NO ROOM IN "
- "OUTSTANDING ARRAY, req_q_cnt=0x%x", ha->req_q_cnt);
- goto out;
- }
-@@ -3104,7 +3027,7 @@ qla1280_64bit_start_scsi(struct scsi_qla
- ha->req_q_cnt -= req_cnt;
- CMD_HANDLE(sp->cmd) = (unsigned char *)(unsigned long)(cnt + 1);
-
-- dprintk(2, "64bit_start: cmd=%p sp=%p CDB=%xm, handle %lx\n", cmd, sp,
-+ dprintk(2, "start: cmd=%p sp=%p CDB=%xm, handle %lx\n", cmd, sp,
- cmd->cmnd[0], (long)CMD_HANDLE(sp->cmd));
- dprintk(2, " bus %i, target %i, lun %i\n",
- SCSI_BUS_32(cmd), SCSI_TCN_32(cmd), SCSI_LUN_32(cmd));
-@@ -3326,7 +3249,7 @@ qla1280_32bit_start_scsi(struct scsi_qla
- struct scsi_cmnd *cmd = sp->cmd;
- struct cmd_entry *pkt;
- struct scatterlist *sg = NULL;
-- uint32_t *dword_ptr;
-+ __le32 *dword_ptr;
- int status = 0;
- int cnt;
- int req_cnt;
-@@ -3969,21 +3892,21 @@ qla1280_get_target_options(struct scsi_c
- result = cmd->request_buffer;
- n = &ha->nvram;
-
-- n->bus[bus].target[target].parameter.f.enable_wide = 0;
-- n->bus[bus].target[target].parameter.f.enable_sync = 0;
-+ n->bus[bus].target[target].parameter.enable_wide = 0;
-+ n->bus[bus].target[target].parameter.enable_sync = 0;
- n->bus[bus].target[target].ppr_1x160.flags.enable_ppr = 0;
-
- if (result[7] & 0x60)
-- n->bus[bus].target[target].parameter.f.enable_wide = 1;
-+ n->bus[bus].target[target].parameter.enable_wide = 1;
- if (result[7] & 0x10)
-- n->bus[bus].target[target].parameter.f.enable_sync = 1;
-+ n->bus[bus].target[target].parameter.enable_sync = 1;
- if ((result[2] >= 3) && (result[4] + 5 > 56) &&
- (result[56] & 0x4))
- n->bus[bus].target[target].ppr_1x160.flags.enable_ppr = 1;
-
- dprintk(2, "get_target_options(): wide %i, sync %i, ppr %i\n",
-- n->bus[bus].target[target].parameter.f.enable_wide,
-- n->bus[bus].target[target].parameter.f.enable_sync,
-+ n->bus[bus].target[target].parameter.enable_wide,
-+ n->bus[bus].target[target].parameter.enable_sync,
- n->bus[bus].target[target].ppr_1x160.flags.enable_ppr);
- }
- #endif
-@@ -4039,8 +3962,8 @@ qla1280_status_entry(struct scsi_qla_hos
- }
-
- /* Target busy */
-- if (scsi_status & SS_BUSY_CONDITION &&
-- scsi_status != SS_RESERVE_CONFLICT) {
-+ if (scsi_status & SAM_STAT_BUSY &&
-+ scsi_status != SAM_STAT_RESERVATION_CONFLICT) {
- CMD_RESULT(cmd) =
- DID_BUS_BUSY << 16 | (scsi_status & 0xff);
- } else {
-@@ -4048,7 +3971,7 @@ qla1280_status_entry(struct scsi_qla_hos
- /* Save ISP completion status */
- CMD_RESULT(cmd) = qla1280_return_status(pkt, cmd);
-
-- if (scsi_status & SS_CHECK_CONDITION) {
-+ if (scsi_status & SAM_STAT_CHECK_CONDITION) {
- if (comp_status != CS_ARS_FAILED) {
- uint16_t req_sense_length =
- le16_to_cpu(pkt->req_sense_length);
-@@ -4627,7 +4550,7 @@ qla1280_probe_one(struct pci_dev *pdev,
- if (pci_set_dma_mask(ha->pdev, (dma_addr_t) ~ 0ULL)) {
- if (pci_set_dma_mask(ha->pdev, 0xffffffff)) {
- printk(KERN_WARNING "scsi(%li): Unable to set a "
-- " suitable DMA mask - aboring\n", ha->host_no);
-+ "suitable DMA mask - aborting\n", ha->host_no);
- error = -ENODEV;
- goto error_free_irq;
- }
-@@ -4637,14 +4560,14 @@ qla1280_probe_one(struct pci_dev *pdev,
- #else
- if (pci_set_dma_mask(ha->pdev, 0xffffffff)) {
- printk(KERN_WARNING "scsi(%li): Unable to set a "
-- " suitable DMA mask - aboring\n", ha->host_no);
-+ "suitable DMA mask - aborting\n", ha->host_no);
- error = -ENODEV;
- goto error_free_irq;
- }
- #endif
-
- ha->request_ring = pci_alloc_consistent(ha->pdev,
-- ((REQUEST_ENTRY_CNT + 1) * (sizeof(request_t))),
-+ ((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)),
- &ha->request_dma);
- if (!ha->request_ring) {
- printk(KERN_INFO "qla1280: Failed to get request memory\n");
-@@ -4652,7 +4575,7 @@ qla1280_probe_one(struct pci_dev *pdev,
- }
-
- ha->response_ring = pci_alloc_consistent(ha->pdev,
-- ((RESPONSE_ENTRY_CNT + 1) * (sizeof(struct response))),
-+ ((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)),
- &ha->response_dma);
- if (!ha->response_ring) {
- printk(KERN_INFO "qla1280: Failed to get response memory\n");
-@@ -4735,7 +4658,7 @@ qla1280_probe_one(struct pci_dev *pdev,
-
- #if LINUX_VERSION_CODE >= 0x020600
- error_disable_adapter:
-- WRT_REG_WORD(&ha->iobase->ictrl, 0);
-+ qla1280_disable_intrs(ha);
- #endif
- error_free_irq:
- free_irq(pdev->irq, ha);
-@@ -4747,11 +4670,11 @@ qla1280_probe_one(struct pci_dev *pdev,
- #endif
- error_free_response_ring:
- pci_free_consistent(ha->pdev,
-- ((RESPONSE_ENTRY_CNT + 1) * (sizeof(struct response))),
-+ ((RESPONSE_ENTRY_CNT + 1) * sizeof(struct response)),
- ha->response_ring, ha->response_dma);
- error_free_request_ring:
- pci_free_consistent(ha->pdev,
-- ((REQUEST_ENTRY_CNT + 1) * (sizeof(request_t))),
-+ ((REQUEST_ENTRY_CNT + 1) * sizeof(request_t)),
- ha->request_ring, ha->request_dma);
- error_put_host:
- scsi_host_put(host);
-@@ -4772,7 +4695,7 @@ qla1280_remove_one(struct pci_dev *pdev)
- scsi_remove_host(host);
- #endif
-
-- WRT_REG_WORD(&ha->iobase->ictrl, 0);
-+ qla1280_disable_intrs(ha);
-
- free_irq(pdev->irq, ha);
-
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/qla1280.h linux_HEAD/drivers/scsi/qla1280.h
---- linux-2.6.12/drivers/scsi/qla1280.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/qla1280.h 2005-07-03 19:45:14.000000000 +0200
-@@ -94,9 +94,6 @@
- #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */
- #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */
-
--/* Number of segments 1 - 65535 */
--#define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */
+-#
+-# Hardware crypto devices
+-#
-
- /*
- * SCSI Request Block structure (sp) that is placed
- * on cmd->SCp location of every I/O
-@@ -378,29 +375,23 @@ struct nvram {
- uint16_t unused_12; /* 12, 13 */
- uint16_t unused_14; /* 14, 15 */
-
-- union {
-- uint8_t c;
-- struct {
-- uint8_t reserved:2;
-- uint8_t burst_enable:1;
-- uint8_t reserved_1:1;
-- uint8_t fifo_threshold:4;
-- } f;
-+ struct {
-+ uint8_t reserved:2;
-+ uint8_t burst_enable:1;
-+ uint8_t reserved_1:1;
-+ uint8_t fifo_threshold:4;
- } isp_config; /* 16 */
-
- /* Termination
- * 0 = Disable, 1 = high only, 3 = Auto term
- */
-- union {
-- uint8_t c;
-- struct {
-- uint8_t scsi_bus_1_control:2;
-- uint8_t scsi_bus_0_control:2;
-- uint8_t unused_0:1;
-- uint8_t unused_1:1;
-- uint8_t unused_2:1;
-- uint8_t auto_term_support:1;
-- } f;
-+ struct {
-+ uint8_t scsi_bus_1_control:2;
-+ uint8_t scsi_bus_0_control:2;
-+ uint8_t unused_0:1;
-+ uint8_t unused_1:1;
-+ uint8_t unused_2:1;
-+ uint8_t auto_term_support:1;
- } termination; /* 17 */
-
- uint16_t isp_parameter; /* 18, 19 */
-@@ -460,18 +451,15 @@ struct nvram {
- uint16_t unused_38; /* 38, 39 */
-
- struct {
-- union {
-- uint8_t c;
-- struct {
-- uint8_t renegotiate_on_error:1;
-- uint8_t stop_queue_on_check:1;
-- uint8_t auto_request_sense:1;
-- uint8_t tag_queuing:1;
-- uint8_t enable_sync:1;
-- uint8_t enable_wide:1;
-- uint8_t parity_checking:1;
-- uint8_t disconnect_allowed:1;
-- } f;
-+ struct {
-+ uint8_t renegotiate_on_error:1;
-+ uint8_t stop_queue_on_check:1;
-+ uint8_t auto_request_sense:1;
-+ uint8_t tag_queuing:1;
-+ uint8_t enable_sync:1;
-+ uint8_t enable_wide:1;
-+ uint8_t parity_checking:1;
-+ uint8_t disconnect_allowed:1;
- } parameter; /* 40 */
-
- uint8_t execution_throttle; /* 41 */
-@@ -528,23 +516,23 @@ struct cmd_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t sys_define; /* System defined. */
- uint8_t entry_status; /* Entry Status. */
-- uint32_t handle; /* System handle. */
-+ __le32 handle; /* System handle. */
- uint8_t lun; /* SCSI LUN */
- uint8_t target; /* SCSI ID */
-- uint16_t cdb_len; /* SCSI command length. */
-- uint16_t control_flags; /* Control flags. */
-- uint16_t reserved;
-- uint16_t timeout; /* Command timeout. */
-- uint16_t dseg_count; /* Data segment count. */
-+ __le16 cdb_len; /* SCSI command length. */
-+ __le16 control_flags; /* Control flags. */
-+ __le16 reserved;
-+ __le16 timeout; /* Command timeout. */
-+ __le16 dseg_count; /* Data segment count. */
- uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
-- uint32_t dseg_0_address; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-- uint32_t dseg_2_address; /* Data segment 2 address. */
-- uint32_t dseg_2_length; /* Data segment 2 length. */
-- uint32_t dseg_3_address; /* Data segment 3 address. */
-- uint32_t dseg_3_length; /* Data segment 3 length. */
-+ __le32 dseg_0_address; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address; /* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
-+ __le32 dseg_2_address; /* Data segment 2 address. */
-+ __le32 dseg_2_length; /* Data segment 2 length. */
-+ __le32 dseg_3_address; /* Data segment 3 address. */
-+ __le32 dseg_3_length; /* Data segment 3 length. */
- };
-
- /*
-@@ -556,21 +544,21 @@ struct cont_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t sys_define; /* System defined. */
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved; /* Reserved */
-- uint32_t dseg_0_address; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-- uint32_t dseg_2_address; /* Data segment 2 address. */
-- uint32_t dseg_2_length; /* Data segment 2 length. */
-- uint32_t dseg_3_address; /* Data segment 3 address. */
-- uint32_t dseg_3_length; /* Data segment 3 length. */
-- uint32_t dseg_4_address; /* Data segment 4 address. */
-- uint32_t dseg_4_length; /* Data segment 4 length. */
-- uint32_t dseg_5_address; /* Data segment 5 address. */
-- uint32_t dseg_5_length; /* Data segment 5 length. */
-- uint32_t dseg_6_address; /* Data segment 6 address. */
-- uint32_t dseg_6_length; /* Data segment 6 length. */
-+ __le32 reserved; /* Reserved */
-+ __le32 dseg_0_address; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address; /* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
-+ __le32 dseg_2_address; /* Data segment 2 address. */
-+ __le32 dseg_2_length; /* Data segment 2 length. */
-+ __le32 dseg_3_address; /* Data segment 3 address. */
-+ __le32 dseg_3_length; /* Data segment 3 length. */
-+ __le32 dseg_4_address; /* Data segment 4 address. */
-+ __le32 dseg_4_length; /* Data segment 4 length. */
-+ __le32 dseg_5_address; /* Data segment 5 address. */
-+ __le32 dseg_5_length; /* Data segment 5 length. */
-+ __le32 dseg_6_address; /* Data segment 6 address. */
-+ __le32 dseg_6_length; /* Data segment 6 length. */
- };
-
- /*
-@@ -586,22 +574,22 @@ struct response {
- #define RF_FULL BIT_1 /* Full */
- #define RF_BAD_HEADER BIT_2 /* Bad header. */
- #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
-- uint32_t handle; /* System handle. */
-- uint16_t scsi_status; /* SCSI status. */
-- uint16_t comp_status; /* Completion status. */
-- uint16_t state_flags; /* State flags. */
--#define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
--#define SF_GOT_SENSE BIT_13 /* Got Sense */
--#define SF_GOT_STATUS BIT_12 /* Got Status */
--#define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
--#define SF_SENT_CDB BIT_10 /* Send CDB */
--#define SF_GOT_TARGET BIT_9 /* */
--#define SF_GOT_BUS BIT_8 /* */
-- uint16_t status_flags; /* Status flags. */
-- uint16_t time; /* Time. */
-- uint16_t req_sense_length; /* Request sense data length. */
-- uint32_t residual_length; /* Residual transfer length. */
-- uint16_t reserved[4];
-+ __le32 handle; /* System handle. */
-+ __le16 scsi_status; /* SCSI status. */
-+ __le16 comp_status; /* Completion status. */
-+ __le16 state_flags; /* State flags. */
-+#define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
-+#define SF_GOT_SENSE BIT_13 /* Got Sense */
-+#define SF_GOT_STATUS BIT_12 /* Got Status */
-+#define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
-+#define SF_SENT_CDB BIT_10 /* Send CDB */
-+#define SF_GOT_TARGET BIT_9 /* */
-+#define SF_GOT_BUS BIT_8 /* */
-+ __le16 status_flags; /* Status flags. */
-+ __le16 time; /* Time. */
-+ __le16 req_sense_length;/* Request sense data length. */
-+ __le32 residual_length; /* Residual transfer length. */
-+ __le16 reserved[4];
- uint8_t req_sense_data[32]; /* Request sense data. */
- };
-
-@@ -614,7 +602,7 @@ struct mrk_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t sys_define; /* System defined. */
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved;
-+ __le32 reserved;
- uint8_t lun; /* SCSI LUN */
- uint8_t target; /* SCSI ID */
- uint8_t modifier; /* Modifier (7-0). */
-@@ -638,11 +626,11 @@ struct ecmd_entry {
- uint32_t handle; /* System handle. */
- uint8_t lun; /* SCSI LUN */
- uint8_t target; /* SCSI ID */
-- uint16_t cdb_len; /* SCSI command length. */
-- uint16_t control_flags; /* Control flags. */
-- uint16_t reserved;
-- uint16_t timeout; /* Command timeout. */
-- uint16_t dseg_count; /* Data segment count. */
-+ __le16 cdb_len; /* SCSI command length. */
-+ __le16 control_flags; /* Control flags. */
-+ __le16 reserved;
-+ __le16 timeout; /* Command timeout. */
-+ __le16 dseg_count; /* Data segment count. */
- uint8_t scsi_cdb[88]; /* SCSI command words. */
- };
-
-@@ -655,20 +643,20 @@ typedef struct {
- uint8_t entry_count; /* Entry count. */
- uint8_t sys_define; /* System defined. */
- uint8_t entry_status; /* Entry Status. */
-- uint32_t handle; /* System handle. */
-+ __le32 handle; /* System handle. */
- uint8_t lun; /* SCSI LUN */
- uint8_t target; /* SCSI ID */
-- uint16_t cdb_len; /* SCSI command length. */
-- uint16_t control_flags; /* Control flags. */
-- uint16_t reserved;
-- uint16_t timeout; /* Command timeout. */
-- uint16_t dseg_count; /* Data segment count. */
-+ __le16 cdb_len; /* SCSI command length. */
-+ __le16 control_flags; /* Control flags. */
-+ __le16 reserved;
-+ __le16 timeout; /* Command timeout. */
-+ __le16 dseg_count; /* Data segment count. */
- uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
-- uint32_t reserved_1[2]; /* unused */
-- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-+ __le32 reserved_1[2]; /* unused */
-+ __le32 dseg_0_address[2]; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address[2]; /* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
- } cmd_a64_entry_t, request_t;
-
- /*
-@@ -680,16 +668,16 @@ struct cont_a64_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t sys_define; /* System defined. */
- uint8_t entry_status; /* Entry Status. */
-- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-- uint32_t dseg_2_address[2]; /* Data segment 2 address. */
-- uint32_t dseg_2_length; /* Data segment 2 length. */
-- uint32_t dseg_3_address[2]; /* Data segment 3 address. */
-- uint32_t dseg_3_length; /* Data segment 3 length. */
-- uint32_t dseg_4_address[2]; /* Data segment 4 address. */
-- uint32_t dseg_4_length; /* Data segment 4 length. */
-+ __le32 dseg_0_address[2]; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address[2]; /* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
-+ __le32 dseg_2_address[2]; /* Data segment 2 address. */
-+ __le32 dseg_2_length; /* Data segment 2 length. */
-+ __le32 dseg_3_address[2]; /* Data segment 3 address. */
-+ __le32 dseg_3_length; /* Data segment 3 length. */
-+ __le32 dseg_4_address[2]; /* Data segment 4 address. */
-+ __le32 dseg_4_length; /* Data segment 4 length. */
- };
-
- /*
-@@ -701,10 +689,10 @@ struct elun_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status not used. */
-- uint32_t reserved_2;
-- uint16_t lun; /* Bit 15 is bus number. */
-- uint16_t reserved_4;
-- uint32_t option_flags;
-+ __le32 reserved_2;
-+ __le16 lun; /* Bit 15 is bus number. */
-+ __le16 reserved_4;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t reserved_5;
- uint8_t command_count; /* Number of ATIOs allocated. */
-@@ -714,8 +702,8 @@ struct elun_entry {
- /* commands (2-26). */
- uint8_t group_7_length; /* SCSI CDB length for group 7 */
- /* commands (2-26). */
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t reserved_6[20];
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 reserved_6[20];
- };
-
- /*
-@@ -729,20 +717,20 @@ struct modify_lun_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun; /* SCSI LUN */
- uint8_t reserved_3;
- uint8_t operators;
- uint8_t reserved_4;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t reserved_5;
- uint8_t command_count; /* Number of ATIOs allocated. */
- uint8_t immed_notify_count; /* Number of Immediate Notify */
- /* entries allocated. */
-- uint16_t reserved_6;
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t reserved_7[20];
-+ __le16 reserved_6;
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 reserved_7[20];
- };
-
- /*
-@@ -754,20 +742,20 @@ struct notify_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun;
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t reserved_4;
- uint8_t tag_value; /* Received queue tag message value */
- uint8_t tag_type; /* Received queue tag message type */
- /* entries allocated. */
-- uint16_t seq_id;
-+ __le16 seq_id;
- uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
-- uint16_t reserved_5[8];
-+ __le16 reserved_5[8];
- uint8_t sense_data[18];
- };
-
-@@ -780,16 +768,16 @@ struct nack_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun;
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t event;
-- uint16_t seq_id;
-- uint16_t reserved_4[22];
-+ __le16 seq_id;
-+ __le16 reserved_4[22];
- };
-
- /*
-@@ -801,12 +789,12 @@ struct atio_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun;
- uint8_t initiator_id;
- uint8_t cdb_len;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t scsi_status;
- uint8_t tag_value; /* Received queue tag message value */
-@@ -824,28 +812,28 @@ struct ctio_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun; /* SCSI LUN */
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t scsi_status;
- uint8_t tag_value; /* Received queue tag message value */
- uint8_t tag_type; /* Received queue tag message type */
-- uint32_t transfer_length;
-- uint32_t residual;
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t dseg_count; /* Data segment count. */
-- uint32_t dseg_0_address; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-- uint32_t dseg_2_address; /* Data segment 2 address. */
-- uint32_t dseg_2_length; /* Data segment 2 length. */
-- uint32_t dseg_3_address; /* Data segment 3 address. */
-- uint32_t dseg_3_length; /* Data segment 3 length. */
-+ __le32 transfer_length;
-+ __le32 residual;
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 dseg_count; /* Data segment count. */
-+ __le32 dseg_0_address; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address; /* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
-+ __le32 dseg_2_address; /* Data segment 2 address. */
-+ __le32 dseg_2_length; /* Data segment 2 length. */
-+ __le32 dseg_3_address; /* Data segment 3 address. */
-+ __le32 dseg_3_length; /* Data segment 3 length. */
- };
-
- /*
-@@ -857,24 +845,24 @@ struct ctio_ret_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun; /* SCSI LUN */
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t scsi_status;
- uint8_t tag_value; /* Received queue tag message value */
- uint8_t tag_type; /* Received queue tag message type */
-- uint32_t transfer_length;
-- uint32_t residual;
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t dseg_count; /* Data segment count. */
-- uint32_t dseg_0_address; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address; /* Data segment 1 address. */
-- uint16_t dseg_1_length; /* Data segment 1 length. */
-+ __le32 transfer_length;
-+ __le32 residual;
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 dseg_count; /* Data segment count. */
-+ __le32 dseg_0_address; /* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address; /* Data segment 1 address. */
-+ __le16 dseg_1_length; /* Data segment 1 length. */
- uint8_t sense_data[18];
- };
-
-@@ -887,25 +875,25 @@ struct ctio_a64_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun; /* SCSI LUN */
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t scsi_status;
- uint8_t tag_value; /* Received queue tag message value */
- uint8_t tag_type; /* Received queue tag message type */
-- uint32_t transfer_length;
-- uint32_t residual;
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t dseg_count; /* Data segment count. */
-- uint32_t reserved_4[2];
-- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
-- uint32_t dseg_0_length; /* Data segment 0 length. */
-- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
-- uint32_t dseg_1_length; /* Data segment 1 length. */
-+ __le32 transfer_length;
-+ __le32 residual;
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 dseg_count; /* Data segment count. */
-+ __le32 reserved_4[2];
-+ __le32 dseg_0_address[2];/* Data segment 0 address. */
-+ __le32 dseg_0_length; /* Data segment 0 length. */
-+ __le32 dseg_1_address[2];/* Data segment 1 address. */
-+ __le32 dseg_1_length; /* Data segment 1 length. */
- };
-
- /*
-@@ -917,21 +905,21 @@ struct ctio_a64_ret_entry {
- uint8_t entry_count; /* Entry count. */
- uint8_t reserved_1;
- uint8_t entry_status; /* Entry Status. */
-- uint32_t reserved_2;
-+ __le32 reserved_2;
- uint8_t lun; /* SCSI LUN */
- uint8_t initiator_id;
- uint8_t reserved_3;
- uint8_t target_id;
-- uint32_t option_flags;
-+ __le32 option_flags;
- uint8_t status;
- uint8_t scsi_status;
- uint8_t tag_value; /* Received queue tag message value */
- uint8_t tag_type; /* Received queue tag message type */
-- uint32_t transfer_length;
-- uint32_t residual;
-- uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-- uint16_t dseg_count; /* Data segment count. */
-- uint16_t reserved_4[7];
-+ __le32 transfer_length;
-+ __le32 residual;
-+ __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
-+ __le16 dseg_count; /* Data segment count. */
-+ __le16 reserved_4[7];
- uint8_t sense_data[18];
- };
+-#
+-# Library routines
+-#
+-# CONFIG_CRC_CCITT is not set
+-# CONFIG_CRC16 is not set
+-CONFIG_CRC32=y
+-# CONFIG_LIBCRC32C is not set
+-CONFIG_ZLIB_INFLATE=m
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/workpad_defconfig linux-mips/arch/mips/configs/workpad_defconfig
+--- kernel.org/arch/mips/configs/workpad_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/workpad_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:17 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:56 2005
+ #
+ CONFIG_MIPS=y
-@@ -979,14 +967,6 @@ struct ctio_a64_ret_entry {
- #define CS_RETRY 0x82 /* Driver defined */
+@@ -157,6 +157,7 @@
+ CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -165,7 +166,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -309,7 +309,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- /*
-- * ISP status entry - SCSI status byte bit definitions.
-- */
--#define SS_CHECK_CONDITION BIT_1
--#define SS_CONDITION_MET BIT_2
--#define SS_BUSY_CONDITION BIT_3
--#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
--
--/*
- * ISP target entries - Option flags bit definitions.
- */
- #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
-@@ -1082,10 +1062,6 @@ struct scsi_qla_host {
- uint32_t reset_active:1; /* 3 */
- uint32_t abort_isp_active:1; /* 4 */
- uint32_t disable_risc_code_load:1; /* 5 */
-- uint32_t enable_64bit_addressing:1; /* 6 */
-- uint32_t in_reset:1; /* 7 */
-- uint32_t ints_enabled:1;
-- uint32_t ignore_nvram:1;
- #ifdef __ia64__
- uint32_t use_pci_vchannel:1;
- #endif
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/sgiwd93.c linux_HEAD/drivers/scsi/sgiwd93.c
---- linux-2.6.12/drivers/scsi/sgiwd93.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/sgiwd93.c 2005-04-12 14:34:50.000000000 +0200
-@@ -33,7 +33,6 @@
- #include "scsi.h"
- #include <scsi/scsi_host.h>
- #include "wd33c93.h"
--#include "sgiwd93.h"
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/configs/yosemite_defconfig linux-mips/arch/mips/configs/yosemite_defconfig
+--- kernel.org/arch/mips/configs/yosemite_defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/configs/yosemite_defconfig 2006-01-10 11:21:15.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:07:19 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:03:57 2005
+ #
+ CONFIG_MIPS=y
- #include <linux/stat.h>
+@@ -118,7 +118,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -170,7 +169,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -296,7 +294,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
-@@ -320,7 +319,6 @@ static int sgiwd93_bus_reset(Scsi_Cmnd *
- * on 64-bit systems with memory outside the compat address spaces.
- */
- static Scsi_Host_Template driver_template = {
-- .proc_name = "SGIWD93",
- .name = "SGI WD93",
- .detect = sgiwd93_detect,
- .release = sgiwd93_release,
-@@ -328,10 +326,12 @@ static Scsi_Host_Template driver_templat
- .eh_abort_handler = wd33c93_abort,
- .eh_bus_reset_handler = sgiwd93_bus_reset,
- .eh_host_reset_handler = wd33c93_host_reset,
-- .can_queue = CAN_QUEUE,
-+ .proc_info = wd33c93_proc_info,
-+ .proc_name = "SGIWD93",
-+ .can_queue = 16,
- .this_id = 7,
- .sg_tablesize = SG_ALL,
-- .cmd_per_lun = CMD_PER_LUN,
-+ .cmd_per_lun = 8,
- .use_clustering = DISABLE_CLUSTERING,
- };
- #include "scsi_module.c"
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/sgiwd93.h linux_HEAD/drivers/scsi/sgiwd93.h
---- linux-2.6.12/drivers/scsi/sgiwd93.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/sgiwd93.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,24 +0,0 @@
--/* $Id: sgiwd93.h,v 1.5 1998/08/25 09:18:50 ralf Exp $
-- * sgiwd93.h: SGI WD93 scsi definitions.
-- *
-- * Copyright (C) 1996 David S. Miller (dm at engr.sgi.com)
-- */
--#ifndef _SGIWD93_H
--#define _SGIWD93_H
--
--#ifndef CMD_PER_LUN
--#define CMD_PER_LUN 8
--#endif
--
--#ifndef CAN_QUEUE
--#define CAN_QUEUE 16
--#endif
--
--int sgiwd93_detect(Scsi_Host_Template *);
--int sgiwd93_release(struct Scsi_Host *instance);
--const char *wd33c93_info(void);
--int wd33c93_queuecommand(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
--int wd33c93_abort(Scsi_Cmnd *);
--int wd33c93_host_reset(Scsi_Cmnd * SCpnt);
--
--#endif /* !(_SGIWD93_H) */
-diff -urpNX dontdiff linux-2.6.12/drivers/scsi/sym53c8xx_defs.h linux_HEAD/drivers/scsi/sym53c8xx_defs.h
---- linux-2.6.12/drivers/scsi/sym53c8xx_defs.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/scsi/sym53c8xx_defs.h 2005-04-08 22:41:10.000000000 +0200
-@@ -314,9 +314,19 @@
- #define writew_b2l __raw_writew
- #define writel_b2l __raw_writel
- #define readw_raw __raw_readw
--#define readl_raw __raw_readl
-+#define readl_raw(a) __raw_readl((unsigned long)(a))
- #define writew_raw __raw_writew
--#define writel_raw __raw_writel
-+#define writel_raw(v,a) __raw_writel(v,(unsigned long)(a))
-+#else /* Other big-endian */
-+#elif defined(__mips__)
-+#define readw_l2b readw
-+#define readl_l2b readl
-+#define writew_b2l writew
-+#define writel_b2l writel
-+#define inw_l2b inw
-+#define inl_l2b inl
-+#define outw_b2l outw
-+#define outl_b2l outl
- #else /* Other big-endian */
- #define readw_l2b readw
- #define readl_l2b readl
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/Makefile linux_HEAD/drivers/serial/Makefile
---- linux-2.6.12/drivers/serial/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/Makefile 2005-04-08 20:58:25.000000000 +0200
-@@ -50,5 +50,4 @@ obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
- obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
- obj-$(CONFIG_SERIAL_JSM) += jsm/
- obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
--obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
- obj-$(CONFIG_BLK_DEV_SGIIOC4) += ioc4_serial.o
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/au1x00_uart.c linux_HEAD/drivers/serial/au1x00_uart.c
---- linux-2.6.12/drivers/serial/au1x00_uart.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/au1x00_uart.c 2005-07-01 12:10:00.000000000 +0200
-@@ -67,30 +67,7 @@
- #define is_real_interrupt(irq) ((irq) != 0)
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/defconfig linux-mips/arch/mips/defconfig
+--- kernel.org/arch/mips/defconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/defconfig 2006-01-10 11:30:59.000000000 +0000
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.15-rc2
+-# Thu Nov 24 01:05:49 2005
++# Linux kernel version: 2.6.15-rc5
++# Sat Dec 17 18:02:11 2005
+ #
+ CONFIG_MIPS=y
- static struct old_serial_port old_serial_port[] = {
-- { .baud_base = 0,
-- .iomem_base = (u8 *)UART0_ADDR,
-- .irq = AU1000_UART0_INT,
-- .flags = STD_COM_FLAGS,
-- .iomem_reg_shift = 2,
-- }, {
-- .baud_base = 0,
-- .iomem_base = (u8 *)UART1_ADDR,
-- .irq = AU1000_UART1_INT,
-- .flags = STD_COM_FLAGS,
-- .iomem_reg_shift = 2
-- }, {
-- .baud_base = 0,
-- .iomem_base = (u8 *)UART2_ADDR,
-- .irq = AU1000_UART2_INT,
-- .flags = STD_COM_FLAGS,
-- .iomem_reg_shift = 2
-- }, {
-- .baud_base = 0,
-- .iomem_base = (u8 *)UART3_ADDR,
-- .irq = AU1000_UART3_INT,
-- .flags = STD_COM_FLAGS,
-- .iomem_reg_shift = 2
-- }
-+ SERIAL_PORT_DFNS
- };
+@@ -123,7 +123,6 @@
+ # CONFIG_64BIT_PHYS_ADDR is not set
+ # CONFIG_CPU_ADVANCED is not set
+ CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_LLDSCD=y
+ CONFIG_CPU_HAS_SYNC=y
+ CONFIG_GENERIC_HARDIRQS=y
+ CONFIG_GENERIC_IRQ_PROBE=y
+@@ -164,6 +163,7 @@
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
+ CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_EMBEDDED=y
+ CONFIG_KALLSYMS=y
+ # CONFIG_KALLSYMS_EXTRA_PASS is not set
+@@ -172,7 +172,6 @@
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+ CONFIG_SHMEM=y
+ CONFIG_CC_ALIGN_FUNCTIONS=0
+ CONFIG_CC_ALIGN_LABELS=0
+@@ -505,7 +504,6 @@
+ # CONFIG_IEEE80211_DEBUG is not set
+ CONFIG_IEEE80211_CRYPT_WEP=m
+ CONFIG_IEEE80211_CRYPT_CCMP=m
+-CONFIG_IEEE80211_CRYPT_TKIP=m
- #define UART_NR ARRAY_SIZE(old_serial_port)
-@@ -803,7 +780,6 @@ serial8250_set_termios(struct uart_port
- */
- baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
- quot = serial8250_get_divisor(port, baud);
-- quot = 0x35; /* FIXME */
+ #
+ # Device Drivers
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/cpu-probe.c linux-mips/arch/mips/kernel/cpu-probe.c
+--- kernel.org/arch/mips/kernel/cpu-probe.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/cpu-probe.c 2006-01-10 11:21:15.000000000 +0000
+@@ -242,9 +242,15 @@
+ break;
+ case PRID_IMP_VR41XX:
+ switch (c->processor_id & 0xf0) {
++#ifndef CONFIG_VR4181
+ case PRID_REV_VR4111:
+ c->cputype = CPU_VR4111;
+ break;
++#else
++ case PRID_REV_VR4181:
++ c->cputype = CPU_VR4181;
++ break;
++#endif
+ case PRID_REV_VR4121:
+ c->cputype = CPU_VR4121;
+ break;
+@@ -435,6 +441,9 @@
+ }
+ }
- /*
- * Work around a bug in the Oxford Semiconductor 952 rev B
-@@ -869,6 +845,7 @@ serial8250_set_termios(struct uart_port
++static char unknown_isa[] __initdata = KERN_ERR \
++ "Unsupported ISA type, c0.config0: %d.";
++
+ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
+ {
+ unsigned int config0;
+@@ -447,16 +456,37 @@
+ isa = (config0 & MIPS_CONF_AT) >> 13;
+ switch (isa) {
+ case 0:
+- c->isa_level = MIPS_CPU_ISA_M32;
++ switch ((config0 >> 10) & 7) {
++ case 0:
++ c->isa_level = MIPS_CPU_ISA_M32R1;
++ break;
++ case 1:
++ c->isa_level = MIPS_CPU_ISA_M32R2;
++ break;
++ default:
++ goto unknown;
++ }
+ break;
+ case 2:
+- c->isa_level = MIPS_CPU_ISA_M64;
++ switch ((config0 >> 10) & 7) {
++ case 0:
++ c->isa_level = MIPS_CPU_ISA_M64R1;
++ break;
++ case 1:
++ c->isa_level = MIPS_CPU_ISA_M64R2;
+ break;
+ default:
+- panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
++ goto unknown;
++ }
++ break;
++ default:
++ goto unknown;
+ }
- serial_out(up, UART_IER, up->ier);
- serial_outp(up, 0x28, quot & 0xffff);
-+ serial_out(up, UART_LCR, cval); /* reset DLAB */
- up->lcr = cval; /* Save LCR */
- if (up->port.type != PORT_16750) {
- if (fcr & UART_FCR_ENABLE_FIFO) {
-@@ -1071,7 +1048,7 @@ static void __init serial8250_isa_init_p
- i++, up++) {
- up->port.iobase = old_serial_port[i].port;
- up->port.irq = old_serial_port[i].irq;
-- up->port.uartclk = get_au1x00_uart_baud_base();
-+ up->port.uartclk = get_au1x00_uart_baud_base() * 16;
- up->port.flags = old_serial_port[i].flags;
- up->port.hub6 = old_serial_port[i].hub6;
- up->port.membase = old_serial_port[i].iomem_base;
-@@ -1209,7 +1186,7 @@ static int __init serial8250_console_set
- return uart_set_options(port, co, baud, parity, bits, flow);
+ return config0 & MIPS_CONF_M;
++
++unknown:
++ panic(unknown_isa, config0);
}
--extern struct uart_driver serial8250_reg;
-+static struct uart_driver serial8250_reg;
- static struct console serial8250_console = {
- .name = "ttyS",
- .write = serial8250_console_write,
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/dz.c linux_HEAD/drivers/serial/dz.c
---- linux-2.6.12/drivers/serial/dz.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/dz.c 2005-07-03 16:44:33.000000000 +0200
-@@ -645,9 +645,9 @@ static void __init dz_init_ports(void)
-
- if (mips_machtype == MACH_DS23100 ||
- mips_machtype == MACH_DS5100)
-- base = (unsigned long) KN01_DZ11_BASE;
-+ base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_DZ11);
- else
-- base = (unsigned long) KN02_DZ11_BASE;
-+ base = CKSEG1ADDR(KN02_SLOT_BASE + KN02_DZ11);
+ static inline unsigned int decode_config1(struct cpuinfo_mips *c)
+@@ -568,7 +598,6 @@
+ break;
+ case PRID_IMP_34K:
+ c->cputype = CPU_34K;
+- c->isa_level = MIPS_CPU_ISA_M32;
+ break;
+ }
+ }
+@@ -647,7 +676,7 @@
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_PR4450:
+ c->cputype = CPU_PR4450;
+- c->isa_level = MIPS_CPU_ISA_M32;
++ c->isa_level = MIPS_CPU_ISA_M32R1;
+ break;
+ default:
+ panic("Unknown Philips Core!"); /* REVISIT: die? */
+@@ -690,8 +719,10 @@
+ if (c->options & MIPS_CPU_FPU) {
+ c->fpu_id = cpu_get_fpu_id();
- for (i = 0, dport = dz_ports; i < DZ_NB_PORT; i++, dport++) {
- spin_lock_init(&dport->port.lock);
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/ip22zilog.c linux_HEAD/drivers/serial/ip22zilog.c
---- linux-2.6.12/drivers/serial/ip22zilog.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/ip22zilog.c 2005-04-17 05:59:54.000000000 +0200
-@@ -881,6 +881,7 @@ ip22zilog_set_termios(struct uart_port *
- up->cflag = termios->c_cflag;
+- if (c->isa_level == MIPS_CPU_ISA_M32 ||
+- c->isa_level == MIPS_CPU_ISA_M64) {
++ if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
++ c->isa_level == MIPS_CPU_ISA_M32R2 ||
++ c->isa_level == MIPS_CPU_ISA_M64R1 ||
++ c->isa_level == MIPS_CPU_ISA_M64R2) {
+ if (c->fpu_id & MIPS_FPIR_3D)
+ c->ases |= MIPS_ASE_MIPS3D;
+ }
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/process.c linux-mips/arch/mips/kernel/process.c
+--- kernel.org/arch/mips/kernel/process.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/process.c 2006-01-10 11:21:15.000000000 +0000
+@@ -205,7 +205,7 @@
+ return 1;
+ }
- ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
-+ uart_update_timeout(port, termios->c_cflag, baud);
+-void dump_regs(elf_greg_t *gp, struct pt_regs *regs)
++void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs)
+ {
+ int i;
- spin_unlock_irqrestore(&up->port.lock, flags);
+@@ -231,7 +231,7 @@
+ {
+ struct thread_info *ti = tsk->thread_info;
+ long ksp = (unsigned long)ti + THREAD_SIZE - 32;
+- dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1);
++ elf_dump_regs(&(*regs)[0], (struct pt_regs *) ksp - 1);
+ return 1;
}
-@@ -1047,6 +1048,8 @@ ip22serial_console_termios(struct consol
- }
- con->cflag = cflag | CS8; /* 8N1 */
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/ptrace.c linux-mips/arch/mips/kernel/ptrace.c
+--- kernel.org/arch/mips/kernel/ptrace.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/ptrace.c 2006-01-10 11:30:59.000000000 +0000
+@@ -21,12 +21,12 @@
+ #include <linux/mm.h>
+ #include <linux/errno.h>
+ #include <linux/ptrace.h>
+-#include <linux/audit.h>
+ #include <linux/smp.h>
+ #include <linux/smp_lock.h>
+ #include <linux/user.h>
+ #include <linux/security.h>
+-#include <linux/signal.h>
++#include <linux/audit.h>
++#include <linux/seccomp.h>
+
+ #include <asm/byteorder.h>
+ #include <asm/cpu.h>
+@@ -280,12 +280,8 @@
+ ret = -EIO;
+ goto out;
+ }
+- if (child->thread.dsp.used_dsp) {
+ dregs = __get_dsp_regs(child);
+ tmp = (unsigned long) (dregs[addr - DSP_BASE]);
+- } else {
+- tmp = -1; /* DSP registers yet used */
+- }
+ break;
+ }
+ case DSP_CONTROL:
+@@ -476,12 +472,16 @@
+ */
+ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
+ {
++ /* do the secure computing check first */
++ secure_computing(regs->orig_eax);
+
-+ uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud);
+ if (unlikely(current->audit_context) && entryexit)
+ audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]),
+ regs->regs[2]);
+
+ if (!(current->ptrace & PT_PTRACED))
+ goto out;
++
+ if (!test_thread_flag(TIF_SYSCALL_TRACE))
+ goto out;
+
+@@ -499,9 +499,14 @@
+ send_sig(current->exit_code, current, 1);
+ current->exit_code = 0;
+ }
+- out:
++
++out:
++ /* There is no ->orig_eax and that's quite intensional for now making
++ this work will require some work in various other place before it's
++ more than a placebo. */
++
+ if (unlikely(current->audit_context) && !entryexit)
+- audit_syscall_entry(current, audit_arch(), regs->regs[2],
++ audit_syscall_entry(current, audit_arch(), regs->orig_eax,
+ regs->regs[4], regs->regs[5],
+ regs->regs[6], regs->regs[7]);
+ }
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/ptrace32.c linux-mips/arch/mips/kernel/ptrace32.c
+--- kernel.org/arch/mips/kernel/ptrace32.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/ptrace32.c 2006-01-10 11:21:15.000000000 +0000
+@@ -215,12 +215,8 @@
+ ret = -EIO;
+ goto out_tsk;
+ }
+- if (child->thread.dsp.used_dsp) {
+ dspreg_t *dregs = __get_dsp_regs(child);
+ tmp = (unsigned long) (dregs[addr - DSP_BASE]);
+- } else {
+- tmp = -1; /* DSP registers yet used */
+- }
+ break;
+ case DSP_CONTROL:
+ if (!cpu_has_dsp) {
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/signal32.c linux-mips/arch/mips/kernel/signal32.c
+--- kernel.org/arch/mips/kernel/signal32.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/signal32.c 2006-01-10 11:21:15.000000000 +0000
+@@ -588,7 +588,7 @@
+ err |= __put_user(regs->hi, &sc->sc_mdhi);
+ err |= __put_user(regs->lo, &sc->sc_mdlo);
+ if (cpu_has_dsp) {
+- err |= __put_user(rddsp(DSP_MASK), &sc->sc_hi1);
++ err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
+ err |= __put_user(mfhi1(), &sc->sc_hi1);
+ err |= __put_user(mflo1(), &sc->sc_lo1);
+ err |= __put_user(mfhi2(), &sc->sc_hi2);
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/time.c linux-mips/arch/mips/kernel/time.c
+--- kernel.org/arch/mips/kernel/time.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/time.c 2006-01-10 11:21:15.000000000 +0000
+@@ -507,14 +507,38 @@
+ return IRQ_HANDLED;
}
- static int __init ip22zilog_console_setup(struct console *con, char *options)
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/serial_txx9.c linux_HEAD/drivers/serial/serial_txx9.c
---- linux-2.6.12/drivers/serial/serial_txx9.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/serial_txx9.c 2005-07-01 12:10:01.000000000 +0200
-@@ -31,6 +31,7 @@
- * 1.01 Set fifosize to make tx_empry called properly.
- * Use standard uart_get_divisor.
- * 1.02 Cleanup. (import 8250.c changes)
-+ * 1.03 Fix low-latency mode. (import 8250.c changes)
- */
- #include <linux/config.h>
++int null_perf_irq(struct pt_regs *regs)
++{
++ return 0;
++}
++
++int (*perf_irq)(struct pt_regs *regs) = null_perf_irq;
++
++EXPORT_SYMBOL(null_perf_irq);
++EXPORT_SYMBOL(perf_irq);
++
+ asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
+ {
++ int r2 = cpu_has_mips_r2;
++
+ irq_enter();
+ kstat_this_cpu.irqs[irq]++;
-@@ -54,7 +55,7 @@
- #include <asm/io.h>
- #include <asm/irq.h>
++ /*
++ * Suckage alert:
++ * Before R2 of the architecture there was no way to see if a
++ * performance counter interrupt was pending, so we have to run the
++ * performance counter interrupt handler anyway.
++ */
++ if (!r2 || (read_c0_cause() & (1 << 26)))
++ if (perf_irq(regs))
++ goto out;
++
+ /* we keep interrupt disabled all the time */
++ if (!r2 || (read_c0_cause() & (1 << 30)))
+ timer_interrupt(irq, NULL, regs);
--static char *serial_version = "1.02";
-+static char *serial_version = "1.03";
- static char *serial_name = "TX39/49 Serial driver";
-
- #define PASS_LIMIT 256
-@@ -304,8 +305,11 @@ receive_chars(struct uart_txx9_port *up,
- /* The following is not allowed by the tty layer and
- unsafe. It should be fixed ASAP */
- if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
-- if(tty->low_latency)
-+ if (tty->low_latency) {
-+ spin_unlock(&up->port.lock);
- tty_flip_buffer_push(tty);
-+ spin_lock(&up->port.lock);
-+ }
- /* If this failed then we will throw away the
- bytes but must do so to clear interrupts */
- }
-@@ -356,7 +360,9 @@ receive_chars(struct uart_txx9_port *up,
- ignore_char:
- disr = sio_in(up, TXX9_SIDISR);
- } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
-+ spin_unlock(&up->port.lock);
- tty_flip_buffer_push(tty);
-+ spin_lock(&up->port.lock);
- *status = disr;
++out:
+ irq_exit();
}
-diff -urpNX dontdiff linux-2.6.12/drivers/serial/vr41xx_siu.c linux_HEAD/drivers/serial/vr41xx_siu.c
---- linux-2.6.12/drivers/serial/vr41xx_siu.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/serial/vr41xx_siu.c 1970-01-01 01:00:00.000000000 +0100
-@@ -1,1050 +0,0 @@
+@@ -628,7 +652,7 @@
+ mips_hpt_init = c0_hpt_init;
+ }
+
+- if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) ||
++ if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
+ (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
+ (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
+ /*
+diff -urN --ignore-space-change kernel.org/arch/mips/kernel/vpe.c linux-mips/arch/mips/kernel/vpe.c
+--- kernel.org/arch/mips/kernel/vpe.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/kernel/vpe.c 2006-01-10 11:21:15.000000000 +0000
+@@ -99,9 +99,9 @@
+
+ /* elfloader stuff */
+ void *load_addr;
+- u32 len;
++ unsigned long len;
+ char *pbuffer;
+- u32 plen;
++ unsigned long plen;
+
+ unsigned long __start;
+
+@@ -253,11 +253,11 @@
+ }
+
+ /* Find some VPE program space */
+-static void *alloc_progmem(u32 len)
++static void *alloc_progmem(unsigned long len)
+ {
+ #ifdef CONFIG_MIPS_VPE_LOADER_TOM
+ /* this means you must tell linux to use less memory than you physically have */
+- return (void *)((max_pfn * PAGE_SIZE) + KSEG0);
++ return pfn_to_kaddr(max_pfn);
+ #else
+ // simple grab some mem for now
+ return kmalloc(len, GFP_KERNEL);
+diff -urN --ignore-space-change kernel.org/arch/mips/lib/Makefile linux-mips/arch/mips/lib/Makefile
+--- kernel.org/arch/mips/lib/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/lib/Makefile 2006-01-10 11:21:15.000000000 +0000
+@@ -5,6 +5,4 @@
+ lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \
+ strnlen_user.o uncached.o
+
+-obj-y += iomap.o
+-
+ EXTRA_AFLAGS := $(CFLAGS)
+diff -urN --ignore-space-change kernel.org/arch/mips/lib/iomap.c linux-mips/arch/mips/lib/iomap.c
+--- kernel.org/arch/mips/lib/iomap.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/lib/iomap.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,78 +0,0 @@
-/*
-- * Driver for NEC VR4100 series Serial Interface Unit.
+- * iomap.c, Memory Mapped I/O routines for MIPS architecture.
- *
-- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
+- * This code is based on lib/iomap.c, by Linus Torvalds.
- *
-- * Based on drivers/serial/8250.c, by Russell King.
+- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
@@ -61236,7744 +3390,16612 @@
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- */
--#include <linux/config.h>
--
--#if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
--#define SUPPORT_SYSRQ
--#endif
--
--#include <linux/console.h>
--#include <linux/device.h>
--#include <linux/err.h>
--#include <linux/ioport.h>
--#include <linux/init.h>
--#include <linux/interrupt.h>
--#include <linux/module.h>
--#include <linux/serial.h>
--#include <linux/serial_core.h>
--#include <linux/serial_reg.h>
--#include <linux/tty.h>
--#include <linux/tty_flip.h>
--
--#include <asm/io.h>
--#include <asm/vr41xx/siu.h>
--#include <asm/vr41xx/vr41xx.h>
--
--#define SIU_PORTS_MAX 2
--#define SIU_BAUD_BASE 1152000
--#define SIU_MAJOR 204
--#define SIU_MINOR_BASE 82
--
--#define RX_MAX_COUNT 256
--#define TX_MAX_COUNT 15
--
--#define SIUIRSEL 0x08
-- #define TMICMODE 0x20
-- #define TMICTX 0x10
-- #define IRMSEL 0x0c
-- #define IRMSEL_HP 0x08
-- #define IRMSEL_TEMIC 0x04
-- #define IRMSEL_SHARP 0x00
-- #define IRUSESEL 0x02
-- #define SIRSEL 0x01
--
--struct siu_port {
-- unsigned int type;
-- unsigned int irq;
-- unsigned long start;
--};
--
--static const struct siu_port siu_type1_ports[] = {
-- { .type = PORT_VR41XX_SIU,
-- .irq = SIU_IRQ,
-- .start = 0x0c000000UL, },
--};
--
--#define SIU_TYPE1_NR_PORTS (sizeof(siu_type1_ports) / sizeof(struct siu_port))
--
--static const struct siu_port siu_type2_ports[] = {
-- { .type = PORT_VR41XX_SIU,
-- .irq = SIU_IRQ,
-- .start = 0x0f000800UL, },
-- { .type = PORT_VR41XX_DSIU,
-- .irq = DSIU_IRQ,
-- .start = 0x0f000820UL, },
--};
--
--#define SIU_TYPE2_NR_PORTS (sizeof(siu_type2_ports) / sizeof(struct siu_port))
--
--static struct uart_port siu_uart_ports[SIU_PORTS_MAX];
--static uint8_t lsr_break_flag[SIU_PORTS_MAX];
--
--#define siu_read(port, offset) readb((port)->membase + (offset))
--#define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
--
--void vr41xx_select_siu_interface(siu_interface_t interface)
--{
-- struct uart_port *port;
-- unsigned long flags;
-- uint8_t irsel;
--
-- port = &siu_uart_ports[0];
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- irsel = siu_read(port, SIUIRSEL);
-- if (interface == SIU_INTERFACE_IRDA)
-- irsel |= SIRSEL;
-- else
-- irsel &= ~SIRSEL;
-- siu_write(port, SIUIRSEL, irsel);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
--
--void vr41xx_use_irda(irda_use_t use)
--{
-- struct uart_port *port;
-- unsigned long flags;
-- uint8_t irsel;
--
-- port = &siu_uart_ports[0];
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- irsel = siu_read(port, SIUIRSEL);
-- if (use == FIR_USE_IRDA)
-- irsel |= IRUSESEL;
-- else
-- irsel &= ~IRUSESEL;
-- siu_write(port, SIUIRSEL, irsel);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+- */
+-#include <linux/ioport.h>
+-#include <linux/module.h>
+-#include <linux/pci.h>
-
--EXPORT_SYMBOL_GPL(vr41xx_use_irda);
+-#include <asm/io.h>
-
--void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
+-void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
-- struct uart_port *port;
-- unsigned long flags;
-- uint8_t irsel;
--
-- port = &siu_uart_ports[0];
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- irsel = siu_read(port, SIUIRSEL);
-- irsel &= ~(IRMSEL | TMICTX | TMICMODE);
-- switch (module) {
-- case SHARP_IRDA:
-- irsel |= IRMSEL_SHARP;
-- break;
-- case TEMIC_IRDA:
-- irsel |= IRMSEL_TEMIC | TMICMODE;
-- if (speed == IRDA_TX_4MBPS)
-- irsel |= TMICTX;
-- break;
-- case HP_IRDA:
-- irsel |= IRMSEL_HP;
-- break;
-- default:
-- break;
-- }
-- siu_write(port, SIUIRSEL, irsel);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
+- unsigned long end;
-
--EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
+- end = port + nr - 1UL;
+- if (ioport_resource.start > port ||
+- ioport_resource.end < end || port > end)
+- return NULL;
-
--static inline void siu_clear_fifo(struct uart_port *port)
--{
-- siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO);
-- siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
-- UART_FCR_CLEAR_XMIT);
-- siu_write(port, UART_FCR, 0);
+- return (void __iomem *)(mips_io_port_base + port);
-}
-
--static inline int siu_probe_ports(void)
+-void ioport_unmap(void __iomem *addr)
-{
-- switch (current_cpu_data.cputype) {
-- case CPU_VR4111:
-- case CPU_VR4121:
-- return SIU_TYPE1_NR_PORTS;
-- case CPU_VR4122:
-- case CPU_VR4131:
-- case CPU_VR4133:
-- return SIU_TYPE2_NR_PORTS;
-- }
--
-- return 0;
-}
+-EXPORT_SYMBOL(ioport_map);
+-EXPORT_SYMBOL(ioport_unmap);
-
--static inline unsigned long siu_port_size(struct uart_port *port)
+-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-- switch (port->type) {
-- case PORT_VR41XX_SIU:
-- return 11UL;
-- case PORT_VR41XX_DSIU:
-- return 8UL;
-- }
+- unsigned long start, len, flags;
-
-- return 0;
--}
+- if (dev == NULL)
+- return NULL;
-
--static inline unsigned int siu_check_type(struct uart_port *port)
--{
-- switch (current_cpu_data.cputype) {
-- case CPU_VR4111:
-- case CPU_VR4121:
-- if (port->line == 0)
-- return PORT_VR41XX_SIU;
-- break;
-- case CPU_VR4122:
-- case CPU_VR4131:
-- case CPU_VR4133:
-- if (port->line == 0)
-- return PORT_VR41XX_SIU;
-- else if (port->line == 1)
-- return PORT_VR41XX_DSIU;
-- break;
-- }
+- start = pci_resource_start(dev, bar);
+- len = pci_resource_len(dev, bar);
+- if (!start || !len)
+- return NULL;
-
-- return PORT_UNKNOWN;
--}
+- if (maxlen != 0 && len > maxlen)
+- len = maxlen;
-
--static inline const char *siu_type_name(struct uart_port *port)
--{
-- switch (port->type) {
-- case PORT_VR41XX_SIU:
-- return "SIU";
-- case PORT_VR41XX_DSIU:
-- return "DSIU";
+- flags = pci_resource_flags(dev, bar);
+- if (flags & IORESOURCE_IO)
+- return ioport_map(start, len);
+- if (flags & IORESOURCE_MEM) {
+- if (flags & IORESOURCE_CACHEABLE)
+- return ioremap_cacheable_cow(start, len);
+- return ioremap_nocache(start, len);
- }
-
- return NULL;
-}
-
--static unsigned int siu_tx_empty(struct uart_port *port)
--{
-- uint8_t lsr;
--
-- lsr = siu_read(port, UART_LSR);
-- if (lsr & UART_LSR_TEMT)
-- return TIOCSER_TEMT;
--
-- return 0;
--}
--
--static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl)
--{
-- uint8_t mcr = 0;
--
-- if (mctrl & TIOCM_DTR)
-- mcr |= UART_MCR_DTR;
-- if (mctrl & TIOCM_RTS)
-- mcr |= UART_MCR_RTS;
-- if (mctrl & TIOCM_OUT1)
-- mcr |= UART_MCR_OUT1;
-- if (mctrl & TIOCM_OUT2)
-- mcr |= UART_MCR_OUT2;
-- if (mctrl & TIOCM_LOOP)
-- mcr |= UART_MCR_LOOP;
--
-- siu_write(port, UART_MCR, mcr);
--}
--
--static unsigned int siu_get_mctrl(struct uart_port *port)
--{
-- uint8_t msr;
-- unsigned int mctrl = 0;
--
-- msr = siu_read(port, UART_MSR);
-- if (msr & UART_MSR_DCD)
-- mctrl |= TIOCM_CAR;
-- if (msr & UART_MSR_RI)
-- mctrl |= TIOCM_RNG;
-- if (msr & UART_MSR_DSR)
-- mctrl |= TIOCM_DSR;
-- if (msr & UART_MSR_CTS)
-- mctrl |= TIOCM_CTS;
--
-- return mctrl;
--}
--
--static void siu_stop_tx(struct uart_port *port, unsigned int tty_stop)
--{
-- unsigned long flags;
-- uint8_t ier;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- ier = siu_read(port, UART_IER);
-- ier &= ~UART_IER_THRI;
-- siu_write(port, UART_IER, ier);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static void siu_start_tx(struct uart_port *port, unsigned int tty_start)
--{
-- unsigned long flags;
-- uint8_t ier;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- ier = siu_read(port, UART_IER);
-- ier |= UART_IER_THRI;
-- siu_write(port, UART_IER, ier);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static void siu_stop_rx(struct uart_port *port)
--{
-- unsigned long flags;
-- uint8_t ier;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- ier = siu_read(port, UART_IER);
-- ier &= ~UART_IER_RLSI;
-- siu_write(port, UART_IER, ier);
--
-- port->read_status_mask &= ~UART_LSR_DR;
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static void siu_enable_ms(struct uart_port *port)
--{
-- unsigned long flags;
-- uint8_t ier;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- ier = siu_read(port, UART_IER);
-- ier |= UART_IER_MSI;
-- siu_write(port, UART_IER, ier);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static void siu_break_ctl(struct uart_port *port, int ctl)
--{
-- unsigned long flags;
-- uint8_t lcr;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- lcr = siu_read(port, UART_LCR);
-- if (ctl == -1)
-- lcr |= UART_LCR_SBC;
-- else
-- lcr &= ~UART_LCR_SBC;
-- siu_write(port, UART_LCR, lcr);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static inline void receive_chars(struct uart_port *port, uint8_t *status,
-- struct pt_regs *regs)
+-void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-{
-- struct tty_struct *tty;
-- uint8_t lsr, ch;
-- char flag;
-- int max_count = RX_MAX_COUNT;
--
-- tty = port->info->tty;
-- lsr = *status;
--
-- do {
-- if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
-- if (tty->low_latency)
-- tty_flip_buffer_push(tty);
-- }
--
-- ch = siu_read(port, UART_RX);
-- port->icount.rx++;
-- flag = TTY_NORMAL;
--
--#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
-- lsr |= lsr_break_flag[port->line];
-- lsr_break_flag[port->line] = 0;
--#endif
-- if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE |
-- UART_LSR_PE | UART_LSR_OE))) {
-- if (lsr & UART_LSR_BI) {
-- lsr &= ~(UART_LSR_FE | UART_LSR_PE);
-- port->icount.brk++;
--
-- if (uart_handle_break(port))
-- goto ignore_char;
-- }
--
-- if (lsr & UART_LSR_FE)
-- port->icount.frame++;
-- if (lsr & UART_LSR_PE)
-- port->icount.parity++;
-- if (lsr & UART_LSR_OE)
-- port->icount.overrun++;
--
-- lsr &= port->read_status_mask;
-- if (lsr & UART_LSR_BI)
-- flag = TTY_BREAK;
-- if (lsr & UART_LSR_FE)
-- flag = TTY_FRAME;
-- if (lsr & UART_LSR_PE)
-- flag = TTY_PARITY;
-- }
--
-- if (uart_handle_sysrq_char(port, ch, regs))
-- goto ignore_char;
--
-- uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
--
-- ignore_char:
-- lsr = siu_read(port, UART_LSR);
-- } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
--
-- tty_flip_buffer_push(tty);
--
-- *status = lsr;
+- iounmap(addr);
-}
+-EXPORT_SYMBOL(pci_iomap);
+-EXPORT_SYMBOL(pci_iounmap);
+diff -urN --ignore-space-change kernel.org/arch/mips/lib-32/dump_tlb.c linux-mips/arch/mips/lib-32/dump_tlb.c
+--- kernel.org/arch/mips/lib-32/dump_tlb.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/lib-32/dump_tlb.c 2006-01-10 11:21:15.000000000 +0000
+@@ -41,8 +41,6 @@
+ return "256Mb";
+ #endif
+ }
-
--static inline void check_modem_status(struct uart_port *port)
--{
-- uint8_t msr;
--
-- msr = siu_read(port, UART_MSR);
-- if ((msr & UART_MSR_ANY_DELTA) == 0)
-- return;
-- if (msr & UART_MSR_DDCD)
-- uart_handle_dcd_change(port, msr & UART_MSR_DCD);
-- if (msr & UART_MSR_TERI)
-- port->icount.rng++;
-- if (msr & UART_MSR_DDSR)
-- port->icount.dsr++;
-- if (msr & UART_MSR_DCTS)
-- uart_handle_cts_change(port, msr & UART_MSR_CTS);
+- return "unknown";
+ }
+
+ #define BARRIER() \
+diff -urN --ignore-space-change kernel.org/arch/mips/lib-64/dump_tlb.c linux-mips/arch/mips/lib-64/dump_tlb.c
+--- kernel.org/arch/mips/lib-64/dump_tlb.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/lib-64/dump_tlb.c 2006-01-10 11:21:15.000000000 +0000
+@@ -32,8 +32,6 @@
+ case PM_256M: return "256Mb";
+ #endif
+ }
-
-- wake_up_interruptible(&port->info->delta_msr_wait);
--}
+- return "unknown";
+ }
+
+ #define BARRIER() \
+diff -urN --ignore-space-change kernel.org/arch/mips/math-emu/dp_fint.c linux-mips/arch/mips/math-emu/dp_fint.c
+--- kernel.org/arch/mips/math-emu/dp_fint.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/math-emu/dp_fint.c 2006-01-10 11:21:15.000000000 +0000
+@@ -33,8 +33,6 @@
+
+ CLEARCX;
+
+- xc = ( 0 ? xc : xc );
-
--static inline void transmit_chars(struct uart_port *port)
--{
-- struct circ_buf *xmit;
-- int max_count = TX_MAX_COUNT;
+ if (x == 0)
+ return ieee754dp_zero(0);
+ if (x == 1 || x == -1)
+diff -urN --ignore-space-change kernel.org/arch/mips/math-emu/dp_flong.c linux-mips/arch/mips/math-emu/dp_flong.c
+--- kernel.org/arch/mips/math-emu/dp_flong.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/math-emu/dp_flong.c 2006-01-10 11:21:15.000000000 +0000
+@@ -33,8 +33,6 @@
+
+ CLEARCX;
+
+- xc = ( 0 ? xc : xc );
-
-- xmit = &port->info->xmit;
+ if (x == 0)
+ return ieee754dp_zero(0);
+ if (x == 1 || x == -1)
+diff -urN --ignore-space-change kernel.org/arch/mips/math-emu/sp_fint.c linux-mips/arch/mips/math-emu/sp_fint.c
+--- kernel.org/arch/mips/math-emu/sp_fint.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/math-emu/sp_fint.c 2006-01-10 11:21:16.000000000 +0000
+@@ -33,8 +33,6 @@
+
+ CLEARCX;
+
+- xc = ( 0 ? xc : xc );
-
-- if (port->x_char) {
-- siu_write(port, UART_TX, port->x_char);
-- port->icount.tx++;
-- port->x_char = 0;
-- return;
-- }
+ if (x == 0)
+ return ieee754sp_zero(0);
+ if (x == 1 || x == -1)
+diff -urN --ignore-space-change kernel.org/arch/mips/math-emu/sp_flong.c linux-mips/arch/mips/math-emu/sp_flong.c
+--- kernel.org/arch/mips/math-emu/sp_flong.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/math-emu/sp_flong.c 2006-01-10 11:21:16.000000000 +0000
+@@ -33,8 +33,6 @@
+
+ CLEARCX;
+
+- xc = ( 0 ? xc : xc );
-
-- if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-- siu_stop_tx(port, 0);
-- return;
+ if (x == 0)
+ return ieee754sp_zero(0);
+ if (x == 1 || x == -1)
+diff -urN --ignore-space-change kernel.org/arch/mips/mips-boards/generic/time.c linux-mips/arch/mips/mips-boards/generic/time.c
+--- kernel.org/arch/mips/mips-boards/generic/time.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/mips-boards/generic/time.c 2006-01-10 11:21:16.000000000 +0000
+@@ -75,20 +75,31 @@
+ do_IRQ (mips_cpu_timer_irq, regs);
+ }
+
++extern int null_perf_irq(struct pt_regs *regs);
++
++extern int (*perf_irq)(struct pt_regs *regs);
++
+ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+ {
+-#ifdef CONFIG_SMP
++ int r2 = cpu_has_mips_r2;
+ int cpu = smp_processor_id();
+
+ if (cpu == 0) {
+ /*
+- * CPU 0 handles the global timer interrupt job and process accounting
+- * resets count/compare registers to trigger next timer int.
++ * CPU 0 handles the global timer interrupt job and process
++ * accounting resets count/compare registers to trigger next
++ * timer int.
+ */
+- (void) timer_interrupt(irq, dev_id, regs);
++ if (!r2 || (read_c0_cause() & (1 << 26)))
++ if (perf_irq(regs))
++ goto out;
++
++ /* we keep interrupt disabled all the time */
++ if (!r2 || (read_c0_cause() & (1 << 30)))
++ timer_interrupt(irq, NULL, regs);
++
+ scroll_display_message();
- }
+- else {
++ } else {
+ /* Everyone else needs to reset the timer int here as
+ ll_local_timer_interrupt doesn't */
+ /*
+@@ -103,16 +114,8 @@
+ local_timer_interrupt (irq, dev_id, regs);
+ }
+
++out:
+ return IRQ_HANDLED;
+-#else
+- irqreturn_t r;
-
-- do {
-- siu_write(port, UART_TX, xmit->buf[xmit->tail]);
-- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-- port->icount.tx++;
-- if (uart_circ_empty(xmit))
-- break;
-- } while (max_count-- > 0);
--
-- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-- uart_write_wakeup(port);
--
-- if (uart_circ_empty(xmit))
-- siu_stop_tx(port, 0);
--}
--
--static irqreturn_t siu_interrupt(int irq, void *dev_id, struct pt_regs *regs)
--{
-- struct uart_port *port;
-- uint8_t iir, lsr;
--
-- port = (struct uart_port *)dev_id;
--
-- iir = siu_read(port, UART_IIR);
-- if (iir & UART_IIR_NO_INT)
-- return IRQ_NONE;
--
-- lsr = siu_read(port, UART_LSR);
-- if (lsr & UART_LSR_DR)
-- receive_chars(port, &lsr, regs);
--
-- check_modem_status(port);
--
-- if (lsr & UART_LSR_THRE)
-- transmit_chars(port);
--
-- return IRQ_HANDLED;
--}
--
--static int siu_startup(struct uart_port *port)
--{
-- int retval;
--
-- if (port->membase == NULL)
-- return -ENODEV;
--
-- siu_clear_fifo(port);
--
-- (void)siu_read(port, UART_LSR);
-- (void)siu_read(port, UART_RX);
-- (void)siu_read(port, UART_IIR);
-- (void)siu_read(port, UART_MSR);
--
-- if (siu_read(port, UART_LSR) == 0xff)
-- return -ENODEV;
--
-- retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
-- if (retval)
-- return retval;
--
-- if (port->type == PORT_VR41XX_DSIU)
-- vr41xx_enable_dsiuint(DSIUINT_ALL);
--
-- siu_write(port, UART_LCR, UART_LCR_WLEN8);
--
-- spin_lock_irq(&port->lock);
-- siu_set_mctrl(port, port->mctrl);
-- spin_unlock_irq(&port->lock);
--
-- siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
--
-- (void)siu_read(port, UART_LSR);
-- (void)siu_read(port, UART_RX);
-- (void)siu_read(port, UART_IIR);
-- (void)siu_read(port, UART_MSR);
--
-- return 0;
--}
--
--static void siu_shutdown(struct uart_port *port)
--{
-- unsigned long flags;
-- uint8_t lcr;
--
-- siu_write(port, UART_IER, 0);
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- port->mctrl &= ~TIOCM_OUT2;
-- siu_set_mctrl(port, port->mctrl);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--
-- lcr = siu_read(port, UART_LCR);
-- lcr &= ~UART_LCR_SBC;
-- siu_write(port, UART_LCR, lcr);
--
-- siu_clear_fifo(port);
+- r = timer_interrupt(irq, dev_id, regs);
-
-- (void)siu_read(port, UART_RX);
+- scroll_display_message();
-
-- if (port->type == PORT_VR41XX_DSIU)
-- vr41xx_disable_dsiuint(DSIUINT_ALL);
+- return r;
+-#endif
+ }
+
+ /*
+diff -urN --ignore-space-change kernel.org/arch/mips/mm/c-r4k.c linux-mips/arch/mips/mm/c-r4k.c
+--- kernel.org/arch/mips/mm/c-r4k.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/mm/c-r4k.c 2006-01-10 11:21:16.000000000 +0000
+@@ -1183,8 +1183,8 @@
+ if (!sc_present)
+ return;
+
+- if ((c->isa_level == MIPS_CPU_ISA_M32 ||
+- c->isa_level == MIPS_CPU_ISA_M64) &&
++ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++ c->isa_level == MIPS_CPU_ISA_M64R1) &&
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+
+diff -urN --ignore-space-change kernel.org/arch/mips/mm/cex-sb1.S linux-mips/arch/mips/mm/cex-sb1.S
+--- kernel.org/arch/mips/mm/cex-sb1.S 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/mm/cex-sb1.S 2006-01-10 11:21:16.000000000 +0000
+@@ -64,7 +64,7 @@
+ sd k0,0x170($0)
+ sd k1,0x178($0)
+
+-#if CONFIG_SB1_CEX_ALWAYS_FATAL
++#ifdef CONFIG_SB1_CEX_ALWAYS_FATAL
+ j handle_vec2_sb1
+ nop
+ #else
+diff -urN --ignore-space-change kernel.org/arch/mips/oprofile/common.c linux-mips/arch/mips/oprofile/common.c
+--- kernel.org/arch/mips/oprofile/common.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/oprofile/common.c 2006-01-10 11:21:16.000000000 +0000
+@@ -75,7 +75,10 @@
+ int res;
+
+ switch (current_cpu_data.cputype) {
++ case CPU_5KC:
++ case CPU_20KC:
+ case CPU_24K:
++ case CPU_25KF:
+ lmodel = &op_model_mipsxx;
+ break;
+
+diff -urN --ignore-space-change kernel.org/arch/mips/oprofile/op_impl.h linux-mips/arch/mips/oprofile/op_impl.h
+--- kernel.org/arch/mips/oprofile/op_impl.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/oprofile/op_impl.h 2006-01-10 11:21:16.000000000 +0000
+@@ -12,8 +12,8 @@
+
+ struct pt_regs;
+
+-extern void null_perf_irq(struct pt_regs *regs);
+-extern void (*perf_irq)(struct pt_regs *regs);
++extern int null_perf_irq(struct pt_regs *regs);
++extern int (*perf_irq)(struct pt_regs *regs);
+
+ /* Per-counter configuration as set via oprofilefs. */
+ struct op_counter_config {
+diff -urN --ignore-space-change kernel.org/arch/mips/oprofile/op_model_mipsxx.c linux-mips/arch/mips/oprofile/op_model_mipsxx.c
+--- kernel.org/arch/mips/oprofile/op_model_mipsxx.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/oprofile/op_model_mipsxx.c 2006-01-10 11:21:16.000000000 +0000
+@@ -114,11 +114,12 @@
+ }
+ }
+
+-static void mipsxx_perfcount_handler(struct pt_regs *regs)
++static int mipsxx_perfcount_handler(struct pt_regs *regs)
+ {
+ unsigned int counters = op_model_mipsxx.num_counters;
+ unsigned int control;
+ unsigned int counter;
++ int handled = 0;
+
+ switch (counters) {
+ #define HANDLE_COUNTER(n) \
+@@ -129,12 +130,15 @@
+ (counter & M_COUNTER_OVERFLOW)) { \
+ oprofile_add_sample(regs, n); \
+ write_c0_perfcntr ## n(reg.counter[n]); \
++ handled = 1; \
+ }
+ HANDLE_COUNTER(3)
+ HANDLE_COUNTER(2)
+ HANDLE_COUNTER(1)
+ HANDLE_COUNTER(0)
+ }
++
++ return handled;
+ }
+
+ #define M_CONFIG1_PC (1 << 4)
+@@ -176,17 +180,31 @@
+ int counters;
+
+ counters = n_counters();
+- if (counters == 0)
++ if (counters == 0) {
++ printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
+ return -ENODEV;
++ }
+
+ reset_counters(counters);
+
+ op_model_mipsxx.num_counters = counters;
+ switch (current_cpu_data.cputype) {
++ case CPU_20KC:
++ op_model_mipsxx.cpu_type = "mips/20K";
++ break;
++
+ case CPU_24K:
+ op_model_mipsxx.cpu_type = "mips/24K";
+ break;
+
++ case CPU_25KF:
++ op_model_mipsxx.cpu_type = "mips/25K";
++ break;
++
++ case CPU_5KC:
++ op_model_mipsxx.cpu_type = "mips/5K";
++ break;
++
+ default:
+ printk(KERN_ERR "Profiling unsupported for this CPU\n");
+
+diff -urN --ignore-space-change kernel.org/arch/mips/pci/Makefile linux-mips/arch/mips/pci/Makefile
+--- kernel.org/arch/mips/pci/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/pci/Makefile 2006-01-10 11:21:16.000000000 +0000
+@@ -50,7 +50,6 @@
+ obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
+-obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
+ obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
+ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
+ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
+diff -urN --ignore-space-change kernel.org/arch/mips/pci/fixup-tb0219.c linux-mips/arch/mips/pci/fixup-tb0219.c
+--- kernel.org/arch/mips/pci/fixup-tb0219.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/pci/fixup-tb0219.c 2006-01-10 11:21:16.000000000 +0000
+@@ -2,7 +2,7 @@
+ * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
+ *
+ * Copyright (C) 2003 Megasolution Inc. <matsu at megasolution.jp>
+- * Copyright (C) 2004 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
++ * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+diff -urN --ignore-space-change kernel.org/arch/mips/pci/fixup-tb0287.c linux-mips/arch/mips/pci/fixup-tb0287.c
+--- kernel.org/arch/mips/pci/fixup-tb0287.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/pci/fixup-tb0287.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,65 +0,0 @@
+-/*
+- * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
+- *
+- * Copyright (C) 2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+- */
+-#include <linux/init.h>
+-#include <linux/pci.h>
-
-- free_irq(port->irq, port);
--}
+-#include <asm/vr41xx/tb0287.h>
-
--static void siu_set_termios(struct uart_port *port, struct termios *new,
-- struct termios *old)
+-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
-- tcflag_t c_cflag, c_iflag;
-- uint8_t lcr, fcr, ier;
-- unsigned int baud, quot;
-- unsigned long flags;
--
-- c_cflag = new->c_cflag;
-- switch (c_cflag & CSIZE) {
-- case CS5:
-- lcr = UART_LCR_WLEN5;
-- break;
-- case CS6:
-- lcr = UART_LCR_WLEN6;
-- break;
-- case CS7:
-- lcr = UART_LCR_WLEN7;
-- break;
-- default:
-- lcr = UART_LCR_WLEN8;
-- break;
-- }
--
-- if (c_cflag & CSTOPB)
-- lcr |= UART_LCR_STOP;
-- if (c_cflag & PARENB)
-- lcr |= UART_LCR_PARITY;
-- if ((c_cflag & PARODD) != PARODD)
-- lcr |= UART_LCR_EPAR;
-- if (c_cflag & CMSPAR)
-- lcr |= UART_LCR_SPAR;
--
-- baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
-- quot = uart_get_divisor(port, baud);
--
-- fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
--
-- spin_lock_irqsave(&port->lock, flags);
--
-- uart_update_timeout(port, c_cflag, baud);
--
-- c_iflag = new->c_iflag;
--
-- port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
-- if (c_iflag & INPCK)
-- port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
-- if (c_iflag & (BRKINT | PARMRK))
-- port->read_status_mask |= UART_LSR_BI;
--
-- port->ignore_status_mask = 0;
-- if (c_iflag & IGNPAR)
-- port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
-- if (c_iflag & IGNBRK) {
-- port->ignore_status_mask |= UART_LSR_BI;
-- if (c_iflag & IGNPAR)
-- port->ignore_status_mask |= UART_LSR_OE;
-- }
--
-- if ((c_cflag & CREAD) == 0)
-- port->ignore_status_mask |= UART_LSR_DR;
--
-- ier = siu_read(port, UART_IER);
-- ier &= ~UART_IER_MSI;
-- if (UART_ENABLE_MS(port, c_cflag))
-- ier |= UART_IER_MSI;
-- siu_write(port, UART_IER, ier);
--
-- siu_write(port, UART_LCR, lcr | UART_LCR_DLAB);
--
-- siu_write(port, UART_DLL, (uint8_t)quot);
-- siu_write(port, UART_DLM, (uint8_t)(quot >> 8));
+- unsigned char bus;
+- int irq = -1;
-
-- siu_write(port, UART_LCR, lcr);
--
-- siu_write(port, UART_FCR, fcr);
--
-- siu_set_mctrl(port, port->mctrl);
--
-- spin_unlock_irqrestore(&port->lock, flags);
--}
--
--static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
--{
-- switch (state) {
-- case 0:
-- switch (port->type) {
-- case PORT_VR41XX_SIU:
-- vr41xx_supply_clock(SIU_CLOCK);
+- bus = dev->bus->number;
+- if (bus == 0) {
+- switch (slot) {
+- case 16:
+- irq = TB0287_SM501_IRQ;
+- break;
+- case 17:
+- irq = TB0287_SIL680A_IRQ;
- break;
-- case PORT_VR41XX_DSIU:
-- vr41xx_supply_clock(DSIU_CLOCK);
+- default:
- break;
- }
-- break;
-- case 3:
-- switch (port->type) {
-- case PORT_VR41XX_SIU:
-- vr41xx_mask_clock(SIU_CLOCK);
+- } else if (bus == 1) {
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- irq = TB0287_PCI_SLOT_IRQ;
- break;
-- case PORT_VR41XX_DSIU:
-- vr41xx_mask_clock(DSIU_CLOCK);
+- case 2:
+- case 3:
+- irq = TB0287_RTL8110_IRQ;
+- break;
+- default:
- break;
- }
-- break;
-- }
--}
--
--static const char *siu_type(struct uart_port *port)
--{
-- return siu_type_name(port);
--}
--
--static void siu_release_port(struct uart_port *port)
--{
-- unsigned long size;
--
-- if (port->flags & UPF_IOREMAP) {
-- iounmap(port->membase);
-- port->membase = NULL;
-- }
--
-- size = siu_port_size(port);
-- release_mem_region(port->mapbase, size);
--}
--
--static int siu_request_port(struct uart_port *port)
--{
-- unsigned long size;
-- struct resource *res;
--
-- size = siu_port_size(port);
-- res = request_mem_region(port->mapbase, size, siu_type_name(port));
-- if (res == NULL)
-- return -EBUSY;
--
-- if (port->flags & UPF_IOREMAP) {
-- port->membase = ioremap(port->mapbase, size);
-- if (port->membase == NULL) {
-- release_resource(res);
-- return -ENOMEM;
-- }
+- } else if (bus > 1) {
+- irq = TB0287_PCI_SLOT_IRQ;
- }
-
-- return 0;
--}
--
--static void siu_config_port(struct uart_port *port, int flags)
--{
-- if (flags & UART_CONFIG_TYPE) {
-- port->type = siu_check_type(port);
-- (void)siu_request_port(port);
-- }
+- return irq;
-}
-
--static int siu_verify_port(struct uart_port *port, struct serial_struct *serial)
+-/* Do platform specific device initialization at pci_enable_device() time */
+-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-- if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU)
-- return -EINVAL;
-- if (port->irq != serial->irq)
-- return -EINVAL;
-- if (port->iotype != serial->io_type)
-- return -EINVAL;
-- if (port->mapbase != (unsigned long)serial->iomem_base)
-- return -EINVAL;
--
- return 0;
-}
--
--static struct uart_ops siu_uart_ops = {
-- .tx_empty = siu_tx_empty,
-- .set_mctrl = siu_set_mctrl,
-- .get_mctrl = siu_get_mctrl,
-- .stop_tx = siu_stop_tx,
-- .start_tx = siu_start_tx,
-- .stop_rx = siu_stop_rx,
-- .enable_ms = siu_enable_ms,
-- .break_ctl = siu_break_ctl,
-- .startup = siu_startup,
-- .shutdown = siu_shutdown,
-- .set_termios = siu_set_termios,
-- .pm = siu_pm,
-- .type = siu_type,
-- .release_port = siu_release_port,
-- .request_port = siu_request_port,
-- .config_port = siu_config_port,
-- .verify_port = siu_verify_port,
--};
--
--static int siu_init_ports(void)
--{
-- const struct siu_port *siu;
-- struct uart_port *port;
-- int i, num;
--
-- switch (current_cpu_data.cputype) {
-- case CPU_VR4111:
-- case CPU_VR4121:
-- siu = siu_type1_ports;
-- break;
-- case CPU_VR4122:
-- case CPU_VR4131:
-- case CPU_VR4133:
-- siu = siu_type2_ports;
-- break;
-- default:
-- return 0;
-- }
--
-- port = siu_uart_ports;
-- num = siu_probe_ports();
-- for (i = 0; i < num; i++) {
-- spin_lock_init(&port->lock);
-- port->irq = siu->irq;
-- port->uartclk = SIU_BAUD_BASE * 16;
-- port->fifosize = 16;
-- port->regshift = 0;
-- port->iotype = UPIO_MEM;
-- port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
-- port->type = siu->type;
-- port->line = i;
-- port->mapbase = siu->start;
-- siu++;
-- port++;
-- }
--
-- return num;
--}
--
--#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
--
--#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
--
--static void wait_for_xmitr(struct uart_port *port)
--{
-- int timeout = 10000;
-- uint8_t lsr, msr;
--
-- do {
-- lsr = siu_read(port, UART_LSR);
-- if (lsr & UART_LSR_BI)
-- lsr_break_flag[port->line] = UART_LSR_BI;
--
-- if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
-- break;
-- } while (timeout-- > 0);
--
-- if (port->flags & UPF_CONS_FLOW) {
-- timeout = 1000000;
--
-- do {
-- msr = siu_read(port, UART_MSR);
-- if ((msr & UART_MSR_CTS) != 0)
-- break;
-- } while (timeout-- > 0);
-- }
--}
--
--static void siu_console_write(struct console *con, const char *s, unsigned count)
--{
-- struct uart_port *port;
-- uint8_t ier;
-- unsigned i;
--
-- port = &siu_uart_ports[con->index];
--
-- ier = siu_read(port, UART_IER);
-- siu_write(port, UART_IER, 0);
--
-- for (i = 0; i < count && *s != '\0'; i++, s++) {
-- wait_for_xmitr(port);
-- siu_write(port, UART_TX, *s);
-- if (*s == '\n') {
-- wait_for_xmitr(port);
-- siu_write(port, UART_TX, '\r');
-- }
-- }
--
-- wait_for_xmitr(port);
-- siu_write(port, UART_IER, ier);
--}
--
--static int siu_console_setup(struct console *con, char *options)
--{
-- struct uart_port *port;
-- int baud = 9600;
-- int parity = 'n';
-- int bits = 8;
-- int flow = 'n';
--
-- if (con->index >= SIU_PORTS_MAX)
-- con->index = 0;
--
-- port = &siu_uart_ports[con->index];
-- if (port->membase == NULL) {
-- if (port->mapbase == 0)
-- return -ENODEV;
-- port->membase = ioremap(port->mapbase, siu_port_size(port));
+diff -urN --ignore-space-change kernel.org/arch/mips/pci/pci-vr41xx.c linux-mips/arch/mips/pci/pci-vr41xx.c
+--- kernel.org/arch/mips/pci/pci-vr41xx.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/pci/pci-vr41xx.c 2006-01-10 11:21:16.000000000 +0000
+@@ -123,10 +123,8 @@
+ return -EBUSY;
+
+ pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
+- if (pciu_base == NULL) {
+- release_mem_region(PCIU_BASE, PCIU_SIZE);
++ if (pciu_base == NULL)
+ return -EBUSY;
- }
+
+ /* Disable PCI interrupt */
+ vr41xx_disable_pciint();
+diff -urN --ignore-space-change kernel.org/arch/mips/qemu/Makefile linux-mips/arch/mips/qemu/Makefile
+--- kernel.org/arch/mips/qemu/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/qemu/Makefile 2006-01-10 11:21:16.000000000 +0000
+@@ -2,4 +2,4 @@
+ # Makefile for Qemu specific kernel interface routines under Linux.
+ #
+
+-obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o
++obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o q-vga.o
+diff -urN --ignore-space-change kernel.org/arch/mips/qemu/q-setup.c linux-mips/arch/mips/qemu/q-setup.c
+--- kernel.org/arch/mips/qemu/q-setup.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/qemu/q-setup.c 2006-01-10 11:21:16.000000000 +0000
+@@ -2,6 +2,8 @@
+ #include <asm/io.h>
+ #include <asm/time.h>
+
++extern void qvga_init(void);
++
+ #define QEMU_PORT_BASE 0xb4000000
+
+ const char *get_system_type(void)
+@@ -21,5 +23,6 @@
+ void __init plat_setup(void)
+ {
+ set_io_port_base(QEMU_PORT_BASE);
++ qvga_init();
+ board_timer_setup = qemu_timer_setup;
+ }
+diff -urN --ignore-space-change kernel.org/arch/mips/qemu/q-vga.c linux-mips/arch/mips/qemu/q-vga.c
+--- kernel.org/arch/mips/qemu/q-vga.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/arch/mips/qemu/q-vga.c 2006-01-10 11:21:16.000000000 +0000
+@@ -0,0 +1,188 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005 by Ralf Baechle (ralf at linux-mips.org)
++ *
++ * This will eventually go into the qemu firmware.
++ */
++#include <linux/init.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <video/vga.h>
++
++/*
++ * This will eventually be done by the firmware; right now Linux assumes to
++ * run on the uninitialized hardware.
++ */
++#undef LOAD_VGA_FONT
++
++static unsigned char sr[8] __initdata = { /* Sequencer */
++ 0x03, 0x00, 0x03, 0x04, 0x02, 0x00, 0x00, 0x00
++};
++
++static unsigned char gr[16] __initdata= { /* Graphics Controller */
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
++ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++};
++
++static unsigned char ar[21] __initdata= { /* Attribute Controller */
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x0c, 0x01, 0x07, 0x13, 0x00
++};
++
++static unsigned char cr[32] __initdata= { /* CRT Controller */
++ 0x91, 0x4f, 0x4f, 0x95, 0x57, 0x4f, 0xc0, 0x1f,
++ 0x00, 0x4f, 0x0d, 0x0e, 0x02, 0x30, 0x09, 0xb0,
++ 0x90, 0x83, 0x8f, 0x28, 0x1f, 0x8f, 0xc1, 0xa3,
++ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++};
++
++static struct rgb {
++ unsigned char r;
++ unsigned char g;
++ unsigned char b;
++} palette[16] __initdata= {
++ [ 0] = {0x00, 0x00, 0x00},
++ [ 1] = {0x00, 0x00, 0x2a},
++ [ 2] = {0x00, 0x2a, 0x00},
++ [ 3] = {0x00, 0x2a, 0x2a},
++ [ 4] = {0x2a, 0x00, 0x00},
++ [ 5] = {0x2a, 0x00, 0x2a},
++ [ 6] = {0x2a, 0x15, 0x00},
++ [ 7] = {0x2a, 0x2a, 0x2a},
++ [ 8] = {0x15, 0x15, 0x15},
++ [ 9] = {0x15, 0x15, 0x3f},
++ [10] = {0x15, 0x3f, 0x15},
++ [11] = {0x15, 0x3f, 0x3f},
++ [12] = {0x3f, 0x15, 0x15},
++ [13] = {0x3f, 0x15, 0x3f},
++ [14] = {0x3f, 0x3f, 0x15},
++ [15] = {0x3f, 0x3f, 0x3f}
++
++};
++
++void __init qvga_init_ibm(void)
++{
++ int i;
++
++ for (i = 0; i < 8; i++) { /* Sequencer registers */
++ outb(i, 0x3c4);
++ outb(sr[i], 0x3c5);
++ }
++
++ for (i = 0; i < 16; i++) { /* Graphics Controller registers */
++ outb(i, 0x3ce);
++ outb(gr[i], 0x3cf);
++ }
++
++ for (i = 0; i < 21; i++) { /* Attribute Controller registers */
++ outb(i, 0x3c0);
++ outb(ar[i], 0x3c1);
++ }
++ outb(0x20, 0x3c0); /* enable bit in *index* register */
++
++ for (i = 0; i < 32; i++) { /* CRT Controller registers */
++ outb(i, 0x3d4);
++ outb(cr[i], 0x3d5);
++ }
++
++ for (i = 0; i < 16; i++) { /* palette */
++ outb(i, 0x3c8);
++ outb(palette[i].r, 0x3c9);
++ outb(palette[i].g, 0x3c9);
++ outb(palette[i].b, 0x3c9);
++ }
++
++#if 1
++ for (i = 0; i < 0x20000; i += 2)
++ *(volatile unsigned short *) (0xb00a0000 + i) = 0xaaaa;
++#endif
++}
++
++#ifdef LOAD_VGA_FONT
++#include "/home/ralf/src/qemu/qemu-mips/vgafont.h"
++
++static void __init
++qvga_load_font(unsigned char *def, unsigned int c)
++{
++ volatile void *w = (volatile void *) 0xb00a0000;
++
++ vga_wseq(NULL, 0, 1);
++ vga_wseq(NULL, 2, 4);
++ vga_wseq(NULL, 4, 7);
++ vga_wseq(NULL, 0, 3);
++ vga_wgfx(NULL, 4, 2);
++ vga_wgfx(NULL, 5, 0);
++ vga_wgfx(NULL, 6, 0);
++
++ memcpy(w, def, c);
++
++ vga_wseq(NULL, 0, 1);
++ vga_wseq(NULL, 2, 3);
++ vga_wseq(NULL, 4, 3);
++ vga_wseq(NULL, 0, 3);
++ vga_wgfx(NULL, 4, 0);
++ vga_wgfx(NULL, 5, 0x10);
++ vga_wgfx(NULL, 6, 0xe);
++}
++#endif
++
++void __init qvga_init(void)
++{
++ struct screen_info *si = &screen_info;
++ unsigned int h;
++ int i;
++
++#if LOAD_VGA_FONT
++ qvga_load_font(vgafont16, 4096);
++#endif
++
++ vga_wgfx(NULL, 5, 0x10); /* Set odd/even mode */
++ vga_wgfx(NULL, 6, 0x0c); /* map to offset 0xb8000, text mode */
++ vga_wseq(NULL, 2, 3); /* Planes 0 & 1 */
++ vga_wseq(NULL, 3, 4); /* Font offset */
++ outb(1, VGA_MIS_W); /* set msr to MSR_COLOR_EMULATION */
++ vga_wcrt(NULL, 1, 79); /* 80 columns */
++ vga_wcrt(NULL, 9, 15); /* 16 pixels per character */
++ vga_wcrt(NULL, 0x0c, 0); /* start address high 8 bit */
++ vga_wcrt(NULL, 0x0d, 0); /* start address low 8 bit */
++ vga_wcrt(NULL, 0x13, 0x28); /* line offset */
++ vga_wcrt(NULL, 0x07, 0x1f); /* line compare bit 8 */
++ vga_wcrt(NULL, 0x09, 0x4f); /* line compare bit 9 */
++ vga_wcrt(NULL, 0x18, 0xff); /* line compare low 8 bit */
++
++ h = (25 * 16);
++ vga_wcrt(NULL, 0x12, h);
++
++ outb(7, 0x3d4);
++ outb((inb(0x3d5) & ~0x42) | ((h >> 7) & 2) | ((h >> 3) & 0x40), 0x3d5);
++
++ for (i = 0; i < 21; i++) /* Attribute Controller */
++ vga_wattr(NULL, i, ar[i]);
++ outb(0x20, 0x3c0); /* Set bit 5 in Attribute Controller */
++ /* index ... VGA is so stupid I want */
++ /* to cry all day ... */
++ outb(0, VGA_PEL_IW);
++ for (i = 0; i < 16; i++) { /* palette */
++ outb(palette[i].r, VGA_PEL_D);
++ outb(palette[i].g, VGA_PEL_D);
++ outb(palette[i].b, VGA_PEL_D);
++ }
++
++ si->orig_x = 0; /* Cursor x position */
++ si->orig_y = 0; /* Cursor y position */
++ si->orig_video_cols = 80; /* Columns */
++ si->orig_video_lines = 25; /* Lines */
++ si->orig_video_isVGA = VIDEO_TYPE_VGAC; /* Card type */
++ si->orig_video_points = 16;
++
++#if 0
++ for (i = 0; i < 80; i += 2)
++ //*(volatile unsigned short *) (0xb00b8000 + i) = 0x0100 | 'A';
++ scr_writew(0x0100 | 'A', (volatile unsigned short *) (0xb00b8000 + i));
++ while (1);
++#endif
++}
+diff -urN --ignore-space-change kernel.org/arch/mips/sibyte/Kconfig linux-mips/arch/mips/sibyte/Kconfig
+--- kernel.org/arch/mips/sibyte/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/sibyte/Kconfig 2006-01-10 11:21:16.000000000 +0000
+@@ -102,11 +102,11 @@
+ Build a kernel suitable for running under the GDB simulator.
+ Primarily adjusts the kernel's notion of time.
+
+-config CONFIG_SB1_CEX_ALWAYS_FATAL
++config SB1_CEX_ALWAYS_FATAL
+ bool "All cache exceptions considered fatal (no recovery attempted)"
+ depends on SIBYTE_SB1xxx_SOC
+
+-config CONFIG_SB1_CERR_STALL
++config SB1_CERR_STALL
+ bool "Stall (rather than panic) on fatal cache error"
+ depends on SIBYTE_SB1xxx_SOC
+
+diff -urN --ignore-space-change kernel.org/arch/mips/vr41xx/Kconfig linux-mips/arch/mips/vr41xx/Kconfig
+--- kernel.org/arch/mips/vr41xx/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/vr41xx/Kconfig 2006-01-10 11:21:16.000000000 +0000
+@@ -1,9 +1,34 @@
++config NEC_CMBVR4133
++ bool "Support for NEC CMB-VR4133"
++ depends on MACH_VR41XX
++ select CPU_VR41XX
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select HW_HAS_PCI
++ select PCI_VR41XX
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
++ select SYS_SUPPORTS_LITTLE_ENDIAN
++
++config ROCKHOPPER
++ bool "Support for Rockhopper baseboard"
++ depends on NEC_CMBVR4133
++ select I8259
++ select HAVE_STD_PC_SERIAL_PORT
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
++
+ config CASIO_E55
+ bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
+ depends on MACH_VR41XX
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select ISA
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
+ config IBM_WORKPAD
+@@ -12,52 +37,36 @@
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select ISA
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
+-config NEC_CMBVR4133
+- bool "Support for NEC CMB-VR4133"
+- depends on MACH_VR41XX
+- select CPU_VR41XX
+- select DMA_NONCOHERENT
+- select IRQ_CPU
+- select HW_HAS_PCI
-
-- vr41xx_select_siu_interface(SIU_INTERFACE_RS232C);
--
-- if (options != NULL)
-- uart_parse_options(options, &baud, &parity, &bits, &flow);
--
-- return uart_set_options(port, con, baud, parity, bits, flow);
--}
--
--static struct uart_driver siu_uart_driver;
--
--static struct console siu_console = {
-- .name = "ttyVR",
-- .write = siu_console_write,
-- .device = uart_console_device,
-- .setup = siu_console_setup,
-- .flags = CON_PRINTBUFFER,
-- .index = -1,
-- .data = &siu_uart_driver,
--};
+-config ROCKHOPPER
+- bool "Support for Rockhopper baseboard"
+- depends on NEC_CMBVR4133
+- select I8259
+- select HAVE_STD_PC_SERIAL_PORT
-
--static int __devinit siu_console_init(void)
--{
-- struct uart_port *port;
-- int num, i;
+ config TANBAC_TB022X
+- bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
++ bool "Support for TANBAC TB0225 (VR4131 multichip module) and TB0229 (VR4131DIMM)"
+ depends on MACH_VR41XX
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ help
+- The TANBAC VR4131 multichip module(TB0225) and
+- the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
+- manufactured by TANBAC.
+- Please refer to <http://www.tanbac.co.jp/>
+- about VR4131 multichip module and VR4131DIMM.
++ The TANBAC TB0225 (VR4131 multichip module) and TB0229 (VR4131DIMM)
++ are MIPS-based platforms manufactured by TANBAC.
++ Please refer to <http://www.tanbac.co.jp/> about
++ VR4131 Multi-chip module and VR4131DIMM.
+
+ config TANBAC_TB0226
+- bool "Support for TANBAC Mbase(TB0226)"
++ bool "Support for TANBAC TB0226 (Mbase)"
+ depends on TANBAC_TB022X
++ select PCI
++ select PCI_VR41XX
+ select GPIO_VR41XX
+ help
+- The TANBAC Mbase(TB0226) is a MIPS-based platform
+- manufactured by TANBAC.
+- Please refer to <http://www.tanbac.co.jp/> about Mbase.
-
-- num = siu_init_ports();
-- if (num <= 0)
-- return -ENODEV;
--
-- for (i = 0; i < num; i++) {
-- port = &siu_uart_ports[i];
-- port->ops = &siu_uart_ops;
-- }
+-config TANBAC_TB0287
+- bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
+- depends on TANBAC_TB022X
+- help
+- The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform
+- manufactured by TANBAC.
+- Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
++ The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by
++ TANBAC. Please refer to <http://www.tanbac.co.jp/> about Mbase.
+
+ config VICTOR_MPC30X
+ bool "Support for Victor MP-C303/304"
+@@ -65,7 +74,11 @@
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
++ depends on MACH_VR41XX
+
+ config ZAO_CAPCELLA
+ bool "Support for ZAO Networks Capcella"
+@@ -73,13 +86,14 @@
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
++ select SYS_HAS_CPU_VR41XX
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+
+ config PCI_VR41XX
+ bool "Add PCI control unit support of NEC VR4100 series"
+- depends on MACH_VR41XX && HW_HAS_PCI
+- default y
+- select PCI
++ depends on MACH_VR41XX && PCI
+
+ config VRC4173
+ tristate "Add NEC VRC4173 companion chip support"
+diff -urN --ignore-space-change kernel.org/arch/mips/vr41xx/nec-cmbvr4133/setup.c linux-mips/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+--- kernel.org/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/arch/mips/vr41xx/nec-cmbvr4133/setup.c 2006-01-10 11:21:16.000000000 +0000
+@@ -16,6 +16,7 @@
+ */
+ #include <linux/config.h>
+ #include <linux/init.h>
++#include <linux/console.h>
+ #include <linux/ide.h>
+ #include <linux/ioport.h>
+
+diff -urN --ignore-space-change kernel.org/drivers/char/Kconfig linux-mips/drivers/char/Kconfig
+--- kernel.org/drivers/char/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/char/Kconfig 2006-01-10 11:21:25.000000000 +0000
+@@ -331,23 +331,68 @@
+ To compile this driver as a module, choose M here: the
+ module will be called istallion.
+
+-config AU1000_UART
+- bool "Enable Au1000 UART Support"
+- depends on SERIAL_NONSTANDARD && MIPS
+- help
+- If you have an Alchemy AU1000 processor (MIPS based) and you want
+- to use serial ports, say Y. Otherwise, say N.
-
-- register_console(&siu_console);
+-config AU1000_SERIAL_CONSOLE
+- bool "Enable Au1000 serial console"
+- depends on AU1000_UART
++config AU1X00_GPIO
++ tristate "Alchemy Au1000 GPIO device support"
++ depends on MIPS && SOC_AU1X00
++
++config TS_AU1X00_ADS7846
++ tristate "Au1000/ADS7846 touchscreen support"
++ depends on MIPS && SOC_AU1X00
++
++config AU1X00_USB_TTY
++ tristate "Au1000 USB TTY Device support"
++ depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE
++
++config AU1X00_USB_RAW
++ tristate "Au1000 USB Raw Device support"
++ depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE
++
++config SIBYTE_SB1250_DUART
++ bool "Support for BCM1xxx onchip DUART"
++ depends on MIPS && SIBYTE_SB1xxx_SOC=y
++
++config SIBYTE_SB1250_DUART_CONSOLE
++ bool "Console on BCM1xxx DUART"
++ depends on SIBYTE_SB1250_DUART
++
++config SERIAL_DEC
++ bool "DECstation serial support"
++ depends on MACH_DECSTATION
++ default y
+ help
+- If you have an Alchemy AU1000 processor (MIPS based) and you want
+- to use a console on a serial port, say Y. Otherwise, say N.
++ This selects whether you want to be asked about drivers for
++ DECstation serial ports.
++
++ Note that the answer to this question won't directly affect the
++ kernel: saying N will just cause the configurator to skip all
++ the questions about DECstation serial ports.
++
++ If unsure, say Y.
++
++config SERIAL_DEC_CONSOLE
++ bool "Support for console on a DECstation serial port"
++ depends on SERIAL_DEC
++ default y
++ help
++ If you say Y here, it will be possible to use a serial port as the
++ system console (the system console is the device which receives all
++ kernel messages and warnings and which allows logins in single user
++ mode). Note that the firmware uses ttyS0 as the serial console on
++ the Maxine and ttyS2 on the others.
++
++ If unsure, say Y.
++
++config ZS
++ bool "Z85C30 Serial Support"
++ depends on SERIAL_DEC
++ default y
++ help
++ Documentation on the Zilog 85C350 serial communications controller
++ is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
+
+ config QTRONIX_KEYBOARD
+ bool "Enable Qtronix 990P Keyboard Support"
+- depends on IT8712
++ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ help
+ Images of Qtronix keyboards are at
+ <http://www.qtronix.com/keyboard.html>.
+@@ -359,7 +404,7 @@
+
+ config IT8172_SCR0
+ bool "Enable Smart Card Reader 0 Support "
+- depends on IT8712
++ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ help
+ Say Y here to support smart-card reader 0 (SCR0) on the Integrated
+ Technology Express, Inc. ITE8172 SBC. Vendor page at
+@@ -368,13 +413,17 @@
+
+ config IT8172_SCR1
+ bool "Enable Smart Card Reader 1 Support "
+- depends on IT8712
++ depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ help
+ Say Y here to support smart-card reader 1 (SCR1) on the Integrated
+ Technology Express, Inc. ITE8172 SBC. Vendor page at
+ <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+ board at <http://www.mvista.com/partners/semiconductor/ite.html>.
+
++config ITE_GPIO
++ tristate "ITE GPIO"
++ depends on MIPS && MIPS_ITE8172
++
+ config A2232
+ tristate "Commodore A2232 serial support (EXPERIMENTAL)"
+ depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
+diff -urN --ignore-space-change kernel.org/drivers/char/Makefile linux-mips/drivers/char/Makefile
+--- kernel.org/drivers/char/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/char/Makefile 2006-01-10 11:21:25.000000000 +0000
+@@ -31,6 +31,7 @@
+ obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
+ obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
+ obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
++obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
+ obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
+ obj-$(CONFIG_RISCOM8) += riscom8.o
+ obj-$(CONFIG_ISI) += isicom.o
+@@ -48,6 +49,7 @@
+ obj-$(CONFIG_VIOTAPE) += viotape.o
+ obj-$(CONFIG_HVCS) += hvcs.o
+ obj-$(CONFIG_SGI_MBCS) += mbcs.o
++obj-$(CONFIG_SERIAL_DEC) += decserial.o
+
+ obj-$(CONFIG_PRINTER) += lp.o
+ obj-$(CONFIG_TIPAR) += tipar.o
+@@ -76,6 +78,10 @@
+ obj-$(CONFIG_HW_RANDOM) += hw_random.o
+ obj-$(CONFIG_FTAPE) += ftape/
+ obj-$(CONFIG_COBALT_LCD) += lcd.o
++obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
++obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o
++obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o
++obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o
+ obj-$(CONFIG_PPDEV) += ppdev.o
+ obj-$(CONFIG_NWBUTTON) += nwbutton.o
+ obj-$(CONFIG_NWFLASH) += nwflash.o
+@@ -113,7 +119,8 @@
+
+ ifdef GENERATE_KEYMAP
+
+-$(obj)/defkeymap.c $(obj)/qtronixmap.c: $(obj)/%.c: $(src)/%.map
++$(obj)/defkeymap.c $(obj)/qtronixmap.c $(obj)/ibm_workpad_keymap.c: \
++ $(obj)/%.c: $(src)/%.map
+ loadkeys --mktable $< > $@.tmp
+ sed -e 's/^static *//' $@.tmp > $@
+ rm $@.tmp
+diff -urN --ignore-space-change kernel.org/drivers/char/au1000_gpio.c linux-mips/drivers/char/au1000_gpio.c
+--- kernel.org/drivers/char/au1000_gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/au1000_gpio.c 2006-01-10 11:21:25.000000000 +0000
+@@ -0,0 +1,266 @@
++/*
++ * FILE NAME au1000_gpio.c
++ *
++ * BRIEF MODULE DESCRIPTION
++ * Driver for Alchemy Au1000 GPIO.
++ *
++ * Author: MontaVista Software, Inc. <source at mvista.com>
++ * Steve Longerbeam <stevel at mvista.com>
++ *
++ * Copyright 2001 MontaVista Software Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/miscdevice.h>
++#include <linux/init.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/au1000.h>
++#include <asm/au1000_gpio.h>
++
++#define VERSION "0.01"
++
++static const struct {
++ u32 active_hi;
++ u32 avail_mask;
++} pinfunc_to_avail[15] = {
++ {1, 0x7<<16}, // 0 = SSI0 / GPIO[18:16]
++ {-1, 0}, // 1 = AC97 / SSI1
++ {1, 1<<19}, // 2 = IRDA / GPIO19
++ {1, 1<<20}, // 3 = UART0 / GPIO20
++ {1, 0x1f<<24}, // 4 = NIC2 / GPIO[28:24]
++ {1, 0x7<<29}, // 5 = I2S / GPIO[31:29]
++ {0, 1<<8}, // 6 = I2SDI / GPIO8
++ {0, 0x3f<<9}, // 7 = UART3 / GPIO[14:9]
++ {0, 1<<15}, // 8 = IRFIRSEL / GPIO15
++ {0, 1<<2}, // 9 = EXTCLK0 or OSC / GPIO2
++ {0, 1<<3}, // 10 = EXTCLK1 / GPIO3
++ {0, 1<<6}, // 11 = SMROMCKE / GPIO6
++ {1, 1<<21}, // 12 = UART1 / GPIO21
++ {1, 1<<22}, // 13 = UART2 / GPIO22
++ {1, 1<<23} // 14 = UART3 / GPIO23
++};
++
++
++u32 get_au1000_avail_gpio_mask(void)
++{
++ int i;
++ u32 pinfunc = inl(SYS_PINFUNC);
++ u32 avail_mask = 0; // start with no gpio available
++
++ // first, check for GPIO's reprogrammed as peripheral pins
++ for (i=0; i<15; i++) {
++ if (pinfunc_to_avail[i].active_hi < 0)
++ continue;
++ if (!(pinfunc_to_avail[i].active_hi ^
++ ((pinfunc & (1<<i)) ? 1:0)))
++ avail_mask |= pinfunc_to_avail[i].avail_mask;
++ }
++
++ // check for GPIO's used as interrupt sources
++ avail_mask &= ~(inl(IC1_MASKRD) &
++ (inl(IC1_CFG0RD) | inl(IC1_CFG1RD)));
++
++#ifdef CONFIG_USB_OHCI
++ avail_mask &= ~((1<<4) | (1<<11));
++#ifndef CONFIG_AU1X00_USB_DEVICE
++ avail_mask &= ~((1<<5) | (1<<13));
++#endif
++#endif
++
++ return avail_mask;
++}
++
++
++/*
++ * Tristate the requested GPIO pins specified in data.
++ * Only available GPIOs will be tristated.
++ */
++int au1000gpio_tristate(u32 data)
++{
++ data &= get_au1000_avail_gpio_mask();
++
++ if (data)
++ outl(data, SYS_TRIOUTCLR);
++
++ return 0;
++}
++
++
++/*
++ * Return the pin state. Pins configured as outputs will return
++ * the output state, and pins configured as inputs (tri-stated)
++ * will return input pin state.
++ */
++int au1000gpio_in(u32 *data)
++{
++ *data = inl(SYS_PINSTATERD);
++ return 0;
++}
++
++
++/*
++ * Set/clear GPIO pins. Only available GPIOs will be affected.
++ */
++int au1000gpio_set(u32 data)
++{
++ data &= get_au1000_avail_gpio_mask();
++
++ if (data)
++ outl(data, SYS_OUTPUTSET);
++ return 0;
++}
++
++int au1000gpio_clear(u32 data)
++{
++ data &= get_au1000_avail_gpio_mask();
++
++ if (data)
++ outl(data, SYS_OUTPUTCLR);
++ return 0;
++}
++
++/*
++ * Output data to GPIO pins. Only available GPIOs will be affected.
++ */
++int au1000gpio_out(u32 data)
++{
++ au1000gpio_set(data);
++ au1000gpio_clear(~data);
++ return 0;
++}
++
++
++EXPORT_SYMBOL(get_au1000_avail_gpio_mask);
++EXPORT_SYMBOL(au1000gpio_tristate);
++EXPORT_SYMBOL(au1000gpio_in);
++EXPORT_SYMBOL(au1000gpio_set);
++EXPORT_SYMBOL(au1000gpio_clear);
++EXPORT_SYMBOL(au1000gpio_out);
++
++
++static int au1000gpio_open(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++
++static int au1000gpio_release(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++
++static int au1000gpio_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int status;
++ u32 val;
++
++ switch(cmd) {
++ case AU1000GPIO_IN:
++
++ status = au1000gpio_in(&val);
++ if (status != 0)
++ return status;
++
++ return put_user(val, (u32 *)arg);
++
++ case AU1000GPIO_OUT:
++
++ if (get_user(val, (u32 *)arg))
++ return -EFAULT;
++
++ return au1000gpio_out(val);
++
++ case AU1000GPIO_SET:
++
++ if (get_user(val, (u32 *)arg))
++ return -EFAULT;
++
++ return au1000gpio_set(val);
++
++ case AU1000GPIO_CLEAR:
++
++ if (get_user(val, (u32 *)arg))
++ return -EFAULT;
++
++ return au1000gpio_clear(val);
++
++ case AU1000GPIO_TRISTATE:
++
++ if (get_user(val, (u32 *)arg))
++ return -EFAULT;
++
++ return au1000gpio_tristate(val);
++
++ case AU1000GPIO_AVAIL_MASK:
++
++ return put_user(get_au1000_avail_gpio_mask(),
++ (u32 *)arg);
++
++ default:
++ return -ENOIOCTLCMD;
++
++ }
++
++ return 0;
++}
++
++
++static struct file_operations au1000gpio_fops =
++{
++ .owner = THIS_MODULE,
++ .ioctl = au1000gpio_ioctl,
++ .open = au1000gpio_open,
++ .release = au1000gpio_release,
++};
++
++
++static struct miscdevice au1000gpio_miscdev =
++{
++ MISC_DYNAMIC_MINOR,
++ "au1000_gpio",
++ &au1000gpio_fops
++};
++
++
++int __init au1000gpio_init(void)
++{
++ misc_register(&au1000gpio_miscdev);
++ printk("Au1000 gpio driver, version %s\n", VERSION);
++ return 0;
++}
++
++
++void __exit au1000gpio_exit(void)
++{
++ misc_deregister(&au1000gpio_miscdev);
++}
++
++
++module_init(au1000gpio_init);
++module_exit(au1000gpio_exit);
+diff -urN --ignore-space-change kernel.org/drivers/char/au1000_ts.c linux-mips/drivers/char/au1000_ts.c
+--- kernel.org/drivers/char/au1000_ts.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/au1000_ts.c 2006-01-10 11:21:25.000000000 +0000
+@@ -0,0 +1,677 @@
++/*
++ * au1000_ts.c -- Touch screen driver for the Alchemy Au1000's
++ * SSI Port 0 talking to the ADS7846 touch screen
++ * controller.
++ *
++ * Copyright 2001 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ * stevel at mvista.com or source at mvista.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Notes:
++ *
++ * Revision history
++ * 06.27.2001 Initial version
++ */
++
++#include <linux/module.h>
++#include <linux/version.h>
++
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/delay.h>
++#include <linux/poll.h>
++#include <linux/string.h>
++#include <linux/ioport.h> /* request_region */
++#include <linux/interrupt.h> /* mark_bh */
++#include <asm/uaccess.h> /* get_user,copy_to_user */
++#include <asm/io.h>
++#include <asm/au1000.h>
++
++#define TS_NAME "au1000-ts"
++#define TS_MAJOR 11
++
++#define PFX TS_NAME
++#define AU1000_TS_DEBUG 1
++
++#ifdef AU1000_TS_DEBUG
++#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
++#else
++#define dbg(format, arg...) do {} while (0)
++#endif
++#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
++#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
++#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
++
++
++// SSI Status register bit defines
++#define SSISTAT_BF (1<<4)
++#define SSISTAT_OF (1<<3)
++#define SSISTAT_UF (1<<2)
++#define SSISTAT_DONE (1<<1)
++#define SSISTAT_BUSY (1<<0)
++
++// SSI Interrupt Pending and Enable register bit defines
++#define SSIINT_OI (1<<3)
++#define SSIINT_UI (1<<2)
++#define SSIINT_DI (1<<1)
++
++// SSI Address/Data register bit defines
++#define SSIADAT_D (1<<24)
++#define SSIADAT_ADDR_BIT 16
++#define SSIADAT_ADDR_MASK (0xff<<SSIADAT_ADDR_BIT)
++#define SSIADAT_DATA_BIT 0
++#define SSIADAT_DATA_MASK (0xfff<<SSIADAT_DATA_BIT)
++
++// SSI Enable register bit defines
++#define SSIEN_CD (1<<1)
++#define SSIEN_E (1<<0)
++
++// SSI Config register bit defines
++#define SSICFG_AO (1<<24)
++#define SSICFG_DO (1<<23)
++#define SSICFG_ALEN_BIT 20
++#define SSICFG_ALEN_MASK (0x7<<SSICFG_ALEN_BIT)
++#define SSICFG_DLEN_BIT 16
++#define SSICFG_DLEN_MASK (0xf<<SSICFG_DLEN_BIT)
++#define SSICFG_DD (1<<11)
++#define SSICFG_AD (1<<10)
++#define SSICFG_BM_BIT 8
++#define SSICFG_BM_MASK (0x3<<SSICFG_BM_BIT)
++#define SSICFG_CE (1<<7)
++#define SSICFG_DP (1<<6)
++#define SSICFG_DL (1<<5)
++#define SSICFG_EP (1<<4)
++
++// Bus Turnaround Selection
++#define SCLK_HOLD_HIGH 0
++#define SCLK_HOLD_LOW 1
++#define SCLK_CYCLE 2
++
++/*
++ * Default config for SSI0:
++ *
++ * - transmit MSBit first
++ * - expect MSBit first on data receive
++ * - address length 7 bits
++ * - expect data length 12 bits
++ * - do not disable Direction bit
++ * - do not disable Address bits
++ * - SCLK held low during bus turnaround
++ * - Address and Data bits clocked out on falling edge of SCLK
++ * - Direction bit high is a read, low is a write
++ * - Direction bit precedes Address bits
++ * - Active low enable signal
++ */
++
++#define DEFAULT_SSI_CONFIG \
++ (SSICFG_AO | SSICFG_DO | (6<<SSICFG_ALEN_BIT) | (11<<SSICFG_DLEN_BIT) |\
++ (SCLK_HOLD_LOW<<SSICFG_BM_BIT) | SSICFG_DP | SSICFG_EP)
++
++
++// ADS7846 Control Byte bit defines
++#define ADS7846_ADDR_BIT 4
++#define ADS7846_ADDR_MASK (0x7<<ADS7846_ADDR_BIT)
++#define ADS7846_MEASURE_X (0x5<<ADS7846_ADDR_BIT)
++#define ADS7846_MEASURE_Y (0x1<<ADS7846_ADDR_BIT)
++#define ADS7846_MEASURE_Z1 (0x3<<ADS7846_ADDR_BIT)
++#define ADS7846_MEASURE_Z2 (0x4<<ADS7846_ADDR_BIT)
++#define ADS7846_8BITS (1<<3)
++#define ADS7846_12BITS 0
++#define ADS7846_SER (1<<2)
++#define ADS7846_DFR 0
++#define ADS7846_PWR_BIT 0
++#define ADS7846_PD 0
++#define ADS7846_ADC_ON (0x1<<ADS7846_PWR_BIT)
++#define ADS7846_REF_ON (0x2<<ADS7846_PWR_BIT)
++#define ADS7846_REF_ADC_ON (0x3<<ADS7846_PWR_BIT)
++
++#define MEASURE_12BIT_X \
++ (ADS7846_MEASURE_X | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Y \
++ (ADS7846_MEASURE_Y | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Z1 \
++ (ADS7846_MEASURE_Z1 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Z2 \
++ (ADS7846_MEASURE_Z2 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++
++typedef enum {
++ IDLE = 0,
++ ACQ_X,
++ ACQ_Y,
++ ACQ_Z1,
++ ACQ_Z2
++} acq_state_t;
++
++/* +++++++++++++ Lifted from include/linux/h3600_ts.h ++++++++++++++*/
++typedef struct {
++ unsigned short pressure; // touch pressure
++ unsigned short x; // calibrated X
++ unsigned short y; // calibrated Y
++ unsigned short millisecs; // timestamp of this event
++} TS_EVENT;
++
++typedef struct {
++ int xscale;
++ int xtrans;
++ int yscale;
++ int ytrans;
++ int xyswap;
++} TS_CAL;
++
++/* Use 'f' as magic number */
++#define IOC_MAGIC 'f'
++
++#define TS_GET_RATE _IO(IOC_MAGIC, 8)
++#define TS_SET_RATE _IO(IOC_MAGIC, 9)
++#define TS_GET_CAL _IOR(IOC_MAGIC, 10, TS_CAL)
++#define TS_SET_CAL _IOW(IOC_MAGIC, 11, TS_CAL)
++
++/* +++++++++++++ Done lifted from include/linux/h3600_ts.h +++++++++*/
++
++
++#define EVENT_BUFSIZE 128
++
++/*
++ * Which pressure equation to use from ADS7846 datasheet.
++ * The first equation requires knowing only the X plate
++ * resistance, but needs 4 measurements (X, Y, Z1, Z2).
++ * The second equation requires knowing both X and Y plate
++ * resistance, but only needs 3 measurements (X, Y, Z1).
++ * The second equation is preferred because of the shorter
++ * acquisition time required.
++ */
++enum {
++ PRESSURE_EQN_1 = 0,
++ PRESSURE_EQN_2
++};
++
++
++/*
++ * The touch screen's X and Y plate resistances, used by
++ * pressure equations.
++ */
++#define DEFAULT_X_PLATE_OHMS 580
++#define DEFAULT_Y_PLATE_OHMS 580
++
++/*
++ * Pen up/down pressure resistance thresholds.
++ *
++ * FIXME: these are bogus and will have to be found empirically.
++ *
++ * These are hysteresis points. If pen state is up and pressure
++ * is greater than pen-down threshold, pen transitions to down.
++ * If pen state is down and pressure is less than pen-up threshold,
++ * pen transitions to up. If pressure is in-between, pen status
++ * doesn't change.
++ *
++ * This wouldn't be needed if PENIRQ* from the ADS7846 were
++ * routed to an interrupt line on the Au1000. This would issue
++ * an interrupt when the panel is touched.
++ */
++#define DEFAULT_PENDOWN_THRESH_OHMS 100
++#define DEFAULT_PENUP_THRESH_OHMS 80
++
++typedef struct {
++ int baudrate;
++ u32 clkdiv;
++ acq_state_t acq_state; // State of acquisition state machine
++ int x_raw, y_raw, z1_raw, z2_raw; // The current raw acquisition values
++ TS_CAL cal; // Calibration values
++ // The X and Y plate resistance, needed to calculate pressure
++ int x_plate_ohms, y_plate_ohms;
++ // pressure resistance at which pen is considered down/up
++ int pendown_thresh_ohms;
++ int penup_thresh_ohms;
++ int pressure_eqn; // eqn to use for pressure calc
++ int pendown; // 1 = pen is down, 0 = pen is up
++ TS_EVENT event_buf[EVENT_BUFSIZE];// The event queue
++ int nextIn, nextOut;
++ int event_count;
++ struct fasync_struct *fasync; // asynch notification
++ struct timer_list acq_timer; // Timer for triggering acquisitions
++ wait_queue_head_t wait; // read wait queue
++ spinlock_t lock;
++ struct tq_struct chug_tq;
++} au1000_ts_t;
++
++static au1000_ts_t au1000_ts;
++
++
++static inline u32
++calc_clkdiv(int baud)
++{
++ u32 sys_busclk =
++ (get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
++ return (sys_busclk / (2 * baud)) - 1;
++}
++
++static inline int
++calc_baudrate(u32 clkdiv)
++{
++ u32 sys_busclk =
++ (get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
++ return sys_busclk / (2 * (clkdiv + 1));
++}
++
++
++/*
++ * This is a bottom-half handler that is scheduled after
++ * raw X,Y,Z1,Z2 coordinates have been acquired, and does
++ * the following:
++ *
++ * - computes touch screen pressure resistance
++ * - if pressure is above a threshold considered to be pen-down:
++ * - compute calibrated X and Y coordinates
++ * - queue a new TS_EVENT
++ * - signal asynchronously and wake up any read
++ */
++static void
++chug_raw_data(void* private)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)private;
++ TS_EVENT event;
++ int Rt, Xcal, Ycal;
++ unsigned long flags;
++
++ // timestamp this new event.
++ event.millisecs = jiffies;
++
++ // Calculate touch pressure resistance
++ if (ts->pressure_eqn == PRESSURE_EQN_2) {
++ Rt = (ts->x_plate_ohms * ts->x_raw *
++ (4096 - ts->z1_raw)) / ts->z1_raw;
++ Rt -= (ts->y_plate_ohms * ts->y_raw);
++ Rt = (Rt + 2048) >> 12; // round up to nearest ohm
++ } else {
++ Rt = (ts->x_plate_ohms * ts->x_raw *
++ (ts->z2_raw - ts->z1_raw)) / ts->z1_raw;
++ Rt = (Rt + 2048) >> 12; // round up to nearest ohm
++ }
++
++ // hysteresis
++ if (!ts->pendown && Rt > ts->pendown_thresh_ohms)
++ ts->pendown = 1;
++ else if (ts->pendown && Rt < ts->penup_thresh_ohms)
++ ts->pendown = 0;
++
++ if (ts->pendown) {
++ // Pen is down
++ // Calculate calibrated X,Y
++ Xcal = ((ts->cal.xscale * ts->x_raw) >> 8) + ts->cal.xtrans;
++ Ycal = ((ts->cal.yscale * ts->y_raw) >> 8) + ts->cal.ytrans;
++
++ event.x = (unsigned short)Xcal;
++ event.y = (unsigned short)Ycal;
++ event.pressure = (unsigned short)Rt;
++
++ // add this event to the event queue
++ spin_lock_irqsave(&ts->lock, flags);
++ ts->event_buf[ts->nextIn++] = event;
++ if (ts->nextIn == EVENT_BUFSIZE)
++ ts->nextIn = 0;
++ if (ts->event_count < EVENT_BUFSIZE) {
++ ts->event_count++;
++ } else {
++ // throw out the oldest event
++ if (++ts->nextOut == EVENT_BUFSIZE)
++ ts->nextOut = 0;
++ }
++ spin_unlock_irqrestore(&ts->lock, flags);
++
++ // async notify
++ if (ts->fasync)
++ kill_fasync(&ts->fasync, SIGIO, POLL_IN);
++ // wake up any read call
++ if (waitqueue_active(&ts->wait))
++ wake_up_interruptible(&ts->wait);
++ }
++}
++
++
++/*
++ * Raw X,Y,pressure acquisition timer function. This triggers
++ * the start of a new acquisition. Its duration between calls
++ * is the touch screen polling rate.
++ */
++static void
++au1000_acq_timer(unsigned long data)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)data;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ts->lock, flags);
++
++ // start acquisition with X coordinate
++ ts->acq_state = ACQ_X;
++ // start me up
++ outl(SSIADAT_D | (MEASURE_12BIT_X << SSIADAT_ADDR_BIT), SSI0_ADATA);
++
++ // schedule next acquire
++ ts->acq_timer.expires = jiffies + HZ / 100;
++ add_timer(&ts->acq_timer);
++
++ spin_unlock_irqrestore(&ts->lock, flags);
++}
++
++static void
++ssi0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ au1000_ts_t *ts = (au1000_ts_t*)dev_id;
++ u32 stat, int_stat, data;
++
++ spin_lock(&ts->lock);
++
++ stat = inl(SSI0_STATUS);
++ // clear sticky status bits
++ outl(stat & (SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE), SSI0_STATUS);
++
++ int_stat = inl(SSI0_INT);
++ // clear sticky intr status bits
++ outl(int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI), SSI0_INT);
++
++ if ((int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI)) != SSIINT_DI) {
++ if (int_stat & SSIINT_OI)
++ err("overflow");
++ if (int_stat & SSIINT_UI)
++ err("underflow");
++ spin_unlock(&ts->lock);
++ return;
++ }
++
++ data = inl(SSI0_ADATA) & SSIADAT_DATA_MASK;
++
++ switch (ts->acq_state) {
++ case IDLE:
++ break;
++ case ACQ_X:
++ ts->x_raw = data;
++ ts->acq_state = ACQ_Y;
++ // trigger Y acq
++ outl(SSIADAT_D | (MEASURE_12BIT_Y << SSIADAT_ADDR_BIT),
++ SSI0_ADATA);
++ break;
++ case ACQ_Y:
++ ts->y_raw = data;
++ ts->acq_state = ACQ_Z1;
++ // trigger Z1 acq
++ outl(SSIADAT_D | (MEASURE_12BIT_Z1 << SSIADAT_ADDR_BIT),
++ SSI0_ADATA);
++ break;
++ case ACQ_Z1:
++ ts->z1_raw = data;
++ if (ts->pressure_eqn == PRESSURE_EQN_2) {
++ // don't acq Z2, using 2nd eqn for touch pressure
++ ts->acq_state = IDLE;
++ // got the raw stuff, now mark BH
++ queue_task(&ts->chug_tq, &tq_immediate);
++ mark_bh(IMMEDIATE_BH);
++ } else {
++ ts->acq_state = ACQ_Z2;
++ // trigger Z2 acq
++ outl(SSIADAT_D | (MEASURE_12BIT_Z2<<SSIADAT_ADDR_BIT),
++ SSI0_ADATA);
++ }
++ break;
++ case ACQ_Z2:
++ ts->z2_raw = data;
++ ts->acq_state = IDLE;
++ // got the raw stuff, now mark BH
++ queue_task(&ts->chug_tq, &tq_immediate);
++ mark_bh(IMMEDIATE_BH);
++ break;
++ }
++
++ spin_unlock(&ts->lock);
++}
++
++
++/* +++++++++++++ File operations ++++++++++++++*/
++
++static int
++au1000_fasync(int fd, struct file *filp, int mode)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++ return fasync_helper(fd, filp, mode, &ts->fasync);
++}
++
++static int
++au1000_ioctl(struct inode * inode, struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++
++ switch(cmd) {
++ case TS_GET_RATE: /* TODO: what is this? */
++ break;
++ case TS_SET_RATE: /* TODO: what is this? */
++ break;
++ case TS_GET_CAL:
++ copy_to_user((char *)arg, (char *)&ts->cal, sizeof(TS_CAL));
++ break;
++ case TS_SET_CAL:
++ copy_from_user((char *)&ts->cal, (char *)arg, sizeof(TS_CAL));
++ break;
++ default:
++ err("unknown cmd %04x", cmd);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static unsigned int
++au1000_poll(struct file * filp, poll_table * wait)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++ poll_wait(filp, &ts->wait, wait);
++ if (ts->event_count)
++ return POLLIN | POLLRDNORM;
++ return 0;
++}
++
++static ssize_t
++au1000_read(struct file * filp, char * buf, size_t count, loff_t * l)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++ unsigned long flags;
++ TS_EVENT event;
++ int i;
++
++ if (ts->event_count == 0) {
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++ interruptible_sleep_on(&ts->wait);
++ if (signal_pending(current))
++ return -ERESTARTSYS;
++ }
++
++ for (i = count;
++ i >= sizeof(TS_EVENT);
++ i -= sizeof(TS_EVENT), buf += sizeof(TS_EVENT)) {
++ if (ts->event_count == 0)
++ break;
++ spin_lock_irqsave(&ts->lock, flags);
++ event = ts->event_buf[ts->nextOut++];
++ if (ts->nextOut == EVENT_BUFSIZE)
++ ts->nextOut = 0;
++ if (ts->event_count)
++ ts->event_count--;
++ spin_unlock_irqrestore(&ts->lock, flags);
++ copy_to_user(buf, &event, sizeof(TS_EVENT));
++ }
++
++ return count - i;
++}
++
++
++static int
++au1000_open(struct inode * inode, struct file * filp)
++{
++ au1000_ts_t* ts;
++ unsigned long flags;
++
++ filp->private_data = ts = &au1000_ts;
++
++ spin_lock_irqsave(&ts->lock, flags);
++
++ // setup SSI0 config
++ outl(DEFAULT_SSI_CONFIG, SSI0_CONFIG);
++
++ // clear out SSI0 status bits
++ outl(SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE, SSI0_STATUS);
++ // clear out SSI0 interrupt pending bits
++ outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT);
++
++ // enable SSI0 interrupts
++ outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT_ENABLE);
++
++ /*
++ * init bh handler that chugs the raw data (calibrates and
++ * calculates touch pressure).
++ */
++ ts->chug_tq.routine = chug_raw_data;
++ ts->chug_tq.data = ts;
++ ts->pendown = 0; // pen up
++
++ // flush event queue
++ ts->nextIn = ts->nextOut = ts->event_count = 0;
++
++ // Start acquisition timer function
++ init_timer(&ts->acq_timer);
++ ts->acq_timer.function = au1000_acq_timer;
++ ts->acq_timer.data = (unsigned long)ts;
++ ts->acq_timer.expires = jiffies + HZ / 100;
++ add_timer(&ts->acq_timer);
++
++ spin_unlock_irqrestore(&ts->lock, flags);
++
++ return 0;
++}
++
++static int
++au1000_release(struct inode * inode, struct file * filp)
++{
++ au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++ unsigned long flags;
++
++ au1000_fasync(-1, filp, 0);
++ del_timer_sync(&ts->acq_timer);
++
++ spin_lock_irqsave(&ts->lock, flags);
++ // disable SSI0 interrupts
++ outl(0, SSI0_INT_ENABLE);
++ spin_unlock_irqrestore(&ts->lock, flags);
++
++ return 0;
++}
++
++
++static struct file_operations ts_fops = {
++ .read = au1000_read,
++ .poll = au1000_poll,
++ .ioctl = au1000_ioctl,
++ .fasync = au1000_fasync,
++ .open = au1000_open,
++ .release = au1000_release,
++};
++
++/* +++++++++++++ End File operations ++++++++++++++*/
++
++
++int __init
++au1000ts_init_module(void)
++{
++ au1000_ts_t* ts = &au1000_ts;
++ int ret;
++
++ /* register our character device */
++ if ((ret = register_chrdev(TS_MAJOR, TS_NAME, &ts_fops)) < 0) {
++ err("can't get major number");
++ return ret;
++ }
++ info("registered");
++
++ memset(ts, 0, sizeof(au1000_ts_t));
++ init_waitqueue_head(&ts->wait);
++ spin_lock_init(&ts->lock);
++
++ if (!request_region(virt_to_phys((void*)SSI0_STATUS), 0x100, TS_NAME)) {
++ err("SSI0 ports in use");
++ return -ENXIO;
++ }
++
++ if ((ret = request_irq(AU1000_SSI0_INT, ssi0_interrupt,
++ SA_SHIRQ | SA_INTERRUPT, TS_NAME, ts))) {
++ err("could not get IRQ");
++ return ret;
++ }
++
++ // initial calibration values
++ ts->cal.xscale = -93;
++ ts->cal.xtrans = 346;
++ ts->cal.yscale = -64;
++ ts->cal.ytrans = 251;
++
++ // init pen up/down hysteresis points
++ ts->pendown_thresh_ohms = DEFAULT_PENDOWN_THRESH_OHMS;
++ ts->penup_thresh_ohms = DEFAULT_PENUP_THRESH_OHMS;
++ ts->pressure_eqn = PRESSURE_EQN_2;
++ // init X and Y plate resistances
++ ts->x_plate_ohms = DEFAULT_X_PLATE_OHMS;
++ ts->y_plate_ohms = DEFAULT_Y_PLATE_OHMS;
++
++ // set GPIO to SSI0 function
++ outl(inl(PIN_FUNCTION) & ~1, PIN_FUNCTION);
++
++ // enable SSI0 clock and bring SSI0 out of reset
++ outl(0, SSI0_CONTROL);
++ udelay(1000);
++ outl(SSIEN_E, SSI0_CONTROL);
++ udelay(100);
++
++ // FIXME: is this a working baudrate?
++ ts->clkdiv = 0;
++ ts->baudrate = calc_baudrate(ts->clkdiv);
++ outl(ts->clkdiv, SSI0_CLKDIV);
++
++ info("baudrate = %d Hz", ts->baudrate);
++
++ return 0;
++}
++
++void
++au1000ts_cleanup_module(void)
++{
++ // disable clocks and hold in reset
++ outl(SSIEN_CD, SSI0_CONTROL);
++ free_irq(AU1000_SSI0_INT, &au1000_ts);
++ release_region(virt_to_phys((void*)SSI0_STATUS), 0x100);
++ unregister_chrdev(TS_MAJOR, TS_NAME);
++}
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1000/ADS7846 Touch Screen Driver");
++
++module_init(au1000ts_init_module);
++module_exit(au1000ts_cleanup_module);
+diff -urN --ignore-space-change kernel.org/drivers/char/au1000_usbraw.c linux-mips/drivers/char/au1000_usbraw.c
+--- kernel.org/drivers/char/au1000_usbraw.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/au1000_usbraw.c 2006-01-10 11:21:25.000000000 +0000
+@@ -0,0 +1,573 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ * Au1x00 USB Device-Side Raw Block Driver (function layer)
++ *
++ * Copyright 2001-2002 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ * stevel at mvista.com or source at mvista.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/errno.h>
++#include <linux/poll.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fcntl.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <linux/smp_lock.h>
++#undef DEBUG
++#include <linux/usb.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/au1000.h>
++#include <asm/au1000_usbdev.h>
++
++#define USBRAW_MAJOR 190 // FIXME: need a legal major
++#define USBRAW_NAME "usbraw"
++
++#define MAX_NUM_PORTS 2
++
++#define IN_MAX_PACKET_SIZE 64
++#define OUT_MAX_PACKET_SIZE 64
++
++// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
++#define NUM_PORTS 1
++#define NUM_EP 2*NUM_PORTS
++
++#define CONFIG_DESC_LEN \
++ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
++
++/* must be power of two */
++#define READ_BUF_SIZE (1<<12)
++
++struct usb_raw_port {
++ unsigned char number;
++ spinlock_t port_lock;
++
++ struct usb_endpoint_descriptor* out_desc;
++ struct usb_endpoint_descriptor* in_desc;
++
++ int out_ep_addr; /* endpoint address of OUT endpoint */
++ int in_ep_addr; /* endpoint address of IN endpoint */
++
++ __u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages
++ int read_nextin, read_nextout;
++ int read_count;
++
++ wait_queue_head_t wait;
++ struct fasync_struct *fasync; // asynch notification
++
++ int active; /* someone has this device open */
++ int open_count; /* number of times this port has been opened */
++};
++
++static struct usb_serial {
++ struct usb_device_descriptor* dev_desc;
++ struct usb_config_descriptor* config_desc;
++ struct usb_interface_descriptor* if_desc;
++ struct usb_string_descriptor * str_desc[6];
++ void* str_desc_buf;
++
++ usbdev_state_t dev_state;
++
++ struct usb_raw_port port[NUM_PORTS];
++} usbraw;
++
++static struct usb_device_descriptor dev_desc = {
++ bLength:USB_DT_DEVICE_SIZE,
++ bDescriptorType:USB_DT_DEVICE,
++ bcdUSB:USBDEV_REV, //usb rev
++ bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
++ bDeviceSubClass:0x00, //subclass (none)
++ bDeviceProtocol:0x00, //protocol (none)
++ bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
++ idVendor:0x6d04, //vendor id
++ idProduct:0x0bc0, //product id
++ bcdDevice:0x0001, //BCD rev 0.1
++ iManufacturer:0x01, //manufactuer string index
++ iProduct:0x02, //product string index
++ iSerialNumber:0x03, //serial# string index
++ bNumConfigurations:0x01 //num configurations
++};
++
++static struct usb_endpoint_descriptor ep_desc[] = {
++ {
++ // Bulk IN for Port 0
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_IN,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:IN_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk OUT for Port 0
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_OUT,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk IN for Port 1
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_IN,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:IN_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk OUT for Port 1
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_OUT,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ }
++};
++
++static struct usb_interface_descriptor if_desc = {
++ bLength:USB_DT_INTERFACE_SIZE,
++ bDescriptorType:USB_DT_INTERFACE,
++ bInterfaceNumber:0x00,
++ bAlternateSetting:0x00,
++ bNumEndpoints:NUM_EP,
++ bInterfaceClass:0xff,
++ bInterfaceSubClass:0xab,
++ bInterfaceProtocol:0x00,
++ iInterface:0x05
++};
++
++static struct usb_config_descriptor config_desc = {
++ bLength:USB_DT_CONFIG_SIZE,
++ bDescriptorType:USB_DT_CONFIG,
++ wTotalLength:CONFIG_DESC_LEN,
++ bNumInterfaces:0x01,
++ bConfigurationValue:0x01,
++ iConfiguration:0x04, // configuration string
++ bmAttributes:0xc0, // self-powered
++ MaxPower:20 // 40 mA
++};
++
++// String[0] is a list of Language IDs supported by this device
++static struct usb_string_descriptor string_desc0 = {
++ bLength:4,
++ bDescriptorType:USB_DT_STRING,
++ wData:{0x0409} // English, US
++};
++
++// These strings will be converted to Unicode in string_desc[]
++static char *strings[5] = {
++ "Alchemy Semiconductor", // iManufacturer
++ "USB Raw Block Device", // iProduct
++ "0.1", // iSerialNumber
++ "USB Raw Config", // iConfiguration
++ "USB Raw Interface" // iInterface
++};
++
++
++static void
++receive_callback(struct usb_raw_port *port)
++{
++ int i, pkt_size;
++ usbdev_pkt_t* pkt;
++
++ if ((pkt_size = usbdev_receive_packet(port->out_ep_addr,
++ &pkt)) <= 0) {
++ dbg(__FUNCTION__ ": usbdev_receive_packet returns %d",
++ pkt_size);
++ return;
++ }
++
++ dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size);
++
++ spin_lock(&port->port_lock);
++ for (i=0; i < pkt_size; i++) {
++ port->read_buf[port->read_nextin++] = pkt->payload[i];
++ port->read_nextin &= (READ_BUF_SIZE - 1);
++ if (++port->read_count == READ_BUF_SIZE)
++ break;
++ }
++ spin_unlock(&port->port_lock);
++
++ /* free the packet */
++ kfree(pkt);
++
++ // async notify
++ if (port->fasync)
++ kill_fasync(&port->fasync, SIGIO, POLL_IN);
++ // wake up any read call
++ if (waitqueue_active(&port->wait))
++ wake_up_interruptible(&port->wait);
++}
++
++static void
++transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt)
++{
++ dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
++ /* just free the returned packet */
++ kfree(pkt);
++}
++
++
++static void
++usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
++{
++ usbdev_pkt_t* pkt;
++ int i;
++
++ switch (cb_type) {
++ case CB_NEW_STATE:
++ usbraw.dev_state = (usbdev_state_t)arg;
++ break;
++ case CB_PKT_COMPLETE:
++ pkt = (usbdev_pkt_t*)arg;
++ for (i=0; i<NUM_PORTS; i++) {
++ struct usb_raw_port *port = &usbraw.port[i];
++ if (pkt->ep_addr == port->in_ep_addr) {
++ transmit_callback(port, pkt);
++ break;
++ } else if (pkt->ep_addr == port->out_ep_addr) {
++ receive_callback(port);
++ break;
++ }
++ }
++ break;
++ }
++}
++
++/*****************************************************************************
++ * Here begins the driver interface functions
++ *****************************************************************************/
++
++static unsigned int usbraw_poll(struct file * filp, poll_table * wait)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++ unsigned long flags;
++ int count;
++
++ poll_wait(filp, &port->wait, wait);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++ count = port->read_count;
++ spin_unlock_irqrestore(&port->port_lock, flags);
++
++ if (count > 0) {
++ dbg(__FUNCTION__ ": count=%d", count);
++ return POLLIN | POLLRDNORM;
++ }
++
++ return 0;
++}
++
++static int usbraw_fasync(int fd, struct file *filp, int mode)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++ return fasync_helper(fd, filp, mode, &port->fasync);
++}
++
++static int usbraw_open(struct inode * inode, struct file *filp)
++{
++ int portNumber;
++ struct usb_raw_port *port;
++ unsigned long flags;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbraw.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ /* set up our port structure making the tty driver remember
++ our port object, and us it */
++ portNumber = MINOR(inode->i_rdev);
++ port = &usbraw.port[portNumber];
++ filp->private_data = port;
++
++ dbg(__FUNCTION__ ": port %d", port->number);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++
++ ++port->open_count;
++
++ if (!port->active) {
++ port->active = 1;
++ }
++
++ /* flush read buffer */
++ port->read_nextin = port->read_nextout = port->read_count = 0;
++
++ spin_unlock_irqrestore(&port->port_lock, flags);
++
++ return 0;
++}
++
++static int usbraw_release(struct inode * inode, struct file * filp)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++ unsigned long flags;
++
++ dbg(__FUNCTION__ ": port %d", port->number);
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not opened");
++ return -ENODEV;
++ }
++
++ usbraw_fasync(-1, filp, 0);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++
++ --port->open_count;
++
++ if (port->open_count <= 0) {
++ port->active = 0;
++ port->open_count = 0;
++ }
++
++ spin_unlock_irqrestore(&port->port_lock, flags);
++
++ return 0;
++}
++
++
++static ssize_t usbraw_read(struct file * filp, char * buf,
++ size_t count, loff_t * l)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++ unsigned long flags;
++ int i, cnt;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbraw.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ do {
++ spin_lock_irqsave(&port->port_lock, flags);
++ cnt = port->read_count;
++ spin_unlock_irqrestore(&port->port_lock, flags);
++ if (cnt == 0) {
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++ interruptible_sleep_on(&port->wait);
++ if (signal_pending(current))
++ return -ERESTARTSYS;
++ }
++ } while (cnt == 0);
++
++ count = (count > cnt) ? cnt : count;
++
++ for (i=0; i<count; i++) {
++ put_user(port->read_buf[port->read_nextout++], &buf[i]);
++ port->read_nextout &= (READ_BUF_SIZE - 1);
++ spin_lock_irqsave(&port->port_lock, flags);
++ port->read_count--;
++ spin_unlock_irqrestore(&port->port_lock, flags);
++ if (port->read_count == 0)
++ break;
++ }
++
++ return i+1;
++}
++
++static ssize_t usbraw_write(struct file * filp, const char * buf,
++ size_t count, loff_t *ppos)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++ usbdev_pkt_t* pkt;
++ int ret, max_pkt_sz;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbraw.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not opened");
++ return -EINVAL;
++ }
++
++ if (count == 0) {
++ dbg(__FUNCTION__ ": write request of 0 bytes");
++ return (0);
++ }
++
++ max_pkt_sz = port->in_desc->wMaxPacketSize;
++ count = (count > max_pkt_sz) ? max_pkt_sz : count;
++
++ if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0)
++ return ret;
++
++ copy_from_user(pkt->payload, buf, count);
++
++ return usbdev_send_packet(port->in_ep_addr, pkt);
++}
++
++static int usbraw_ioctl(struct inode *inode, struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not open");
++ return -ENODEV;
++ }
++ // FIXME: need any IOCTLs?
++
++ return -ENOIOCTLCMD;
++}
++
++
++static struct file_operations usbraw_fops = {
++ .owner = THIS_MODULE,
++ .write = usbraw_write,
++ .read = usbraw_read,
++ .poll = usbraw_poll,
++ .ioctl = usbraw_ioctl,
++ .fasync = usbraw_fasync,
++ .open = usbraw_open,
++ .release = usbraw_release,
++};
++
++void usbfn_raw_exit(void)
++{
++ /* kill the device layer */
++ usbdev_exit();
++
++ unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME);
++
++ if (usbraw.str_desc_buf)
++ kfree(usbraw.str_desc_buf);
++}
++
++
++int usbfn_raw_init(void)
++{
++ int ret = 0, i, str_desc_len;
++
++ /* register our character device */
++ if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME,
++ &usbraw_fops)) < 0) {
++ err("can't get major number");
++ return ret;
++ }
++ info("registered");
++
++ /*
++ * initialize pointers to descriptors
++ */
++ usbraw.dev_desc = &dev_desc;
++ usbraw.config_desc = &config_desc;
++ usbraw.if_desc = &if_desc;
++
++ /*
++ * initialize the string descriptors
++ */
++
++ /* alloc buffer big enough for all string descriptors */
++ str_desc_len = string_desc0.bLength;
++ for (i = 0; i < 5; i++)
++ str_desc_len += 2 + 2 * strlen(strings[i]);
++ usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
++ if (!usbraw.str_desc_buf) {
++ err(__FUNCTION__ ": failed to alloc string descriptors");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ usbraw.str_desc[0] =
++ (struct usb_string_descriptor *)usbraw.str_desc_buf;
++ memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength);
++ usbraw.str_desc[1] = (struct usb_string_descriptor *)
++ (usbraw.str_desc_buf + string_desc0.bLength);
++ for (i = 1; i < 6; i++) {
++ struct usb_string_descriptor *desc = usbraw.str_desc[i];
++ char *str = strings[i - 1];
++ int j, str_len = strlen(str);
++
++ desc->bLength = 2 + 2 * str_len;
++ desc->bDescriptorType = USB_DT_STRING;
++ for (j = 0; j < str_len; j++) {
++ desc->wData[j] = (u16) str[j];
++ }
++ if (i < 5)
++ usbraw.str_desc[i + 1] =
++ (struct usb_string_descriptor *)
++ ((u8 *) desc + desc->bLength);
++ }
++
++ /*
++ * start the device layer. The device layer assigns us
++ * our endpoint addresses
++ */
++ if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
++ usbraw.str_desc, usbraw_callback, NULL))) {
++ err(__FUNCTION__ ": device-layer init failed");
++ goto out;
++ }
++
++ /* initialize the devfs nodes for this device and let the user
++ know what ports we are bound to */
++ for (i = 0; i < NUM_PORTS; ++i) {
++ struct usb_raw_port *port = &usbraw.port[i];
++
++ port->number = i;
++ port->in_desc = &ep_desc[NUM_PORTS*i];
++ port->out_desc = &ep_desc[NUM_PORTS*i + 1];
++ port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
++ port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
++ init_waitqueue_head(&port->wait);
++ spin_lock_init(&port->port_lock);
++ }
++
++ out:
++ if (ret)
++ usbfn_raw_exit();
++ return ret;
++}
++
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver");
++MODULE_LICENSE("GPL");
++
++module_init(usbfn_raw_init);
++module_exit(usbfn_raw_exit);
+diff -urN --ignore-space-change kernel.org/drivers/char/au1000_usbtty.c linux-mips/drivers/char/au1000_usbtty.c
+--- kernel.org/drivers/char/au1000_usbtty.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/au1000_usbtty.c 2006-01-10 11:21:25.000000000 +0000
+@@ -0,0 +1,761 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ * Au1x00 USB Device-Side Serial TTY Driver (function layer)
++ *
++ * Copyright 2001-2002 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ * stevel at mvista.com or source at mvista.com
++ *
++ * Derived from drivers/usb/serial/usbserial.c:
++ *
++ * Copyright (C) 1999 - 2001 Greg Kroah-Hartman (greg at kroah.com)
++ * Copyright (c) 2000 Peter Berger (pberger at brimson.com)
++ * Copyright (c) 2000 Al Borchers (borchers at steinerpoint.com)
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/errno.h>
++#include <linux/poll.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fcntl.h>
++#include <linux/tty.h>
++#include <linux/tty_driver.h>
++#include <linux/tty_flip.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <linux/smp_lock.h>
++#undef DEBUG
++#include <linux/usb.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/au1000.h>
++#include <asm/au1000_usbdev.h>
++
++
++/* local function prototypes */
++static int serial_open(struct tty_struct *tty, struct file *filp);
++static void serial_close(struct tty_struct *tty, struct file *filp);
++static int serial_write(struct tty_struct *tty, int from_user,
++ const unsigned char *buf, int count);
++static int serial_write_room(struct tty_struct *tty);
++static int serial_chars_in_buffer(struct tty_struct *tty);
++static void serial_throttle(struct tty_struct *tty);
++static void serial_unthrottle(struct tty_struct *tty);
++static int serial_ioctl(struct tty_struct *tty, struct file *file,
++ unsigned int cmd, unsigned long arg);
++static void serial_set_termios (struct tty_struct *tty, struct termios * old);
++
++#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major
++
++#define MAX_NUM_PORTS 2
++
++#define IN_MAX_PACKET_SIZE 32
++#define OUT_MAX_PACKET_SIZE 32
++
++// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
++#define NUM_PORTS 2
++#define NUM_EP 2*NUM_PORTS
++
++#define CONFIG_DESC_LEN \
++ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
++
++struct usb_serial_port {
++ struct tty_struct *tty; /* the coresponding tty for this port */
++ unsigned char number;
++ spinlock_t port_lock;
++
++ struct usb_endpoint_descriptor* out_desc;
++ struct usb_endpoint_descriptor* in_desc;
++
++ int out_ep_addr; /* endpoint address of OUT endpoint */
++ int in_ep_addr; /* endpoint address of IN endpoint */
++
++ /* task queue for line discipline waking up on send packet complete */
++ struct tq_struct send_complete_tq;
++ /* task queue for line discipline wakeup on receive packet complete */
++ struct tq_struct receive_complete_tq;
++
++ int active; /* someone has this device open */
++ int writing; /* a packet write is in progress */
++ int open_count; /* number of times this port has been opened */
++
++};
++
++static struct usb_serial {
++ usbdev_state_t dev_state; // current state of device layer
++ struct usb_device_descriptor* dev_desc;
++ struct usb_config_descriptor* config_desc;
++ struct usb_interface_descriptor* if_desc;
++ struct usb_string_descriptor * str_desc[6];
++ void* str_desc_buf;
++
++ struct usb_serial_port port[NUM_PORTS];
++} usbtty;
++
++static int serial_refcount;
++static struct tty_driver serial_tty_driver;
++static struct tty_struct * serial_tty[NUM_PORTS];
++static struct termios * serial_termios[NUM_PORTS];
++static struct termios * serial_termios_locked[NUM_PORTS];
++
++static struct usb_device_descriptor dev_desc = {
++ bLength:USB_DT_DEVICE_SIZE,
++ bDescriptorType:USB_DT_DEVICE,
++ bcdUSB:USBDEV_REV, //usb rev
++ bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
++ bDeviceSubClass:0x00, //subclass (none)
++ bDeviceProtocol:0x00, //protocol (none)
++ bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
++ idVendor:0x6d04, //vendor id
++ idProduct:0x0bc0, //product id
++ bcdDevice:0x0001, //BCD rev 0.1
++ iManufacturer:0x01, //manufactuer string index
++ iProduct:0x02, //product string index
++ iSerialNumber:0x03, //serial# string index
++ bNumConfigurations:0x01 //num configurations
++};
++
++static struct usb_endpoint_descriptor ep_desc[] = {
++ {
++ // Bulk IN for Port 0
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_IN,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:IN_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk OUT for Port 0
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_OUT,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk IN for Port 1
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_IN,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:IN_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ },
++ {
++ // Bulk OUT for Port 1
++ bLength:USB_DT_ENDPOINT_SIZE,
++ bDescriptorType:USB_DT_ENDPOINT,
++ bEndpointAddress:USB_DIR_OUT,
++ bmAttributes:USB_ENDPOINT_XFER_BULK,
++ wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++ bInterval:0x00 // ignored for bulk
++ }
++};
++
++static struct usb_interface_descriptor if_desc = {
++ bLength:USB_DT_INTERFACE_SIZE,
++ bDescriptorType:USB_DT_INTERFACE,
++ bInterfaceNumber:0x00,
++ bAlternateSetting:0x00,
++ bNumEndpoints:NUM_EP,
++ bInterfaceClass:0xff,
++ bInterfaceSubClass:0xab,
++ bInterfaceProtocol:0x00,
++ iInterface:0x05
++};
++
++static struct usb_config_descriptor config_desc = {
++ bLength:USB_DT_CONFIG_SIZE,
++ bDescriptorType:USB_DT_CONFIG,
++ wTotalLength:CONFIG_DESC_LEN,
++ bNumInterfaces:0x01,
++ bConfigurationValue:0x01,
++ iConfiguration:0x04, // configuration string
++ bmAttributes:0xc0, // self-powered
++ MaxPower:20 // 40 mA
++};
++
++// String[0] is a list of Language IDs supported by this device
++static struct usb_string_descriptor string_desc0 = {
++ bLength:4,
++ bDescriptorType:USB_DT_STRING,
++ wData:{0x0409} // English, US
++};
++
++// These strings will be converted to Unicode in string_desc[]
++static char *strings[5] = {
++ "Alchemy Semiconductor", // iManufacturer
++ "WutzAMattaU", // iProduct
++ "1.0.doh!", // iSerialNumber
++ "Au1000 TTY Config", // iConfiguration
++ "Au1000 TTY Interface" // iInterface
++};
++
++static inline int
++port_paranoia_check(struct usb_serial_port *port, const char *function)
++{
++ if (!port) {
++ err("%s: port is NULL", function);
++ return -1;
++ }
++ if (!port->tty) {
++ err("%s: port->tty is NULL", function);
++ return -1;
++ }
++
++ return 0;
++}
++
++
++static void
++port_rx_callback(struct usb_serial_port *port)
++{
++ dbg(__FUNCTION__ ": ep%d", port->out_ep_addr);
++ // mark a bh to push this data up to the tty
++ queue_task(&port->receive_complete_tq, &tq_immediate);
++ mark_bh(IMMEDIATE_BH);
++}
++
++static void
++port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt)
++{
++ dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
++ // mark a bh to wakeup any tty write system call on the port.
++ queue_task(&port->send_complete_tq, &tq_immediate);
++ mark_bh(IMMEDIATE_BH);
++
++ /* free the returned packet */
++ kfree(pkt);
++}
++
++static void
++usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
++{
++ usbdev_pkt_t* pkt;
++ int i;
++
++ switch (cb_type) {
++ case CB_NEW_STATE:
++ dbg(__FUNCTION__ ": new dev_state=%d", (int)arg);
++ usbtty.dev_state = (usbdev_state_t)arg;
++ break;
++ case CB_PKT_COMPLETE:
++ pkt = (usbdev_pkt_t*)arg;
++ for (i=0; i<NUM_PORTS; i++) {
++ struct usb_serial_port *port = &usbtty.port[i];
++ if (pkt->ep_addr == port->in_ep_addr) {
++ port_tx_callback(port, pkt);
++ break;
++ } else if (pkt->ep_addr == port->out_ep_addr) {
++ port_rx_callback(port);
++ break;
++ }
++ }
++ break;
++ }
++}
++
++
++/*****************************************************************************
++ * Here begins the tty driver interface functions
++ *****************************************************************************/
++
++static int serial_open(struct tty_struct *tty, struct file *filp)
++{
++ int portNumber;
++ struct usb_serial_port *port;
++ unsigned long flags;
++
++ /* initialize the pointer incase something fails */
++ tty->driver_data = NULL;
++
++ /* set up our port structure making the tty driver remember
++ our port object, and us it */
++ portNumber = MINOR(tty->device);
++ port = &usbtty.port[portNumber];
++ tty->driver_data = port;
++ port->tty = tty;
++
++ if (usbtty.dev_state != CONFIGURED ||
++ port_paranoia_check(port, __FUNCTION__)) {
++ /*
++ * the device-layer must be in the configured state before
++ * the function layer can operate.
++ */
++ return -ENODEV;
++ }
++
++ dbg(__FUNCTION__ ": port %d", port->number);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++
++ ++port->open_count;
++
++ if (!port->active) {
++ port->active = 1;
++
++ /*
++ * force low_latency on so that our tty_push actually forces
++ * the data through, otherwise it is scheduled, and with high
++ * data rates (like with OHCI) data can get lost.
++ */
++ port->tty->low_latency = 1;
++
++ }
++
++ spin_unlock_irqrestore(&port->port_lock, flags);
++
++ return 0;
++}
++
++
++static void serial_close(struct tty_struct *tty, struct file *filp)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++ unsigned long flags;
++
++ dbg(__FUNCTION__ ": port %d", port->number);
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not opened");
++ return;
++ }
++
++ spin_lock_irqsave(&port->port_lock, flags);
++
++ --port->open_count;
++
++ if (port->open_count <= 0) {
++ port->active = 0;
++ port->open_count = 0;
++ }
++
++ spin_unlock_irqrestore(&port->port_lock, flags);
++ MOD_DEC_USE_COUNT;
++}
++
++
++static int serial_write(struct tty_struct *tty, int from_user,
++ const unsigned char *buf, int count)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++ usbdev_pkt_t* pkt;
++ int max_pkt_sz, ret;
++ unsigned long flags;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbtty.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not open");
++ return -EINVAL;
++ }
++
++ if (count == 0) {
++ dbg(__FUNCTION__ ": request of 0 bytes");
++ return (0);
++ }
++
++#if 0
++ if (port->writing) {
++ dbg(__FUNCTION__ ": already writing");
++ return 0;
++ }
++#endif
++
++ max_pkt_sz = port->in_desc->wMaxPacketSize;
++ count = (count > max_pkt_sz) ? max_pkt_sz : count;
++
++ if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)))
++ return ret;
++
++ if (from_user)
++ copy_from_user(pkt->payload, buf, count);
++ else
++ memcpy(pkt->payload, buf, count);
++
++ ret = usbdev_send_packet(port->in_ep_addr, pkt);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++ port->writing = 1;
++ spin_unlock_irqrestore(&port->port_lock, flags);
++
++ return ret;
++}
++
++
++static int serial_write_room(struct tty_struct *tty)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++ int room = 0;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbtty.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not open");
++ return -EINVAL;
++ }
++
++ //room = port->writing ? 0 : port->in_desc->wMaxPacketSize;
++ room = port->in_desc->wMaxPacketSize;
++
++ dbg(__FUNCTION__ ": %d", room);
++ return room;
++}
++
++
++static int serial_chars_in_buffer(struct tty_struct *tty)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++ int chars = 0;
++
++ /*
++ * the device-layer must be in the configured state before the
++ * function layer can operate.
++ */
++ if (usbtty.dev_state != CONFIGURED)
++ return -ENODEV;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not open");
++ return -EINVAL;
++ }
++
++ //chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0;
++ chars = usbdev_get_byte_count(port->in_ep_addr);
++
++ dbg(__FUNCTION__ ": %d", chars);
++ return chars;
++}
++
++
++static void serial_throttle(struct tty_struct *tty)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++
++ if (!port->active || usbtty.dev_state != CONFIGURED) {
++ err(__FUNCTION__ ": port not open");
++ return;
++ }
++
++ // FIXME: anything to do?
++ dbg(__FUNCTION__);
++}
++
++
++static void serial_unthrottle(struct tty_struct *tty)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++
++ if (!port->active || usbtty.dev_state != CONFIGURED) {
++ err(__FUNCTION__ ": port not open");
++ return;
++ }
++
++ // FIXME: anything to do?
++ dbg(__FUNCTION__);
++}
++
++
++static int serial_ioctl(struct tty_struct *tty, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++
++ if (!port->active) {
++ err(__FUNCTION__ ": port not open");
++ return -ENODEV;
++ }
++ // FIXME: need any IOCTLs?
++ dbg(__FUNCTION__);
++
++ return -ENOIOCTLCMD;
++}
++
++
++static void serial_set_termios(struct tty_struct *tty, struct termios *old)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++
++ if (!port->active || usbtty.dev_state != CONFIGURED) {
++ err(__FUNCTION__ ": port not open");
++ return;
++ }
++
++ dbg(__FUNCTION__);
++ // FIXME: anything to do?
++}
++
++
++static void serial_break(struct tty_struct *tty, int break_state)
++{
++ struct usb_serial_port *port =
++ (struct usb_serial_port *) tty->driver_data;
++
++ if (!port->active || usbtty.dev_state != CONFIGURED) {
++ err(__FUNCTION__ ": port not open");
++ return;
++ }
++
++ dbg(__FUNCTION__);
++ // FIXME: anything to do?
++}
++
++
++static void port_send_complete(void *private)
++{
++ struct usb_serial_port *port = (struct usb_serial_port *) private;
++ struct tty_struct *tty;
++ unsigned long flags;
++
++ dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr);
++
++ tty = port->tty;
++ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++ tty->ldisc.write_wakeup) {
++ dbg(__FUNCTION__ ": write wakeup call.");
++ (tty->ldisc.write_wakeup) (tty);
++ }
++
++ wake_up_interruptible(&tty->write_wait);
++
++ spin_lock_irqsave(&port->port_lock, flags);
++ port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1;
++ spin_unlock_irqrestore(&port->port_lock, flags);
++}
++
++
++static void port_receive_complete(void *private)
++{
++ struct usb_serial_port *port = (struct usb_serial_port *) private;
++ struct tty_struct *tty = port->tty;
++ usbdev_pkt_t* pkt = NULL;
++ int i, count;
++
++ /* while there is a packet available */
++ while ((count = usbdev_receive_packet(port->out_ep_addr,
++ &pkt)) != -ENODATA) {
++ if (count < 0) {
++ if (pkt)
++ kfree(pkt);
++ break; /* exit if error other than ENODATA */
++ }
++
++ dbg(__FUNCTION__ ": port %d, ep%d, size=%d",
++ port->number, port->out_ep_addr, count);
++
++ for (i = 0; i < count; i++) {
++ /* if we insert more than TTY_FLIPBUF_SIZE characters,
++ we drop them. */
++ if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
++ tty_flip_buffer_push(tty);
++ }
++ /* this doesn't actually push the data through
++ unless tty->low_latency is set */
++ tty_insert_flip_char(tty, pkt->payload[i], 0);
++ }
++ tty_flip_buffer_push(tty);
++
++ kfree(pkt); /* make sure we free the packet */
++ }
++
++}
++
++
++static struct tty_driver serial_tty_driver = {
++ .magic= TTY_DRIVER_MAGIC,
++ .driver_name= "usbfn-tty",
++ .name= "usb/ttsdev/%d",
++ .major= SERIAL_TTY_MAJOR,
++ .minor_start= 0,
++ .num= NUM_PORTS,
++ .type= TTY_DRIVER_TYPE_SERIAL,
++ .subtype= SERIAL_TYPE_NORMAL,
++ .flags= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
++ .refcount= &serial_refcount,
++ .table= serial_tty,
++ .termios= serial_termios,
++ .termios_locked= serial_termios_locked,
++
++ .open= serial_open,
++ .close= serial_close,
++ .write= serial_write,
++ .write_room= serial_write_room,
++ .ioctl= serial_ioctl,
++ .set_termios= serial_set_termios,
++ .throttle= serial_throttle,
++ .unthrottle= serial_unthrottle,
++ .break_ctl= serial_break,
++ .chars_in_buffer= serial_chars_in_buffer,
++};
++
++
++void usbfn_tty_exit(void)
++{
++ int i;
++
++ /* kill the device layer */
++ usbdev_exit();
++
++ for (i=0; i < NUM_PORTS; i++) {
++ tty_unregister_devfs(&serial_tty_driver, i);
++ info("usb serial converter now disconnected from ttyUSBdev%d",
++ i);
++ }
++
++ tty_unregister_driver(&serial_tty_driver);
++
++ if (usbtty.str_desc_buf)
++ kfree(usbtty.str_desc_buf);
++}
++
++
++int usbfn_tty_init(void)
++{
++ int ret = 0, i, str_desc_len;
++
++ /* register the tty driver */
++ serial_tty_driver.init_termios = tty_std_termios;
++ serial_tty_driver.init_termios.c_cflag =
++ B9600 | CS8 | CREAD | HUPCL | CLOCAL;
++
++ if (tty_register_driver(&serial_tty_driver)) {
++ err(__FUNCTION__ ": failed to register tty driver");
++ ret = -ENXIO;
++ goto out;
++ }
++
++ /*
++ * initialize pointers to descriptors
++ */
++ usbtty.dev_desc = &dev_desc;
++ usbtty.config_desc = &config_desc;
++ usbtty.if_desc = &if_desc;
++
++ /*
++ * initialize the string descriptors
++ */
++
++ /* alloc buffer big enough for all string descriptors */
++ str_desc_len = string_desc0.bLength;
++ for (i = 0; i < 5; i++)
++ str_desc_len += 2 + 2 * strlen(strings[i]);
++ usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
++ if (!usbtty.str_desc_buf) {
++ err(__FUNCTION__ ": failed to alloc string descriptors");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ usbtty.str_desc[0] =
++ (struct usb_string_descriptor *)usbtty.str_desc_buf;
++ memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength);
++ usbtty.str_desc[1] = (struct usb_string_descriptor *)
++ (usbtty.str_desc_buf + string_desc0.bLength);
++ for (i = 1; i < 6; i++) {
++ struct usb_string_descriptor *desc = usbtty.str_desc[i];
++ char *str = strings[i - 1];
++ int j, str_len = strlen(str);
++
++ desc->bLength = 2 + 2 * str_len;
++ desc->bDescriptorType = USB_DT_STRING;
++ for (j = 0; j < str_len; j++) {
++ desc->wData[j] = (u16) str[j];
++ }
++ if (i < 5)
++ usbtty.str_desc[i + 1] =
++ (struct usb_string_descriptor *)
++ ((u8 *) desc + desc->bLength);
++ }
++
++ /*
++ * start the device layer. The device layer assigns us
++ * our endpoint addresses
++ */
++ if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
++ usbtty.str_desc, usbtty_callback, NULL))) {
++ err(__FUNCTION__ ": device-layer init failed");
++ goto out;
++ }
++
++ /* initialize the devfs nodes for this device and let the user
++ know what ports we are bound to */
++ for (i = 0; i < NUM_PORTS; ++i) {
++ struct usb_serial_port *port;
++ tty_register_devfs(&serial_tty_driver, 0, i);
++ info("usbdev serial attached to ttyUSBdev%d "
++ "(or devfs usb/ttsdev/%d)", i, i);
++ port = &usbtty.port[i];
++ port->number = i;
++ port->in_desc = &ep_desc[NUM_PORTS*i];
++ port->out_desc = &ep_desc[NUM_PORTS*i + 1];
++ port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
++ port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
++ port->send_complete_tq.routine = port_send_complete;
++ port->send_complete_tq.data = port;
++ port->receive_complete_tq.routine = port_receive_complete;
++ port->receive_complete_tq.data = port;
++ spin_lock_init(&port->port_lock);
++ }
++
++ out:
++ if (ret)
++ usbfn_tty_exit();
++ return ret;
++}
++
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel at mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver");
++MODULE_LICENSE("GPL");
++
++module_init(usbfn_tty_init);
++module_exit(usbfn_tty_exit);
+diff -urN --ignore-space-change kernel.org/drivers/char/decserial.c linux-mips/drivers/char/decserial.c
+--- kernel.org/drivers/char/decserial.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/char/decserial.c 2006-01-10 11:21:25.000000000 +0000
+@@ -14,87 +14,85 @@
+ * device. Added support for PROM console in drivers/char/tty_io.c
+ * instead. Although it may work to enable more than one
+ * console device I strongly recommend to use only one.
++ *
++ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+
+ #include <linux/config.h>
++#include <linux/errno.h>
+ #include <linux/init.h>
+-#include <asm/dec/machtype.h>
-
-- return 0;
--}
+-#ifdef CONFIG_ZS
+-extern int zs_init(void);
+-#endif
+
+-#ifdef CONFIG_DZ
+-extern int dz_init(void);
+-#endif
++#include <asm/dec/machtype.h>
++#include <asm/dec/serial.h>
+
+-#ifdef CONFIG_SERIAL_CONSOLE
++extern int register_zs_hook(unsigned int channel,
++ struct dec_serial_hook *hook);
++extern int unregister_zs_hook(unsigned int channel);
+
++int register_dec_serial_hook(unsigned int channel,
++ struct dec_serial_hook *hook)
++{
+ #ifdef CONFIG_ZS
+-extern void zs_serial_console_init(void);
+-#endif
-
--console_initcall(siu_console_init);
+-#ifdef CONFIG_DZ
+-extern void dz_serial_console_init(void);
++ if (IOASIC)
++ return register_zs_hook(channel, hook);
+ #endif
++ return 0;
++}
+
++int unregister_dec_serial_hook(unsigned int channel)
++{
++#ifdef CONFIG_ZS
++ if (IOASIC)
++ return unregister_zs_hook(channel);
+ #endif
++ return 0;
++}
+
+-/* rs_init - starts up the serial interface -
+- handle normal case of starting up the serial interface */
+
+-#ifdef CONFIG_SERIAL
++extern int zs_init(void);
++extern int dz_init(void);
+
++/*
++ * rs_init - starts up the serial interface -
++ * handle normal case of starting up the serial interface
++ */
+ int __init rs_init(void)
+ {
-
--#define SERIAL_VR41XX_CONSOLE &siu_console
+-#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
+- if (IOASIC)
+- return zs_init();
+- else
+- return dz_init();
-#else
--#define SERIAL_VR41XX_CONSOLE NULL
--#endif
-
--static struct uart_driver siu_uart_driver = {
-- .owner = THIS_MODULE,
-- .driver_name = "SIU",
-- .dev_name = "ttyVR",
-- .devfs_name = "ttvr/",
-- .major = SIU_MAJOR,
-- .minor = SIU_MINOR_BASE,
-- .cons = SERIAL_VR41XX_CONSOLE,
--};
+ #ifdef CONFIG_ZS
++ if (IOASIC)
+ return zs_init();
+ #endif
-
--static int siu_probe(struct device *dev)
--{
-- struct uart_port *port;
-- int num, i, retval;
+ #ifdef CONFIG_DZ
++ if (!IOASIC)
+ return dz_init();
+ #endif
-
-- num = siu_init_ports();
-- if (num <= 0)
-- return -ENODEV;
--
-- siu_uart_driver.nr = num;
-- retval = uart_register_driver(&siu_uart_driver);
-- if (retval)
-- return retval;
--
-- for (i = 0; i < num; i++) {
-- port = &siu_uart_ports[i];
-- port->ops = &siu_uart_ops;
-- port->dev = dev;
--
-- retval = uart_add_one_port(&siu_uart_driver, port);
-- if (retval < 0) {
-- port->dev = NULL;
-- break;
-- }
-- }
+-#endif
++ return -ENXIO;
+ }
+
+ __initcall(rs_init);
+
+-#endif
+
+-#ifdef CONFIG_SERIAL_CONSOLE
++#ifdef CONFIG_SERIAL_DEC_CONSOLE
+
+-/* serial_console_init handles the special case of starting
++extern void zs_serial_console_init(void);
++extern void dz_serial_console_init(void);
++
++/*
++ * dec_serial_console_init handles the special case of starting
+ * up the console on the serial port
+ */
+-static int __init decserial_console_init(void)
++static int __init dec_serial_console_init(void)
+ {
+-#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
+- if (IOASIC)
+- zs_serial_console_init();
+- else
+- dz_serial_console_init();
+-#else
-
-- if (i == 0 && retval < 0) {
-- uart_unregister_driver(&siu_uart_driver);
-- return retval;
-- }
+ #ifdef CONFIG_ZS
++ if (IOASIC)
+ zs_serial_console_init();
+ #endif
-
-- return 0;
--}
+ #ifdef CONFIG_DZ
++ if (!IOASIC)
+ dz_serial_console_init();
+ #endif
-
--static int siu_remove(struct device *dev)
--{
-- struct uart_port *port;
-- int i;
+-#endif
+ return 0;
+ }
+-console_initcall(decserial_console_init);
++console_initcall(dec_serial_console_init);
+
+ #endif
+diff -urN --ignore-space-change kernel.org/drivers/char/ibm_workpad_keymap.map linux-mips/drivers/char/ibm_workpad_keymap.map
+--- kernel.org/drivers/char/ibm_workpad_keymap.map 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/ibm_workpad_keymap.map 2006-01-10 11:21:27.000000000 +0000
+@@ -0,0 +1,343 @@
++# Keymap for IBM Workpad z50
++# US Mapping
++#
++# by Michael Klar <wyldfier at iname.com>
++#
++# This is a great big mess on account of how the Caps Lock key is handled as
++# LeftShift-RightShift. Right shift key had to be broken out, so don't use
++# use this map file as a basis for other keyboards that don't do the same
++# thing with Caps Lock.
++#
++# This file is subject to the terms and conditions of the GNU General Public
++# License. See the file "COPYING" in the main directory of this archive
++# for more details.
++
++keymaps 0-2,4-5,8,12,32-33,36-37
++strings as usual
++
++keycode 0 = F1 F11 Console_13
++ shiftr keycode 0 = F11
++ shift shiftr keycode 0 = F11
++ control keycode 0 = F1
++ alt keycode 0 = Console_1
++ control alt keycode 0 = Console_1
++keycode 1 = F3 F13 Console_15
++ shiftr keycode 1 = F13
++ shift shiftr keycode 1 = F13
++ control keycode 1 = F3
++ alt keycode 1 = Console_3
++ control alt keycode 1 = Console_3
++keycode 2 = F5 F15 Console_17
++ shiftr keycode 2 = F15
++ shift shiftr keycode 2 = F15
++ control keycode 2 = F5
++ alt keycode 2 = Console_5
++ control alt keycode 2 = Console_5
++keycode 3 = F7 F17 Console_19
++ shiftr keycode 3 = F17
++ shift shiftr keycode 3 = F17
++ control keycode 3 = F7
++ alt keycode 3 = Console_7
++ control alt keycode 3 = Console_7
++keycode 4 = F9 F19 Console_21
++ shiftr keycode 4 = F19
++ shift shiftr keycode 4 = F19
++ control keycode 4 = F9
++ alt keycode 4 = Console_9
++ control alt keycode 4 = Console_9
++#keycode 5 is contrast down
++#keycode 6 is contrast up
++keycode 7 = F11 F11 Console_23
++ shiftr keycode 7 = F11
++ shift shiftr keycode 7 = F11
++ control keycode 7 = F11
++ alt keycode 7 = Console_11
++ control alt keycode 7 = Console_11
++keycode 8 = F2 F12 Console_14
++ shiftr keycode 8 = F12
++ shift shiftr keycode 8 = F12
++ control keycode 8 = F2
++ alt keycode 8 = Console_2
++ control alt keycode 8 = Console_2
++keycode 9 = F4 F14 Console_16
++ shiftr keycode 9 = F14
++ shift shiftr keycode 9 = F14
++ control keycode 9 = F4
++ alt keycode 9 = Console_4
++ control alt keycode 9 = Console_4
++keycode 10 = F6 F16 Console_18
++ shiftr keycode 10 = F16
++ shift shiftr keycode 10 = F16
++ control keycode 10 = F6
++ alt keycode 10 = Console_6
++ control alt keycode 10 = Console_6
++keycode 11 = F8 F18 Console_20
++ shiftr keycode 11 = F18
++ shift shiftr keycode 11 = F18
++ control keycode 11 = F8
++ alt keycode 11 = Console_8
++ control alt keycode 11 = Console_8
++keycode 12 = F10 F20 Console_22
++ shiftr keycode 12 = F20
++ shift shiftr keycode 12 = F20
++ control keycode 12 = F10
++ alt keycode 12 = Console_10
++ control alt keycode 12 = Console_10
++#keycode 13 is brightness down
++#keycode 14 is brightness up
++keycode 15 = F12 F12 Console_24
++ shiftr keycode 15 = F12
++ shift shiftr keycode 15 = F12
++ control keycode 15 = F12
++ alt keycode 15 = Console_12
++ control alt keycode 15 = Console_12
++keycode 16 = apostrophe quotedbl
++ shiftr keycode 16 = quotedbl
++ shift shiftr keycode 16 = quotedbl
++ control keycode 16 = Control_g
++ alt keycode 16 = Meta_apostrophe
++keycode 17 = bracketleft braceleft
++ shiftr keycode 17 = braceleft
++ shift shiftr keycode 17 = braceleft
++ control keycode 17 = Escape
++ alt keycode 17 = Meta_bracketleft
++keycode 18 = minus underscore backslash
++ shiftr keycode 18 = underscore
++ shift shiftr keycode 18 = underscore
++ control keycode 18 = Control_underscore
++ shift control keycode 18 = Control_underscore
++ shiftr control keycode 18 = Control_underscore
++ shift shiftr control keycode 18 = Control_underscore
++ alt keycode 18 = Meta_minus
++keycode 19 = zero parenright braceright
++ shiftr keycode 19 = parenright
++ shift shiftr keycode 19 = parenright
++ alt keycode 19 = Meta_zero
++keycode 20 = p
++ shiftr keycode 20 = +P
++ shift shiftr keycode 20 = +p
++keycode 21 = semicolon colon
++ shiftr keycode 21 = colon
++ shift shiftr keycode 21 = colon
++ alt keycode 21 = Meta_semicolon
++keycode 22 = Up Scroll_Backward
++ shiftr keycode 22 = Scroll_Backward
++ shift shiftr keycode 22 = Scroll_Backward
++ alt keycode 22 = Prior
++keycode 23 = slash question
++ shiftr keycode 23 = question
++ shift shiftr keycode 23 = question
++ control keycode 23 = Delete
++ alt keycode 23 = Meta_slash
++
++keycode 27 = nine parenleft bracketright
++ shiftr keycode 27 = parenleft
++ shift shiftr keycode 27 = parenleft
++ alt keycode 27 = Meta_nine
++keycode 28 = o
++ shiftr keycode 28 = +O
++ shift shiftr keycode 28 = +o
++keycode 29 = l
++ shiftr keycode 29 = +L
++ shift shiftr keycode 29 = +l
++keycode 30 = period greater
++ shiftr keycode 30 = greater
++ shift shiftr keycode 30 = greater
++ control keycode 30 = Compose
++ alt keycode 30 = Meta_period
++
++keycode 32 = Left Decr_Console
++ shiftr keycode 32 = Decr_Console
++ shift shiftr keycode 32 = Decr_Console
++ alt keycode 32 = Home
++keycode 33 = bracketright braceright asciitilde
++ shiftr keycode 33 = braceright
++ shift shiftr keycode 33 = braceright
++ control keycode 33 = Control_bracketright
++ alt keycode 33 = Meta_bracketright
++keycode 34 = equal plus
++ shiftr keycode 34 = plus
++ shift shiftr keycode 34 = plus
++ alt keycode 34 = Meta_equal
++keycode 35 = eight asterisk bracketleft
++ shiftr keycode 35 = asterisk
++ shift shiftr keycode 35 = asterisk
++ control keycode 35 = Delete
++ alt keycode 35 = Meta_eight
++keycode 36 = i
++ shiftr keycode 36 = +I
++ shift shiftr keycode 36 = +i
++keycode 37 = k
++ shiftr keycode 37 = +K
++ shift shiftr keycode 37 = +k
++keycode 38 = comma less
++ shiftr keycode 38 = less
++ shift shiftr keycode 38 = less
++ alt keycode 38 = Meta_comma
++
++keycode 40 = h
++ shiftr keycode 40 = +H
++ shift shiftr keycode 40 = +h
++keycode 41 = y
++ shiftr keycode 41 = +Y
++ shift shiftr keycode 41 = +y
++keycode 42 = six asciicircum
++ shiftr keycode 42 = asciicircum
++ shift shiftr keycode 42 = asciicircum
++ control keycode 42 = Control_asciicircum
++ alt keycode 42 = Meta_six
++keycode 43 = seven ampersand braceleft
++ shiftr keycode 43 = ampersand
++ shift shiftr keycode 43 = ampersand
++ control keycode 43 = Control_underscore
++ alt keycode 43 = Meta_seven
++keycode 44 = u
++ shiftr keycode 44 = +U
++ shift shiftr keycode 44 = +u
++keycode 45 = j
++ shiftr keycode 45 = +J
++ shift shiftr keycode 45 = +j
++keycode 46 = m
++ shiftr keycode 46 = +M
++ shift shiftr keycode 46 = +m
++keycode 47 = n
++ shiftr keycode 47 = +N
++ shift shiftr keycode 47 = +n
++
++# This is the "Backspace" key:
++keycode 49 = Delete Delete
++ shiftr keycode 49 = Delete
++ shift shiftr keycode 49 = Delete
++ control keycode 49 = BackSpace
++ alt keycode 49 = Meta_Delete
++keycode 50 = Num_Lock
++ shift keycode 50 = Bare_Num_Lock
++ shiftr keycode 50 = Bare_Num_Lock
++ shift shiftr keycode 50 = Bare_Num_Lock
++# This is the "Delete" key:
++keycode 51 = Remove
++ control alt keycode 51 = Boot
++
++keycode 53 = backslash bar
++ shiftr keycode 53 = bar
++ shift shiftr keycode 53 = bar
++ control keycode 53 = Control_backslash
++ alt keycode 53 = Meta_backslash
++keycode 54 = Return
++ alt keycode 54 = Meta_Control_m
++keycode 55 = space space
++ shiftr keycode 55 = space
++ shift shiftr keycode 55 = space
++ control keycode 55 = nul
++ alt keycode 55 = Meta_space
++keycode 56 = g
++ shiftr keycode 56 = +G
++ shift shiftr keycode 56 = +g
++keycode 57 = t
++ shiftr keycode 57 = +T
++ shift shiftr keycode 57 = +t
++keycode 58 = five percent
++ shiftr keycode 58 = percent
++ shift shiftr keycode 58 = percent
++ control keycode 58 = Control_bracketright
++ alt keycode 58 = Meta_five
++keycode 59 = four dollar dollar
++ shiftr keycode 59 = dollar
++ shift shiftr keycode 59 = dollar
++ control keycode 59 = Control_backslash
++ alt keycode 59 = Meta_four
++keycode 60 = r
++ shiftr keycode 60 = +R
++ shift shiftr keycode 60 = +r
++keycode 61 = f
++ shiftr keycode 61 = +F
++ shift shiftr keycode 61 = +f
++ altgr keycode 61 = Hex_F
++keycode 62 = v
++ shiftr keycode 62 = +V
++ shift shiftr keycode 62 = +v
++keycode 63 = b
++ shiftr keycode 63 = +B
++ shift shiftr keycode 63 = +b
++ altgr keycode 63 = Hex_B
++
++keycode 67 = three numbersign
++ shiftr keycode 67 = numbersign
++ shift shiftr keycode 67 = numbersign
++ control keycode 67 = Escape
++ alt keycode 67 = Meta_three
++keycode 68 = e
++ shiftr keycode 68 = +E
++ shift shiftr keycode 68 = +e
++ altgr keycode 68 = Hex_E
++keycode 69 = d
++ shiftr keycode 69 = +D
++ shift shiftr keycode 69 = +d
++ altgr keycode 69 = Hex_D
++keycode 70 = c
++ shiftr keycode 70 = +C
++ shift shiftr keycode 70 = +c
++ altgr keycode 70 = Hex_C
++keycode 71 = Right Incr_Console
++ shiftr keycode 71 = Incr_Console
++ shift shiftr keycode 71 = Incr_Console
++ alt keycode 71 = End
++
++keycode 75 = two at at
++ shiftr keycode 75 = at
++ shift shiftr keycode 75 = at
++ control keycode 75 = nul
++ shift control keycode 75 = nul
++ shiftr control keycode 75 = nul
++ shift shiftr control keycode 75 = nul
++ alt keycode 75 = Meta_two
++keycode 76 = w
++ shiftr keycode 76 = +W
++ shift shiftr keycode 76 = +w
++keycode 77 = s
++ shiftr keycode 77 = +S
++ shift shiftr keycode 77 = +s
++keycode 78 = x
++ shiftr keycode 78 = +X
++ shift shiftr keycode 78 = +x
++keycode 79 = Down Scroll_Forward
++ shiftr keycode 79 = Scroll_Forward
++ shift shiftr keycode 79 = Scroll_Forward
++ alt keycode 79 = Next
++keycode 80 = Escape Escape
++ shiftr keycode 80 = Escape
++ shift shiftr keycode 80 = Escape
++ alt keycode 80 = Meta_Escape
++keycode 81 = Tab Tab
++ shiftr keycode 81 = Tab
++ shift shiftr keycode 81 = Tab
++ alt keycode 81 = Meta_Tab
++keycode 82 = grave asciitilde
++ shiftr keycode 82 = asciitilde
++ shift shiftr keycode 82 = asciitilde
++ control keycode 82 = nul
++ alt keycode 82 = Meta_grave
++keycode 83 = one exclam
++ shiftr keycode 83 = exclam
++ shift shiftr keycode 83 = exclam
++ alt keycode 83 = Meta_one
++keycode 84 = q
++ shiftr keycode 84 = +Q
++ shift shiftr keycode 84 = +q
++keycode 85 = a
++ shiftr keycode 85 = +A
++ shift shiftr keycode 85 = +a
++ altgr keycode 85 = Hex_A
++keycode 86 = z
++ shiftr keycode 86 = +Z
++ shift shiftr keycode 86 = +z
++
++# This is the windows key:
++keycode 88 = Decr_Console
++keycode 89 = Shift
++keycode 90 = Control
++keycode 91 = Control
++keycode 92 = Alt
++keycode 93 = AltGr
++keycode 94 = ShiftR
++ shift keycode 94 = Caps_Lock
+diff -urN --ignore-space-change kernel.org/drivers/char/qtronix.c linux-mips/drivers/char/qtronix.c
+--- kernel.org/drivers/char/qtronix.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/char/qtronix.c 2006-01-10 11:21:31.000000000 +0000
+@@ -535,8 +535,7 @@
+ i--;
+ }
+ if (count-i) {
+- struct inode *inode = file->f_dentry->d_inode;
+- inode->i_atime = current_fs_time(inode->i_sb);
++ file->f_dentry->d_inode->i_atime = get_seconds();
+ return count-i;
+ }
+ if (signal_pending(current))
+diff -urN --ignore-space-change kernel.org/drivers/char/rtc.c linux-mips/drivers/char/rtc.c
+--- kernel.org/drivers/char/rtc.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/char/rtc.c 2006-01-10 11:21:32.000000000 +0000
+@@ -46,12 +46,10 @@
+ * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
+ * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
+ * CONFIG_HPET_EMULATE_RTC
+- *
++ * 1.12a Maciej W. Rozycki: Handle memory-mapped chips properly.
+ */
+
+-#define RTC_VERSION "1.12"
-
-- for (i = 0; i < siu_uart_driver.nr; i++) {
-- port = &siu_uart_ports[i];
-- if (port->dev == dev) {
-- uart_remove_one_port(&siu_uart_driver, port);
-- port->dev = NULL;
-- }
+-#define RTC_IO_EXTENT 0x8
++#define RTC_VERSION "1.12a"
+
+ /*
+ * Note that *all* calls to CMOS_READ and CMOS_WRITE are done with
+@@ -338,7 +336,15 @@
+ if (rtc_has_irq == 0)
+ return -EIO;
+
+- if (count < sizeof(unsigned))
++ /*
++ * Historically this function used to assume that sizeof(unsigned long)
++ * is the same in userspace and kernelspace. This lead to problems
++ * for configurations with multiple ABIs such a the MIPS o32 and 64
++ * ABIs supported on the same kernel. So now we support read of both
++ * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the
++ * userspace ABI.
++ */
++ if (count != sizeof(unsigned int) && count != sizeof(unsigned long))
+ return -EINVAL;
+
+ add_wait_queue(&rtc_wait, &wait);
+@@ -369,10 +375,12 @@
+ schedule();
+ } while (1);
+
+- if (count < sizeof(unsigned long))
++ if (count == sizeof(unsigned int))
+ retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int);
+ else
+ retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long);
++ if (!retval)
++ retval = count;
+ out:
+ current->state = TASK_RUNNING;
+ remove_wait_queue(&rtc_wait, &wait);
+@@ -924,6 +932,9 @@
+ struct sparc_isa_device *isa_dev;
+ #endif
+ #endif
++#ifndef __sparc__
++ void *r;
++#endif
+
+ #ifdef __sparc__
+ for_each_ebus(ebus) {
+@@ -969,8 +980,13 @@
+ }
+ no_irq:
+ #else
+- if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) {
+- printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0));
++ if (RTC_IOMAPPED)
++ r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
++ else
++ r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
++ if (!r) {
++ printk(KERN_ERR "rtc: I/O resource %lx is not free.\n",
++ (long)(RTC_PORT(0)));
+ return -EIO;
+ }
+
+@@ -984,7 +1000,10 @@
+ if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) {
+ /* Yeah right, seeing as irq 8 doesn't even hit the bus. */
+ printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ);
++ if (RTC_IOMAPPED)
+ release_region(RTC_PORT(0), RTC_IO_EXTENT);
++ else
++ release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
+ return -EIO;
+ }
+ hpet_rtc_timer_init();
+@@ -1084,7 +1103,10 @@
+ if (rtc_has_irq)
+ free_irq (rtc_irq, &rtc_port);
+ #else
+- release_region (RTC_PORT (0), RTC_IO_EXTENT);
++ if (RTC_IOMAPPED)
++ release_region(RTC_PORT(0), RTC_IO_EXTENT);
++ else
++ release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
+ #ifdef RTC_IRQ
+ if (rtc_has_irq)
+ free_irq (RTC_IRQ, NULL);
+diff -urN --ignore-space-change kernel.org/drivers/char/sb1250_duart.c linux-mips/drivers/char/sb1250_duart.c
+--- kernel.org/drivers/char/sb1250_duart.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/char/sb1250_duart.c 2006-01-10 11:21:32.000000000 +0000
+@@ -0,0 +1,915 @@
++/*
++ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++/*
++ * Driver support for the on-chip sb1250 dual-channel serial port,
++ * running in asynchronous mode. Also, support for doing a serial console
++ * on one of those ports
++ */
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/console.h>
++#include <linux/kdev_t.h>
++#include <linux/major.h>
++#include <linux/termios.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/errno.h>
++#include <linux/tty.h>
++#include <linux/sched.h>
++#include <linux/tty_flip.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <asm/delay.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/sibyte/swarm.h>
++#include <asm/sibyte/sb1250.h>
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#include <asm/sibyte/bcm1480_regs.h>
++#include <asm/sibyte/bcm1480_int.h>
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
++#include <asm/sibyte/sb1250_regs.h>
++#include <asm/sibyte/sb1250_int.h>
++#else
++#error invalid SiByte UART configuation
++#endif
++#include <asm/sibyte/sb1250_uart.h>
++#include <asm/war.h>
++
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#define UNIT_CHANREG(n,reg) A_BCM1480_DUART_CHANREG((n),(reg))
++#define UNIT_IMRREG(n) A_BCM1480_DUART_IMRREG(n)
++#define UNIT_INT(n) (K_BCM1480_INT_UART_0 + (n))
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
++#define UNIT_CHANREG(n,reg) A_DUART_CHANREG((n),(reg))
++#define UNIT_IMRREG(n) A_DUART_IMRREG(n)
++#define UNIT_INT(n) (K_INT_UART_0 + (n))
++#else
++#error invalid SiByte UART configuation
++#endif
++
++/* Toggle spewing of debugging output */
++#undef DEBUG
++
++#define DEFAULT_CFLAGS (CS8 | B115200)
++
++#define TX_INTEN 1
++#define DUART_INITIALIZED 2
++
++#define DUART_MAX_LINE 4
++char sb1250_duart_present[DUART_MAX_LINE];
++EXPORT_SYMBOL(sb1250_duart_present);
++
++/*
++ * Still not sure what the termios structures set up here are for,
++ * but we have to supply pointers to them to register the tty driver
++ */
++static struct tty_driver *sb1250_duart_driver; //, sb1250_duart_callout_driver;
++
++/*
++ * This lock protects both the open flags for all the uart states as
++ * well as the reference count for the module
++ */
++static DEFINE_SPINLOCK(open_lock);
++
++typedef struct {
++ unsigned char outp_buf[SERIAL_XMIT_SIZE];
++ unsigned int outp_head;
++ unsigned int outp_tail;
++ unsigned int outp_count;
++ spinlock_t outp_lock;
++ unsigned int open;
++ unsigned int line;
++ unsigned int last_cflags;
++ unsigned long flags;
++ struct tty_struct *tty;
++ /* CSR addresses */
++ u32 *status;
++ u32 *imr;
++ u32 *tx_hold;
++ u32 *rx_hold;
++ u32 *mode_1;
++ u32 *mode_2;
++ u32 *clk_sel;
++ u32 *cmd;
++} uart_state_t;
++
++static uart_state_t uart_states[DUART_MAX_LINE];
++
++/*
++ * Inline functions local to this module
++ */
++
++/*
++ * In bug 1956, we get glitches that can mess up uart registers. This
++ * "write-mode-1 after any register access" is the accepted
++ * workaround.
++ */
++#if SIBYTE_1956_WAR
++static unsigned int last_mode1[DUART_MAX_LINE];
++#endif
++
++static inline u32 READ_SERCSR(u32 *addr, int line)
++{
++ u32 val = csr_in32(addr);
++#if SIBYTE_1956_WAR
++ csr_out32(last_mode1[line], uart_states[line].mode_1);
++#endif
++ return val;
++}
++
++static inline void WRITE_SERCSR(u32 val, u32 *addr, int line)
++{
++ csr_out32(val, addr);
++#if SIBYTE_1956_WAR
++ csr_out32(last_mode1[line], uart_states[line].mode_1);
++#endif
++}
++
++static void init_duart_port(uart_state_t *port, int line)
++{
++ if (!(port->flags & DUART_INITIALIZED)) {
++ port->line = line;
++ port->status = IOADDR(UNIT_CHANREG(line, R_DUART_STATUS));
++ port->imr = IOADDR(UNIT_IMRREG(line));
++ port->tx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_TX_HOLD));
++ port->rx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_RX_HOLD));
++ port->mode_1 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_1));
++ port->mode_2 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_2));
++ port->clk_sel = IOADDR(UNIT_CHANREG(line, R_DUART_CLK_SEL));
++ port->cmd = IOADDR(UNIT_CHANREG(line, R_DUART_CMD));
++ port->flags |= DUART_INITIALIZED;
++ }
++}
++
++/*
++ * Mask out the passed interrupt lines at the duart level. This should be
++ * called while holding the associated outp_lock.
++ */
++static inline void duart_mask_ints(unsigned int line, unsigned int mask)
++{
++ uart_state_t *port = uart_states + line;
++ u64 tmp = READ_SERCSR(port->imr, line);
++ WRITE_SERCSR(tmp & ~mask, port->imr, line);
++}
++
++
++/* Unmask the passed interrupt lines at the duart level */
++static inline void duart_unmask_ints(unsigned int line, unsigned int mask)
++{
++ uart_state_t *port = uart_states + line;
++ u64 tmp = READ_SERCSR(port->imr, line);
++ WRITE_SERCSR(tmp | mask, port->imr, line);
++}
++
++static inline void transmit_char_pio(uart_state_t *us)
++{
++ struct tty_struct *tty = us->tty;
++ int blocked = 0;
++
++ if (spin_trylock(&us->outp_lock)) {
++ for (;;) {
++ if (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_RDY))
++ break;
++ if (us->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
++ break;
++ } else {
++ WRITE_SERCSR(us->outp_buf[us->outp_head],
++ us->tx_hold, us->line);
++ us->outp_head = (us->outp_head + 1) & (SERIAL_XMIT_SIZE-1);
++ if (--us->outp_count <= 0)
++ break;
++ }
++ udelay(10);
++ }
++ spin_unlock(&us->outp_lock);
++ } else {
++ blocked = 1;
++ }
++
++ if (!us->outp_count || tty->stopped ||
++ tty->hw_stopped || blocked) {
++ us->flags &= ~TX_INTEN;
++ duart_mask_ints(us->line, M_DUART_IMR_TX);
++ }
++
++ if (us->open &&
++ (us->outp_count < (SERIAL_XMIT_SIZE/2))) {
++ /*
++ * We told the discipline at one point that we had no
++ * space, so it went to sleep. Wake it up when we hit
++ * half empty
++ */
++ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++ tty->ldisc.write_wakeup)
++ tty->ldisc.write_wakeup(tty);
++ wake_up_interruptible(&tty->write_wait);
++ }
++}
++
++/*
++ * Generic interrupt handler for both channels. dev_id is a pointer
++ * to the proper uart_states structure, so from that we can derive
++ * which port interrupted
++ */
++
++static irqreturn_t duart_int(int irq, void *dev_id, struct pt_regs *regs)
++{
++ uart_state_t *us = (uart_state_t *)dev_id;
++ struct tty_struct *tty = us->tty;
++ unsigned int status = READ_SERCSR(us->status, us->line);
++
++ pr_debug("DUART INT\n");
++
++ if (status & M_DUART_RX_RDY) {
++ int counter = 2048;
++ unsigned int ch;
++
++ if (status & M_DUART_OVRUN_ERR)
++ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
++ if (status & M_DUART_PARITY_ERR) {
++ printk("Parity error!\n");
++ } else if (status & M_DUART_FRM_ERR) {
++ printk("Frame error!\n");
++ }
++
++ while (counter > 0) {
++ if (!(READ_SERCSR(us->status, us->line) & M_DUART_RX_RDY))
++ break;
++ ch = READ_SERCSR(us->rx_hold, us->line);
++ if (tty->flip.count < TTY_FLIPBUF_SIZE) {
++ *tty->flip.char_buf_ptr++ = ch;
++ *tty->flip.flag_buf_ptr++ = 0;
++ tty->flip.count++;
++ }
++ udelay(1);
++ counter--;
++ }
++ tty_flip_buffer_push(tty);
++ }
++
++ if (status & M_DUART_TX_RDY) {
++ transmit_char_pio(us);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * Actual driver functions
++ */
++
++/* Return the number of characters we can accomodate in a write at this instant */
++static int duart_write_room(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ int retval;
++
++ retval = SERIAL_XMIT_SIZE - us->outp_count;
++
++ pr_debug("duart_write_room called, returning %i\n", retval);
++
++ return retval;
++}
++
++/* memcpy the data from src to destination, but take extra care if the
++ data is coming from user space */
++static inline int copy_buf(char *dest, const char *src, int size, int from_user)
++{
++ if (from_user) {
++ (void) copy_from_user(dest, src, size);
++ } else {
++ memcpy(dest, src, size);
++ }
++ return size;
++}
++
++/*
++ * Buffer up to count characters from buf to be written. If we don't have
++ * other characters buffered, enable the tx interrupt to start sending
++ */
++static int duart_write(struct tty_struct *tty, const unsigned char *buf,
++ int count)
++{
++ uart_state_t *us;
++ int c, t, total = 0;
++ unsigned long flags;
++
++ if (!tty) return 0;
++
++ us = tty->driver_data;
++ if (!us) return 0;
++
++ pr_debug("duart_write called for %i chars by %i (%s)\n", count, current->pid, current->comm);
++
++ spin_lock_irqsave(&us->outp_lock, flags);
++
++ for (;;) {
++ c = count;
++
++ t = SERIAL_XMIT_SIZE - us->outp_tail;
++ if (t < c) c = t;
++
++ t = SERIAL_XMIT_SIZE - 1 - us->outp_count;
++ if (t < c) c = t;
++
++ if (c <= 0) break;
++
++ memcpy(us->outp_buf + us->outp_tail, buf, c);
++
++ us->outp_count += c;
++ us->outp_tail = (us->outp_tail + c) & (SERIAL_XMIT_SIZE - 1);
++ buf += c;
++ count -= c;
++ total += c;
++ }
++
++ spin_unlock_irqrestore(&us->outp_lock, flags);
++
++ if (us->outp_count && !tty->stopped &&
++ !tty->hw_stopped && !(us->flags & TX_INTEN)) {
++ us->flags |= TX_INTEN;
++ duart_unmask_ints(us->line, M_DUART_IMR_TX);
++ }
++
++ return total;
++}
++
++
++/* Buffer one character to be written. If there's not room for it, just drop
++ it on the floor. This is used for echo, among other things */
++static void duart_put_char(struct tty_struct *tty, u_char ch)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ unsigned long flags;
++
++ pr_debug("duart_put_char called. Char is %x (%c)\n", (int)ch, ch);
++
++ spin_lock_irqsave(&us->outp_lock, flags);
++
++ if (us->outp_count == SERIAL_XMIT_SIZE) {
++ spin_unlock_irqrestore(&us->outp_lock, flags);
++ return;
++ }
++
++ us->outp_buf[us->outp_tail] = ch;
++ us->outp_tail = (us->outp_tail + 1) &(SERIAL_XMIT_SIZE-1);
++ us->outp_count++;
++
++ spin_unlock_irqrestore(&us->outp_lock, flags);
++}
++
++static void duart_flush_chars(struct tty_struct * tty)
++{
++ uart_state_t *port;
++
++ if (!tty) return;
++
++ port = tty->driver_data;
++
++ if (!port) return;
++
++ if (port->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
++ return;
++ }
++
++ port->flags |= TX_INTEN;
++ duart_unmask_ints(port->line, M_DUART_IMR_TX);
++}
++
++/* Return the number of characters in the output buffer that have yet to be
++ written */
++static int duart_chars_in_buffer(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ int retval;
++
++ retval = us->outp_count;
++
++ pr_debug("duart_chars_in_buffer returning %i\n", retval);
++
++ return retval;
++}
++
++/* Kill everything we haven't yet shoved into the FIFO. Turn off the
++ transmit interrupt since we've nothing more to transmit */
++static void duart_flush_buffer(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ unsigned long flags;
++
++ pr_debug("duart_flush_buffer called\n");
++ spin_lock_irqsave(&us->outp_lock, flags);
++ us->outp_head = us->outp_tail = us->outp_count = 0;
++ spin_unlock_irqrestore(&us->outp_lock, flags);
++
++ wake_up_interruptible(&us->tty->write_wait);
++ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++ tty->ldisc.write_wakeup)
++ tty->ldisc.write_wakeup(tty);
++}
++
++
++/* See sb1250 user manual for details on these registers */
++static inline void duart_set_cflag(unsigned int line, unsigned int cflag)
++{
++ unsigned int mode_reg1 = 0, mode_reg2 = 0;
++ unsigned int clk_divisor;
++ uart_state_t *port = uart_states + line;
++
++ switch (cflag & CSIZE) {
++ case CS7:
++ mode_reg1 |= V_DUART_BITS_PER_CHAR_7;
++
++ default:
++ /* We don't handle CS5 or CS6...is there a way we're supposed to flag this?
++ right now we just force them to CS8 */
++ mode_reg1 |= 0x0;
++ break;
++ }
++ if (cflag & CSTOPB) {
++ mode_reg2 |= M_DUART_STOP_BIT_LEN_2;
++ }
++ if (!(cflag & PARENB)) {
++ mode_reg1 |= V_DUART_PARITY_MODE_NONE;
++ }
++ if (cflag & PARODD) {
++ mode_reg1 |= M_DUART_PARITY_TYPE_ODD;
++ }
++
++ /* Formula for this is (5000000/baud)-1, but we saturate
++ at 12 bits, which means we can't actually do anything less
++ that 1200 baud */
++ switch (cflag & CBAUD) {
++ case B200:
++ case B300:
++ case B1200: clk_divisor = 4095; break;
++ case B1800: clk_divisor = 2776; break;
++ case B2400: clk_divisor = 2082; break;
++ case B4800: clk_divisor = 1040; break;
++ default:
++ case B9600: clk_divisor = 519; break;
++ case B19200: clk_divisor = 259; break;
++ case B38400: clk_divisor = 129; break;
++ case B57600: clk_divisor = 85; break;
++ case B115200: clk_divisor = 42; break;
++ }
++ WRITE_SERCSR(mode_reg1, port->mode_1, port->line);
++ WRITE_SERCSR(mode_reg2, port->mode_2, port->line);
++ WRITE_SERCSR(clk_divisor, port->clk_sel, port->line);
++ port->last_cflags = cflag;
++}
++
++
++/* Handle notification of a termios change. */
++static void duart_set_termios(struct tty_struct *tty, struct termios *old)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++ pr_debug("duart_set_termios called by %i (%s)\n", current->pid, current->comm);
++ if (old && tty->termios->c_cflag == old->c_cflag)
++ return;
++ duart_set_cflag(us->line, tty->termios->c_cflag);
++}
++
++static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) {
++
++ struct serial_struct tmp;
++
++ memset(&tmp, 0, sizeof(tmp));
++
++ tmp.type=PORT_SB1250;
++ tmp.line=us->line;
++ tmp.port=UNIT_CHANREG(tmp.line,0);
++ tmp.irq=UNIT_INT(tmp.line);
++ tmp.xmit_fifo_size=16; /* fixed by hw */
++ tmp.baud_base=5000000;
++ tmp.io_type=SERIAL_IO_MEM;
++
++ if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
++ return -EFAULT;
++
++ return 0;
++}
++
++static int duart_ioctl(struct tty_struct *tty, struct file * file,
++ unsigned int cmd, unsigned long arg)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++/* if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
++ return -ENODEV;*/
++ switch (cmd) {
++ case TIOCMGET:
++ printk("Ignoring TIOCMGET\n");
++ break;
++ case TIOCMBIS:
++ printk("Ignoring TIOCMBIS\n");
++ break;
++ case TIOCMBIC:
++ printk("Ignoring TIOCMBIC\n");
++ break;
++ case TIOCMSET:
++ printk("Ignoring TIOCMSET\n");
++ break;
++ case TIOCGSERIAL:
++ return get_serial_info(us,(struct serial_struct *) arg);
++ case TIOCSSERIAL:
++ printk("Ignoring TIOCSSERIAL\n");
++ break;
++ case TIOCSERCONFIG:
++ printk("Ignoring TIOCSERCONFIG\n");
++ break;
++ case TIOCSERGETLSR: /* Get line status register */
++ printk("Ignoring TIOCSERGETLSR\n");
++ break;
++ case TIOCSERGSTRUCT:
++ printk("Ignoring TIOCSERGSTRUCT\n");
++ break;
++ case TIOCMIWAIT:
++ printk("Ignoring TIOCMIWAIT\n");
++ break;
++ case TIOCGICOUNT:
++ printk("Ignoring TIOCGICOUNT\n");
++ break;
++ case TIOCSERGWILD:
++ printk("Ignoring TIOCSERGWILD\n");
++ break;
++ case TIOCSERSWILD:
++ printk("Ignoring TIOCSERSWILD\n");
++ break;
++ default:
++ break;
++ }
++// printk("Ignoring IOCTL %x from pid %i (%s)\n", cmd, current->pid, current->comm);
++ return -ENOIOCTLCMD;
++}
++
++/* XXXKW locking? */
++static void duart_start(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++ pr_debug("duart_start called\n");
++
++ if (us->outp_count && !(us->flags & TX_INTEN)) {
++ us->flags |= TX_INTEN;
++ duart_unmask_ints(us->line, M_DUART_IMR_TX);
++ }
++}
++
++/* XXXKW locking? */
++static void duart_stop(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++ pr_debug("duart_stop called\n");
++
++ if (us->outp_count && (us->flags & TX_INTEN)) {
++ us->flags &= ~TX_INTEN;
++ duart_mask_ints(us->line, M_DUART_IMR_TX);
++ }
++}
++
++/* Not sure on the semantics of this; are we supposed to wait until the stuff
++ already in the hardware FIFO drains, or are we supposed to wait until
++ we've drained the output buffer, too? I'm assuming the former, 'cause thats
++ what the other drivers seem to assume
++*/
++
++static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ unsigned long orig_jiffies;
++
++ orig_jiffies = jiffies;
++ pr_debug("duart_wait_until_sent(%d)+\n", timeout);
++ while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) {
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule_timeout(1);
++ if (signal_pending(current))
++ break;
++ if (timeout && time_after(jiffies, orig_jiffies + timeout))
++ break;
++ }
++ pr_debug("duart_wait_until_sent()-\n");
++}
++
++/*
++ * duart_hangup() --- called by tty_hangup() when a hangup is signaled.
++ */
++static void duart_hangup(struct tty_struct *tty)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++ duart_flush_buffer(tty);
++ us->open = 0;
++ us->tty = 0;
++}
++
++/*
++ * Open a tty line. Note that this can be called multiple times, so ->open can
++ * be >1. Only set up the tty struct if this is a "new" open, e.g. ->open was
++ * zero
++ */
++static int duart_open(struct tty_struct *tty, struct file *filp)
++{
++ uart_state_t *us;
++ unsigned int line = tty->index;
++ unsigned long flags;
++
++ if ((line >= tty->driver->num) || !sb1250_duart_present[line])
++ return -ENODEV;
++
++ pr_debug("duart_open called by %i (%s), tty is %p, rw is %p, ww is %p\n",
++ current->pid, current->comm, tty, tty->read_wait,
++ tty->write_wait);
++
++ us = uart_states + line;
++ tty->driver_data = us;
++
++ spin_lock_irqsave(&open_lock, flags);
++ if (!us->open) {
++ us->tty = tty;
++ us->tty->termios->c_cflag = us->last_cflags;
++ }
++ us->open++;
++ us->flags &= ~TX_INTEN;
++ duart_unmask_ints(line, M_DUART_IMR_RX);
++ spin_unlock_irqrestore(&open_lock, flags);
++
++ return 0;
++}
++
++
++/*
++ * Close a reference count out. If reference count hits zero, null the
++ * tty, kill the interrupts. The tty_io driver is responsible for making
++ * sure we've cleared out our internal buffers before calling close()
++ */
++static void duart_close(struct tty_struct *tty, struct file *filp)
++{
++ uart_state_t *us = (uart_state_t *) tty->driver_data;
++ unsigned long flags;
++
++ pr_debug("duart_close called by %i (%s)\n", current->pid, current->comm);
++
++ if (!us || !us->open)
++ return;
++
++ spin_lock_irqsave(&open_lock, flags);
++ if (tty_hung_up_p(filp)) {
++ spin_unlock_irqrestore(&open_lock, flags);
++ return;
++ }
++
++ if (--us->open < 0) {
++ us->open = 0;
++ printk(KERN_ERR "duart: bad open count: %d\n", us->open);
++ }
++ if (us->open) {
++ spin_unlock_irqrestore(&open_lock, flags);
++ return;
++ }
++
++ spin_unlock_irqrestore(&open_lock, flags);
++
++ tty->closing = 1;
++
++ /* Stop accepting input */
++ duart_mask_ints(us->line, M_DUART_IMR_RX);
++ /* Wait for FIFO to drain */
++ while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT))
++ ;
++
++ if (tty->driver->flush_buffer)
++ tty->driver->flush_buffer(tty);
++ if (tty->ldisc.flush_buffer)
++ tty->ldisc.flush_buffer(tty);
++ tty->closing = 0;
++}
++
++
++static struct tty_operations duart_ops = {
++ .open = duart_open,
++ .close = duart_close,
++ .write = duart_write,
++ .put_char = duart_put_char,
++ .flush_chars = duart_flush_chars,
++ .write_room = duart_write_room,
++ .chars_in_buffer = duart_chars_in_buffer,
++ .flush_buffer = duart_flush_buffer,
++ .ioctl = duart_ioctl,
++// .throttle = duart_throttle,
++// .unthrottle = duart_unthrottle,
++ .set_termios = duart_set_termios,
++ .stop = duart_stop,
++ .start = duart_start,
++ .hangup = duart_hangup,
++ .wait_until_sent = duart_wait_until_sent,
++};
++
++/* Initialize the sb1250_duart_present array based on SOC type. */
++static void __init sb1250_duart_init_present_lines(void)
++{
++ int i, max_lines;
++
++ /* Set the number of available units based on the SOC type. */
++ switch (soc_type) {
++ case K_SYS_SOC_TYPE_BCM1x55:
++ case K_SYS_SOC_TYPE_BCM1x80:
++ max_lines = 4;
++ break;
++ default:
++ /* Assume at least two serial ports at the normal address. */
++ max_lines = 2;
++ break;
++ }
++ if (max_lines > DUART_MAX_LINE)
++ max_lines = DUART_MAX_LINE;
++
++ for (i = 0; i < max_lines; i++)
++ sb1250_duart_present[i] = 1;
++}
++
++/* Set up the driver and register it, register the UART interrupts. This
++ is called from tty_init, or as a part of the module init */
++static int __init sb1250_duart_init(void)
++{
++ int i;
++
++ sb1250_duart_init_present_lines();
++
++ sb1250_duart_driver = alloc_tty_driver(DUART_MAX_LINE);
++ if (!sb1250_duart_driver)
++ return -ENOMEM;
++
++ sb1250_duart_driver->owner = THIS_MODULE;
++ sb1250_duart_driver->name = "duart";
++ sb1250_duart_driver->devfs_name = "duart/";
++ sb1250_duart_driver->major = TTY_MAJOR;
++ sb1250_duart_driver->minor_start = SB1250_DUART_MINOR_BASE;
++ sb1250_duart_driver->type = TTY_DRIVER_TYPE_SERIAL;
++ sb1250_duart_driver->subtype = SERIAL_TYPE_NORMAL;
++ sb1250_duart_driver->init_termios = tty_std_termios;
++ sb1250_duart_driver->flags = TTY_DRIVER_REAL_RAW;
++ tty_set_operations(sb1250_duart_driver, &duart_ops);
++
++ for (i=0; i<DUART_MAX_LINE; i++) {
++ uart_state_t *port = uart_states + i;
++
++ if (!sb1250_duart_present[i])
++ continue;
++
++ init_duart_port(port, i);
++ spin_lock_init(&port->outp_lock);
++ duart_mask_ints(i, M_DUART_IMR_ALL);
++ if (request_irq(UNIT_INT(i), duart_int, 0, "uart", port)) {
++ panic("Couldn't get uart0 interrupt line");
++ }
++ __raw_writeq(M_DUART_RX_EN|M_DUART_TX_EN,
++ IOADDR(UNIT_CHANREG(i, R_DUART_CMD)));
++ duart_set_cflag(i, DEFAULT_CFLAGS);
++ }
++
++ /* Interrupts are now active, our ISR can be called. */
++
++ if (tty_register_driver(sb1250_duart_driver)) {
++ printk(KERN_ERR "Couldn't register sb1250 duart serial driver\n");
++ put_tty_driver(sb1250_duart_driver);
++ return 1;
++ }
++ return 0;
++}
++
++/* Unload the driver. Unregister stuff, get ready to go away */
++static void __exit sb1250_duart_fini(void)
++{
++ unsigned long flags;
++ int i;
++
++ local_irq_save(flags);
++ tty_unregister_driver(sb1250_duart_driver);
++ put_tty_driver(sb1250_duart_driver);
++
++ for (i=0; i<DUART_MAX_LINE; i++) {
++ if (!sb1250_duart_present[i])
++ continue;
++ free_irq(UNIT_INT(i), &uart_states[i]);
++ disable_irq(UNIT_INT(i));
++ }
++ local_irq_restore(flags);
++}
++
++module_init(sb1250_duart_init);
++module_exit(sb1250_duart_fini);
++MODULE_DESCRIPTION("SB1250 Duart serial driver");
++MODULE_AUTHOR("Broadcom Corp.");
++
++#ifdef CONFIG_SIBYTE_SB1250_DUART_CONSOLE
++
++/*
++ * Serial console stuff. Very basic, polling driver for doing serial
++ * console output. The console_sem is held by the caller, so we
++ * shouldn't be interrupted for more console activity.
++ * XXXKW What about getting interrupted by uart driver activity?
++ */
++
++void serial_outc(unsigned char c, int line)
++{
++ uart_state_t *port = uart_states + line;
++ while (!(READ_SERCSR(port->status, line) & M_DUART_TX_RDY)) ;
++ WRITE_SERCSR(c, port->tx_hold, line);
++ while (!(READ_SERCSR(port->status, port->line) & M_DUART_TX_EMT)) ;
++}
++
++static void ser_console_write(struct console *cons, const char *s,
++ unsigned int count)
++{
++ int line = cons->index;
++ uart_state_t *port = uart_states + line;
++ u32 imr;
++
++ imr = READ_SERCSR(port->imr, line);
++ WRITE_SERCSR(0, port->imr, line);
++ while (count--) {
++ if (*s == '\n')
++ serial_outc('\r', line);
++ serial_outc(*s++, line);
++ }
++ WRITE_SERCSR(imr, port->imr, line);
++}
++
++static struct tty_driver *ser_console_device(struct console *c, int *index)
++{
++ *index = c->index;
++ return sb1250_duart_driver;
++}
++
++static int ser_console_setup(struct console *cons, char *str)
++{
++ int i;
++
++ sb1250_duart_init_present_lines();
++
++ for (i=0; i<DUART_MAX_LINE; i++) {
++ uart_state_t *port = uart_states + i;
++
++ if (!sb1250_duart_present[i])
++ continue;
++
++ init_duart_port(port, i);
++#if SIBYTE_1956_WAR
++ last_mode1[i] = V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8;
++#endif
++ WRITE_SERCSR(V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8,
++ port->mode_1, i);
++ WRITE_SERCSR(M_DUART_STOP_BIT_LEN_1,
++ port->mode_2, i);
++ WRITE_SERCSR(V_DUART_BAUD_RATE(115200),
++ port->clk_sel, i);
++ WRITE_SERCSR(M_DUART_RX_EN|M_DUART_TX_EN,
++ port->cmd, i);
++ }
++ return 0;
++}
++
++static struct console sb1250_ser_cons = {
++ .name = "duart",
++ .write = ser_console_write,
++ .device = ser_console_device,
++ .setup = ser_console_setup,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++};
++
++static int __init sb1250_serial_console_init(void)
++{
++ register_console(&sb1250_ser_cons);
++ return 0;
++}
++
++console_initcall(sb1250_serial_console_init);
++
++#endif /* CONFIG_SIBYTE_SB1250_DUART_CONSOLE */
+diff -urN --ignore-space-change kernel.org/drivers/ide/mips/Makefile linux-mips/drivers/ide/mips/Makefile
+--- kernel.org/drivers/ide/mips/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/ide/mips/Makefile 2006-01-10 11:21:34.000000000 +0000
+@@ -1,4 +1,4 @@
+ obj-$(CONFIG_BLK_DEV_IDE_SWARM) += swarm.o
+ obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o
+
+-EXTRA_CFLAGS := -Idrivers/ide
++CFLAGS_au1xxx-ide.o := -Idrivers/ide
+diff -urN --ignore-space-change kernel.org/drivers/media/video/Makefile linux-mips/drivers/media/video/Makefile
+--- kernel.org/drivers/media/video/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/media/video/Makefile 2006-01-10 11:21:36.000000000 +0000
+@@ -54,6 +54,8 @@
+ obj-$(CONFIG_VIDEO_BTCX) += btcx-risc.o
+ obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
+
++obj-$(CONFIG_TUNER_3036) += tuner-3036.o
++
+ obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o
+
+ obj-$(CONFIG_VIDEO_DECODER) += saa7115.o cx25840/ saa7127.o
+diff -urN --ignore-space-change kernel.org/drivers/mmc/au1xmmc.c linux-mips/drivers/mmc/au1xmmc.c
+--- kernel.org/drivers/mmc/au1xmmc.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/mmc/au1xmmc.c 2006-01-10 11:21:37.000000000 +0000
+@@ -37,7 +37,7 @@
+ #include <linux/config.h>
+ #include <linux/module.h>
+ #include <linux/init.h>
+-#include <linux/device.h>
++#include <linux/platform_device.h>
+ #include <linux/mm.h>
+ #include <linux/interrupt.h>
+ #include <linux/dma-mapping.h>
+@@ -739,7 +739,6 @@
+ static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs)
+ {
+ struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
+- u32 status;
+
+ /* Avoid spurious interrupts */
+
+@@ -837,11 +836,6 @@
+ mmc_detect_change(host->mmc, 0);
+ }
+
+- if (host->mrq != NULL) {
+- u32 status = au_readl(HOST_STATUS(host));
+- DEBUG("PENDING - %8.8x\n", host->id, status);
- }
-
-- uart_unregister_driver(&siu_uart_driver);
--
-- return 0;
--}
--
--static int siu_suspend(struct device *dev, pm_message_t state, u32 level)
--{
-- struct uart_port *port;
-- int i;
--
-- if (level != SUSPEND_DISABLE)
-- return 0;
--
-- for (i = 0; i < siu_uart_driver.nr; i++) {
-- port = &siu_uart_ports[i];
-- if ((port->type == PORT_VR41XX_SIU ||
-- port->type == PORT_VR41XX_DSIU) && port->dev == dev)
-- uart_suspend_port(&siu_uart_driver, port);
--
-- }
+ mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
+ }
+
+diff -urN --ignore-space-change kernel.org/drivers/mtd/devices/Kconfig linux-mips/drivers/mtd/devices/Kconfig
+--- kernel.org/drivers/mtd/devices/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/mtd/devices/Kconfig 2006-01-10 11:21:37.000000000 +0000
+@@ -47,6 +47,11 @@
+ accelerator. Say Y here if you have a DECstation 5000/2x0 or a
+ DECsystem 5900 equipped with such a module.
+
++ If you want to compile this driver as a module ( = code which can be
++ inserted in and removed from the running kernel whenever you want),
++ say M here and read <file:Documentation/modules.txt>. The module will
++ be called ms02-nv.o.
++
+ config MTD_SLRAM
+ tristate "Uncached system RAM"
+ depends on MTD
+diff -urN --ignore-space-change kernel.org/drivers/mtd/devices/docprobe.c linux-mips/drivers/mtd/devices/docprobe.c
+--- kernel.org/drivers/mtd/devices/docprobe.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/mtd/devices/docprobe.c 2006-01-10 11:21:37.000000000 +0000
+@@ -87,7 +87,7 @@
+ 0xff000000,
+ #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
+ 0xff000000,
+-##else
++#else
+ #warning Unknown architecture for DiskOnChip. No default probe locations defined
+ #endif
+ 0xffffffff };
+diff -urN --ignore-space-change kernel.org/drivers/mtd/maps/Kconfig linux-mips/drivers/mtd/maps/Kconfig
+--- kernel.org/drivers/mtd/maps/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/mtd/maps/Kconfig 2006-01-10 11:21:37.000000000 +0000
+@@ -200,8 +200,8 @@
+ Support for the flash chip on Tsunami TIG bus.
+
+ config MTD_LASAT
+- tristate "Flash chips on LASAT board"
+- depends on LASAT
++ tristate "LASAT flash device"
++ depends on LASAT && MTD_CFI
+ help
+ Support for the flash chips on the Lasat 100 and 200 boards.
+
+@@ -299,6 +299,18 @@
+ Mapping for the Flaga digital module. If you don't have one, ignore
+ this setting.
+
++config MTD_XXS1500
++ tristate "MyCable XXS1500 Flash device"
++ depends on MIPS && MIPS_XXS1500
++ help
++ Flash memory access on MyCable XXS1500 Board
++
++config MTD_MTX1
++ tristate "4-G Systems MTX-1 Flash device"
++ depends on MIPS && MIPS_MTX1
++ help
++ Flash memory access on 4-G Systems MTX-1 Board
++
+ config MTD_BEECH
+ tristate "CFI Flash device mapped on IBM 405LP Beech"
+ depends on MTD_CFI && BEECH
+diff -urN --ignore-space-change kernel.org/drivers/mtd/maps/lasat.c linux-mips/drivers/mtd/maps/lasat.c
+--- kernel.org/drivers/mtd/maps/lasat.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/mtd/maps/lasat.c 2006-01-10 11:21:37.000000000 +0000
+@@ -7,7 +7,7 @@
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+- * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $
++ * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $
+ *
+ */
+
+@@ -50,7 +50,7 @@
+ ENABLE_VPP((&lasat_map));
+
+ lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER);
+- lasat_map.virt = ioremap_nocache(
++ lasat_map.virt = (unsigned long)ioremap_nocache(
+ lasat_map.phys, lasat_board_info.li_flash_size);
+ lasat_map.size = lasat_board_info.li_flash_size;
+
+diff -urN --ignore-space-change kernel.org/drivers/net/Kconfig linux-mips/drivers/net/Kconfig
+--- kernel.org/drivers/net/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/Kconfig 2006-01-10 11:21:37.000000000 +0000
+@@ -427,6 +427,14 @@
+ This is the driver for the onboard card of MIPS Magnum 4000,
+ Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
+
++config GALILEO_64240_ETH
++ tristate "Galileo GT64240 Ethernet support"
++ depends on NET_ETHERNET && MOMENCO_OCELOT_G
++ select MII
++ help
++ This is the driver for the ethernet interfaces integrated into
++ the Galileo (now Marvell) GT64240 chipset.
++
+ config MIPS_GT96100ETH
+ bool "MIPS GT96100 Ethernet support"
+ depends on NET_ETHERNET && MIPS_GT96100
+@@ -441,10 +449,6 @@
+ If you have an Alchemy Semi AU1X00 based system
+ say Y. Otherwise, say N.
+
+-config NET_SB1250_MAC
+- tristate "SB1250 Ethernet support"
+- depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC
-
-- return 0;
--}
+ config SGI_IOC3_ETH
+ bool "SGI IOC3 Ethernet"
+ depends on NET_ETHERNET && PCI && SGI_IP27
+@@ -483,6 +487,14 @@
+ emulated by the MIPS Simulator.
+ If you are not using a MIPSsim or are unsure, say N.
+
++config MIPS_SIM_NET
++ tristate "MIPS simulator Network device (EXPERIMENTAL)"
++ depends on NETDEVICES && MIPS_SIM && EXPERIMENTAL
++ help
++ The MIPSNET device is a simple Ethernet network device which is
++ emulated by the MIPS Simulator.
++ If you are not using a MIPSsim or are unsure, say N.
++
+ config SGI_O2MACE_ETH
+ tristate "SGI O2 MACE Fast Ethernet support"
+ depends on NET_ETHERNET && SGI_IP32=y
+@@ -1974,6 +1986,10 @@
+
+ If in doubt, say N.
+
++config NET_SB1250_MAC
++ tristate "SB1250 Ethernet support"
++ depends on SIBYTE_SB1xxx_SOC
++
+ config R8169_VLAN
+ bool "VLAN support"
+ depends on R8169 && VLAN_8021Q
+@@ -2142,8 +2158,8 @@
+ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM
+ help
+ This driver supports the gigabit Ethernet on the Marvell MV643XX
+- chipset which is used in the Momenco Ocelot C and Jaguar ATX and
+- Pegasos II, amongst other PPC and MIPS boards.
++ chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX
++ and Pegasos II, amongst other PPC and MIPS boards.
+
+ config MV643XX_ETH_0
+ bool "MV-643XX Port 0"
+@@ -2166,6 +2182,20 @@
+ This enables support for Port 2 of the Marvell MV643XX Gigabit
+ Ethernet.
+
++config BIG_SUR_FE
++ bool "PMC-Sierra TITAN Fast Ethernet Support"
++ depends on NET_ETHERNET && PMC_BIG_SUR
++ help
++ This enables support for the the integrated ethernet of
++ PMC-Sierra's Big Sur SoC.
++
++config TITAN_GE
++ bool "PMC-Sierra TITAN Gigabit Ethernet Support"
++ depends on PMC_YOSEMITE
++ help
++ This enables support for the the integrated ethernet of
++ PMC-Sierra's Titan SoC.
++
+ endmenu
+
+ #
+diff -urN --ignore-space-change kernel.org/drivers/net/Makefile linux-mips/drivers/net/Makefile
+--- kernel.org/drivers/net/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/Makefile 2006-01-10 11:30:59.000000000 +0000
+@@ -107,6 +107,11 @@
+
+ obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
+
++obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o
++obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o
++obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o
++obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
++
+ obj-$(CONFIG_PPP) += ppp_generic.o slhc.o
+ obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
+ obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
+diff -urN --ignore-space-change kernel.org/drivers/net/big_sur_ge.c linux-mips/drivers/net/big_sur_ge.c
+--- kernel.org/drivers/net/big_sur_ge.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/big_sur_ge.c 2006-01-10 11:21:37.000000000 +0000
+@@ -0,0 +1,2005 @@
++/*
++ * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
++ * Copyright (C) 2003 Ralf Baechle (ralf at linux-mips.org)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ */
++
++/*************************************************************************
++ * Description :
++ *
++ * The driver has three modes of operation: FIFO non-DMA, Simple DMA
++ * and SG DMA. There is also a Polled mode and an Interrupt mode of
++ * operation. SG DMA should do zerocopy and check offload. Probably,
++ * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy
++ * case on the Tx and the Rx.
++ *
++ * We turn on Simple DMA and interrupt mode. Although, support has been
++ * added for the SG mode also but not for the polled mode. This is a
++ * Fast Ethernet driver although there will be support for Gigabit soon.
++ *
++ * The driver is divided into two parts: Hardware dependent and a
++ * Hardware independent. There is currently no support for checksum offload
++ * zerocopy and Rx NAPI. There is support for Interrupt Mitigation.
++ ****************************************************************************/
++
++/*************************************************************
++ * Hardware Indepenent Part of the driver
++ *************************************************************/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mii.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include "big_sur_ge.h"
++
++#define TX_TIMEOUT (60*HZ) /* Transmission timeout is 60 seconds. */
++
++static struct net_device *dev_list = NULL;
++static DEFINE_SPINLOCK(dev_lock);
++
++typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
++
++/* Big Sur Ethernet MAC structure */
++struct big_sur_ge_enet {
++ struct net_device_stats stats; /* Statistics for this device */
++ struct net_device *next_dev; /* The next device in dev_list */
++ struct timer_list phy_timer; /* PHY monitoring timer */
++ u32 index; /* Which interface is this */
++ u32 save_base_address; /* Saved physical base address */
++ struct sk_buff *saved_skb; /* skb being transmitted */
++ spinlock_t lock; /* For atomic access to saved_skb */
++ u8 mii_addr; /* The MII address of the PHY */
++ big_sur_ge emac; /* GE driver structure */
++};
++
++/* Manish : For testing purposes only */
++static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55";
++
++/*********************************************************************
++ * Function Prototypes (whole bunch of them)
++ *********************************************************************/
++unsigned long big_sur_ge_dma_control(xdma_channel *);
++void big_sur_ge_dma_reset(xdma_channel *);
++static void handle_fifo_intr(big_sur_ge *);
++void big_sur_ge_check_fifo_recv_error(big_sur_ge *);
++void big_sur_ge_check_fifo_send_error(big_sur_ge *);
++static int big_sur_ge_config_fifo(big_sur_ge *);
++big_sur_ge_config *big_sur_ge_lookup_config(unsigned int);
++static int big_sur_ge_config_dma(big_sur_ge *);
++void big_sur_ge_enet_reset(big_sur_ge *);
++void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
++
++/*********************************************************************
++ * DMA Channel Initialization
++ **********************************************************************/
++static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address)
++{
++ dma->reg_base_address = base_address;
++ dma->get_ptr = NULL;
++ dma->put_ptr = NULL;
++ dma->commit_ptr = NULL;
++ dma->last_ptr = NULL;
++ dma->total_desc_count = (unsigned long) NULL;
++ dma->active_desc_count = (unsigned long) NULL;
++ dma->ready = 1; /* DMA channel is ready */
++
++ big_sur_ge_dma_reset(dma);
++
++ return 0;
++}
++
++/*********************************************************************
++ * Is the DMA channel ready yet ?
++ **********************************************************************/
++static int big_sur_ge_dma_ready(xdma_channel * dma)
++{
++ return dma->ready == 1;
++}
++
++/*********************************************************************
++ * Perform the self test on the DMA channel
++ **********************************************************************/
++#define BIG_SUR_GE_CONTROL_REG_RESET_MASK 0x98000000
++
++static int big_sur_ge_dma_self_test(xdma_channel * dma)
++{
++ unsigned long reg_data;
++
++ big_sur_ge_dma_reset(dma);
++
++ reg_data = big_sur_ge_dma_control(dma);
++ if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
++ printk(KERN_ERR "DMA Channel Self Test Failed \n");
++ return -1;
++ }
++
++ return 0;
++}
++
++/*********************************************************************
++ * Reset the DMA channel
++ **********************************************************************/
++static void big_sur_ge_dma_reset(xdma_channel * dma)
++{
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
++ BIG_SUR_GE_RESET_MASK);
++}
++
++/*********************************************************************
++ * Get control of the DMA channel
++ **********************************************************************/
++static unsigned long big_sur_ge_dma_control(xdma_channel * dma)
++{
++ return BIG_SUR_GE_READ(dma->reg_base_address +
++ BIG_SUR_GE_DMAC_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set control of the DMA channel
++ **********************************************************************/
++static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control)
++{
++ BIG_SUR_GE_WRITE(dma->reg_base_address +
++ BIG_SUR_GE_DMAC_REG_OFFSET, control);
++}
++
++/*********************************************************************
++ * Get the status of the DMA channel
++ *********************************************************************/
++static unsigned long big_sur_ge_dma_status(xdma_channel * dma)
++{
++ return BIG_SUR_GE_READ(dma->reg_base_address +
++ BIG_SUR_GE_DMAS_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set the interrupt status of the DMA channel
++ *********************************************************************/
++static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status)
++{
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET,
++ status);
++}
++
++/*********************************************************************
++ * Get the interrupt status of the DMA channel
++ *********************************************************************/
++static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma)
++{
++ return BIG_SUR_GE_READ(dma->reg_base_address +
++ BIG_SUR_GE_IS_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set the Interrupt Enable
++ *********************************************************************/
++static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable)
++{
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET,
++ enable);
++}
++
++/*********************************************************************
++ * Get the Interrupt Enable field to make a check
++ *********************************************************************/
++static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma)
++{
++ return BIG_SUR_GE_READ(dma->reg_base_address +
++ BIG_SUR_GE_IE_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Transfer the data over the DMA channel
++ *********************************************************************/
++static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source,
++ unsigned long *dest, unsigned long length)
++{
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
++ (unsigned long) source);
++
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
++ (unsigned long) dest);
++
++ BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
++ length);
++}
++
++/*********************************************************************
++ * Get the DMA descriptor
++ *********************************************************************/
++static int big_sur_ge_get_descriptor(xdma_channel * dma,
++ xbuf_descriptor ** buffer_desc)
++{
++ unsigned long reg_data;
++
++ reg_data = xbuf_descriptor_GetControl(dma->get_ptr);
++ xbuf_descriptor_SetControl(dma->get_ptr, reg_data |
++ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++ *buffer_desc = dma->get_ptr;
++
++ dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr);
++ dma->active_desc_count--;
++
++ return 0;
++}
++
++/*********************************************************************
++ * Get the packet count
++ *********************************************************************/
++static int big_sur_ge_get_packet_count(xdma_channel * dma)
++{
++ return (BIG_SUR_GE_READ
++ (dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET));
++}
++
++/*********************************************************************
++ * Descrement the packet count
++ *********************************************************************/
++static void big_sur_ge_decr_packet_count(xdma_channel * dma)
++{
++ unsigned long reg_data;
++
++ reg_data =
++ BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET);
++ if (reg_data > 0)
++ BIG_SUR_GE_WRITE(dma->base_address +
++ BIG_SUR_GE_UPC_REG_OFFSET, 1);
++}
++
++/****************************************************************************
++ * Start of the code that deals with the Packet Fifo
++ *****************************************************************************/
++
++/****************************************************************************
++ * Init the packet fifo
++ ****************************************************************************/
++static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data)
++{
++ fifo->reg_base_addr = reg;
++ fifo->data_base_address = data;
++ fifo->ready_status = 1;
++
++ BIG_SUR_GE_FIFO_RESET(fifo);
++
++ return 0;
++}
++
++/****************************************************************************
++ * Packet fifo self test
++ ****************************************************************************/
++static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type)
++{
++ unsigned long reg_data;
++
++ BIG_SUR_GE_FIFO_RESET(fifo);
++ reg_data =
++ BIG_SUR_GE_READ(fifo->reg_base_addr +
++ BIG_SUR_GE_COUNT_STATUS_REG_OFFSET);
++
++ if (type == BIG_SUR_GE_READ_FIFO_TYPE) {
++ if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) {
++ printk(KERN_ERR "Read FIFO not empty \n");
++ return -1;
++ }
++ } else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) {
++ printk(KERN_ERR "Write FIFO is full \n");
++ return -1;
++ }
++
++ return 0;
++}
++
++/****************************************************************************
++ * Packet FIFO read
++ ****************************************************************************/
++static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
++{
++ unsigned long fifo_count, word_count, extra_byte;
++ unsigned long *buffer_data = (unsigned long *) buffer;
++
++ fifo_count =
++ BIG_SUR_GE_READ(fifo->reg_base_addr +
++ BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
++ fifo_count &= BIG_SUR_GE_COUNT_MASK;
++
++ if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
++ return -1;
++
++ word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++ extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++
++ for (fifo_count = 0; fifo_count < word_count; fifo_count++)
++ buffer_data[fifo_count] =
++ BIG_SUR_GE_READ(fifo->reg_base_addr);
++
++ if (extra_byte > 0) {
++ unsigned long last_word;
++ int *extra_buffer_data =
++ (int *) (buffer_data + word_count);
++
++ last_word = BIG_SUR_GE_READ(fifo->data_base_address);
++ if (extra_byte == 1)
++ extra_buffer_data[0] = (int) (last_word << 24);
++ else if (extra_byte == 2) {
++ extra_buffer_data[0] = (int) (last_word << 24);
++ extra_buffer_data[1] = (int) (last_word << 16);
++ } else if (extra_byte == 3) {
++ extra_buffer_data[0] = (int) (last_word << 24);
++ extra_buffer_data[1] = (int) (last_word << 16);
++ extra_buffer_data[2] = (int) (last_word << 8);
++ }
++ }
++
++ return 0;
++}
++
++/*****************************************************************************
++ * Write the data into the packet fifo
++ *****************************************************************************/
++static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
++{
++ unsigned long fifo_count, word_count, extra_byte;
++ unsigned long *buffer_data = (unsigned long *) buffer;
++
++ fifo_count =
++ BIG_SUR_GE_READ(fifo->reg_base_addr +
++ BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
++ fifo_count &= BIG_SUR_GE_COUNT_MASK;
++
++ word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++ extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++
++ /* You should see what the ppc driver does here. It just slobbers */
++ if (extra_byte > 0)
++ if (fifo_count > (word_count + 1)) {
++ printk(KERN_ERR
++ "No room in the packet send fifo \n");
++ return -1;
++ }
++
++ for (fifo_count = 0; fifo_count < word_count; fifo_count++)
++ BIG_SUR_GE_WRITE(fifo->data_base_address,
++ buffer_data[fifo_count]);
++
++
++ if (extra_byte > 0) {
++ unsigned long last_word = 0;
++ int *extra_buffer_data =
++ (int *) (buffer_data + word_count);
++
++ if (extra_byte == 1)
++ last_word = extra_buffer_data[0] << 24;
++ else if (extra_byte == 2)
++ last_word = (extra_buffer_data[0] << 24 |
++ extra_buffer_data[1] << 16);
++
++ else if (extra_byte == 3)
++ last_word = (extra_buffer_data[0] << 24 |
++ extra_buffer_data[1] << 16 |
++ extra_buffer_data[2] << 8);
++
++
++ BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
++ }
++
++ return 0;
++}
++
++
++/*****************************************************************************
++ * Interrupt handlers: We handle any errors associated with the FIFO.
++ * FIFO is for simple dma case and we do want to handle the simple DMA
++ * case. We dont handle the Scatter Gather DMA for now since it is not working.
++ ******************************************************************************/
++
++/*********************************************************************************
++ * FIFO send for Simple DMA with Interrupts
++ **********************************************************************************/
++static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer,
++ unsigned long byte_cnt)
++{
++ unsigned long int_status, reg_data;
++
++ /* Silly checks here that we really dont need */
++ if (!emac->started)
++ return -1;
++
++ if (emac->polled)
++ return -1;
++
++ if (emac->dma_sg)
++ return -1;
++
++ int_status =
++ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++ if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
++ printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
++ return -1;
++ }
++
++ /*
++ * Write the data to the FIFO in the hardware
++ */
++ if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) *
++ sizeof(unsigned long)) < byte_cnt) {
++ printk(KERN_ERR "Send FIFO on chip is full \n");
++ return -1;
++ }
++
++ if (big_sur_ge_dma_status(&emac->send_channel) &
++ BIG_SUR_GE_DMASR_BUSY_MASK) {
++ printk(KERN_ERR "Send channel FIFO engine busy \n");
++ return -1;
++ }
++
++ big_sur_ge_set_dma_control(&emac->send_channel,
++ BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
++ BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
++ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++ big_sur_ge_dma_transfer(&emac->send_channel,
++ (unsigned long *) buffer,
++ (unsigned long *) (emac->base_address +
++ BIG_SUR_GE_PFIFO_TXDATA_OFFSET),
++ byte_cnt);
++
++ reg_data = big_sur_ge_dma_status(&emac->send_channel);
++ while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
++ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++ if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
++ break;
++ }
++
++ if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
++ (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
++ printk(KERN_ERR "Send side DMA error \n");
++ return -1;
++ }
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET,
++ byte_cnt);
++
++ return 0;
++}
++
++/*************************************************************************
++ * FIFO receive for Simple DMA case
++ *************************************************************************/
++static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer,
++ unsigned long *byte_cnt)
++{
++ unsigned long int_status, reg_data;
++
++ /* Silly checks here that we really dont need */
++ if (!emac->started)
++ return -1;
++
++ if (emac->polled)
++ return -1;
++
++ if (emac->dma_sg)
++ return -1;
++
++ if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
++ return -1;
++
++ int_status =
++ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++ if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_IISR_OFFSET,
++ BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
++ return -1;
++ }
++
++ if (big_sur_ge_dma_status(&emac->recv_channel) &
++ BIG_SUR_GE_DMASR_BUSY_MASK) {
++ printk(KERN_ERR "Rx side DMA Engine busy \n");
++ return -1;
++ }
++
++ if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) ==
++ 0) {
++ printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
++ return -1;
++ }
++
++ /* For the simple DMA case only */
++ big_sur_ge_set_dma_control(&emac->recv_channel,
++ BIG_SUR_GE_DMACR_DEST_INCR_MASK |
++ BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
++ BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++ if (packet_fifo_read(&emac->recv_fifo, buffer,
++ BIG_SUR_GE_READ(emac->base_address +
++ BIG_SUR_GE_RPLR_OFFSET)) ==
++ -1) {
++ printk(KERN_ERR "Not enough space in the FIFO \n");
++ return -1;
++ }
++
++ big_sur_ge_dma_transfer(&emac->recv_channel,
++ (unsigned long *) (emac->base_address +
++ BIG_SUR_GE_PFIFO_RXDATA_OFFSET),
++ (unsigned long *)
++ buffer,
++ BIG_SUR_GE_READ(emac->base_address +
++ BIG_SUR_GE_RPLR_OFFSET));
++
++ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++ while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
++ reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++ if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
++ break;
++ }
++
++ if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
++ (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
++ printk(KERN_ERR "DMA Bus Error \n");
++ return -1;
++ }
++
++ *byte_cnt =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
++
++ return 0;
++}
++
++static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct net_device *netdev = dev_id;
++ struct big_sur_ge_enet *lp = netdev->priv;
++ big_sur_ge *emac = (big_sur_ge *)emac_ptr;
++ void *emac_ptr = &lp->emac;
++ unsigned long int_status;
++
++ int_status =
++ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET);
++ if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
++ handle_fifo_intr(emac);
++
++ if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++ big_sur_ge_check_fifo_recv_error(emac);
++
++ if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
++ big_sur_ge_check_fifo_send_error(emac);
++
++ if (int_status & XIIF_V123B_ERROR_MASK)
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_DISR_OFFSET,
++ XIIF_V123B_ERROR_MASK);
++
++ return IRQ_HANDLED;
++}
++
++/****************************************************************************
++ * Set the FIFO send handler
++ ***************************************************************************/
++static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back,
++ big_sur_fifo_handler function)
++{
++ emac->big_sur_ge_fifo_send_handler = function;
++ emac->fifo_send_ref = call_back;
++}
++
++/****************************************************************************
++ * Set the FIFO recv handler
++ ***************************************************************************/
++static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back,
++ big_sur_fifo_handler function)
++{
++ emac->big_sur_ge_fifo_recv_handler = function;
++ emac->fifo_recv_ref = call_back;
++}
++
++/****************************************************************************
++ * Main Fifo intr handler
++ ***************************************************************************/
++static void handle_fifo_intr(big_sur_ge * emac)
++{
++ unsigned long int_status;
++
++ /* Ack the interrupts asap */
++ int_status =
++ BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
++ int_status);
++
++ /* Process the Rx side */
++ if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
++ emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref);
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_IISR_OFFSET,
++ BIG_SUR_GE_EIR_RECV_DONE_MASK);
++ }
++
++ if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
++ /* We dont collect stats and hence we dont need to get status */
++
++ emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref);
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_IISR_OFFSET,
++ BIG_SUR_GE_EIR_XMIT_DONE_MASK);
++ }
++
++ big_sur_ge_check_mac_error(emac, int_status);
++}
++
++/******************************************************************
++ * Handle the Receive side DMA interrupts. The PPC driver has
++ * callbacks all over the place. This has been eliminated here by
++ * using the following approach:
++ *
++ * The ISR is set to the main interrrupt handler. This will handle
++ * all the interrupts including the ones for DMA. In this main isr,
++ * we determine if we need to call recv or send side intr functions.
++ * Pretty complex but thats the way it is now.
++ *******************************************************************/
++static void big_sur_ge_handle_recv_intr(big_sur_ge * emac)
++{
++ unsigned long int_status;
++
++ int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
++ if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
++ BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
++ u32 num_packets;
++ u32 num_processed;
++ u32 num_buffers;
++ u32 num_bytes;
++ xbuf_descriptor *first_desc_ptr = NULL;
++ xbuf_descriptor *buffer_desc;
++ int is_last = 0;
++
++ /* The number of packets we need to process on the Rx */
++ num_packets =
++ big_sur_ge_get_packet_count(&emac->recv_channel);
++
++ for (num_processed = 0; num_processed < num_packets;
++ num_processed++) {
++ while (!is_last) {
++ if (big_sur_ge_get_descriptor
++ (&emac->recv_channel,
++ &buffer_desc) == -1)
++ break;
++
++ if (first_desc_ptr == NULL)
++ first_desc_ptr = buffer_desc;
++
++ num_bytes +=
++ xbuf_descriptor_GetLength(buffer_desc);
++
++ if (xbuf_descriptor_IsLastStatus
++ (buffer_desc)) {
++ is_last = 1;
++ }
++
++ num_buffers++;
++ }
++
++ /* Number of buffers is always 1 since we dont do SG */
++
++ /*
++ * Only for SG DMA which is currently not supported. In the
++ * future, as we have SG channel working, we will code this
++ * receive side routine. For now, do nothing. This is never
++ * called from FIFO mode - Manish
++ */
++ big_sur_ge_decr_packet_count(&emac->recv_channel);
++ }
++ }
++
++ /* Ack the interrupts */
++ big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
++
++ if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
++ /* We need a reset here */
++ }
++
++ big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
++}
++
++/****************************************************************
++ * Handle the send side DMA interrupt
++ ****************************************************************/
++static void big_sur_ge_handle_send_intr(big_sur_ge * emac)
++{
++ unsigned long int_status;
++
++ int_status = big_sur_ge_get_intr_status(&emac->send_channel);
++
++ if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
++ BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
++ unsigned long num_frames = 0;
++ unsigned long num_processed = 0;
++ unsigned long num_buffers = 0;
++ unsigned long num_bytes = 0;
++ unsigned long is_last = 0;
++ xbuf_descriptor *first_desc_ptr = NULL;
++ xbuf_descriptor *buffer_desc;
++
++ num_frames =
++ big_sur_ge_get_packet_count(&emac->send_channel);
++
++ for (num_processed = 0; num_processed < num_frames;
++ num_processed++) {
++ while (!is_last) {
++ if (big_sur_ge_get_descriptor
++ (&emac->send_channel, &buffer_desc)
++ == -1) {
++ break;
++ }
++
++ if (first_desc_ptr == NULL)
++ first_desc_ptr = buffer_desc;
++
++ num_bytes +=
++ xbuf_descriptor_GetLength(buffer_desc);
++ if (xbuf_descriptor_IsLastControl
++ (buffer_desc))
++ is_last = 1;
++
++ num_buffers++;
++ }
++
++ /*
++ * Only for SG DMA which is currently not supported. In the
++ * future, as we have SG channel working, we will code this
++ * receive side routine. For now, do nothing. This is never
++ * called from FIFO mode - Manish
++ */
++ big_sur_ge_decr_packet_count(&emac->send_channel);
++ }
++ }
++
++ /* Ack the interrupts and reset DMA channel if necessary */
++ big_sur_ge_set_intr_status(&emac->send_channel, int_status);
++ if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
++ /* Manish : need reset */
++ }
++
++ big_sur_ge_set_intr_status(&emac->send_channel, int_status);
++}
++
++/*****************************************************************
++ * For now, the MAC address errors dont trigger a update of the
++ * stats. There is no stats framework in place. Hence, we just
++ * check for the errors below and do a reset if needed.
++ *****************************************************************/
++static void big_sur_ge_check_mac_error(big_sur_ge * emac,
++ unsigned long int_status)
++{
++ if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
++ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
++ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
++ BIG_SUR_GE_EIR_RECV_ERROR_MASK |
++ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
++ BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
++ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
++ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
++ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
++ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
++ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
++ BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
++ BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
++ BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
++ BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) {
++
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_IIER_OFFSET, 0);
++ /*
++ * Manish Reset the MAC here
++ */
++ }
++}
++
++/*****************************************************************
++ * Check for FIFO Recv errors
++ *****************************************************************/
++static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac)
++{
++ if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
++ unsigned long intr_enable;
++
++ intr_enable =
++ BIG_SUR_GE_READ(emac->base_address +
++ XIIF_V123B_DIER_OFFSET);
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_DIER_OFFSET,
++ intr_enable &
++ ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
++
++ }
++}
++
++/*****************************************************************
++ * Check for FIFO Send errors
++ *****************************************************************/
++static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac)
++{
++ if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
++ unsigned long intr_enable;
++
++ intr_enable =
++ BIG_SUR_GE_READ(emac->base_address +
++ XIIF_V123B_DIER_OFFSET);
++ BIG_SUR_GE_WRITE(emac->base_address +
++ XIIF_V123B_DIER_OFFSET,
++ intr_enable &
++ ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
++ }
++}
++
++/*****************************************************************
++ * GE unit init
++ ****************************************************************/
++static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id)
++{
++ unsigned long reg_data;
++ big_sur_ge_config *config;
++ int err;
++
++ /* Assume that the device has been stopped */
++
++ config = big_sur_ge_lookup_config(device_id);
++ if (config == NULL)
++ return -1;
++
++ emac->ready = 0;
++ emac->started = 0;
++ emac->dma_sg = 0; /* This MAC has no support for Scatter Gather DMA */
++ emac->has_mii = config->has_mii;
++ emac->has_mcast_hash_table = 0;
++ emac->dma_config = config->dma_config;
++
++ /*
++ * Initialize the FIFO send and recv handlers to the stub handlers.
++ * We only deal with the FIFO mode of operation since SG is not supported.
++ * Also, there is no error handler. We try to handle as much of error as
++ * possible and then return. No error codes also.
++ */
++
++ emac->base_address = config->base_address;
++
++ if (big_sur_ge_config_dma(emac) == -1)
++ return -1;
++
++ err = big_sur_ge_config_fifo(emac);
++ if (err == -1)
++ return err;
++
++ /* Now, we know that the FIFO initialized successfully. So, set the ready flag */
++ emac->ready = 1;
++
++ /* Do we need a PHY reset here also. It did cause problems on some boards */
++ big_sur_ge_enet_reset(emac);
++
++ /* PHY reset code. Remove if causes a problem on the board */
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++ reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++ reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++
++ return 0;
++}
++
++/*******************************************************************
++ * Start the GE unit for Tx, Rx and Interrupts
++ *******************************************************************/
++static int big_sur_ge_start(big_sur_ge * emac)
++{
++ unsigned long reg_data;
++
++ /*
++ * Basic mode of operation is polled and interrupt mode. We disable the polled
++ * mode for good. We may use the polled mode for Rx NAPI but that does not
++ * require all the interrupts to be disabled
++ */
++
++ emac->polled = 0;
++
++ /*
++ * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working
++ * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may
++ * not use FIFO at all. So, we enable the interrupts below
++ */
++
++ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
++ BIG_SUR_GE_IPIF_FIFO_DFT_MASK |
++ XIIF_V123B_ERROR_MASK);
++
++ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
++ BIG_SUR_GE_EIR_DFT_FIFO_MASK);
++
++ /* Toggle the started flag */
++ emac->started = 1;
++
++ /* Start the Tx and Rx units respectively */
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++ reg_data &=
++ ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK |
++ BIG_SUR_GE_ECR_RECV_RESET_MASK);
++ reg_data |=
++ (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
++ BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++
++ return 0;
++}
++
++/**************************************************************************
++ * Stop the GE unit
++ **************************************************************************/
++static int big_sur_ge_stop(big_sur_ge * emac)
++{
++ unsigned long reg_data;
++
++ /* We assume that the device is not already stopped */
++ if (!emac->started)
++ return 0;
++
++ /* Disable the Tx and Rx unit respectively */
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++ reg_data &=
++ ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
++ BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++
++ /* Disable the interrupts */
++ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
++
++ /* Toggle the started flag */
++ emac->started = 0;
++
++ return 0;
++}
++
++/************************************************************************
++ * Reset the GE MAC unit
++ *************************************************************************/
++static void big_sur_ge_enet_reset(big_sur_ge * emac)
++{
++ unsigned long reg_data;
++
++ (void) big_sur_ge_stop(emac);
++
++ BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
++ XIIF_V123B_RESET_MASK);
++
++ /*
++ * For now, configure the receiver to not strip off FCS and padding since
++ * this is not currently supported. In the future, just take the default
++ * and provide the option for the user to change this behavior.
++ */
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++ reg_data &=
++ ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK |
++ BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
++ reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++}
++
++/*************************************************************************
++ * Set the MAC address of the GE mac unit
++ *************************************************************************/
++static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr)
++{
++ unsigned long mac_addr = 0;
++
++ /* Device is started and so mac address must be set */
++ if (emac->started == 1)
++ return 0;
++
++ mac_addr = ((addr[0] << 8) | addr[1]);
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET,
++ mac_addr);
++
++ mac_addr |= ((addr[2] << 24) | (addr[3] << 16) |
++ (addr[4] << 8) | addr[5]);
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET,
++ mac_addr);
++
++ return 0;
++}
++
++/****************************************************************************
++ * Get the MAC address of the GE MAC unit
++ ***************************************************************************/
++static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr)
++{
++ unsigned long mac_addr_hi, mac_addr_lo;
++
++ mac_addr_hi =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
++ mac_addr_lo =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
++
++ addr[0] = (mac_addr_hi >> 8);
++ addr[1] = mac_addr_hi;
++
++ addr[2] = (mac_addr_lo >> 24);
++ addr[3] = (mac_addr_lo >> 16);
++ addr[4] = (mac_addr_lo >> 8);
++ addr[5] = mac_addr_lo;
++}
++
++/*********************************************************************************
++ * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple
++ *********************************************************************************/
++static int big_sur_ge_config_dma(big_sur_ge * emac)
++{
++ if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
++ BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
++ printk(KERN_ERR "Could not initialize the DMA unit \n");
++ return -1;
++ }
++
++ if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
++ BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
++ printk(KERN_ERR "Could not initialize the DMA unit \n");
++ return -1;
++ }
++
++ return 0;
++}
++
++/******************************************************************************
++ * Configure the FIFO for simple DMA
++ ******************************************************************************/
++static int big_sur_ge_config_fifo(big_sur_ge * emac)
++{
++ int err = 0;
++
++ err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
++ BIG_SUR_GE_PFIFO_RXREG_OFFSET,
++ emac->base_address +
++ BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
++
++ if (err == -1) {
++ printk(KERN_ERR
++ "Could not initialize Rx packet FIFO for Simple DMA \n");
++ return err;
++ }
++
++ err = packet_fifo_init(&emac->send_fifo, emac->base_address +
++ BIG_SUR_GE_PFIFO_TXREG_OFFSET,
++ emac->base_address +
++ BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
++
++ if (err == -1) {
++ printk(KERN_ERR
++ "Could not initialize Tx packet FIFO for Simple DMA \n");
++ }
++
++ return err;
++}
++
++#define BIG_SUR_GE_NUM_INSTANCES 2
++
++
++/**********************************************************************************
++ * Look up the config of the MAC
++ **********************************************************************************/
++static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id)
++{
++ big_sur_ge_config *config = NULL;
++ int i = 0;
++
++ for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) {
++ /* Manish : Init the config here */
++ break;
++ }
++
++ return config;
++}
++
++typedef struct {
++ unsigned long option;
++ unsigned long mask;
++} option_map;
++
++static option_map option_table[] = {
++ {BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
++ {BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
++ {BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
++ {BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
++ {BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
++ {BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
++ {BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
++ {BIG_SUR_GE_INSERT_PAD_OPTION,
++ BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
++ {BIG_SUR_GE_INSERT_FCS_OPTION,
++ BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
++ {BIG_SUR_GE_INSERT_ADDR_OPTION,
++ BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
++ {BIG_SUR_GE_OVWRT_ADDR_OPTION,
++ BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
++ {BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
++ {BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
++ {BIG_SUR_GE_STRIP_PAD_FCS_OPTION,
++ BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
++};
++
++#define BIG_SUR_GE_NUM_OPTIONS (sizeof(option_table) / sizeof(option_map))
++
++/**********************************************************************
++ * Set the options for the GE
++ **********************************************************************/
++static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag)
++{
++ unsigned long reg_data;
++ unsigned int index;
++
++ /* Assume that the device is stopped before calling this function */
++
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++ for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
++ if (option_flag & option_table[index].option)
++ reg_data |= option_table[index].mask;
++ else
++ reg_data &= ~(option_table[index].mask);
++
++ }
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++ reg_data);
++
++ /* No polled option */
++ emac->polled = 0;
++
++ return 0;
++}
++
++/*******************************************************
++ * Get the options from the GE
++ *******************************************************/
++static unsigned long big_sur_ge_get_options(big_sur_ge * emac)
++{
++ unsigned long option_flag = 0, reg_data;
++ unsigned int index;
++
++ reg_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++
++ for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
++ if (option_flag & option_table[index].option)
++ reg_data |= option_table[index].mask;
++ }
++
++ /* No polled mode */
++
++ return option_flag;
++}
++
++/********************************************************
++ * Set the Inter frame gap
++ ********************************************************/
++static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2)
++{
++ unsigned long config;
++
++ /* Assume that the device is stopped before calling this */
++
++ config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
++ (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT));
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET,
++ config);
++
++ return 0;
++}
++
++/********************************************************
++ * Get the Inter frame gap
++ ********************************************************/
++static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2)
++{
++ unsigned long config;
++
++ config =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
++ *part1 =
++ ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >>
++ BIG_SUR_GE_IFGP_PART1_SHIFT);
++ *part2 =
++ ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >>
++ BIG_SUR_GE_IFGP_PART2_SHIFT);
++}
++
++/*******************************************************************
++ * PHY specific functions for the MAC
++ *******************************************************************/
++#define BIG_SUR_GE_MAX_PHY_ADDR 32
++#define BIG_SUR_GE_MAX_PHY_REG 32
++
++/*******************************************************************
++ * Read the PHY reg
++ *******************************************************************/
++static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr,
++ unsigned long reg_num, unsigned int *data)
++{
++ unsigned long mii_control, mii_data;
++
++ if (!emac->has_mii)
++ return -1;
++
++ mii_control =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
++ if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
++ printk(KERN_ERR "PHY busy \n");
++ return -1;
++ }
++
++ mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
++ mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
++ mii_control |=
++ (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
++ BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
++ mii_control);
++
++ while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
++ if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
++ break;
++
++ mii_data =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
++ *data = (unsigned int) mii_data;
++
++ return 0;
++}
++
++/**********************************************************************
++ * Write to the PHY register
++ **********************************************************************/
++static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr,
++ unsigned long reg_num, unsigned int data)
++{
++ unsigned long mii_control;
++
++ if (!emac->has_mii)
++ return -1;
++
++ mii_control =
++ BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
++ if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
++ printk(KERN_ERR "PHY busy \n");
++ return -1;
++ }
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET,
++ (unsigned long) data);
++
++ mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
++ mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
++ mii_control |=
++ (BIG_SUR_GE_MGTCR_START_MASK |
++ BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
++
++ BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
++ mii_control);
++
++ while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
++ if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
++ break;
++
++ return 0;
++}
++
++
++
++
++
++
++/********************************************************************
++ * The hardware dependent part of the driver begins here
++ ********************************************************************/
++
++
++/*******************************************************************
++ * Reset the GE system
++ *******************************************************************/
++static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ struct sk_buff *skb;
++ unsigned long options;
++ int ifcfg1, ifcfg2;
++
++ /* Stop the queue */
++ netif_stop_queue(netdev);
++
++ big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2);
++ options = big_sur_ge_get_options(&lp->emac);
++ switch (duplex) {
++ case HALF_DUPLEX:
++ options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
++ break;
++
++ case FULL_DUPLEX:
++ options |= BIG_SUR_GE_FDUPLEX_OPTION;
++ break;
++
++ case UNKNOWN:
++ break;
++ }
++
++ /* There is no support for SG DMA in a 100 Mpbs NIC */
++
++ big_sur_ge_enet_reset(&lp->emac);
++
++ /* Set the necessary options for the MAC unit */
++ big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr);
++ big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2);
++ big_sur_ge_set_options(&lp->emac, options);
++
++ (void) big_sur_ge_start(&lp->emac);
++
++ spin_lock_irq(&lp->lock);
++ skb = lp->saved_skb;
++ lp->saved_skb = NULL;
++ spin_unlock_irq(&lp->lock);
++
++ if (skb)
++ dev_kfree_skb(skb);
++
++ /* Wake the queue */
++ netif_wake_queue(netdev);
++}
++
++/********************************************************************
++ * Get the PHY status
++ *******************************************************************/
++static int big_sur_ge_get_phy_status(struct net_device *netdev,
++ DUPLEX * duplex, int *linkup)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ unsigned int reg_data;
++ int err = 0;
++
++ err =
++ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR,
++ ®_data);
++ if (err == -1) {
++ printk(KERN_ERR "%s: Could not read PHY control register",
++ netdev->name);
++ return err;
++ }
++
++ if (!(reg_data & BMCR_ANENABLE)) {
++ if (reg_data & BMCR_FULLDPLX)
++ *duplex = FULL_DUPLEX;
++ else
++ *duplex = HALF_DUPLEX;
++ } else {
++ unsigned int advertise, partner, neg;
++
++ err =
++ big_sur_ge_phy_read(&lp->emac, lp->mii_addr,
++ MII_ADVERTISE, &advertise);
++ if (err == -1) {
++ printk(KERN_ERR
++ "%s: Could not read PHY control register",
++ netdev->name);
++ return err;
++ }
++
++ err =
++ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA,
++ &partner);
++ if (err == -1) {
++ printk(KERN_ERR
++ "%s: Could not read PHY control register",
++ netdev->name);
++ return err;
++ }
++
++ neg = advertise & partner & ADVERTISE_ALL;
++ if (neg & ADVERTISE_100FULL)
++ *duplex = FULL_DUPLEX;
++ else if (neg & ADVERTISE_100HALF)
++ *duplex = HALF_DUPLEX;
++ else if (neg & ADVERTISE_10FULL)
++ *duplex = FULL_DUPLEX;
++ else
++ *duplex = HALF_DUPLEX;
++
++ err =
++ big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR,
++ ®_data);
++ if (err == -1) {
++ printk(KERN_ERR
++ "%s: Could not read PHY control register",
++ netdev->name);
++ return err;
++ }
++
++ *linkup = (reg_data & BMSR_LSTATUS) != 0;
++
++ }
++ return 0;
++}
++
++/************************************************************
++ * Poll the MII for duplex and link status
++ ***********************************************************/
++static void big_sur_ge_poll_mii(unsigned long data)
++{
++ struct net_device *netdev = (struct net_device *) data;
++ struct big_sur_ge_enet *lp = netdev->priv;
++ unsigned long options;
++ DUPLEX mac_duplex, phy_duplex;
++ int phy_carrier, netif_carrier;
++
++ if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) ==
++ -1) {
++ printk(KERN_ERR "%s: Terminating link monitoring.\n",
++ netdev->name);
++ return;
++ }
++
++ options = big_sur_ge_get_options(&lp->emac);
++ if (options & BIG_SUR_GE_FDUPLEX_OPTION)
++ mac_duplex = FULL_DUPLEX;
++ else
++ mac_duplex = HALF_DUPLEX;
++
++ if (mac_duplex != phy_duplex) {
++ disable_irq(netdev->irq);
++ big_sur_ge_reset(netdev, phy_duplex);
++ enable_irq(netdev->irq);
++ }
++
++ netif_carrier = netif_carrier_ok(netdev) != 0;
++
++ if (phy_carrier != netif_carrier) {
++ if (phy_carrier) {
++ printk(KERN_INFO "%s: Link carrier restored.\n",
++ netdev->name);
++ netif_carrier_on(netdev);
++ } else {
++ printk(KERN_INFO "%s: Link carrier lost.\n",
++ netdev->name);
++ netif_carrier_off(netdev);
++ }
++ }
++
++ /* Set up the timer so we'll get called again in 2 seconds. */
++ lp->phy_timer.expires = jiffies + 2 * HZ;
++ add_timer(&lp->phy_timer);
++}
++
++/**************************************************************
++ * Open the network interface
++ *************************************************************/
++static int big_sur_ge_open(struct net_device *netdev)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ unsigned long options;
++ DUPLEX phy_duplex, mac_duplex;
++ int phy_carrier, retval;
++
++ (void) big_sur_ge_stop(&lp->emac);
++
++ if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
++ printk(KERN_ERR "%s: Could not set MAC address.\n",
++ netdev->name);
++ return -EIO;
++ }
++
++ options = big_sur_ge_get_options(&lp->emac);
++
++ retval =
++ request_irq(netdev->irq, &big_sur_ge_int_handler, 0,
++ netdev->name, netdev);
++ if (retval) {
++ printk(KERN_ERR
++ "%s: Could not allocate interrupt %d.\n",
++ netdev->name, netdev->irq);
++
++ return retval;
++ }
++
++ if (!
++ (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier)))
++ {
++ if (options & BIG_SUR_GE_FDUPLEX_OPTION)
++ mac_duplex = FULL_DUPLEX;
++ else
++ mac_duplex = HALF_DUPLEX;
++
++ if (mac_duplex != phy_duplex) {
++ switch (phy_duplex) {
++ case HALF_DUPLEX:
++ options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
++ break;
++ case FULL_DUPLEX:
++ options |= BIG_SUR_GE_FDUPLEX_OPTION;
++ break;
++ case UNKNOWN:
++ break;
++ }
++
++ big_sur_ge_set_options(&lp->emac, options);
++ }
++ }
++
++ if (big_sur_ge_start(&lp->emac) == -1) {
++ printk(KERN_ERR "%s: Could not start device.\n",
++ netdev->name);
++ free_irq(netdev->irq, netdev);
++ return -EBUSY;
++ }
++
++ netif_start_queue(netdev);
++
++ lp->phy_timer.expires = jiffies + 2 * HZ;
++ lp->phy_timer.data = (unsigned long) netdev;
++ lp->phy_timer.function = &big_sur_ge_poll_mii;
++ add_timer(&lp->phy_timer);
++
++ return 0;
++}
++
++/*********************************************************************
++ * Close the network device interface
++ *********************************************************************/
++static int big_sur_ge_close(struct net_device *netdev)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++
++ del_timer_sync(&lp->phy_timer);
++ netif_stop_queue(netdev);
++
++ free_irq(netdev->irq, netdev);
++
++ if (big_sur_ge_stop(&lp->emac) == -1) {
++ printk(KERN_ERR "%s: Could not stop device.\n",
++ netdev->name);
++ return -EBUSY;
++ }
++
++ return 0;
++}
++
++/*********************************************************************
++ * Get the network device stats. For now, do nothing
++ *********************************************************************/
++static struct net_device_stats *big_sur_ge_get_stats(struct net_device
++ *netdev)
++{
++ /* Do nothing */
++ return (struct net_device_stats *) 0;
++}
++
++/********************************************************************
++ * FIFO send for a packet that needs to be transmitted
++ ********************************************************************/
++static int big_sur_ge_fifo_send(struct sk_buff *orig_skb,
++ struct net_device *netdev)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ struct sk_buff *new_skb;
++ unsigned int len, align;
++
++ netif_stop_queue(netdev);
++ len = orig_skb->len;
++
++ if (!(new_skb = dev_alloc_skb(len + 4))) {
++ dev_kfree_skb(orig_skb);
++ printk(KERN_ERR
++ "%s: Could not allocate transmit buffer.\n",
++ netdev->name);
++ netif_wake_queue(netdev);
++ return -EBUSY;
++ }
++
++ align = 4 - ((unsigned long) new_skb->data & 3);
++ if (align != 4)
++ skb_reserve(new_skb, align);
++
++ skb_put(new_skb, len);
++ memcpy(new_skb->data, orig_skb->data, len);
++
++ dev_kfree_skb(orig_skb);
++
++ lp->saved_skb = new_skb;
++ if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len)
++ == -1) {
++ spin_lock_irq(&lp->lock);
++ new_skb = lp->saved_skb;
++ lp->saved_skb = NULL;
++ spin_unlock_irq(&lp->lock);
++
++ dev_kfree_skb(new_skb);
++ printk(KERN_ERR "%s: Could not transmit buffer.\n",
++ netdev->name);
++ netif_wake_queue(netdev);
++ return -EIO;
++ }
++ return 0;
++}
++
++/**********************************************************************
++ * Call the fifo send handler
++ **********************************************************************/
++static void big_sur_ge_fifo_send_handler(void *callback)
++{
++ struct net_device *netdev = (struct net_device *) callback;
++ struct big_sur_ge_enet *lp = netdev->priv;
++ struct sk_buff *skb;
++
++ spin_lock_irq(&lp->lock);
++ skb = lp->saved_skb;
++ lp->saved_skb = NULL;
++ spin_unlock_irq(&lp->lock);
++
++ if (skb)
++ dev_kfree_skb(skb);
++
++ netif_wake_queue(netdev);
++}
++
++/**********************************************************************
++ * Handle the timeout of the ethernet device
++ **********************************************************************/
++static void big_sur_ge_tx_timeout(struct net_device *netdev)
++{
++ printk
++ ("%s: Exceeded transmit timeout of %lu ms. Resetting mac.\n",
++ netdev->name, TX_TIMEOUT * 1000UL / HZ);
++
++ disable_irq(netdev->irq);
++ big_sur_ge_reset(netdev, UNKNOWN);
++ enable_irq(netdev->irq);
++}
++
++/*********************************************************************
++ * When in FIFO mode, the callback function for packets received
++ *********************************************************************/
++static void big_sur_ge_fifo_recv_handler(void *callback)
++{
++ struct net_device *netdev = (struct net_device *) callback;
++ struct big_sur_ge_enet *lp = netdev->priv;
++ struct sk_buff *skb;
++ unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
++ unsigned int align;
++
++ if (!(skb = dev_alloc_skb(len + 4))) {
++ printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
++ netdev->name);
++ return;
++ }
++
++ align = 4 - ((unsigned long) skb->data & 3);
++ if (align != 4)
++ skb_reserve(skb, align);
++
++ if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) ==
++ -1) {
++ dev_kfree_skb(skb);
++
++ printk(KERN_ERR "%s: Could not receive buffer \n",
++ netdev->name);
++ netdev->tx_timeout = NULL;
++ big_sur_ge_reset(netdev, UNKNOWN);
++ netdev->tx_timeout = big_sur_ge_tx_timeout;
++ }
++
++ skb_put(skb, len); /* Tell the skb how much data we got. */
++ skb->dev = netdev; /* Fill out required meta-data. */
++ skb->protocol = eth_type_trans(skb, netdev);
++
++ netif_rx(skb); /* Send the packet upstream. */
++}
++
++/*********************************************************************
++ * Set the Multicast Hash list
++ *********************************************************************/
++static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ unsigned long options;
++
++ disable_irq(netdev->irq);
++ local_bh_disable();
++
++ (void) big_sur_ge_stop(&lp->emac);
++ options = big_sur_ge_get_options(&lp->emac);
++ options &=
++ ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
++
++ /* Do nothing for now */
++
++ (void) big_sur_ge_start(&lp->emac);
++ local_bh_enable();
++ enable_irq(netdev->irq);
++}
++
++/***********************************************************************
++ * IOCTL support
++ ***********************************************************************/
++static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq,
++ int cmd)
++{
++ struct big_sur_ge_enet *lp = netdev->priv;
++ struct mii_ioctl_data *data =
++ (struct mii_ioctl_data *) &rq->ifr_data;
++
++ switch (cmd) {
++ case SIOCGMIIPHY: /* Get address of MII PHY in use. */
++ case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
++ data->phy_id = lp->mii_addr;
++
++ case SIOCGMIIREG: /* Read MII PHY register. */
++ case SIOCDEVPRIVATE + 1: /* for binary compat, remove in 2.5 */
++ if (data->phy_id > 31 || data->reg_num > 31)
++ return -ENXIO;
++
++ del_timer_sync(&lp->phy_timer);
++
++ if (big_sur_ge_phy_read(&lp->emac, data->phy_id,
++ data->reg_num,
++ &data->val_out) == -1) {
++ printk(KERN_ERR "%s: Could not read from PHY",
++ netdev->name);
++ return -EBUSY;
++ }
++
++ lp->phy_timer.expires = jiffies + 2 * HZ;
++ add_timer(&lp->phy_timer);
++
++ return 0;
++
++ case SIOCSMIIREG: /* Write MII PHY register. */
++ case SIOCDEVPRIVATE + 2: /* for binary compat, remove in 2.5 */
++ if (data->phy_id > 31 || data->reg_num > 31)
++ return -ENXIO;
++
++ del_timer_sync(&lp->phy_timer);
++
++ if (big_sur_ge_phy_write
++ (&lp->emac, data->phy_id, data->reg_num,
++ data->val_in) == -1) {
++ printk(KERN_ERR "%s: Could not write to PHY",
++ netdev->name);
++ return -EBUSY;
++ }
++
++ lp->phy_timer.expires = jiffies + 2 * HZ;
++ add_timer(&lp->phy_timer);
++
++ return 0;
++
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++/*****************************************************************
++ * Get the config from the config table
++ *****************************************************************/
++static big_sur_ge_config *big_sur_ge_get_config(int index)
++{
++ /* Manish */
++ return (big_sur_ge_config *) 0;
++}
++
++/*****************************************************************
++ * Release the network device structure
++ *****************************************************************/
++static void big_sur_ge_remove_head(void)
++{
++ struct net_device *netdev;
++ struct big_sur_ge_enet *lp;
++ big_sur_ge_config *config;
++
++ spin_lock(&dev_lock);
++ netdev = dev_list;
++ lp = netdev->priv;
++
++ spin_unlock(&dev_lock);
++
++ config = big_sur_ge_get_config(lp->index);
++ iounmap((void *) config->base_address);
++ config->base_address = lp->save_base_address;
++
++ if (lp->saved_skb)
++ dev_kfree_skb(lp->saved_skb);
++ kfree(lp);
++
++ unregister_netdev(netdev);
++ kfree(netdev);
++}
++
++/*****************************************************************
++ * Initial Function to probe the network interface
++ *****************************************************************/
++static int __init big_sur_ge_probe(int index)
++{
++ static const unsigned long remap_size =
++ BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1;
++ struct net_device *netdev;
++ struct big_sur_ge_enet *lp;
++ big_sur_ge_config *config;
++ unsigned int irq;
++ unsigned long maddr;
++ goto err;
++
++ switch (index) {
++ case 0:
++ irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID);
++ break;
++ case 1:
++ irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID);
++ break;
++ case 2:
++ irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID);
++ break;
++ default:
++ err = -ENODEV;
++ goto out;
++ }
++
++ config = big_sur_ge_get_config(index);
++ if (!config) {
++ err = -ENODEV;
++ goto out;
++ }
++
++ netdev = alloc_etherdev(sizeof(big_sur_ge_config));
++
++ if (!netdev) {
++ err = -ENOMEM;
++ goto out;
++ }
++
++ SET_MODULE_OWNER(netdev);
++
++ netdev->irq = irq;
++
++ lp = (struct big_sur_ge_enet *) netdev->priv;
++ memset(lp, 0, sizeof(struct big_sur_ge_enet));
++ spin_lock_init(&lp->lock);
++ spin_lock(&dev_lock);
++ lp->next_dev = dev_list;
++ dev_list = netdev;
++ spin_unlock(&dev_lock);
++
++ lp->save_base_address = config->base_address;
++ config->base_address =
++ (unsigned long) ioremap(lp->save_base_address, remap_size);
++ if (!config->base_address) {
++ err = -ENOMEM;
++ goto out_unlock;
++ }
++
++ if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) {
++ printk(KERN_ERR "%s: Could not initialize device.\n",
++ netdev->name);
++ err = -ENODEV;
++ goto out_unmap;
++ }
++
++ /* Manish: dev_addr value */
++ memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
++ if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
++ printk(KERN_ERR "%s: Could not set MAC address.\n",
++ netdev->name);
++ err = -EIO;
++ goto out_unmap;
++ }
++
++ /*
++ * There is no Scatter Gather support but there is a Simple DMA support
++ */
++ big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev,
++ big_sur_ge_fifo_recv_handler);
++ big_sur_ge_set_fifo_send_handler(&lp->emac, netdev,
++ big_sur_ge_fifo_send_handler);
++ netdev->hard_start_xmit = big_sur_ge_fifo_send;
++
++ lp->mii_addr = 0xFF;
++
++ for (maddr = 0; maddr < 31; maddr++) {
++ unsigned int reg_data;
++
++ if (big_sur_ge_phy_read
++ (&lp->emac, maddr, MII_BMCR, ®_data) == 0) {
++ lp->mii_addr = maddr;
++ break;
++ }
++ }
++
++ if (lp->mii_addr == 0xFF) {
++ lp->mii_addr = 0;
++ printk(KERN_WARNING
++ "%s: No PHY detected. Assuming a PHY at address %d.\n",
++ netdev->name, lp->mii_addr);
++ }
++
++ netdev->open = big_sur_ge_open;
++ netdev->stop = big_sur_ge_close;
++ netdev->get_stats = big_sur_ge_get_stats; /* Does nothing */
++ netdev->do_ioctl = big_sur_ge_ioctl;
++ netdev->tx_timeout = big_sur_ge_tx_timeout;
++ netdev->watchdog_timeo = TX_TIMEOUT;
++
++ err = register_netdev(netdev))
++ if (!err)
++ goto out_unmap;
++
++ printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d at 0x%08X "
++ "mapped to 0x%08X, irq=%d\n", netdev->name, index,
++ lp->save_base_address, config->base_address, netdev->irq);
++
++ return ret;
++
++out_unmap:
++ iounmap(config->base_address);
++
++out_unlock:
++ big_sur_ge_remove_head();
++
++out:
++ return ret;
++}
++
++static int __init big_sur_ge_init(void)
++{
++ int index = 0;
++
++ while (big_sur_ge_probe(index++) == 0);
++
++ return (index > 1) ? 0 : -ENODEV;
++}
++
++static void __exit big_sur_ge_cleanup(void)
++{
++ while (dev_list)
++ big_sur_ge_remove_head();
++}
++
++module_init(big_sur_ge_init);
++module_exit(big_sur_ge_cleanup);
++
++MODULE_AUTHOR("Manish Lachwani <lachwani at pmc-sierra.com>");
++MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
++MODULE_LICENSE("GPL");
+diff -urN --ignore-space-change kernel.org/drivers/net/big_sur_ge.h linux-mips/drivers/net/big_sur_ge.h
+--- kernel.org/drivers/net/big_sur_ge.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/big_sur_ge.h 2006-01-10 11:21:37.000000000 +0000
+@@ -0,0 +1,713 @@
++/*
++ * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur
++ * ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
++ * Copyright (C) 2005 Ralf Baechle (ralf at linux-mips.org)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ */
++
++#ifndef __BIG_SUR_GE_H__
++#define __BIG_SUR_GE_H__
++
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#define BIG_SUR_DEVICE_NAME "big sur"
++#define BIG_SUR_DEVICE_DESC "Big Sur Ethernet 10/100 MAC"
++
++#define BIG_SUR_GE_BASE 0xbb000000
++
++#define BIG_SUR_GE_WRITE(ofs,data) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data
++
++#define BIG_SUR_GE_READ(ofs) *(volatile u32 *)(BIG_SUR_GE_BASE+(ofs))
++
++/* Manish : Need to fix these defines later */
++#define BIG_SUR_GE_EMAC_0_HIGHADDR
++#define BIG_SUR_GE_EMAC_0_BASEADDR
++#define BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID 1
++#define BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID 2
++#define BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID 3
++#define BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST
++#define BIG_SUR_GE_EMAC_0_DMA_PRESENT
++#define BIG_SUR_GE_EMAC_0_MII_EXIST
++#define BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR
++#define BIG_SUR_GE_EMAC_0_DEVICE_ID
++#define BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST
++#define BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT
++#define BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST
++#define BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID
++
++#define BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT 4UL
++/* IPIF specific defines */
++#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
++#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
++#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
++#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
++#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
++#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
++#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
++#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
++#define XIIF_V123B_RESET_MASK 0xAUL
++#define XIIF_V123B_ERROR_MASK 0x1UL
++
++/* defines */
++#define BIG_SUR_GE_UNICAST_OPTION 0x00000001
++#define BIG_SUR_GE_BROADCAST_OPTION 0x00000002
++#define BIG_SUR_GE_PROMISC_OPTION 0x00000004
++#define BIG_SUR_GE_FDUPLEX_OPTION 0x00000008
++#define BIG_SUR_GE_POLLED_OPTION 0x00000010
++#define BIG_SUR_GE_LOOPBACK_OPTION 0x00000020
++#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080
++#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100
++#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200
++#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400
++#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800
++#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION 0x00002000
++
++/* Not Supported */
++#define BIG_SUR_GE_MULTICAST_OPTION 0x00000040
++#define BIG_SUR_GE_FLOW_CONTROL_OPTION 0x00000080
++#define BIG_SUR_GE_INSERT_PAD_OPTION 0x00000100
++#define BIG_SUR_GE_INSERT_FCS_OPTION 0x00000200
++#define BIG_SUR_GE_INSERT_ADDR_OPTION 0x00000400
++#define BIG_SUR_GE_OVWRT_ADDR_OPTION 0x00000800
++#define BIG_SUR_GE_STRIP_PAD_OPTION 0x00001000
++#define BIG_SUR_GE_STRIP_FCS_OPTION 0x00002000
++
++
++/* Defaults for Interrupt Coalescing in the SG DMA Engine */
++#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */
++#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */
++#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */
++#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */
++
++/* Direction */
++#define BIG_SUR_GE_SEND 1
++#define BIG_SUR_GE_RECV 2
++
++/* SG DMA */
++#define BIG_SUR_GE_SGDMA_NODELAY 0 /* start SG DMA immediately */
++#define BIG_SUR_GE_SGDMA_DELAY 1 /* do not start SG DMA */
++
++#define BIG_SUR_GE_CFG_NO_IPIF 0 /* Not supported by the driver */
++#define BIG_SUR_GE_CFG_NO_DMA 1 /* No DMA */
++#define BIG_SUR_GE_CFG_SIMPLE_DMA 2 /* Simple DMA */
++#define BIG_SUR_GE_CFG_DMA_SG 3 /* DMA scatter gather */
++
++#define BIG_SUR_GE_MAC_ADDR_SIZE 6 /* six-byte MAC address */
++#define BIG_SUR_GE_MTU 1500 /* max size of Ethernet frame */
++#define BIG_SUR_GE_HDR_SIZE 14 /* size of Ethernet header */
++#define BIG_SUR_GE_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
++#define BIG_SUR_GE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
++#define BIG_SUR_GE_MAX_FRAME_SIZE \
++ (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE)
++
++#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE \
++ (BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE)
++
++/* Send and Receive buffers */
++#define BIG_SUR_GE_MIN_RECV_BUFS 32 /* minimum # of recv buffers */
++#define BIG_SUR_GE_DFT_RECV_BUFS 64 /* default # of recv buffers */
++
++#define BIG_SUR_GE_MIN_SEND_BUFS 16 /* minimum # of send buffers */
++#define BIG_SUR_GE_DFT_SEND_BUFS 32 /* default # of send buffers */
++
++#define BIG_SUR_GE_MIN_BUFFERS (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS)
++#define BIG_SUR_GE_DFT_BUFFERS (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS)
++
++/* Send and Receive Descriptors */
++#define BIG_SUR_GE_MIN_RECV_DESC 16 /* minimum # of recv descriptors */
++#define BIG_SUR_GE_DFT_RECV_DESC 32 /* default # of recv descriptors */
++
++#define BIG_SUR_GE_MIN_SEND_DESC 8 /* minimum # of send descriptors */
++#define BIG_SUR_GE_DFT_SEND_DESC 16 /* default # of send descriptors */
++
++/* FIFO Specific Defines */
++#define BIG_SUR_GE_READ_FIFO_TYPE 0 /* a read FIFO */
++#define BIG_SUR_GE_WRITE_FIFO_TYPE 1 /* a write FIFO */
++#define BIG_SUR_GE_RESET_REG_OFFSET 0UL
++#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET 0UL
++#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET 4UL
++#define BIG_SUR_GE_RESET_FIFO_MASK 0x0000000A
++#define BIG_SUR_GE_COUNT_MASK 0x0000FFFF
++#define BIG_SUR_GE_DEADLOCK_MASK 0x20000000
++#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK 0x40000000
++#define BIG_SUR_GE_EMPTY_FULL_MASK 0x80000000
++
++#define BIG_SUR_GE_FIFO_RESET(fifo) \
++ BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK)
++
++#define BIG_SUR_GE_GET_COUNT(fifo) \
++ (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_COUNT_MASK)
++
++#define BIG_SUR_GE_IS_ALMOST_EMPTY(fifo) \
++ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_ALMOST_FULL(fifo) \
++ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_EMPTY(fifo) \
++ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_FULL(fifo) \
++ (BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_DEADLOCKED(fifo) \
++ (BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & \
++ BIG_SUR_GE_DEADLOCK_MASK)
++
++/* Device Config */
++typedef struct _big_sur_ge_config {
++ u16 device_id;
++ u32 base_address;
++ u32 has_counters;
++ u32 has_sg_dma;
++ u8 dma_config;
++ u32 has_mii;
++} big_sur_ge_config;
++
++#define BIG_SUR_GE_SIZE_IN_WORDS 10
++typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS];
++
++/* Callback Functions */
++typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc);
++typedef void (*big_sur_fifo_handler) (void *callback);
++typedef void (*big_sur_irq_handler) (void *instance);
++
++typedef struct _xdma_channel_tag {
++ u32 reg_base_address;
++ u32 base_address;
++ u32 ready;
++ xbuf_descriptor *put_ptr;
++ xbuf_descriptor *get_ptr;
++ xbuf_descriptor *commit_ptr;
++ xbuf_descriptor *last_ptr;
++
++ u32 total_desc_count;
++ u32 active_desc_count;
++} xdma_channel;
++
++typedef struct _packet_fifo {
++ u32 reg_base_addr;
++ u32 ready_status;
++ u32 data_base_address;
++} packet_fifo;
++
++
++/* Big Sur GE driver structure */
++typedef struct _big_sur_ge {
++ u32 base_address;
++ u32 started;
++ u32 ready;
++ u32 polled;
++ u32 dma_sg;
++
++ u8 dma_config;
++ u32 has_mii;
++ u32 has_mcast_hash_table;
++
++ /* For the FIFO and simple DMA case only */
++ packet_fifo recv_fifo;
++ packet_fifo send_fifo;
++
++ big_sur_fifo_handler big_sur_ge_fifo_recv_handler;
++ big_sur_fifo_handler big_sur_ge_fifo_send_handler;
++
++ void *fifo_send_ref;
++ void *fifo_recv_ref;
++
++ /* For SG DMA only */
++ xdma_channel recv_channel;
++ xdma_channel send_channel;
++} big_sur_ge;
++
++/* Offset of the MAC registers from the IPIF base address */
++#define BIG_SUR_GE_REG_OFFSET 0x1100UL
++
++/*
++ * Register offsets for the Ethernet MAC. Each register is 32 bits.
++ */
++#define BIG_SUR_GE_EMIR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x0) /* EMAC Module ID */
++#define BIG_SUR_GE_ECR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x4) /* MAC Control */
++#define BIG_SUR_GE_IFGP_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x8) /* Interframe Gap */
++#define BIG_SUR_GE_SAH_OFFSET (BIG_SUR_GE_REG_OFFSET + 0xC) /* Station addr, high */
++#define BIG_SUR_GE_SAL_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x10) /* Station addr, low */
++#define BIG_SUR_GE_MGTCR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x14) /* MII mgmt control */
++#define BIG_SUR_GE_MGTDR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x18) /* MII mgmt data */
++#define BIG_SUR_GE_RPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x1C) /* Rx packet length */
++#define BIG_SUR_GE_TPLR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x20) /* Tx packet length */
++#define BIG_SUR_GE_TSR_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x24) /* Tx status */
++#define BIG_SUR_GE_RMFC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x28) /* Rx missed frames */
++#define BIG_SUR_GE_RCC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x2C) /* Rx collisions */
++#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30) /* Rx FCS errors */
++#define BIG_SUR_GE_RAEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x34) /* Rx alignment errors */
++#define BIG_SUR_GE_TEDC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x38) /* Transmit excess
++ * deferral cnt */
++/*
++ * Register offsets for the IPIF components
++ */
++#define BIG_SUR_GE_ISR_OFFSET 0x20UL /* Interrupt status */
++
++#define BIG_SUR_GE_DMA_OFFSET 0x2300UL
++#define BIG_SUR_GE_DMA_SEND_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */
++#define BIG_SUR_GE_DMA_RECV_OFFSET (BIG_SUR_GE_DMA_OFFSET + 0x40) /* DMA recv channel */
++
++#define BIG_SUR_GE_PFIFO_OFFSET 0x2000UL
++#define BIG_SUR_GE_PFIFO_TXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x0) /* Tx registers */
++#define BIG_SUR_GE_PFIFO_RXREG_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x10) /* Rx registers */
++#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x100) /* Tx keyhole */
++#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET (BIG_SUR_GE_PFIFO_OFFSET + 0x200) /* Rx keyhole */
++
++/*
++ * EMAC Module Identification Register (EMIR)
++ */
++#define BIG_SUR_GE_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */
++#define BIG_SUR_GE_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */
++
++/*
++ * EMAC Control Register (ECR)
++ */
++#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK 0x80000000 /* Full duplex mode */
++#define BIG_SUR_GE_ECR_XMIT_RESET_MASK 0x40000000 /* Reset transmitter */
++#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK 0x20000000 /* Enable transmitter */
++#define BIG_SUR_GE_ECR_RECV_RESET_MASK 0x10000000 /* Reset receiver */
++#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK 0x08000000 /* Enable receiver */
++#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK 0x04000000 /* Enable PHY */
++#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK 0x02000000 /* Enable xmit pad insert */
++#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK 0x01000000 /* Enable xmit FCS insert */
++#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK 0x00800000 /* Enable xmit source addr insertion */
++#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK 0x00400000 /* Insert xmit error */
++#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000 /* Enable xmit source addr overwrite */
++#define BIG_SUR_GE_ECR_LOOPBACK_MASK 0x00100000 /* Enable internal loopback */
++#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK 0x00080000 /* Enable recv pad strip */
++#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK 0x00040000 /* Enable recv FCS strip */
++#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK 0x00080000 /* Enable recv pad/fcs strip */
++#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK 0x00020000 /* Enable unicast addr */
++#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK 0x00010000 /* Enable multicast addr */
++#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK 0x00008000 /* Enable broadcast addr */
++#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK 0x00004000 /* Enable promiscuous mode */
++#define BIG_SUR_GE_ECR_RECV_ALL_MASK 0x00002000 /* Receive all frames */
++#define BIG_SUR_GE_ECR_RESERVED2_MASK 0x00001000 /* Reserved */
++#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK 0x00000800 /* Enable multicast hash */
++#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK 0x00000400 /* Interpret pause frames */
++#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK 0x00000200 /* Clear hash table */
++#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK 0x00000100 /* Add hash table address */
++
++/*
++ * Interframe Gap Register (IFGR)
++ */
++#define BIG_SUR_GE_IFGP_PART1_MASK 0xF8000000 /* Interframe Gap Part1 */
++#define BIG_SUR_GE_IFGP_PART1_SHIFT 27
++#define BIG_SUR_GE_IFGP_PART2_MASK 0x07C00000 /* Interframe Gap Part2 */
++#define BIG_SUR_GE_IFGP_PART2_SHIFT 22
++
++/*
++ * Station Address High Register (SAH)
++ */
++#define BIG_SUR_GE_SAH_ADDR_MASK 0x0000FFFF /* Station address high bytes */
++
++/*
++ * Station Address Low Register (SAL)
++ */
++#define BIG_SUR_GE_SAL_ADDR_MASK 0xFFFFFFFF /* Station address low bytes */
++
++/*
++ * MII Management Control Register (MGTCR)
++ */
++#define BIG_SUR_GE_MGTCR_START_MASK 0x80000000 /* Start/Busy */
++#define BIG_SUR_GE_MGTCR_RW_NOT_MASK 0x40000000 /* Read/Write Not (direction) */
++#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK 0x3E000000 /* PHY address */
++#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */
++#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK 0x01F00000 /* Register address */
++#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */
++#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK 0x00080000 /* Enable MII from EMAC */
++#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK 0x00040000 /* MII mgmt read error */
++
++/*
++ * MII Management Data Register (MGTDR)
++ */
++#define BIG_SUR_GE_MGTDR_DATA_MASK 0x0000FFFF /* MII data */
++
++/*
++ * Receive Packet Length Register (RPLR)
++ */
++#define BIG_SUR_GE_RPLR_LENGTH_MASK 0x0000FFFF /* Receive packet length */
++
++/*
++ * Transmit Packet Length Register (TPLR)
++ */
++#define BIG_SUR_GE_TPLR_LENGTH_MASK 0x0000FFFF /* Transmit packet length */
++
++/*
++ * Transmit Status Register (TSR)
++ */
++#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000 /* Transmit excess deferral */
++#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK 0x40000000 /* Packet FIFO underrun */
++#define BIG_SUR_GE_TSR_ATTEMPTS_MASK 0x3E000000 /* Transmission attempts */
++#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK 0x01000000 /* Transmit late collision */
++
++/*
++ * Receive Missed Frame Count (RMFC)
++ */
++#define BIG_SUR_GE_RMFC_DATA_MASK 0x0000FFFF
++
++/*
++ * Receive Collision Count (RCC)
++ */
++#define BIG_SUR_GE_RCC_DATA_MASK 0x0000FFFF
++/*
++ * Receive FCS Error Count (RFCSEC)
++ */
++#define BIG_SUR_GE_RFCSEC_DATA_MASK 0x0000FFFF
++
++/*
++ * Receive Alignment Error Count (RALN)
++ */
++#define BIG_SUR_GE_RAEC_DATA_MASK 0x0000FFFF
++
++/*
++ * Transmit Excess Deferral Count (TEDC)
++ */
++#define BIG_SUR_GE_TEDC_DATA_MASK 0x0000FFFF
++
++/*
++ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
++ * part of the IPIF IP Interrupt registers
++ */
++#define BIG_SUR_GE_EIR_XMIT_DONE_MASK 0x00000001 /* Xmit complete */
++#define BIG_SUR_GE_EIR_RECV_DONE_MASK 0x00000002 /* Recv complete */
++#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK 0x00000004 /* Xmit error */
++#define BIG_SUR_GE_EIR_RECV_ERROR_MASK 0x00000008 /* Recv error */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /* Xmit status fifo empty */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020 /* Recv length fifo empty */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK 0x00000040 /* Xmit length fifo full */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK 0x00000080 /* Recv length fifo overrun */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK 0x00000100 /* Recv length fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK 0x00000200 /* Xmit status fifo overrun */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400 /* Transmit status fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK 0x00000800 /* Transmit length fifo overrun */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000 /* Transmit length fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK 0x00002000 /* Transmit pause pkt received */
++#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK 0x00004000 /* Receive data fifo overrun */
++#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000 /* Receive missed frame error */
++#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK 0x00010000 /* Receive collision error */
++#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK 0x00020000 /* Receive FCS error */
++#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK 0x00040000 /* Receive length field error */
++#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK 0x00080000 /* Receive short frame error */
++#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK 0x00100000 /* Receive long frame error */
++#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK 0x00200000 /* Receive alignment error */
++
++#define BIG_SUR_GE_READ_REG(base_addr, reg_offset) \
++ BIG_SUR_GE_READ(base_addr + reg_offset)
++
++#define BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data) \
++ BIG_SUR_GE_WRITE(base_addr + reg_offset, data)
++
++#define BIG_SUR_GE_CONTROL_REG(base_addr, mask) \
++ BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask)
++
++/* Set the MAC Address */
++#define big_sur_ge_set_mac(base_addr, address) \
++{ \
++ u32 mac_addr; \
++ \
++ mac_addr = ((address[0] << 8) | (address[1]); \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address); \
++ \
++ mac_addr = ((address[2] << 24) | (address[3] << 16) | \
++ (address[4] << 8) | address[5]); \
++ \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address); \
++ \
++}
++
++/* Enable the MAC unit */
++#define big_sur_ge_mac_enable(base_address) \
++{ \
++ u32 control; \
++ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
++ control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK); \
++ control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
++}
++
++/* Disable the MAC unit */
++#define big_sur_ge_mac_disable(base_address) \
++{ \
++ u32 control; \
++ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
++ control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK); \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
++}
++
++/* Check if the Tx is done */
++#define big_sur_ge_tx_done(base_address) \
++ (BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK)
++
++
++/* Check if Rx FIFO is empty */
++#define big_sur_ge_rx_empty(base_address) \
++ (!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK))
++
++/* Reset the MAC PHY */
++#define big_sur_ge_reset_phy(base_address) \
++{ \
++ u32 control; \
++ control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET); \
++ control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK); \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
++ control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK; \
++ BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control); \
++}
++
++/* DMA SG defines */
++#define BIG_SUR_GE_CONTROL_LAST_BD_MASK 0x02000000
++#define BIG_SUR_GE_STATUS_LAST_BD_MASK 0x10000000
++#define BIG_SUR_GE_RST_REG_OFFSET 0 /* reset register */
++#define BIG_SUR_GE_MI_REG_OFFSET 0 /* module information register */
++#define BIG_SUR_GE_DMAC_REG_OFFSET 4 /* DMA control register */
++#define BIG_SUR_GE_SA_REG_OFFSET 8 /* source address register */
++#define BIG_SUR_GE_DA_REG_OFFSET 12 /* destination address register */
++#define BIG_SUR_GE_LEN_REG_OFFSET 16 /* length register */
++#define BIG_SUR_GE_DMAS_REG_OFFSET 20 /* DMA status register */
++#define BIG_SUR_GE_BDA_REG_OFFSET 24 /* buffer descriptor address register */
++#define BIG_SUR_GE_SWCR_REG_OFFSET 28 /* software control register */
++#define BIG_SUR_GE_UPC_REG_OFFSET 32 /* unserviced packet count register */
++#define BIG_SUR_GE_PCT_REG_OFFSET 36 /* packet count threshold register */
++#define BIG_SUR_GE_PWB_REG_OFFSET 40 /* packet wait bound register */
++#define BIG_SUR_GE_IS_REG_OFFSET 44 /* interrupt status register */
++#define BIG_SUR_GE_IE_REG_OFFSET 48 /* interrupt enable register */
++
++#define BIG_SUR_GE_RESET_MASK 0x0000000A
++
++/* Buffer Descriptor Control */
++
++#define BIG_SUR_GE_DEVICE_STATUS_OFFSET 0
++#define BIG_SUR_GE_CONTROL_OFFSET 1
++#define BIG_SUR_GE_SOURCE_OFFSET 2
++#define BIG_SUR_GE_DESTINATION_OFFSET 3
++#define BIG_SUR_GE_LENGTH_OFFSET 4
++#define BIG_SUR_GE_STATUS_OFFSET 5
++#define BIG_SUR_GE_NEXT_PTR_OFFSET 6
++#define BIG_SUR_GE_ID_OFFSET 7
++#define BIG_SUR_GE_FLAGS_OFFSET 8
++#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET 9
++
++#define BIG_SUR_GE_FLAGS_LOCKED_MASK 1
++
++#define xbuf_descriptor_init(base) \
++{ \
++ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0); \
++ (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \
++}
++
++#define xbuf_descriptor_GetControl(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET))
++
++#define xbuf_descriptor_SetControl(base, Control) \
++ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control)
++
++#define xbuf_descriptor_IsLastControl(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \
++ BIG_SUR_GE_CONTROL_LAST_BD_MASK)
++
++#define xbuf_descriptor_SetLast(base) \
++ (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK)
++
++#define xbuf_descriptor_GetSrcAddress(base) \
++ ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET)))
++
++#define xbuf_descriptor_SetSrcAddress(base, Source) \
++ (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source)
++
++#define xbuf_descriptor_GetDestAddress(base) \
++ ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET)))
++
++#define xbuf_descriptor_SetDestAddress(base, Destination) \
++ (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination)
++
++#define xbuf_descriptor_GetLength(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) - \
++ *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET))
++
++#define xbuf_descriptor_SetLength(base, Length) \
++{ \
++ (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length)); \
++ (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
++}
++
++#define xbuf_descriptor_GetStatus(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET))
++
++#define xbuf_descriptor_SetStatus(base, Status) \
++ (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status)
++
++#define xbuf_descriptor_IsLastStatus(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \
++ BIG_SUR_GE_STATUS_LAST_BD_MASK)
++
++#define xbuf_descriptor_GetDeviceStatus(base) \
++ ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET)))
++
++#define xbuf_descriptor_SetDeviceStatus(base, Status) \
++ (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status)
++
++#define xbuf_descriptor_GetNextPtr(base) \
++ (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET))
++
++#define xbuf_descriptor_SetNextPtr(base, NextPtr) \
++ (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr)
++
++#define xbuf_descriptor_GetId(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET))
++
++#define xbuf_descriptor_SetId(base, Id) \
++ (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id)
++
++#define xbuf_descriptor_GetFlags(base) \
++ (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET))
++
++#define xbuf_descriptor_SetFlags(base, Flags) \
++ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags)
++
++#define xbuf_descriptor_Lock(base) \
++ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define xbuf_descriptor_Unlock(base) \
++ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define xbuf_descriptor_IsLocked(base) \
++ (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */
++#define BIG_SUR_GE_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */
++#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */
++#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */
++#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */
++#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */
++#define BIG_SUR_GE_DMACR_LAST_BD_MASK BIG_SUR_GE_CONTROL_LAST_BD_MASK /* last buffer */
++#define BIG_SUR_GE_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */
++#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */
++#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */
++#define BIG_SUR_GE_DMASR_LAST_BD_MASK BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */
++#define BIG_SUR_GE_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */
++#define BIG_SUR_GE_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */
++#define BIG_SUR_GE_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */
++#define BIG_SUR_GE_IXR_PKT_DONE_MASK 0x4UL /* packet done */
++#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */
++#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */
++#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable
++ acknowledge occurred */
++#define BIG_SUR_GEIXR_SG_END_MASK 0x40UL /* last buffer descriptor
++ disabled scatter gather */
++#define BIG_SUR_GEIXR_BD_MASK 0x80UL /* buffer descriptor done */
++
++/* BD control */
++#define BIG_SUR_GE_DFT_SEND_BD_MASK (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \
++ BIG_SUR_GEDMACR_DEST_LOCAL_MASK)
++#define BIG_SUR_GE_DFT_RECV_BD_MASK (BIG_SUR_GEDMACR_DEST_INCR_MASK | \
++ BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK)
++
++/* Interrupts */
++#define BIG_SUR_GE_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */
++#define BIG_SUR_GE_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */
++#define BIG_SUR_GE_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */
++#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */
++#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */
++
++#define BIG_SUR_GE_IPIF_DMA_DFT_MASK (BIG_SUR_GE_IPIF_SEND_DMA_MASK | \
++ BIG_SUR_GE_IPIF_RECV_DMA_MASK | \
++ BIG_SUR_GE_IPIF_EMAC_MASK | \
++ BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \
++ BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++
++#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK (BIG_SUR_GE_IPIF_EMAC_MASK | \
++ BIG_SUR_GE_IPIF_SEND_FIFO_MASK | \
++ BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++
++#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */
++
++/* a mask for all transmit interrupts, used in polled mode */
++#define BIG_SUR_GE_EIR_XMIT_ALL_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \
++ BIG_SUR_GE_EIR_XMIT_ERROR_MASK | \
++ BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK | \
++ BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK)
++
++/* a mask for all receive interrupts, used in polled mode */
++#define BIG_SUR_GE_EIR_RECV_ALL_MASK (BIG_SUR_GE_EIR_RECV_DONE_MASK | \
++ BIG_SUR_GE_EIR_RECV_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK | \
++ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \
++ BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \
++ BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \
++ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
++
++/* a default interrupt mask for scatter-gather DMA operation */
++#define BIG_SUR_GE_EIR_DFT_SG_MASK (BIG_SUR_GE_EIR_RECV_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK | \
++ BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK | \
++ BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK | \
++ BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK | \
++ BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK | \
++ BIG_SUR_GE_EIR_RECV_COLLISION_MASK | \
++ BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK | \
++ BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
++
++/* a default interrupt mask for non-DMA operation (direct FIFOs) */
++#define BIG_SUR_GE_EIR_DFT_FIFO_MASK (BIG_SUR_GE_EIR_XMIT_DONE_MASK | \
++ BIG_SUR_GE_EIR_RECV_DONE_MASK | \
++ BIG_SUR_GE_EIR_DFT_SG_MASK)
++
++#define BIG_SUR_GE_DMA_SG_INTR_MASK (BIG_SUR_GEIXR_DMA_ERROR_MASK | \
++ BIG_SUR_GEIXR_PKT_THRESHOLD_MASK | \
++ BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK | \
++ BIG_SUR_GEIXR_SG_END_MASK)
++
++#endif
+diff -urN --ignore-space-change kernel.org/drivers/net/declance.c linux-mips/drivers/net/declance.c
+--- kernel.org/drivers/net/declance.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/declance.c 2006-01-10 11:21:38.000000000 +0000
+@@ -704,8 +704,8 @@
+ return IRQ_HANDLED;
+ }
+
+-static irqreturn_t
+-lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs)
++static irqreturn_t lance_interrupt(const int irq, void *dev_id,
++ struct pt_regs *regs)
+ {
+ struct net_device *dev = (struct net_device *) dev_id;
+ struct lance_private *lp = netdev_priv(dev);
+@@ -1255,7 +1255,7 @@
+ return 0;
+
+ err_out_free_dev:
+- kfree(dev);
++ free_netdev(dev);
+
+ err_out:
+ return ret;
+@@ -1301,6 +1301,7 @@
+ while (root_lance_dev) {
+ struct net_device *dev = root_lance_dev;
+ struct lance_private *lp = netdev_priv(dev);
++
+ unregister_netdev(dev);
+ #ifdef CONFIG_TC
+ if (lp->slot >= 0)
+diff -urN --ignore-space-change kernel.org/drivers/net/gt64240eth.c linux-mips/drivers/net/gt64240eth.c
+--- kernel.org/drivers/net/gt64240eth.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/gt64240eth.c 2006-01-10 11:21:38.000000000 +0000
+@@ -0,0 +1,1672 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2001 Patton Electronics Company
++ * Copyright (C) 2002 Momentum Computer
++ *
++ * Copyright 2000 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ * stevel at mvista.com or support at mvista.com
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
++ *
++ * Modified for the Gallileo/Marvell GT-64240 Communication Controller.
++ *
++ * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added
++ * Manish Lachwani (lachwani at pmc-sierra.com) - 09/16/2003
++ *
++ * Modified for later version of Linux 2.4 kernel
++ * Manish Lachwani (lachwani at pmc-sierra.com) - 04/29/2004
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/string.h>
++#include <linux/timer.h>
++#include <linux/errno.h>
++#include <linux/in.h>
++#include <linux/ioport.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/skbuff.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/mii.h>
++
++#include <asm/irq.h>
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#define DESC_DATA_BE 1
++
++#include "gt64240eth.h"
++
++// enable this port (set hash size to 1/2K)
++//- #define PORT_CONFIG pcrHS
++#define PORT_CONFIG (pcrHS | pcrHD)
++//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1<<pcrLPBKBit);
++
++// clear all the MIB ctr regs
++#define EXT_CONFIG_CLEAR (pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen | pcxrPRIOrxOverride | pcxrRMIIen)
++
++/*
++ * _debug level:
++ * <= 2 none.
++ * > 2 some warnings such as queue full, .....
++ * > 3 lots of change-of-state messages.
++ * > 4 EXTENSIVE data/descriptor dumps.
++ */
++
++#ifdef GT64240_DEBUG
++static int gt64240_debug = GT64240_DEBUG;
++#else
++static int gt64240_debug = 0;
++#endif
++
++static int debug = -1;
++
++#define GT64240_MSG_ENABLE (NETIF_MSG_DRV | \
++ NETIF_MSG_PROBE | \
++ NETIF_MSG_LINK)
++
++
++/********************************************************/
++
++// prototypes
++static void gt64240_delay(int msec);
++static int gt64240_add_hash_entry(struct net_device *dev,
++ unsigned char *addr);
++static void read_mib_counters(struct gt64240_private *gp);
++static void dump_MII(struct net_device *dev);
++static void dump_tx_desc(struct net_device *dev, int i);
++static void dump_rx_desc(struct net_device *dev, int i);
++static void dump_hw_addr(unsigned char *addr_str);
++static void update_stats(struct gt64240_private *gp);
++static void abort(struct net_device *dev, u32 abort_bits);
++static void hard_stop(struct net_device *dev);
++static void enable_ether_irq(struct net_device *dev);
++static void disable_ether_irq(struct net_device *dev);
++static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num);
++static void reset_tx(struct net_device *dev);
++static void reset_rx(struct net_device *dev);
++static int gt64240_init(struct net_device *dev);
++static int gt64240_open(struct net_device *dev);
++static int gt64240_close(struct net_device *dev);
++static int gt64240_tx(struct sk_buff *skb, struct net_device *dev);
++#ifdef GT64240_NAPI
++static int gt64240_poll(struct net_device *dev, int *budget);
++static int gt64240_rx(struct net_device *dev, u32 status, int budget);
++#else
++static int gt64240_rx(struct net_device *dev, u32 status);
++#endif
++static void gt64240_tx_timeout(struct net_device *dev);
++static void gt64240_set_rx_mode(struct net_device *dev);
++static struct net_device_stats *gt64240_get_stats(struct net_device *dev);
++
++extern char *__init prom_getcmdline(void);
++extern int prom_get_mac_addrs(unsigned char
++ station_addr[NUM_INTERFACES][6]);
++
++static char version[] __devinitdata =
++ "gt64240eth.o: version 0.1, <www.patton.com>\n";
++
++// PHY device addresses
++static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa };
++
++// Need real Ethernet addresses -- in parse_mac_addr_options(),
++// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline().
++static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = {
++ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05},
++ {0x01, 0x02, 0x03, 0x04, 0x05, 0x06},
++ {0x02, 0x03, 0x04, 0x05, 0x06, 0x07}
++};
++
++static int max_interrupt_work = 32;
++
++/*
++ * Base address and interupt of the GT64240 ethernet controllers
++ */
++static struct {
++ unsigned int port;
++ int irq;
++} gt64240_iflist[NUM_INTERFACES] = {
++ {
++ GT64240_ETH0_BASE, 8}, {
++ GT64240_ETH1_BASE, 8}, {
++ GT64240_ETH2_BASE, 8}
++};
++
++static void gt64240_delay(int ms)
++{
++ if (in_interrupt())
++ return;
++ else {
++ current->state = TASK_INTERRUPTIBLE;
++ schedule_timeout(ms * HZ / 1000);
++ }
++}
++
++unsigned char prom_mac_addr_base[6];
++
++int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6])
++{
++ memcpy(station_addr[0], prom_mac_addr_base, 6);
++ memcpy(station_addr[1], prom_mac_addr_base, 6);
++ memcpy(station_addr[2], prom_mac_addr_base, 6);
++
++ station_addr[1][5] += 1;
++ station_addr[2][5] += 2;
++
++ return 0;
++}
++
++void parse_mac_addr_options(void)
++{
++ prom_get_mac_addrs(gt64240_station_addr);
++}
++
++static int read_MII(struct net_device *dev, int phy, int reg)
++{
++ int timedout = 20;
++ u32 smir = smirOpCode | (phy << smirPhyAdBit) |
++ (reg << smirRegAdBit);
++
++ // wait for last operation to complete
++ while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) {
++ // snooze for 1 msec and check again
++ gt64240_delay(1);
++
++ if (--timedout == 0) {
++ printk("%s: read_MII busy timeout!!\n", dev->name);
++ return -1;
++ }
++ }
++
++ GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
++
++ timedout = 20;
++ // wait for read to complete
++ while (!
++ ((smir =
++ GT64240_READ(GT64240_ETH_SMI_REG)) & smirReadValid)) {
++ // snooze for 1 msec and check again
++ gt64240_delay(1);
++
++ if (--timedout == 0) {
++ printk("%s: read_MII timeout!!\n", dev->name);
++ return -1;
++ }
++ }
++
++ return (int) (smir & smirDataMask);
++}
++
++static void gp_get_drvinfo (struct net_device *dev,
++ struct ethtool_drvinfo *info)
++{
++ strcpy(info->driver, "gt64260");
++ strcpy(info->version, version);
++}
++
++static int gp_get_settings(struct net_device *dev,
++ struct ethtool_cmd *cmd)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int rc;
++
++ spin_lock_irq(&gp->lock);
++ rc = mii_ethtool_gset(&gp->mii_if, cmd);
++ spin_unlock_irq(&gp->lock);
++ return rc;
++}
++
++static int gp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int rc;
++
++ spin_lock_irq(&gp->lock);
++ rc = mii_ethtool_sset(&gp->mii_if, cmd);
++ spin_unlock_irq(&gp->lock);
++ return rc;
++}
++
++static int gp_nway_reset(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ return mii_nway_restart(&gp->mii_if);
++}
++
++static u32 gp_get_link(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ return mii_link_ok(&gp->mii_if);
++}
++
++static u32 gp_get_msglevel(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ return gp->msg_enable;
++}
++
++static void gp_set_msglevel(struct net_device *dev, u32 value)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ gp->msg_enable = value;
++}
++
++static struct ethtool_ops gp_ethtool_ops = {
++ .get_drvinfo = gp_get_drvinfo,
++ .get_settings = gp_get_settings,
++ .set_settings = gp_set_settings,
++ .nway_reset = gp_nway_reset,
++ .get_link = gp_get_link,
++ .get_msglevel = gp_get_msglevel,
++ .set_msglevel = gp_set_msglevel,
++};
++
++static int gt64240_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ struct mii_ioctl_data *data =
++ (struct mii_ioctl_data *) &rq->ifr_data;
++ int retval;
++
++ if (!netif_running(dev))
++ return -EINVAL;
++
++ spin_lock_irq(&gp->lock);
++ retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL);
++ spin_unlock_irq(&gp->lock);
++
++ return retval;
++}
++
++static void dump_tx_desc(struct net_device *dev, int i)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ gt64240_td_t *td = &gp->tx_ring[i];
++
++ printk("%s:tx[%d]: self=%p cmd=%08x, cnt=%4d. bufp=%08x, next=%08x\n",
++ dev->name, i, td, td->cmdstat, td->byte_cnt, td->buff_ptr,
++ td->next);
++}
++
++static void dump_rx_desc(struct net_device *dev, int i)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ gt64240_rd_t *rd = &gp->rx_ring[i];
++
++ printk("%s:rx_dsc[%d]: self=%p cst=%08x,size=%4d. cnt=%4d. "
++ "bufp=%08x, next=%08x\n",
++ dev->name, i, rd, rd->cmdstat, rd->buff_sz, rd->byte_cnt,
++ rd->buff_ptr, rd->next);
++}
++
++// These routines work, just disabled to avoid compile warnings
++static void write_MII(struct net_device *dev, int phy, int reg, int data)
++{
++ u32 smir = (phy << smirPhyAdBit) | (reg << smirRegAdBit) | data;
++ int timedout = 20;
++
++ // wait for last operation to complete
++ while (GT64240_READ(GT64240_ETH_SMI_REG) & smirBusy) {
++ // snooze for 1 msec and check again
++ gt64240_delay(1);
++
++ if (--timedout == 0) {
++ printk("%s: write_MII busy timeout!!\n",
++ dev->name);
++ return;
++ }
++ }
++
++ GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
++}
++
++static void dump_MII(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int i, val;
++
++ for (i = 0; i < 7; i++) {
++ if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
++ printk("%s: MII Reg %d=%x\n", dev->name, i, val);
++ }
++ for (i = 16; i < 21; i++) {
++ if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
++ printk("%s: MII Reg %d=%x\n", dev->name, i, val);
++ }
++}
++
++
++static void dump_hw_addr(unsigned char *addr_str)
++{
++ int i;
++ for (i = 0; i < 6; i++) {
++ printk("%2.2x", addr_str[i]);
++ printk(i < 5 ? ":" : "\n");
++ }
++}
++
++static int gt64240_add_hash_entry(struct net_device *dev,
++ unsigned char *addr)
++{
++ static unsigned char swapped[256];
++ struct gt64240_private *gp;
++ u32 value1, value0, *entry;
++ unsigned char hash_ea[6];
++ static int flag = 0;
++ u16 hashResult;
++ int i;
++
++ if (flag == 0) { /* Create table to swap bits in a byte */
++ flag = 1;
++ for (i = 0; i < 256; i++) {
++ swapped[i] = (i & 0x01) << 7;
++ swapped[i] |= (i & 0x02) << 5;
++ swapped[i] |= (i & 0x04) << 3;
++ swapped[i] |= (i & 0x08) << 1;
++ swapped[i] |= (i & 0x10) >> 1;
++ swapped[i] |= (i & 0x20) >> 3;
++ swapped[i] |= (i & 0x40) >> 5;
++ swapped[i] |= (i & 0x80) >> 7;
++ }
++ }
++
++ for (i = 0; i < 6; i++) { /* swap bits from mac to create hash mac */
++ hash_ea[i] = swapped[addr[i]];
++ }
++
++ gp = netdev_priv(dev);
++
++ /* create hash entry address */
++ hashResult = (((hash_ea[5] >> 2) & 0x3F) << 9) & 0x7E00;
++ hashResult |= ((hash_ea[4] & 0x7F) << 2) | (hash_ea[5] & 0x03);
++ hashResult ^=
++ ((hash_ea[3] & 0xFF) << 1) | ((hash_ea[4] >> 7) & 0x01);
++ hashResult ^= ((hash_ea[1] & 0x01) << 8) | (hash_ea[2] & 0xFF);
++
++ value0 = hteValid | hteRD; /* Create hash table entry value */
++ value0 |= (u32) addr[0] << 3;
++ value0 |= (u32) addr[1] << 11;
++ value0 |= (u32) addr[2] << 19;
++ value0 |= ((u32) addr[3] & 0x1f) << 27;
++
++ value1 = ((u32) addr[3] >> 5) & 0x07;
++ value1 |= (u32) addr[4] << 3;
++ value1 |= (u32) addr[5] << 11;
++
++ /* Inset entry value into hash table */
++ for (i = 0; i < HASH_HOP_NUMBER; i++) {
++ entry = (u32 *) ((u32) gp->hash_table +
++ (((u32) hashResult & 0x07ff) << 3));
++ if ((*entry & hteValid) && !(*entry & hteSkip)) {
++ hashResult += 2; /* oops, occupied, go to next entry */
++ } else {
++#ifdef __LITTLE_ENDIAN
++ entry[1] = value1;
++ entry[0] = value0;
++#else
++ entry[0] = value1;
++ entry[1] = value0;
++#endif
++ break;
++ }
++ }
++ if (i >= HASH_HOP_NUMBER) {
++ printk("%s: gt64240_add_hash_entry expired!\n", dev->name);
++ return (-1);
++ }
++ return (0);
++}
++
++
++static void read_mib_counters(struct gt64240_private *gp)
++{
++ u32 *mib_regs = (u32 *) & gp->mib;
++ int i;
++
++ for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++)
++ mib_regs[i] =
++ GT64240ETH_READ(gp,
++ GT64240_ETH_MIB_COUNT_BASE +
++ i * sizeof(u32));
++}
++
++
++static void update_stats(struct gt64240_private *gp)
++{
++ mib_counters_t *mib = &gp->mib;
++ struct net_device_stats *stats = &gp->stats;
++
++ read_mib_counters(gp);
++
++ stats->rx_packets = mib->totalFramesReceived;
++ stats->tx_packets = mib->framesSent;
++ stats->rx_bytes = mib->totalByteReceived;
++ stats->tx_bytes = mib->byteSent;
++ stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
++ //the tx error counters are incremented by the ISR
++ //rx_dropped incremented by gt64240_rx
++ //tx_dropped incremented by gt64240_tx
++ stats->multicast = mib->multicastFramesReceived;
++ // collisions incremented by gt64240_tx_complete
++ stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
++ // The RxError condition means the Rx DMA encountered a
++ // CPU owned descriptor, which, if things are working as
++ // they should, means the Rx ring has overflowed.
++ stats->rx_over_errors = mib->macRxError;
++ stats->rx_crc_errors = mib->cRCError;
++}
++
++static void abort(struct net_device *dev, u32 abort_bits)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int timedout = 100; // wait up to 100 msec for hard stop to complete
++
++ if (gt64240_debug > 3)
++ printk("%s: abort\n", dev->name);
++
++ // Return if neither Rx or Tx abort bits are set
++ if (!(abort_bits & (sdcmrAR | sdcmrAT)))
++ return;
++
++ // make sure only the Rx/Tx abort bits are set
++ abort_bits &= (sdcmrAR | sdcmrAT);
++
++ spin_lock(&gp->lock);
++
++ // abort any Rx/Tx DMA immediately
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits);
++
++ if (gt64240_debug > 3)
++ printk("%s: abort: SDMA cmd = %x/%x\n",
++ dev->name, abort_bits, GT64240ETH_READ(gp,
++ GT64240_ETH_SDMA_COMM));
++
++ // wait for abort to complete
++ while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) {
++ // snooze for 20 msec and check again
++ gt64240_delay(1);
++
++ if (--timedout == 0) {
++ printk("%s: abort timeout!!\n", dev->name);
++ break;
++ }
++ }
++
++ spin_unlock(&gp->lock);
++}
++
++
++static void hard_stop(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++
++ if (gt64240_debug > 3)
++ printk("%s: hard stop\n", dev->name);
++
++ disable_ether_irq(dev);
++
++ abort(dev, sdcmrAR | sdcmrAT);
++
++ // disable port
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0);
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_hard_stop: Port Config=%x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_PORT_CONFIG));
++
++}
++
++static void gt64240_tx_complete(struct net_device *dev, u32 status)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int nextOut, cdp;
++ gt64240_td_t *td;
++ u32 cmdstat;
++
++ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
++ - gp->tx_ring_dma) / sizeof(gt64240_td_t);
++
++ if (gt64240_debug > 3) { /*+prk17aug01 */
++ nextOut = gp->tx_next_out;
++ printk
++ ("%s: tx_complete: TX_PTR0=0x%08x, cdp=%d. nextOut=%d.\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_CURR_TX_DESC_PTR0),
++ cdp, nextOut);
++ td = &gp->tx_ring[nextOut];
++ }
++
++/*** NEED to check and CLEAR these errors every time thru here: ***/
++ if (gt64240_debug > 2) {
++ if (GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE))
++ printk
++ ("%s: gt64240_tx_complete: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
++ dev->name,
++ GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
++ GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
++ GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
++ GT64240_WRITE(COMM_UNIT_INTERRUPT_CAUSE, 0);
++ }
++ // Continue until we reach the current descriptor pointer
++ for (nextOut = gp->tx_next_out; nextOut != cdp;
++ nextOut = (nextOut + 1) % TX_RING_SIZE) {
++
++ if (--gp->intr_work_done == 0)
++ break;
++
++ td = &gp->tx_ring[nextOut];
++ cmdstat = td->cmdstat;
++
++ if (cmdstat & (u32) txOwn) {
++ // DMA is not finished writing descriptor???
++ // Leave and come back later to pick-up where we left off.
++ break;
++ }
++ // increment Tx error stats
++ if (cmdstat & (u32) txErrorSummary) {
++ if (gt64240_debug > 2)
++ printk
++ ("%s: tx_complete: Tx error, cmdstat = %x\n",
++ dev->name, cmdstat);
++ gp->stats.tx_errors++;
++ if (cmdstat & (u32) txReTxLimit)
++ gp->stats.tx_aborted_errors++;
++ if (cmdstat & (u32) txUnderrun)
++ gp->stats.tx_fifo_errors++;
++ if (cmdstat & (u32) txLateCollision)
++ gp->stats.tx_window_errors++;
++ }
++
++ if (cmdstat & (u32) txCollision)
++ gp->stats.collisions +=
++ (unsigned long) ((cmdstat & txReTxCntMask) >>
++ txReTxCntBit);
++
++ // Wake the queue if the ring was full
++ if (gp->tx_full) {
++ gp->tx_full = 0;
++ if (gp->last_psr & psrLink) {
++ netif_wake_queue(dev);
++ }
++ }
++ // decrement tx ring buffer count
++ if (gp->tx_count)
++ gp->tx_count--;
++
++ // free the skb
++ if (gp->tx_skbuff[nextOut]) {
++ if (gt64240_debug > 3)
++ printk
++ ("%s: tx_complete: good Tx, skb=%p\n",
++ dev->name, gp->tx_skbuff[nextOut]);
++ dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
++ gp->tx_skbuff[nextOut] = NULL;
++ } else {
++ printk("%s: tx_complete: no skb!\n", dev->name);
++ }
++ }
++
++ gp->tx_next_out = nextOut;
++
++ if ((status & icrTxEndLow) && gp->tx_count != 0) {
++ // we must restart the DMA
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++ sdcmrERD | sdcmrTXDL);
++ }
++}
++
++static irqreturn_t gt64240_interrupt(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct net_device *dev = (struct net_device *) dev_id;
++ struct gt64240_private *gp = netdev_priv(dev);
++ u32 status;
++
++ if (dev == NULL) {
++ printk("%s: isr: null dev ptr\n", dev->name);
++ return IRQ_NONE;
++ }
++
++ spin_lock(&gp->lock);
++
++ if (gt64240_debug > 3)
++ printk("%s: isr: entry\n", dev->name);
++
++ gp->intr_work_done = max_interrupt_work;
++
++ while (gp->intr_work_done > 0) {
++
++ status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
++#ifdef GT64240_NAPI
++ /* dont ack Rx interrupts */
++ if (!(status & icrRxBuffer))
++ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++#else
++ // ACK interrupts
++ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++#endif
++
++ if (gt64240_debug > 3)
++ printk("%s: isr: work=%d., icr=%x\n", dev->name,
++ gp->intr_work_done, status);
++
++ if ((status & icrEtherIntSum) == 0) {
++ if (!(status &
++ (icrTxBufferLow | icrTxBufferHigh |
++ icrRxBuffer))) {
++ /* exit from the while() loop */
++ break;
++ }
++ }
++
++ if (status & icrMIIPhySTC) {
++ u32 psr =
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS);
++ if (gp->last_psr != psr) {
++ printk("%s: port status: 0x%08x\n",
++ dev->name, psr);
++ printk
++ ("%s: %s MBit/s, %s-duplex, flow-control %s, link is %s,\n",
++ dev->name,
++ psr & psrSpeed ? "100" : "10",
++ psr & psrDuplex ? "full" : "half",
++ psr & psrFctl ? "disabled" :
++ "enabled",
++ psr & psrLink ? "up" : "down");
++ printk
++ ("%s: TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n",
++ dev->name,
++ psr & psrTxLow ? "running" :
++ "stopped",
++ psr & psrTxHigh ? "running" :
++ "stopped",
++ psr & psrTxInProg ? "on" : "off");
++
++ if ((psr & psrLink) && !gp->tx_full &&
++ netif_queue_stopped(dev)) {
++ printk
++ ("%s: isr: Link up, waking queue.\n",
++ dev->name);
++ netif_wake_queue(dev);
++ } else if (!(psr & psrLink)
++ && !netif_queue_stopped(dev)) {
++ printk
++ ("%s: isr: Link down, stopping queue.\n",
++ dev->name);
++ netif_stop_queue(dev);
++ }
++
++ gp->last_psr = psr;
++ }
++ }
++
++ if (status & (icrTxBufferLow | icrTxEndLow))
++ gt64240_tx_complete(dev, status);
++
++ if (status & icrRxBuffer) {
++#ifdef GT64240_NAPI
++ if (netif_rx_schedule_prep(dev)) {
++ disable_ether_irq(dev);
++ __netif_rx_schedule(dev);
++ }
++#else
++ gt64240_rx(dev, status);
++#endif
++ }
++ // Now check TX errors (RX errors were handled in gt64240_rx)
++ if (status & icrTxErrorLow) {
++ printk("%s: isr: Tx resource error\n", dev->name);
++ }
++
++ if (status & icrTxUdr) {
++ printk("%s: isr: Tx underrun error\n", dev->name);
++ }
++ }
++
++ if (gp->intr_work_done == 0) {
++ // ACK any remaining pending interrupts
++ GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++ if (gt64240_debug > 3)
++ printk("%s: isr: hit max work\n", dev->name);
++ }
++
++ if (gt64240_debug > 3)
++ printk("%s: isr: exit, icr=%x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_INT_CAUSE));
++
++ spin_unlock(&gp->lock);
++
++ return IRQ_HANDLED;
++}
++
++static void enable_ether_irq(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ u32 intMask;
++
++ intMask =
++ icrTxBufferLow | icrTxEndLow | icrTxErrorLow |
++ icrTxBufferHigh | icrTxEndHigh | icrTxErrorHigh | icrTxUdr |
++ icrRxBuffer | icrRxOVR | icrRxError | icrMIIPhySTC |
++ icrEtherIntSum;
++
++
++//- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */
++ // unmask device interrupts:
++ GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask);
++
++ // now route ethernet interrupts to GT PCI1 (eth0 and eth1 will be
++ // sharing it).
++ intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
++ intMask |= 1 << gp->port_num;
++ MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
++}
++
++static void disable_ether_irq(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ u32 intMask;
++
++ intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
++ intMask &= ~(1 << gp->port_num);
++ MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
++
++ // mask all device interrupts:
++ GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0);
++}
++
++/*
++ * Probe for a GT64240 ethernet controller.
++ */
++static int __init gt64240_probe(void)
++{
++ int found = 0;
++ int i;
++
++ parse_mac_addr_options();
++
++ for (i = 0; i < NUM_INTERFACES; i++) {
++ unsigned long base_addr = gt64240_iflist[i].port;
++
++ if (check_region(base_addr, GT64240_ETH_IO_SIZE)) {
++ printk("gt64240_probe: ioaddr 0x%lx taken?\n",
++ base_addr);
++ continue;
++ }
++
++ if (gt64240_probe1(base_addr, gt64240_iflist[i].irq, i) == 0) {
++ /*
++ * Does not seem to be the "traditional" way folks do
++ * this, but I want to init both eth ports if at all
++ * possible!
++ *
++ * So, until I find out the "correct" way to do this:
++ */
++ if (++found == NUM_INTERFACES) /* That's all of them */
++ return 0;
++ }
++ }
++
++ if (found)
++ return 0; /* as long as we found at least one! */
++
++ return -ENODEV;
++}
++
++module_init(gt64240_probe);
++
++static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num)
++{
++ struct net_device *dev = NULL;
++ static unsigned version_printed = 0;
++ struct gt64240_private *gp = NULL;
++ int retval;
++ u32 cpuConfig;
++
++ dev = alloc_etherdev(sizeof(struct gt64240_private));
++ if (!dev)
++ return -ENOMEM;
++
++ if (irq < 0) {
++ printk
++ ("gt64240_probe1: irq unknown - probing not supported\n");
++ return -ENODEV;
++ }
++#if 1 /* KLUDGE Alert: no check on return value: */
++ if (!request_region(ioaddr, GT64240_ETH_IO_SIZE, "gt64240eth"))
++ printk("*** request_region() failed!\n");
++#endif
++
++ cpuConfig = GT64240_READ(CPU_CONFIGURATION);
++ printk("gt64240_probe1: cpu in %s-endian mode\n",
++ (cpuConfig & (1 << 12)) ? "little" : "big");
++
++ printk("%s: GT64240 found at ioaddr 0x%lx, irq %d.\n",
++ dev->name, ioaddr, irq);
++
++ if (gt64240_debug && version_printed++ == 0)
++ printk("%s: %s", dev->name, version);
++
++ /* private struct aligned and zeroed by init_etherdev */
++ /* Fill in the 'dev' fields. */
++ dev->base_addr = ioaddr;
++ dev->irq = irq;
++ memcpy(dev->dev_addr, gt64240_station_addr[port_num],
++ sizeof(dev->dev_addr));
++
++ printk("%s: HW Address ", dev->name);
++ dump_hw_addr(dev->dev_addr);
++
++ gp = dev->priv;
++
++ gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug);
++ gp->port_num = port_num;
++ gp->io_size = GT64240_ETH_IO_SIZE;
++ gp->port_offset = port_num * GT64240_ETH_IO_SIZE;
++ gp->phy_addr = gt64240_phy_addr[port_num];
++
++ printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num);
++
++#ifdef GT64240_NAPI
++ printk("Rx NAPI supported \n");
++#endif
++
++/* MII Initialization */
++ gp->mii_if.dev = dev;
++ gp->mii_if.phy_id = dev->base_addr;
++ gp->mii_if.mdio_read = read_MII;
++ gp->mii_if.mdio_write = write_MII;
++ gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE);
++
++ // Allocate Rx and Tx descriptor rings
++ if (gp->rx_ring == NULL) {
++ // All descriptors in ring must be 16-byte aligned
++ gp->rx_ring = dma_alloc_noncoherent(NULL,
++ sizeof(gt64240_rd_t) * RX_RING_SIZE +
++ sizeof(gt64240_td_t) * TX_RING_SIZE,
++ &gp->rx_ring_dma, GFP_KERNEL);
++ if (gp->rx_ring == NULL) {
++ retval = -ENOMEM;
++ goto free_region;
++ }
++
++ gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE);
++ gp->tx_ring_dma =
++ gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE;
++ }
++ // Allocate the Rx Data Buffers
++ if (gp->rx_buff == NULL) {
++ gp->rx_buff = dma_alloc_coherent(NULL,
++ PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma,
++ GFP_KERNEL);
++ if (gp->rx_buff == NULL) {
++ dma_free_noncoherent(NULL,
++ sizeof(gt64240_rd_t) * RX_RING_SIZE +
++ sizeof(gt64240_td_t) * TX_RING_SIZE,
++ gp->rx_ring, gp->rx_ring_dma);
++ retval = -ENOMEM;
++ goto free_region;
++ }
++ }
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_probe1, rx_ring=%p, tx_ring=%p\n",
++ dev->name, gp->rx_ring, gp->tx_ring);
++
++ // Allocate Rx Hash Table
++ if (gp->hash_table == NULL) {
++ gp->hash_table = dma_alloc_coherent(NULL,
++ RX_HASH_TABLE_SIZE, &gp->hash_table_dma,
++ GFP_KERNEL);
++ if (gp->hash_table == NULL) {
++ dma_free_noncoherent(NULL,
++ sizeof(gt64240_rd_t) * RX_RING_SIZE +
++ sizeof(gt64240_td_t) * TX_RING_SIZE,
++ gp->rx_ring, gp->rx_ring_dma);
++ dma_free_noncoherent(NULL, PKT_BUF_SZ * RX_RING_SIZE,
++ gp->rx_buff, gp->rx_buff_dma);
++ retval = -ENOMEM;
++ goto free_region;
++ }
++ }
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_probe1, hash=%p\n",
++ dev->name, gp->hash_table);
++
++ spin_lock_init(&gp->lock);
++
++ dev->open = gt64240_open;
++ dev->hard_start_xmit = gt64240_tx;
++ dev->stop = gt64240_close;
++ dev->get_stats = gt64240_get_stats;
++ dev->do_ioctl = gt64240_ioctl;
++ dev->set_multicast_list = gt64240_set_rx_mode;
++ dev->tx_timeout = gt64240_tx_timeout;
++ dev->watchdog_timeo = GT64240ETH_TX_TIMEOUT;
++
++#ifdef GT64240_NAPI
++ dev->poll = gt64240_poll;
++ dev->weight = 64;
++#endif
++ dev->ethtool_ops = &gp_ethtool_ops;
++
++ /* Fill in the fields of the device structure with ethernet values. */
++ return 0;
++
++free_region:
++ release_region(ioaddr, gp->io_size);
++ unregister_netdev(dev);
++ free_netdev(dev);
++ printk("%s: gt64240_probe1 failed. Returns %d\n",
++ dev->name, retval);
++ return retval;
++}
++
++
++static void reset_tx(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int i;
++
++ abort(dev, sdcmrAT);
++
++ for (i = 0; i < TX_RING_SIZE; i++) {
++ if (gp->tx_skbuff[i]) {
++ if (in_interrupt())
++ dev_kfree_skb_irq(gp->tx_skbuff[i]);
++ else
++ dev_kfree_skb(gp->tx_skbuff[i]);
++ gp->tx_skbuff[i] = NULL;
++ }
++//- gp->tx_ring[i].cmdstat = 0; // CPU owns
++ gp->tx_ring[i].cmdstat =
++ (u32) (txGenCRC | txEI | txPad | txFirst | txLast);
++ gp->tx_ring[i].byte_cnt = 0;
++ gp->tx_ring[i].buff_ptr = 0;
++ gp->tx_ring[i].next =
++ gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1);
++ if (gt64240_debug > 4)
++ dump_tx_desc(dev, i);
++ }
++ /* Wrap the ring. */
++ gp->tx_ring[i - 1].next = gp->tx_ring_dma;
++ if (gt64240_debug > 4)
++ dump_tx_desc(dev, i - 1);
++
++ // setup only the lowest priority TxCDP reg
++ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
++ gp->tx_ring_dma);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0); /* ROLLINS */
++//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0])); /* ROLLINS */
++
++ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0);
++
++ // init Tx indeces and pkt counter
++ gp->tx_next_in = gp->tx_next_out = 0;
++ gp->tx_count = 0;
++}
++
++static void reset_rx(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int i;
++
++ abort(dev, sdcmrAR);
++
++ for (i = 0; i < RX_RING_SIZE; i++) {
++ gp->rx_ring[i].next =
++ gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1);
++ gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ;
++ gp->rx_ring[i].buff_sz = PKT_BUF_SZ;
++ gp->rx_ring[i].byte_cnt = 0; /* just for debug printk's */
++ // Give ownership to device, set first and last, enable interrupt
++ gp->rx_ring[i].cmdstat =
++ (uint32_t) (rxFirst | rxLast | rxOwn | rxEI);
++ if (gt64240_debug > 4)
++ dump_rx_desc(dev, i);
++ }
++ /* Wrap the ring. */
++ gp->rx_ring[i - 1].next = gp->rx_ring_dma;
++ if (gt64240_debug > 4)
++ dump_rx_desc(dev, i - 1);
++
++ // Setup only the lowest priority RxFDP and RxCDP regs
++ for (i = 0; i < 4; i++) {
++ if (i == 0) {
++ GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0,
++ gp->rx_ring_dma);
++ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0,
++ gp->rx_ring_dma);
++ } else {
++ GT64240ETH_WRITE(gp,
++ GT64240_ETH_1ST_RX_DESC_PTR0 +
++ i * 4, 0);
++ GT64240ETH_WRITE(gp,
++ GT64240_ETH_CURR_RX_DESC_PTR0 +
++ i * 4, 0);
++ }
++ }
++
++ // init Rx NextOut index
++ gp->rx_next_out = 0;
++}
++
++
++static int gt64240_init(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++
++ if (gt64240_debug > 3) {
++ printk("%s: gt64240_init: dev=%p\n", dev->name, dev);
++ printk("%s: gt64240_init: scs0_lo=%04x, scs0_hi=%04x\n",
++ dev->name, GT64240_READ(0x008),
++ GT64240_READ(0x010));
++ printk("%s: gt64240_init: scs1_lo=%04x, scs1_hi=%04x\n",
++ dev->name, GT64240_READ(0x208),
++ GT64240_READ(0x210));
++ printk("%s: gt64240_init: scs2_lo=%04x, scs2_hi=%04x\n",
++ dev->name, GT64240_READ(0x018),
++ GT64240_READ(0x020));
++ printk("%s: gt64240_init: scs3_lo=%04x, scs3_hi=%04x\n",
++ dev->name, GT64240_READ(0x218),
++ GT64240_READ(0x220));
++ }
++ // Stop and disable Port
++ hard_stop(dev);
++
++ GT64240_WRITE(COMM_UNIT_INTERRUPT_MASK, 0x07070777); /*+prk21aug01 */
++ if (gt64240_debug > 2)
++ printk
++ ("%s: gt64240_init: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
++ dev->name, GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
++ GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
++ GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
++
++ // Set-up hash table
++ memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
++ gp->hash_mode = 0;
++ // Add a single entry to hash table - our ethernet address
++ gt64240_add_hash_entry(dev, dev->dev_addr);
++ // Set-up DMA ptr to hash table
++ GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma);
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Hash Tbl Ptr=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR));
++
++ // Setup Tx
++ reset_tx(dev);
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Curr Tx Desc Ptr0=%x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_CURR_TX_DESC_PTR0));
++
++ // Setup Rx
++ reset_rx(dev);
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: 1st/Curr Rx Desc Ptr0=%x/%x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_1ST_RX_DESC_PTR0),
++ GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0));
++
++ if (gt64240_debug > 3)
++ dump_MII(dev);
++
++ /* force a PHY reset -- self-clearing! */
++ write_MII(dev, gp->phy_addr, 0, 0x8000);
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: PhyAD=%x\n", dev->name,
++ GT64240_READ(GT64240_ETH_PHY_ADDR_REG));
++
++ // setup DMA
++ // We want the Rx/Tx DMA to write/read data to/from memory in
++ // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
++#ifdef DESC_DATA_BE
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG,
++ (0xf << sdcrRCBit) | sdcrRIFB | (3 <<
++ sdcrBSZBit));
++#else
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT |
++//- (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
++ (0xf << sdcrRCBit) | sdcrRIFB | (2 <<
++ sdcrBSZBit));
++#endif
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: SDMA Config=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG));
++
++#if 0
++ // start Rx DMA
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++#endif
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: SDMA Cmd =%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM));
++
++#if 1
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG);
++#endif
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Port Config=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++
++ /*
++ * Disable all Type-of-Service queueing. All Rx packets will be
++ * treated normally and will be sent to the lowest priority
++ * queue.
++ *
++ * Disable flow-control for now. FIX! support flow control?
++ */
++
++#if 1
++ // clear all the MIB ctr regs
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
++ EXT_CONFIG_CLEAR);
++ read_mib_counters(gp);
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
++ EXT_CONFIG_CLEAR | pcxrMIBclrMode);
++
++#endif
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Port Config Ext=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT));
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Port Command=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND));
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0);
++
++ netif_start_queue(dev);
++
++ /* enable the port */
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
++ (PORT_CONFIG | pcrEN));
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_init: Port Config=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++#if 1
++ // start Rx DMA
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++#endif
++
++
++ // enable interrupts
++ enable_ether_irq(dev);
++
++//--- gp->last_psr |= psrLink; /* KLUDGE ALERT */
++
++ // we should now be receiving frames
++ return 0;
++}
++
++
++static int gt64240_open(struct net_device *dev)
++{
++ int retval;
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_open: dev=%p\n", dev->name, dev);
++
++ if ((retval = request_irq(dev->irq, >64240_interrupt,
++ SA_SHIRQ, dev->name, dev))) {
++ printk("%s: unable to get IRQ %d\n", dev->name, dev->irq);
++
++ return retval;
++ }
++ // Initialize and startup the GT-64240 ethernet port
++ if ((retval = gt64240_init(dev))) {
++ printk("%s: error in gt64240_open\n", dev->name);
++ free_irq(dev->irq, dev);
++
++ return retval;
++ }
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_open: Initialization done.\n",
++ dev->name);
++
++ return 0;
++}
++
++static int gt64240_close(struct net_device *dev)
++{
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_close: dev=%p\n", dev->name, dev);
++
++ // stop the device
++ if (netif_device_present(dev)) {
++ netif_stop_queue(dev);
++ hard_stop(dev);
++ }
++
++ free_irq(dev->irq, dev);
++
++ return 0;
++}
++
++#ifdef GT64240_NAPI
++/*
++ * Function will release Tx skbs which are now complete
++ */
++static void gt64240_tx_fill(struct net_device *dev, u32 status)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ int nextOut, cdp;
++ gt64240_td_t *td;
++ u32 cmdstat;
++
++ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
++ - gp->tx_ring_dma) / sizeof(gt64240_td_t);
++
++ for (nextOut = gp->tx_next_out; nextOut != cdp;
++ nextOut = (nextOut + 1) % TX_RING_SIZE) {
++ if (--gp->intr_work_done == 0)
++ break;
++
++ td = &gp->tx_ring[nextOut];
++ cmdstat = td->cmdstat;
++
++ if (cmdstat & (u32) txOwn)
++ break;
++
++ if (gp->tx_full) {
++ gp->tx_full = 0;
++ if (gp->last_psr & psrLink) {
++ netif_wake_queue(dev);
++ }
++ }
++ // decrement tx ring buffer count
++ if (gp->tx_count)
++ gp->tx_count--;
++
++ // free the skb
++ if (gp->tx_skbuff[nextOut]) {
++ dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
++ gp->tx_skbuff[nextOut] = NULL;
++ }
++ }
++
++ gp->tx_next_out = nextOut;
++
++ if ((status & icrTxEndLow) && gp->tx_count != 0)
++ // we must restart the DMA
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++ sdcmrERD | sdcmrTXDL);
++}
++
++/*
++ * Main function for NAPI
++ */
++static int gt64240_poll(struct net_device *dev, int *budget)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ unsigned long flags;
++ int done = 1, orig_budget, work_done;
++ u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
++
++ spin_lock_irqsave(&gp->lock, flags);
++ gt64240_tx_fill(dev, status);
++
++ if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) !=
++ gp->rx_next_out) {
++ orig_budget = *budget;
++ if (orig_budget > dev->quota)
++ orig_budget = dev->quota;
++
++ work_done = gt64240_rx(dev, status, orig_budget);
++ *budget -= work_done;
++ dev->quota -= work_done;
++ if (work_done >= orig_budget)
++ done = 0;
++ if (done) {
++ __netif_rx_complete(dev);
++ enable_ether_irq(dev);
++ }
++ }
++
++ spin_unlock_irqrestore(&gp->lock, flags);
++
++ return (done ? 0 : 1);
++}
++#endif
++
++static int gt64240_tx(struct sk_buff *skb, struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ unsigned long flags;
++ int nextIn;
++
++ spin_lock_irqsave(&gp->lock, flags);
++
++ nextIn = gp->tx_next_in;
++
++ if (gt64240_debug > 3) {
++ printk("%s: gt64240_tx: nextIn=%d.\n", dev->name, nextIn);
++ }
++
++ if (gp->tx_count >= TX_RING_SIZE) {
++ printk("%s: Tx Ring full, pkt dropped.\n", dev->name);
++ gp->stats.tx_dropped++;
++ spin_unlock_irqrestore(&gp->lock, flags);
++ return 1;
++ }
++
++ if (!(gp->last_psr & psrLink)) {
++ printk("%s: gt64240_tx: Link down, pkt dropped.\n",
++ dev->name);
++ gp->stats.tx_dropped++;
++ spin_unlock_irqrestore(&gp->lock, flags);
++//--- dump_MII(dev); /* KLUDGE ALERT !!! */
++ return 1;
++ }
++
++ if (gp->tx_ring[nextIn].cmdstat & txOwn) {
++ printk
++ ("%s: gt64240_tx: device owns descriptor, pkt dropped.\n",
++ dev->name);
++ gp->stats.tx_dropped++;
++ // stop the queue, so Tx timeout can fix it
++ netif_stop_queue(dev);
++ spin_unlock_irqrestore(&gp->lock, flags);
++ return 1;
++ }
++ // Prepare the Descriptor at tx_next_in
++ gp->tx_skbuff[nextIn] = skb;
++ gp->tx_ring[nextIn].byte_cnt = skb->len;
++ gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data);
++
++ // make sure packet gets written back to memory
++ dma_cache_wback_inv((unsigned long) (skb->data), skb->len);
++ mb();
++
++ // Give ownership to device, set first and last desc, enable interrupt
++ // Setting of ownership bit must be *last*!
++ gp->tx_ring[nextIn].cmdstat =
++ txOwn | txGenCRC | txEI | txPad | txFirst | txLast;
++
++ if (gt64240_debug > 5) {
++ dump_tx_desc(dev, nextIn);
++ }
++ // increment tx_next_in with wrap
++ gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
++
++//+prk20aug01:
++ if (0) { /* ROLLINS */
++ GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
++ virt_to_phys(&gp->tx_ring[nextIn]));
++ }
++
++ if (gt64240_debug > 3) { /*+prk17aug01 */
++ printk
++ ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_CURR_TX_DESC_PTR0),
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
++ }
++ // If DMA is stopped, restart
++ if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) {
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++ sdcmrERD | sdcmrTXDL);
++ }
++
++ if (gt64240_debug > 3) { /*+prk17aug01 */
++ printk
++ ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
++ dev->name, GT64240ETH_READ(gp,
++ GT64240_ETH_CURR_TX_DESC_PTR0),
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
++ }
++ // increment count and stop queue if full
++ if (++gp->tx_count >= TX_RING_SIZE) {
++ gp->tx_full = 1;
++ netif_stop_queue(dev);
++ }
++
++ dev->trans_start = jiffies;
++ spin_unlock_irqrestore(&gp->lock, flags);
++
++ return 0;
++}
++
++
++static int
++#ifdef GT64240_NAPI
++gt64240_rx(struct net_device *dev, u32 status, int budget)
++#else
++gt64240_rx(struct net_device *dev, u32 status)
++#endif
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ struct sk_buff *skb;
++ int pkt_len, nextOut, cdp;
++ gt64240_rd_t *rd;
++ u32 cmdstat;
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_rx: dev=%p, status=%x\n",
++ dev->name, dev, status);
++
++ cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)
++ - gp->rx_ring_dma) / sizeof(gt64240_rd_t);
++
++ // Continue until we reach the current descriptor pointer
++ for (nextOut = gp->rx_next_out; nextOut != cdp;
++ nextOut = (nextOut + 1) % RX_RING_SIZE) {
++
++#ifdef GT64240_NAPI
++ if (budget <= 0)
++ break;
++
++ budget--;
++#endif
++
++ if (--gp->intr_work_done == 0)
++ break;
++
++ if (gt64240_debug > 4)
++ dump_rx_desc(dev, nextOut);
++
++ rd = &gp->rx_ring[nextOut];
++ cmdstat = rd->cmdstat;
++
++ if (gt64240_debug > 3)
++ printk("%s: isr: Rx desc cmdstat=%x, nextOut=%d\n",
++ dev->name, cmdstat, nextOut);
++
++ if (cmdstat & (u32) rxOwn) {
++ if (gt64240_debug > 2)
++ printk
++ ("%s: gt64240_rx: device owns descriptor!\n",
++ dev->name);
++ // DMA is not finished updating descriptor???
++ // Leave and come back later to pick-up where we left off.
++ break;
++ }
++ // must be first and last (ie only) buffer of packet
++ if (!(cmdstat & (u32) rxFirst)
++ || !(cmdstat & (u32) rxLast)) {
++ printk
++ ("%s: gt64240_rx: desc not first and last!\n",
++ dev->name);
++ cmdstat |= (u32) rxOwn;
++ rd->cmdstat = cmdstat;
++ continue;
++ }
++ // Drop this received pkt if there were any errors
++ if ((cmdstat & (u32) rxErrorSummary)
++ || (status & icrRxError)) {
++ // update the detailed rx error counters that are not covered
++ // by the MIB counters.
++ if (cmdstat & (u32) rxOverrun)
++ gp->stats.rx_fifo_errors++;
++ cmdstat |= (u32) rxOwn;
++ rd->cmdstat = cmdstat;
++ continue;
++ }
++
++ pkt_len = rd->byte_cnt;
++
++ /* Create new skb. */
++// skb = dev_alloc_skb(pkt_len+2);
++ skb = dev_alloc_skb(1538);
++ if (skb == NULL) {
++ printk("%s: Memory squeeze, dropping packet.\n",
++ dev->name);
++ gp->stats.rx_dropped++;
++ cmdstat |= (u32) rxOwn;
++ rd->cmdstat = cmdstat;
++ continue;
++ }
++ skb->dev = dev;
++ skb_reserve(skb, 2); /* 16 byte IP header align */
++ memcpy(skb_put(skb, pkt_len),
++ &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len);
++ skb->protocol = eth_type_trans(skb, dev);
++
++ /* NIC performed some checksum computation */
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++#ifdef GT64240_NAPI
++ netif_receive_skb(skb);
++#else
++ netif_rx(skb); /* pass the packet to upper layers */
++#endif
++
++ // now we can release ownership of this desc back to device
++ cmdstat |= (u32) rxOwn;
++ rd->cmdstat = cmdstat;
++
++ dev->last_rx = jiffies;
++ }
++
++ if (gt64240_debug > 3 && nextOut == gp->rx_next_out)
++ printk("%s: gt64240_rx: RxCDP did not increment?\n",
++ dev->name);
++
++ gp->rx_next_out = nextOut;
++ return 0;
++}
++
++
++static void gt64240_tx_timeout(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ unsigned long flags;
++
++ spin_lock_irqsave(&gp->lock, flags);
++
++
++ if (!(gp->last_psr & psrLink)) {
++ spin_unlock_irqrestore(&gp->lock, flags);
++ } else {
++ printk("======------> gt64240_tx_timeout: %d jiffies \n",
++ GT64240ETH_TX_TIMEOUT);
++
++ disable_ether_irq(dev);
++ spin_unlock_irqrestore(&gp->lock, flags);
++ reset_tx(dev);
++ enable_ether_irq(dev);
++
++ netif_wake_queue(dev);
++ }
++}
++
++
++static void gt64240_set_rx_mode(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ unsigned long flags;
++ struct dev_mc_list *mcptr;
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_set_rx_mode: dev=%p, flags=%x\n",
++ dev->name, dev, dev->flags);
++
++ // stop the Receiver DMA
++ abort(dev, sdcmrAR);
++
++ spin_lock_irqsave(&gp->lock, flags);
++
++ if (dev->flags & IFF_PROMISC)
++ GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
++ else
++ GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
++/*
++ GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
++ (PORT_CONFIG | pcrPM | pcrEN));
++*/
++
++ memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table
++ // Add our ethernet address
++ gt64240_add_hash_entry(dev, dev->dev_addr);
++ if (dev->mc_count) {
++ for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
++ if (gt64240_debug > 2) {
++ printk("%s: gt64240_set_rx_mode: addr=\n",
++ dev->name);
++ dump_hw_addr(mcptr->dmi_addr);
++ }
++ gt64240_add_hash_entry(dev, mcptr->dmi_addr);
++ }
++ }
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_set_rx: Port Config=%x\n", dev->name,
++ GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++
++ // restart Rx DMA
++ GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++
++ spin_unlock_irqrestore(&gp->lock, flags);
++}
++
++static struct net_device_stats *gt64240_get_stats(struct net_device *dev)
++{
++ struct gt64240_private *gp = netdev_priv(dev);
++ unsigned long flags;
++
++ if (gt64240_debug > 3)
++ printk("%s: gt64240_get_stats: dev=%p\n", dev->name, dev);
++
++ if (netif_device_present(dev)) {
++ spin_lock_irqsave(&gp->lock, flags);
++ update_stats(gp);
++ spin_unlock_irqrestore(&gp->lock, flags);
++ }
++
++ return &gp->stats;
++}
+diff -urN --ignore-space-change kernel.org/drivers/net/gt64240eth.h linux-mips/drivers/net/gt64240eth.h
+--- kernel.org/drivers/net/gt64240eth.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/gt64240eth.h 2006-01-10 11:21:38.000000000 +0000
+@@ -9,6 +9,7 @@
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel at mvista.com or support at mvista.com
++ * Copyright 2004, 05 Ralf Baechle (ralf at linux-mips.org)
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+@@ -31,6 +32,7 @@
+ #ifndef _GT64240ETH_H
+ #define _GT64240ETH_H
+
++#include <linux/config.h>
+ #include <asm/gt64240.h>
+
+ #define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
+@@ -108,10 +110,10 @@
+ #define REV_GT64240A 0x10
+
+ #define GT64240ETH_READ(gp, offset) \
+- GT_READ((gp)->port_offset + (offset))
++ MV_READ((gp)->port_offset + (offset))
+
+ #define GT64240ETH_WRITE(gp, offset, data) \
+- GT_WRITE((gp)->port_offset + (offset), (data))
++ MV_WRITE((gp)->port_offset + (offset), (data))
+
+ #define GT64240ETH_SETBIT(gp, offset, bits) \
+ GT64240ETH_WRITE((gp), (offset), \
+@@ -121,8 +123,8 @@
+ GT64240ETH_WRITE((gp), (offset), \
+ GT64240ETH_READ((gp), (offset)) & ~(bits))
+
+-#define GT64240_READ(ofs) GT_READ(ofs)
+-#define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data))
++#define GT64240_READ(ofs) MV_READ(ofs)
++#define GT64240_WRITE(ofs, data) MV_WRITE((ofs), (data))
+
+ /* Bit definitions of the SMI Reg */
+ enum {
+diff -urN --ignore-space-change kernel.org/drivers/net/sb1250-mac.c linux-mips/drivers/net/sb1250-mac.c
+--- kernel.org/drivers/net/sb1250-mac.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/sb1250-mac.c 2006-01-10 11:21:39.000000000 +0000
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2001,2002,2003 Broadcom Corporation
++ * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+@@ -43,6 +43,7 @@
+ #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
+ #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
+ #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
++#define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
+ #endif
+
+
+@@ -57,7 +58,7 @@
+
+ #define CONFIG_SBMAC_COALESCE
+
+-#define MAX_UNITS 3 /* More are supported, limit only on options */
++#define MAX_UNITS 4 /* More are supported, limit only on options */
+
+ /* Time in jiffies before concluding the transmitter is hung. */
+ #define TX_TIMEOUT (2*HZ)
+@@ -85,11 +86,11 @@
+ The media type is usually passed in 'options[]'.
+ */
+ #ifdef MODULE
+-static int options[MAX_UNITS] = {-1, -1, -1};
++static int options[MAX_UNITS] = {-1, -1, -1, -1};
+ module_param_array(options, int, NULL, S_IRUGO);
+ MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
+
+-static int full_duplex[MAX_UNITS] = {-1, -1, -1};
++static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
+ module_param_array(full_duplex, int, NULL, S_IRUGO);
+ MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
+ #endif
+@@ -105,13 +106,26 @@
+ #endif
+
+ #include <asm/sibyte/sb1250.h>
+-#include <asm/sibyte/sb1250_defs.h>
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#include <asm/sibyte/bcm1480_regs.h>
++#include <asm/sibyte/bcm1480_int.h>
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
+ #include <asm/sibyte/sb1250_regs.h>
+-#include <asm/sibyte/sb1250_mac.h>
+-#include <asm/sibyte/sb1250_dma.h>
+ #include <asm/sibyte/sb1250_int.h>
++#else
++#error invalid SiByte MAC configuation
++#endif
+ #include <asm/sibyte/sb1250_scd.h>
++#include <asm/sibyte/sb1250_mac.h>
++#include <asm/sibyte/sb1250_dma.h>
+
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
++#define UNIT_INT(n) (K_INT_MAC_0 + (n))
++#else
++#error invalid SiByte MAC configuation
++#endif
+
+ /**********************************************************************
+ * Simple types
+@@ -142,6 +156,10 @@
+
+ #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
+
++#define SBMAC_READCSR(t) __raw_readq((unsigned long)t)
++#define SBMAC_WRITECSR(t,v) __raw_writeq(v, (unsigned long)t)
++
++
+ #define SBMAC_MAX_TXDESCR 32
+ #define SBMAC_MAX_RXDESCR 32
+
+@@ -1476,10 +1494,10 @@
+ * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
+ * Use a larger RD_THRSH for gigabit
+ */
+- if (periph_rev >= 2)
+- th_value = 64;
+- else
++ if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
+ th_value = 28;
++ else
++ th_value = 64;
+
+ fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
+ ((s->sbm_speed == sbmac_speed_1000)
+@@ -1589,13 +1607,17 @@
+ * Turn on the rest of the bits in the enable register
+ */
+
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++ __raw_writeq(M_MAC_RXDMA_EN0 |
++ M_MAC_TXDMA_EN0, s->sbm_macenable);
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
+ __raw_writeq(M_MAC_RXDMA_EN0 |
+ M_MAC_TXDMA_EN0 |
+ M_MAC_RX_ENABLE |
+ M_MAC_TX_ENABLE, s->sbm_macenable);
-
--static int siu_resume(struct device *dev, u32 level)
--{
-- struct uart_port *port;
-- int i;
-
-- if (level != RESUME_ENABLE)
-- return 0;
-
-- for (i = 0; i < siu_uart_driver.nr; i++) {
-- port = &siu_uart_ports[i];
-- if ((port->type == PORT_VR41XX_SIU ||
-- port->type == PORT_VR41XX_DSIU) && port->dev == dev)
-- uart_resume_port(&siu_uart_driver, port);
++#else
++#error invalid SiByte MAC configuation
++#endif
+
+ #ifdef CONFIG_SBMAC_COALESCE
+ /*
+@@ -1786,11 +1808,12 @@
+ reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
+ __raw_writeq(reg, sc->sbm_rxfilter);
+
+- /* read system identification to determine revision */
+- if (periph_rev >= 2) {
+- sc->rx_hw_checksum = ENABLE;
+- } else {
++ /* BCM1250 pass1 didn't have hardware checksum. Everything
++ later does. */
++ if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
+ sc->rx_hw_checksum = DISABLE;
++ } else {
++ sc->rx_hw_checksum = ENABLE;
+ }
+ }
+
+@@ -2220,7 +2243,7 @@
+
+
+
+-#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
++#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
+ /**********************************************************************
+ * SBMAC_PARSE_XDIGIT(str)
+ *
+@@ -2397,6 +2420,11 @@
+ sc->sbm_dev->name);
+ }
+
++ if (periph_rev >= 2) {
++ printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
++ sc->sbm_dev->name);
++ }
++
+ /*
+ * Display Ethernet address (this is called during the config
+ * process so we need to finish off the config message that
+@@ -2792,7 +2820,7 @@
+
+
+
+-#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
++#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
+ static void
+ sbmac_setup_hwaddr(int chan,char *addr)
+ {
+@@ -2818,43 +2846,55 @@
+ unsigned long port;
+ int chip_max_units;
+
++ /* Set the number of available units based on the SOC type. */
++ switch (soc_type) {
++ case K_SYS_SOC_TYPE_BCM1250:
++ case K_SYS_SOC_TYPE_BCM1250_ALT:
++ chip_max_units = 3;
++ break;
++ case K_SYS_SOC_TYPE_BCM1120:
++ case K_SYS_SOC_TYPE_BCM1125:
++ case K_SYS_SOC_TYPE_BCM1125H:
++ case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
++ chip_max_units = 2;
++ break;
++ case K_SYS_SOC_TYPE_BCM1x55:
++ case K_SYS_SOC_TYPE_BCM1x80:
++ chip_max_units = 4;
++ break;
++ default:
++ chip_max_units = 0;
++ break;
++ }
++ if (chip_max_units > MAX_UNITS)
++ chip_max_units = MAX_UNITS;
++
+ /*
+ * For bringup when not using the firmware, we can pre-fill
+ * the MAC addresses using the environment variables
+ * specified in this file (or maybe from the config file?)
+ */
+ #ifdef SBMAC_ETH0_HWADDR
++ if (chip_max_units > 0)
+ sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
+ #endif
+ #ifdef SBMAC_ETH1_HWADDR
++ if (chip_max_units > 1)
+ sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
+ #endif
+ #ifdef SBMAC_ETH2_HWADDR
++ if (chip_max_units > 2)
+ sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
+ #endif
++#ifdef SBMAC_ETH3_HWADDR
++ if (chip_max_units > 3)
++ sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
++#endif
+
+ /*
+ * Walk through the Ethernet controllers and find
+ * those who have their MAC addresses set.
+ */
+- switch (soc_type) {
+- case K_SYS_SOC_TYPE_BCM1250:
+- case K_SYS_SOC_TYPE_BCM1250_ALT:
+- chip_max_units = 3;
+- break;
+- case K_SYS_SOC_TYPE_BCM1120:
+- case K_SYS_SOC_TYPE_BCM1125:
+- case K_SYS_SOC_TYPE_BCM1125H:
+- case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
+- chip_max_units = 2;
+- break;
+- default:
+- chip_max_units = 0;
+- break;
- }
+- if (chip_max_units > MAX_UNITS)
+- chip_max_units = MAX_UNITS;
-
-- return 0;
--}
--
--static struct platform_device *siu_platform_device;
--
--static struct device_driver siu_device_driver = {
-- .name = "SIU",
-- .bus = &platform_bus_type,
-- .probe = siu_probe,
-- .remove = siu_remove,
-- .suspend = siu_suspend,
-- .resume = siu_resume,
--};
--
--static int __devinit vr41xx_siu_init(void)
--{
-- int retval;
--
-- siu_platform_device = platform_device_register_simple("SIU", -1, NULL, 0);
-- if (IS_ERR(siu_platform_device))
-- return PTR_ERR(siu_platform_device);
--
-- retval = driver_register(&siu_device_driver);
-- if (retval < 0)
-- platform_device_unregister(siu_platform_device);
--
-- return retval;
--}
--
--static void __devexit vr41xx_siu_exit(void)
--{
-- driver_unregister(&siu_device_driver);
--
-- platform_device_unregister(siu_platform_device);
--}
--
--module_init(vr41xx_siu_init);
--module_exit(vr41xx_siu_exit);
-diff -urpNX dontdiff linux-2.6.12/drivers/tc/tc.c linux_HEAD/drivers/tc/tc.c
---- linux-2.6.12/drivers/tc/tc.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/tc/tc.c 2005-07-03 16:44:34.000000000 +0200
-@@ -8,33 +8,31 @@
- * for more details.
- *
- * Copyright (c) Harald Koerfgen, 1998
-- * Copyright (c) 2001, 2003 Maciej W. Rozycki
-+ * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
- */
--#include <linux/string.h>
- #include <linux/init.h>
--#include <linux/ioport.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
+ for (idx = 0; idx < chip_max_units; idx++) {
- #include <asm/addrspace.h>
-+#include <asm/bug.h>
- #include <asm/errno.h>
+ /*
+@@ -2886,7 +2926,7 @@
+
+ printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
+
+- dev->irq = K_INT_MAC_0 + idx;
++ dev->irq = UNIT_INT(idx);
+ dev->base_addr = port;
+ dev->mem_end = 0;
+ if (sbmac_init(dev, idx)) {
+diff -urN --ignore-space-change kernel.org/drivers/net/titan_ge.c linux-mips/drivers/net/titan_ge.c
+--- kernel.org/drivers/net/titan_ge.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/titan_ge.c 2006-01-10 11:21:43.000000000 +0000
+@@ -0,0 +1,2071 @@
++/*
++ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++/*
++ * The MAC unit of the Titan consists of the following:
++ *
++ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
++ * -> FIFO is where the incoming and outgoing data is placed
++ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
++ * the data into the FIFO for Rx
++ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
++ * -> AFX is the address filtering block
++ * -> GMII block to communicate with the PHY
++ *
++ * Rx will look like the following:
++ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
++ *
++ * Tx will look like the following:
++ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
++ *
++ * The Titan driver has support for the following performance features:
++ * -> Rx side checksumming
++ * -> Jumbo Frames
++ * -> Interrupt Coalscing
++ * -> Rx NAPI
++ * -> SKB Recycling
++ * -> Transmit/Receive descriptors in SRAM
++ * -> Fast routing for IP forwarding
++ */
++
++#include <linux/config.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/ioport.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/ip.h>
++#include <linux/init.h>
++#include <linux/in.h>
++#include <linux/platform_device.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mii.h>
++#include <linux/delay.h>
++#include <linux/skbuff.h>
++#include <linux/prefetch.h>
++
++/* For MII specifc registers, titan_mdio.h should be included */
++#include <net/ip.h>
++
++#include <asm/bitops.h>
+#include <asm/io.h>
-+#include <asm/paccess.h>
++#include <asm/types.h>
++#include <asm/pgtable.h>
++#include <asm/system.h>
++#include <asm/titan_dep.h>
++
++#include "titan_ge.h"
++#include "titan_mdio.h"
++
++/* Static Function Declarations */
++static int titan_ge_eth_open(struct net_device *);
++static void titan_ge_eth_stop(struct net_device *);
++static struct net_device_stats *titan_ge_get_stats(struct net_device *);
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
++ unsigned long, unsigned long,
++ unsigned long);
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
++ unsigned long, unsigned long);
++
++static int titan_ge_open(struct net_device *);
++static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
++static int titan_ge_stop(struct net_device *);
++
++static unsigned long titan_ge_tx_coal(unsigned long, int);
++
++static void titan_ge_port_reset(unsigned int);
++static int titan_ge_free_tx_queue(titan_ge_port_info *);
++static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
++static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
++
++static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
++
++/*
++ * Some configuration for the FIFO and the XDMA channel needs
++ * to be done only once for all the ports. This flag controls
++ * that
++ */
++static unsigned long config_done;
++
++/*
++ * One time out of memory flag
++ */
++static unsigned int oom_flag;
++
++static int titan_ge_poll(struct net_device *netdev, int *budget);
++
++static int titan_ge_receive_queue(struct net_device *, unsigned int);
++
++static struct platform_device *titan_ge_device[3];
++
++/* MAC Address */
++extern unsigned char titan_ge_mac_addr_base[6];
++
++unsigned long titan_ge_base;
++static unsigned long titan_ge_sram;
++
++static char titan_string[] = "titan";
++
++/*
++ * The Titan GE has two alignment requirements:
++ * -> skb->data to be cacheline aligned (32 byte)
++ * -> IP header alignment to 16 bytes
++ *
++ * The latter is not implemented. So, that results in an extra copy on
++ * the Rx. This is a big performance hog. For the former case, the
++ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
++ * requested is calculated:
++ *
++ * Ethernet Frame Size : 1518
++ * Ethernet Header : 14
++ * Future Titan change for IP header alignment : 2
++ *
++ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes. For IP header
++ * alignment, we use skb_reserve().
++ */
++
++#define ALIGNED_RX_SKB_ADDR(addr) \
++ ((((unsigned long)(addr) + (64UL - 1UL)) \
++ & ~(64UL - 1UL)) - (unsigned long)(addr))
++
++#define titan_ge_alloc_skb(__length, __gfp_flags) \
++({ struct sk_buff *__skb; \
++ __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
++ if(__skb) { \
++ int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
++ if(__offset) \
++ skb_reserve(__skb, __offset); \
++ } \
++ __skb; \
++})
++
++/*
++ * Configure the GMII block of the Titan based on what the PHY tells us
++ */
++static void titan_ge_gmii_config(int port_num)
++{
++ unsigned int reg_data = 0, phy_reg;
++ int err;
++
++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++
++ if (err == TITAN_GE_MDIO_ERROR) {
++ printk(KERN_ERR
++ "Could not read PHY control register 0x11 \n");
++ printk(KERN_ERR
++ "Setting speed to 1000 Mbps and Duplex to Full \n");
++
++ return;
++ }
++
++ err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
++
++ if (phy_reg & 0x8000) {
++ if (phy_reg & 0x2000) {
++ /* Full Duplex and 1000 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x201);
++ } else {
++ /* Half Duplex and 1000 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x2201);
++ }
++ }
++ if (phy_reg & 0x4000) {
++ if (phy_reg & 0x2000) {
++ /* Full Duplex and 100 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x100);
++ } else {
++ /* Half Duplex and 100 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x2100);
++ }
++ }
++ reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
++ (port_num << 12));
++ reg_data |= 0x3;
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
++ (port_num << 12)), reg_data);
++}
++
++/*
++ * Enable the TMAC if it is not
++ */
++static void titan_ge_enable_tx(unsigned int port_num)
++{
++ unsigned long reg_data;
++
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++ if (!(reg_data & 0x8000)) {
++ printk("TMAC disabled for port %d!! \n", port_num);
++
++ reg_data |= 0x0001; /* Enable TMAC */
++ reg_data |= 0x4000; /* CRC Check Enable */
++ reg_data |= 0x2000; /* Padding enable */
++ reg_data |= 0x0800; /* CRC Add enable */
++ reg_data |= 0x0080; /* PAUSE frame */
++
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++ }
++}
++
++/*
++ * Tx Timeout function
++ */
++static void titan_ge_tx_timeout(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ printk(KERN_INFO "%s: TX timeout ", netdev->name);
++ printk(KERN_INFO "Resetting card \n");
++
++ /* Do the reset outside of interrupt context */
++ schedule_work(&titan_ge_eth->tx_timeout_task);
++}
++
++/*
++ * Update the AFX tables for UC and MC for slice 0 only
++ */
++static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
++{
++ int port = titan_ge_eth->port_num;
++ unsigned int i;
++ volatile unsigned long reg_data = 0;
++ u8 p_addr[6];
++
++ memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
++
++ /* Set the MAC address here for TMAC and RMAC */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
++ /* Configure the eight address filters */
++ for (i = 0; i < 8; i++) {
++ /* Select each of the eight filters */
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
++ (port << 12)), i);
++
++ /* Configure the match */
++ reg_data = 0x9; /* Forward Enable Bit */
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
++ (port << 12)), reg_data);
++
++ /* Finally, AFX Exact Match Address Registers */
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++
++ /* VLAN id set to 0 */
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
++ (port << 12)), 0);
++ }
++}
++
++/*
++ * Actual Routine to reset the adapter when the timeout occurred
++ */
++static void titan_ge_tx_timeout_task(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ int port = titan_ge_eth->port_num;
++
++ printk("Titan GE: Transmit timed out. Resetting ... \n");
++
++ /* Dump debug info */
++ printk(KERN_ERR "TRTG cause : %x \n",
++ TITAN_GE_READ(0x100c + (port << 12)));
++
++ /* Fix this for the other ports */
++ printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
++ printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
++ printk(KERN_ERR "XDMA GDI ERROR : %x \n",
++ TITAN_GE_READ(0x5008 + (port << 8)));
++ printk(KERN_ERR "CHANNEL ERROR: %x \n",
++ TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
++ + (port << 8)));
++
++ netif_device_detach(netdev);
++ titan_ge_port_reset(titan_ge_eth->port_num);
++ titan_ge_port_start(netdev, titan_ge_eth);
++ netif_device_attach(netdev);
++}
++
++/*
++ * Change the MTU of the Ethernet Device
++ */
++static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned long flags;
++
++ if ((new_mtu > 9500) || (new_mtu < 64))
++ return -EINVAL;
++
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ netdev->mtu = new_mtu;
++
++ /* Now we have to reopen the interface so that SKBs with the new
++ * size will be allocated */
++
++ if (netif_running(netdev)) {
++ titan_ge_eth_stop(netdev);
++
++ if (titan_ge_eth_open(netdev) != TITAN_OK) {
++ printk(KERN_ERR
++ "%s: Fatal error on opening device\n",
++ netdev->name);
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ return -1;
++ }
++ }
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ return 0;
++}
++
++/*
++ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
++ * only. Once an interrupt is triggered, figure out the port and then check
++ * the channel.
++ */
++static irqreturn_t titan_ge_int_handler(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ struct net_device *netdev = (struct net_device *) dev_id;
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int reg_data;
++ unsigned int eth_int_cause_error = 0, is;
++ unsigned long eth_int_cause1;
++ int err = 0;
++#ifdef CONFIG_SMP
++ unsigned long eth_int_cause2;
++#endif
++
++ /* Ack the CPU interrupt */
++ switch (port_num) {
++ case 0:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
++#endif
++ break;
++
++ case 1:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
++#endif
++ break;
++
++ case 2:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
++#endif
++ }
++
++ eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++#ifdef CONFIG_SMP
++ eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
++#endif
++
++ /* Spurious interrupt */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
++#else
++ if (eth_int_cause1 == 0) {
++#endif
++ eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
++ (port_num << 8));
++
++ if (eth_int_cause_error == 0)
++ return IRQ_NONE;
++ }
++
++ /* Handle Tx first. No need to ack interrupts */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 & 0x20202) ||
++ (eth_int_cause2 & 0x20202) )
++#else
++ if (eth_int_cause1 & 0x20202)
++#endif
++ titan_ge_free_tx_queue(titan_ge_eth);
++
++ /* Handle the Rx next */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 & 0x10101) ||
++ (eth_int_cause2 & 0x10101)) {
++#else
++ if (eth_int_cause1 & 0x10101) {
++#endif
++ if (netif_rx_schedule_prep(netdev)) {
++ unsigned int ack;
++
++ ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++ /* Disable Tx and Rx both */
++ if (port_num == 0)
++ ack &= ~(0x3);
++ if (port_num == 1)
++ ack &= ~(0x300);
++
++ if (port_num == 2)
++ ack &= ~(0x30000);
++
++ /* Interrupts have been disabled */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
++
++ __netif_rx_schedule(netdev);
++ }
++ }
++
++ /* Handle error interrupts */
++ if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
++ printk(KERN_ERR
++ "XDMA Channel Error : %x on port %d\n",
++ eth_int_cause_error, port_num);
++
++ printk(KERN_ERR
++ "XDMA GDI Hardware error : %x on port %d\n",
++ TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
++
++ printk(KERN_ERR
++ "XDMA currently has %d Rx descriptors \n",
++ TITAN_GE_READ(0x5048 + (port_num << 8)));
++
++ printk(KERN_ERR
++ "XDMA currently has prefetcted %d Rx descriptors \n",
++ TITAN_GE_READ(0x505c + (port_num << 8)));
++
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
++ (port_num << 8)), eth_int_cause_error);
++ }
++
++ /*
++ * PHY interrupt to inform abt the changes. Reading the
++ * PHY Status register will clear the interrupt
++ */
++ if ((!(eth_int_cause1 & 0x30303)) &&
++ (eth_int_cause_error == 0)) {
++ err =
++ titan_ge_mdio_read(port_num,
++ TITAN_GE_MDIO_PHY_IS, ®_data);
++
++ if (reg_data & 0x0400) {
++ /* Link status change */
++ titan_ge_mdio_read(port_num,
++ TITAN_GE_MDIO_PHY_STATUS, ®_data);
++ if (!(reg_data & 0x0400)) {
++ /* Link is down */
++ netif_carrier_off(netdev);
++ netif_stop_queue(netdev);
++ } else {
++ /* Link is up */
++ netif_carrier_on(netdev);
++ netif_wake_queue(netdev);
++
++ /* Enable the queue */
++ titan_ge_enable_tx(port_num);
++ }
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * Multicast and Promiscuous mode set. The
++ * set_multi entry point is called whenever the
++ * multicast address list or the network interface
++ * flags are updated.
++ */
++static void titan_ge_set_multi(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned long reg_data;
++
++ reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++ (port_num << 12));
++
++ if (netdev->flags & IFF_PROMISC) {
++ reg_data |= 0x2;
++ }
++ else if (netdev->flags & IFF_ALLMULTI) {
++ reg_data |= 0x01;
++ reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
++ }
++ else {
++ reg_data = 0x2;
++ }
++
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++ (port_num << 12)), reg_data);
++ if (reg_data & 0x01) {
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
++ (port_num << 12)), 0xffff);
++ }
++}
++
++/*
++ * Open the network device
++ */
++static int titan_ge_open(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
++ int retval;
++
++ retval = request_irq(irq, titan_ge_int_handler,
++ SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
++
++ if (retval != 0) {
++ printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
++ return -1;
++ }
++
++ netdev->irq = irq;
++ printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
++
++ spin_lock_irq(&(titan_ge_eth->lock));
++
++ if (titan_ge_eth_open(netdev) != TITAN_OK) {
++ spin_unlock_irq(&(titan_ge_eth->lock));
++ printk("%s: Error opening interface \n", netdev->name);
++ free_irq(netdev->irq, netdev);
++ return -EBUSY;
++ }
++
++ spin_unlock_irq(&(titan_ge_eth->lock));
++
++ return 0;
++}
++
++/*
++ * Allocate the SKBs for the Rx ring. Also used
++ * for refilling the queue
++ */
++static int titan_ge_rx_task(struct net_device *netdev,
++ titan_ge_port_info *titan_ge_port)
++{
++ struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
++ volatile titan_ge_rx_desc *rx_desc;
++ struct sk_buff *skb;
++ int rx_used_desc;
++ int count = 0;
++
++ while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
++
++ /* First try to get the skb from the recycler */
++#ifdef TITAN_GE_JUMBO_FRAMES
++ skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
++#else
++ skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
++#endif
++ if (unlikely(!skb)) {
++ /* OOM, set the flag */
++ printk("OOM \n");
++ oom_flag = 1;
++ break;
++ }
++ count++;
++ skb->dev = netdev;
++
++ titan_ge_port->rx_ring_skbs++;
++
++ rx_used_desc = titan_ge_port->rx_used_desc_q;
++ rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ rx_desc->buffer_addr = dma_map_single(device, skb->data,
++ TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
++#else
++ rx_desc->buffer_addr = dma_map_single(device, skb->data,
++ TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
++#endif
++
++ titan_ge_port->rx_skb[rx_used_desc] = skb;
++ rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
++
++ titan_ge_port->rx_used_desc_q =
++ (rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
++ }
++
++ return count;
++}
++
++/*
++ * Actual init of the Tital GE port. There is one register for
++ * the channel configuration
++ */
++static void titan_port_init(struct net_device *netdev,
++ titan_ge_port_info * titan_ge_eth)
++{
++ unsigned long reg_data;
++
++ titan_ge_port_reset(titan_ge_eth->port_num);
++
++ /* First reset the TMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data |= 0x80000000;
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ udelay(30);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data &= ~(0xc0000000);
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ /* Now reset the RMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data |= 0x00080000;
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ udelay(30);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data &= ~(0x000c0000);
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++}
++
++/*
++ * Start the port. All the hardware specific configuration
++ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
++ * go here
++ */
++static int titan_ge_port_start(struct net_device *netdev,
++ titan_ge_port_info * titan_port)
++{
++ volatile unsigned long reg_data, reg_data1;
++ int port_num = titan_port->port_num;
++ int count = 0;
++ unsigned long reg_data_1;
++
++ if (config_done == 0) {
++ reg_data = TITAN_GE_READ(0x0004);
++ reg_data |= 0x100;
++ TITAN_GE_WRITE(0x0004, reg_data);
++
++ reg_data &= ~(0x100);
++ TITAN_GE_WRITE(0x0004, reg_data);
++
++ /* Turn on GMII/MII mode and turn off TBI mode */
++ reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
++ reg_data |= 0x00000700;
++ reg_data &= ~(0x00800000); /* Fencing */
++
++ TITAN_GE_WRITE(0x000c, 0x00001100);
++
++ TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
++
++ /* Set the CPU Resource Limit register */
++ TITAN_GE_WRITE(0x00f8, 0x8);
++
++ /* Be conservative when using the BIU buffers */
++ TITAN_GE_WRITE(0x0068, 0x4);
++ }
++
++ titan_port->tx_threshold = 0;
++ titan_port->rx_threshold = 0;
++
++ /* We need to write the descriptors for Tx and Rx */
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
++ (unsigned long) titan_port->tx_dma);
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
++ (unsigned long) titan_port->rx_dma);
++
++ if (config_done == 0) {
++ /* Step 1: XDMA config */
++ reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
++ reg_data &= ~(0x80000000); /* clear reset */
++ reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */
++ reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */
++ reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */
++ reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */
++ TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
++ }
++
++ /* IR register for the XDMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
++ reg_data |= 0x80068000; /* No Rx_OOD */
++ TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
++
++ /* Start the Tx and Rx XDMA controller */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
++ reg_data &= 0x4fffffff; /* Clear tx reset */
++ reg_data &= 0xfff4ffff; /* Clear rx reset */
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ reg_data |= 0xa0 | 0x30030000;
++#else
++ reg_data |= 0x40 | 0x20030000;
++#endif
++
++#ifndef CONFIG_SMP
++ reg_data &= ~(0x10);
++ reg_data |= 0x0f; /* All of the packet */
++#endif
++
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
++
++ /* Rx desc count */
++ count = titan_ge_rx_task(netdev, titan_port);
++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
++ count = TITAN_GE_READ(0x5048 + (port_num << 8));
++
++ udelay(30);
++
++ /*
++ * Step 2: Configure the SDQPF, i.e. FIFO
++ */
++ if (config_done == 0) {
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++ reg_data = 0x1;
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++ reg_data &= ~(0x1);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++ reg_data = 0x1;
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ reg_data &= ~(0x1);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ }
++ /*
++ * Enable RX FIFO 0, 4 and 8
++ */
++ if (port_num == 0) {
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10);
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4844);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x4844, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ reg_data |= (0xff << 10);
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4944);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x4944, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ }
++
++ if (port_num == 1) {
++ reg_data = TITAN_GE_READ(0x4870);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (0xff + 1);
++
++ TITAN_GE_WRITE(0x4870, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4874);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x4874, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4870, reg_data);
++
++ reg_data = TITAN_GE_READ(0x494c);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x494c, reg_data);
++ reg_data |= (0xff << 10) | (0xff + 1);
++ TITAN_GE_WRITE(0x494c, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4950);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x4950, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x494c, reg_data);
++ }
++
++ /*
++ * Titan 1.2 revision does support port #2
++ */
++ if (port_num == 2) {
++ /*
++ * Put the descriptors in the SRAM
++ */
++ reg_data = TITAN_GE_READ(0x48a0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x48a4);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x48a4, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++
++ reg_data = TITAN_GE_READ(0x4958);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++ TITAN_GE_WRITE(0x4958, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x495c);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x495c, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ }
++
++ if (port_num == 2) {
++ reg_data = TITAN_GE_READ(0x48a0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x48a4);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x48a4, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++
++ reg_data = TITAN_GE_READ(0x4958);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++ TITAN_GE_WRITE(0x4958, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x495c);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x495c, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ }
++
++ /*
++ * Step 3: TRTG block enable
++ */
++ reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
++
++ /*
++ * This is the 1.2 revision of the chip. It has fix for the
++ * IP header alignment. Now, the IP header begins at an
++ * aligned address and this wont need an extra copy in the
++ * driver. This performance drawback existed in the previous
++ * versions of the silicon
++ */
++ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
++ reg_data_1 |= 0x40000000;
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ reg_data_1 |= 0x04000000;
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ mdelay(5);
++
++ reg_data_1 &= ~(0x04000000);
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ mdelay(5);
++
++ reg_data |= 0x0001;
++ TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
++
++ /*
++ * Step 4: Start the Tx activity
++ */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
++#ifdef TITAN_GE_JUMBO_FRAMES
++ TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
++#endif
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++ reg_data |= 0x0001; /* Enable TMAC */
++ reg_data |= 0x6c70; /* PAUSE also set */
++
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ udelay(30);
++
++ /* Destination Address drop bit */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
++ reg_data |= 0x218; /* DA_DROP bit and pause */
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
++
++ TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
++#endif
++ /* Start the Rx activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++ reg_data |= 0x0001; /* RMAC Enable */
++ reg_data |= 0x0010; /* CRC Check enable */
++ reg_data |= 0x0040; /* Min Frame check enable */
++ reg_data |= 0x4400; /* Max Frame check enable */
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ udelay(30);
++
++ /*
++ * Enable the Interrupts for Tx and Rx
++ */
++ reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++ if (port_num == 0) {
++ reg_data1 |= 0x3;
++#ifdef CONFIG_SMP
++ TITAN_GE_WRITE(0x0038, 0x003);
++#else
++ TITAN_GE_WRITE(0x0038, 0x303);
++#endif
++ }
++
++ if (port_num == 1) {
++ reg_data1 |= 0x300;
++ }
++
++ if (port_num == 2)
++ reg_data1 |= 0x30000;
++
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
++ TITAN_GE_WRITE(0x003c, 0x300);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */
++ TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */
++ }
++
++ /* Priority */
++ reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
++ reg_data &= ~(0x00f00000);
++ TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
++
++ /* Step 5: GMII config */
++ titan_ge_gmii_config(port_num);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(0x1a80, 0);
++ config_done = 1;
++ }
++
++ return TITAN_OK;
++}
++
++/*
++ * Function to queue the packet for the Ethernet device
++ */
++static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
++ struct sk_buff * skb)
++{
++ struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
++ unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
++ volatile titan_ge_tx_desc *tx_curr;
++ int port_num = titan_ge_eth->port_num;
++
++ tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
++ tx_curr->buffer_addr =
++ dma_map_single(device, skb->data, skb_headlen(skb),
++ DMA_TO_DEVICE);
++
++ titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
++ tx_curr->buffer_len = skb_headlen(skb);
++
++ /* Last descriptor enables interrupt and changes ownership */
++ tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
++
++ /* Kick the XDMA to start the transfer from memory to the FIFO */
++ TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
++
++ /* Current descriptor updated */
++ titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
++
++ /* Prefetch the next descriptor */
++ prefetch((const void *)
++ &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
++}
++
++/*
++ * Actually does the open of the Ethernet device
++ */
++static int titan_ge_eth_open(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ struct device *device = &titan_ge_device[port_num]->dev;
++ unsigned long reg_data;
++ unsigned int phy_reg;
++ int err = 0;
++
++ /* Stop the Rx activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ /* Clear the port interrupts */
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
++ }
++
++ /* Set the MAC Address */
++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++
++ if (config_done == 0)
++ titan_port_init(netdev, titan_ge_eth);
++
++ titan_ge_update_afx(titan_ge_eth);
++
++ /* Allocate the Tx ring now */
++ titan_ge_eth->tx_ring_skbs = 0;
++ titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
++
++ /* Allocate space in the SRAM for the descriptors */
++ titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
++ (titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
++ titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
++
++ if (!titan_ge_eth->tx_desc_area) {
++ printk(KERN_ERR
++ "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
++ netdev->name, TITAN_TX_RING_BYTES, port_num);
++ return -ENOMEM;
++ }
++
++ memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
++
++ /* Now initialize the Tx descriptor ring */
++ titan_ge_init_tx_desc_ring(titan_ge_eth,
++ titan_ge_eth->tx_ring_size,
++ (unsigned long) titan_ge_eth->tx_desc_area,
++ (unsigned long) titan_ge_eth->tx_dma);
++
++ /* Allocate the Rx ring now */
++ titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
++ titan_ge_eth->rx_ring_skbs = 0;
++
++ titan_ge_eth->rx_desc_area =
++ (titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
++
++ titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
++
++ if (!titan_ge_eth->rx_desc_area) {
++ printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
++ netdev->name, TITAN_RX_RING_BYTES);
++
++ printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
++ netdev->name);
++
++ dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
++ (void *) titan_ge_eth->tx_desc_area,
++ titan_ge_eth->tx_dma);
++
++ return -ENOMEM;
++ }
++
++ memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
++
++ /* Now initialize the Rx ring */
++#ifdef TITAN_GE_JUMBO_FRAMES
++ if ((titan_ge_init_rx_desc_ring
++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
++ (unsigned long) titan_ge_eth->rx_desc_area, 0,
++ (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#else
++ if ((titan_ge_init_rx_desc_ring
++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
++ (unsigned long) titan_ge_eth->rx_desc_area, 0,
++ (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#endif
++ panic("%s: Error initializing RX Ring\n", netdev->name);
++
++ /* Fill the Rx ring with the SKBs */
++ titan_ge_port_start(netdev, titan_ge_eth);
++
++ /*
++ * Check if Interrupt Coalscing needs to be turned on. The
++ * values specified in the register is multiplied by
++ * (8 x 64 nanoseconds) to determine when an interrupt should
++ * be sent to the CPU.
++ */
++
++ if (TITAN_GE_TX_COAL) {
++ titan_ge_eth->tx_int_coal =
++ titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
++ }
++
++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++ if (err == TITAN_GE_MDIO_ERROR) {
++ printk(KERN_ERR
++ "Could not read PHY control register 0x11 \n");
++ return TITAN_ERROR;
++ }
++ if (!(phy_reg & 0x0400)) {
++ netif_carrier_off(netdev);
++ netif_stop_queue(netdev);
++ return TITAN_ERROR;
++ } else {
++ netif_carrier_on(netdev);
++ netif_start_queue(netdev);
++ }
++
++ return TITAN_OK;
++}
++
++/*
++ * Queue the packet for Tx. Currently no support for zero copy,
++ * checksum offload and Scatter Gather. The chip does support
++ * Scatter Gather only. But, that wont help here since zero copy
++ * requires support for Tx checksumming also.
++ */
++int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned long flags;
++ struct net_device_stats *stats;
++//printk("titan_ge_start_xmit\n");
++
++ stats = &titan_ge_eth->stats;
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
++ (skb_shinfo(skb)->nr_frags + 1)) {
++ netif_stop_queue(netdev);
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ printk(KERN_ERR "Tx OOD \n");
++ return 1;
++ }
++
++ titan_ge_tx_queue(titan_ge_eth, skb);
++ titan_ge_eth->tx_ring_skbs++;
++
++ if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ titan_ge_free_tx_queue(titan_ge_eth);
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++ }
++
++ stats->tx_bytes += skb->len;
++ stats->tx_packets++;
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ netdev->trans_start = jiffies;
++
++ return 0;
++}
++
++/*
++ * Actually does the Rx. Rx side checksumming supported.
++ */
++static int titan_ge_rx(struct net_device *netdev, int port_num,
++ titan_ge_port_info * titan_ge_port,
++ titan_ge_packet * packet)
++{
++ int rx_curr_desc, rx_used_desc;
++ volatile titan_ge_rx_desc *rx_desc;
++
++ rx_curr_desc = titan_ge_port->rx_curr_desc_q;
++ rx_used_desc = titan_ge_port->rx_used_desc_q;
++
++ if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
++ return TITAN_ERROR;
++
++ rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
++
++ if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
++ return TITAN_ERROR;
++
++ packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
++ packet->len = (rx_desc->cmd_sts & 0x7fff);
++
++ /*
++ * At this point, we dont know if the checksumming
++ * actually helps relieve CPU. So, keep it for
++ * port 0 only
++ */
++ packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
++ packet->cmd_sts = rx_desc->cmd_sts;
++
++ titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
++
++ /* Prefetch the next descriptor */
++ prefetch((const void *)
++ &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
++
++ return TITAN_OK;
++}
++
++/*
++ * Free the Tx queue of the used SKBs
++ */
++static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
++{
++ unsigned long flags;
++
++ /* Take the lock */
++ spin_lock_irqsave(&(titan_ge_eth->lock), flags);
++
++ while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
++ if (titan_ge_eth->tx_ring_skbs != 1)
++ titan_ge_eth->tx_ring_skbs--;
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ return TITAN_OK;
++}
++
++/*
++ * Threshold beyond which we do the cleaning of
++ * Tx queue and new allocation for the Rx
++ * queue
++ */
++#define TX_THRESHOLD 4
++#define RX_THRESHOLD 10
++
++/*
++ * Receive the packets and send it to the kernel.
++ */
++static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ titan_ge_packet packet;
++ struct net_device_stats *stats;
++ struct sk_buff *skb;
++ unsigned long received_packets = 0;
++ unsigned int ack;
++
++ stats = &titan_ge_eth->stats;
++
++ while ((--max)
++ && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
++ skb = (struct sk_buff *) packet.skb;
++
++ titan_ge_eth->rx_ring_skbs--;
++
++ if (--titan_ge_eth->rx_work_limit < 0)
++ break;
++ received_packets++;
++
++ stats->rx_packets++;
++ stats->rx_bytes += packet.len;
++
++ if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
++ (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
++ (packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
++ (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
++ stats->rx_dropped++;
++ dev_kfree_skb_any(skb);
++
++ continue;
++ }
++ /*
++ * Either support fast path or slow path. Decision
++ * making can really slow down the performance. The
++ * idea is to cut down the number of checks and improve
++ * the fastpath.
++ */
++
++ skb_put(skb, packet.len - 2);
++
++ /*
++ * Increment data pointer by two since thats where
++ * the MAC starts
++ */
++ skb_reserve(skb, 2);
++ skb->protocol = eth_type_trans(skb, netdev);
++ netif_receive_skb(skb);
++
++ if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
++ ack = titan_ge_rx_task(netdev, titan_ge_eth);
++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
++ titan_ge_eth->rx_threshold = 0;
++ } else
++ titan_ge_eth->rx_threshold++;
++
++ if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
++ titan_ge_eth->tx_threshold = 0;
++ titan_ge_free_tx_queue(titan_ge_eth);
++ }
++ else
++ titan_ge_eth->tx_threshold++;
++
++ }
++ return received_packets;
++}
++
++
++/*
++ * Enable the Rx side interrupts
++ */
++static void titan_ge_enable_int(unsigned int port_num,
++ titan_ge_port_info *titan_ge_eth,
++ struct net_device *netdev)
++{
++ unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++ if (port_num == 0)
++ reg_data |= 0x3;
++ if (port_num == 1)
++ reg_data |= 0x300;
++ if (port_num == 2)
++ reg_data |= 0x30000;
++
++ /* Re-enable interrupts */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
++}
++
++/*
++ * Main function to handle the polling for Rx side NAPI.
++ * Receive interrupts have been disabled at this point.
++ * The poll schedules the transmit followed by receive.
++ */
++static int titan_ge_poll(struct net_device *netdev, int *budget)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ int port_num = titan_ge_eth->port_num;
++ int work_done = 0;
++ unsigned long flags, status;
++
++ titan_ge_eth->rx_work_limit = *budget;
++ if (titan_ge_eth->rx_work_limit > netdev->quota)
++ titan_ge_eth->rx_work_limit = netdev->quota;
++
++ do {
++ /* Do the transmit cleaning work here */
++ titan_ge_free_tx_queue(titan_ge_eth);
++
++ /* Ack the Rx interrupts */
++ if (port_num == 0)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
++ if (port_num == 1)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
++ if (port_num == 2)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
++
++ work_done += titan_ge_receive_queue(netdev, 0);
++
++ /* Out of quota and there is work to be done */
++ if (titan_ge_eth->rx_work_limit < 0)
++ goto not_done;
++
++ /* Receive alloc_skb could lead to OOM */
++ if (oom_flag == 1) {
++ oom_flag = 0;
++ goto oom;
++ }
++
++ status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++ } while (status & 0x30300);
++
++ /* If we are here, then no more interrupts to process */
++ goto done;
++
++not_done:
++ *budget -= work_done;
++ netdev->quota -= work_done;
++ return 1;
++
++oom:
++ printk(KERN_ERR "OOM \n");
++ netif_rx_complete(netdev);
++ return 0;
++
++done:
++ /*
++ * No more packets on the poll list. Turn the interrupts
++ * back on and we should be able to catch the new
++ * packets in the interrupt handler
++ */
++ if (!work_done)
++ work_done = 1;
++
++ *budget -= work_done;
++ netdev->quota -= work_done;
++
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ /* Remove us from the poll list */
++ netif_rx_complete(netdev);
++
++ /* Re-enable interrupts */
++ titan_ge_enable_int(port_num, titan_ge_eth, netdev);
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ return 0;
++}
++
++/*
++ * Close the network device
++ */
++int titan_ge_stop(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ spin_lock_irq(&(titan_ge_eth->lock));
++ titan_ge_eth_stop(netdev);
++ free_irq(netdev->irq, netdev);
++ spin_unlock_irq(&titan_ge_eth->lock);
++
++ return TITAN_OK;
++}
++
++/*
++ * Free the Tx ring
++ */
++static void titan_ge_free_tx_rings(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int curr;
++ unsigned long reg_data;
++
++ /* Stop the Tx DMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8));
++ reg_data |= 0xc0000000;
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8)), reg_data);
++
++ /* Disable the TMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ for (curr = 0;
++ (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
++ curr++) {
++ if (titan_ge_eth->tx_skb[curr]) {
++ dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
++ titan_ge_eth->tx_ring_skbs--;
++ }
++ }
++
++ if (titan_ge_eth->tx_ring_skbs != 0)
++ printk
++ ("%s: Error on Tx descriptor free - could not free %d"
++ " descriptors\n", netdev->name,
++ titan_ge_eth->tx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++ dma_free_coherent(&titan_ge_device[port_num]->dev,
++ titan_ge_eth->tx_desc_area_size,
++ (void *) titan_ge_eth->tx_desc_area,
++ titan_ge_eth->tx_dma);
++#endif
++}
++
++/*
++ * Free the Rx ring
++ */
++static void titan_ge_free_rx_rings(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int curr;
++ unsigned long reg_data;
++
++ /* Stop the Rx DMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8));
++ reg_data |= 0x000c0000;
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8)), reg_data);
++
++ /* Disable the RMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ for (curr = 0;
++ titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
++ curr++) {
++ if (titan_ge_eth->rx_skb[curr]) {
++ dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
++ titan_ge_eth->rx_ring_skbs--;
++ }
++ }
++
++ if (titan_ge_eth->rx_ring_skbs != 0)
++ printk(KERN_ERR
++ "%s: Error in freeing Rx Ring. %d skb's still"
++ " stuck in RX Ring - ignoring them\n", netdev->name,
++ titan_ge_eth->rx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++ dma_free_coherent(&titan_ge_device[port_num]->dev,
++ titan_ge_eth->rx_desc_area_size,
++ (void *) titan_ge_eth->rx_desc_area,
++ titan_ge_eth->rx_dma);
++#endif
++}
++
++/*
++ * Actually does the stop of the Ethernet device
++ */
++static void titan_ge_eth_stop(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ netif_stop_queue(netdev);
++
++ titan_ge_port_reset(titan_ge_eth->port_num);
++
++ titan_ge_free_tx_rings(netdev);
++ titan_ge_free_rx_rings(netdev);
++
++ /* Disable the Tx and Rx Interrupts for all channels */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
++}
++
++/*
++ * Update the MAC address. Note that we have to write the
++ * address in three station registers, 16 bits each. And this
++ * has to be done for TMAC and RMAC
++ */
++static void titan_ge_update_mac_address(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ u8 p_addr[6];
++
++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++ memcpy(p_addr, netdev->dev_addr, 6);
++
++ /* Update the Address Filtering Match tables */
++ titan_ge_update_afx(titan_ge_eth);
++
++ printk("Station MAC : %d %d %d %d %d %d \n",
++ p_addr[5], p_addr[4], p_addr[3],
++ p_addr[2], p_addr[1], p_addr[0]);
++
++ /* Set the MAC address here for TMAC and RMAC */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++}
++
++/*
++ * Set the MAC address of the Ethernet device
++ */
++static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
++{
++ titan_ge_port_info *tp = netdev_priv(dev);
++ struct sockaddr *sa = addr;
++
++ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
++
++ spin_lock_irq(&tp->lock);
++ titan_ge_update_mac_address(dev);
++ spin_unlock_irq(&tp->lock);
++
++ return 0;
++}
++
++/*
++ * Get the Ethernet device stats
++ */
++static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ return &titan_ge_eth->stats;
++}
++
++/*
++ * Initialize the Rx descriptor ring for the Titan Ge
++ */
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
++ int rx_desc_num,
++ int rx_buff_size,
++ unsigned long rx_desc_base_addr,
++ unsigned long rx_buff_base_addr,
++ unsigned long rx_dma)
++{
++ volatile titan_ge_rx_desc *rx_desc;
++ unsigned long buffer_addr;
++ int index;
++ unsigned long titan_ge_rx_desc_bus = rx_dma;
++
++ buffer_addr = rx_buff_base_addr;
++ rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
++
++ /* Check alignment */
++ if (rx_buff_base_addr & 0xF)
++ return 0;
++
++ /* Check Rx buffer size */
++ if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
++ return 0;
++
++ /* 64-bit alignment
++ if ((rx_buff_base_addr + rx_buff_size) & 0x7)
++ return 0; */
++
++ /* Initialize the Rx desc ring */
++ for (index = 0; index < rx_desc_num; index++) {
++ titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
++ rx_desc[index].cmd_sts = 0;
++ rx_desc[index].buffer_addr = buffer_addr;
++ titan_eth_port->rx_skb[index] = NULL;
++ buffer_addr += rx_buff_size;
++ }
++
++ titan_eth_port->rx_curr_desc_q = 0;
++ titan_eth_port->rx_used_desc_q = 0;
++
++ titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
++ titan_eth_port->rx_desc_area_size =
++ rx_desc_num * sizeof(titan_ge_rx_desc);
++
++ titan_eth_port->rx_dma = rx_dma;
++
++ return TITAN_OK;
++}
++
++/*
++ * Initialize the Tx descriptor ring. Descriptors in the SRAM
++ */
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
++ int tx_desc_num,
++ unsigned long tx_desc_base_addr,
++ unsigned long tx_dma)
++{
++ titan_ge_tx_desc *tx_desc;
++ int index;
++ unsigned long titan_ge_tx_desc_bus = tx_dma;
++
++ if (tx_desc_base_addr & 0xF)
++ return 0;
++
++ tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
++
++ for (index = 0; index < tx_desc_num; index++) {
++ titan_ge_port->tx_dma_array[index] =
++ (dma_addr_t) titan_ge_tx_desc_bus;
++ titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
++ tx_desc[index].cmd_sts = 0x0000;
++ tx_desc[index].buffer_len = 0;
++ tx_desc[index].buffer_addr = 0x00000000;
++ titan_ge_port->tx_skb[index] = NULL;
++ }
++
++ titan_ge_port->tx_curr_desc_q = 0;
++ titan_ge_port->tx_used_desc_q = 0;
++
++ titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
++ titan_ge_port->tx_desc_area_size =
++ tx_desc_num * sizeof(titan_ge_tx_desc);
++
++ titan_ge_port->tx_dma = tx_dma;
++ return TITAN_OK;
++}
++
++/*
++ * Initialize the device as an Ethernet device
++ */
++static int __init titan_ge_probe(struct device *device)
++{
++ titan_ge_port_info *titan_ge_eth;
++ struct net_device *netdev;
++ int port = to_platform_device(device)->id;
++ int err;
++
++ netdev = alloc_etherdev(sizeof(titan_ge_port_info));
++ if (!netdev) {
++ err = -ENODEV;
++ goto out;
++ }
++
++ netdev->open = titan_ge_open;
++ netdev->stop = titan_ge_stop;
++ netdev->hard_start_xmit = titan_ge_start_xmit;
++ netdev->get_stats = titan_ge_get_stats;
++ netdev->set_multicast_list = titan_ge_set_multi;
++ netdev->set_mac_address = titan_ge_set_mac_address;
++
++ /* Tx timeout */
++ netdev->tx_timeout = titan_ge_tx_timeout;
++ netdev->watchdog_timeo = 2 * HZ;
++
++ /* Set these to very high values */
++ netdev->poll = titan_ge_poll;
++ netdev->weight = 64;
++
++ netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
++ netif_carrier_off(netdev);
++ netdev->base_addr = 0;
++
++ netdev->change_mtu = titan_ge_change_mtu;
++
++ titan_ge_eth = netdev_priv(netdev);
++ /* Allocation of memory for the driver structures */
++
++ titan_ge_eth->port_num = port;
++
++ /* Configure the Tx timeout handler */
++ INIT_WORK(&titan_ge_eth->tx_timeout_task,
++ (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
++
++ spin_lock_init(&titan_ge_eth->lock);
++
++ /* set MAC addresses */
++ memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
++ netdev->dev_addr[5] += port;
++
++ err = register_netdev(netdev);
++
++ if (err)
++ goto out_free_netdev;
++
++ printk(KERN_NOTICE
++ "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
++ netdev->name, port, netdev->dev_addr[0],
++ netdev->dev_addr[1], netdev->dev_addr[2],
++ netdev->dev_addr[3], netdev->dev_addr[4],
++ netdev->dev_addr[5]);
++
++ printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
++
++ return 0;
++
++out_free_netdev:
++ kfree(netdev);
++
++out:
++ return err;
++}
++
++static void __devexit titan_device_remove(struct device *device)
++{
++}
++
++/*
++ * Reset the Ethernet port
++ */
++static void titan_ge_port_reset(unsigned int port_num)
++{
++ unsigned int reg_data;
++
++ /* Stop the Tx port activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x0001);
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ /* Stop the Rx port activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x0001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ return;
++}
++
++/*
++ * Return the Tx desc after use by the XDMA
++ */
++static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
++{
++ int tx_desc_used;
++ struct sk_buff *skb;
++
++ tx_desc_used = titan_ge_eth->tx_used_desc_q;
++
++ /* return right away */
++ if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
++ return TITAN_ERROR;
++
++ /* Now the critical stuff */
++ skb = titan_ge_eth->tx_skb[tx_desc_used];
++
++ dev_kfree_skb_any(skb);
++
++ titan_ge_eth->tx_skb[tx_desc_used] = NULL;
++ titan_ge_eth->tx_used_desc_q =
++ (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
++
++ return 0;
++}
++
++/*
++ * Coalescing for the Tx path
++ */
++static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
++{
++ unsigned long rx_delay;
++
++ rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
++ delay = (delay << 16) | rx_delay;
++
++ TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
++ TITAN_GE_WRITE(0x5038, delay);
++
++ return delay;
++}
++
++static struct device_driver titan_soc_driver = {
++ .name = titan_string,
++ .bus = &platform_bus_type,
++ .probe = titan_ge_probe,
++ .remove = __devexit_p(titan_device_remove),
++};
++
++static void titan_platform_release (struct device *device)
++{
++ struct platform_device *pldev;
++
++ /* free device */
++ pldev = to_platform_device (device);
++ kfree (pldev);
++}
++
++/*
++ * Register the Titan GE with the kernel
++ */
++static int __init titan_ge_init_module(void)
++{
++ struct platform_device *pldev;
++ unsigned int version, device;
++ int i;
++
++ printk(KERN_NOTICE
++ "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
++
++ titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
++ if (!titan_ge_base) {
++ printk("Mapping Titan GE failed\n");
++ goto out;
++ }
++
++ device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
++ version = (device & 0x000f0000) >> 16;
++ device &= 0x0000ffff;
++
++ printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version);
++
++#ifdef TITAN_RX_RING_IN_SRAM
++ titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
++ TITAN_SRAM_SIZE);
++ if (!titan_ge_sram) {
++ printk("Mapping Titan SRAM failed\n");
++ goto out_unmap_ge;
++ }
++#endif
++
++ if (driver_register(&titan_soc_driver)) {
++ printk(KERN_ERR "Driver registration failed\n");
++ goto out_unmap_sram;
++ }
++
++ for (i = 0; i < 3; i++) {
++ titan_ge_device[i] = NULL;
++
++ if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
++ continue;
++
++ memset (pldev, 0, sizeof (*pldev));
++ pldev->name = titan_string;
++ pldev->id = i;
++ pldev->dev.release = titan_platform_release;
++ titan_ge_device[i] = pldev;
++
++ if (platform_device_register (pldev)) {
++ kfree (pldev);
++ titan_ge_device[i] = NULL;
++ continue;
++ }
++
++ if (!pldev->dev.driver) {
++ /*
++ * The driver was not bound to this device, there was
++ * no hardware at this address. Unregister it, as the
++ * release fuction will take care of freeing the
++ * allocated structure
++ */
++ titan_ge_device[i] = NULL;
++ platform_device_unregister (pldev);
++ }
++ }
++
++ return 0;
++
++out_unmap_sram:
++ iounmap((void *)titan_ge_sram);
++
++out_unmap_ge:
++ iounmap((void *)titan_ge_base);
++
++out:
++ return -ENOMEM;
++}
++
++/*
++ * Unregister the Titan GE from the kernel
++ */
++static void __exit titan_ge_cleanup_module(void)
++{
++ int i;
++
++ driver_unregister(&titan_soc_driver);
++
++ for (i = 0; i < 3; i++) {
++ if (titan_ge_device[i]) {
++ platform_device_unregister (titan_ge_device[i]);
++ titan_ge_device[i] = NULL;
++ }
++ }
++
++ iounmap((void *)titan_ge_sram);
++ iounmap((void *)titan_ge_base);
++}
++
++MODULE_AUTHOR("Manish Lachwani <lachwani at pmc-sierra.com>");
++MODULE_DESCRIPTION("Titan GE Ethernet driver");
++MODULE_LICENSE("GPL");
++
++module_init(titan_ge_init_module);
++module_exit(titan_ge_cleanup_module);
+diff -urN --ignore-space-change kernel.org/drivers/net/titan_ge.h linux-mips/drivers/net/titan_ge.h
+--- kernel.org/drivers/net/titan_ge.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/titan_ge.h 2006-01-10 11:21:43.000000000 +0000
+@@ -0,0 +1,419 @@
++#ifndef _TITAN_GE_H_
++#define _TITAN_GE_H_
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/config.h>
++#include <linux/spinlock.h>
++#include <asm/byteorder.h>
++
++/*
++ * These functions should be later moved to a more generic location since there
++ * will be others accessing it also
++ */
++
++/*
++ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
++ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
++ * register.
++ */
++
++#define TITAN_GE_BASE 0xfe000000UL
++#define TITAN_GE_SIZE 0x10000UL
++
++extern unsigned long titan_ge_base;
++
++#define TITAN_GE_WRITE(offset, data) \
++ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
++
++#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
++
++#ifndef msec_delay
++#define msec_delay(x) do { if(in_interrupt()) { \
++ /* Don't mdelay in interrupt context! */ \
++ BUG(); \
++ } else { \
++ set_current_state(TASK_UNINTERRUPTIBLE); \
++ schedule_timeout((x * HZ)/1000); \
++ } } while(0)
++#endif
++
++#define TITAN_GE_PORT_0
++
++#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
++#define TITAN_SRAM_SIZE 0x2000UL
++
++extern unsigned long titan_ge_sram;
++
++/*
++ * We may need these constants
++ */
++#define TITAN_BIT0 0x00000001
++#define TITAN_BIT1 0x00000002
++#define TITAN_BIT2 0x00000004
++#define TITAN_BIT3 0x00000008
++#define TITAN_BIT4 0x00000010
++#define TITAN_BIT5 0x00000020
++#define TITAN_BIT6 0x00000040
++#define TITAN_BIT7 0x00000080
++#define TITAN_BIT8 0x00000100
++#define TITAN_BIT9 0x00000200
++#define TITAN_BIT10 0x00000400
++#define TITAN_BIT11 0x00000800
++#define TITAN_BIT12 0x00001000
++#define TITAN_BIT13 0x00002000
++#define TITAN_BIT14 0x00004000
++#define TITAN_BIT15 0x00008000
++#define TITAN_BIT16 0x00010000
++#define TITAN_BIT17 0x00020000
++#define TITAN_BIT18 0x00040000
++#define TITAN_BIT19 0x00080000
++#define TITAN_BIT20 0x00100000
++#define TITAN_BIT21 0x00200000
++#define TITAN_BIT22 0x00400000
++#define TITAN_BIT23 0x00800000
++#define TITAN_BIT24 0x01000000
++#define TITAN_BIT25 0x02000000
++#define TITAN_BIT26 0x04000000
++#define TITAN_BIT27 0x08000000
++#define TITAN_BIT28 0x10000000
++#define TITAN_BIT29 0x20000000
++#define TITAN_BIT30 0x40000000
++#define TITAN_BIT31 0x80000000
++
++/* Flow Control */
++#define TITAN_GE_FC_NONE 0x0
++#define TITAN_GE_FC_FULL 0x1
++#define TITAN_GE_FC_TX_PAUSE 0x2
++#define TITAN_GE_FC_RX_PAUSE 0x3
++
++/* Duplex Settings */
++#define TITAN_GE_FULL_DUPLEX 0x1
++#define TITAN_GE_HALF_DUPLEX 0x2
++
++/* Speed settings */
++#define TITAN_GE_SPEED_1000 0x1
++#define TITAN_GE_SPEED_100 0x2
++#define TITAN_GE_SPEED_10 0x3
++
++/* Debugging info only */
++#undef TITAN_DEBUG
++
++/* Keep the rings in the Titan's SSRAM */
++#define TITAN_RX_RING_IN_SRAM
++
++#ifdef CONFIG_64BIT
++#define TITAN_GE_IE_MASK 0xfffffffffb001b64
++#define TITAN_GE_IE_STATUS 0xfffffffffb001b60
++#else
++#define TITAN_GE_IE_MASK 0xfb001b64
++#define TITAN_GE_IE_STATUS 0xfb001b60
++#endif
+
- #include <asm/dec/machtype.h>
- #include <asm/dec/prom.h>
- #include <asm/dec/tcinfo.h>
- #include <asm/dec/tcmodule.h>
- #include <asm/dec/interrupts.h>
--#include <asm/paccess.h>
--#include <asm/ptrace.h>
--
--#define TC_DEBUG
-
- MODULE_LICENSE("GPL");
- slot_info tc_bus[MAX_SLOT];
- static int num_tcslots;
- static tcinfo *info;
-
--unsigned long system_base;
--
- /*
- * Interface to the world. Read comment in include/asm-mips/tc.h.
- */
-@@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
- static void __init tc_probe(unsigned long startaddr, unsigned long size,
- int slots)
- {
-+ unsigned long slotaddr;
- int i, slot, err;
- long offset;
-- unsigned char pattern[4];
-- unsigned char *module;
-+ u8 pattern[4];
-+ volatile u8 *module;
-
- for (slot = 0; slot < slots; slot++) {
-- module = (char *)(startaddr + slot * size);
-+ slotaddr = startaddr + slot * size;
-+ module = ioremap_nocache(slotaddr, size);
-+ BUG_ON(!module);
-
- offset = OLDCARD;
-
-@@ -112,8 +113,10 @@ static void __init tc_probe(unsigned lon
- err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
- err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
- err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
-- if (err)
-+ if (err) {
-+ iounmap(module);
- continue;
-+ }
-
- if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
- pattern[2] != 0xaa || pattern[3] != 0xff) {
-@@ -124,16 +127,20 @@ static void __init tc_probe(unsigned lon
- err |= get_dbe(pattern[1], module + TC_PATTERN1);
- err |= get_dbe(pattern[2], module + TC_PATTERN2);
- err |= get_dbe(pattern[3], module + TC_PATTERN3);
-- if (err)
-+ if (err) {
-+ iounmap(module);
- continue;
-+ }
- }
-
- if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
-- pattern[2] != 0xaa || pattern[3] != 0xff)
-+ pattern[2] != 0xaa || pattern[3] != 0xff) {
-+ iounmap(module);
- continue;
-+ }
-
-- tc_bus[slot].base_addr = (unsigned long)module;
-- for(i = 0; i < 8; i++) {
-+ tc_bus[slot].base_addr = slotaddr;
-+ for (i = 0; i < 8; i++) {
- tc_bus[slot].firmware[i] =
- module[TC_FIRM_VER + offset + 4 * i];
- tc_bus[slot].vendor[i] =
-@@ -171,13 +178,15 @@ static void __init tc_probe(unsigned lon
- tc_bus[slot].interrupt = -1;
- break;
- }
++/* Support for Jumbo Frames */
++#undef TITAN_GE_JUMBO_FRAMES
+
-+ iounmap(module);
- }
- }
-
- /*
- * the main entry
- */
--void __init tc_init(void)
-+static int __init tc_init(void)
- {
- int tc_clock;
- int i;
-@@ -185,7 +194,7 @@ void __init tc_init(void)
- unsigned long slot_size;
-
- if (!TURBOCHANNEL)
-- return;
-+ return 0;
-
- for (i = 0; i < MAX_SLOT; i++) {
- tc_bus[i].base_addr = 0;
-@@ -196,8 +205,8 @@ void __init tc_init(void)
- tc_bus[i].flags = FREE;
- }
-
-- info = (tcinfo *) rex_gettcinfo();
-- slot0addr = (unsigned long)KSEG1ADDR(rex_slot_address(0));
-+ info = rex_gettcinfo();
-+ slot0addr = CPHYSADDR((long)rex_slot_address(0));
-
- switch (mips_machtype) {
- case MACH_DS5000_200:
-@@ -216,37 +225,24 @@ void __init tc_init(void)
-
- tc_clock = 10000 / info->clk_period;
-
-- if (TURBOCHANNEL && info->slot_size && slot0addr) {
-- printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision,
-- tc_clock / 10, tc_clock % 10);
-- printk("(with%s parity)\n", info->parity ? "" : "out");
-+ if (info->slot_size && slot0addr) {
-+ pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
-+ info->revision, tc_clock / 10, tc_clock % 10,
-+ info->parity ? "" : "out");
-
- slot_size = info->slot_size << 20;
-
- tc_probe(slot0addr, slot_size, num_tcslots);
-
-- /*
-- * All TURBOchannel DECstations have the onboard devices
-- * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module
-- * would be.
-- */
-- if(mips_machtype == MACH_DS5000_XX)
-- i = 1;
-- else
-- i = 0;
--
-- system_base = slot0addr + slot_size * (num_tcslots + i);
--
--#ifdef TC_DEBUG
-- for (i = 0; i < num_tcslots; i++)
-- if (tc_bus[i].base_addr) {
-- printk(" slot %d: ", i);
-- printk("%s %s %s\n", tc_bus[i].vendor,
-- tc_bus[i].name, tc_bus[i].firmware);
-- }
--#endif
-- ioport_resource.end = KSEG2 - 1;
-+ for (i = 0; i < num_tcslots; i++) {
-+ if (!tc_bus[i].base_addr)
-+ continue;
-+ pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
-+ tc_bus[i].name, tc_bus[i].firmware);
-+ }
- }
++/* Rx buffer size */
++#ifdef TITAN_GE_JUMBO_FRAMES
++#define TITAN_GE_JUMBO_BUFSIZE 9080
++#else
++#define TITAN_GE_STD_BUFSIZE 1580
++#endif
+
-+ return 0;
- }
-
- subsys_initcall(tc_init);
-@@ -257,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
- EXPORT_SYMBOL(get_tc_base_addr);
- EXPORT_SYMBOL(get_tc_irq_nr);
- EXPORT_SYMBOL(get_tc_speed);
--EXPORT_SYMBOL(system_base);
-diff -urpNX dontdiff linux-2.6.12/drivers/tc/zs.c linux_HEAD/drivers/tc/zs.c
---- linux-2.6.12/drivers/tc/zs.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/tc/zs.c 2005-07-03 16:44:34.000000000 +0200
-@@ -6,7 +6,7 @@
- *
- * DECstation changes
- * Copyright (C) 1998-2000 Harald Koerfgen
-- * Copyright (C) 2000, 2001, 2002, 2003, 2004 Maciej W. Rozycki
-+ * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005 Maciej W. Rozycki
- *
- * For the rest of the code the original Copyright applies:
- * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras at cs.anu.edu.au)
-@@ -55,6 +55,7 @@
- #include <linux/delay.h>
- #include <linux/init.h>
- #include <linux/ioport.h>
-+#include <linux/spinlock.h>
- #ifdef CONFIG_SERIAL_DEC_CONSOLE
- #include <linux/console.h>
- #endif
-@@ -63,16 +64,15 @@
- #include <asm/pgtable.h>
- #include <asm/irq.h>
- #include <asm/system.h>
--#include <asm/uaccess.h>
- #include <asm/bootinfo.h>
--#include <asm/dec/serial.h>
-
--#ifdef CONFIG_MACH_DECSTATION
- #include <asm/dec/interrupts.h>
-+#include <asm/dec/ioasic_addrs.h>
- #include <asm/dec/machtype.h>
-+#include <asm/dec/serial.h>
-+#include <asm/dec/system.h>
- #include <asm/dec/tc.h>
--#include <asm/dec/ioasic_addrs.h>
--#endif
++/*
++ * Tx and Rx Interrupt Coalescing parameter. These values are
++ * for 1 Ghz processor. Rx coalescing can be taken care of
++ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
++ * is not adaptive. Hence, these values need to be adjusted
++ * based on load, CPU speed etc.
++ */
++#define TITAN_GE_RX_COAL 150
++#define TITAN_GE_TX_COAL 300
+
- #ifdef CONFIG_KGDB
- #include <asm/kgdb.h>
- #endif
-@@ -128,6 +128,8 @@ static struct zs_parms ds_parms = {
-
- #define BUS_PRESENT (DS_BUS_PRESENT)
-
-+DEFINE_SPINLOCK(zs_lock);
++#if defined(__BIG_ENDIAN)
+
- struct dec_zschannel zs_channels[NUM_CHANNELS];
- struct dec_serial zs_soft[NUM_CHANNELS];
- int zs_channels_found;
-@@ -159,8 +161,6 @@ static unsigned char zs_init_regs[16] __
- 0 /* write 15 */
- };
-
--DECLARE_TASK_QUEUE(tq_zs_serial);
--
- static struct tty_driver *serial_driver;
-
- /* serial subtype definitions */
-@@ -192,18 +192,6 @@ static void probe_sccs(void);
- static void change_speed(struct dec_serial *info);
- static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
-
--/*
-- * tmp_buf is used as a temporary buffer by serial_write. We need to
-- * lock it in case the copy_from_user blocks while swapping in a page,
-- * and some other program tries to do a serial write at the same time.
-- * Since the lock will only come under contention when the system is
-- * swapping and available memory is low, it makes sense to share one
-- * buffer across all the serial ports, since it significantly saves
-- * memory if large numbers of serial ports are open.
-- */
--static unsigned char tmp_buf[4096]; /* This is cheating */
--static DECLARE_MUTEX(tmp_buf_sem);
--
- static inline int serial_paranoia_check(struct dec_serial *info,
- char *name, const char *routine)
- {
-@@ -306,8 +294,7 @@ static inline void zs_rtsdtr(struct dec_
- {
- unsigned long flags;
-
--
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- if (info->zs_channel != info->zs_chan_a) {
- if (set) {
- info->zs_chan_a->curregs[5] |= (which & (RTS | DTR));
-@@ -316,7 +303,7 @@ static inline void zs_rtsdtr(struct dec_
- }
- write_zsreg(info->zs_chan_a, 5, info->zs_chan_a->curregs[5]);
- }
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- /* Utility routines for the Zilog */
-@@ -357,12 +344,10 @@ static inline void rs_recv_clear(struct
- * This routine is used by the interrupt handler to schedule
- * processing in the software interrupt portion of the driver.
- */
--static _INLINE_ void rs_sched_event(struct dec_serial *info,
-- int event)
-+static _INLINE_ void rs_sched_event(struct dec_serial *info, int event)
- {
- info->event |= 1 << event;
-- queue_task(&info->tqueue, &tq_zs_serial);
-- mark_bh(SERIAL_BH);
-+ tasklet_schedule(&info->tlet);
- }
-
- static _INLINE_ void receive_chars(struct dec_serial *info,
-@@ -509,9 +494,10 @@ static _INLINE_ void status_handle(struc
- /*
- * This is the serial driver's generic interrupt routine
- */
--void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs)
-+static irqreturn_t rs_interrupt(int irq, void *dev_id, struct pt_regs *regs)
- {
- struct dec_serial *info = (struct dec_serial *) dev_id;
-+ irqreturn_t status = IRQ_NONE;
- unsigned char zs_intreg;
- int shift;
-
-@@ -533,6 +519,8 @@ void rs_interrupt(int irq, void *dev_id,
- if ((zs_intreg & CHAN_IRQMASK) == 0)
- break;
-
-+ status = IRQ_HANDLED;
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++ u32 reserved; /* Unused */
++ u32 buffer_addr; /* CPU buffer address */
++ u32 cmd_sts; /* Command and Status */
++ u32 buffer; /* XDMA buffer address */
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++ u16 cmd_sts; /* Command, Status and Buffer count */
++ u16 buffer_len; /* Length of the buffer */
++ u32 buffer_addr; /* Physical address of the buffer */
++} titan_ge_tx_desc;
++
++#elif defined(__LITTLE_ENDIAN)
++
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++ u32 buffer_addr; /* CPU buffer address */
++ u32 reserved; /* Unused */
++ u32 buffer; /* XDMA buffer address */
++ u32 cmd_sts; /* Command and Status */
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++ u32 buffer_addr; /* Physical address of the buffer */
++ u16 buffer_len; /* Length of the buffer */
++ u16 cmd_sts; /* Command, Status and Buffer count */
++} titan_ge_tx_desc;
++#endif
++
++/* Default Tx Queue Size */
++#define TITAN_GE_TX_QUEUE 128
++#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
++
++/* Default Rx Queue Size */
++#define TITAN_GE_RX_QUEUE 64
++#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
++
++/* Packet Structure */
++typedef struct _pkt_info {
++ unsigned int len;
++ unsigned int cmd_sts;
++ unsigned int buffer;
++ struct sk_buff *skb;
++ unsigned int checksum;
++} titan_ge_packet;
++
++
++#define PHYS_CNT 3
++
++/* Titan Port specific data structure */
++typedef struct _eth_port_ctrl {
++ unsigned int port_num;
++ u8 port_mac_addr[6];
++
++ /* Rx descriptor pointers */
++ int rx_curr_desc_q, rx_used_desc_q;
++
++ /* Tx descriptor pointers */
++ int tx_curr_desc_q, tx_used_desc_q;
++
++ /* Rx descriptor area */
++ volatile titan_ge_rx_desc *rx_desc_area;
++ unsigned int rx_desc_area_size;
++ struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE];
++
++ /* Tx Descriptor area */
++ volatile titan_ge_tx_desc *tx_desc_area;
++ unsigned int tx_desc_area_size;
++ struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE];
++
++ /* Timeout task */
++ struct work_struct tx_timeout_task;
++
++ /* DMA structures and handles */
++ dma_addr_t tx_dma;
++ dma_addr_t rx_dma;
++ dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE];
++
++ /* Device lock */
++ spinlock_t lock;
++
++ unsigned int tx_ring_skbs;
++ unsigned int rx_ring_size;
++ unsigned int tx_ring_size;
++ unsigned int rx_ring_skbs;
++
++ struct net_device_stats stats;
++
++ /* Tx and Rx coalescing */
++ unsigned long rx_int_coal;
++ unsigned long tx_int_coal;
++
++ /* Threshold for replenishing the Rx and Tx rings */
++ unsigned int tx_threshold;
++ unsigned int rx_threshold;
++
++ /* NAPI work limit */
++ unsigned int rx_work_limit;
++} titan_ge_port_info;
++
++/* Titan specific constants */
++#define TITAN_ETH_PORT_IRQ 3
++
++/* Max Rx buffer */
++#define TITAN_GE_MAX_RX_BUFFER 65536
++
++/* Tx and Rx Error */
++#define TITAN_GE_ERROR
++
++/* Rx Descriptor Command and Status */
++
++#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */
++#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */
++#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */
++#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */
++#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */
++#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */
++#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */
++#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */
++#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */
++#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */
++
++/* Tx Descriptor Command */
++#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */
++#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */
++
++/* Return Status */
++#define TITAN_OK 0x1 /* Good Status */
++#define TITAN_ERROR 0x2 /* Error Status */
++
++/* MIB specific register offset */
++#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */
++#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */
++#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */
++
++/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
++#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040
++#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050
++#define TITAN_GE_MSTATX_RXFRAMES 0x0060
++#define TITAN_GE_MSTATX_RXOCTETS 0x0070
++#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080
++#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090
++#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0
++#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0
++#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0
++#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0
++#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0
++#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0
++#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100
++#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110
++#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120
++#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130
++#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140
++#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150
++#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160
++#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170
++#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180
++#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190
++#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0
++#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0
++#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0
++#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0
++#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0
++#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0
++#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200
++#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210
++#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220
++#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230
++#define TITAN_GE_MSTATX_HASHFILTERED 0x0240
++#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250
++#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260
++#define TITAN_GE_MSTATX_TXOCTETS 0x0270
++#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280
++#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290
++#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0
++#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0
++#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0
++#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0
++#define TITAN_GE_MSTATX_TXMACERROR 0x02E0
++#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0
++#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360
++#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370
++#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380
++#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390
++#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0
++#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0
++#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0
++#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0
++#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0
++#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0
++#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400
++#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410
++#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420
++#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430
++#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440
+
- if (zs_intreg & CHBRxIP) {
- receive_chars(info, regs);
- }
-@@ -546,6 +534,8 @@ void rs_interrupt(int irq, void *dev_id,
-
- /* Why do we need this ? */
- write_zsreg(info->zs_channel, 0, RES_H_IUS);
++/* Interrupt specific defines */
++#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */
++#define TITAN_GE_RESET 0x0004 /* Reset reg */
++#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */
++#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */
++#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */
++#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/
++#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/
++#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */
++#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */
++#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */
++#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */
++#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */
++#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */
++#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */
++#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */
++#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */
++#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */
++#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */
+
-+ return status;
- }
-
- #ifdef ZS_DEBUG_REGS
-@@ -590,12 +580,12 @@ static void rs_stop(struct tty_struct *t
- return;
-
- #if 1
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- if (info->zs_channel->curregs[5] & TxENAB) {
- info->zs_channel->curregs[5] &= ~TxENAB;
- write_zsreg(info->zs_channel, 5, info->zs_channel->curregs[5]);
- }
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- #endif
- }
-
-@@ -607,7 +597,7 @@ static void rs_start(struct tty_struct *
- if (serial_paranoia_check(info, tty->name, "rs_start"))
- return;
-
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- #if 1
- if (info->xmit_cnt && info->xmit_buf && !(info->zs_channel->curregs[5] & TxENAB)) {
- info->zs_channel->curregs[5] |= TxENAB;
-@@ -618,7 +608,7 @@ static void rs_start(struct tty_struct *
- transmit_chars(info);
- }
- #endif
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- /*
-@@ -630,12 +620,8 @@ static void rs_start(struct tty_struct *
- * interrupt driver proper are done; the interrupt driver schedules
- * them using rs_sched_event(), and they get done here.
- */
--static void do_serial_bh(void)
--{
-- run_task_queue(&tq_zs_serial);
--}
-
--static void do_softint(void *private_)
-+static void do_softint(unsigned long private_)
- {
- struct dec_serial *info = (struct dec_serial *) private_;
- struct tty_struct *tty;
-@@ -646,10 +632,11 @@ static void do_softint(void *private_)
-
- if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) {
- tty_wakeup(tty);
-+ wake_up_interruptible(&tty->write_wait);
- }
- }
-
--int zs_startup(struct dec_serial * info)
-+static int zs_startup(struct dec_serial * info)
- {
- unsigned long flags;
-
-@@ -662,7 +649,7 @@ int zs_startup(struct dec_serial * info)
- return -ENOMEM;
- }
-
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
-
- #ifdef SERIAL_DEBUG_OPEN
- printk("starting up ttyS%d (irq %d)...", info->line, info->irq);
-@@ -718,7 +705,7 @@ int zs_startup(struct dec_serial * info)
- info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
-
- info->flags |= ZILOG_INITIALIZED;
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- return 0;
- }
-
-@@ -738,7 +725,7 @@ static void shutdown(struct dec_serial *
- info->irq);
- #endif
-
-- save_flags(flags); cli(); /* Disable interrupts */
-+ spin_lock_irqsave(&zs_lock, flags);
-
- if (info->xmit_buf) {
- free_page((unsigned long) info->xmit_buf);
-@@ -761,7 +748,7 @@ static void shutdown(struct dec_serial *
- set_bit(TTY_IO_ERROR, &info->tty->flags);
-
- info->flags &= ~ZILOG_INITIALIZED;
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- /*
-@@ -797,7 +784,7 @@ static void change_speed(struct dec_seri
- i += 15;
- }
-
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- info->zs_baud = baud_table[i];
- if (info->zs_baud) {
- brg = BPS_TO_BRG(info->zs_baud, zs_parms->clock/info->clk_divisor);
-@@ -870,7 +857,7 @@ static void change_speed(struct dec_seri
- /* Load up the new values */
- load_zsregs(info->zs_channel, info->zs_channel->curregs);
-
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- static void rs_flush_chars(struct tty_struct *tty)
-@@ -886,9 +873,9 @@ static void rs_flush_chars(struct tty_st
- return;
-
- /* Enable transmitter */
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- transmit_chars(info);
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- static int rs_write(struct tty_struct * tty,
-@@ -904,26 +891,17 @@ static int rs_write(struct tty_struct *
- if (!tty || !info->xmit_buf)
- return 0;
-
-- save_flags(flags);
- while (1) {
-- cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- c = min(count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
- SERIAL_XMIT_SIZE - info->xmit_head));
- if (c <= 0)
- break;
-
-- if (from_user) {
-- down(&tmp_buf_sem);
-- copy_from_user(tmp_buf, buf, c);
-- c = min(c, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
-- SERIAL_XMIT_SIZE - info->xmit_head));
-- memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c);
-- up(&tmp_buf_sem);
-- } else
-- memcpy(info->xmit_buf + info->xmit_head, buf, c);
-+ memcpy(info->xmit_buf + info->xmit_head, buf, c);
- info->xmit_head = (info->xmit_head + c) & (SERIAL_XMIT_SIZE-1);
- info->xmit_cnt += c;
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- buf += c;
- count -= c;
- total += c;
-@@ -932,7 +910,7 @@ static int rs_write(struct tty_struct *
- if (info->xmit_cnt && !tty->stopped && !info->tx_stopped
- && !info->tx_active)
- transmit_chars(info);
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- return total;
- }
-
-@@ -964,9 +942,9 @@ static void rs_flush_buffer(struct tty_s
-
- if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
- return;
-- cli();
-+ spin_lock_irq(&zs_lock);
- info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
-- sti();
-+ spin_unlock_irq(&zs_lock);
- tty_wakeup(tty);
- }
-
-@@ -994,11 +972,11 @@ static void rs_throttle(struct tty_struc
- return;
-
- if (I_IXOFF(tty)) {
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- info->x_char = STOP_CHAR(tty);
- if (!info->tx_active)
- transmit_chars(info);
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- if (C_CRTSCTS(tty)) {
-@@ -1022,7 +1000,7 @@ static void rs_unthrottle(struct tty_str
- return;
-
- if (I_IXOFF(tty)) {
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- if (info->x_char)
- info->x_char = 0;
- else {
-@@ -1030,7 +1008,7 @@ static void rs_unthrottle(struct tty_str
- if (!info->tx_active)
- transmit_chars(info);
- }
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- if (C_CRTSCTS(tty)) {
-@@ -1123,9 +1101,9 @@ static int get_lsr_info(struct dec_seria
- {
- unsigned char status;
-
-- cli();
-+ spin_lock(&zs_lock);
- status = read_zsreg(info->zs_channel, 0);
-- sti();
-+ spin_unlock_irq(&zs_lock);
- put_user(status,value);
- return 0;
- }
-@@ -1148,11 +1126,11 @@ static int rs_tiocmget(struct tty_struct
- if (info->zs_channel == info->zs_chan_a)
- result = 0;
- else {
-- cli();
-+ spin_lock(&zs_lock);
- control = info->zs_chan_a->curregs[5];
- status_a = read_zsreg(info->zs_chan_a, 0);
- status_b = read_zsreg(info->zs_channel, 0);
-- sti();
-+ spin_unlock_irq(&zs_lock);
- result = ((control & RTS) ? TIOCM_RTS: 0)
- | ((control & DTR) ? TIOCM_DTR: 0)
- | ((status_b & DCD) ? TIOCM_CAR: 0)
-@@ -1167,8 +1145,6 @@ static int rs_tiocmset(struct tty_struct
- unsigned int set, unsigned int clear)
- {
- struct dec_serial * info = (struct dec_serial *)tty->driver_data;
-- int error;
-- unsigned int arg, bits;
-
- if (info->hook)
- return -ENODEV;
-@@ -1182,8 +1158,7 @@ static int rs_tiocmset(struct tty_struct
- if (info->zs_channel == info->zs_chan_a)
- return 0;
-
-- get_user(arg, value);
-- cli();
-+ spin_lock(&zs_lock);
- if (set & TIOCM_RTS)
- info->zs_chan_a->curregs[5] |= RTS;
- if (set & TIOCM_DTR)
-@@ -1193,7 +1168,7 @@ static int rs_tiocmset(struct tty_struct
- if (clear & TIOCM_DTR)
- info->zs_chan_a->curregs[5] &= ~DTR;
- write_zsreg(info->zs_chan_a, 5, info->zs_chan_a->curregs[5]);
-- sti();
-+ spin_unlock_irq(&zs_lock);
- return 0;
- }
-
-@@ -1210,19 +1185,18 @@ static void rs_break(struct tty_struct *
- if (!info->port)
- return;
-
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
- if (break_state == -1)
- info->zs_channel->curregs[5] |= SND_BRK;
- else
- info->zs_channel->curregs[5] &= ~SND_BRK;
- write_zsreg(info->zs_channel, 5, info->zs_channel->curregs[5]);
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- static int rs_ioctl(struct tty_struct *tty, struct file * file,
- unsigned int cmd, unsigned long arg)
- {
-- int error;
- struct dec_serial * info = (struct dec_serial *)tty->driver_data;
-
- if (info->hook)
-@@ -1299,10 +1273,10 @@ static void rs_close(struct tty_struct *
- if (!info || serial_paranoia_check(info, tty->name, "rs_close"))
- return;
-
-- save_flags(flags); cli();
-+ spin_lock_irqsave(&zs_lock, flags);
-
- if (tty_hung_up_p(filp)) {
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- return;
- }
-
-@@ -1327,7 +1301,7 @@ static void rs_close(struct tty_struct *
- info->count = 0;
- }
- if (info->count) {
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- return;
- }
- info->flags |= ZILOG_CLOSING;
-@@ -1370,7 +1344,7 @@ static void rs_close(struct tty_struct *
- }
- info->flags &= ~(ZILOG_NORMAL_ACTIVE|ZILOG_CLOSING);
- wake_up_interruptible(&info->close_wait);
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- /*
-@@ -1410,7 +1384,7 @@ static void rs_wait_until_sent(struct tt
- /*
- * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
- */
--void rs_hangup(struct tty_struct *tty)
-+static void rs_hangup(struct tty_struct *tty)
- {
- struct dec_serial * info = (struct dec_serial *)tty->driver_data;
-
-@@ -1478,16 +1452,16 @@ static int block_til_ready(struct tty_st
- printk("block_til_ready before block: ttyS%d, count = %d\n",
- info->line, info->count);
- #endif
-- cli();
-+ spin_lock(&zs_lock);
- if (!tty_hung_up_p(filp))
- info->count--;
-- sti();
-+ spin_unlock_irq(&zs_lock);
- info->blocked_open++;
- while (1) {
-- cli();
-+ spin_lock(&zs_lock);
- if (tty->termios->c_cflag & CBAUD)
- zs_rtsdtr(info, RTS | DTR, 1);
-- sti();
-+ spin_unlock_irq(&zs_lock);
- set_current_state(TASK_INTERRUPTIBLE);
- if (tty_hung_up_p(filp) ||
- !(info->flags & ZILOG_INITIALIZED)) {
-@@ -1535,7 +1509,7 @@ static int block_til_ready(struct tty_st
- * the IRQ chain. It also performs the serial-specific
- * initialization for the tty structure.
- */
--int rs_open(struct tty_struct *tty, struct file * filp)
-+static int rs_open(struct tty_struct *tty, struct file * filp)
- {
- struct dec_serial *info;
- int retval, line;
-@@ -1628,30 +1602,22 @@ static void __init probe_sccs(void)
- return;
- }
-
-- /*
-- * When serial console is activated, tc_init has not been called yet
-- * and system_base is undefined. Unfortunately we have to hardcode
-- * system_base for this case :-(. HK
-- */
- switch(mips_machtype) {
- #ifdef CONFIG_MACH_DECSTATION
- case MACH_DS5000_2X0:
- case MACH_DS5900:
-- system_base = KSEG1ADDR(0x1f800000);
- n_chips = 2;
- zs_parms = &ds_parms;
- zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
- zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
- break;
- case MACH_DS5000_1XX:
-- system_base = KSEG1ADDR(0x1c000000);
- n_chips = 2;
- zs_parms = &ds_parms;
- zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
- zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
- break;
- case MACH_DS5000_XX:
-- system_base = KSEG1ADDR(0x1c000000);
- n_chips = 1;
- zs_parms = &ds_parms;
- zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
-@@ -1673,10 +1639,10 @@ static void __init probe_sccs(void)
- * The sccs reside on the high byte of the 16 bit IOBUS
- */
- zs_channels[n_channels].control =
-- (volatile unsigned char *)system_base +
-+ (volatile void *)CKSEG1ADDR(dec_kn_slot_base +
- (0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
- (0 == channel ? zs_parms->channel_a_offset :
-- zs_parms->channel_b_offset);
-+ zs_parms->channel_b_offset));
- zs_channels[n_channels].data =
- zs_channels[n_channels].control + 4;
-
-@@ -1726,7 +1692,7 @@ static void __init probe_sccs(void)
- }
- }
-
-- save_and_cli(flags);
-+ spin_lock_irqsave(&zs_lock, flags);
- for (n = 0; n < zs_channels_found; n++) {
- if (n % 2 == 0) {
- write_zsreg(zs_soft[n].zs_chan_a, R9, FHWRES);
-@@ -1736,7 +1702,7 @@ static void __init probe_sccs(void)
- load_zsregs(zs_soft[n].zs_channel,
- zs_soft[n].zs_channel->curregs);
- }
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
- }
-
- static struct tty_operations serial_ops = {
-@@ -1769,9 +1735,6 @@ int __init zs_init(void)
- if(!BUS_PRESENT)
- return -ENODEV;
-
-- /* Setup base handler, and timer table. */
-- init_bh(SERIAL_BH, do_serial_bh);
--
- /* Find out how many Z8530 SCCs we have */
- if (zs_chain == 0)
- probe_sccs();
-@@ -1820,8 +1783,7 @@ int __init zs_init(void)
- info->event = 0;
- info->count = 0;
- info->blocked_open = 0;
-- info->tqueue.routine = do_softint;
-- info->tqueue.data = info;
-+ tasklet_init(&info->tlet, do_softint, (unsigned long)info);
- init_waitqueue_head(&info->open_wait);
- init_waitqueue_head(&info->close_wait);
- printk("ttyS%02d at 0x%08x (irq = %d) is a Z85C30 SCC\n",
-@@ -1853,8 +1815,7 @@ int __init zs_init(void)
- /*
- * polling I/O routines
- */
--static int
--zs_poll_tx_char(void *handle, unsigned char ch)
-+static int zs_poll_tx_char(void *handle, unsigned char ch)
- {
- struct dec_serial *info = handle;
- struct dec_zschannel *chan = info->zs_channel;
-@@ -1877,8 +1838,7 @@ zs_poll_tx_char(void *handle, unsigned c
- return -ENODEV;
- }
-
--static int
--zs_poll_rx_char(void *handle)
-+static int zs_poll_rx_char(void *handle)
- {
- struct dec_serial *info = handle;
- struct dec_zschannel *chan = info->zs_channel;
-@@ -2057,7 +2017,7 @@ static int __init serial_console_setup(s
- }
- co->cflag = cflag;
-
-- save_and_cli(flags);
-+ spin_lock_irqsave(&zs_lock, flags);
-
- /*
- * Set up the baud rate generator.
-@@ -2112,7 +2072,7 @@ static int __init serial_console_setup(s
- zs_soft[co->index].clk_divisor = clk_divisor;
- zs_soft[co->index].zs_baud = get_zsbaud(&zs_soft[co->index]);
-
-- restore_flags(flags);
-+ spin_unlock_irqrestore(&zs_lock, flags);
-
- return 0;
- }
-@@ -2249,5 +2209,3 @@ void __init zs_kgdb_hook(int tty_num)
- set_debug_traps(); /* init stub */
- }
- #endif /* ifdef CONFIG_KGDB */
--
--
-diff -urpNX dontdiff linux-2.6.12/drivers/tc/zs.h linux_HEAD/drivers/tc/zs.h
---- linux-2.6.12/drivers/tc/zs.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/tc/zs.h 2005-07-10 12:28:27.000000000 +0200
-@@ -6,14 +6,14 @@
- *
- * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras at cs.anu.edu.au)
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
-- * Copyright (C) 2004 Maciej W. Rozycki
-+ * Copyright (C) 2004, 2005 Maciej W. Rozycki
- */
- #ifndef _DECSERIAL_H
- #define _DECSERIAL_H
-
- #include <asm/dec/serial.h>
-
--#define NUM_ZSREGS 16
-+#define NUM_ZSREGS 16
-
- struct serial_struct {
- int type;
-@@ -139,8 +139,7 @@ struct dec_serial {
- int xmit_head;
- int xmit_tail;
- int xmit_cnt;
-- struct tq_struct tqueue;
-- struct tq_struct tqueue_hangup;
-+ struct tasklet_struct tlet;
- wait_queue_head_t open_wait;
- wait_queue_head_t close_wait;
- };
-@@ -282,7 +281,7 @@ struct dec_serial {
- #define DLC 4 /* Disable Lower Chain */
- #define MIE 8 /* Master Interrupt Enable */
- #define STATHI 0x10 /* Status high */
--#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
-+#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
- #define NORESET 0 /* No reset on write to R9 */
- #define CHRB 0x40 /* Reset channel B */
- #define CHRA 0x80 /* Reset channel A */
-@@ -395,8 +394,8 @@ struct dec_serial {
- /* Read Register 15 (value of WR 15) */
-
- /* Misc macros */
--#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
--#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
-+#define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
-+#define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
- garbage = read_zsdata(channel); \
- garbage = read_zsdata(channel); \
- garbage = read_zsdata(channel); \
-diff -urpNX dontdiff linux-2.6.12/drivers/usb/gadget/net2280.c linux_HEAD/drivers/usb/gadget/net2280.c
---- linux-2.6.12/drivers/usb/gadget/net2280.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/usb/gadget/net2280.c 2005-04-08 22:41:12.000000000 +0200
-@@ -448,7 +448,8 @@ net2280_free_request (struct usb_ep *_ep
- #elif defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
- #define USE_KMALLOC
-
--#elif defined(CONFIG_MIPS) && !defined(CONFIG_NONCOHERENT_IO)
-+#elif defined(CONFIG_MIPS) && \
-+ (defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27))
- #define USE_KMALLOC
-
- /* FIXME there are other cases, including an x86-64 one ... */
-diff -urpNX dontdiff linux-2.6.12/drivers/usb/host/ohci-au1xxx.c linux_HEAD/drivers/usb/host/ohci-au1xxx.c
---- linux-2.6.12/drivers/usb/host/ohci-au1xxx.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/usb/host/ohci-au1xxx.c 2005-07-10 12:28:27.000000000 +0200
-@@ -89,12 +89,12 @@ int usb_hcd_au1xxx_probe (const struct h
- int retval;
- struct usb_hcd *hcd;
-
-- if(dev->resource[1].flags != IORESOURCE_IRQ) {
-+ if (dev->resource[1].flags != IORESOURCE_IRQ) {
- pr_debug ("resource[1] is not IORESOURCE_IRQ");
-- return -ENOMEM;
-+ retval = -ENOMEM;
- }
-
-- hcd = usb_create_hcd(driver, &dev->dev, "au1xxx");
-+ hcd = usb_create_hcd(driver, &dev->dev, "Au1xxx");
- if (!hcd)
- return -ENOMEM;
- hcd->rsrc_start = dev->resource[0].start;
-diff -urpNX dontdiff linux-2.6.12/drivers/usb/host/ohci-hcd.c linux_HEAD/drivers/usb/host/ohci-hcd.c
---- linux-2.6.12/drivers/usb/host/ohci-hcd.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/usb/host/ohci-hcd.c 2005-04-08 22:41:12.000000000 +0200
-@@ -901,10 +901,6 @@ MODULE_LICENSE ("GPL");
- #include "ohci-lh7a404.c"
- #endif
-
--#ifdef CONFIG_PXA27x
--#include "ohci-pxa27x.c"
--#endif
--
- #ifdef CONFIG_SOC_AU1X00
- #include "ohci-au1xxx.c"
- #endif
-diff -urpNX dontdiff linux-2.6.12/drivers/video/Kconfig linux_HEAD/drivers/video/Kconfig
---- linux-2.6.12/drivers/video/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/Kconfig 2005-07-10 12:16:34.000000000 +0200
-@@ -1164,6 +1164,19 @@ config FB_VOODOO1
- Please read the <file:Documentation/fb/README-sstfb.txt> for supported
- options and other important info support.
-
-+config FB_SMIVGX
-+ tristate "Silicon Motion VoyagerGX support"
-+ depends on FB && PCI && (MIPS || EXPERIMENTAL)
-+ select FB_CFB_FILLRECT
-+ select FB_CFB_COPYAREA
-+ select FB_CFB_IMAGEBLIT
-+ select FB_SOFT_CURSOR
-+ ---help---
-+ This drivers supports SMI VoyagerGX 501 based PCI boards
-+ The default settings drive both a CRT and LCD. The CRT
-+ can be turned off by passing in the no_crt option
-+
++/* Rx MAC defines */
++#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */
++#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */
++#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */
++#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */
++#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */
++#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */
++#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */
+
- config FB_TRIDENT
- tristate "Trident support"
- depends on FB && PCI
-@@ -1233,7 +1246,15 @@ config PB1500_TFT
-
- config FB_AU1100
- bool "Au1100 LCD Driver"
-- depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
-+ depends on FB && MIPS && SOC_AU1100
-+ select FB_CFB_FILLRECT
-+ select FB_CFB_COPYAREA
-+ select FB_CFB_IMAGEBLIT
-+ select FB_SOFT_CURSOR
-+ help
-+ This is the framebuffer driver for the AMD Au1100 SOC. It can drive
-+ various panels and CRTs by passing in kernel cmd line option
-+ au1100fb:panel=<name>.
-
- source "drivers/video/geode/Kconfig"
-
-@@ -1325,7 +1346,7 @@ config FB_HIT
-
- config FB_PMAG_AA
- bool "PMAG-AA TURBOchannel framebuffer support"
-- depends on (FB = y) && MACH_DECSTATION && TC
-+ depends on (FB = y) && TC
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-@@ -1336,7 +1357,7 @@ config FB_PMAG_AA
-
- config FB_PMAG_BA
- bool "PMAG-BA TURBOchannel framebuffer support"
-- depends on (FB = y) && MACH_DECSTATION && TC
-+ depends on (FB = y) && TC
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-@@ -1347,19 +1368,19 @@ config FB_PMAG_BA
-
- config FB_PMAGB_B
- bool "PMAGB-B TURBOchannel framebuffer support"
-- depends on (FB = y) && MACH_DECSTATION && TC
-+ depends on (FB = y) && TC
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- select FB_SOFT_CURSOR
- help
- Support for the PMAGB-B TURBOchannel framebuffer card used mainly
-- in the MIPS-based DECstation series. The card is currently only
-- supported in 1280x1024x8 mode.
-+ in the MIPS-based DECstation series. The card is currently only
-+ supported in 1280x1024x8 mode.
-
- config FB_MAXINE
- bool "Maxine (Personal DECstation) onboard framebuffer support"
-- depends on (FB = y) && MACH_DECSTATION && TC
-+ depends on (FB = y) && MACH_DECSTATION
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-diff -urpNX dontdiff linux-2.6.12/drivers/video/Makefile linux_HEAD/drivers/video/Makefile
---- linux-2.6.12/drivers/video/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/Makefile 2005-07-10 12:16:34.000000000 +0200
-@@ -83,7 +83,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
- obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
- obj-$(CONFIG_FB_PXA) += pxafb.o
- obj-$(CONFIG_FB_W100) += w100fb.o
--obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o
-+obj-$(CONFIG_FB_AU1100) += au1100fb.o
- obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
- obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
- obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
-@@ -91,6 +91,7 @@ obj-$(CONFIG_FB_MAXINE) += maxinefb.o
- obj-$(CONFIG_FB_TX3912) += tx3912fb.o
- obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
- obj-$(CONFIG_FB_IMX) += imxfb.o
-+obj-$(CONFIG_FB_SMIVGX) += smivgxfb.o
-
- # Platform or fallback drivers go here
- obj-$(CONFIG_FB_VESA) += vesafb.o
-diff -urpNX dontdiff linux-2.6.12/drivers/video/au1100fb.c linux_HEAD/drivers/video/au1100fb.c
---- linux-2.6.12/drivers/video/au1100fb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/au1100fb.c 2005-04-14 16:40:18.000000000 +0200
-@@ -2,6 +2,11 @@
- * BRIEF MODULE DESCRIPTION
- * Au1100 LCD Driver.
- *
-+ * Rewritten for 2.6 by Embedded Alley Solutions
-+ * <source at embeddedalley.com>, based on submissions by
-+ * Karl Lessard <klessard at sunrisetelecom.com>
-+ * <c.pellegrin at exadron.com>
++/* Tx MAC defines */
++#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */
++#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */
++#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */
++#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */
++#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */
++#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */
++#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */
++#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */
++#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */
++#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */
++
++/* GMII register */
++#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */
++#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */
++#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */
++
++/* Tx and Rx XDMA defines */
++#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */
++#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */
++#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */
++#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */
++#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */
++#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */
++#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */
++#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */
++
++/* AFX (Address Filter Exact) register offsets for Slice 0 */
++#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/
++#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/
++#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */
++#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */
++#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */
++#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */
++
++/* Traffic Groomer block */
++#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */
++
++#endif /* _TITAN_GE_H_ */
++
+diff -urN --ignore-space-change kernel.org/drivers/net/titan_mdio.c linux-mips/drivers/net/titan_mdio.c
+--- kernel.org/drivers/net/titan_mdio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/titan_mdio.c 2006-01-10 11:21:43.000000000 +0000
+@@ -0,0 +1,217 @@
++/*
++ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
+ *
- * Copyright 2002 MontaVista Software
- * Author: MontaVista Software, Inc.
- * ppopov at mvista.com or source at mvista.com
-@@ -34,297 +39,253 @@
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-+#include <linux/config.h>
- #include <linux/module.h>
- #include <linux/kernel.h>
- #include <linux/errno.h>
- #include <linux/string.h>
- #include <linux/mm.h>
--#include <linux/tty.h>
--#include <linux/slab.h>
--#include <linux/delay.h>
- #include <linux/fb.h>
- #include <linux/init.h>
--#include <linux/pci.h>
-+#include <linux/interrupt.h>
-+#include <linux/ctype.h>
-+#include <linux/dma-mapping.h>
-
--#include <asm/au1000.h>
--#include <asm/pb1100.h>
--#include "au1100fb.h"
-+#include <asm/mach-au1x00/au1000.h>
-
--#include <video/fbcon.h>
--#include <video/fbcon-mfb.h>
--#include <video/fbcon-cfb2.h>
--#include <video/fbcon-cfb4.h>
--#include <video/fbcon-cfb8.h>
--#include <video/fbcon-cfb16.h>
-+#define DEBUG 0
-
--/*
-+#include "au1100fb.h"
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani at pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
++ * on the Titan. No support for the TBI as yet.
++ *
++ */
+
-+/*
- * Sanity check. If this is a new Au1100 based board, search for
- * the PB1100 ifdefs to make sure you modify the code accordingly.
- */
--#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_HYDROGEN3)
-+#if defined(CONFIG_MIPS_PB1100)
-+ #include <asm/mach-pb1x00/pb1100.h>
-+#elif defined(CONFIG_MIPS_DB1100)
-+ #include <asm/mach-db1x00/db1x00.h>
- #else
--error Unknown Au1100 board
-+ #error "Unknown Au1100 board, Au1100 FB driver not supported"
- #endif
-
--#define CMAPSIZE 16
-+#define DRIVER_NAME "au1100fb"
-+#define DRIVER_DESC "LCD controller driver for AU1100 processors"
-
--static int my_lcd_index; /* default is zero */
--struct known_lcd_panels *p_lcd;
--AU1100_LCD *p_lcd_reg = (AU1100_LCD *)AU1100_LCD_ADDR;
--
--struct au1100fb_info {
-- struct fb_info_gen gen;
-- unsigned long fb_virt_start;
-- unsigned long fb_size;
-- unsigned long fb_phys;
-- int mmaped;
-- int nohwcursor;
-+#define to_au1100fb_device(_info) \
-+ (_info ? container_of(_info, struct au1100fb_device, info) : NULL);
-
-- struct { unsigned red, green, blue, pad; } palette[256];
-+/* Bitfields format supported by the controller. Note that the order of formats
-+ * SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the
-+ * right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF]
++#include "titan_mdio.h"
++
++#define MDIO_DEBUG
++
++/*
++ * Local constants
+ */
-+struct fb_bitfield rgb_bitfields[][4] =
++#define MAX_CLKA 1023
++#define MAX_PHY_DEV 31
++#define MAX_PHY_REG 31
++#define WRITEADDRS_OPCODE 0x0
++#define READ_OPCODE 0x2
++#define WRITE_OPCODE 0x1
++#define MAX_MDIO_POLL 100
++
++/*
++ * Titan MDIO and SCMB registers
++ */
++#define TITAN_GE_SCMB_CONTROL 0x01c0 /* SCMB Control */
++#define TITAN_GE_SCMB_CLKA 0x01c4 /* SCMB Clock A */
++#define TITAN_GE_MDIO_COMMAND 0x01d0 /* MDIO Command */
++#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO Device and Port addrs */
++#define TITAN_GE_MDIO_DATA 0x01d8 /* MDIO Data */
++#define TITAN_GE_MDIO_INTERRUPTS 0x01dC /* MDIO Interrupts */
++
++/*
++ * Function to poll the MDIO
++ */
++static int titan_ge_mdio_poll(void)
+{
-+ /* Red, Green, Blue, Transp */
-+ { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
-+ { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
-+ { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
-+ { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
-+ { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
-
--#if defined(FBCON_HAS_CFB16)
-- u16 fbcon_cmap16[16];
--#endif
-+ /* The last is used to describe 12bpp format */
-+ { { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
- };
-
--
--struct au1100fb_par {
-- struct fb_var_screeninfo var;
--
-- int line_length; // in bytes
-- int cmap_len; // color-map length
-+static struct fb_fix_screeninfo au1100fb_fix __initdata = {
-+ .id = "AU1100 FB",
-+ .xpanstep = 1,
-+ .ypanstep = 1,
-+ .type = FB_TYPE_PACKED_PIXELS,
-+ .accel = FB_ACCEL_NONE,
- };
-
--
--static struct au1100fb_info fb_info;
--static struct au1100fb_par current_par;
--static struct display disp;
--
--int au1100fb_init(void);
--void au1100fb_setup(char *options, int *ints);
--static int au1100fb_mmap(struct fb_info *fb, struct file *file,
-- struct vm_area_struct *vma);
--static int au1100_blank(int blank_mode, struct fb_info_gen *info);
--static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
-- u_long arg, int con, struct fb_info *info);
--
--void au1100_nocursor(struct display *p, int mode, int xx, int yy){};
--
--static struct fb_ops au1100fb_ops = {
-- owner: THIS_MODULE,
-- fb_get_fix: fbgen_get_fix,
-- fb_get_var: fbgen_get_var,
-- fb_set_var: fbgen_set_var,
-- fb_get_cmap: fbgen_get_cmap,
-- fb_set_cmap: fbgen_set_cmap,
-- fb_pan_display: fbgen_pan_display,
-- fb_ioctl: au1100fb_ioctl,
-- fb_mmap: au1100fb_mmap,
-+static struct fb_var_screeninfo au1100fb_var __initdata = {
-+ .activate = FB_ACTIVATE_NOW,
-+ .height = -1,
-+ .width = -1,
-+ .vmode = FB_VMODE_NONINTERLACED,
- };
-
--static void au1100_detect(void)
--{
-- /*
-- * This function should detect the current video mode settings
-- * and store it as the default video mode
-- */
-+static struct au1100fb_drv_info drv_info;
-
-- /*
-- * Yeh, well, we're not going to change any settings so we're
-- * always stuck with the default ...
++ int i, val;
++
++ for (i = 0; i < MAX_MDIO_POLL; i++) {
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++
++ if (!(val & 0x8000))
++ return TITAN_GE_MDIO_GOOD;
++ }
++
++ return TITAN_GE_MDIO_ERROR;
++}
++
++
+/*
-+ * Set hardware with var settings. This will enable the controller with a specific
-+ * mode, normally validated with the fb_check_var method
- */
--
--}
--
--static int au1100_encode_fix(struct fb_fix_screeninfo *fix,
-- const void *_par, struct fb_info_gen *_info)
--{
-- struct au1100fb_info *info = (struct au1100fb_info *) _info;
-- struct au1100fb_par *par = (struct au1100fb_par *) _par;
-- struct fb_var_screeninfo *var = &par->var;
--
-- memset(fix, 0, sizeof(struct fb_fix_screeninfo));
--
-- fix->smem_start = info->fb_phys;
-- fix->smem_len = info->fb_size;
-- fix->type = FB_TYPE_PACKED_PIXELS;
-- fix->type_aux = 0;
-- fix->visual = (var->bits_per_pixel == 8) ?
-- FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
-- fix->ywrapstep = 0;
-- fix->xpanstep = 1;
-- fix->ypanstep = 1;
-- fix->line_length = current_par.line_length;
-- return 0;
--}
--
--static void set_color_bitfields(struct fb_var_screeninfo *var)
--{
-- switch (var->bits_per_pixel) {
-- case 8:
-- var->red.offset = 0;
-- var->red.length = 8;
-- var->green.offset = 0;
-- var->green.length = 8;
-- var->blue.offset = 0;
-- var->blue.length = 8;
-- var->transp.offset = 0;
-- var->transp.length = 0;
-- break;
-- case 16: /* RGB 565 */
-- var->red.offset = 11;
-- var->red.length = 5;
-- var->green.offset = 5;
-- var->green.length = 6;
-- var->blue.offset = 0;
-- var->blue.length = 5;
-- var->transp.offset = 0;
-- var->transp.length = 0;
-- break;
-- }
--
-- var->red.msb_right = 0;
-- var->green.msb_right = 0;
-- var->blue.msb_right = 0;
-- var->transp.msb_right = 0;
--}
--
--static int au1100_decode_var(const struct fb_var_screeninfo *var,
-- void *_par, struct fb_info_gen *_info)
-+int au1100fb_setmode(struct au1100fb_device *fbdev)
- {
-+ struct fb_info *info = &fbdev->info;
-+ u32 words;
-+ int index;
-
-- struct au1100fb_par *par = (struct au1100fb_par *)_par;
--
-- /*
-- * Don't allow setting any of these yet: xres and yres don't
-- * make sense for LCD panels.
-- */
-- if (var->xres != p_lcd->xres ||
-- var->yres != p_lcd->yres ||
-- var->xres != p_lcd->xres ||
-- var->yres != p_lcd->yres) {
-- return -EINVAL;
-- }
-- if(var->bits_per_pixel != p_lcd->bpp) {
-+ if (!fbdev)
- return -EINVAL;
-- }
--
-- memset(par, 0, sizeof(struct au1100fb_par));
-- par->var = *var;
--
-- /* FIXME */
-- switch (var->bits_per_pixel) {
-- case 8:
-- par->var.bits_per_pixel = 8;
-- break;
-- case 16:
-- par->var.bits_per_pixel = 16;
-- break;
-- default:
-- printk("color depth %d bpp not supported\n",
-- var->bits_per_pixel);
-- return -EINVAL;
-
-+ /* Update var-dependent FB info */
-+ if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) {
-+ if (info->var.bits_per_pixel <= 8) {
-+ /* palettized */
-+ info->var.red.offset = 0;
-+ info->var.red.length = info->var.bits_per_pixel;
-+ info->var.red.msb_right = 0;
-+
-+ info->var.green.offset = 0;
-+ info->var.green.length = info->var.bits_per_pixel;
-+ info->var.green.msb_right = 0;
-+
-+ info->var.blue.offset = 0;
-+ info->var.blue.length = info->var.bits_per_pixel;
-+ info->var.blue.msb_right = 0;
-+
-+ info->var.transp.offset = 0;
-+ info->var.transp.length = 0;
-+ info->var.transp.msb_right = 0;
-+
-+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
-+ info->fix.line_length = info->var.xres_virtual /
-+ (8/info->var.bits_per_pixel);
-+ } else {
-+ /* non-palettized */
-+ index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT;
-+ info->var.red = rgb_bitfields[index][0];
-+ info->var.green = rgb_bitfields[index][1];
-+ info->var.blue = rgb_bitfields[index][2];
-+ info->var.transp = rgb_bitfields[index][3];
++ * Initialize and configure the MDIO
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
++{
++ unsigned long val;
++
++ /* Reset the SCMB and program into MDIO mode*/
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
++
++ /* CLK A */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
++ val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
++
++ /* Preamble Suppresion */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ /* MDIO mode */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++ return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Set the PHY address in indirect mode
++ */
++int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
++{
++ volatile unsigned long val;
++
++ /* Setup the PHY device */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
-+ info->fix.visual = FB_VISUAL_TRUECOLOR;
-+ info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */
-+ }
-+ } else {
-+ /* mono */
-+ info->fix.visual = FB_VISUAL_MONO10;
-+ info->fix.line_length = info->var.xres_virtual / 8;
-+ }
++ /* Write the new address */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
-+ info->screen_size = info->fix.line_length * info->var.yres_virtual;
-+
-+ /* Determine BPP mode and format */
-+ fbdev->regs->lcd_control = fbdev->panel->control_base |
-+ ((info->var.rotate/90) << LCD_CONTROL_SM_BIT);
++ return TITAN_GE_MDIO_GOOD;
++}
+
-+ fbdev->regs->lcd_intenable = 0;
-+ fbdev->regs->lcd_intstatus = 0;
++/*
++ * Read the MDIO register. This is what the individual parametes mean:
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register offset
++ *
++ * See the spec for the Titan MAC. We operate in the Direct Mode.
++ */
+
-+ fbdev->regs->lcd_horztiming = fbdev->panel->horztiming;
++#define MAX_RETRIES 2
+
-+ fbdev->regs->lcd_verttiming = fbdev->panel->verttiming;
++int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
++{
++ volatile unsigned long val;
++ int retries = 0;
+
-+ fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base;
++ /* Setup the PHY device */
+
-+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys);
++again:
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ val |= 0x4000;
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
-+ if (panel_is_dual(fbdev->panel)) {
-+ /* Second panel display seconf half of screen if possible,
-+ * otherwise display the same as the first panel */
-+ if (info->var.yres_virtual >= (info->var.yres << 1)) {
-+ fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys +
-+ (info->fix.line_length *
-+ (info->var.yres_virtual >> 1)));
-+ } else {
-+ fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys);
-+ }
- }
-- set_color_bitfields(&par->var);
-- par->cmap_len = (par->var.bits_per_pixel == 8) ? 256 : 16;
-- return 0;
--}
--
--static int au1100_encode_var(struct fb_var_screeninfo *var,
-- const void *par, struct fb_info_gen *_info)
--{
--
-- *var = ((struct au1100fb_par *)par)->var;
-- return 0;
--}
--
--static void
--au1100_get_par(void *_par, struct fb_info_gen *_info)
--{
-- *(struct au1100fb_par *)_par = current_par;
--}
--
--static void au1100_set_par(const void *par, struct fb_info_gen *info)
--{
-- /* nothing to do: we don't change any settings */
--}
--
--static int au1100_getcolreg(unsigned regno, unsigned *red, unsigned *green,
-- unsigned *blue, unsigned *transp,
-- struct fb_info *info)
--{
-
-- struct au1100fb_info* i = (struct au1100fb_info*)info;
--
-- if (regno > 255)
-- return 1;
-+ words = info->fix.line_length / sizeof(u32);
-+ if (!info->var.rotate || (info->var.rotate == 180)) {
-+ words *= info->var.yres_virtual;
-+ if (info->var.rotate /* 180 */) {
-+ words -= (words % 8); /* should be divisable by 8 */
++ udelay(30);
++
++ /* Issue the read command */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ udelay(30);
++
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
++
++ *pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++
++ udelay(30);
++
++ if (val & 0x2) {
++ if (retries == MAX_RETRIES)
++ return TITAN_GE_MDIO_ERROR;
++ else {
++ retries++;
++ goto again;
+ }
+ }
-+ fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words);
-
-- *red = i->palette[regno].red;
-- *green = i->palette[regno].green;
-- *blue = i->palette[regno].blue;
-- *transp = 0;
-+ fbdev->regs->lcd_pwmdiv = 0;
-+ fbdev->regs->lcd_pwmhi = 0;
-+
-+ /* Resume controller */
-+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
-
- return 0;
- }
-
--static int au1100_setcolreg(unsigned regno, unsigned red, unsigned green,
-- unsigned blue, unsigned transp,
-- struct fb_info *info)
-+/* fb_setcolreg
-+ * Set color in LCD palette.
-+ */
-+int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
- {
-- struct au1100fb_info* i = (struct au1100fb_info *)info;
-- u32 rgbcol;
-+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
-+ u32 *palette = fbdev->regs->lcd_pallettebase;
-+ u32 value;
-
-- if (regno > 255)
-- return 1;
-+ if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
-+ return -EINVAL;
-
-- i->palette[regno].red = red;
-- i->palette[regno].green = green;
-- i->palette[regno].blue = blue;
-+ if (fbi->var.grayscale) {
-+ /* Convert color to grayscale */
-+ red = green = blue =
-+ (19595 * red + 38470 * green + 7471 * blue) >> 16;
-+ }
-+
-+ if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
-+ /* Place color in the pseudopalette */
-+ if (regno > 16)
-+ return -EINVAL;
-+
-+ palette = (u32*)fbi->pseudo_palette;
-
-- switch(p_lcd->bpp) {
--#ifdef FBCON_HAS_CFB8
-- case 8:
-- red >>= 10;
-- green >>= 10;
-- blue >>= 10;
-- p_lcd_reg->lcd_pallettebase[regno] = (blue&0x1f) |
-- ((green&0x3f)<<5) | ((red&0x1f)<<11);
-- break;
--#endif
--#ifdef FBCON_HAS_CFB16
-- case 16:
-- i->fbcon_cmap16[regno] =
-- ((red & 0xf800) >> 0) |
-- ((green & 0xfc00) >> 5) |
-- ((blue & 0xf800) >> 11);
-- break;
--#endif
-- default:
-- break;
-+ red >>= (16 - fbi->var.red.length);
-+ green >>= (16 - fbi->var.green.length);
-+ blue >>= (16 - fbi->var.blue.length);
-+
-+ value = (red << fbi->var.red.offset) |
-+ (green << fbi->var.green.offset)|
-+ (blue << fbi->var.blue.offset);
-+ value &= 0xFFFF;
+
-+ } else if (panel_is_active(fbdev->panel)) {
-+ /* COLOR TFT PALLETTIZED (use RGB 565) */
-+ value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F);
-+ value &= 0xFFFF;
++ return TITAN_GE_MDIO_GOOD;
++}
+
-+ } else if (panel_is_color(fbdev->panel)) {
-+ /* COLOR STN MODE */
-+ value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) |
-+ ((green >> 8) & 0x00F0) |
-+ (((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00);
-+ value &= 0xFFF;
-+ } else {
-+ /* MONOCHROME MODE */
-+ value = (green >> 12) & 0x000F;
-+ value &= 0xF;
- }
-
-+ palette[regno] = value;
-+
- return 0;
- }
-
--
--static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
-+/* fb_blank
-+ * Blank the screen. Depending on the mode, the screen will be
-+ * activated with the backlight color, or desactivated
++/*
++ * Write to the MDIO register
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register that needs to be written to
++ *
+ */
-+int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
- {
-+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
++int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
++{
++ volatile unsigned long val;
+
-+ print_dbg("fb_blank %d %p", blank_mode, fbi);
-
- switch (blank_mode) {
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
+
- case VESA_NO_BLANKING:
-- /* turn on panel */
-- //printk("turn on panel\n");
-+ /* Turn on panel */
-+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
- #ifdef CONFIG_MIPS_PB1100
-- p_lcd_reg->lcd_control |= LCD_CONTROL_GO;
-- au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight,
-+ if (drv_info.panel_idx == 1) {
-+ au_writew(au_readw(PB1100_G_CONTROL)
-+ | (PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
- PB1100_G_CONTROL);
--#endif
--#ifdef CONFIG_MIPS_HYDROGEN3
-- /* Turn controller & power supply on, GPIO213 */
-- au_writel(0x20002000, 0xB1700008);
-- au_writel(0x00040000, 0xB1900108);
-- au_writel(0x01000100, 0xB1700008);
-+ }
- #endif
- au_sync();
- break;
-@@ -332,65 +293,105 @@ static int au1100_blank(int blank_mode,
- case VESA_VSYNC_SUSPEND:
- case VESA_HSYNC_SUSPEND:
- case VESA_POWERDOWN:
-- /* turn off panel */
-- //printk("turn off panel\n");
-+ /* Turn off panel */
-+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
- #ifdef CONFIG_MIPS_PB1100
-- au_writew(au_readw(PB1100_G_CONTROL) & ~p_lcd->mode_backlight,
-+ if (drv_info.panel_idx == 1) {
-+ au_writew(au_readw(PB1100_G_CONTROL)
-+ & ~(PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
- PB1100_G_CONTROL);
-- p_lcd_reg->lcd_control &= ~LCD_CONTROL_GO;
-+ }
- #endif
- au_sync();
- break;
-- default:
-+ default:
- break;
-
- }
- return 0;
- }
-
--static void au1100_set_disp(const void *unused, struct display *disp,
-- struct fb_info_gen *info)
-+/* fb_pan_display
-+ * Pan display in x and/or y as specified
-+ */
-+int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
- {
-- disp->screen_base = (char *)fb_info.fb_virt_start;
-+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
-+ int dy;
-
-- switch (disp->var.bits_per_pixel) {
--#ifdef FBCON_HAS_CFB8
-- case 8:
-- disp->dispsw = &fbcon_cfb8;
-- if (fb_info.nohwcursor)
-- fbcon_cfb8.cursor = au1100_nocursor;
-- break;
--#endif
--#ifdef FBCON_HAS_CFB16
-- case 16:
-- disp->dispsw = &fbcon_cfb16;
-- disp->dispsw_data = fb_info.fbcon_cmap16;
-- if (fb_info.nohwcursor)
-- fbcon_cfb16.cursor = au1100_nocursor;
-- break;
--#endif
-- default:
-- disp->dispsw = &fbcon_dummy;
-- disp->dispsw_data = NULL;
-- break;
-+ print_dbg("fb_pan_display %p %p", var, fbi);
++ /* Setup the PHY device */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ val |= 0x4000;
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
+
-+ if (!var || !fbdev) {
-+ return -EINVAL;
-+ }
++ udelay(30);
+
-+ if (var->xoffset - fbi->var.xoffset) {
-+ /* No support for X panning for now! */
-+ return -EINVAL;
-+ }
-+
-+ print_dbg("fb_pan_display 2 %p %p", var, fbi);
-+ dy = var->yoffset - fbi->var.yoffset;
-+ if (dy) {
++ /* Setup the data to write */
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
+
-+ u32 dmaaddr;
++ udelay(30);
+
-+ print_dbg("Panning screen of %d lines", dy);
++ /* Issue the write command */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
+
-+ dmaaddr = fbdev->regs->lcd_dmaaddr0;
-+ dmaaddr += (fbi->fix.line_length * dy);
++ udelay(30);
+
-+ /* TODO: Wait for current frame to finished */
-+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
+
-+ if (panel_is_dual(fbdev->panel)) {
-+ dmaaddr = fbdev->regs->lcd_dmaaddr1;
-+ dmaaddr += (fbi->fix.line_length * dy);
-+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
-+ }
-+ }
-+ print_dbg("fb_pan_display 3 %p %p", var, fbi);
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++ if (val & 0x2)
++ return TITAN_GE_MDIO_ERROR;
+
-+ return 0;
++ return TITAN_GE_MDIO_GOOD;
+}
+
-+/* fb_rotate
-+ * Rotate the display of this angle. This doesn't seems to be used by the core,
-+ * but as our hardware supports it, so why not implementing it...
+diff -urN --ignore-space-change kernel.org/drivers/net/titan_mdio.h linux-mips/drivers/net/titan_mdio.h
+--- kernel.org/drivers/net/titan_mdio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/net/titan_mdio.h 2006-01-10 11:21:43.000000000 +0000
+@@ -0,0 +1,56 @@
++/*
++ * MDIO used to interact with the PHY when using GMII/MII
+ */
-+void au1100fb_fb_rotate(struct fb_info *fbi, int angle)
-+{
-+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
++#ifndef _TITAN_MDIO_H
++#define _TITAN_MDIO_H
++
++#include <linux/netdevice.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include "titan_ge.h"
++
+
-+ print_dbg("fb_rotate %p %d", fbi, angle);
++#define TITAN_GE_MDIO_ERROR (-9000)
++#define TITAN_GE_MDIO_GOOD 0
++
++#define TITAN_GE_MDIO_BASE titan_ge_base
+
-+ if (fbdev && (angle > 0) && !(angle % 90)) {
++#define TITAN_GE_MDIO_READ(offset) \
++ *(volatile u32 *)(titan_ge_base + (offset))
+
-+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
++#define TITAN_GE_MDIO_WRITE(offset, data) \
++ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
+
-+ fbdev->regs->lcd_control &= ~(LCD_CONTROL_SM_MASK);
-+ fbdev->regs->lcd_control |= ((angle/90) << LCD_CONTROL_SM_BIT);
+
-+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
- }
- }
++/* GMII specific registers */
++#define TITAN_GE_MARVEL_PHY_ID 0x00
++#define TITAN_PHY_AUTONEG_ADV 0x04
++#define TITAN_PHY_LP_ABILITY 0x05
++#define TITAN_GE_MDIO_MII_CTRL 0x09
++#define TITAN_GE_MDIO_MII_EXTENDED 0x0f
++#define TITAN_GE_MDIO_PHY_CTRL 0x10
++#define TITAN_GE_MDIO_PHY_STATUS 0x11
++#define TITAN_GE_MDIO_PHY_IE 0x12
++#define TITAN_GE_MDIO_PHY_IS 0x13
++#define TITAN_GE_MDIO_PHY_LED 0x18
++#define TITAN_GE_MDIO_PHY_LED_OVER 0x19
++#define PHY_ANEG_TIME_WAIT 45 /* 45 seconds wait time */
++
++/*
++ * MDIO Config Structure
++ */
++typedef struct {
++ unsigned int clka;
++ int mdio_spre;
++ int mdio_mode;
++} titan_ge_mdio_config;
++
++/*
++ * Function Prototypes
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *);
++int titan_ge_mdio_inaddrs(int, int);
++int titan_ge_mdio_read(int, int, unsigned int *);
++int titan_ge_mdio_write(int, int, unsigned int);
++
++#endif /* _TITAN_MDIO_H */
+diff -urN --ignore-space-change kernel.org/drivers/net/tulip/tulip_core.c linux-mips/drivers/net/tulip/tulip_core.c
+--- kernel.org/drivers/net/tulip/tulip_core.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/net/tulip/tulip_core.c 2006-01-10 11:21:43.000000000 +0000
+@@ -1495,8 +1495,8 @@
+ if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
+ /* DDB5477 MAC address in first EEPROM locations. */
+ sa_offset = 0;
+- /* No media table either */
+- tp->flags &= ~HAS_MEDIA_TABLE;
++ /* Ensure our media table fixup get's applied */
++ memcpy(ee_data + 16, ee_data, 8);
+ }
+ #endif
+ #ifdef CONFIG_MIPS_COBALT
+diff -urN --ignore-space-change kernel.org/drivers/scsi/NCR53C9x.h linux-mips/drivers/scsi/NCR53C9x.h
+--- kernel.org/drivers/scsi/NCR53C9x.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/scsi/NCR53C9x.h 2006-01-10 11:21:46.000000000 +0000
+@@ -145,12 +145,7 @@
--static int
--au1100fb_mmap(struct fb_info *_fb,
-- struct file *file,
-- struct vm_area_struct *vma)
-+/* fb_mmap
-+ * Map video memory in user space. We don't use the generic fb_mmap method mainly
-+ * to allow the use of the TLB streaming flag (CCA=6)
-+ */
-+int au1100fb_fb_mmap(struct fb_info *fbi, struct file *file, struct vm_area_struct *vma)
- {
-+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
- unsigned int len;
- unsigned long start=0, off;
-- struct au1100fb_info *fb = (struct au1100fb_info *)_fb;
+ #ifndef MULTIPLE_PAD_SIZES
- if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
- return -EINVAL;
- }
--
-- start = fb_info.fb_phys & PAGE_MASK;
-- len = PAGE_ALIGN((start & ~PAGE_MASK) + fb_info.fb_size);
-+
-+ start = fbdev->fb_phys & PAGE_MASK;
-+ len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
+-#ifdef CONFIG_CPU_HAS_WB
+-#include <asm/wbflush.h>
+-#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
+-#else
+-#define esp_write(__reg, __val) ((__reg) = (__val))
+-#endif
++#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0)
+ #define esp_read(__reg) (__reg)
- off = vma->vm_pgoff << PAGE_SHIFT;
+ struct ESP_regs {
+diff -urN --ignore-space-change kernel.org/drivers/scsi/dec_esp.c linux-mips/drivers/scsi/dec_esp.c
+--- kernel.org/drivers/scsi/dec_esp.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/scsi/dec_esp.c 2006-01-10 11:21:47.000000000 +0000
+@@ -55,7 +55,7 @@
-@@ -401,276 +402,310 @@ au1100fb_mmap(struct fb_info *_fb,
- off += start;
- vma->vm_pgoff = off >> PAGE_SHIFT;
+ static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
+ static void dma_drain(struct NCR_ESP *esp);
+-static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp);
++static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp);
+ static void dma_dump_state(struct NCR_ESP *esp);
+ static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
+ static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length);
+@@ -64,9 +64,9 @@
+ static int dma_irq_p(struct NCR_ESP *esp);
+ static int dma_ports_p(struct NCR_ESP *esp);
+ static void dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write);
+-static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp);
+-static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp);
+-static void dma_advance_sg(struct scsi_cmnd * sp);
++static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp);
++static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp);
++static void dma_advance_sg(Scsi_Cmnd * sp);
-- pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
-- //pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
+ static void pmaz_dma_drain(struct NCR_ESP *esp);
+ static void pmaz_dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
+@@ -74,7 +74,7 @@
+ static void pmaz_dma_ints_off(struct NCR_ESP *esp);
+ static void pmaz_dma_ints_on(struct NCR_ESP *esp);
+ static void pmaz_dma_setup(struct NCR_ESP *esp, u32 addr, int count, int write);
+-static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp);
++static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp);
-- /* This is an IO map - tell maydump to skip this VMA */
- vma->vm_flags |= VM_IO;
--
-- if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-+
-+ if (io_remap_page_range(vma, vma->vm_start, off,
- vma->vm_end - vma->vm_start,
- vma->vm_page_prot)) {
- return -EAGAIN;
- }
+ #define TC_ESP_RAM_SIZE 0x20000
+ #define ESP_TGT_DMA_SIZE ((TC_ESP_RAM_SIZE/7) & ~(sizeof(int)-1))
+@@ -98,7 +98,7 @@
+ static irqreturn_t scsi_dma_err_int(int, void *, struct pt_regs *);
+ static irqreturn_t scsi_dma_int(int, void *, struct pt_regs *);
-- fb->mmaped = 1;
- return 0;
- }
+-static int dec_esp_detect(struct scsi_host_template * tpnt);
++int dec_esp_detect(Scsi_Host_Template * tpnt);
--int au1100_pan_display(const struct fb_var_screeninfo *var,
-- struct fb_info_gen *info)
-+static struct fb_ops au1100fb_ops =
+ static int dec_esp_release(struct Scsi_Host *shost)
{
-- return 0;
--}
-+ .owner = THIS_MODULE,
-+ .fb_setcolreg = au1100fb_fb_setcolreg,
-+ .fb_blank = au1100fb_fb_blank,
-+ .fb_pan_display = au1100fb_fb_pan_display,
-+ .fb_fillrect = cfb_fillrect,
-+ .fb_copyarea = cfb_copyarea,
-+ .fb_imageblit = cfb_imageblit,
-+ .fb_cursor = soft_cursor,
-+ .fb_rotate = au1100fb_fb_rotate,
-+ .fb_mmap = au1100fb_fb_mmap,
-+};
-
--static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
-- u_long arg, int con, struct fb_info *info)
--{
-- /* nothing to do yet */
-- return -EINVAL;
--}
-
--static struct fbgen_hwswitch au1100_switch = {
-- au1100_detect,
-- au1100_encode_fix,
-- au1100_decode_var,
-- au1100_encode_var,
-- au1100_get_par,
-- au1100_set_par,
-- au1100_getcolreg,
-- au1100_setcolreg,
-- au1100_pan_display,
-- au1100_blank,
-- au1100_set_disp
--};
-+/*-------------------------------------------------------------------------*/
+@@ -110,9 +110,9 @@
+ return 0;
+ }
-+/* AU1100 LCD controller device driver */
+-static struct scsi_host_template driver_template = {
++static Scsi_Host_Template driver_template = {
+ .proc_name = "dec_esp",
+- .proc_info = esp_proc_info,
++ .proc_info = &esp_proc_info,
+ .name = "NCR53C94",
+ .detect = dec_esp_detect,
+ .slave_alloc = esp_slave_alloc,
+@@ -133,7 +133,7 @@
+ #include "scsi_module.c"
--int au1100_setmode(void)
-+int au1100fb_drv_probe(struct device *dev)
+ /***************************************************************** Detection */
+-static int dec_esp_detect(struct scsi_host_template * tpnt)
++int dec_esp_detect(struct scsi_host_template * tpnt)
{
-- int words;
-+ struct au1100fb_device *fbdev = NULL;
-+ struct resource *regs_res;
-+ unsigned long page;
-+ u32 sys_clksrc;
-
-- /* FIXME Need to accomodate for swivel mode and 12bpp, <8bpp*/
-- switch (p_lcd->mode_control & LCD_CONTROL_SM)
-- {
-- case LCD_CONTROL_SM_0:
-- case LCD_CONTROL_SM_180:
-- words = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 32;
-- break;
-- case LCD_CONTROL_SM_90:
-- case LCD_CONTROL_SM_270:
-- /* is this correct? */
-- words = (p_lcd->xres * p_lcd->bpp) / 8;
-- break;
-- default:
-- printk("mode_control reg not initialized\n");
-+ if (!dev)
- return -EINVAL;
-- }
-
-- /*
-- * Setup LCD controller
-- */
-+ /* Allocate new device private */
-+ if (!(fbdev = kmalloc(sizeof(struct au1100fb_device), GFP_KERNEL))) {
-+ print_err("fail to allocate device private record");
-+ return -ENOMEM;
-+ }
-+ memset((void*)fbdev, 0, sizeof(struct au1100fb_device));
-
-- p_lcd_reg->lcd_control = p_lcd->mode_control;
-- p_lcd_reg->lcd_intstatus = 0;
-- p_lcd_reg->lcd_intenable = 0;
-- p_lcd_reg->lcd_horztiming = p_lcd->mode_horztiming;
-- p_lcd_reg->lcd_verttiming = p_lcd->mode_verttiming;
-- p_lcd_reg->lcd_clkcontrol = p_lcd->mode_clkcontrol;
-- p_lcd_reg->lcd_words = words - 1;
-- p_lcd_reg->lcd_dmaaddr0 = fb_info.fb_phys;
-+ fbdev->panel = &known_lcd_panels[drv_info.panel_idx];
-
-- /* turn on panel */
--#ifdef CONFIG_MIPS_PB1100
-- au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight,
-- PB1100_G_CONTROL);
--#endif
--#ifdef CONFIG_MIPS_HYDROGEN3
-- /* Turn controller & power supply on, GPIO213 */
-- au_writel(0x20002000, 0xB1700008);
-- au_writel(0x00040000, 0xB1900108);
-- au_writel(0x01000100, 0xB1700008);
--#endif
-+ dev_set_drvdata(dev, (void*)fbdev);
-
-- p_lcd_reg->lcd_control |= LCD_CONTROL_GO;
-+ /* Allocate region for our registers and map them */
-+ if (!(regs_res = platform_get_resource(to_platform_device(dev),
-+ IORESOURCE_MEM, 0))) {
-+ print_err("fail to retrieve registers resource");
-+ return -EFAULT;
-+ }
-
-- return 0;
--}
-+ au1100fb_fix.mmio_start = regs_res->start;
-+ au1100fb_fix.mmio_len = regs_res->end - regs_res->start + 1;
-
-+ if (!request_mem_region(au1100fb_fix.mmio_start, au1100fb_fix.mmio_len,
-+ DRIVER_NAME)) {
-+ print_err("fail to lock memory region at 0x%08x",
-+ au1100fb_fix.mmio_start);
-+ return -EBUSY;
-+ }
+ struct NCR_ESP *esp;
+ struct ConfigDev *esp_dev;
+@@ -230,7 +230,7 @@
+ mem_start = get_tc_base_addr(slot);
--int __init au1100fb_init(void)
--{
-- uint32 sys_clksrc;
-- unsigned long page;
-+ fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
-
-- /*
-- * Get the panel information/display mode and update the registry
-- */
-- p_lcd = &panels[my_lcd_index];
--
-- switch (p_lcd->mode_control & LCD_CONTROL_SM)
-- {
-- case LCD_CONTROL_SM_0:
-- case LCD_CONTROL_SM_180:
-- p_lcd->xres =
-- (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
-- p_lcd->yres =
-- (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
-- break;
-- case LCD_CONTROL_SM_90:
-- case LCD_CONTROL_SM_270:
-- p_lcd->yres =
-- (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
-- p_lcd->xres =
-- (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
-- break;
-- }
-+ print_dbg("Register memory map at %p", fbdev->regs);
-+ print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
+ /* Store base addr into esp struct */
+- esp->slot = CPHYSADDR(mem_start);
++ esp->slot = mem_start;
-- /*
-- * Panel dimensions x bpp must be divisible by 32
-- */
-- if (((p_lcd->yres * p_lcd->bpp) % 32) != 0)
-- printk("VERT %% 32\n");
-- if (((p_lcd->xres * p_lcd->bpp) % 32) != 0)
-- printk("HORZ %% 32\n");
-
-- /*
-- * Allocate LCD framebuffer from system memory
-- */
-- fb_info.fb_size = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 8;
-
-- current_par.var.xres = p_lcd->xres;
-- current_par.var.xres_virtual = p_lcd->xres;
-- current_par.var.yres = p_lcd->yres;
-- current_par.var.yres_virtual = p_lcd->yres;
-- current_par.var.bits_per_pixel = p_lcd->bpp;
--
-- /* FIX!!! only works for 8/16 bpp */
-- current_par.line_length = p_lcd->xres * p_lcd->bpp / 8; /* in bytes */
-- fb_info.fb_virt_start = (unsigned long )
-- __get_free_pages(GFP_ATOMIC | GFP_DMA,
-- get_order(fb_info.fb_size + 0x1000));
-- if (!fb_info.fb_virt_start) {
-- printk("Unable to allocate fb memory\n");
-+ /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
-+ fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
-+ (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
-+
-+ fbdev->fb_mem = dma_alloc_coherent(dev, PAGE_ALIGN(fbdev->fb_len),
-+ &fbdev->fb_phys, GFP_KERNEL);
-+ if (!fbdev->fb_mem) {
-+ print_err("fail to allocate frambuffer (size: %dK))",
-+ fbdev->fb_len / 1024);
- return -ENOMEM;
+ esp->dregs = 0;
+ esp->eregs = (void *)CKSEG1ADDR(mem_start +
+@@ -379,7 +379,7 @@
}
-- fb_info.fb_phys = virt_to_bus((void *)fb_info.fb_virt_start);
-+
-+ au1100fb_fix.smem_start = fbdev->fb_phys;
-+ au1100fb_fix.smem_len = fbdev->fb_len;
+ }
- /*
- * Set page reserved so that mmap will work. This is necessary
- * since we'll be remapping normal memory.
- */
-- for (page = fb_info.fb_virt_start;
-- page < PAGE_ALIGN(fb_info.fb_virt_start + fb_info.fb_size);
-+ for (page = (unsigned long)fbdev->fb_mem;
-+ page < PAGE_ALIGN((unsigned long)fbdev->fb_mem + fbdev->fb_len);
- page += PAGE_SIZE) {
-+#if CONFIG_DMA_NONCOHERENT
-+ SetPageReserved(virt_to_page(CAC_ADDR(page)));
-+#else
- SetPageReserved(virt_to_page(page));
-+#endif
- }
+-static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp)
++static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp)
+ {
+ return sp->SCp.this_residual;
+ }
+@@ -491,12 +491,12 @@
+ dma_init_write(esp, addr, count);
+ }
-- memset((void *)fb_info.fb_virt_start, 0, fb_info.fb_size);
-+ print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
-+ print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
-
-- /* set freqctrl now to allow more time to stabilize */
-- /* zero-out out LCD bits */
-- sys_clksrc = au_readl(SYS_CLKSRC) & ~0x000003e0;
-- sys_clksrc |= p_lcd->mode_toyclksrc;
-- au_writel(sys_clksrc, SYS_CLKSRC);
--
-- /* FIXME add check to make sure auxpll is what is expected! */
-- au1100_setmode();
--
-- fb_info.gen.parsize = sizeof(struct au1100fb_par);
-- fb_info.gen.fbhw = &au1100_switch;
--
-- strcpy(fb_info.gen.info.modename, "Au1100 LCD");
-- fb_info.gen.info.changevar = NULL;
-- fb_info.gen.info.node = -1;
--
-- fb_info.gen.info.fbops = &au1100fb_ops;
-- fb_info.gen.info.disp = &disp;
-- fb_info.gen.info.switch_con = &fbgen_switch;
-- fb_info.gen.info.updatevar = &fbgen_update_var;
-- fb_info.gen.info.blank = &fbgen_blank;
-- fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT;
--
-- /* This should give a reasonable default video mode */
-- fbgen_get_var(&disp.var, -1, &fb_info.gen.info);
-- fbgen_do_set_var(&disp.var, 1, &fb_info.gen);
-- fbgen_set_disp(-1, &fb_info.gen);
-- fbgen_install_cmap(0, &fb_info.gen);
-- if (register_framebuffer(&fb_info.gen.info) < 0)
-- return -EINVAL;
-- printk(KERN_INFO "fb%d: %s frame buffer device\n",
-- GET_FB_IDX(fb_info.gen.info.node),
-- fb_info.gen.info.modename);
-+ /* Setup LCD clock to AUX (48 MHz) */
-+ sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL);
-+ au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC);
-+
-+ /* load the panel info into the var struct */
-+ au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
-+ au1100fb_var.xres = fbdev->panel->xres;
-+ au1100fb_var.xres_virtual = au1100fb_var.xres;
-+ au1100fb_var.yres = fbdev->panel->yres;
-+ au1100fb_var.yres_virtual = au1100fb_var.yres;
-+
-+ fbdev->info.screen_base = fbdev->fb_mem;
-+ fbdev->info.fbops = &au1100fb_ops;
-+ fbdev->info.fix = au1100fb_fix;
-+
-+ if (!(fbdev->info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL))) {
-+ return -ENOMEM;
-+ }
-+ memset(fbdev->info.pseudo_palette, 0, sizeof(u32) * 16);
-+
-+ if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
-+ print_err("Fail to allocate colormap (%d entries)",
-+ AU1100_LCD_NBR_PALETTE_ENTRIES);
-+ kfree(fbdev->info.pseudo_palette);
-+ return -EFAULT;
-+ }
-+
-+ fbdev->info.var = au1100fb_var;
-+
-+ /* Set h/w registers */
-+ au1100fb_setmode(fbdev);
-+
-+ /* Register new framebuffer */
-+ if (register_framebuffer(&fbdev->info) < 0) {
-+ print_err("cannot register new framebuffer");
-+ goto failed;
-+ }
+-static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp)
++static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp)
+ {
+ sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer);
+ }
- return 0;
--}
+-static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, struct scsi_cmnd * sp)
++static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp)
+ {
+ int sz = sp->SCp.buffers_residual;
+ struct scatterlist *sg = sp->SCp.buffer;
+@@ -508,7 +508,7 @@
+ sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address);
+ }
-+failed:
-+ if (fbdev->regs) {
-+ release_mem_region(fbdev->regs_phys, fbdev->regs_len);
-+ }
-+ if (fbdev->fb_mem) {
-+ dma_free_noncoherent(dev, fbdev->fb_len, fbdev->fb_mem, fbdev->fb_phys);
-+ }
-+ if (fbdev->info.cmap.len != 0) {
-+ fb_dealloc_cmap(&fbdev->info.cmap);
-+ }
-+ kfree(fbdev);
-+ dev_set_drvdata(dev, NULL);
-+
-+ return 0;
-+}
+-static void dma_advance_sg(struct scsi_cmnd * sp)
++static void dma_advance_sg(Scsi_Cmnd * sp)
+ {
+ sp->SCp.ptr = (char *)(sp->SCp.buffer->dma_address);
+ }
+@@ -572,7 +572,7 @@
+ pmaz_dma_init_write(esp, addr, count);
+ }
--void au1100fb_cleanup(struct fb_info *info)
-+int au1100fb_drv_remove(struct device *dev)
+-static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, struct scsi_cmnd * sp)
++static void pmaz_dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp)
{
-- unregister_framebuffer(info);
-+ struct au1100fb_device *fbdev = NULL;
-+
-+ if (!dev)
-+ return -ENODEV;
-+
-+ fbdev = (struct au1100fb_device*) dev_get_drvdata(dev);
-+
-+#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
-+ au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
-+#endif
-+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
-+
-+ /* Clean up all probe data */
-+ unregister_framebuffer(&fbdev->info);
-+
-+ release_mem_region(fbdev->regs_phys, fbdev->regs_len);
-+
-+ dma_free_coherent(dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys);
-+
-+ fb_dealloc_cmap(&fbdev->info.cmap);
-+ kfree(fbdev->info.pseudo_palette);
-+ kfree((void*)fbdev);
-+
-+ return 0;
+ sp->SCp.ptr = (char *)virt_to_phys(sp->request_buffer);
}
+diff -urN --ignore-space-change kernel.org/drivers/scsi/eata.c linux-mips/drivers/scsi/eata.c
+--- kernel.org/drivers/scsi/eata.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/scsi/eata.c 2006-01-10 11:21:47.000000000 +0000
+@@ -941,6 +941,8 @@
+ {
+ int tqd, utqd;
+ char *tag_suffix, *link_suffix;
++ struct Scsi_Host *shost = dev->host;
++ struct hostdata *ha = (struct hostdata *)shost->hostdata;
+
+ utqd = MAX_CMD_PER_LUN;
+ tqd = max_queue_depth;
+@@ -971,8 +973,8 @@
+ else
+ link_suffix = "";
-+int au1100fb_drv_suspend(struct device *dev, u32 state, u32 level)
-+{
-+ /* TODO */
-+ return 0;
-+}
+- sdev_printk(KERN_INFO, dev,
+- "cmds/lun %d%s%s.\n",
++ printk("%s: scsi%d, channel %d, id %d, lun %d, cmds/lun %d%s%s.\n",
++ ha->board_name, shost->host_no, dev->channel, dev->id, dev->lun,
+ dev->queue_depth, link_suffix, tag_suffix);
--void au1100fb_setup(char *options, int *ints)
-+int au1100fb_drv_resume(struct device *dev, u32 level)
- {
-- char* this_opt;
-- int i;
-- int num_panels = sizeof(panels)/sizeof(struct known_lcd_panels);
-+ /* TODO */
-+ return 0;
-+}
+ return 0;
+@@ -1811,8 +1813,9 @@
+ SCpnt->host_scribble = (unsigned char *)&cpp->cpp_index;
-+static struct device_driver au1100fb_driver = {
-+ .name = "au1100-lcd",
-+ .bus = &platform_bus_type,
-+
-+ .probe = au1100fb_drv_probe,
-+ .remove = au1100fb_drv_remove,
-+ .suspend = au1100fb_drv_suspend,
-+ .resume = au1100fb_drv_resume,
-+};
-+
-+/*-------------------------------------------------------------------------*/
+ if (do_trace)
+- scmd_printk(KERN_INFO, SCpnt,
+- "qcomm, mbox %d, pid %ld.\n", i, SCpnt->pid);
++ printk("%s: qcomm, mbox %d, target %d.%d:%d, pid %ld.\n",
++ ha->board_name, i, SCpnt->device->channel, SCpnt->device->id,
++ SCpnt->device->lun, SCpnt->pid);
+
+ cpp->reqsen = 1;
+ cpp->dispri = 1;
+@@ -1844,8 +1847,9 @@
+ if (do_dma(shost->io_port, cpp->cp_dma_addr, SEND_CP_DMA)) {
+ unmap_dma(i, ha);
+ SCpnt->host_scribble = NULL;
+- scmd_printk(KERN_INFO, SCpnt,
+- "qcomm, pid %ld, adapter busy.\n", SCpnt->pid);
++ printk("%s: qcomm, target %d.%d:%d, pid %ld, adapter busy.\n",
++ ha->board_name, SCpnt->device->channel, SCpnt->device->id,
++ SCpnt->device->lun, SCpnt->pid);
+ return 1;
+ }
-- if (!options || !*options)
-- return;
-+/* Kernel driver */
-+
-+int au1100fb_setup(char *options)
-+{
-+ char* this_opt;
-+ int num_panels = ARRAY_SIZE(known_lcd_panels);
-+ char* mode = NULL;
-+ int panel_idx = 0;
-+
-+ if (num_panels <= 0) {
-+ print_err("No LCD panels supported by driver!");
-+ return -EFAULT;
-+ }
+@@ -1860,14 +1864,16 @@
+ unsigned int i;
-- for(this_opt=strtok(options, ","); this_opt;
-- this_opt=strtok(NULL, ",")) {
-+ if (options) {
-+ while ((this_opt = strsep(&options,",")) != NULL) {
-+ /* Panel option */
- if (!strncmp(this_opt, "panel:", 6)) {
--#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100)
-- /* Read Pb1100 Switch S10 ? */
-- if (!strncmp(this_opt+6, "s10", 3))
-- {
-- int panel;
-- panel = *(volatile int *)0xAE000008; /* BCSR SWITCHES */
-- panel >>= 8;
-- panel &= 0x0F;
-- if (panel >= num_panels) panel = 0;
-- my_lcd_index = panel;
-- }
-- else
--#endif
-- /* Get the panel name, everything else if fixed */
-- for (i=0; i<num_panels; i++) {
-- if (!strncmp(this_opt+6, panels[i].panel_name,
-+ int i;
-+ this_opt += 6;
-+ for (i = 0; i < num_panels; i++) {
-+ if (!strncmp(this_opt,
-+ known_lcd_panels[i].name,
- strlen(this_opt))) {
-- my_lcd_index = i;
-+ panel_idx = i;
- break;
- }
- }
-+ if (i >= num_panels) {
-+ print_warn("Panel %s not supported!", this_opt);
-+ }
-+ }
-+ /* Mode option (only option that start with digit) */
-+ else if (isdigit(this_opt[0])) {
-+ mode = kmalloc(strlen(this_opt) + 1, GFP_KERNEL);
-+ strncpy(mode, this_opt, strlen(this_opt) + 1);
-+ }
-+ /* Unsupported option */
-+ else {
-+ print_warn("Unsupported option \"%s\"", this_opt);
- }
-- else if (!strncmp(this_opt, "nohwcursor", 10)) {
-- printk("nohwcursor\n");
-- fb_info.nohwcursor = 1;
+ if (SCarg->host_scribble == NULL) {
+- scmd_printk(KERN_INFO, SCarg,
+- "abort, pid %ld inactive.\n", SCarg->pid);
++ printk("%s: abort, target %d.%d:%d, pid %ld inactive.\n",
++ ha->board_name, SCarg->device->channel, SCarg->device->id,
++ SCarg->device->lun, SCarg->pid);
+ return SUCCESS;
+ }
+
+ i = *(unsigned int *)SCarg->host_scribble;
+- scmd_printk(KERN_WARNING, SCarg,
+- "abort, mbox %d, pid %ld.\n", i, SCarg->pid);
++ printk("%s: abort, mbox %d, target %d.%d:%d, pid %ld.\n",
++ ha->board_name, i, SCarg->device->channel, SCarg->device->id,
++ SCarg->device->lun, SCarg->pid);
+
+ if (i >= shost->can_queue)
+ panic("%s: abort, invalid SCarg->host_scribble.\n", ha->board_name);
+@@ -1928,8 +1934,9 @@
+ struct Scsi_Host *shost = SCarg->device->host;
+ struct hostdata *ha = (struct hostdata *)shost->hostdata;
+
+- scmd_printk(KERN_INFO, SCarg,
+- "reset, enter, pid %ld.\n", SCarg->pid);
++ printk("%s: reset, enter, target %d.%d:%d, pid %ld.\n",
++ ha->board_name, SCarg->device->channel, SCarg->device->id,
++ SCarg->device->lun, SCarg->pid);
+
+ spin_lock_irq(shost->host_lock);
+
+@@ -2246,11 +2253,12 @@
+ k = il[n];
+ cpp = &ha->cp[k];
+ SCpnt = cpp->SCpnt;
+- scmd_printk(KERN_INFO, SCpnt,
+- "%s pid %ld mb %d fc %d nr %d sec %ld ns %ld"
++ printk
++ ("%s %d.%d:%d pid %ld mb %d fc %d nr %d sec %ld ns %ld"
+ " cur %ld s:%c r:%c rev:%c in:%c ov:%c xd %d.\n",
+ (ihdlr ? "ihdlr" : "qcomm"),
+- SCpnt->pid, k, flushcount,
++ SCpnt->device->channel, SCpnt->device->id,
++ SCpnt->device->lun, SCpnt->pid, k, flushcount,
+ n_ready, SCpnt->request->sector,
+ SCpnt->request->nr_sectors, cursec, YESNO(s),
+ YESNO(r), YESNO(rev), YESNO(input_only),
+@@ -2293,11 +2301,12 @@
+ SCpnt = cpp->SCpnt;
+
+ if (do_dma(dev->host->io_port, cpp->cp_dma_addr, SEND_CP_DMA)) {
+- scmd_printk(KERN_INFO, SCpnt,
+- "%s, pid %ld, mbox %d, adapter"
+- " busy, will abort.\n",
++ printk
++ ("%s: %s, target %d.%d:%d, pid %ld, mbox %d, adapter"
++ " busy, will abort.\n", ha->board_name,
+ (ihdlr ? "ihdlr" : "qcomm"),
+- SCpnt->pid, k);
++ SCpnt->device->channel, SCpnt->device->id,
++ SCpnt->device->lun, SCpnt->pid, k);
+ ha->cp_stat[k] = ABORTING;
+ continue;
}
-- }
-+ }
+@@ -2533,10 +2542,11 @@
+ spp->adapter_status != ASST && ha->iocount <= 1000) ||
+ do_trace || msg_byte(spp->target_status))
+ #endif
+- scmd_printk(KERN_INFO, SCpnt, "ihdlr, mbox %2d, err 0x%x:%x,"
+- " pid %ld, reg 0x%x, count %d.\n",
+- i, spp->adapter_status, spp->target_status,
+- SCpnt->pid, reg, ha->iocount);
++ printk("%s: ihdlr, mbox %2d, err 0x%x:%x,"
++ " target %d.%d:%d, pid %ld, reg 0x%x, count %d.\n",
++ ha->board_name, i, spp->adapter_status, spp->target_status,
++ SCpnt->device->channel, SCpnt->device->id,
++ SCpnt->device->lun, SCpnt->pid, reg, ha->iocount);
+
+ unmap_dma(i, ha);
+
+diff -urN --ignore-space-change kernel.org/drivers/scsi/jazz_esp.c linux-mips/drivers/scsi/jazz_esp.c
+--- kernel.org/drivers/scsi/jazz_esp.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/scsi/jazz_esp.c 2006-01-10 11:21:47.000000000 +0000
+@@ -52,7 +52,6 @@
+ * via PIO.
+ */
-- printk("au1100fb: Panel %d %s\n", my_lcd_index,
-- panels[my_lcd_index].panel_name);
--}
-+ drv_info.panel_idx = panel_idx;
-+ drv_info.opt_mode = mode;
+-int jazz_esp_detect(struct scsi_host_template *tpnt);
+ static int jazz_esp_release(struct Scsi_Host *shost)
+ {
+ if (shost->irq)
+@@ -65,27 +64,6 @@
+ return 0;
+ }
-+ print_info("Panel=%s Mode=%s",
-+ known_lcd_panels[drv_info.panel_idx].name,
-+ drv_info.opt_mode ? drv_info.opt_mode : "default");
+-static struct scsi_host_template driver_template = {
+- .proc_name = "jazz_esp",
+- .proc_info = &esp_proc_info,
+- .name = "ESP 100/100a/200",
+- .detect = jazz_esp_detect,
+- .slave_alloc = esp_slave_alloc,
+- .slave_destroy = esp_slave_destroy,
+- .release = jazz_esp_release,
+- .info = esp_info,
+- .queuecommand = esp_queue,
+- .eh_abort_handler = esp_abort,
+- .eh_bus_reset_handler = esp_reset,
+- .can_queue = 7,
+- .this_id = 7,
+- .sg_tablesize = SG_ALL,
+- .cmd_per_lun = 1,
+- .use_clustering = DISABLE_CLUSTERING,
+-};
+-
+-#include "scsi_module.c"
+-
+ /***************************************************************** Detection */
+ static int jazz_esp_detect(struct scsi_host_template *tpnt)
+ {
+@@ -96,7 +74,7 @@
+ * first assumption it is there:-)
+ */
+ if (1) {
+- esp_dev = 0;
++ esp_dev = NULL;
+ esp = esp_allocate(tpnt, (void *) esp_dev);
+
+ /* Do command transfer with programmed I/O */
+@@ -115,13 +93,13 @@
+ esp->dma_setup = &dma_setup;
+
+ /* Optional functions */
+- esp->dma_barrier = 0;
+- esp->dma_drain = 0;
+- esp->dma_invalidate = 0;
+- esp->dma_irq_entry = 0;
+- esp->dma_irq_exit = 0;
+- esp->dma_poll = 0;
+- esp->dma_reset = 0;
++ esp->dma_barrier = NULL;
++ esp->dma_drain = NULL;
++ esp->dma_invalidate = NULL;
++ esp->dma_irq_entry = NULL;
++ esp->dma_irq_exit = NULL;
++ esp->dma_poll = NULL;
++ esp->dma_reset = NULL;
+ esp->dma_led_off = &dma_led_off;
+ esp->dma_led_on = &dma_led_on;
+
+@@ -141,7 +119,7 @@
+ * of DMA channel, so we can use the jazz DMA functions
+ *
+ */
+- esp->dregs = JAZZ_SCSI_DMA;
++ esp->dregs = (void *) JAZZ_SCSI_DMA;
+
+ /* ESP register base */
+ esp->eregs = (struct ESP_regs *)(JAZZ_SCSI_BASE);
+diff -urN --ignore-space-change kernel.org/drivers/scsi/sym53c8xx_defs.h linux-mips/drivers/scsi/sym53c8xx_defs.h
+--- kernel.org/drivers/scsi/sym53c8xx_defs.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/scsi/sym53c8xx_defs.h 2006-01-10 11:21:48.000000000 +0000
+@@ -301,9 +301,19 @@
+ #define writew_b2l __raw_writew
+ #define writel_b2l __raw_writel
+ #define readw_raw __raw_readw
+-#define readl_raw __raw_readl
++#define readl_raw(a) __raw_readl((unsigned long)(a))
+ #define writew_raw __raw_writew
+-#define writel_raw __raw_writel
++#define writel_raw(v,a) __raw_writel(v,(unsigned long)(a))
++#else /* Other big-endian */
++#elif defined(__mips__)
++#define readw_l2b readw
++#define readl_l2b readl
++#define writew_b2l writew
++#define writel_b2l writel
++#define inw_l2b inw
++#define inl_l2b inl
++#define outw_b2l outw
++#define outl_b2l outl
+ #else /* Other big-endian */
+ #define readw_l2b readw
+ #define readl_l2b readl
+diff -urN --ignore-space-change kernel.org/drivers/serial/8250.c linux-mips/drivers/serial/8250.c
+--- kernel.org/drivers/serial/8250.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/8250.c 2006-01-10 11:21:48.000000000 +0000
+@@ -2214,8 +2214,10 @@
-+ return 0;
-+}
+ touch_nmi_watchdog();
--#ifdef MODULE
--MODULE_LICENSE("GPL");
--int init_module(void)
-+int __init au1100fb_init(void)
- {
-- return au1100fb_init();
-+ char* options;
-+ int ret;
-+
-+ print_info("" DRIVER_DESC "");
-+
-+ memset(&drv_info, 0, sizeof(drv_info));
-+
-+ if (fb_get_options(DRIVER_NAME, &options))
-+ return -ENODEV;
-+
-+ /* Setup driver with options */
-+ ret = au1100fb_setup(options);
-+ if (ret < 0) {
-+ print_err("Fail to setup driver");
-+ return ret;
-+ }
++ spin_lock(&up->port.lock);
+
-+ return driver_register(&au1100fb_driver);
- }
+ /*
+- * First save the UER then disable the interrupts
++ * First save the IER then disable the interrupts
+ */
+ ier = serial_in(up, UART_IER);
--void cleanup_module(void)
-+void __exit au1100fb_cleanup(void)
- {
-- au1100fb_cleanup(void);
-+ driver_unregister(&au1100fb_driver);
+@@ -2247,6 +2249,8 @@
+ */
+ wait_for_xmitr(up);
+ serial_out(up, UART_IER, ier);
+
-+ if (drv_info.opt_mode)
-+ kfree(drv_info.opt_mode);
++ spin_unlock(&up->port.lock);
}
--MODULE_AUTHOR("Pete Popov <ppopov at mvista.com>");
--MODULE_DESCRIPTION("Au1100 LCD framebuffer device driver");
--#endif /* MODULE */
-+module_init(au1100fb_init);
-+module_exit(au1100fb_cleanup);
-+
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_LICENSE("GPL");
-diff -urpNX dontdiff linux-2.6.12/drivers/video/au1100fb.h linux_HEAD/drivers/video/au1100fb.h
---- linux-2.6.12/drivers/video/au1100fb.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/au1100fb.h 2005-04-05 06:42:36.000000000 +0200
-@@ -30,352 +30,352 @@
- #ifndef _AU1100LCD_H
- #define _AU1100LCD_H
-
-+#include <asm/mach-au1x00/au1000.h>
-+
-+#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
-+#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
-+#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
-+
-+#if DEBUG
-+#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
-+#else
-+#define print_dbg(f, arg...) do {} while (0)
-+#endif
-+
-+#if defined(__BIG_ENDIAN)
-+#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
-+#else
-+#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
-+#endif
-+#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
-+
- /********************************************************************/
--#define uint32 unsigned long
--typedef volatile struct
--{
-- uint32 lcd_control;
-- uint32 lcd_intstatus;
-- uint32 lcd_intenable;
-- uint32 lcd_horztiming;
-- uint32 lcd_verttiming;
-- uint32 lcd_clkcontrol;
-- uint32 lcd_dmaaddr0;
-- uint32 lcd_dmaaddr1;
-- uint32 lcd_words;
-- uint32 lcd_pwmdiv;
-- uint32 lcd_pwmhi;
-- uint32 reserved[(0x0400-0x002C)/4];
-- uint32 lcd_pallettebase[256];
+ static int serial8250_console_setup(struct console *co, char *options)
+diff -urN --ignore-space-change kernel.org/drivers/serial/Kconfig linux-mips/drivers/serial/Kconfig
+--- kernel.org/drivers/serial/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/Kconfig 2006-01-10 11:21:48.000000000 +0000
+@@ -616,6 +616,25 @@
+ If you have an Alchemy AU1X00 processor (MIPS based) and you want
+ to use a console on a serial port, say Y. Otherwise, say N.
+
++config SERIAL_IP3106
++ bool "Enable IP3106 UART Support (Philips PNX 8xx0 SoCs)"
++ depends on MIPS && (SOC_PNX8550 || SOC_PNX8330)
++ select SERIAL_CORE
++ help
++ If you have a Philips SoC with an IP 3106 UART in it, such as
++ the PNX8550 or PNX8330 (MIPS based) and you want to use
++ serial ports, say Y. Otherwise, say N.
++
++config SERIAL_IP3106_CONSOLE
++ bool "Enable PNX8XX0 serial console"
++ depends on SERIAL_IP3106
++ select SERIAL_CORE_CONSOLE
++ help
++ If you have a Philips SoC with an IP 3106 UART in it, such as
++ the PNX8550 or PNX8330 (MIPS based) and you want to use
++ a serial console, say Y.
++ Otherwise, say N.
++
+ config SERIAL_CORE
+ tristate
+
+diff -urN --ignore-space-change kernel.org/drivers/serial/Makefile linux-mips/drivers/serial/Makefile
+--- kernel.org/drivers/serial/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/Makefile 2006-01-10 11:21:48.000000000 +0000
+@@ -43,6 +43,7 @@
+ obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
+ obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
+ obj-$(CONFIG_SERIAL_AU1X00) += au1x00_uart.o
++obj-$(CONFIG_SERIAL_IP3106) += ip3106_uart.o
+ obj-$(CONFIG_SERIAL_DZ) += dz.o
+ obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
+ obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
+diff -urN --ignore-space-change kernel.org/drivers/serial/au1x00_uart.c linux-mips/drivers/serial/au1x00_uart.c
+--- kernel.org/drivers/serial/au1x00_uart.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/au1x00_uart.c 2006-01-10 11:21:48.000000000 +0000
+@@ -67,30 +67,7 @@
+ #define is_real_interrupt(irq) ((irq) != 0)
--} AU1100_LCD;
-+/* LCD controller restrictions */
-+#define AU1100_LCD_MAX_XRES 800
-+#define AU1100_LCD_MAX_YRES 600
-+#define AU1100_LCD_MAX_BPP 16
-+#define AU1100_LCD_MAX_CLK 48000000
-+#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
-+
-+/* Default number of visible screen buffer to allocate */
-+#define AU1100FB_NBR_VIDEO_BUFFERS 4
+ static struct old_serial_port old_serial_port[] = {
+- { .baud_base = 0,
+- .iomem_base = (u8 *)UART0_ADDR,
+- .irq = AU1000_UART0_INT,
+- .flags = STD_COM_FLAGS,
+- .iomem_reg_shift = 2,
+- }, {
+- .baud_base = 0,
+- .iomem_base = (u8 *)UART1_ADDR,
+- .irq = AU1000_UART1_INT,
+- .flags = STD_COM_FLAGS,
+- .iomem_reg_shift = 2
+- }, {
+- .baud_base = 0,
+- .iomem_base = (u8 *)UART2_ADDR,
+- .irq = AU1000_UART2_INT,
+- .flags = STD_COM_FLAGS,
+- .iomem_reg_shift = 2
+- }, {
+- .baud_base = 0,
+- .iomem_base = (u8 *)UART3_ADDR,
+- .irq = AU1000_UART3_INT,
+- .flags = STD_COM_FLAGS,
+- .iomem_reg_shift = 2
+- }
++ SERIAL_PORT_DFNS
+ };
- /********************************************************************/
+ #define UART_NR ARRAY_SIZE(old_serial_port)
+@@ -800,7 +777,6 @@
+ */
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ quot = serial8250_get_divisor(port, baud);
+- quot = 0x35; /* FIXME */
--#define AU1100_LCD_ADDR 0xB5000000
-+struct au1100fb_panel
-+{
-+ const char name[25]; /* Full name <vendor>_<model> */
+ /*
+ * Work around a bug in the Oxford Semiconductor 952 rev B
+@@ -866,6 +842,7 @@
--/*
-- * Register bit definitions
-- */
-+ u32 control_base; /* Mode-independent control values */
-+ u32 clkcontrol_base; /* Panel pixclock preferences */
+ serial_out(up, UART_IER, up->ier);
+ serial_outp(up, 0x28, quot & 0xffff);
++ serial_out(up, UART_LCR, cval); /* reset DLAB */
+ up->lcr = cval; /* Save LCR */
+ if (up->port.type != PORT_16750) {
+ if (fcr & UART_FCR_ENABLE_FIFO) {
+@@ -1068,7 +1045,7 @@
+ i++, up++) {
+ up->port.iobase = old_serial_port[i].port;
+ up->port.irq = old_serial_port[i].irq;
+- up->port.uartclk = get_au1x00_uart_baud_base();
++ up->port.uartclk = get_au1x00_uart_baud_base() * 16;
+ up->port.flags = old_serial_port[i].flags;
+ up->port.hub6 = old_serial_port[i].hub6;
+ up->port.membase = old_serial_port[i].iomem_base;
+@@ -1206,7 +1183,7 @@
+ return uart_set_options(port, co, baud, parity, bits, flow);
+ }
--/* lcd_control */
--#define LCD_CONTROL_SBPPF (7<<18)
--#define LCD_CONTROL_SBPPF_655 (0<<18)
--#define LCD_CONTROL_SBPPF_565 (1<<18)
--#define LCD_CONTROL_SBPPF_556 (2<<18)
--#define LCD_CONTROL_SBPPF_1555 (3<<18)
--#define LCD_CONTROL_SBPPF_5551 (4<<18)
--#define LCD_CONTROL_WP (1<<17)
--#define LCD_CONTROL_WD (1<<16)
--#define LCD_CONTROL_C (1<<15)
--#define LCD_CONTROL_SM (3<<13)
--#define LCD_CONTROL_SM_0 (0<<13)
--#define LCD_CONTROL_SM_90 (1<<13)
--#define LCD_CONTROL_SM_180 (2<<13)
--#define LCD_CONTROL_SM_270 (3<<13)
--#define LCD_CONTROL_DB (1<<12)
--#define LCD_CONTROL_CCO (1<<11)
--#define LCD_CONTROL_DP (1<<10)
--#define LCD_CONTROL_PO (3<<8)
--#define LCD_CONTROL_PO_00 (0<<8)
--#define LCD_CONTROL_PO_01 (1<<8)
--#define LCD_CONTROL_PO_10 (2<<8)
--#define LCD_CONTROL_PO_11 (3<<8)
--#define LCD_CONTROL_MPI (1<<7)
--#define LCD_CONTROL_PT (1<<6)
--#define LCD_CONTROL_PC (1<<5)
--#define LCD_CONTROL_BPP (7<<1)
--#define LCD_CONTROL_BPP_1 (0<<1)
--#define LCD_CONTROL_BPP_2 (1<<1)
--#define LCD_CONTROL_BPP_4 (2<<1)
--#define LCD_CONTROL_BPP_8 (3<<1)
--#define LCD_CONTROL_BPP_12 (4<<1)
--#define LCD_CONTROL_BPP_16 (5<<1)
--#define LCD_CONTROL_GO (1<<0)
--
--/* lcd_intstatus, lcd_intenable */
--#define LCD_INT_SD (1<<7)
--#define LCD_INT_OF (1<<6)
--#define LCD_INT_UF (1<<5)
--#define LCD_INT_SA (1<<3)
--#define LCD_INT_SS (1<<2)
--#define LCD_INT_S1 (1<<1)
--#define LCD_INT_S0 (1<<0)
--
--/* lcd_horztiming */
--#define LCD_HORZTIMING_HN2 (255<<24)
--#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
--#define LCD_HORZTIMING_HN1 (255<<16)
--#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
--#define LCD_HORZTIMING_HPW (63<<10)
--#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
--#define LCD_HORZTIMING_PPL (1023<<0)
--#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
--
--/* lcd_verttiming */
--#define LCD_VERTTIMING_VN2 (255<<24)
--#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
--#define LCD_VERTTIMING_VN1 (255<<16)
--#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
--#define LCD_VERTTIMING_VPW (63<<10)
--#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
--#define LCD_VERTTIMING_LPP (1023<<0)
--#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
--
--/* lcd_clkcontrol */
--#define LCD_CLKCONTROL_IB (1<<18)
--#define LCD_CLKCONTROL_IC (1<<17)
--#define LCD_CLKCONTROL_IH (1<<16)
--#define LCD_CLKCONTROL_IV (1<<15)
--#define LCD_CLKCONTROL_BF (31<<10)
--#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
--#define LCD_CLKCONTROL_PCD (1023<<0)
--#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
--
--/* lcd_pwmdiv */
--#define LCD_PWMDIV_EN (1<<12)
--#define LCD_PWMDIV_PWMDIV (2047<<0)
--#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0)
--
--/* lcd_pwmhi */
--#define LCD_PWMHI_PWMHI1 (2047<<12)
--#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12)
--#define LCD_PWMHI_PWMHI0 (2047<<0)
--#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
--
--/* lcd_pallettebase - MONOCHROME */
--#define LCD_PALLETTE_MONO_MI (15<<0)
--#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0)
--
--/* lcd_pallettebase - COLOR */
--#define LCD_PALLETTE_COLOR_BI (15<<8)
--#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8)
--#define LCD_PALLETTE_COLOR_GI (15<<4)
--#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4)
--#define LCD_PALLETTE_COLOR_RI (15<<0)
--#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0)
--
--/* lcd_palletebase - COLOR TFT PALLETIZED */
--#define LCD_PALLETTE_TFT_DC (65535<<0)
--#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0)
-+ u32 horztiming;
-+ u32 verttiming;
-
--/********************************************************************/
-+ u32 xres; /* Maximum horizontal resolution */
-+ u32 yres; /* Maximum vertical resolution */
-+ u32 bpp; /* Maximum depth supported */
-+};
+-extern struct uart_driver serial8250_reg;
++static struct uart_driver serial8250_reg;
+ static struct console serial8250_console = {
+ .name = "ttyS",
+ .write = serial8250_console_write,
+diff -urN --ignore-space-change kernel.org/drivers/serial/dz.c linux-mips/drivers/serial/dz.c
+--- kernel.org/drivers/serial/dz.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/dz.c 2006-01-10 11:21:48.000000000 +0000
+@@ -264,6 +264,7 @@
+ }
+ tty_insert_flip_char(tty, ch, flag);
+ ignore_char:
++ ;
+ } while (status & DZ_DVAL);
--struct known_lcd_panels
-+struct au1100fb_regs
- {
-- uint32 xres;
-- uint32 yres;
-- uint32 bpp;
-- unsigned char panel_name[256];
-- uint32 mode_control;
-- uint32 mode_horztiming;
-- uint32 mode_verttiming;
-- uint32 mode_clkcontrol;
-- uint32 mode_pwmdiv;
-- uint32 mode_pwmhi;
-- uint32 mode_toyclksrc;
-- uint32 mode_backlight;
-+ u32 lcd_control;
-+ u32 lcd_intstatus;
-+ u32 lcd_intenable;
-+ u32 lcd_horztiming;
-+ u32 lcd_verttiming;
-+ u32 lcd_clkcontrol;
-+ u32 lcd_dmaaddr0;
-+ u32 lcd_dmaaddr1;
-+ u32 lcd_words;
-+ u32 lcd_pwmdiv;
-+ u32 lcd_pwmhi;
-+ u32 reserved[(0x0400-0x002C)/4];
-+ u32 lcd_pallettebase[256];
-+};
-+
-+struct au1100fb_device {
-+
-+ struct fb_info info; /* FB driver info record */
-+
-+ struct au1100fb_panel *panel; /* Panel connected to this device */
+ if (tty)
+diff -urN --ignore-space-change kernel.org/drivers/serial/ip22zilog.c linux-mips/drivers/serial/ip22zilog.c
+--- kernel.org/drivers/serial/ip22zilog.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/serial/ip22zilog.c 2006-01-10 11:21:48.000000000 +0000
+@@ -882,6 +882,7 @@
+ up->cflag = termios->c_cflag;
-+ struct au1100fb_regs* regs; /* Registers memory map */
-+ size_t regs_len;
-+ unsigned int regs_phys;
-+
-+ unsigned char* fb_mem; /* FrameBuffer memory map */
-+ size_t fb_len;
-+ dma_addr_t fb_phys;
- };
+ ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
++ uart_update_timeout(port, termios->c_cflag, baud);
--#if defined(__BIG_ENDIAN)
--#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
--#else
--#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
--#endif
-+/********************************************************************/
+ spin_unlock_irqrestore(&up->port.lock, flags);
+ }
+@@ -1048,6 +1049,8 @@
+ }
--/*
-- * The fb driver assumes that AUX PLL is at 48MHz. That can
-- * cover up to 800x600 resolution; if you need higher resolution,
-- * you should modify the driver as needed, not just this structure.
-+#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
-+ #define LCD_CONTROL_SBB_BIT 21
-+ #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
-+ #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
-+ #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
-+ #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
-+ #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
-+ #define LCD_CONTROL_SBPPF_BIT 18
-+ #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
-+ #define LCD_CONTROL_WP (1<<17)
-+ #define LCD_CONTROL_WD (1<<16)
-+ #define LCD_CONTROL_C (1<<15)
-+ #define LCD_CONTROL_SM_BIT 13
-+ #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
-+ #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
-+ #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
-+ #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
-+ #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
-+ #define LCD_CONTROL_DB (1<<12)
-+ #define LCD_CONTROL_CCO (1<<11)
-+ #define LCD_CONTROL_DP (1<<10)
-+ #define LCD_CONTROL_PO_BIT 8
-+ #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
-+ #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
-+ #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
-+ #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
-+ #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
-+ #define LCD_CONTROL_MPI (1<<7)
-+ #define LCD_CONTROL_PT (1<<6)
-+ #define LCD_CONTROL_PC (1<<5)
-+ #define LCD_CONTROL_BPP_BIT 1
-+ #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
-+ #define LCD_CONTROL_GO (1<<0)
-+
-+#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
-+#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
-+ #define LCD_INT_SD (1<<7)
-+ #define LCD_INT_OF (1<<6)
-+ #define LCD_INT_UF (1<<5)
-+ #define LCD_INT_SA (1<<3)
-+ #define LCD_INT_SS (1<<2)
-+ #define LCD_INT_S1 (1<<1)
-+ #define LCD_INT_S0 (1<<0)
-+
-+#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
-+ #define LCD_HORZTIMING_HN2_BIT 24
-+ #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
-+ #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
-+ #define LCD_HORZTIMING_HN1_BIT 16
-+ #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
-+ #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
-+ #define LCD_HORZTIMING_HPW_BIT 10
-+ #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
-+ #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
-+ #define LCD_HORZTIMING_PPL_BIT 0
-+ #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
-+ #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
-+
-+#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
-+ #define LCD_VERTTIMING_VN2_BIT 24
-+ #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
-+ #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
-+ #define LCD_VERTTIMING_VN1_BIT 16
-+ #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
-+ #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
-+ #define LCD_VERTTIMING_VPW_BIT 10
-+ #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
-+ #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
-+ #define LCD_VERTTIMING_LPP_BIT 0
-+ #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
-+ #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
-+
-+#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
-+ #define LCD_CLKCONTROL_IB (1<<18)
-+ #define LCD_CLKCONTROL_IC (1<<17)
-+ #define LCD_CLKCONTROL_IH (1<<16)
-+ #define LCD_CLKCONTROL_IV (1<<15)
-+ #define LCD_CLKCONTROL_BF_BIT 10
-+ #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
-+ #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
-+ #define LCD_CLKCONTROL_PCD_BIT 0
-+ #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
-+ #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
-+
-+#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
-+#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
-+ #define LCD_DMA_SA_BIT 5
-+ #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
-+ #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
-+
-+#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
-+ #define LCD_WRD_WRDS_BIT 0
-+ #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
-+ #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
-+
-+#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
-+ #define LCD_PWMDIV_EN (1<<12)
-+ #define LCD_PWMDIV_PWMDIV_BIT 0
-+ #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
-+ #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
-+
-+#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
-+ #define LCD_PWMHI_PWMHI1_BIT 12
-+ #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
-+ #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
-+ #define LCD_PWMHI_PWMHI0_BIT 0
-+ #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
-+ #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
-+
-+#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
-+ #define LCD_PALLETTE_MONO_MI_BIT 0
-+ #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
-+ #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
-+
-+ #define LCD_PALLETTE_COLOR_RI_BIT 8
-+ #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
-+ #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
-+ #define LCD_PALLETTE_COLOR_GI_BIT 4
-+ #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
-+ #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
-+ #define LCD_PALLETTE_COLOR_BI_BIT 0
-+ #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
-+ #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
-+
-+ #define LCD_PALLETTE_TFT_DC_BIT 0
-+ #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
-+ #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
-+
-+/********************************************************************/
+ con->cflag = cflag | CS8; /* 8N1 */
+
-+/* List of panels known to work with the AU1100 LCD controller.
-+ * To add a new panel, enter the same specifications as the
-+ * Generic_TFT one, and MAKE SURE that it doesn't conflicts
-+ * with the controller restrictions. Restrictions are:
-+ *
-+ * STN color panels: max_bpp <= 12
-+ * STN mono panels: max_bpp <= 4
-+ * TFT panels: max_bpp <= 16
-+ * max_xres <= 800
-+ * max_yres <= 600
- */
--struct known_lcd_panels panels[] =
-+static struct au1100fb_panel known_lcd_panels[] =
- {
-- { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */
-- 320, /* xres */
-- 240, /* yres */
-- 16, /* bpp */
--
-- "Sharp_320x240_16",
-- /* mode_control */
-+ /* 800x600x16bpp CRT */
-+ [0] = {
-+ .name = "CRT_800x600_16",
-+ .xres = 800,
-+ .yres = 600,
-+ .bpp = 16,
-+ .control_base = 0x0004886A |
-+ LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
-+ LCD_CONTROL_BPP_16,
-+ .clkcontrol_base = 0x00020000,
-+ .horztiming = 0x005aff1f,
-+ .verttiming = 0x16000e57,
-+ },
-+ /* just the standard LCD */
-+ [1] = {
-+ .name = "WWPC LCD",
-+ .xres = 240,
-+ .yres = 320,
-+ .bpp = 16,
-+ .control_base = 0x0006806A,
-+ .horztiming = 0x0A1010EF,
-+ .verttiming = 0x0301013F,
-+ .clkcontrol_base = 0x00018001,
-+ },
-+ /* Sharp 320x240 TFT panel */
-+ [2] = {
-+ .name = "Sharp_LQ038Q5DR01",
-+ .xres = 320,
-+ .yres = 240,
-+ .bpp = 16,
-+ .control_base =
- ( LCD_CONTROL_SBPPF_565
-- /*LCD_CONTROL_WP*/
-- /*LCD_CONTROL_WD*/
- | LCD_CONTROL_C
- | LCD_CONTROL_SM_0
-- /*LCD_CONTROL_DB*/
-- /*LCD_CONTROL_CCO*/
-- /*LCD_CONTROL_DP*/
-- | LCD_DEFAULT_PIX_FORMAT
-- /*LCD_CONTROL_MPI*/
-+ | LCD_CONTROL_DEFAULT_PO
- | LCD_CONTROL_PT
- | LCD_CONTROL_PC
- | LCD_CONTROL_BPP_16 ),
--
-- /* mode_horztiming */
-+ .horztiming =
- ( LCD_HORZTIMING_HN2_N(8)
- | LCD_HORZTIMING_HN1_N(60)
- | LCD_HORZTIMING_HPW_N(12)
- | LCD_HORZTIMING_PPL_N(320) ),
--
-- /* mode_verttiming */
-+ .verttiming =
- ( LCD_VERTTIMING_VN2_N(5)
- | LCD_VERTTIMING_VN1_N(17)
- | LCD_VERTTIMING_VPW_N(1)
- | LCD_VERTTIMING_LPP_N(240) ),
--
-- /* mode_clkcontrol */
-- ( 0
-- /*LCD_CLKCONTROL_IB*/
-- /*LCD_CLKCONTROL_IC*/
-- /*LCD_CLKCONTROL_IH*/
-- /*LCD_CLKCONTROL_IV*/
-- | LCD_CLKCONTROL_PCD_N(1) ),
--
-- /* mode_pwmdiv */
-- 0,
--
-- /* mode_pwmhi */
-- 0,
--
-- /* mode_toyclksrc */
-- ((1<<7) | (1<<6) | (1<<5)),
--
-- /* mode_backlight */
-- 6
-+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
- },
-
-- { /* 1: Pb1100 LCDC 640x480 TFT panel */
-- 640, /* xres */
-- 480, /* yres */
-- 16, /* bpp */
--
-- "Generic_640x480_16",
--
-- /* mode_control */
-- 0x004806a | LCD_DEFAULT_PIX_FORMAT,
--
-- /* mode_horztiming */
-- 0x3434d67f,
--
-- /* mode_verttiming */
-- 0x0e0e39df,
--
-- /* mode_clkcontrol */
-- ( 0
-- /*LCD_CLKCONTROL_IB*/
-- /*LCD_CLKCONTROL_IC*/
-- /*LCD_CLKCONTROL_IH*/
-- /*LCD_CLKCONTROL_IV*/
-- | LCD_CLKCONTROL_PCD_N(1) ),
--
-- /* mode_pwmdiv */
-- 0,
--
-- /* mode_pwmhi */
-- 0,
--
-- /* mode_toyclksrc */
-- ((1<<7) | (1<<6) | (0<<5)),
--
-- /* mode_backlight */
-- 7
-+ /* Hitachi SP14Q005 and possibly others */
-+ [3] = {
-+ .name = "Hitachi_SP14Qxxx",
-+ .xres = 320,
-+ .yres = 240,
-+ .bpp = 4,
-+ .control_base =
-+ ( LCD_CONTROL_C
-+ | LCD_CONTROL_BPP_4 ),
-+ .horztiming =
-+ ( LCD_HORZTIMING_HN2_N(1)
-+ | LCD_HORZTIMING_HN1_N(1)
-+ | LCD_HORZTIMING_HPW_N(1)
-+ | LCD_HORZTIMING_PPL_N(320) ),
-+ .verttiming =
-+ ( LCD_VERTTIMING_VN2_N(1)
-+ | LCD_VERTTIMING_VN1_N(1)
-+ | LCD_VERTTIMING_VPW_N(1)
-+ | LCD_VERTTIMING_LPP_N(240) ),
-+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
- },
-
-- { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */
-- 640, /* xres */
-- 480, /* yres */
-- 16, /* bpp */
--
-- "PrimeView_640x480_16",
--
-- /* mode_control */
-- 0x0004886a | LCD_DEFAULT_PIX_FORMAT,
--
-- /* mode_horztiming */
-- 0x0e4bfe7f,
--
-- /* mode_verttiming */
-- 0x210805df,
--
-- /* mode_clkcontrol */
-- 0x00038001,
--
-- /* mode_pwmdiv */
-- 0,
--
-- /* mode_pwmhi */
-- 0,
--
-- /* mode_toyclksrc */
-- ((1<<7) | (1<<6) | (0<<5)),
--
-- /* mode_backlight */
-- 7
-+ /* Generic 640x480 TFT panel */
-+ [4] = {
-+ .name = "TFT_640x480_16",
-+ .xres = 640,
-+ .yres = 480,
-+ .bpp = 16,
-+ .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
-+ .horztiming = 0x3434d67f,
-+ .verttiming = 0x0e0e39df,
-+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
- },
-
-- { /* 3: Pb1100 800x600x16bpp NEON CRT */
-- 800, /* xres */
-- 600, /* yres */
-- 16, /* bpp */
--
-- "NEON_800x600_16",
--
-- /* mode_control */
-- 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
--
-- /* mode_horztiming */
-- 0x005AFF1F,
--
-- /* mode_verttiming */
-- 0x16000E57,
--
-- /* mode_clkcontrol */
-- 0x00020000,
--
-- /* mode_pwmdiv */
-- 0,
--
-- /* mode_pwmhi */
-- 0,
--
-- /* mode_toyclksrc */
-- ((1<<7) | (1<<6) | (0<<5)),
--
-- /* mode_backlight */
-- 7
-+ /* Pb1100 LCDB 640x480 PrimeView TFT panel */
-+ [5] = {
-+ .name = "PrimeView_640x480_16",
-+ .xres = 640,
-+ .yres = 480,
-+ .bpp = 16,
-+ .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
-+ .horztiming = 0x0e4bfe7f,
-+ .verttiming = 0x210805df,
-+ .clkcontrol_base = 0x00038001,
- },
-+};
-
-- { /* 4: Pb1100 640x480x16bpp NEON CRT */
-- 640, /* xres */
-- 480, /* yres */
-- 16, /* bpp */
--
-- "NEON_640x480_16",
--
-- /* mode_control */
-- 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
--
-- /* mode_horztiming */
-- 0x0052E27F,
--
-- /* mode_verttiming */
-- 0x18000DDF,
--
-- /* mode_clkcontrol */
-- 0x00020000,
-+struct au1100fb_drv_info {
-+ int panel_idx;
-+ char *opt_mode;
-+};
-
-- /* mode_pwmdiv */
-- 0,
-+/********************************************************************/
-
-- /* mode_pwmhi */
-- 0,
-+/* Inline helpers */
++ uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud);
+ }
-- /* mode_toyclksrc */
-- ((1<<7) | (1<<6) | (0<<5)),
-+#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
-+#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
-+#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
-+#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
-
-- /* mode_backlight */
-- 7
-- },
--};
- #endif /* _AU1100LCD_H */
-diff -urpNX dontdiff linux-2.6.12/drivers/video/epson1356fb.c linux_HEAD/drivers/video/epson1356fb.c
---- linux-2.6.12/drivers/video/epson1356fb.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/video/epson1356fb.c 2005-07-07 11:22:55.000000000 +0200
-@@ -0,0 +1,3117 @@
+ static int __init ip22zilog_console_setup(struct console *con, char *options)
+diff -urN --ignore-space-change kernel.org/drivers/serial/ip3106_uart.c linux-mips/drivers/serial/ip3106_uart.c
+--- kernel.org/drivers/serial/ip3106_uart.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/serial/ip3106_uart.c 2006-01-10 11:21:48.000000000 +0000
+@@ -0,0 +1,912 @@
+/*
-+ * epson1356fb.c -- Epson SED1356 Framebuffer Driver
-+ *
-+ * Copyright 2001, 2002 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or source at mvista.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
++ * Initially based on linux-2.4.20_mvl31-pnx8xx0/drivers/char/serial_pnx8550.c
+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ * Complete rewrite to drivers/serial/pnx8550_uart.c by
++ * Embedded Alley Solutions, source at embeddedalley.com as part of the
++ * PNX8550 2.6 port, and then drivers/serial/ip3106_uart.c to work
++ * with other Philips SoCs.
+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ * Existing copyrights from files used to write this driver:
++ * Author: Per Hallsmark per.hallsmark at mvista.com
+ *
-+ *
-+ * TODO:
++ * and
+ *
-+ * Revision history
-+ * 03.12.2001 0.1 Initial release
++ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
++ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ */
+
+#include <linux/config.h>
-+#include <linux/version.h>
-+#include <linux/module.h>
+
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/tty.h>
-+#include <linux/slab.h>
-+#include <linux/vmalloc.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/fb.h>
-+#include <linux/selection.h>
-+#include <linux/console.h>
++#if defined(CONFIG_SERIAL_IP3106_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/module.h>
++#include <linux/ioport.h>
+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <linux/nvram.h>
-+#include <linux/kd.h>
-+#include <linux/vt_kern.h>
++#include <linux/console.h>
++#include <linux/sysrq.h>
++#include <linux/device.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/serial_ip3106.h>
++
+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <linux/timer.h>
-+#include <linux/pagemap.h>
++#include <asm/irq.h>
+
-+#include <asm/pgalloc.h>
-+#include <asm/uaccess.h>
-+#include <asm/tlb.h>
++#include <uart.h>
+
-+#ifdef CONFIG_MTRR
-+#include <asm/mtrr.h>
-+#endif
++/* We've been assigned a range on the "Low-density serial ports" major */
++#define SERIAL_IP3106_MAJOR 204
++#define MINOR_START 5
++
++#define NR_PORTS 2
++
++#define IP3106_ISR_PASS_LIMIT 256
++
++/*
++ * Convert from ignore_status_mask or read_status_mask to FIFO
++ * and interrupt status bits
++ */
++#define SM_TO_FIFO(x) ((x) >> 10)
++#define SM_TO_ISTAT(x) ((x) & 0x000001ff)
++#define FIFO_TO_SM(x) ((x) << 10)
++#define ISTAT_TO_SM(x) ((x) & 0x000001ff)
++
++/*
++ * This is the size of our serial port register set.
++ */
++#define UART_PORT_SIZE 0x1000
++
++/*
++ * This determines how often we check the modem status signals
++ * for any change. They generally aren't connected to an IRQ
++ * so we have to poll them. We also check immediately before
++ * filling the TX fifo incase CTS has been dropped.
++ */
++#define MCTRL_TIMEOUT (250*HZ/1000)
++
++
++extern struct ip3106_port ip3106_ports[];
++
++static inline int serial_in(struct ip3106_port *sport, int offset)
++{
++ return (__raw_readl(sport->port.membase + offset));
++}
++
++static inline void serial_out(struct ip3106_port *sport, int offset, int value)
++{
++ __raw_writel(value, sport->port.membase + offset);
++}
+
-+#include <video/fbcon.h>
-+#include <video/fbcon-cfb8.h>
-+#include <video/fbcon-cfb16.h>
-+#include <video/fbcon-cfb24.h>
-+#include <video/fbcon-cfb32.h>
++/*
++ * Handle any change of modem status signal since we were last called.
++ */
++static void ip3106_mctrl_check(struct ip3106_port *sport)
++{
++ unsigned int status, changed;
+
-+#include <linux/spinlock.h>
++ status = sport->port.ops->get_mctrl(&sport->port);
++ changed = status ^ sport->old_status;
+
-+#include <linux/e1356fb.h>
++ if (changed == 0)
++ return;
+
-+#ifdef CONFIG_MIPS_AU1000
-+#include <asm/au1000.h>
-+#endif
++ sport->old_status = status;
+
-+#define E1356FB_DEBUG 1
-+#undef E1356FB_VERBOSE_DEBUG
-+#undef SHADOW_FRAME_BUFFER
-+#include "epson1356fb.h"
++ if (changed & TIOCM_RI)
++ sport->port.icount.rng++;
++ if (changed & TIOCM_DSR)
++ sport->port.icount.dsr++;
++ if (changed & TIOCM_CAR)
++ uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
++ if (changed & TIOCM_CTS)
++ uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
+
-+static char *options;
-+MODULE_PARM(options, "s");
++ wake_up_interruptible(&sport->port.info->delta_msr_wait);
++}
+
+/*
-+ * Frame buffer device API
++ * This is our per-port timeout handler, for checking the
++ * modem status signals.
+ */
-+static int e1356fb_open(struct fb_info *fb, int user);
-+static int e1356fb_release(struct fb_info *fb, int user);
-+static int e1356fb_get_fix(struct fb_fix_screeninfo* fix,
-+ int con,
-+ struct fb_info* fb);
-+static int e1356fb_get_var(struct fb_var_screeninfo* var,
-+ int con,
-+ struct fb_info* fb);
-+static int e1356fb_set_var(struct fb_var_screeninfo* var,
-+ int con,
-+ struct fb_info* fb);
-+static int e1356fb_pan_display(struct fb_var_screeninfo* var,
-+ int con,
-+ struct fb_info* fb);
-+static int e1356fb_get_cmap(struct fb_cmap *cmap,
-+ int kspc,
-+ int con,
-+ struct fb_info* info);
-+static int e1356fb_set_cmap(struct fb_cmap* cmap,
-+ int kspc,
-+ int con,
-+ struct fb_info* info);
-+static int e1356fb_ioctl(struct inode* inode,
-+ struct file* file,
-+ u_int cmd,
-+ u_long arg,
-+ int con,
-+ struct fb_info* info);
-+static int e1356fb_mmap(struct fb_info *info,
-+ struct file *file,
-+ struct vm_area_struct *vma);
++static void ip3106_timeout(unsigned long data)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)data;
++ unsigned long flags;
++
++ if (sport->port.info) {
++ spin_lock_irqsave(&sport->port.lock, flags);
++ ip3106_mctrl_check(sport);
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++
++ mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
++ }
++}
+
+/*
-+ * Interface to the low level console driver
++ * interrupts disabled on entry
+ */
-+static int e1356fb_switch_con(int con,
-+ struct fb_info* fb);
-+static int e1356fb_updatevar(int con,
-+ struct fb_info* fb);
-+static void e1356fb_blank(int blank,
-+ struct fb_info* fb);
++static void ip3106_stop_tx(struct uart_port *port, unsigned int tty_stop)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ u32 ien;
++
++ /* Disable TX intr */
++ ien = serial_in(sport, IP3106_IEN);
++ serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLTX);
++
++ /* Clear all pending TX intr */
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
++}
+
+/*
-+ * Internal routines
++ * interrupts may not be disabled on entry
+ */
-+static void e1356fb_set_par(const struct e1356fb_par* par,
-+ struct fb_info_e1356*
-+ info);
-+static int e1356fb_var_to_par(const struct fb_var_screeninfo *var,
-+ struct e1356fb_par* par,
-+ const struct fb_info_e1356* info);
-+static int e1356fb_par_to_var(struct fb_var_screeninfo* var,
-+ struct e1356fb_par* par,
-+ const struct fb_info_e1356* info);
-+static int e1356fb_encode_fix(struct fb_fix_screeninfo* fix,
-+ const struct e1356fb_par* par,
-+ const struct fb_info_e1356* info);
-+static void e1356fb_set_dispsw(struct display* disp,
-+ struct fb_info_e1356* info,
-+ int bpp,
-+ int accel);
-+static int e1356fb_getcolreg(u_int regno,
-+ u_int* red,
-+ u_int* green,
-+ u_int* blue,
-+ u_int* transp,
-+ struct fb_info* fb);
-+static int e1356fb_setcolreg(u_int regno,
-+ u_int red,
-+ u_int green,
-+ u_int blue,
-+ u_int transp,
-+ struct fb_info* fb);
-+static void e1356fb_install_cmap(struct display *d,
-+ struct fb_info *info);
-+
-+static void e1356fb_hwcursor_init(struct fb_info_e1356* info);
-+static void e1356fb_createcursorshape(struct display* p);
-+static void e1356fb_createcursor(struct display * p);
++static void ip3106_start_tx(struct uart_port *port, unsigned int tty_start)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ unsigned long flags;
++ u32 ien;
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++
++ /* Clear all pending TX intr */
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
++
++ /* Enable TX intr */
++ ien = serial_in(sport, IP3106_IEN);
++ serial_out(sport, IP3106_IEN, ien | IP3106_UART_INT_ALLTX);
++
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++}
+
+/*
-+ * do_xxx: Hardware-specific functions
++ * Interrupts enabled
+ */
-+static void do_pan_var(struct fb_var_screeninfo* var,
-+ struct fb_info_e1356* i);
-+static void do_flashcursor(unsigned long ptr);
-+static void doBlt_Move(const struct e1356fb_par* par,
-+ struct fb_info_e1356* i,
-+ blt_info_t* blt);
-+static void doBlt_SolidFill(const struct e1356fb_par* par,
-+ struct fb_info_e1356* i,
-+ blt_info_t* blt);
++static void ip3106_stop_rx(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ u32 ien;
++
++ /* Disable RX intr */
++ ien = serial_in(sport, IP3106_IEN);
++ serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLRX);
++
++ /* Clear all pending RX intr */
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX);
++}
+
+/*
-+ * Interface used by the world
++ * Set the modem control timer to fire immediately.
+ */
-+int e1356fb_init(void);
-+void e1356fb_setup(char *options, int *ints);
++static void ip3106_enable_ms(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
+
-+static int currcon = 0;
++ mod_timer(&sport->timer, jiffies);
++}
+
-+static struct fb_ops e1356fb_ops = {
-+ .owner = THIS_MODULE,
-+ .fb_open = e1356fb_open,
-+ .fb_release = e1356fb_release,
-+ .fb_get_fix = e1356fb_get_fix,
-+ .fb_get_var = e1356fb_get_var,
-+ .fb_set_var = e1356fb_set_var,
-+ .fb_get_cmap = e1356fb_get_cmap,
-+ .fb_set_cmap = e1356fb_set_cmap,
-+ .fb_pan_display = e1356fb_pan_display,
-+ .fb_mmap = e1356fb_mmap,
-+};
++static void
++ip3106_rx_chars(struct ip3106_port *sport, struct pt_regs *regs)
++{
++ struct tty_struct *tty = sport->port.info->tty;
++ unsigned int status, ch, flg, ignored = 0;
++
++ status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
++ ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
++ while (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFIFO)) {
++ ch = serial_in(sport, IP3106_FIFO);
++
++ if (tty->flip.count >= TTY_FLIPBUF_SIZE)
++ goto ignore_char;
++ sport->port.icount.rx++;
+
-+#define PCI_VENDOR_ID_EPSON 0x10f4
-+#define PCI_DEVICE_ID_EPSON_SDU1356 0x1300
++ flg = TTY_NORMAL;
+
++ /*
++ * note that the error handling code is
++ * out of the main execution path
++ */
++ if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE |
++ IP3106_UART_FIFO_RXPAR))
++ goto handle_error;
++
++ if (uart_handle_sysrq_char(&sport->port, ch, regs))
++ goto ignore_char;
++
++ error_return:
++ tty_insert_flip_char(tty, ch, flg);
++ ignore_char:
++ serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
++ IP3106_UART_LCR_RX_NEXT);
++ status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
++ ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
++ }
++ out:
++ tty_flip_buffer_push(tty);
++ return;
+
-+static struct fb_info_e1356 fb_info;
-+static struct e1356fb_fix boot_fix; // boot options
-+static struct e1356fb_par boot_par; // boot options
++ handle_error:
++ if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
++ sport->port.icount.parity++;
++ else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
++ sport->port.icount.frame++;
++ if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN))
++ sport->port.icount.overrun++;
+
-+static int e1356_remap_page_range(unsigned long from, phys_t phys_addr, unsigned long size, pgprot_t prot);
++ if (status & sport->port.ignore_status_mask) {
++ if (++ignored > 100)
++ goto out;
++ goto ignore_char;
++ }
+
++// status &= sport->port.read_status_mask;
+
-+/* -------------------------------------------------------------------------
-+ * Hardware-specific funcions
-+ * ------------------------------------------------------------------------- */
++ if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
++ flg = TTY_PARITY;
++ else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
++ flg = TTY_FRAME;
+
-+/*
-+ * The SED1356 has only a 16-bit wide data bus, so some embedded
-+ * implementations with 32-bit CPU's (Alchemy Pb1000) may not
-+ * correctly emulate a 32-bit write to the framebuffer by splitting
-+ * the write into two seperate 16-bit writes. So it is safest to
-+ * only do byte or half-word writes to the fb. This routine assumes
-+ * fbaddr is atleast aligned on a half-word boundary.
-+ */
-+static inline void
-+fbfill(u16* fbaddr, u8 val, int size)
-+{
-+ u16 valw = (u16)val | ((u16)val << 8);
-+ for ( ; size >= 2; size -= 2)
-+ writew(valw, fbaddr++);
-+ if (size)
-+ writeb(val, (u8*)fbaddr);
++ if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN)) {
++ /*
++ * overrun does *not* affect the character
++ * we read from the FIFO
++ */
++ tty_insert_flip_char(tty, ch, flg);
++ ch = 0;
++ flg = TTY_OVERRUN;
++ }
++#ifdef SUPPORT_SYSRQ
++ sport->port.sysrq = 0;
++#endif
++ goto error_return;
+}
+
-+static inline int
-+e1356_wait_bitclr(u8* reg, u8 bit, int timeout)
++static void ip3106_tx_chars(struct ip3106_port *sport)
+{
-+ while (readb(reg) & bit) {
-+ udelay(10);
-+ if (!--timeout)
++ struct circ_buf *xmit = &sport->port.info->xmit;
++
++ if (sport->port.x_char) {
++ serial_out(sport, IP3106_FIFO, sport->port.x_char);
++ sport->port.icount.tx++;
++ sport->port.x_char = 0;
++ return;
++ }
++
++ /*
++ * Check the modem control lines before
++ * transmitting anything.
++ */
++ ip3106_mctrl_check(sport);
++
++ if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
++ ip3106_stop_tx(&sport->port, 0);
++ return;
++ }
++
++ /*
++ * TX while bytes available
++ */
++ while (((serial_in(sport, IP3106_FIFO) &
++ IP3106_UART_FIFO_TXFIFO) >> 16) < 16) {
++ serial_out(sport, IP3106_FIFO, xmit->buf[xmit->tail]);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ sport->port.icount.tx++;
++ if (uart_circ_empty(xmit))
+ break;
+ }
-+ return timeout;
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&sport->port);
++
++ if (uart_circ_empty(xmit))
++ ip3106_stop_tx(&sport->port, 0);
+}
+
-+static inline int
-+e1356_wait_bitset(u8* reg, u8 bit, int timeout)
++static irqreturn_t ip3106_int(int irq, void *dev_id, struct pt_regs *regs)
+{
-+ while (!(readb(reg) & bit)) {
-+ udelay(10);
-+ if (!--timeout)
-+ break;
++ struct ip3106_port *sport = dev_id;
++ unsigned int status;
++
++ spin_lock(&sport->port.lock);
++ /* Get the interrupts */
++ status = serial_in(sport, IP3106_ISTAT) & serial_in(sport, IP3106_IEN);
++
++ /* RX Receiver Holding Register Overrun */
++ if (status & IP3106_UART_INT_RXOVRN) {
++ sport->port.icount.overrun++;
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RXOVRN);
+ }
-+ return timeout;
-+}
+
++ /* RX Frame Error */
++ if (status & IP3106_UART_INT_FRERR) {
++ sport->port.icount.frame++;
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_FRERR);
++ }
+
-+static struct fb_videomode panel_modedb[] = {
-+ {
-+ /* 320x240 @ 109 Hz, 33.3 kHz hsync */
-+ NULL, 109, 320, 240, KHZ2PICOS(MAX_PIXCLOCK/3),
-+ 16, 16, 32, 24, 48, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 640x480 @ 84 Hz, 48.1 kHz hsync */
-+ NULL, 84, 640, 480, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 96, 32, 32, 48, 64, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 800x600 @ 76 Hz, 46.3 kHz hsync */
-+ NULL, 76, 800, 600, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 32, 10, 1, 1, 22, 1,
-+ 0, FB_VMODE_NONINTERLACED
++ /* Break signal received */
++ if (status & IP3106_UART_INT_BREAK) {
++ sport->port.icount.brk++;
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_BREAK);
+ }
-+};
-+static struct fb_videomode crt_modedb[] = {
-+ {
-+ /* 320x240 @ 84 Hz, 31.25 kHz hsync */
-+ NULL, 84, 320, 240, KHZ2PICOS(MAX_PIXCLOCK/2),
-+ 128, 128, 60, 60, 64, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 320x240 @ 109 Hz, 33.3 kHz hsync */
-+ NULL, 109, 320, 240, KHZ2PICOS(MAX_PIXCLOCK/3),
-+ 16, 16, 32, 24, 48, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 512x384 @ 77 Hz, 31.25 kHz hsync */
-+ NULL, 77, 512, 384, KHZ2PICOS(MAX_PIXCLOCK/2),
-+ 48, 16, 16, 1, 64, 3,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 640x400 @ 88 Hz, 43.1 kHz hsync */
-+ NULL, 88, 640, 400, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 128, 96, 32, 48, 64, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 640x480 @ 84 Hz, 48.1 kHz hsync */
-+ NULL, 84, 640, 480, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 96, 32, 32, 48, 64, 8,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 768x576 @ 62 Hz, 38.5 kHz hsync */
-+ NULL, 62, 768, 576, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 144, 16, 28, 6, 112, 4,
-+ 0, FB_VMODE_NONINTERLACED
-+ }, {
-+ /* 800x600 @ 60 Hz, 37.9 kHz hsync */
-+ NULL, 60, 800, 600, KHZ2PICOS(MAX_PIXCLOCK/1),
-+ 88, 40, 23, 1, 128, 4,
-+ FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
-+ FB_VMODE_NONINTERLACED
++
++ /* RX Parity Error */
++ if (status & IP3106_UART_INT_PARITY) {
++ sport->port.icount.parity++;
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_PARITY);
+ }
-+};
+
-+static struct fb_videomode ntsc_modedb[] = {
-+ {
-+ /* 640x480 @ 62 Hz, requires flicker filter */
-+ //NULL, 62, 640, 480, 34921, 213, 57, 20, 2, 0, 0,
-+ NULL, 62, 640, 480, KHZ2PICOS(2*NTSC_PIXCLOCK),
-+ 200, 70, 15, 7, 0, 0,
-+ FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
++ /* Byte received */
++ if (status & IP3106_UART_INT_RX) {
++ ip3106_rx_chars(sport, regs);
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RX);
+ }
-+};
-+static struct fb_videomode pal_modedb[] = {
-+ {
-+ /* 640x480 @ 56 Hz, requires flicker filter */
-+ NULL, 56, 640, 480, KHZ2PICOS(2*PAL_PIXCLOCK),
-+ 350, 145, 49, 23, 0, 0,
-+ FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
++
++ /* TX holding register empty - transmit a byte */
++ if (status & IP3106_UART_INT_TX) {
++ ip3106_tx_chars(sport);
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX);
+ }
-+};
+
++ /* TX shift register and holding register empty */
++ if (status & IP3106_UART_INT_EMPTY) {
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_EMPTY);
++ }
++
++ /* Receiver time out */
++ if (status & IP3106_UART_INT_RCVTO) {
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RCVTO);
++ }
++ spin_unlock(&sport->port.lock);
++ return IRQ_HANDLED;
++}
++
++/*
++ * Return TIOCSER_TEMT when transmitter is not busy.
++ */
++static unsigned int ip3106_tx_empty(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
+
-+static inline void
-+fb_videomode_to_var(struct fb_videomode* mode,
-+ struct fb_var_screeninfo*var)
-+{
-+ var->xres = mode->xres;
-+ var->yres = mode->yres;
-+ var->pixclock = mode->pixclock;
-+ var->left_margin = mode->left_margin;
-+ var->right_margin = mode->right_margin;
-+ var->upper_margin = mode->upper_margin;
-+ var->lower_margin = mode->lower_margin;
-+ var->hsync_len = mode->hsync_len;
-+ var->vsync_len = mode->vsync_len;
-+ var->sync = mode->sync;
-+ var->vmode = mode->vmode;
++ return serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
+}
+
++static unsigned int ip3106_get_mctrl(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ unsigned int mctrl = TIOCM_DSR;
++ unsigned int msr;
+
-+static int
-+e1356fb_get_mode(const struct fb_info_e1356 *info,
-+ int xres,
-+ int yres,
-+ struct fb_videomode ** modedb,
-+ struct fb_videomode ** mode)
-+{
-+ struct fb_videomode * ret;
-+ int i, dbsize;
-+
-+ if (IS_PANEL(info->fix.disp_type)) {
-+ ret = panel_modedb;
-+ dbsize = sizeof(panel_modedb)/sizeof(struct fb_videomode);
-+ } else if (info->fix.disp_type == DISP_TYPE_CRT) {
-+ ret = crt_modedb;
-+ dbsize = sizeof(crt_modedb)/sizeof(struct fb_videomode);
-+ } else if (info->fix.disp_type == DISP_TYPE_NTSC) {
-+ ret = ntsc_modedb;
-+ dbsize = sizeof(ntsc_modedb)/sizeof(struct fb_videomode);
-+ } else {
-+ ret = pal_modedb;
-+ dbsize = sizeof(pal_modedb)/sizeof(struct fb_videomode);
++ /* REVISIT */
++
++ msr = serial_in(sport, IP3106_MCR);
++
++ mctrl |= msr & IP3106_UART_MCR_CTS ? TIOCM_CTS : 0;
++ mctrl |= msr & IP3106_UART_MCR_DCD ? TIOCM_CAR : 0;
++
++ return mctrl;
++}
++
++static void ip3106_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++#if 0 /* FIXME */
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ unsigned int msr;
++#endif
++}
++
++/*
++ * Interrupts always disabled.
++ */
++static void ip3106_break_ctl(struct uart_port *port, int break_state)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ unsigned long flags;
++ unsigned int lcr;
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++ lcr = serial_in(sport, IP3106_LCR);
++ if (break_state == -1)
++ lcr |= IP3106_UART_LCR_TXBREAK;
++ else
++ lcr &= ~IP3106_UART_LCR_TXBREAK;
++ serial_out(sport, IP3106_LCR, lcr);
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++}
++
++static int ip3106_startup(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ int retval;
++
++ /*
++ * Allocate the IRQ
++ */
++ retval = request_irq(sport->port.irq, ip3106_int, 0,
++ "ip3106-uart", sport);
++ if (retval)
++ return retval;
++
++ /*
++ * Finally, clear and enable interrupts
++ */
++
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
++ IP3106_UART_INT_ALLTX);
++
++ serial_out(sport, IP3106_IEN, serial_in(sport, IP3106_IEN) |
++ IP3106_UART_INT_ALLRX |
++ IP3106_UART_INT_ALLTX);
++
++ /*
++ * Enable modem status interrupts
++ */
++ spin_lock_irq(&sport->port.lock);
++ ip3106_enable_ms(&sport->port);
++ spin_unlock_irq(&sport->port.lock);
++
++ return 0;
++}
++
++static void ip3106_shutdown(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++
++ /*
++ * Stop our timer.
++ */
++ del_timer_sync(&sport->timer);
++
++ /*
++ * Disable all interrupts, port and break condition.
++ */
++ serial_out(sport, IP3106_IEN, 0);
++
++ /*
++ * Reset the Tx and Rx FIFOS
++ */
++ serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
++ IP3106_UART_LCR_TX_RST |
++ IP3106_UART_LCR_RX_RST);
++
++ /*
++ * Clear all interrupts
++ */
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
++ IP3106_UART_INT_ALLTX);
++
++ /*
++ * Free the interrupt
++ */
++ free_irq(sport->port.irq, sport);
++}
++
++static void
++ip3106_set_termios(struct uart_port *port, struct termios *termios,
++ struct termios *old)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ unsigned long flags;
++ unsigned int lcr_fcr, old_ien, baud, quot;
++ unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
++
++ /*
++ * We only support CS7 and CS8.
++ */
++ while ((termios->c_cflag & CSIZE) != CS7 &&
++ (termios->c_cflag & CSIZE) != CS8) {
++ termios->c_cflag &= ~CSIZE;
++ termios->c_cflag |= old_csize;
++ old_csize = CS8;
+ }
-+
-+ if (modedb)
-+ *modedb = ret;
-+ for (i=0; i<dbsize; i++) {
-+ if (xres == ret[i].xres && yres == ret[i].yres) {
-+ *mode = &ret[i];
-+ break;
-+ }
++
++ if ((termios->c_cflag & CSIZE) == CS8)
++ lcr_fcr = IP3106_UART_LCR_8BIT;
++ else
++ lcr_fcr = 0;
++
++ if (termios->c_cflag & CSTOPB)
++ lcr_fcr |= IP3106_UART_LCR_2STOPB;
++ if (termios->c_cflag & PARENB) {
++ lcr_fcr |= IP3106_UART_LCR_PAREN;
++ if (!(termios->c_cflag & PARODD))
++ lcr_fcr |= IP3106_UART_LCR_PAREVN;
+ }
-+ if (i == dbsize)
-+ return -EINVAL;
-+ return dbsize;
++
++ /*
++ * Ask the core to calculate the divisor for us.
++ */
++ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
++ quot = uart_get_divisor(port, baud);
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++
++#if 0 /* REVISIT */
++ sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
++ sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
++ if (termios->c_iflag & INPCK)
++ sport->port.read_status_mask |=
++ UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
++ if (termios->c_iflag & (BRKINT | PARMRK))
++ sport->port.read_status_mask |=
++ UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
++
++ /*
++ * Characters to ignore
++ */
++ sport->port.ignore_status_mask = 0;
++ if (termios->c_iflag & IGNPAR)
++ sport->port.ignore_status_mask |=
++ UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
++ if (termios->c_iflag & IGNBRK) {
++ sport->port.ignore_status_mask |=
++ UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
++ /*
++ * If we're ignoring parity and break indicators,
++ * ignore overruns too (for real raw support).
++ */
++ if (termios->c_iflag & IGNPAR)
++ sport->port.ignore_status_mask |=
++ UTSR1_TO_SM(UTSR1_ROR);
++ }
++#endif
++
++ del_timer_sync(&sport->timer);
++
++ /*
++ * Update the per-port timeout.
++ */
++ uart_update_timeout(port, termios->c_cflag, baud);
++
++ /*
++ * disable interrupts and drain transmitter
++ */
++ old_ien = serial_in(sport, IP3106_IEN);
++ serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
++ IP3106_UART_INT_ALLRX));
++
++ while (serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA)
++ barrier();
++
++ /* then, disable everything */
++ serial_out(sport, IP3106_IEN, 0);
++
++ /* Reset the Rx and Tx FIFOs too */
++ lcr_fcr |= IP3106_UART_LCR_TX_RST;
++ lcr_fcr |= IP3106_UART_LCR_RX_RST;
++
++ /* set the parity, stop bits and data size */
++ serial_out(sport, IP3106_LCR, lcr_fcr);
++
++ /* set the baud rate */
++ quot -= 1;
++ serial_out(sport, IP3106_BAUD, quot);
++
++ serial_out(sport, IP3106_ICLR, -1);
++
++ serial_out(sport, IP3106_IEN, old_ien);
++
++ if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
++ ip3106_enable_ms(&sport->port);
++
++ spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
++static const char *ip3106_type(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
+
++ return sport->port.type == PORT_IP3106 ? "IP3106" : NULL;
++}
+
-+#ifdef E1356FB_VERBOSE_DEBUG
-+static void
-+dump_par(const struct e1356fb_par* par)
++/*
++ * Release the memory region(s) being used by 'port'.
++ */
++static void ip3106_release_port(struct uart_port *port)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++
++ release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
++}
++
++/*
++ * Request the memory region(s) being used by 'port'.
++ */
++static int ip3106_request_port(struct uart_port *port)
+{
-+ DPRINTK("width: %d\n", par->width);
-+ DPRINTK("height: %d\n", par->height);
-+ DPRINTK("width_virt: %d\n", par->width_virt);
-+ DPRINTK("height_virt: %d\n", par->height_virt);
-+ DPRINTK("bpp: %d\n", par->bpp);
-+ DPRINTK("pixclock: %d\n", par->ipclk.pixclk);
-+ DPRINTK("horiz_ndp: %d\n", par->horiz_ndp);
-+ DPRINTK("vert_ndp: %d\n", par->vert_ndp);
-+ DPRINTK("hsync_pol: %d\n", par->hsync_pol);
-+ DPRINTK("hsync_start: %d\n", par->hsync_start);
-+ DPRINTK("hsync_width: %d\n", par->hsync_width);
-+ DPRINTK("vsync_pol: %d\n", par->vsync_pol);
-+ DPRINTK("vsync_start: %d\n", par->vsync_start);
-+ DPRINTK("vsync_width: %d\n", par->vsync_width);
-+ DPRINTK("cmap_len: %d\n", par->cmap_len);
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++
++ return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
++ "ip3106-uart") != NULL ? 0 : -EBUSY;
+}
+
-+static void
-+dump_display_regs(reg_dispcfg_t* dispcfg, reg_dispmode_t* dispmode)
++/*
++ * Configure/autoconfigure the port.
++ */
++static void ip3106_config_port(struct uart_port *port, int flags)
+{
-+ DPRINTK("hdw: 0x%02x\n", readb(&dispcfg->hdw));
-+ DPRINTK("hndp: 0x%02x\n", readb(&dispcfg->hndp));
-+ DPRINTK("hsync_start: 0x%02x\n", readb(&dispcfg->hsync_start));
-+ DPRINTK("hsync_pulse: 0x%02x\n", readb(&dispcfg->hsync_pulse));
-+ DPRINTK("vdh0: 0x%02x\n", readb(&dispcfg->vdh0));
-+ DPRINTK("vdh1: 0x%02x\n", readb(&dispcfg->vdh1));
-+ DPRINTK("vndp: 0x%02x\n", readb(&dispcfg->vndp));
-+ DPRINTK("vsync_start: 0x%02x\n", readb(&dispcfg->vsync_start));
-+ DPRINTK("vsync_pulse: 0x%02x\n", readb(&dispcfg->vsync_pulse));
-+ DPRINTK("tv_output_ctrl: 0x%02x\n\n", readb(&dispcfg->tv_output_ctrl));
-+
-+ DPRINTK("disp_mode: 0x%02x\n", readb(&dispmode->disp_mode));
-+ DPRINTK("lcd_misc: 0x%02x\n", readb(&dispmode->lcd_misc));
-+ DPRINTK("start_addr0: 0x%02x\n", readb(&dispmode->start_addr0));
-+ DPRINTK("start_addr1: 0x%02x\n", readb(&dispmode->start_addr1));
-+ DPRINTK("start_addr2: 0x%02x\n", readb(&dispmode->start_addr2));
-+ DPRINTK("mem_addr_offset0: 0x%02x\n", readb(&dispmode->mem_addr_offset0));
-+ DPRINTK("mem_addr_offset1: 0x%02x\n", readb(&dispmode->mem_addr_offset1));
-+ DPRINTK("pixel_panning: 0x%02x\n", readb(&dispmode->pixel_panning));
-+ DPRINTK("fifo_high_thresh: 0x%02x\n", readb(&dispmode->fifo_high_thresh));
-+ DPRINTK("fifo_low_thresh: 0x%02x\n", readb(&dispmode->fifo_low_thresh));
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++
++ if (flags & UART_CONFIG_TYPE &&
++ ip3106_request_port(&sport->port) == 0)
++ sport->port.type = PORT_IP3106;
+}
+
-+static void
-+dump_fb(u8* base, int len)
++/*
++ * Verify the new serial_struct (for TIOCSSERIAL).
++ * The only change we allow are to the flags and type, and
++ * even then only between PORT_IP3106 and PORT_UNKNOWN
++ */
++static int
++ip3106_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++ struct ip3106_port *sport = (struct ip3106_port *)port;
++ int ret = 0;
++
++ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IP3106)
++ ret = -EINVAL;
++ if (sport->port.irq != ser->irq)
++ ret = -EINVAL;
++ if (ser->io_type != SERIAL_IO_MEM)
++ ret = -EINVAL;
++ if (sport->port.uartclk / 16 != ser->baud_base)
++ ret = -EINVAL;
++ if ((void *)sport->port.mapbase != ser->iomem_base)
++ ret = -EINVAL;
++ if (sport->port.iobase != ser->port)
++ ret = -EINVAL;
++ if (ser->hub6 != 0)
++ ret = -EINVAL;
++ return ret;
++}
++
++struct uart_ops ip3106_pops = {
++ .tx_empty = ip3106_tx_empty,
++ .set_mctrl = ip3106_set_mctrl,
++ .get_mctrl = ip3106_get_mctrl,
++ .stop_tx = ip3106_stop_tx,
++ .start_tx = ip3106_start_tx,
++ .stop_rx = ip3106_stop_rx,
++ .enable_ms = ip3106_enable_ms,
++ .break_ctl = ip3106_break_ctl,
++ .startup = ip3106_startup,
++ .shutdown = ip3106_shutdown,
++ .set_termios = ip3106_set_termios,
++ .type = ip3106_type,
++ .release_port = ip3106_release_port,
++ .request_port = ip3106_request_port,
++ .config_port = ip3106_config_port,
++ .verify_port = ip3106_verify_port,
++};
++
++
++/*
++ * Setup the IP3106 serial ports.
++ *
++ * Note also that we support "console=ttySx" where "x" is either 0 or 1.
++ */
++static void __init ip3106_init_ports(void)
+{
++ static int first = 1;
+ int i;
-+ DPRINTK("FB memory dump, start 0x%p, len %d", base, len);
-+ for (i=0; i<len; i++) {
-+ if (!(i%16))
-+ printk("\n%p: %02x ", &base[i], readb(&base[i]));
-+ else
-+ printk("%02x ", readb(&base[i]));
++
++ if (!first)
++ return;
++ first = 0;
++
++ for (i = 0; i < NR_PORTS; i++) {
++ init_timer(&ip3106_ports[i].timer);
++ ip3106_ports[i].timer.function = ip3106_timeout;
++ ip3106_ports[i].timer.data = (unsigned long)&ip3106_ports[i];
+ }
-+ printk("\n");
+}
+
-+#endif // E1356FB_VERBOSE_DEBUG
++#ifdef CONFIG_SERIAL_IP3106_CONSOLE
++
++/*
++ * Interrupts are disabled on entering
++ */
++static void
++ip3106_console_write(struct console *co, const char *s, unsigned int count)
++{
++ struct ip3106_port *sport = &ip3106_ports[co->index];
++ unsigned int old_ien, status, i;
++
++ /*
++ * First, save IEN and then disable interrupts
++ */
++ old_ien = serial_in(sport, IP3106_IEN);
++ serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
++ IP3106_UART_INT_ALLRX));
++
++ /*
++ * Now, do each character
++ */
++ for (i = 0; i < count; i++) {
++ do {
++ /* Wait for UART_TX register to empty */
++ status = serial_in(sport, IP3106_FIFO);
++ } while (status & IP3106_UART_FIFO_TXFIFO);
++ serial_out(sport, IP3106_FIFO, s[i]);
++ if (s[i] == '\n') {
++ do {
++ status = serial_in(sport, IP3106_FIFO);
++ } while (status & IP3106_UART_FIFO_TXFIFO);
++ serial_out(sport, IP3106_FIFO, '\r');
++ }
++ }
++
++ /*
++ * Finally, wait for transmitter to become empty
++ * and restore IEN
++ */
++ do {
++ /* Wait for UART_TX register to empty */
++ status = serial_in(sport, IP3106_FIFO);
++ } while (status & IP3106_UART_FIFO_TXFIFO);
++
++ /* Clear TX and EMPTY interrupt */
++ serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX |
++ IP3106_UART_INT_EMPTY);
++
++ serial_out(sport, IP3106_IEN, old_ien);
++}
+
++static int __init
++ip3106_console_setup(struct console *co, char *options)
++{
++ struct ip3106_port *sport;
++ int baud = 38400;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
+
++ /*
++ * Check whether an invalid uart number has been specified, and
++ * if so, search for the first available port that does have
++ * console support.
++ */
++ if (co->index == -1 || co->index >= NR_PORTS)
++ co->index = 0;
++ sport = &ip3106_ports[co->index];
++
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
++
++ return uart_set_options(&sport->port, co, baud, parity, bits, flow);
++}
++
++extern struct uart_driver ip3106_reg;
++static struct console ip3106_console = {
++ .name = "ttyS",
++ .write = ip3106_console_write,
++ .device = uart_console_device,
++ .setup = ip3106_console_setup,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .data = &ip3106_reg,
++};
+
-+// Input: ipclk->clksrc, ipclk->pixclk_d
-+// Output: ipclk->pixclk, ipclk->error, and ipclk->divisor
-+static int
-+get_nearest_pixclk_div(pixclock_info_t* ipclk, int x2)
++static int __init ip3106_rs_console_init(void)
+{
-+ int pixclk_d = ipclk->pixclk_d;
-+ int clksrc = ipclk->clksrc;
-+
-+ if (x2) clksrc *= 2;
-+
-+ if (clksrc < (3*pixclk_d+1)/2)
-+ ipclk->divisor = 1;
-+ else if (clksrc < (5*pixclk_d+1)/2)
-+ ipclk->divisor = 2;
-+ else if (clksrc < (7*pixclk_d+1)/2)
-+ ipclk->divisor = 3;
-+ else if (clksrc < (9*pixclk_d+1)/2)
-+ ipclk->divisor = 4;
-+ else
-+ return -ENXIO;
-+
-+ ipclk->pixclk = clksrc / ipclk->divisor;
-+ ipclk->error = (100*(pixclk_d - ipclk->pixclk)) / pixclk_d;
++ ip3106_init_ports();
++ register_console(&ip3106_console);
+ return 0;
+}
++console_initcall(ip3106_rs_console_init);
+
-+static int
-+e1356_calc_pixclock(const struct fb_info_e1356 *info,
-+ pixclock_info_t* ipclk)
-+{
-+ int src_sel=-1, flicker_mult=0;
-+ pixclock_info_t test, ret;
-+
-+ if (ipclk->pixclk > info->max_pixclock)
-+ return -ENXIO;
-+
-+ test.pixclk_d = ipclk->pixclk_d;
-+ ret.error = 100;
-+
-+ if (IS_TV(info->fix.disp_type) &&
-+ (info->fix.tv_filt & TV_FILT_FLICKER))
-+ flicker_mult = 0x80;
-+
-+ test.clksrc = info->fix.busclk;
-+ if (get_nearest_pixclk_div(&test, flicker_mult != 0) == 0 &&
-+ abs(test.error) < abs(ret.error)) {
-+ ret = test;
-+ src_sel = 0x01;
-+ }
++#define IP3106_CONSOLE &ip3106_console
++#else
++#define IP3106_CONSOLE NULL
++#endif
+
-+ test.clksrc = info->fix.mclk;
-+ if (get_nearest_pixclk_div(&test, flicker_mult != 0) == 0 &&
-+ abs(test.error) < abs(ret.error)) {
-+ ret = test;
-+ src_sel = 0x03;
-+ }
++static struct uart_driver ip3106_reg = {
++ .owner = THIS_MODULE,
++ .driver_name = "ttyS",
++ .dev_name = "ttyS",
++ .devfs_name = "tts/",
++ .major = SERIAL_IP3106_MAJOR,
++ .minor = MINOR_START,
++ .nr = NR_PORTS,
++ .cons = IP3106_CONSOLE,
++};
+
-+ test.clksrc = info->fix.clki;
-+ if (get_nearest_pixclk_div(&test, flicker_mult != 0) == 0 &&
-+ abs(test.error) < abs(ret.error)) {
-+ ret = test;
-+ src_sel = 0x00;
-+ }
++static int ip3106_serial_suspend(struct device *_dev, u32 state, u32 level)
++{
++ struct ip3106_port *sport = dev_get_drvdata(_dev);
+
-+ test.clksrc = info->fix.clki2;
-+ if (get_nearest_pixclk_div(&test, flicker_mult != 0) == 0 &&
-+ abs(test.error) < abs(ret.error)) {
-+ ret = test;
-+ src_sel = 0x02;
-+ }
++ if (sport && level == SUSPEND_DISABLE)
++ uart_suspend_port(&ip3106_reg, &sport->port);
+
-+ if (ret.error > MAX_PCLK_ERROR_LOWER ||
-+ ret.error < MAX_PCLK_ERROR_HIGHER)
-+ return -ENXIO;
-+
-+ ret.pixclk_bits = flicker_mult | ((ret.divisor-1)<<4) | src_sel;
-+ *ipclk = ret;
+ return 0;
+}
+
-+static inline int
-+e1356_engine_wait_complete(reg_bitblt_t* bltreg)
-+{
-+ return e1356_wait_bitclr(&bltreg->ctrl0, 0x80, 5000);
-+}
-+static inline int
-+e1356_engine_wait_busy(reg_bitblt_t* bltreg)
++static int ip3106_serial_resume(struct device *_dev, u32 level)
+{
-+ return e1356_wait_bitset(&bltreg->ctrl0, 0x80, 5000);
-+}
++ struct ip3106_port *sport = dev_get_drvdata(_dev);
+
-+static void
-+e1356fb_engine_init(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info)
-+{
-+ reg_bitblt_t* bltreg = info->reg.bitblt;
-+
-+ e1356_engine_wait_complete(bltreg);
++ if (sport && level == RESUME_ENABLE)
++ uart_resume_port(&ip3106_reg, &sport->port);
+
-+ writeb(0, &bltreg->ctrl0);
-+ writeb(0, &bltreg->ctrl1);
-+ writeb(0, &bltreg->rop_code);
-+ writeb(0, &bltreg->operation);
-+ writeb(0, &bltreg->src_start_addr0);
-+ writeb(0, &bltreg->src_start_addr1);
-+ writeb(0, &bltreg->src_start_addr2);
-+ writeb(0, &bltreg->dest_start_addr0);
-+ writeb(0, &bltreg->dest_start_addr1);
-+ writeb(0, &bltreg->dest_start_addr2);
-+ writew(0, &bltreg->mem_addr_offset0);
-+ writew(0, &bltreg->width0);
-+ writew(0, &bltreg->height0);
-+ writew(0, &bltreg->bg_color0);
-+ writew(0, &bltreg->fg_color0);
++ return 0;
+}
+
++static int ip3106_serial_probe(struct device *_dev)
++{
++ struct platform_device *dev = to_platform_device(_dev);
++ struct resource *res = dev->resource;
++ int i;
+
-+static void doBlt_Write(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info,
-+ blt_info_t* blt)
-+{
-+ reg_bitblt_t* bltreg = info->reg.bitblt;
-+ int nWords, nTotalWords;
-+ u32 srcphase, dstAddr;
-+ u16* w16;
-+ u32 stride = par->width_virt * par->Bpp;
++ for (i = 0; i < dev->num_resources; i++, res++) {
++ if (!(res->flags & IORESOURCE_MEM))
++ continue;
+
-+ dstAddr = blt->dst_x * par->Bpp + blt->dst_y * stride;
-+ srcphase = (u32)blt->src & 1;
-+
-+ if (blt->attribute & BLT_ATTR_TRANSPARENT)
-+ writew(blt->bg_color, &bltreg->bg_color0);
-+ else
-+ writeb(blt->rop, &bltreg->rop_code);
-+
-+ writeb(blt->operation, &bltreg->operation);
-+ writeb((u8)srcphase, &bltreg->src_start_addr0);
-+ writew(stride/2, &bltreg->mem_addr_offset0);
++ for (i = 0; i < NR_PORTS; i++) {
++ if (ip3106_ports[i].port.mapbase != res->start)
++ continue;
+
-+ writeb(dstAddr, &bltreg->dest_start_addr0);
-+ writeb(dstAddr>>8, &bltreg->dest_start_addr1);
-+ writeb(dstAddr>>16, &bltreg->dest_start_addr2);
++ ip3106_ports[i].port.dev = _dev;
++ uart_add_one_port(&ip3106_reg, &ip3106_ports[i].port);
++ dev_set_drvdata(_dev, &ip3106_ports[i]);
++ break;
++ }
++ }
+
-+ writew(blt->dst_width-1, &bltreg->width0);
-+ writew(blt->dst_height-1, &bltreg->height0);
++ return 0;
++}
+
-+ // program color format operation
-+ writeb(par->bpp == 8 ? 0x00 : 0x01, &bltreg->ctrl1);
++static int ip3106_serial_remove(struct device *_dev)
++{
++ struct ip3106_port *sport = dev_get_drvdata(_dev);
+
-+ // start it up
-+ writeb(0x80, &bltreg->ctrl0);
++ dev_set_drvdata(_dev, NULL);
+
-+ // wait for it to actually start
-+ e1356_engine_wait_busy(bltreg);
++ if (sport)
++ uart_remove_one_port(&ip3106_reg, &sport->port);
+
-+ // calculate the number of 16 bit words per one blt line
++ return 0;
++}
+
-+ nWords = srcphase + ((blt->dst_width - srcphase)*par->Bpp + 1) / 2;
-+ nTotalWords = nWords*blt->dst_height;
-+ w16 = (u16*)((u32)blt->src & 0xfffffffe); // Word aligned
++static struct device_driver ip3106_serial_driver = {
++ .name = "ip3106-uart",
++ .bus = &platform_bus_type,
++ .probe = ip3106_serial_probe,
++ .remove = ip3106_serial_remove,
++ .suspend = ip3106_serial_suspend,
++ .resume = ip3106_serial_resume,
++};
+
-+ while (nTotalWords > 0) {
-+ int j, nFIFO;
-+ u8 ctrl0;
++static int __init ip3106_serial_init(void)
++{
++ int ret;
+
-+ // read the FIFO status
-+ ctrl0 = readb(&bltreg->ctrl0);
++ printk(KERN_INFO "Serial: IP3106 driver $Revision: 1.2 $\n");
+
-+ if ((ctrl0 & 0x30) == 0x20)
-+ // FIFO is at least half full, but not full
-+ nFIFO = 1;
-+ else if ((ctrl0 & 0x40) == 0)
-+ // FIFO is empty
-+ nFIFO = 16;
-+ else
-+ // FIFO is full
-+ continue;
++ ip3106_init_ports();
+
-+ for (j = 0; j < nFIFO && nTotalWords > 0; j++,nTotalWords--)
-+ writew(*w16++, info->reg.bitblt_data);
++ ret = uart_register_driver(&ip3106_reg);
++ if (ret == 0) {
++ ret = driver_register(&ip3106_serial_driver);
++ if (ret)
++ uart_unregister_driver(&ip3106_reg);
+ }
-+
-+ e1356_engine_wait_complete(bltreg);
++ return ret;
+}
+
++static void __exit ip3106_serial_exit(void)
++{
++ driver_unregister(&ip3106_serial_driver);
++ uart_unregister_driver(&ip3106_reg);
++}
+
-+static void
-+doBlt_SolidFill(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info,
-+ blt_info_t* blt)
-+{
-+ reg_bitblt_t* bltreg = info->reg.bitblt;
-+ u32 width = blt->dst_width, height = blt->dst_height;
-+ u32 stride = par->width_virt * par->Bpp;
-+ u32 dest_addr = (blt->dst_y * stride) + (blt->dst_x * par->Bpp);
++module_init(ip3106_serial_init);
++module_exit(ip3106_serial_exit);
+
-+ if (width == 0 || height == 0)
-+ return;
++MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
++MODULE_DESCRIPTION("IP3106 generic serial port driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_IP3106_MAJOR);
+diff -urN --ignore-space-change kernel.org/drivers/usb/gadget/net2280.c linux-mips/drivers/usb/gadget/net2280.c
+--- kernel.org/drivers/usb/gadget/net2280.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/usb/gadget/net2280.c 2006-01-10 11:21:48.000000000 +0000
+@@ -448,7 +448,8 @@
+ #elif defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ #define USE_KMALLOC
+
+-#elif defined(CONFIG_MIPS) && !defined(CONFIG_DMA_NONCOHERENT)
++#elif defined(CONFIG_MIPS) && \
++ (defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27))
+ #define USE_KMALLOC
+
+ /* FIXME there are other cases, including an x86-64 one ... */
+diff -urN --ignore-space-change kernel.org/drivers/usb/host/ohci-au1xxx.c linux-mips/drivers/usb/host/ohci-au1xxx.c
+--- kernel.org/drivers/usb/host/ohci-au1xxx.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/usb/host/ohci-au1xxx.c 2006-01-10 11:21:48.000000000 +0000
+@@ -91,12 +91,12 @@
+ int retval;
+ struct usb_hcd *hcd;
+
+- if(dev->resource[1].flags != IORESOURCE_IRQ) {
++ if (dev->resource[1].flags != IORESOURCE_IRQ) {
+ pr_debug ("resource[1] is not IORESOURCE_IRQ");
+- return -ENOMEM;
++ retval = -ENOMEM;
+ }
+
+- hcd = usb_create_hcd(driver, &dev->dev, "au1xxx");
++ hcd = usb_create_hcd(driver, &dev->dev, "Au1xxx");
+ if (!hcd)
+ return -ENOMEM;
+ hcd->rsrc_start = dev->resource[0].start;
+diff -urN --ignore-space-change kernel.org/drivers/usb/host/ohci-hcd.c linux-mips/drivers/usb/host/ohci-hcd.c
+--- kernel.org/drivers/usb/host/ohci-hcd.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/usb/host/ohci-hcd.c 2006-01-10 11:21:48.000000000 +0000
+@@ -913,6 +913,10 @@
+ #include "ohci-au1xxx.c"
+ #endif
+
++#ifdef CONFIG_PNX8550
++#include "ohci-pnx8550.c"
++#endif
+
-+ // program dest address
-+ writeb(dest_addr & 0x00ff, &bltreg->dest_start_addr0);
-+ writeb((dest_addr>>8) & 0x00ff, &bltreg->dest_start_addr1);
-+ writeb((dest_addr>>16) & 0x00ff, &bltreg->dest_start_addr2);
-+
-+ // program width and height of solid-fill blit
-+ writew(width-1, &bltreg->width0);
-+ writew(height-1, &bltreg->height0);
-+
-+ // program color of fill
-+ writew(blt->fg_color, &bltreg->fg_color0);
-+ // select solid-fill BLIT
-+ writeb(BLT_SOLID_FILL, &bltreg->operation);
-+ // program color format operation
-+ writeb(par->bpp == 8 ? 0x00 : 0x01, &bltreg->ctrl1);
-+ // program BLIT memory offset
-+ writew(stride/2, &bltreg->mem_addr_offset0);
+ #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
+ #include "ohci-ppc-soc.c"
+ #endif
+diff -urN --ignore-space-change kernel.org/drivers/usb/host/ohci-pnx8550.c linux-mips/drivers/usb/host/ohci-pnx8550.c
+--- kernel.org/drivers/usb/host/ohci-pnx8550.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/usb/host/ohci-pnx8550.c 2006-01-10 11:21:48.000000000 +0000
+@@ -0,0 +1,277 @@
++/*
++ * OHCI HCD (Host Controller Driver) for USB.
++ *
++ * (C) Copyright 1999 Roman Weissgaerber <weissg at vienna.at>
++ * (C) Copyright 2000-2002 David Brownell <dbrownell at users.sourceforge.net>
++ * (C) Copyright 2002 Hewlett-Packard Company
++ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
++ *
++ * Bus Glue for PNX8550
++ *
++ * Written by Christopher Hoover <ch at hpl.hp.com>
++ * Based on fragments of previous driver by Russell King et al.
++ *
++ * Modified for LH7A404 from ohci-sa1111.c
++ * by Durgesh Pattamatta <pattamattad at sharpsec.com>
++ *
++ * Modified for pxa27x from ohci-lh7a404.c
++ * by Nick Bane <nick at cecomputing.co.uk> 26-8-2004
++ *
++ * Modified for PNX8550 from ohci-pxa27x.c
++ * by Embedded Alley Solutions, Inc.
++ *
++ * This file is licenced under the GPL.
++ */
+
-+ // start it up (self completes)
-+ writeb(0x80, &bltreg->ctrl0);
++#include <linux/device.h>
++#include <asm/mach-pnx8550/usb.h>
++#include <asm/mach-pnx8550/int.h>
++#include <asm/mach-pnx8550/pci.h>
+
-+ e1356_engine_wait_complete(bltreg);
-+}
++#ifndef CONFIG_PNX8550
++#error "This file is PNX8550 bus glue. CONFIG_PNX8550 must be defined."
++#endif
+
++extern int usb_disabled(void);
+
-+static void
-+doBlt_Move(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info,
-+ blt_info_t* blt)
-+{
-+ reg_bitblt_t* bltreg = info->reg.bitblt;
-+ int neg_dir=0;
-+ u32 dest_addr, src_addr;
-+ u32 bpp = par->bpp;
-+ u32 stride = par->width_virt * par->Bpp; // virt line length in bytes
-+ u32 srcx = blt->src_x, srcy = blt->src_y;
-+ u32 dstx = blt->dst_x, dsty = blt->dst_y;
-+ u32 width = blt->dst_width, height = blt->dst_height;
-+
-+ if (width == 0 || height == 0)
-+ return;
-+
-+ src_addr = srcx*par->Bpp + srcy*stride;
-+ dest_addr = dstx*par->Bpp + dsty*stride;
++/*-------------------------------------------------------------------------*/
+
++static void pnx8550_start_hc(struct platform_device *dev)
++{
+ /*
-+ * See if regions overlap and dest region is beyond source region.
-+ * If so, we need to do a move BLT in negative direction. Only applies
-+ * if the BLT is not transparent.
++ * Set register CLK48CTL to enable and 48MHz
+ */
-+ if (!(blt->attribute & BLT_ATTR_TRANSPARENT)) {
-+ if ((srcx + width > dstx) && (srcx < dstx + width) &&
-+ (srcy + height > dsty) && (srcy < dsty + height) &&
-+ (dest_addr > src_addr)) {
-+ neg_dir = 1;
-+ // negative direction : get the coords of lower right corner
-+ src_addr += stride * (height-1) + par->Bpp * (width-1);
-+ dest_addr += stride * (height-1) + par->Bpp * (width-1);
-+ }
-+ }
-+
-+ // program BLIT memory offset
-+ writew(stride/2, &bltreg->mem_addr_offset0);
-+
-+ // program src and dest addresses
-+ writeb(src_addr & 0x00ff, &bltreg->src_start_addr0);
-+ writeb((src_addr>>8) & 0x00ff, &bltreg->src_start_addr1);
-+ writeb((src_addr>>16) & 0x00ff, &bltreg->src_start_addr2);
-+ writeb(dest_addr & 0x00ff, &bltreg->dest_start_addr0);
-+ writeb((dest_addr>>8) & 0x00ff, &bltreg->dest_start_addr1);
-+ writeb((dest_addr>>16) & 0x00ff, &bltreg->dest_start_addr2);
-+
-+ // program width and height of blit
-+ writew(width-1, &bltreg->width0);
-+ writew(height-1, &bltreg->height0);
-+
-+ // program color format operation
-+ writeb(bpp == 8 ? 0x00 : 0x01, &bltreg->ctrl1);
-+
-+ // set the blt type
-+ if (blt->attribute & BLT_ATTR_TRANSPARENT) {
-+ writew(blt->bg_color, &bltreg->bg_color0);
-+ writeb(BLT_MOVE_POS_TRANSP, &bltreg->operation);
-+ } else {
-+ writeb(blt->rop, &bltreg->rop_code);
-+ // select pos/neg move BLIT
-+ writeb(neg_dir ? BLT_MOVE_NEG_ROP : BLT_MOVE_POS_ROP,
-+ &bltreg->operation);
-+ }
++ outl(0x00000003, PCI_BASE | 0x0004770c);
+
-+ // start it up (self completes)
-+ writeb(0x80, &bltreg->ctrl0);
++ /*
++ * Set register CLK12CTL to enable and 48MHz
++ */
++ outl(0x00000003, PCI_BASE | 0x00047710);
+
-+ e1356_engine_wait_complete(bltreg);
++ udelay(100);
+}
+
-+
-+static void doBlt_ColorExpand(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info,
-+ blt_info_t* blt)
++static void pnx8550_stop_hc(struct platform_device *dev)
+{
-+ reg_bitblt_t* bltreg = info->reg.bitblt;
-+ int i, j, nWords, Sx, Sy;
-+ u32 dstAddr;
-+ u16* wpt, *wpt1;
-+ u32 stride = par->width_virt * par->Bpp;
-+
-+ if (blt->dst_width == 0 || blt->dst_height == 0)
-+ return;
-+
-+ Sx = blt->src_x;
-+ Sy = blt->src_y;
-+
-+ writeb((7 - Sx%8), &bltreg->rop_code);
-+
-+ writeb(blt->operation, &bltreg->operation);
-+
-+ writeb((u8)(Sx & 1), &bltreg->src_start_addr0);
-+
-+ dstAddr = blt->dst_x*par->Bpp + blt->dst_y * stride;
-+ writeb(dstAddr, &bltreg->dest_start_addr0);
-+ writeb(dstAddr>>8, &bltreg->dest_start_addr1);
-+ writeb(dstAddr>>16, &bltreg->dest_start_addr2);
-+
-+ // program color format operation
-+ writeb(par->bpp == 8 ? 0x00 : 0x01, &bltreg->ctrl1);
-+ writew(stride/2, &bltreg->mem_addr_offset0);
-+ writew(blt->dst_width-1, &bltreg->width0);
-+ writew(blt->dst_height-1, &bltreg->height0);
-+ writew(blt->bg_color, &bltreg->bg_color0);
-+ writew(blt->fg_color, &bltreg->fg_color0);
-+
-+ // start it up
-+ writeb(0x80, &bltreg->ctrl0);
++ udelay(10);
++}
+
-+ // wait for it to actually start
-+ e1356_engine_wait_busy(bltreg);
+
-+ // calculate the number of 16 bit words per one blt line
++/*-------------------------------------------------------------------------*/
+
-+ nWords = (Sx%16 + blt->dst_width + 15)/16;
++/* configure so an HC device and id are always provided */
++/* always called with process context; sleeping is OK */
+
-+ wpt = blt->src + (Sy*blt->srcstride + Sx/16)/2;
+
-+ for (i = 0; i < blt->dst_height; i++) {
-+ wpt1 = wpt;
++/**
++ * usb_hcd_pnx8550_probe - initialize pnx8550-based HCDs
++ * Context: !in_interrupt()
++ *
++ * Allocates basic resources for this USB host controller, and
++ * then invokes the start() method for the HCD associated with it
++ * through the hotplug entry's driver_data.
++ *
++ */
++int usb_hcd_pnx8550_probe (const struct hc_driver *driver,
++ struct platform_device *dev)
++{
++ int retval;
++ struct usb_hcd *hcd;
+
-+ for (j = 0; j < nWords; j++) {
-+ // loop until FIFO becomes empty...
-+ e1356_wait_bitclr(&bltreg->ctrl0, 0x40, 10000);
-+ writew(*wpt1++, info->reg.bitblt_data);
-+ }
-+
-+ wpt += blt->srcstride/2;
++ if (dev->resource[1].flags != IORESOURCE_IRQ) {
++ pr_debug ("resource[1] is not IORESOURCE_IRQ");
++ return -ENOMEM;
+ }
+
-+ e1356_engine_wait_complete(bltreg);
-+}
++ hcd = usb_create_hcd (driver, &dev->dev, "pnx8550");
++ if (!hcd)
++ return -ENOMEM;
++ hcd->rsrc_start = dev->resource[0].start;
++ hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
+
++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
++ pr_debug("request_mem_region failed");
++ retval = -EBUSY;
++ goto err1;
++ }
+
-+/*
-+ * The BitBLT operation dispatcher
-+ */
-+static int
-+doBlt(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info,
-+ blt_info_t* blt)
-+{
-+ /*
-+ * Make sure we're not reentering in the middle of an
-+ * active BitBLT operation. ALWAYS call this dispatcher
-+ * and not one of the above BLT routines directly, or you
-+ * run the risk of overlapping BLT operations, which can
-+ * cause complete system hangs.
-+ */
-+ if (readb(&info->reg.bitblt->ctrl0) & 0x80)
-+ return -ENXIO;
-+
-+ switch (blt->operation) {
-+ case BLT_MOVE_POS_ROP:
-+ case BLT_MOVE_NEG_ROP:
-+ case BLT_MOVE_POS_TRANSP:
-+ doBlt_Move(par, info, blt);
-+ break;
-+ case BLT_COLOR_EXP:
-+ case BLT_COLOR_EXP_TRANSP:
-+ doBlt_ColorExpand(par, info, blt);
-+ break;
-+ case BLT_SOLID_FILL:
-+ doBlt_SolidFill(par, info, blt);
-+ break;
-+ case BLT_WRITE_ROP:
-+ case BLT_WRITE_TRANSP:
-+ doBlt_Write(par, info, blt);
-+ break;
-+ case BLT_READ:
-+ case BLT_PAT_FILL_ROP:
-+ case BLT_PAT_FILL_TRANSP:
-+ case BLT_MOVE_COLOR_EXP:
-+ case BLT_MOVE_COLOR_EXP_TRANSP:
-+ DPRINTK("BitBLT operation 0x%02x not implemented yet\n",
-+ blt->operation);
-+ return -ENXIO;
-+ default:
-+ DPRINTK("Unknown BitBLT operation 0x%02x\n", blt->operation);
-+ return -ENXIO;
++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
++ if (!hcd->regs) {
++ pr_debug("ioremap failed");
++ retval = -ENOMEM;
++ goto err2;
+ }
-+
-+ return 0;
-+}
+
++ pnx8550_start_hc(dev);
+
-+// Initializes blt->src and blt->srcstride
-+static void fill_putcs_buffer(struct display *p,
-+ blt_info_t* blt,
-+ const unsigned short* str,
-+ int count)
-+{
-+ int row, i, j;
-+ u8* b1, *b2;
-+ u32 fw = fontwidth(p);
-+ u32 fwb = (fw + 7) >> 3;
-+ u32 fh = fontheight(p);
-+ int bytesPerChar = fwb * fh;
-+
-+ if (count*bytesPerChar > PAGE_SIZE) {
-+ // Truncate the string if it overflows putcs_buffer, which is
-+ // one page in size.
-+ count = PAGE_SIZE/bytesPerChar - 1;
-+ }
++ ohci_hcd_init(hcd_to_ohci(hcd));
+
-+ blt->srcstride = (fwb*count + 1) & ~1; //round up to be even
-+
-+ b1 = (u8*)blt->src;
++ retval = usb_add_hcd(hcd, dev->resource[1].start, SA_INTERRUPT);
++ if (retval == 0)
++ return retval;
+
-+ for (row = 0; row < fh; row++) {
-+ b2 = b1;
-+ for (i = 0; i < count; i++) {
-+ for (j=0; j<fwb; j++)
-+ *b2++ = p->fontdata[(str[i] & p->charmask) *
-+ bytesPerChar +
-+ row*fwb + j];
-+ }
-+ b1 += blt->srcstride;
-+ }
++ pnx8550_stop_hc(dev);
++ iounmap(hcd->regs);
++ err2:
++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++ err1:
++ usb_put_hcd(hcd);
++ return retval;
+}
+
+
-+/*
-+ * Set the color of a palette entry in 8bpp mode
-+ */
-+static inline void
-+do_setpalentry(reg_lut_t* lut, unsigned regno,
-+ u8 r, u8 g, u8 b)
-+{
-+ writeb(0x00, &lut->mode);
-+ writeb((u8)regno, &lut->addr);
-+ writeb(r&0xf0, &lut->data);
-+ writeb(g&0xf0, &lut->data);
-+ writeb(b&0xf0, &lut->data);
-+}
++/* may be called without controller electrically present */
++/* may be called with controller, bus, and devices active */
+
-+
-+static void
-+do_pan_var(struct fb_var_screeninfo* var, struct fb_info_e1356* info)
-+{
-+ u32 pixel_start, start_addr;
-+ u8 pixel_pan;
-+ struct e1356fb_par* par = &info->current_par;
-+ reg_misc_t* misc = info->reg.misc;
-+ reg_dispmode_t* dispmode = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_mode : info->reg.crttv_mode;
-+
-+ pixel_start = var->yoffset * par->width_virt + var->xoffset;
-+ start_addr = (pixel_start * par->Bpp) / 2;
-+ pixel_pan = (par->bpp == 8) ? (u8)(pixel_start & 1) : 0;
-+
-+ if (readb(&misc->disp_mode) != 0) {
-+ reg_dispcfg_t* dispcfg = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_cfg : info->reg.crttv_cfg;
-+
-+ // wait for the end of the current VNDP
-+ e1356_wait_bitclr(&dispcfg->vndp, 0x80, 5000);
-+ // now wait for the start of a new VNDP
-+ e1356_wait_bitset(&dispcfg->vndp, 0x80, 5000);
-+ }
-+
-+ writeb((u8)(start_addr & 0xff), &dispmode->start_addr0);
-+ writeb((u8)((start_addr>>8) & 0xff), &dispmode->start_addr1);
-+ writeb((u8)((start_addr>>16) & 0xff), &dispmode->start_addr2);
-+ writeb(pixel_pan, &dispmode->pixel_panning);
++/**
++ * usb_hcd_pnx8550_remove - shutdown processing for pnx8550-based HCDs
++ * @dev: USB Host Controller being removed
++ * Context: !in_interrupt()
++ *
++ * Reverses the effect of usb_hcd_pnx8550_probe(), first invoking
++ * the HCD's stop() method. It is always called from a thread
++ * context, normally "rmmod", "apmd", or something similar.
++ *
++ */
++void usb_hcd_pnx8550_remove (struct usb_hcd *hcd, struct platform_device *dev)
++{
++ usb_remove_hcd(hcd);
++ pnx8550_stop_hc(dev);
++ iounmap(hcd->regs);
++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++ usb_put_hcd(hcd);
+}
+
++/*-------------------------------------------------------------------------*/
+
-+/*
-+ * Invert the hardware cursor image (timerfunc)
-+ */
-+static void
-+do_flashcursor(unsigned long ptr)
++static int __devinit
++ohci_pnx8550_start (struct usb_hcd *hcd)
+{
-+ u8 curs_ctrl;
-+ struct fb_info_e1356* info = (struct fb_info_e1356 *)ptr;
-+ reg_inkcurs_t* inkcurs = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_inkcurs : info->reg.crttv_inkcurs;
-+
-+ spin_lock(&info->cursor.lock);
-+ // toggle cursor enable bit
-+ curs_ctrl = readb(&inkcurs->ctrl);
-+ writeb((curs_ctrl ^ 0x01) & 0x01, &inkcurs->ctrl);
-+ info->cursor.timer.expires = jiffies+HZ/2;
-+ add_timer(&info->cursor.timer);
-+ spin_unlock(&info->cursor.lock);
-+}
++ struct ohci_hcd *ohci = hcd_to_ohci (hcd);
++ int ret;
+
-+#ifdef SHADOW_FRAME_BUFFER
-+/*
-+ * Write BLT the shadow frame buffer to the real fb (timerfunc)
-+ */
-+static void
-+do_write_shadow_fb(unsigned long ptr)
-+{
-+ blt_info_t blt;
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)ptr;
-+ struct fb_info* fb = &info->fb_info;
-+ struct e1356fb_par* par = &info->current_par;
-+ u32 stride = par->width_virt * par->Bpp;
++ ohci_dbg (ohci, "ohci_pnx8550_start, ohci:%p", ohci);
+
-+ unsigned long j_start = jiffies;
-+
-+ blt.src_x = blt.src_y = 0;
-+ blt.attribute = 0;
-+ blt.dst_width = par->width;
-+ blt.dst_height = par->height;
-+ blt.dst_y = fb->var.yoffset;
-+ blt.dst_x = fb->var.xoffset;
-+ blt.operation = BLT_WRITE_ROP;
-+ blt.rop = 0x0c; // ROP: destination = source
-+ blt.src = (u16*)(info->shadow.fb + blt.dst_x * par->Bpp +
-+ blt.dst_y * stride);
++ if ((ret = ohci_init(ohci)) < 0)
++ return ret;
+
-+ doBlt(par, info, &blt);
-+
-+ info->shadow.timer.expires = jiffies+HZ/2;
-+ add_timer(&info->shadow.timer);
++ if ((ret = ohci_run (ohci)) < 0) {
++ err ("can't start %s", hcd->self.bus_name);
++ ohci_stop (hcd);
++ return ret;
++ }
+
-+ //DPRINTK("delta jiffies = %ld\n", jiffies - j_start);
++ return 0;
+}
-+#endif
-+
+
-+/* -------------------------------------------------------------------------
-+ * Hardware independent part, interface to the world
-+ * ------------------------------------------------------------------------- */
-+
-+static void
-+e1356_cfbX_clear_margins(struct vc_data* conp, struct display* p,
-+ int bottom_only)
-+{
-+ blt_info_t blt;
-+ unsigned int cw=fontwidth(p);
-+ unsigned int ch=fontheight(p);
-+ unsigned int rw=p->var.xres % cw;
-+ unsigned int bh=p->var.yres % ch;
-+ unsigned int rs=p->var.xres - rw;
-+ unsigned int bs=p->var.yres - bh;
-+
-+ //DPRINTK("\n");
-+
-+ if (!bottom_only && rw) {
-+ blt.dst_x = p->var.xoffset+rs;
-+ blt.dst_y = p->var.yoffset;
-+ blt.dst_height = p->var.yres;
-+ blt.dst_width = rw;
-+ blt.attribute = 0;
-+ blt.fg_color = 0;
-+ blt.operation = BLT_SOLID_FILL;
-+ doBlt (&fb_info.current_par, &fb_info, &blt);
-+ }
-+
-+ if (bh) {
-+ blt.dst_x = p->var.xoffset;
-+ blt.dst_y = p->var.yoffset+bs;
-+ blt.dst_height = bh;
-+ blt.dst_width = rs;
-+ blt.attribute = 0;
-+ blt.fg_color = 0;
-+ blt.operation = BLT_SOLID_FILL;
-+ doBlt (&fb_info.current_par, &fb_info, &blt);
-+ }
-+}
++/*-------------------------------------------------------------------------*/
+
-+static void
-+e1356_cfbX_bmove(struct display* p,
-+ int sy,
-+ int sx,
-+ int dy,
-+ int dx,
-+ int height,
-+ int width)
-+{
-+ blt_info_t blt;
-+
-+ //DPRINTK("(%d,%d) to (%d,%d) size (%d,%d)\n", sx,sy,dx,dy,width,height);
++static const struct hc_driver ohci_pnx8550_hc_driver = {
++ .description = hcd_name,
++ .product_desc = "PNX8550 OHCI",
++ .hcd_priv_size = sizeof(struct ohci_hcd),
+
-+ blt.src_x = fontwidth_x8(p)*sx;
-+ blt.src_y = fontheight(p)*sy;
-+ blt.dst_x = fontwidth_x8(p)*dx;
-+ blt.dst_y = fontheight(p)*dy;
-+ blt.src_height = blt.dst_height = fontheight(p)*height;
-+ blt.src_width = blt.dst_width = fontwidth_x8(p)*width;
-+ blt.attribute = 0;
-+ blt.rop = 0x0c;
+ /*
-+ * The move BLT routine will actually decide between a pos/neg
-+ * move BLT. This is just so that the BLT dispatcher knows to
-+ * call the move BLT routine.
++ * generic hardware linkage
+ */
-+ blt.operation = BLT_MOVE_POS_ROP;
-+
-+ doBlt (&fb_info.current_par, &fb_info, &blt);
-+}
-+
-+static void
-+e1356_cfb8_putc(struct vc_data* conp,
-+ struct display* p,
-+ int c, int yy,int xx)
-+{
-+ blt_info_t blt;
-+ u32 fgx,bgx;
-+ u32 fw = fontwidth_x8(p);
-+ u32 fh = fontheight(p);
-+ u16 cs = (u16)c;
-+
-+ fgx = attr_fgcol(p, c);
-+ bgx = attr_bgcol(p, c);
-+
-+ blt.src_x = blt.src_y = 0;
-+ blt.attribute = 0;
-+ blt.dst_width = fw;
-+ blt.dst_height = fh;
-+ blt.dst_y = yy * fh;
-+ blt.dst_x = xx * fw;
-+ blt.bg_color = bgx;
-+ blt.fg_color = fgx;
-+ blt.operation = BLT_COLOR_EXP;
-+ blt.src = fb_info.putcs_buffer;
-+ fill_putcs_buffer(p, &blt, &cs, 1);
-+
-+ doBlt(&fb_info.current_par, &fb_info, &blt);
++ .irq = ohci_irq,
++ .flags = HCD_USB11 | HCD_MEMORY,
+
-+}
++ /*
++ * basic lifecycle operations
++ */
++ .start = ohci_pnx8550_start,
++ .stop = ohci_stop,
+
-+static void
-+e1356_cfb16_putc(struct vc_data* conp,
-+ struct display* p,
-+ int c, int yy,int xx)
-+{
-+ blt_info_t blt;
-+ u32 fgx,bgx;
-+ u32 fw = fontwidth_x8(p);
-+ u32 fh = fontheight(p);
-+ u16 cs = (u16)c;
-+
-+ fgx = ((u16*)p->dispsw_data)[attr_fgcol(p,c)];
-+ bgx = ((u16*)p->dispsw_data)[attr_bgcol(p,c)];
++ /*
++ * managing i/o requests and associated device resources
++ */
++ .urb_enqueue = ohci_urb_enqueue,
++ .urb_dequeue = ohci_urb_dequeue,
++ .endpoint_disable = ohci_endpoint_disable,
+
-+ blt.src_x = blt.src_y = 0;
-+ blt.attribute = 0;
-+ blt.dst_width = fw;
-+ blt.dst_height = fh;
-+ blt.dst_y = yy * fh;
-+ blt.dst_x = xx * fw;
-+ blt.bg_color = bgx;
-+ blt.fg_color = fgx;
-+ blt.operation = BLT_COLOR_EXP;
-+ blt.src = fb_info.putcs_buffer;
-+ fill_putcs_buffer(p, &blt, &cs, 1);
++ /*
++ * scheduling support
++ */
++ .get_frame_number = ohci_get_frame,
+
-+ doBlt(&fb_info.current_par, &fb_info, &blt);
-+}
++ /*
++ * root hub support
++ */
++ .hub_status_data = ohci_hub_status_data,
++ .hub_control = ohci_hub_control,
++#ifdef CONFIG_USB_SUSPEND
++ .hub_suspend = ohci_hub_suspend,
++ .hub_resume = ohci_hub_resume,
++#endif
++};
+
++/*-------------------------------------------------------------------------*/
+
-+static void
-+e1356_cfb8_putcs(struct vc_data* conp,
-+ struct display* p,
-+ const unsigned short *s,int count,int yy,int xx)
-+{
-+ blt_info_t blt;
-+ u32 fgx,bgx;
-+ u32 fw = fontwidth_x8(p);
-+ u32 fh = fontheight(p);
-+
-+ //DPRINTK("\n");
-+
-+ fgx=attr_fgcol(p, *s);
-+ bgx=attr_bgcol(p, *s);
-+
-+ blt.src_x = blt.src_y = 0;
-+ blt.attribute = 0;
-+ blt.dst_width = count * fw;
-+ blt.dst_height = fh;
-+ blt.dst_y = yy * fh;
-+ blt.dst_x = xx * fw;
-+ blt.bg_color = bgx;
-+ blt.fg_color = fgx;
-+ blt.operation = BLT_COLOR_EXP;
-+ blt.src = fb_info.putcs_buffer;
-+ fill_putcs_buffer(p, &blt, s, count);
++static int ohci_hcd_pnx8550_drv_probe(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ int ret;
+
-+ doBlt(&fb_info.current_par, &fb_info, &blt);
-+}
++ pr_debug ("In ohci_hcd_pnx8550_drv_probe");
+
-+static void
-+e1356_cfb16_putcs(struct vc_data* conp,
-+ struct display* p,
-+ const unsigned short *s,int count,int yy,int xx)
-+{
-+ blt_info_t blt;
-+ u32 fgx,bgx;
-+ u32 fw = fontwidth_x8(p);
-+ u32 fh = fontheight(p);
-+
-+ //DPRINTK("\n");
-+
-+ fgx=((u16*)p->dispsw_data)[attr_fgcol(p,*s)];
-+ bgx=((u16*)p->dispsw_data)[attr_bgcol(p,*s)];
-+
-+ blt.src_x = blt.src_y = 0;
-+ blt.attribute = 0;
-+ blt.dst_width = count * fw;
-+ blt.dst_height = fh;
-+ blt.dst_y = yy * fh;
-+ blt.dst_x = xx * fw;
-+ blt.bg_color = bgx;
-+ blt.fg_color = fgx;
-+ blt.operation = BLT_COLOR_EXP;
-+ blt.src = fb_info.putcs_buffer;
-+ fill_putcs_buffer(p, &blt, s, count);
++ if (usb_disabled())
++ return -ENODEV;
+
-+ doBlt(&fb_info.current_par, &fb_info, &blt);
++ ret = usb_hcd_pnx8550_probe(&ohci_pnx8550_hc_driver, pdev);
++ return ret;
+}
+
++static int ohci_hcd_pnx8550_drv_remove(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct usb_hcd *hcd = dev_get_drvdata(dev);
+
-+static void
-+e1356_cfb8_clear(struct vc_data* conp,
-+ struct display* p,
-+ int sy,
-+ int sx,
-+ int height,
-+ int width)
-+{
-+ blt_info_t blt;
-+ u32 bg = attr_bgcol_ec(p,conp);
-+
-+ //DPRINTK("(%d,%d) size (%d,%d)\n", sx,sy,width,height);
-+
-+ blt.dst_x = fontwidth_x8(p)*sx;
-+ blt.dst_y = fontheight(p)*sy;
-+ blt.dst_height = fontheight(p)*height;
-+ blt.dst_width = fontwidth_x8(p)*width;
-+ blt.attribute = 0;
-+ blt.fg_color = bg;
-+ blt.operation = BLT_SOLID_FILL;
-+
-+ doBlt (&fb_info.current_par, &fb_info, &blt);
++ usb_hcd_pnx8550_remove(hcd, pdev);
++ return 0;
+}
+
-+static void
-+e1356_cfb16_clear(struct vc_data* conp,
-+ struct display* p,
-+ int sy,
-+ int sx,
-+ int height,
-+ int width)
-+{
-+ blt_info_t blt;
-+ u32 bg = ((u16*)p->dispsw_data)[attr_bgcol_ec(p,conp)];
-+
-+ //DPRINTK("(%d,%d) size (%d,%d)\n", sx,sy,width,height);
-+
-+ blt.dst_x = fontwidth_x8(p)*sx;
-+ blt.dst_y = fontheight(p)*sy;
-+ blt.dst_height = fontheight(p)*height;
-+ blt.dst_width = fontwidth_x8(p)*width;
-+ blt.attribute = 0;
-+ blt.fg_color = bg;
-+ blt.operation = BLT_SOLID_FILL;
++static int ohci_hcd_pnx8550_drv_suspend(struct device *dev, u32 state, u32 level)
++{
++// struct platform_device *pdev = to_platform_device(dev);
++// struct usb_hcd *hcd = dev_get_drvdata(dev);
++ printk("%s: not implemented yet\n", __FUNCTION__);
+
-+ doBlt (&fb_info.current_par, &fb_info, &blt);
++ return 0;
+}
+
-+
-+static void
-+e1356_cfbX_revc(struct display *p, int xx, int yy)
++static int ohci_hcd_pnx8550_drv_resume(struct device *dev, u32 state)
+{
-+ // not used if h/w cursor
-+ //DPRINTK("\n");
-+}
++// struct platform_device *pdev = to_platform_device(dev);
++// struct usb_hcd *hcd = dev_get_drvdata(dev);
++ printk("%s: not implemented yet\n", __FUNCTION__);
+
-+static void
-+e1356_cfbX_cursor(struct display *p, int mode, int x, int y)
-+{
-+ unsigned long flags;
-+ struct fb_info_e1356 *info=(struct fb_info_e1356 *)p->fb_info;
-+ reg_inkcurs_t* inkcurs = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_inkcurs : info->reg.crttv_inkcurs;
-+
-+ //DPRINTK("\n");
++ return 0;
++}
+
-+ if (mode == CM_ERASE) {
-+ if (info->cursor.state != CM_ERASE) {
-+ spin_lock_irqsave(&info->cursor.lock,flags);
-+ info->cursor.state = CM_ERASE;
-+ del_timer(&(info->cursor.timer));
-+ writeb(0x00, &inkcurs->ctrl);
-+ spin_unlock_irqrestore(&info->cursor.lock,flags);
-+ }
-+ return;
-+ }
-+
-+ if ((p->conp->vc_cursor_type & CUR_HWMASK) != info->cursor.type)
-+ e1356fb_createcursor(p);
-+
-+ x *= fontwidth_x8(p);
-+ y *= fontheight(p);
-+ x -= p->var.xoffset;
-+ y -= p->var.yoffset;
-+
-+ spin_lock_irqsave(&info->cursor.lock,flags);
-+ if ((x != info->cursor.x) || (y != info->cursor.y) ||
-+ (info->cursor.redraw)) {
-+ info->cursor.x = x;
-+ info->cursor.y = y;
-+ info->cursor.redraw = 0;
-+ writeb(0x01, &inkcurs->ctrl);
-+ writew(x, &inkcurs->x_pos0);
-+ writew(y, &inkcurs->y_pos0);
-+ /* fix cursor color - XFree86 forgets to restore it properly */
-+ writeb(0x00, &inkcurs->blue0);
-+ writeb(0x00, &inkcurs->green0);
-+ writeb(0x00, &inkcurs->red0);
-+ writeb(0x1f, &inkcurs->blue1);
-+ writeb(0x3f, &inkcurs->green1);
-+ writeb(0x1f, &inkcurs->red1);
-+ }
-+
-+ info->cursor.state = CM_DRAW;
-+ mod_timer(&info->cursor.timer, jiffies+HZ/2);
-+ spin_unlock_irqrestore(&info->cursor.lock,flags);
-+}
-+
-+#ifdef FBCON_HAS_CFB8
-+static struct display_switch fbcon_e1356_8 = {
-+ .setup = fbcon_cfb8_setup,
-+ .bmove = e1356_cfbX_bmove,
-+ .clear = e1356_cfb8_clear,
-+ .putc = e1356_cfb8_putc,
-+ .putcs = e1356_cfb8_putcs,
-+ .revc = e1356_cfbX_revc,
-+ .cursor = e1356_cfbX_cursor,
-+ .clear_margins = e1356_cfbX_clear_margins,
-+ .fontwidthmask = FONTWIDTHRANGE(6,16)
-+};
-+#endif
+
-+#ifdef FBCON_HAS_CFB16
-+static struct display_switch fbcon_e1356_16 = {
-+ .setup = fbcon_cfb16_setup,
-+ .bmove = e1356_cfbX_bmove,
-+ .clear = e1356_cfb16_clear,
-+ .putc = e1356_cfb16_putc,
-+ .putcs = e1356_cfb16_putcs,
-+ .revc = e1356_cfbX_revc,
-+ .cursor = e1356_cfbX_cursor,
-+ .clear_margins = e1356_cfbX_clear_margins,
-+ .fontwidthmask = FONTWIDTHRANGE(6,16)
++static struct device_driver ohci_hcd_pnx8550_driver = {
++ .name = "pnx8550-ohci",
++ .bus = &platform_bus_type,
++ .probe = ohci_hcd_pnx8550_drv_probe,
++ .remove = ohci_hcd_pnx8550_drv_remove,
++ .suspend = ohci_hcd_pnx8550_drv_suspend,
++ .resume = ohci_hcd_pnx8550_drv_resume,
+};
-+#endif
+
-+/* ------------------------------------------------------------------------- */
++static int __init ohci_hcd_pnx8550_init (void)
++{
++ pr_debug (DRIVER_INFO " (pnx8550)");
++ pr_debug ("block sizes: ed %d td %d\n",
++ sizeof (struct ed), sizeof (struct td));
+
-+static void
-+e1356fb_set_par(const struct e1356fb_par* par,
-+ struct fb_info_e1356* info)
++ return driver_register(&ohci_hcd_pnx8550_driver);
++}
++
++static void __exit ohci_hcd_pnx8550_cleanup (void)
+{
-+ reg_dispcfg_t* dispcfg=NULL;
-+ reg_dispmode_t* dispmode=NULL;
-+ u8* pclk_cfg=NULL;
-+ u8 width, hndp=0, hsync_start=0, hsync_width=0;
-+ u8 vndp, vsync_start, vsync_width=0, display_mode;
-+ u8 main_display_mode=0;
-+ u16 height, addr_offset;
-+ int disp_type = info->fix.disp_type;
-+
-+ DPRINTK("%dx%d-%dbpp @ %d Hz, %d kHz hsync\n",
-+ par->width, par->height, par->bpp,
-+ par->vsync_freq, (((2*par->hsync_freq)/1000)+1)/2);
-+#ifdef E1356FB_VERBOSE_DEBUG
-+ dump_par(par);
-+#endif
-+
-+ info->current_par = *par;
++ driver_unregister(&ohci_hcd_pnx8550_driver);
++}
+
-+ width = (par->width >> 3) - 1;
-+ display_mode = (par->bpp == 8) ? 0x03 : 0x05;
-+ addr_offset = (par->width_virt * par->Bpp) / 2;
-+ vsync_start = (disp_type == DISP_TYPE_LCD) ? 0 : par->vsync_start - 1;
-+ height = par->height - 1;
-+ vndp = par->vert_ndp - 1;
-+
-+ switch (disp_type) {
-+ case DISP_TYPE_LCD:
-+ dispcfg = info->reg.lcd_cfg;
-+ dispmode = info->reg.lcd_mode;
-+ pclk_cfg = &info->reg.clk_cfg->lcd_pclk_cfg;
-+ hndp = (par->horiz_ndp >> 3) - 1;
-+ hsync_start = 0;
-+ hsync_width = par->hsync_pol ? 0x00 : 0x80;
-+ vsync_width = par->vsync_pol ? 0x00 : 0x80;
-+ main_display_mode = 0x01;
-+ break;
-+ case DISP_TYPE_TFT:
-+ dispcfg = info->reg.lcd_cfg;
-+ dispmode = info->reg.lcd_mode;
-+ pclk_cfg = &info->reg.clk_cfg->lcd_pclk_cfg;
-+ hndp = (par->horiz_ndp >> 3) - 1;
-+ hsync_start = (par->bpp == 8) ?
-+ (par->hsync_start - 4) >> 3 :
-+ (par->hsync_start - 6) >> 3;
-+ hsync_width =
-+ (par->hsync_pol ? 0x80 : 0x00) |
-+ ((par->hsync_width >> 3) - 1);
-+ vsync_width =
-+ (par->vsync_pol ? 0x80 : 0x00) |
-+ (par->vsync_width - 1);
-+ main_display_mode = 0x01;
-+ break;
-+ case DISP_TYPE_CRT:
-+ dispcfg = info->reg.crttv_cfg;
-+ dispmode = info->reg.crttv_mode;
-+ pclk_cfg = &info->reg.clk_cfg->crttv_pclk_cfg;
-+ hndp = (par->horiz_ndp >> 3) - 1;
-+ hsync_start = (par->bpp == 8) ?
-+ (par->hsync_start - 3) >> 3 :
-+ (par->hsync_start - 5) >> 3;
-+ hsync_width =
-+ (par->hsync_pol ? 0x80 : 0x00) |
-+ ((par->hsync_width >> 3) - 1);
-+ vsync_width =
-+ (par->vsync_pol ? 0x80 : 0x00) |
-+ (par->vsync_width - 1);
-+ main_display_mode = 0x02;
-+ break;
-+ case DISP_TYPE_NTSC:
-+ case DISP_TYPE_PAL:
-+ dispcfg = info->reg.crttv_cfg;
-+ dispmode = info->reg.crttv_mode;
-+ pclk_cfg = &info->reg.clk_cfg->crttv_pclk_cfg;
-+ hndp = (disp_type == DISP_TYPE_PAL) ?
-+ (par->horiz_ndp - 7) >> 3 :
-+ (par->horiz_ndp - 6) >> 3;
-+ hsync_start = (par->bpp == 8) ?
-+ (par->hsync_start + 7) >> 3 :
-+ (par->hsync_start + 5) >> 3;
-+ hsync_width = 0;
-+ vsync_width = 0;
-+ main_display_mode = (info->fix.tv_filt & TV_FILT_FLICKER) ?
-+ 0x06 : 0x04;
-+ break;
-+ }
++module_init (ohci_hcd_pnx8550_init);
++module_exit (ohci_hcd_pnx8550_cleanup);
+diff -urN --ignore-space-change kernel.org/drivers/video/Kconfig linux-mips/drivers/video/Kconfig
+--- kernel.org/drivers/video/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/video/Kconfig 2006-01-10 11:21:49.000000000 +0000
+@@ -1149,6 +1149,17 @@
+ Please read the <file:Documentation/fb/README-sstfb.txt> for supported
+ options and other important info support.
+
++config FB_SMIVGX
++ tristate "Silicon Motion VoyagerGX support"
++ depends on FB && PCI && (MIPS || EXPERIMENTAL)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ This drivers supports SMI VoyagerGX 501 based PCI boards
++ The default settings drive both a CRT and LCD. The CRT
++ can be turned off by passing in the no_crt option
+
-+ // Blast the regs!
-+ // note: reset panning/scrolling (set start-addr and
-+ // pixel pan regs to 0). Panning is handled by pan_display.
-+
-+ e1356_engine_wait_complete(info->reg.bitblt);
-+
-+ // disable display while initializing
-+ writeb(0, &info->reg.misc->disp_mode);
-+
-+ writeb(par->ipclk.pixclk_bits, pclk_cfg);
-+
-+ writeb(width, &dispcfg->hdw);
-+ writeb(hndp, &dispcfg->hndp);
-+ writeb(hsync_start, &dispcfg->hsync_start);
-+ writeb(hsync_width, &dispcfg->hsync_pulse);
-+ writew(height, &dispcfg->vdh0);
-+ writeb(vndp, &dispcfg->vndp);
-+ writeb(vsync_start, &dispcfg->vsync_start);
-+ writeb(vsync_width, &dispcfg->vsync_pulse);
-+
-+ writeb(display_mode, &dispmode->disp_mode);
-+ if (info->fix.mmunalign && info->mmaped)
-+ writeb(1, &dispmode->start_addr0);
-+ else
-+ writeb(0, &dispmode->start_addr0);
-+ writeb(0, &dispmode->start_addr1);
-+ writeb(0, &dispmode->start_addr2);
-+ writew(addr_offset, &dispmode->mem_addr_offset0);
-+ writeb(0, &dispmode->pixel_panning);
+ config FB_CYBLA
+ tristate "Cyberblade/i1 support"
+ depends on FB && PCI
+@@ -1213,7 +1224,25 @@
+
+ config FB_AU1100
+ bool "Au1100 LCD Driver"
+- depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
++ depends on FB && MIPS && SOC_AU1100
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the framebuffer driver for the AMD Au1100 SOC. It can drive
++ various panels and CRTs by passing in kernel cmd line option
++ au1100fb:panel=<name>.
+
-+ // reset BitBlt engine
-+ e1356fb_engine_init(par, info);
++config FB_AU1200
++ bool "Au1200 LCD Driver"
++ depends on FB && MIPS && SOC_AU1200
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the framebuffer driver for the AMD Au1200 SOC. It can drive
++ various panels and CRTs by passing in kernel cmd line option
++ au1200fb:panel=<name>.
+
+ source "drivers/video/geode/Kconfig"
+
+diff -urN --ignore-space-change kernel.org/drivers/video/Makefile linux-mips/drivers/video/Makefile
+--- kernel.org/drivers/video/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/video/Makefile 2006-01-10 11:30:59.000000000 +0000
+@@ -86,6 +86,7 @@
+ obj-$(CONFIG_FB_PXA) += pxafb.o
+ obj-$(CONFIG_FB_W100) += w100fb.o
+ obj-$(CONFIG_FB_AU1100) += au1100fb.o
++obj-$(CONFIG_FB_AU1200) += au1200fb.o
+ obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
+ obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
+ obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
+@@ -93,6 +94,7 @@
+ obj-$(CONFIG_FB_TX3912) += tx3912fb.o
+ obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
+ obj-$(CONFIG_FB_IMX) += imxfb.o
++obj-$(CONFIG_FB_SMIVGX) += smivgxfb.o
+ obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
+
+ # Platform or fallback drivers go here
+diff -urN --ignore-space-change kernel.org/drivers/video/au1100fb.c linux-mips/drivers/video/au1100fb.c
+--- kernel.org/drivers/video/au1100fb.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/drivers/video/au1100fb.c 2006-01-10 11:21:49.000000000 +0000
+@@ -38,6 +38,7 @@
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
-+#ifdef E1356FB_VERBOSE_DEBUG
-+ dump_display_regs(dispcfg, dispmode);
-+#endif
+ #include <linux/config.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+diff -urN --ignore-space-change kernel.org/drivers/video/au1200fb.c linux-mips/drivers/video/au1200fb.c
+--- kernel.org/drivers/video/au1200fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/video/au1200fb.c 2006-01-10 11:21:49.000000000 +0000
+@@ -0,0 +1,1940 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ * Au1200 LCD Driver.
++ *
++ * Copyright 2004-2005 AMD
++ * Author: AMD
++ *
++ * Based on:
++ * linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
++ * Created 28 Dec 1997 by Geert Uytterhoeven
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
+
-+ /* clear out framebuffer memory */
-+ fbfill(fb_info.membase_virt, 0, fb_info.fb_size);
-+ // finally, enable display!
-+ writeb(main_display_mode, &info->reg.misc->disp_mode);
-+}
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/ctype.h>
++#include <linux/dma-mapping.h>
+
++#include <asm/mach-au1x00/au1000.h>
++#include "au1200fb.h"
+
-+static int
-+e1356fb_verify_timing(struct e1356fb_par* par,
-+ const struct fb_info_e1356* info)
-+{
-+ int disp_type = info->fix.disp_type;
++#ifdef CONFIG_PM
++#include <asm/mach-au1x00/au1xxx_pm.h>
++#endif
+
-+ // timing boundary checks
-+ if (par->horiz_ndp > max_hndp[disp_type]) {
-+ DPRINTK("horiz_ndp too big: %d\n", par->horiz_ndp);
-+ return -EINVAL;
-+ }
-+ if (par->vert_ndp > max_vndp[disp_type]) {
-+ DPRINTK("vert_ndp too big: %d\n", par->vert_ndp);
-+ return -EINVAL;
-+ }
++#ifndef CONFIG_FB_AU1200_DEVS
++#define CONFIG_FB_AU1200_DEVS 4
++#endif
+
-+ if (disp_type != DISP_TYPE_LCD) {
-+ if (par->hsync_start >
-+ max_hsync_start[(par->bpp==16)][disp_type]) {
-+ DPRINTK("hsync_start too big: %d\n",
-+ par->hsync_start);
-+ return -EINVAL;
-+ }
-+ if (par->vsync_start > max_vsync_start[disp_type]) {
-+ DPRINTK("vsync_start too big: %d\n",
-+ par->vsync_start);
-+ return -EINVAL;
-+ }
-+ if (!IS_TV(disp_type)) {
-+ if (par->hsync_width > max_hsync_width[disp_type]) {
-+ DPRINTK("hsync_width too big: %d\n",
-+ par->hsync_width);
-+ return -EINVAL;
-+ }
-+ if (par->vsync_width > max_vsync_width[disp_type]) {
-+ DPRINTK("vsync_width too big: %d\n",
-+ par->vsync_width);
-+ return -EINVAL;
-+ }
-+ }
-+ }
++#define DRIVER_NAME "au1200fb"
++#define DRIVER_DESC "LCD controller driver for AU1200 processors"
+
-+ if (IS_TV(disp_type)) {
-+ int tv_pixclk = (disp_type == DISP_TYPE_NTSC) ?
-+ NTSC_PIXCLOCK : PAL_PIXCLOCK;
-+ if (info->fix.tv_filt & TV_FILT_FLICKER)
-+ tv_pixclk *= 2;
-+
-+ if (par->ipclk.pixclk_d != tv_pixclk) {
-+ DPRINTK("invalid TV pixel clock %u kHz\n",
-+ par->ipclk.pixclk_d);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ if (e1356_calc_pixclock(info, &par->ipclk) < 0) {
-+ DPRINTK("can't set pixel clock %u kHz\n",
-+ par->ipclk.pixclk_d);
-+ return -EINVAL;
-+ }
-+
-+#ifdef E1356FB_VERBOSE_DEBUG
-+ DPRINTK("desired pixclock = %d kHz, actual = %d kHz, error = %d%%\n",
-+ par->ipclk.pixclk_d, par->ipclk.pixclk, par->ipclk.error);
++#define DEBUG 1
++
++#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
++#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
++#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
++
++#if DEBUG
++#define print_dbg(f, arg...) printk(KERN_DEBUG __FILE__ ": " f "\n", ## arg)
++#else
++#define print_dbg(f, arg...) do {} while (0)
+#endif
-+
-+ if (disp_type != DISP_TYPE_LCD) {
-+ if (par->horiz_ndp < par->hsync_start + par->hsync_width) {
-+ DPRINTK("invalid horiz. timing\n");
-+ return -EINVAL;
-+ }
-+ if (par->vert_ndp < par->vsync_start + par->vsync_width) {
-+ DPRINTK("invalid vert. timing\n");
-+ return -EINVAL;
-+ }
+
-+ // SED1356 Hardware Functional Spec, section 13.5
-+ if (disp_type == DISP_TYPE_NTSC &&
-+ ((par->width + par->horiz_ndp != 910) ||
-+ (par->height + 2*par->vert_ndp+1 != 525))) {
-+ DPRINTK("invalid NTSC timing\n");
-+ return -EINVAL;
-+ } else if (disp_type == DISP_TYPE_PAL &&
-+ ((par->width + par->horiz_ndp != 1135) ||
-+ (par->height + 2*par->vert_ndp+1 != 625))) {
-+ DPRINTK("invalid PAL timing\n");
-+ return -EINVAL;
-+ }
-+ }
-+
-+ par->hsync_freq = (1000 * par->ipclk.pixclk) /
-+ (par->width + par->horiz_ndp);
-+ par->vsync_freq = par->hsync_freq / (par->height + par->vert_ndp);
-+
-+ if (par->hsync_freq < 30000 || par->hsync_freq > 90000) {
-+ DPRINTK("hsync freq too %s: %u Hz\n",
-+ par->hsync_freq < 30000 ? "low" : "high",
-+ par->hsync_freq);
-+ return -EINVAL;
-+ }
-+ if (par->vsync_freq < 50 || par->vsync_freq > 110) {
-+ DPRINTK("vsync freq too %s: %u Hz\n",
-+ par->vsync_freq < 50 ? "low" : "high",
-+ par->vsync_freq);
-+ return -EINVAL;
-+ }
+
-+ return 0;
-+}
++#define AU1200_LCD_FB_IOCTL 0x46FF
+
-+static int
-+e1356fb_verify_par(struct e1356fb_par* par,
-+ const struct fb_info_e1356* info)
-+{
-+ int disp_type = info->fix.disp_type;
-+
-+ if (par->bpp != 8 && par->bpp != 16) {
-+ DPRINTK("depth not supported: %u bpp\n", par->bpp);
-+ return -EINVAL;
-+ }
++#define AU1200_LCD_SET_SCREEN 1
++#define AU1200_LCD_GET_SCREEN 2
++#define AU1200_LCD_SET_WINDOW 3
++#define AU1200_LCD_GET_WINDOW 4
++#define AU1200_LCD_SET_PANEL 5
++#define AU1200_LCD_GET_PANEL 6
++
++#define SCREEN_SIZE (1<< 1)
++#define SCREEN_BACKCOLOR (1<< 2)
++#define SCREEN_BRIGHTNESS (1<< 3)
++#define SCREEN_COLORKEY (1<< 4)
++#define SCREEN_MASK (1<< 5)
++typedef struct au1200_lcd_global_regs_t
++{
++ unsigned int flags;
++ unsigned int xsize;
++ unsigned int ysize;
++ unsigned int backcolor;
++ unsigned int brightness;
++ unsigned int colorkey;
++ unsigned int mask;
++ unsigned int panel_choice;
++ char panel_desc[80];
++
++} au1200_lcd_global_regs_t;
++
++#define WIN_POSITION (1<< 0)
++#define WIN_ALPHA_COLOR (1<< 1)
++#define WIN_ALPHA_MODE (1<< 2)
++#define WIN_PRIORITY (1<< 3)
++#define WIN_CHANNEL (1<< 4)
++#define WIN_BUFFER_FORMAT (1<< 5)
++#define WIN_COLOR_ORDER (1<< 6)
++#define WIN_PIXEL_ORDER (1<< 7)
++#define WIN_SIZE (1<< 8)
++#define WIN_COLORKEY_MODE (1<< 9)
++#define WIN_DOUBLE_BUFFER_MODE (1<< 10)
++#define WIN_RAM_ARRAY_MODE (1<< 11)
++#define WIN_BUFFER_SCALE (1<< 12)
++#define WIN_ENABLE (1<< 13)
++
++typedef struct au1200_lcd_window_regs_t
++{
++ unsigned int flags;
++ unsigned int xpos;
++ unsigned int ypos;
++ unsigned int alpha_color;
++ unsigned int alpha_mode;
++ unsigned int priority;
++ unsigned int channel;
++ unsigned int buffer_format;
++ unsigned int color_order;
++ unsigned int pixel_order;
++ unsigned int xsize;
++ unsigned int ysize;
++ unsigned int colorkey_mode;
++ unsigned int double_buffer_mode;
++ unsigned int ram_array_mode;
++ unsigned int xscale;
++ unsigned int yscale;
++ unsigned int enable;
++} au1200_lcd_window_regs_t;
++
++
++typedef struct au1200_lcd_iodata_t
++{
++
++ unsigned int subcmd;
++ au1200_lcd_global_regs_t global;
++ au1200_lcd_window_regs_t window;
+
-+ if (par->width > par->width_virt) {
-+ DPRINTK("virtual x resolution < physical x resolution not possible\n");
-+ return -EINVAL;
-+ }
++} au1200_lcd_iodata_t;
+
-+ if (par->height > par->height_virt) {
-+ DPRINTK("virtual y resolution < physical y resolution not possible\n");
-+ return -EINVAL;
-+ }
++#if defined(__BIG_ENDIAN)
++#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
++#else
++#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
++#endif
++#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
+
-+ if (par->width < 320 || par->width > 1024) {
-+ DPRINTK("width not supported: %u\n", par->width);
-+ return -EINVAL;
-+ }
++/* Private, per-framebuffer management information (independent of the panel itself) */
++struct au1200fb_device {
++ struct fb_info fb_info; /* FB driver info record */
+
-+ if ((disp_type == DISP_TYPE_LCD && (par->width % 16)) ||
-+ (disp_type == DISP_TYPE_TFT && (par->width % 8))) {
-+ DPRINTK("invalid width for panel type: %u\n", par->width);
-+ return -EINVAL;
-+ }
++ int plane;
++ unsigned char* fb_mem; /* FrameBuffer memory map */
++ unsigned int fb_len;
++ dma_addr_t fb_phys;
++};
+
-+ if (par->height < 200 || par->height > 1024) {
-+ DPRINTK("height not supported: %u\n", par->height);
-+ return -EINVAL;
-+ }
++static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS];
++/********************************************************************/
+
-+ if (par->width_virt * par->height_virt * par->Bpp >
-+ info->fb_size) {
-+ DPRINTK("not enough memory for virtual screen (%ux%ux%u)\n",
-+ par->width_virt, par->height_virt, par->bpp);
-+ return -EINVAL;
-+ }
++/* LCD controller restrictions */
++#define AU1200_LCD_MAX_XRES 1280
++#define AU1200_LCD_MAX_YRES 1024
++#define AU1200_LCD_MAX_BPP 32
++#define AU1200_LCD_MAX_CLK 96000000 /* fixme: this needs to go away ? */
++#define AU1200_LCD_NBR_PALETTE_ENTRIES 256
+
-+ return e1356fb_verify_timing(par, info);
-+}
++/* Default number of visible screen buffer to allocate */
++#define AU1200FB_NBR_VIDEO_BUFFERS 1
+
++/********************************************************************/
+
-+static int
-+e1356fb_var_to_par(const struct fb_var_screeninfo* var,
-+ struct e1356fb_par* par,
-+ const struct fb_info_e1356* info)
-+{
-+ if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
-+ DPRINTK("interlace not supported\n");
-+ return -EINVAL;
-+ }
++AU1200_LCD *lcd = (AU1200_LCD *)AU1200_LCD_ADDR;
++static int window_index = 2; /* default is zero */
++static int panel_index = 2; /* default is zero */
++static struct window_settings *win;
++static struct panel_settings *panel;
++static int noblanking = 1;
++static int nohwcursor = 0;
++
++struct window_settings
++{
++ unsigned char name[64];
++ uint32 mode_backcolor;
++ uint32 mode_colorkey;
++ uint32 mode_colorkeymsk;
++ struct
++ {
++ int xres;
++ int yres;
++ int xpos;
++ int ypos;
++ uint32 mode_winctrl1; /* winctrl1[FRM,CCO,PO,PIPE] */
++ uint32 mode_winenable;
++ } w[4];
++};
+
-+ memset(par, 0, sizeof(struct e1356fb_par));
++#if defined(__BIG_ENDIAN)
++#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_00
++#else
++#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
++#endif
+
-+ par->width = (var->xres + 15) & ~15; /* could sometimes be 8 */
-+ par->width_virt = var->xres_virtual;
-+ par->height = var->yres;
-+ par->height_virt = var->yres_virtual;
-+ par->bpp = var->bits_per_pixel;
-+ par->Bpp = (par->bpp + 7) >> 3;
++extern int board_au1200fb_panel_init (void);
++extern int board_au1200fb_panel_shutdown (void);
+
-+ par->ipclk.pixclk_d = PICOS2KHZ(var->pixclock);
++#ifdef CONFIG_PM
++int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
++ au1xxx_request_t request, void *data);
++au1xxx_power_dev_t *LCD_pm_dev;
++#endif
+
-+ par->hsync_start = var->right_margin;
-+ par->hsync_width = var->hsync_len;
++/*
++ * Default window configurations
++ */
++static struct window_settings windows[] =
++{
++ { /* Index 0 */
++ "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
++ /* mode_backcolor */ 0x006600ff,
++ /* mode_colorkey,msk*/ 0, 0,
++ {
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP,
++ /* mode_winenable*/ LCD_WINENABLE_WEN0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 100, 100, 100, 100,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP |
++ LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ LCD_WINENABLE_WEN1,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP,
++ /* mode_winenable*/ 0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP |
++ LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ 0,
++ },
++ },
++ },
+
-+ par->vsync_start = var->lower_margin;
-+ par->vsync_width = var->vsync_len;
++ { /* Index 1 */
++ "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
++ /* mode_backcolor */ 0x006600ff,
++ /* mode_colorkey,msk*/ 0, 0,
++ {
++ {
++ /* xres, yres, xpos, ypos */ 320, 240, 5, 5,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_24BPP |
++ LCD_WINCTRL1_PO_00,
++ /* mode_winenable*/ LCD_WINENABLE_WEN0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565
++ | LCD_WINCTRL1_PO_16BPP,
++ /* mode_winenable*/ 0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 100, 100, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP |
++ LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 200, 25, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP |
++ LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ 0,
++ },
++ },
++ },
++ { /* Index 2 */
++ "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
++ /* mode_backcolor */ 0x006600ff,
++ /* mode_colorkey,msk*/ 0, 0,
++ {
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP,
++ /* mode_winenable*/ LCD_WINENABLE_WEN0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP,
++ /* mode_winenable*/ 0,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_32BPP |
++ LCD_WINCTRL1_PO_00|LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
++ },
++ {
++ /* xres, yres, xpos, ypos */ 0, 0, 0, 0,
++ /* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
++ LCD_WINCTRL1_PO_16BPP |
++ LCD_WINCTRL1_PIPE,
++ /* mode_winenable*/ 0,
++ },
++ },
++ },
++ /* Need VGA 640 @ 24bpp, @ 32bpp */
++ /* Need VGA 800 @ 24bpp, @ 32bpp */
++ /* Need VGA 1024 @ 24bpp, @ 32bpp */
++} ;
+
-+ par->horiz_ndp = var->left_margin + var->right_margin + var->hsync_len;
-+ par->vert_ndp = var->upper_margin + var->lower_margin + var->vsync_len;
++/*
++ * Controller configurations for various panels.
++ */
+
-+ par->hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 1 : 0;
-+ par->vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 1 : 0;
++struct panel_settings
++{
++ const char name[25]; /* Full name <vendor>_<model> */
+
-+ par->cmap_len = (par->bpp == 8) ? 256 : 16;
++ struct fb_monspecs monspecs; /* FB monitor specs */
+
-+ return e1356fb_verify_par(par, info);
-+}
++ /* panel timings */
++ uint32 mode_screen;
++ uint32 mode_horztiming;
++ uint32 mode_verttiming;
++ uint32 mode_clkcontrol;
++ uint32 mode_pwmdiv;
++ uint32 mode_pwmhi;
++ uint32 mode_outmask;
++ uint32 mode_fifoctrl;
++ uint32 mode_toyclksrc;
++ uint32 mode_backlight;
++ uint32 mode_auxpll;
++ int (*device_init)(void);
++ int (*device_shutdown)(void);
++#define Xres min_xres
++#define Yres min_yres
++ u32 min_xres; /* Minimum horizontal resolution */
++ u32 max_xres; /* Maximum horizontal resolution */
++ u32 min_yres; /* Minimum vertical resolution */
++ u32 max_yres; /* Maximum vertical resolution */
++};
+
-+static int
-+e1356fb_par_to_var(struct fb_var_screeninfo* var,
-+ struct e1356fb_par* par,
-+ const struct fb_info_e1356* info)
++/********************************************************************/
++/* fixme: Maybe a modedb for the CRT ? otherwise panels should be as-is */
++
++/* List of panels known to work with the AU1200 LCD controller.
++ * To add a new panel, enter the same specifications as the
++ * Generic_TFT one, and MAKE SURE that it doesn't conflicts
++ * with the controller restrictions. Restrictions are:
++ *
++ * STN color panels: max_bpp <= 12
++ * STN mono panels: max_bpp <= 4
++ * TFT panels: max_bpp <= 16
++ * max_xres <= 800
++ * max_yres <= 600
++ */
++static struct panel_settings known_lcd_panels[] =
+{
-+ struct fb_var_screeninfo v;
-+ int ret;
-+
-+ // First, make sure par is valid.
-+ if ((ret = e1356fb_verify_par(par, info)))
-+ return ret;
++ [0] = { /* QVGA 320x240 H:33.3kHz V:110Hz */
++ .name = "QVGA_320x240",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = LCD_SCREEN_SX_N(320) |
++ LCD_SCREEN_SY_N(240),
++ .mode_horztiming = 0x00c4623b,
++ .mode_verttiming = 0x00502814,
++ .mode_clkcontrol = 0x00020002, /* /4=24Mhz */
++ .mode_pwmdiv = 0x00000000,
++ .mode_pwmhi = 0x00000000,
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = NULL,
++ .device_shutdown = NULL,
++ 320, 320,
++ 240, 240,
++ },
+
-+ memset(&v, 0, sizeof(struct fb_var_screeninfo));
-+ v.xres_virtual = par->width_virt;
-+ v.yres_virtual = par->height_virt;
-+ v.xres = par->width;
-+ v.yres = par->height;
-+ v.right_margin = par->hsync_start;
-+ v.hsync_len = par->hsync_width;
-+ v.left_margin = par->horiz_ndp - par->hsync_start - par->hsync_width;
-+ v.lower_margin = par->vsync_start;
-+ v.vsync_len = par->vsync_width;
-+ v.upper_margin = par->vert_ndp - par->vsync_start - par->vsync_width;
-+ v.bits_per_pixel = par->bpp;
-+
-+ switch(par->bpp) {
-+ case 8:
-+ v.red.offset = v.green.offset = v.blue.offset = 0;
-+ v.red.length = v.green.length = v.blue.length = 4;
-+ break;
-+ case 16:
-+ v.red.offset = 11;
-+ v.red.length = 5;
-+ v.green.offset = 5;
-+ v.green.length = 6;
-+ v.blue.offset = 0;
-+ v.blue.length = 5;
-+ break;
-+ }
++ [1] = { /* VGA 640x480 H:30.3kHz V:58Hz */
++ .name = "VGA_640x480",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = 0x13f9df80,
++ .mode_horztiming = 0x003c5859,
++ .mode_verttiming = 0x00741201,
++ .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
++ .mode_pwmdiv = 0x00000000,
++ .mode_pwmhi = 0x00000000,
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = NULL,
++ .device_shutdown = NULL,
++ 640, 480,
++ 640, 480,
++ },
+
-+ v.height = v.width = -1;
-+ v.pixclock = KHZ2PICOS(par->ipclk.pixclk);
++ [2] = { /* SVGA 800x600 H:46.1kHz V:69Hz */
++ .name = "SVGA_800x600",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = 0x18fa5780,
++ .mode_horztiming = 0x00dc7e77,
++ .mode_verttiming = 0x00584805,
++ .mode_clkcontrol = 0x00020000, /* /2=48Mhz */
++ .mode_pwmdiv = 0x00000000,
++ .mode_pwmhi = 0x00000000,
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = NULL,
++ .device_shutdown = NULL,
++ 800, 800,
++ 600, 600,
++ },
+
-+ if (par->hsync_pol)
-+ v.sync |= FB_SYNC_HOR_HIGH_ACT;
-+ if (par->vsync_pol)
-+ v.sync |= FB_SYNC_VERT_HIGH_ACT;
++ [3] = { /* XVGA 1024x768 H:56.2kHz V:70Hz */
++ .name = "XVGA_1024x768",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = 0x1ffaff80,
++ .mode_horztiming = 0x007d0e57,
++ .mode_verttiming = 0x00740a01,
++ .mode_clkcontrol = 0x000A0000, /* /1 */
++ .mode_pwmdiv = 0x00000000,
++ .mode_pwmhi = 0x00000000,
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 6, /* 72MHz AUXPLL */
++ .device_init = NULL,
++ .device_shutdown = NULL,
++ 1024, 1024,
++ 768, 768,
++ },
+
-+ *var = v;
-+ return 0;
-+}
++ [4] = { /* XVGA XVGA 1280x1024 H:68.5kHz V:65Hz */
++ .name = "XVGA_1280x1024",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = 0x27fbff80,
++ .mode_horztiming = 0x00cdb2c7,
++ .mode_verttiming = 0x00600002,
++ .mode_clkcontrol = 0x000A0000, /* /1 */
++ .mode_pwmdiv = 0x00000000,
++ .mode_pwmhi = 0x00000000,
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 10, /* 120MHz AUXPLL */
++ .device_init = NULL,
++ .device_shutdown = NULL,
++ 1280, 1280,
++ 1024, 1024,
++ },
+
-+static int
-+e1356fb_encode_fix(struct fb_fix_screeninfo* fix,
-+ const struct e1356fb_par* par,
-+ const struct fb_info_e1356* info)
-+{
-+ memset(fix, 0, sizeof(struct fb_fix_screeninfo));
-+
-+ strcpy(fix->id, "Epson SED1356");
-+ fix->smem_start = info->fix.membase_phys;
-+ fix->smem_len = info->fb_size;
-+ fix->mmio_start = info->fix.regbase_phys;
-+ fix->mmio_len = info->regbase_size;
-+ fix->accel = FB_ACCEL_EPSON_SED1356;
-+ fix->type = FB_TYPE_PACKED_PIXELS;
-+ fix->type_aux = 0;
-+ fix->line_length = par->width_virt * par->Bpp;
-+ fix->visual =
-+ (par->bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
-+
-+ fix->xpanstep = info->fix.nopan ? 0 : 1;
-+ fix->ypanstep = info->fix.nopan ? 0 : 1;
-+ fix->ywrapstep = 0;
-+
-+ return 0;
-+}
++ [5] = { /* Samsung 1024x768 TFT */
++ .name = "Samsung_1024x768_TFT",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = 0x1ffaff80,
++ .mode_horztiming = 0x018cc677,
++ .mode_verttiming = 0x00241217,
++ .mode_clkcontrol = 0x00000000, /* SCB 0x1 /4=24Mhz */
++ .mode_pwmdiv = 0x8000063f, /* SCB 0x0 */
++ .mode_pwmhi = 0x03400000, /* SCB 0x0 */
++ .mode_outmask = 0x00FFFFFF,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = board_au1200fb_panel_init,
++ .device_shutdown = board_au1200fb_panel_shutdown,
++ 1024, 1024,
++ 768, 768,
++ },
+
-+static int e1356fb_open(struct fb_info *fb, int user)
-+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ if (user) {
-+ info->open++;
-+ }
++ [6] = { /* Toshiba 640x480 TFT */
++ .name = "Toshiba_640x480_TFT",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = LCD_SCREEN_SX_N(640) |
++ LCD_SCREEN_SY_N(480),
++ .mode_horztiming = LCD_HORZTIMING_HPW_N(96) |
++ LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(51),
++ .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
++ LCD_VERTTIMING_VND1_N(11) | LCD_VERTTIMING_VND2_N(32),
++ .mode_clkcontrol = 0x00000000, /* /4=24Mhz */
++ .mode_pwmdiv = 0x8000063f,
++ .mode_pwmhi = 0x03400000,
++ .mode_outmask = 0x00fcfcfc,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = board_au1200fb_panel_init,
++ .device_shutdown = board_au1200fb_panel_shutdown,
++ 640, 480,
++ 640, 480,
++ },
++
++ [7] = { /* Sharp 320x240 TFT */
++ .name = "Sharp_320x240_TFT",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 12500,
++ .hfmax = 20000,
++ .vfmin = 38,
++ .vfmax = 81,
++ .dclkmin = 4500000,
++ .dclkmax = 6800000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = LCD_SCREEN_SX_N(320) |
++ LCD_SCREEN_SY_N(240),
++ .mode_horztiming = LCD_HORZTIMING_HPW_N(60) |
++ LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2),
++ .mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
++ LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5),
++ .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(7), /*16=6Mhz*/
++ .mode_pwmdiv = 0x8000063f,
++ .mode_pwmhi = 0x03400000,
++ .mode_outmask = 0x00fcfcfc,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = board_au1200fb_panel_init,
++ .device_shutdown = board_au1200fb_panel_shutdown,
++ 320, 320,
++ 240, 240,
++ },
+
-+ return 0;
-+}
++ [8] = { /* Toppoly TD070WGCB2 7" 856x480 TFT */
++ .name = "Toppoly_TD070WGCB2",
++ .monspecs = {
++ .modedb = NULL,
++ .modedb_len = 0,
++ .hfmin = 30000,
++ .hfmax = 70000,
++ .vfmin = 60,
++ .vfmax = 60,
++ .dclkmin = 6000000,
++ .dclkmax = 28000000,
++ .input = FB_DISP_RGB,
++ },
++ .mode_screen = LCD_SCREEN_SX_N(856) |
++ LCD_SCREEN_SY_N(480),
++ .mode_horztiming = LCD_HORZTIMING_HND2_N(43) |
++ LCD_HORZTIMING_HND1_N(43) | LCD_HORZTIMING_HPW_N(114),
++ .mode_verttiming = LCD_VERTTIMING_VND2_N(20) |
++ LCD_VERTTIMING_VND1_N(21) | LCD_VERTTIMING_VPW_N(4),
++ .mode_clkcontrol = 0x00020001, /* /4=24Mhz */
++ .mode_pwmdiv = 0x8000063f,
++ .mode_pwmhi = 0x03400000,
++ .mode_outmask = 0x00fcfcfc,
++ .mode_fifoctrl = 0x2f2f2f2f,
++ .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
++ .mode_backlight = 0x00000000,
++ .mode_auxpll = 8, /* 96MHz AUXPLL */
++ .device_init = board_au1200fb_panel_init,
++ .device_shutdown = board_au1200fb_panel_shutdown,
++ 856, 856,
++ 480, 480,
++ },
++};
+
-+static int e1356fb_release(struct fb_info *fb, int user)
-+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ if (user && info->open) {
-+ info->open--;
-+ if (info->open == 0)
-+ info->mmaped = 0;
-+ }
++#define NUM_PANELS (sizeof(known_lcd_panels) / sizeof(struct panel_settings))
+
-+ return 0;
-+}
++/********************************************************************/
+
-+static int
-+e1356fb_get_fix(struct fb_fix_screeninfo *fix,
-+ int con,
-+ struct fb_info *fb)
++static int set_brightness(unsigned int brightness)
+{
-+ const struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ struct e1356fb_par par;
++ unsigned int hi1, divider;
+
-+ //DPRINTK("\n");
++ /* limit brightness pwm duty to >= 30/1600 */
++ if (brightness < 30) {
++ brightness = 30;
++ }
++ divider = (lcd->pwmdiv & 0x3FFFF) + 1;
++ hi1 = (lcd->pwmhi >> 16) + 1;
++ hi1 = (((brightness & 0xFF)+1) * divider >> 8);
++ lcd->pwmhi &= 0xFFFF;
++ lcd->pwmhi |= (hi1 << 16);
+
-+ if (con == -1)
-+ par = info->current_par;
-+ else
-+ e1356fb_var_to_par(&fb_display[con].var, &par, info);
-+ e1356fb_encode_fix(fix, &par, info);
-+ return 0;
++ return brightness;
+}
+
+static int
-+e1356fb_get_var(struct fb_var_screeninfo *var,
-+ int con,
-+ struct fb_info *fb)
++winbpp (unsigned int winctrl1)
+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+
-+ //DPRINTK("\n");
-+
-+ if (con == -1)
-+ e1356fb_par_to_var(var, &info->current_par, info);
-+ else
-+ *var = fb_display[con].var;
-+ return 0;
-+}
-+
-+static void
-+e1356fb_set_dispsw(struct display *disp,
-+ struct fb_info_e1356 *info,
-+ int bpp,
-+ int accel)
-+{
-+ struct e1356fb_fix* fix = &info->fix;
-+ //DPRINTK("\n");
-+
-+ if (disp->dispsw && disp->conp)
-+ fb_con.con_cursor(disp->conp, CM_ERASE);
-+ switch (bpp) {
-+#ifdef FBCON_HAS_CFB8
-+ case 8:
-+ disp->dispsw = fix->noaccel ? &fbcon_cfb8 : &fbcon_e1356_8;
-+ if (fix->nohwcursor)
-+ fbcon_e1356_8.cursor = NULL;
-+ break;
-+#endif
-+#ifdef FBCON_HAS_CFB16
-+ case 16:
-+ disp->dispsw = fix->noaccel ? &fbcon_cfb16 : &fbcon_e1356_16;
-+ disp->dispsw_data = info->fbcon_cmap16;
-+ if (fix->nohwcursor)
-+ fbcon_e1356_16.cursor = NULL;
-+ break;
-+#endif
-+ default:
-+ disp->dispsw = &fbcon_dummy;
++ /* how many bits are needed for each pixel format */
++ switch (winctrl1 & LCD_WINCTRL1_FRM)
++ {
++ case LCD_WINCTRL1_FRM_1BPP: return 1; break;
++ case LCD_WINCTRL1_FRM_2BPP: return 2; break;
++ case LCD_WINCTRL1_FRM_4BPP: return 4; break;
++ case LCD_WINCTRL1_FRM_8BPP: return 8; break;
++ case LCD_WINCTRL1_FRM_12BPP: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPP655: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPP565: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPP556: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPPI1555: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPPI5551: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPPA1555: return 16; break;
++ case LCD_WINCTRL1_FRM_16BPPA5551: return 16; break;
++ case LCD_WINCTRL1_FRM_24BPP: return 32; break;
++ case LCD_WINCTRL1_FRM_32BPP: return 32; break;
++ default: return 0; break;
+ }
-+
+}
+
+static int
-+e1356fb_set_var(struct fb_var_screeninfo *var,
-+ int con,
-+ struct fb_info *fb)
-+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ struct e1356fb_par par;
-+ struct display *display;
-+ int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel, err;
-+ int activate = var->activate;
-+ int j,k;
-+
-+ DPRINTK("\n");
-+
-+ if (con >= 0)
-+ display = &fb_display[con];
-+ else
-+ display = fb->disp; /* used during initialization */
-+
-+ if ((err = e1356fb_var_to_par(var, &par, info))) {
-+ struct fb_videomode *dm;
-+ /*
-+ * this mode didn't pass the tests. Try the
-+ * corresponding mode from our own modedb.
-+ */
-+ DPRINTK("req mode failed, trying SED1356 %dx%d mode\n",
-+ var->xres, var->yres);
-+ if (e1356fb_get_mode(info, var->xres,
-+ var->yres, NULL, &dm) < 0) {
-+ DPRINTK("no SED1356 %dx%d mode found, failed\n",
-+ var->xres, var->yres);
-+ return err;
-+ }
-+ fb_videomode_to_var(dm, var);
-+ if ((err = e1356fb_var_to_par(var, &par, info))) {
-+ DPRINTK("SED1356 %dx%d mode failed\n",
-+ var->xres, var->yres);
-+ return err;
-+ }
-+ }
-+
-+ if (info->fix.tv_filt & TV_FILT_FLICKER)
-+ printk("e1356fb: TV flicker filter enabled\n");
-+
-+ e1356fb_par_to_var(var, &par, info);
-+
-+ if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
-+ oldxres = display->var.xres;
-+ oldyres = display->var.yres;
-+ oldvxres = display->var.xres_virtual;
-+ oldvyres = display->var.yres_virtual;
-+ oldbpp = display->var.bits_per_pixel;
-+ oldaccel = display->var.accel_flags;
-+ display->var = *var;
-+ if (con < 0 ||
-+ oldxres != var->xres ||
-+ oldyres != var->yres ||
-+ oldvxres != var->xres_virtual ||
-+ oldvyres != var->yres_virtual ||
-+ oldbpp != var->bits_per_pixel ||
-+ oldaccel != var->accel_flags) {
-+ struct fb_fix_screeninfo fix;
-+
-+ e1356fb_encode_fix(&fix, &par, info);
-+ display->screen_base = info->membase_virt;
-+ display->visual = fix.visual;
-+ display->type = fix.type;
-+ display->type_aux = fix.type_aux;
-+ display->ypanstep = fix.ypanstep;
-+ display->ywrapstep = fix.ywrapstep;
-+ display->line_length = fix.line_length;
-+ display->next_line = fix.line_length;
-+ display->can_soft_blank = 1;
-+ display->inverse = 0;
-+ accel = var->accel_flags & FB_ACCELF_TEXT;
-+ e1356fb_set_dispsw(display, info, par.bpp, accel);
-+
-+ if (info->fix.nopan)
-+ display->scrollmode = SCROLL_YREDRAW;
-+
-+ if (info->fb_info.changevar)
-+ (*info->fb_info.changevar)(con);
-+ }
-+ if (var->bits_per_pixel==8)
-+ for(j = 0; j < 16; j++) {
-+ k = color_table[j];
-+ fb_info.palette[j].red = default_red[k];
-+ fb_info.palette[j].green = default_grn[k];
-+ fb_info.palette[j].blue = default_blu[k];
-+ }
-+
-+ del_timer(&(info->cursor.timer));
-+ fb_info.cursor.state=CM_ERASE;
-+
-+ if (!info->fb_info.display_fg ||
-+ info->fb_info.display_fg->vc_num == con || con < 0)
-+ e1356fb_set_par(&par, info);
-+
-+ if (!info->fix.nohwcursor)
-+ if (display && display->conp)
-+ e1356fb_createcursor( display );
-+ info->cursor.redraw = 1;
-+
-+ if (oldbpp != var->bits_per_pixel || con < 0) {
-+ if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
-+ return err;
-+ e1356fb_install_cmap(display, &(info->fb_info));
-+ }
++fbinfo2index (struct fb_info *fb_info)
++{
++ int i;
++ for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i)
++ {
++ if (fb_info == (struct fb_info *)(&_au1200fb_devices[i].fb_info))
++ return i;
+ }
-+
-+ return 0;
++ printk("au1200fb: ERROR: fbinfo2index failed!\n");
++ return -1;
+}
+
-+static int
-+e1356fb_pan_display(struct fb_var_screeninfo* var,
-+ int con,
-+ struct fb_info* fb)
++static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, int xpos, int ypos)
+{
-+ struct fb_info_e1356* info = (struct fb_info_e1356*)fb;
-+ struct e1356fb_par* par = &info->current_par;
-+
-+ //DPRINTK("\n");
-+
-+ if (info->fix.nopan)
-+ return -EINVAL;
++ uint32 winctrl0, winctrl1, winenable, fb_offset = 0;
++ int xsz, ysz;
+
-+ if ((int)var->xoffset < 0 ||
-+ var->xoffset + par->width > par->width_virt ||
-+ (int)var->yoffset < 0 ||
-+ var->yoffset + par->height > par->height_virt)
-+ return -EINVAL;
-+
-+ if (con == currcon)
-+ do_pan_var(var, info);
-+
-+ fb_display[con].var.xoffset = var->xoffset;
-+ fb_display[con].var.yoffset = var->yoffset;
-+
-+ return 0;
-+}
-+
-+static int
-+e1356fb_get_cmap(struct fb_cmap *cmap,
-+ int kspc,
-+ int con,
-+ struct fb_info *fb)
-+{
-+ struct fb_info_e1356* info = (struct fb_info_e1356*)fb;
-+ struct display *d = (con<0) ? fb->disp : fb_display + con;
-+
-+ //DPRINTK("\n");
++ /* FIX!!! NOT CHECKING FOR COMPLETE OFFSCREEN YET */
+
-+ if (con == currcon) {
-+ /* current console? */
-+ return fb_get_cmap(cmap, kspc, e1356fb_getcolreg, fb);
-+ } else if (d->cmap.len) {
-+ /* non default colormap? */
-+ fb_copy_cmap(&d->cmap, cmap, kspc ? 0 : 2);
-+ } else {
-+ fb_copy_cmap(fb_default_cmap(info->current_par.cmap_len),
-+ cmap, kspc ? 0 : 2);
++ winctrl0 = lcd->window[plane].winctrl0;
++ winctrl1 = lcd->window[plane].winctrl1;
++ winctrl0 &= (LCD_WINCTRL0_A | LCD_WINCTRL0_AEN);
++ winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY);
++
++ /* Check for off-screen adjustments */
++ xsz = win->w[plane].xres;
++ ysz = win->w[plane].yres;
++ if ((xpos + win->w[plane].xres) > panel->Xres)
++ {
++ /* Off-screen to the right */
++ xsz = panel->Xres - xpos; /* off by 1 ??? */
++ /*printk("off screen right\n");*/
+ }
-+ return 0;
-+}
+
-+static int
-+e1356fb_set_cmap(struct fb_cmap *cmap,
-+ int kspc,
-+ int con,
-+ struct fb_info *fb)
-+{
-+ struct display *d = (con<0) ? fb->disp : fb_display + con;
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ int cmap_len = (info->current_par.bpp == 8) ? 256 : 16;
-+
-+ //DPRINTK("\n");
-+
-+ if (d->cmap.len!=cmap_len) {
-+ int err;
-+ if ((err = fb_alloc_cmap(&d->cmap, cmap_len, 0)))
-+ return err;
++ if ((ypos + win->w[plane].yres) > panel->Yres)
++ {
++ /* Off-screen to the bottom */
++ ysz = panel->Yres - ypos; /* off by 1 ??? */
++ /*printk("off screen bottom\n");*/
+ }
-+
-+ if (con == currcon) {
-+ /* current console? */
-+ return fb_set_cmap(cmap, kspc, e1356fb_setcolreg, fb);
-+ } else {
-+ fb_copy_cmap(cmap, &d->cmap, kspc ? 0 : 1);
++
++ if (xpos < 0)
++ {
++ /* Off-screen to the left */
++ xsz = win->w[plane].xres + xpos;
++ fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8);
++ xpos = 0;
++ /*printk("off screen left\n");*/
+ }
++
++ if (ypos < 0)
++ {
++ /* Off-screen to the top */
++ ysz = win->w[plane].yres + ypos;
++ /* fixme: fb_offset += ((0-ypos)*fb_pars[plane].line_length); */
++ ypos = 0;
++ /*printk("off screen top\n");*/
++ }
++
++ /* record settings */
++ win->w[plane].xpos = xpos;
++ win->w[plane].ypos = ypos;
++
++ xsz -= 1;
++ ysz -= 1;
++ winctrl0 |= (xpos << 21);
++ winctrl0 |= (ypos << 10);
++ winctrl1 |= (xsz << 11);
++ winctrl1 |= (ysz << 0);
++
++ /* Disable the window while making changes, then restore WINEN */
++ winenable = lcd->winenable & (1 << plane);
++ au_sync();
++ lcd->winenable &= ~(1 << plane);
++ lcd->window[plane].winctrl0 = winctrl0;
++ lcd->window[plane].winctrl1 = winctrl1;
++ lcd->window[plane].winbuf0 =
++ lcd->window[plane].winbuf1 = fbdev->fb_phys;
++ lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
++ lcd->winenable |= winenable;
++ au_sync();
++
+ return 0;
+}
+
-+static int
-+e1356fb_mmap(struct fb_info *fb,
-+ struct file *file,
-+ struct vm_area_struct *vma)
++static void au1200_setpanel (struct panel_settings *newpanel)
+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ unsigned int len;
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
-+ u64 start=0, off;
-+#else
-+ unsigned long start=0, off;
-+#endif
++ /*
++ * Perform global setup/init of LCD controller
++ */
++ uint32 winenable;
+
-+ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
-+ DPRINTK("invalid vma->vm_pgoff\n");
-+ return -EINVAL;
-+ }
-+
-+#ifdef SHADOW_FRAME_BUFFER
-+ if (!info->shadow.fb) {
-+ int order = 0;
-+ while (info->fb_size > (PAGE_SIZE * (1 << order)))
-+ order++;
-+ info->shadow.fb = (void*)__get_free_pages(GFP_KERNEL, order);
-+ if (!info->shadow.fb) {
-+ DPRINTK("shadow fb alloc failed\n");
-+ return -ENXIO;
++ /* Make sure all windows disabled */
++ winenable = lcd->winenable;
++ lcd->winenable = 0;
++ au_sync();
++ /*
++ * Ensure everything is disabled before reconfiguring
++ */
++ if (lcd->screen & LCD_SCREEN_SEN)
++ {
++ /* Wait for vertical sync period */
++ lcd->intstatus = LCD_INT_SS;
++ while ((lcd->intstatus & LCD_INT_SS) == 0) {
++ au_sync();
++ }
++
++ lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
++
++ do
++ {
++ lcd->intstatus = lcd->intstatus; /*clear interrupts*/
++ au_sync();
+ }
-+ memset(info->shadow.fb, 0, info->fb_size);
-+ init_timer(&info->shadow.timer);
-+ info->shadow.timer.function = do_write_shadow_fb;
-+ info->shadow.timer.data = (unsigned long)info;
++ /*wait for controller to shut down*/
++ while ((lcd->intstatus & LCD_INT_SD) == 0);
++
++ /* Call shutdown of current panel (if up) */
++ /* this must occur last, because if an external clock is driving
++ the controller, the clock cannot be turned off before first
++ shutting down the controller.
++ */
++ if (panel->device_shutdown != NULL) panel->device_shutdown();
+ }
-+ mod_timer(&info->shadow.timer, jiffies+HZ/2);
-+ start = virt_to_phys(info->shadow.fb) & PAGE_MASK;
-+#else
-+ start = info->fix.membase_phys & PAGE_MASK;
-+#endif
+
-+ len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fb_size);
++ /* Newpanel == NULL indicates a shutdown operation only */
++ if (newpanel == NULL)
++ return;
+
-+ off = vma->vm_pgoff << PAGE_SHIFT;
-+
-+ if ((vma->vm_end - vma->vm_start + off) > len) {
-+ DPRINTK("invalid vma\n");
-+ return -EINVAL;
++ panel = newpanel;
++
++ printk("Panel(%s), %dx%d\n", panel->name, panel->Xres, panel->Yres);
++
++ /*
++ * Setup clocking if internal LCD clock source (assumes sys_auxpll valid)
++ */
++ if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
++ {
++ uint32 sys_clksrc;
++ au_writel(panel->mode_auxpll, SYS_AUXPLL);
++ sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f;
++ sys_clksrc |= panel->mode_toyclksrc;
++ au_writel(sys_clksrc, SYS_CLKSRC);
+ }
+
-+ off += start;
-+ vma->vm_pgoff = off >> PAGE_SHIFT;
++ /*
++ * Configure panel timings
++ */
++ lcd->screen = panel->mode_screen;
++ lcd->horztiming = panel->mode_horztiming;
++ lcd->verttiming = panel->mode_verttiming;
++ lcd->clkcontrol = panel->mode_clkcontrol;
++ lcd->pwmdiv = panel->mode_pwmdiv;
++ lcd->pwmhi = panel->mode_pwmhi;
++ lcd->outmask = panel->mode_outmask;
++ lcd->fifoctrl = panel->mode_fifoctrl;
++ au_sync();
+
-+ pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
-+#ifdef SHADOW_FRAME_BUFFER
-+ vma->vm_flags |= VM_RESERVED;
-+ pgprot_val(vma->vm_page_prot) &= ~_CACHE_UNCACHED;
-+#else
-+ pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED;
++ /* fixme: Check window settings to make sure still valid
++ * for new geometry */
++#if 0
++ au1200_setlocation(fbdev, 0, win->w[0].xpos, win->w[0].ypos);
++ au1200_setlocation(fbdev, 1, win->w[1].xpos, win->w[1].ypos);
++ au1200_setlocation(fbdev, 2, win->w[2].xpos, win->w[2].ypos);
++ au1200_setlocation(fbdev, 3, win->w[3].xpos, win->w[3].ypos);
+#endif
++ lcd->winenable = winenable;
+
-+ /* This is an IO map - tell maydump to skip this VMA */
-+ vma->vm_flags |= VM_IO;
-+ // FIXME: shouldn't have to do this. If the pages are marked writeable,
-+ // the TLB fault handlers should set these.
-+ pgprot_val(vma->vm_page_prot) |= (_PAGE_DIRTY | _PAGE_VALID);
-+
+ /*
-+ * The SED1356 has only a 16-bit wide data bus, and some
-+ * embedded platforms, such as the Pb1000, do not automatically
-+ * split 32-bit word accesses to the framebuffer into
-+ * seperate half-word accesses. Hence the upper half-word
-+ * never gets to the framebuffer. The following solution is
-+ * to intentionally return a non-32-bit-aligned VA. As long
-+ * as the user app assumes (and doesn't check) that the returned
-+ * VA is 32-bit aligned, all (assumed aligned) 32-bit accesses
-+ * will actually be unaligned and will get trapped by the MIPS
-+ * unaligned exception handler. This handler will emulate the
-+ * load/store instructions by splitting up the load/store
-+ * into two 16-bit load/stores. (This emulation is currently
-+ * enabled by default, but may be disabled in the future, when
-+ * alignment problems in user-level programs get fixed. When
-+ * that happens, this solution won't work anymore, unless the
-+ * process that mmap's the fb also calls sysmips(MIPS_FIXADE, 1),
-+ * which turns address-error emulation back on).
-+ *
-+ * Furthermore, this solution only seems to work for TinyX
-+ * (Xfbdev). Others, like Qt/E, do snoop the returned VA
-+ * and compensate, or do originally unaligned 32-bit accesses
-+ * which then become aligned, hence breaking this solution.
++ * Re-enable screen now that it is configured
+ */
-+ if (info->fix.mmunalign)
-+ vma->vm_start += 2;
-+
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
-+ if (e1356_remap_page_range(vma->vm_start, off,
-+ vma->vm_end - vma->vm_start,
-+ vma->vm_page_prot))
-+ return -EAGAIN;
-+#else
-+ if (io_remap_page_range(vma->vm_start, off,
-+ vma->vm_end - vma->vm_start,
-+ vma->vm_page_prot))
-+ return -EAGAIN;
-+#endif
-+
-+ info->mmaped = 1;
-+ return 0;
-+}
-+
++ lcd->screen |= LCD_SCREEN_SEN;
++ au_sync();
+
-+int __init
-+e1356fb_init(void)
-+{
-+ struct fb_var_screeninfo var;
-+ struct e1356fb_fix * epfix = &fb_info.fix;
-+ e1356_reg_t* reg;
-+ void* regbase;
-+ char* name = "SED1356";
-+ int periodMCLK, periodBCLK;
-+ int dram_timing, rr_div, mclk_src;
-+ u8 rev_code, btmp, mclk_cfg;
++ /* Call init of panel */
++ if (panel->device_init != NULL) panel->device_init();
+
-+ if (options) {
-+ e1356fb_setup(options, 0);
-+ }
++ /* FIX!!!! not appropriate on panel change!!! Global setup/init */
++ lcd->intenable = 0;
++ lcd->intstatus = ~0;
++ lcd->backcolor = win->mode_backcolor;
++
++ /* Setup Color Key - FIX!!! */
++ lcd->colorkey = win->mode_colorkey;
++ lcd->colorkeymsk = win->mode_colorkeymsk;
++
++ /* Setup HWCursor - FIX!!! Need to support this eventually */
++ lcd->hwc.cursorctrl = 0;
++ lcd->hwc.cursorpos = 0;
++ lcd->hwc.cursorcolor0 = 0;
++ lcd->hwc.cursorcolor1 = 0;
++ lcd->hwc.cursorcolor2 = 0;
++ lcd->hwc.cursorcolor3 = 0;
+
-+ // clear out fb_info
-+ memset(&fb_info, 0, sizeof(struct fb_info_e1356));
+
-+ // copy boot options
-+ fb_info.fix = boot_fix;
-+ fb_info.default_par = boot_par;
++#if 0
++#define D(X) printk("%25s: %08X\n", #X, X)
++ D(lcd->screen);
++ D(lcd->horztiming);
++ D(lcd->verttiming);
++ D(lcd->clkcontrol);
++ D(lcd->pwmdiv);
++ D(lcd->pwmhi);
++ D(lcd->outmask);
++ D(lcd->fifoctrl);
++ D(lcd->window[0].winctrl0);
++ D(lcd->window[0].winctrl1);
++ D(lcd->window[0].winctrl2);
++ D(lcd->window[0].winbuf0);
++ D(lcd->window[0].winbuf1);
++ D(lcd->window[0].winbufctrl);
++ D(lcd->window[1].winctrl0);
++ D(lcd->window[1].winctrl1);
++ D(lcd->window[1].winctrl2);
++ D(lcd->window[1].winbuf0);
++ D(lcd->window[1].winbuf1);
++ D(lcd->window[1].winbufctrl);
++ D(lcd->window[2].winctrl0);
++ D(lcd->window[2].winctrl1);
++ D(lcd->window[2].winctrl2);
++ D(lcd->window[2].winbuf0);
++ D(lcd->window[2].winbuf1);
++ D(lcd->window[2].winbufctrl);
++ D(lcd->window[3].winctrl0);
++ D(lcd->window[3].winctrl1);
++ D(lcd->window[3].winctrl2);
++ D(lcd->window[3].winbuf0);
++ D(lcd->window[3].winbuf1);
++ D(lcd->window[3].winbufctrl);
++ D(lcd->winenable);
++ D(lcd->intenable);
++ D(lcd->intstatus);
++ D(lcd->backcolor);
++ D(lcd->winenable);
++ D(lcd->colorkey);
++ D(lcd->colorkeymsk);
++ D(lcd->hwc.cursorctrl);
++ D(lcd->hwc.cursorpos);
++ D(lcd->hwc.cursorcolor0);
++ D(lcd->hwc.cursorcolor1);
++ D(lcd->hwc.cursorcolor2);
++ D(lcd->hwc.cursorcolor3);
++#endif
++}
++
++static void au1200_setmode(struct au1200fb_device *fbdev)
++{
++ int plane = fbdev->plane;
++ /* Window/plane setup */
++ lcd->window[plane].winctrl1 = ( 0
++ | LCD_WINCTRL1_PRI_N(plane)
++ | win->w[plane].mode_winctrl1 /* FRM,CCO,PO,PIPE */
++ ) ;
++
++ au1200_setlocation(fbdev, plane, win->w[plane].xpos, win->w[plane].ypos);
++
++ lcd->window[plane].winctrl2 = ( 0
++ | LCD_WINCTRL2_CKMODE_00
++ | LCD_WINCTRL2_DBM
++ | LCD_WINCTRL2_BX_N( fbdev->fb_info.fix.line_length)
++ | LCD_WINCTRL2_SCX_1
++ | LCD_WINCTRL2_SCY_1
++ ) ;
++ lcd->winenable |= win->w[plane].mode_winenable;
++ au_sync();
++}
+
-+ fb_info.regbase_size = E1356_REG_SIZE;
+
-+ if (!epfix->system) {
-+ printk(KERN_ERR "e1356/86fb: no valid system found\n");
-+ return -ENODEV;
-+ }
++/* Inline helpers */
+
-+ if (epfix->system == SYS_SDU1356) {
-+ // it's the SDU1356B0C PCI eval card.
-+ struct pci_dev *pdev = NULL;
-+ if (!pci_present()) /* No PCI bus in this machine! */
-+ return -ENODEV;
-+ if (!(pdev = pci_find_device(PCI_VENDOR_ID_EPSON,
-+ PCI_DEVICE_ID_EPSON_SDU1356, pdev)))
-+ return -ENODEV;
-+ if (pci_enable_device(pdev))
-+ return -ENODEV;
-+ epfix->regbase_phys = pci_resource_start(pdev, 0);
-+ epfix->membase_phys = epfix->regbase_phys + E1356_REG_SIZE;
-+ }
-+
-+ fb_info.regbase_virt = ioremap_nocache(epfix->regbase_phys,
-+ E1356_REG_SIZE);
++/*#define panel_is_dual(panel) ((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
++/*#define panel_is_active(panel)((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
+
-+ if (!fb_info.regbase_virt) {
-+ printk("e1356fb: Can't remap %s register area.\n", name);
-+ return -ENXIO;
-+ }
++#define panel_is_color(panel) ((panel->mode_screen & LCD_SCREEN_PT) <= LCD_SCREEN_PT_CDSTN)
+
-+ regbase = fb_info.regbase_virt;
-+ reg = &fb_info.reg;
-+
-+ // Initialize the register pointers
-+ reg->basic = (reg_basic_t*) (regbase + REG_BASE_BASIC);
-+ reg->genio = (reg_genio_t*) (regbase + REG_BASE_GENIO);
-+ reg->md_cfg = (reg_mdcfg_t*) (regbase + REG_BASE_MDCFG);
-+ reg->clk_cfg = (reg_clkcfg_t*) (regbase + REG_BASE_CLKCFG);
-+ reg->mem_cfg = (reg_memcfg_t*) (regbase + REG_BASE_MEMCFG);
-+ reg->panel_cfg = (reg_panelcfg_t*)(regbase + REG_BASE_PANELCFG);
-+ reg->lcd_cfg = (reg_dispcfg_t*) (regbase + REG_BASE_LCD_DISPCFG);
-+ reg->crttv_cfg = (reg_dispcfg_t*) (regbase + REG_BASE_CRTTV_DISPCFG);
-+ reg->lcd_mode = (reg_dispmode_t*)(regbase + REG_BASE_LCD_DISPMODE);
-+ reg->crttv_mode = (reg_dispmode_t*)(regbase + REG_BASE_CRTTV_DISPMODE);
-+ reg->lcd_inkcurs = (reg_inkcurs_t*) (regbase + REG_BASE_LCD_INKCURS);
-+ reg->crttv_inkcurs = (reg_inkcurs_t*) (regbase + REG_BASE_CRTTV_INKCURS);
-+ reg->bitblt = (reg_bitblt_t*) (regbase + REG_BASE_BITBLT);
-+ reg->lut = (reg_lut_t*) (regbase + REG_BASE_LUT);
-+ reg->pwr_save = (reg_pwrsave_t*) (regbase + REG_BASE_PWRSAVE);
-+ reg->misc = (reg_misc_t*) (regbase + REG_BASE_MISC);
-+ reg->mediaplug = (reg_mediaplug_t*)(regbase + REG_BASE_MEDIAPLUG);
-+ reg->bitblt_data = (u16*) (regbase + REG_BASE_BITBLT_DATA);
-+
-+ // Enable all register access
-+ writeb(0, ®->basic->misc);
++/* Bitfields format supported by the controller. */
++struct fb_bitfield rgb_bitfields[][4] =
++{
++ /* Red, Green, Blue, Transp */
++ [LCD_WINCTRL1_FRM_16BPP655 >> 25] =
++ { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
+
-+ rev_code = readb(®->basic->rev_code);
-+ if ((rev_code >> 2) == 0x04) {
-+ printk("Found EPSON1356 Display Controller\n");
-+ }
-+ else if ((rev_code >> 2) == 0x07) {
-+ printk("Found EPSON13806 Display Controller\n");
-+ }
-+ else {
-+ iounmap(fb_info.regbase_virt);
-+ printk("e1356/806fb: %s not found, rev_code=0x%02x.\n",
-+ name, rev_code);
-+ return -ENODEV;
-+ }
++ [LCD_WINCTRL1_FRM_16BPP565 >> 25] =
++ { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
+
-+ fb_info.chip_rev = rev_code & 0x03;
++ [LCD_WINCTRL1_FRM_16BPP556 >> 25] =
++ { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
+
-+ // Determine frame-buffer size
-+ switch (readb(®->md_cfg->md_cfg_stat0) >> 6) {
-+ case 0:
-+ case 2:
-+ fb_info.fb_size = 0x80000; /* 512K bytes */
-+ break;
-+ case 1:
-+ if ((rev_code >> 2) == 7) /* 806 */
-+ fb_info.fb_size = 0x140000; /* 1.2M bytes */
-+ else
-+ fb_info.fb_size = 0x200000; /* 2M bytes */
-+ break;
-+ default:
-+ fb_info.fb_size = 0x200000; /* 2M bytes */
-+ break;
-+ }
++ [LCD_WINCTRL1_FRM_16BPPI1555 >> 25] =
++ { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
+
-+ fb_info.membase_virt = ioremap_nocache(epfix->membase_phys,
-+ fb_info.fb_size);
-+
-+ if (!fb_info.membase_virt) {
-+ printk("e1356fb: Can't remap %s framebuffer.\n", name);
-+ iounmap(fb_info.regbase_virt);
-+ return -ENXIO;
-+ }
-+
-+ printk("e1356/806fb: Detected %dKB framebuffer\n",
-+ (unsigned)fb_info.fb_size/1000);
++ [LCD_WINCTRL1_FRM_16BPPI5551 >> 25] =
++ { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 0, 0 } },
+
-+#ifdef CONFIG_MTRR
-+ if (!epfix->nomtrr) {
-+ fb_info.mtrr_idx = mtrr_add(epfix->membase_phys, fb_info.fb_size,
-+ MTRR_TYPE_WRCOMB, 1);
-+ printk("e1356fb: MTRR's turned on\n");
-+ }
-+#endif
-+
-+ if (!boot_fix.noaccel) {
-+ /*
-+ Allocate a page for string BLTs. A 4K page is
-+ enough for a 256 character string at an 8x16 font.
-+ */
-+ fb_info.putcs_buffer = (void*)__get_free_pages(GFP_KERNEL, 0);
-+ if (fb_info.putcs_buffer == NULL) {
-+ printk("e1356fb: Can't allocate putcs buffer\n");
-+ goto unmap_ret_enxio;
-+ }
-+ }
++ [LCD_WINCTRL1_FRM_16BPPA1555 >> 25] =
++ { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
+
-+ // Begin SED1356 initialization
++ [LCD_WINCTRL1_FRM_16BPPA5551 >> 25] =
++ { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
+
-+ // disable display while initializing
-+ writeb(0, ®->misc->disp_mode);
-+ // Set the GPIO1 and 2 to inputs
-+ writeb(0, ®->genio->gpio_cfg);
-+ writeb(0, ®->genio->gpio_ctrl);
-+ if (fb_info.chip_rev == 7) /* 806 */
-+ writeb(0, ®->genio->gpio_ctrl2);
++ [LCD_WINCTRL1_FRM_24BPP >> 25] =
++ { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 0, 0, 0 } },
+
-+ /*
-+ * Program the clocks
-+ */
++ [LCD_WINCTRL1_FRM_32BPP >> 25] =
++ { { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 0, 0 } },
++};
+
-+#ifdef CONFIG_MIPS_AU1000
-+ if ((epfix->system == SYS_PB1000) || (epfix->system == SYS_PB1500))
-+ epfix->busclk = get_au1000_lcd_clock();
-+#endif
-+
-+ if (epfix->busclk > 80000) {
-+ printk("e1356fb: specified busclk too high\n");
-+ goto ret_enxio;
-+ }
++/*-------------------------------------------------------------------------*/
+
-+ epfix->mclk = mclk_cfg = 0;
-+ if (epfix->system == SYS_PB1500) {
-+ epfix->mclk = epfix->busclk;
-+ mclk_cfg = 0x01;
-+ }
-+ else {
-+ // Find the highest allowable MCLK
-+ if (epfix->busclk <= MAX_PIXCLOCK &&
-+ epfix->busclk > epfix->mclk) {
-+ epfix->mclk = epfix->busclk;
-+ mclk_cfg = 0x01;
-+ }
-+ if (epfix->clki <= MAX_PIXCLOCK && epfix->clki > epfix->mclk) {
-+ epfix->mclk = epfix->clki;
-+ mclk_cfg = 0x00;
-+ }
-+ if (epfix->busclk/2 <= MAX_PIXCLOCK &&
-+ epfix->busclk/2 > epfix->mclk) {
-+ epfix->mclk = epfix->busclk/2;
-+ mclk_cfg = 0x11;
-+ }
-+ if (epfix->clki/2 <= MAX_PIXCLOCK &&
-+ epfix->clki/2 > epfix->mclk) {
-+ epfix->mclk = epfix->clki/2;
-+ mclk_cfg = 0x10;
-+ }
-+ }
++/* Helpers */
+
-+ if (!epfix->mclk) {
-+ printk("e1356fb: couldn't find an allowable MCLK!\n");
-+ goto ret_enxio;
-+ }
-+
-+ // When changing mclk src, you must first set bit 4 to 1.
-+ writeb(readb(®->clk_cfg->mem_clk_cfg) | 0x10,
-+ ®->clk_cfg->mem_clk_cfg);
-+ writeb(mclk_cfg, ®->clk_cfg->mem_clk_cfg);
-+
-+ printk("e1356fb: clocks (kHz): busclk=%d mclk=%d clki=%d clki2=%d\n",
-+ epfix->busclk, epfix->mclk, epfix->clki, epfix->clki2);
-+
-+ // Set max pixel clock
-+ switch (epfix->disp_type) {
-+ case DISP_TYPE_LCD:
-+ case DISP_TYPE_TFT:
-+ case DISP_TYPE_CRT:
-+ fb_info.max_pixclock = epfix->mclk;
-+ break;
-+ case DISP_TYPE_NTSC:
-+ case DISP_TYPE_PAL:
-+ fb_info.max_pixclock = (epfix->disp_type == DISP_TYPE_NTSC) ?
-+ NTSC_PIXCLOCK : PAL_PIXCLOCK;
-+ if (epfix->tv_filt & TV_FILT_FLICKER)
-+ fb_info.max_pixclock *= 2;
-+ break;
-+ default:
-+ printk("e1356fb: invalid specified display type\n");
-+ goto ret_enxio;
-+ }
-+
-+ periodMCLK = 1000000L / epfix->mclk; // in nano-seconds
-+ periodBCLK = 1000000L / epfix->busclk; // in nano-seconds
-+ if (readb(®->md_cfg->md_cfg_stat1) & (1<<4))
-+ periodBCLK *= 2;
-+
-+ if ((epfix->system == SYS_PB1000) || (epfix->system == SYS_PB1500))
-+ writeb(0x00, ®->clk_cfg->cpu2mem_wait_sel);
-+ else if (periodMCLK - 4 > periodBCLK)
-+ writeb(0x02, ®->clk_cfg->cpu2mem_wait_sel);
-+ else if (2*periodMCLK - 4 > periodBCLK)
-+ writeb(0x01, ®->clk_cfg->cpu2mem_wait_sel);
-+ else
-+ writeb(0x00, ®->clk_cfg->cpu2mem_wait_sel);
-+
-+ // Program memory config
-+ if (epfix->mem_type < MEM_TYPE_EDO_2CAS ||
-+ epfix->mem_type > MEM_TYPE_EMBEDDED_SDRAM) {
-+ printk("e1356fb: bad memory type specified\n");
-+ goto ret_enxio;
-+ }
-+ writeb((u8)epfix->mem_type, ®->mem_cfg->mem_cfg);
-+
-+ // calc closest refresh rate
-+ rr_div = 7;
-+ mclk_src = (mclk_cfg & 1) ? epfix->busclk : epfix->clki;
-+ while ((mclk_src >> (6 + rr_div)) < epfix->mem_refresh)
-+ if (--rr_div < 0) {
-+ printk("e1356fb: can't set specified refresh rate\n");
-+ goto ret_enxio;
-+ }
-+
-+ DPRINTK("refresh rate = %d kHz\n", (mclk_src >> (6 + rr_div)));
-+
-+ // add Suspend-Mode Refresh bits
-+ if (epfix->mem_smr < MEM_SMR_CBR || epfix->mem_smr > MEM_SMR_NONE) {
-+ printk("e1356fb: invalid specified suspend-mode refresh type\n");
-+ goto ret_enxio;
-+ }
-+ writeb(rr_div | (epfix->mem_smr << 6), ®->mem_cfg->dram_refresh);
-+
-+ // set DRAM speed
-+ switch (epfix->mem_speed) {
-+ case 50:
-+ dram_timing = epfix->mclk >= 33000 ? 0x0101 : 0x0212;
-+ break;
-+ case 60:
-+ if (epfix->mclk >= 30000)
-+ dram_timing = 0x0101;
-+ else if (epfix->mclk >= 25000)
-+ dram_timing =
-+ (epfix->mem_type == MEM_TYPE_EDO_2CAS ||
-+ epfix->mem_type == MEM_TYPE_EDO_2WE) ?
-+ 0x0212 : 0x0101;
-+ else
-+ dram_timing = 0x0212;
-+ break;
-+ case 70:
-+ if (epfix->mclk >= 30000)
-+ dram_timing = 0x0000;
-+ else if (epfix->mclk >= 25000)
-+ dram_timing = 0x0101;
-+ else
-+ dram_timing =
-+ (epfix->mem_type == MEM_TYPE_EDO_2CAS ||
-+ epfix->mem_type == MEM_TYPE_EDO_2WE) ?
-+ 0x0212 : 0x0211;
-+ break;
-+ case 80:
-+ if (epfix->mclk >= 25000)
-+ dram_timing = 0x0100;
-+ else
-+ dram_timing = 0x0101;
-+ break;
-+ default:
-+ printk("e1356fb: invalid specified memory speed\n");
-+ goto ret_enxio;
-+ }
-+
-+ writew(dram_timing, ®->mem_cfg->dram_timings_ctrl0);
-+
-+ currcon = -1;
-+ if (!epfix->nohwcursor)
-+ e1356fb_hwcursor_init(&fb_info);
-+
-+ init_timer(&fb_info.cursor.timer);
-+ fb_info.cursor.timer.function = do_flashcursor;
-+ fb_info.cursor.timer.data = (unsigned long)(&fb_info);
-+ fb_info.cursor.state = CM_ERASE;
-+ spin_lock_init(&fb_info.cursor.lock);
-+
-+ strcpy(fb_info.fb_info.modename, "Epson ");
-+ strcat(fb_info.fb_info.modename, name);
-+ fb_info.fb_info.changevar = NULL;
-+ fb_info.fb_info.node = -1;
-+
-+ fb_info.fb_info.fbops = &e1356fb_ops;
-+ fb_info.fb_info.disp = &fb_info.disp;
-+ strcpy(fb_info.fb_info.fontname, epfix->fontname);
-+ fb_info.fb_info.switch_con = &e1356fb_switch_con;
-+ fb_info.fb_info.updatevar = &e1356fb_updatevar;
-+ fb_info.fb_info.blank = &e1356fb_blank;
-+ fb_info.fb_info.flags = FBINFO_FLAG_DEFAULT;
-+
-+ // Set-up display
-+ // clear out unused stuff
-+ writeb(0, ®->panel_cfg->mod_rate);
-+ writeb(0x01, ®->lcd_mode->lcd_misc);
-+ writeb(0, ®->lcd_mode->fifo_high_thresh);
-+ writeb(0, ®->lcd_mode->fifo_low_thresh);
-+ writeb(0, ®->crttv_mode->fifo_high_thresh);
-+ writeb(0, ®->crttv_mode->fifo_low_thresh);
-+
-+ switch (epfix->disp_type) {
-+ case DISP_TYPE_LCD:
-+ switch (epfix->panel_width) {
-+ case 4: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x04); break;
-+ case 8: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x14); break;
-+ case 16: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x24); break;
-+ default:
-+ printk("e1356fb: invalid specified LCD panel data width\n");
-+ goto ret_enxio;
-+ }
-+ writeb(btmp, ®->panel_cfg->panel_type);
-+ break;
-+ case DISP_TYPE_TFT:
-+ switch (epfix->panel_width) {
-+ case 9: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x05); break;
-+ case 12: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x15); break;
-+ case 18: btmp = (u8)(((epfix->panel_el & 1)<<7) | 0x25); break;
-+ default:
-+ printk("e1356fb: invalid specified TFT panel data width\n");
-+ goto ret_enxio;
-+ }
-+ writeb(btmp, ®->panel_cfg->panel_type);
-+ break;
-+ case DISP_TYPE_CRT:
-+ writeb(0x00, ®->crttv_cfg->tv_output_ctrl);
-+ break;
-+ case DISP_TYPE_NTSC:
-+ case DISP_TYPE_PAL:
-+ if (epfix->tv_fmt < TV_FMT_COMPOSITE ||
-+ epfix->tv_fmt > TV_FMT_S_VIDEO) {
-+ printk("e1356fb: invalid specified TV output format\n");
-+ goto ret_enxio;
-+ }
-+ btmp = epfix->disp_type == DISP_TYPE_PAL ? 0x01 : 0x00;
-+ btmp |= (epfix->tv_fmt == TV_FMT_S_VIDEO ? 0x02 : 0x00);
-+ btmp |= ((epfix->tv_filt & TV_FILT_LUM) ? 0x10 : 0x00);
-+ btmp |= ((epfix->tv_filt & TV_FILT_CHROM) ? 0x20 : 0x00);
-+ writeb(btmp, ®->crttv_cfg->tv_output_ctrl);
-+ break;
-+ }
++static void
++au1200fb_update_fbinfo(struct fb_info *fbi)
++{
++ /* FIX!!!! This also needs to take the window pixel format into account!!! */
+
-+ memset(&var, 0, sizeof(var));
-+ /*
-+ * If mode_option wasn't given at boot, assume all the boot
-+ * option timing parameters were specified individually, in
-+ * which case we convert par_to_var instead of calling
-+ * fb_find_mode.
-+ */
-+ if (epfix->mode_option) {
-+ struct fb_videomode* modedb, *dm;
-+ int dbsize = e1356fb_get_mode(&fb_info, 640, 480, &modedb, &dm);
-+
-+ // first try the generic modedb
-+ if (!fb_find_mode(&var, &fb_info.fb_info, epfix->mode_option,
-+ NULL, 0, NULL, boot_par.bpp)) {
-+ printk("e1356fb: mode %s failed, trying e1356 modedb\n",
-+ epfix->mode_option);
-+ // didn't work in generic modedb, try ours
-+ if (!fb_find_mode(&var, &fb_info.fb_info,
-+ epfix->mode_option,
-+ modedb, dbsize, dm, boot_par.bpp)) {
-+ printk("e1356fb: mode %s failed e1356 modedb too, sorry\n",
-+ epfix->mode_option);
-+
-+ goto ret_enxio;
-+ }
++ /* Update var-dependent FB info */
++ if (panel_is_color(panel)) {
++ if (fbi->var.bits_per_pixel <= 8) {
++ /* palettized */
++ fbi->fix.visual = FB_VISUAL_PSEUDOCOLOR;
++ fbi->fix.line_length = fbi->var.xres_virtual /
++ (8/fbi->var.bits_per_pixel);
++ } else {
++ /* non-palettized */
++ fbi->fix.visual = FB_VISUAL_TRUECOLOR;
++ fbi->fix.line_length = fbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);
+ }
-+
-+ var.xres_virtual = boot_par.width_virt ?
-+ boot_par.width_virt : boot_par.width;
-+ var.yres_virtual = boot_par.height_virt ?
-+ boot_par.height_virt : boot_par.height;
+ } else {
-+ if (e1356fb_par_to_var(&var, &fb_info.default_par, &fb_info)) {
-+ printk("e1356fb: boot option mode failed\n");
-+ goto ret_enxio;
-+ }
-+ }
-+
-+ if (boot_fix.noaccel)
-+ var.accel_flags &= ~FB_ACCELF_TEXT;
-+ else
-+ var.accel_flags |= FB_ACCELF_TEXT;
-+
-+ if (e1356fb_var_to_par(&var, &fb_info.default_par, &fb_info)) {
-+ /*
-+ * Can't use the mode from the mode db or the default
-+ * mode or the boot options - give up
-+ */
-+ printk("e1356fb: mode failed var_to_par\n");
-+ goto ret_enxio;
++ /* mono FIX!!! mono 8 and 4 bits */
++ fbi->fix.visual = FB_VISUAL_MONO10;
++ fbi->fix.line_length = fbi->var.xres_virtual / 8;
+ }
-+
-+ fb_info.disp.screen_base = fb_info.membase_virt;
-+ fb_info.disp.var = var; // struct copy
-+
-+ // here's where the screen is actually initialized and enabled
-+ if (e1356fb_set_var(&var, -1, &fb_info.fb_info)) {
-+ printk("e1356fb: can't set video mode\n");
-+ goto ret_enxio;
-+ }
-+
-+ writeb(0, ®->pwr_save->cfg); // disable power-save mode
-+ writeb(0, ®->misc->cpu2mem_watchdog); // disable watchdog timer
+
-+#ifdef E1356FB_VERBOSE_DEBUG
-+ dump_fb(fb_info.membase_virt + 0x100000, 512);
-+#endif
++ fbi->screen_size = fbi->fix.line_length * fbi->var.yres_virtual;
++ print_dbg("line length: %d\n", fbi->fix.line_length);
++ print_dbg("bits_per_pixel: %d\n", fbi->var.bits_per_pixel);
++}
+
-+ if (register_framebuffer(&fb_info.fb_info) < 0) {
-+ writeb(0, ®->misc->disp_mode);
-+ printk("e1356fb: can't register framebuffer\n");
-+ goto ret_enxio;
-+ }
-+
-+ printk("fb%d: %s frame buffer device\n",
-+ GET_FB_IDX(fb_info.fb_info.node),
-+ fb_info.fb_info.modename);
-+
-+
++/*-------------------------------------------------------------------------*/
++
++/* AU1200 framebuffer driver */
++
++int au1200fb_fb_open(struct fb_info *fbi, int user)
++{
+ return 0;
++}
+
-+ ret_enxio:
-+ free_pages((unsigned long)fb_info.putcs_buffer, 0);
-+ unmap_ret_enxio:
-+ iounmap(fb_info.regbase_virt);
-+ iounmap(fb_info.membase_virt);
-+ return -ENXIO;
++int au1200fb_fb_release(struct fb_info *fbi, int user)
++{
++ return 0;
+}
+
-+/**
-+ * e1356fb_exit - Driver cleanup
-+ *
-+ * Releases all resources allocated during the
-+ * course of the driver's lifetime.
-+ *
-+ * FIXME - do results of fb_alloc_cmap need disposal?
++/* fb_check_var
++ * Validate var settings with hardware restrictions and modify it if necessary
+ */
-+static void __exit
-+e1356fb_exit (void)
++int au1200fb_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
+{
-+ unregister_framebuffer(&fb_info.fb_info);
-+ del_timer_sync(&fb_info.cursor.timer);
-+
-+#ifdef CONFIG_MTRR
-+ if (!fb_info.fix.nomtrr) {
-+ mtrr_del(fb_info.mtrr_idx, fb_info.fix.membase_phys,
-+ fb_info.fb_size);
-+ printk("fb: MTRR's turned off\n");
-+ }
-+#endif
++ struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
++ u32 pixclock;
++ int screen_size, plane;
+
-+ free_pages((unsigned long)fb_info.putcs_buffer, 0);
-+ iounmap(fb_info.regbase_virt);
-+ iounmap(fb_info.membase_virt);
-+}
++ plane = fbdev->plane;
+
-+MODULE_AUTHOR("Steve Longerbeam <stevel at mvista.com>");
-+MODULE_DESCRIPTION("SED1356 framebuffer device driver");
++ /* Make sure that the mode respect all LCD controller and
++ * panel restrictions. */
++ var->xres = win->w[plane].xres;
++ var->yres = win->w[plane].yres;
++
++ /* No need for virtual resolution support */
++ var->xres_virtual = var->xres;
++ var->yres_virtual = var->yres;
+
-+#ifdef MODULE
-+module_init(e1356fb_init);
-+#endif
-+module_exit(e1356fb_exit);
++ var->bits_per_pixel = winbpp(win->w[plane].mode_winctrl1);
+
++ screen_size = var->xres_virtual * var->yres_virtual;
++ if (var->bits_per_pixel > 8) screen_size *= (var->bits_per_pixel / 8);
++ else screen_size /= (8/var->bits_per_pixel);
+
-+void
-+e1356fb_setup(char *options, int *ints)
-+{
-+ char* this_opt;
-+
-+ memset(&boot_fix, 0, sizeof(struct e1356fb_fix));
-+ memset(&boot_par, 0, sizeof(struct e1356fb_par));
-+ boot_fix.system = -1;
-+
-+ if (!options || !*options)
-+ return;
-+
-+ for(this_opt=strtok(options, ","); this_opt;
-+ this_opt=strtok(NULL, ",")) {
-+ if (!strncmp(this_opt, "noaccel", 7)) {
-+ boot_fix.noaccel = 1;
-+ } else if (!strncmp(this_opt, "nopan", 5)) {
-+ boot_fix.nopan = 1;
-+ } else if (!strncmp(this_opt, "nohwcursor", 10)) {
-+ boot_fix.nohwcursor = 1;
-+ } else if (!strncmp(this_opt, "mmunalign:", 10)) {
-+ boot_fix.mmunalign = simple_strtoul(this_opt+10,
-+ NULL, 0);
-+#ifdef CONFIG_MTRR
-+ } else if (!strncmp(this_opt, "nomtrr", 6)) {
-+ boot_fix.nomtrr = 1;
-+#endif
-+ } else if (!strncmp(this_opt, "font:", 5)) {
-+ strncpy(boot_fix.fontname, this_opt+5,
-+ sizeof(boot_fix.fontname)-1);
-+ } else if (!strncmp(this_opt, "regbase:", 8)) {
-+ boot_fix.regbase_phys = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "membase:", 8)) {
-+ boot_fix.membase_phys = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "memsp:", 6)) {
-+ boot_fix.mem_speed = simple_strtoul(this_opt+6,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "memtyp:", 7)) {
-+ boot_fix.mem_type = simple_strtoul(this_opt+7,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "memref:", 7)) {
-+ boot_fix.mem_refresh = simple_strtoul(this_opt+7,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "memsmr:", 7)) {
-+ boot_fix.mem_smr = simple_strtoul(this_opt+7, NULL, 0);
-+ } else if (!strncmp(this_opt, "busclk:", 7)) {
-+ boot_fix.busclk = simple_strtoul(this_opt+7, NULL, 0);
-+ } else if (!strncmp(this_opt, "clki:", 5)) {
-+ boot_fix.clki = simple_strtoul(this_opt+5, NULL, 0);
-+ } else if (!strncmp(this_opt, "clki2:", 6)) {
-+ boot_fix.clki2 = simple_strtoul(this_opt+6, NULL, 0);
-+ } else if (!strncmp(this_opt, "display:", 8)) {
-+ if (!strncmp(this_opt+8, "lcd", 3))
-+ boot_fix.disp_type = DISP_TYPE_LCD;
-+ else if (!strncmp(this_opt+8, "tft", 3))
-+ boot_fix.disp_type = DISP_TYPE_TFT;
-+ else if (!strncmp(this_opt+8, "crt", 3))
-+ boot_fix.disp_type = DISP_TYPE_CRT;
-+ else if (!strncmp(this_opt+8, "pal", 3))
-+ boot_fix.disp_type = DISP_TYPE_PAL;
-+ else if (!strncmp(this_opt+8, "ntsc", 4))
-+ boot_fix.disp_type = DISP_TYPE_NTSC;
-+ } else if (!strncmp(this_opt, "width:", 6)) {
-+ boot_par.width = simple_strtoul(this_opt+6, NULL, 0);
-+ } else if (!strncmp(this_opt, "height:", 7)) {
-+ boot_par.height = simple_strtoul(this_opt+7, NULL, 0);
-+ } else if (!strncmp(this_opt, "bpp:", 4)) {
-+ boot_par.bpp = simple_strtoul(this_opt+4, NULL, 0);
-+ boot_par.cmap_len = (boot_par.bpp == 8) ? 256 : 16;
-+ } else if (!strncmp(this_opt, "elpanel:", 8)) {
-+ boot_fix.panel_el = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "pdataw:", 7)) {
-+ boot_fix.panel_width = simple_strtoul(this_opt+7,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "hndp:", 5)) {
-+ boot_par.horiz_ndp = simple_strtoul(this_opt+5,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "vndp:", 5)) {
-+ boot_par.vert_ndp = simple_strtoul(this_opt+5,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "hspol:", 6)) {
-+ boot_par.hsync_pol = simple_strtoul(this_opt+6,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "vspol:", 6)) {
-+ boot_par.vsync_pol = simple_strtoul(this_opt+6,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "hsstart:", 8)) {
-+ boot_par.hsync_start = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "hswidth:", 8)) {
-+ boot_par.hsync_width = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "vsstart:", 8)) {
-+ boot_par.vsync_start = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "vswidth:", 8)) {
-+ boot_par.vsync_width = simple_strtoul(this_opt+8,
-+ NULL, 0);
-+ } else if (!strncmp(this_opt, "tvfilt:", 7)) {
-+ boot_fix.tv_filt = simple_strtoul(this_opt+7, NULL, 0);
-+ } else if (!strncmp(this_opt, "tvfmt:", 6)) {
-+ boot_fix.tv_fmt = simple_strtoul(this_opt+6, NULL, 0);
-+ } else if (!strncmp(this_opt, "system:", 7)) {
-+ if (!strncmp(this_opt+7, "pb1000", 10)) {
-+ boot_fix = systems[SYS_PB1000].fix;
-+ boot_par = systems[SYS_PB1000].par;
-+ } else if (!strncmp(this_opt+7, "pb1500", 7)) {
-+ boot_fix = systems[SYS_PB1500].fix;
-+ boot_par = systems[SYS_PB1500].par;
-+ } else if (!strncmp(this_opt+7, "sdu1356", 7)) {
-+ boot_fix = systems[SYS_SDU1356].fix;
-+ boot_par = systems[SYS_SDU1356].par;
-+ } else if (!strncmp(this_opt+7, "clio1050", 7)) {
-+ boot_fix = systems[SYS_CLIO1050].fix;
-+ boot_par = systems[SYS_CLIO1050].par;
-+ }
-+ } else {
-+ boot_fix.mode_option = this_opt;
-+ }
-+ }
-+}
++ if (fbdev->fb_len < screen_size)
++ return -EINVAL; /* Virtual screen is to big, abort */
+
++ /* FIX!!!! what are the implicaitons of ignoring this for windows ??? */
++ /* The max LCD clock is fixed to 48MHz (value of AUX_CLK). The pixel
++ * clock can only be obtain by dividing this value by an even integer.
++ * Fallback to a slower pixel clock if necessary. */
++ pixclock = max((u32)(PICOS2KHZ(var->pixclock) * 1000), fbi->monspecs.dclkmin);
++ pixclock = min(pixclock, min(fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2));
+
-+/*
-+ * FIXME: switching consoles could be dangerous. What if switching
-+ * from a panel to a CRT/TV, or vice versa? More needs to be
-+ * done here.
-+ */
-+static int
-+e1356fb_switch_con(int con, struct fb_info *fb)
-+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ struct e1356fb_par par;
-+ int old_con = currcon;
-+ int set_par = 1;
-+
-+ //DPRINTK("\n");
-+
-+ /* Do we have to save the colormap? */
-+ if (currcon>=0)
-+ if (fb_display[currcon].cmap.len)
-+ fb_get_cmap(&fb_display[currcon].cmap, 1,
-+ e1356fb_getcolreg, fb);
-+
-+ currcon = con;
-+ fb_display[currcon].var.activate = FB_ACTIVATE_NOW;
-+ e1356fb_var_to_par(&fb_display[con].var, &par, info);
-+ if (old_con>=0 && vt_cons[old_con]->vc_mode!=KD_GRAPHICS) {
-+ /* check if we have to change video registers */
-+ struct e1356fb_par old_par;
-+ e1356fb_var_to_par(&fb_display[old_con].var, &old_par, info);
-+ if (!memcmp(&par,&old_par,sizeof(par)))
-+ set_par = 0; /* avoid flicker */
++ if (AU1200_LCD_MAX_CLK % pixclock) {
++ int diff = AU1200_LCD_MAX_CLK % pixclock;
++ pixclock -= diff;
+ }
-+ if (set_par)
-+ e1356fb_set_par(&par, info);
-+
-+ if (fb_display[con].dispsw && fb_display[con].conp)
-+ fb_con.con_cursor(fb_display[con].conp, CM_ERASE);
-+
-+ del_timer(&(info->cursor.timer));
-+ fb_info.cursor.state=CM_ERASE;
-+
-+ if (!info->fix.nohwcursor)
-+ if (fb_display[con].conp)
-+ e1356fb_createcursor( &fb_display[con] );
-+
-+ info->cursor.redraw=1;
-+
-+ e1356fb_set_dispsw(&fb_display[con],
-+ info,
-+ par.bpp,
-+ fb_display[con].var.accel_flags & FB_ACCELF_TEXT);
-+
-+ e1356fb_install_cmap(&fb_display[con], fb);
-+ e1356fb_updatevar(con, fb);
-+
-+ return 1;
-+}
+
-+/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
-+static void
-+e1356fb_blank(int blank, struct fb_info *fb)
-+{
-+ struct fb_info_e1356 *info = (struct fb_info_e1356*)fb;
-+ reg_dispmode_t* dispmode = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_mode : info->reg.crttv_mode;
-+ reg_pwrsave_t* pwrsave = info->reg.pwr_save;
++ var->pixclock = KHZ2PICOS(pixclock/1000);
++#if 0
++ if (!panel_is_active(panel)) {
++ int pcd = AU1200_LCD_MAX_CLK / (pixclock * 2) - 1;
+
-+ //DPRINTK("\n");
++ if (!panel_is_color(panel)
++ && (panel->control_base & LCD_CONTROL_MPI) && (pcd < 3)) {
++ /* STN 8bit mono panel support is up to 6MHz pixclock */
++ var->pixclock = KHZ2PICOS(6000);
++ } else if (!pcd) {
++ /* Other STN panel support is up to 12MHz */
++ var->pixclock = KHZ2PICOS(12000);
++ }
++ }
++#endif
++ /* Set bitfield accordingly */
++ switch (var->bits_per_pixel) {
++ case 16:
++ {
++ /* 16bpp True color.
++ * These must be set to MATCH WINCTRL[FORM] */
++ int idx;
++ idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
++ var->red = rgb_bitfields[idx][0];
++ var->green = rgb_bitfields[idx][1];
++ var->blue = rgb_bitfields[idx][2];
++ var->transp = rgb_bitfields[idx][3];
++ break;
++ }
+
-+ switch (blank) {
-+ case 0:
-+ // Get out of power save mode
-+ writeb(0x00, &pwrsave->cfg);
-+ writeb(readb(&dispmode->disp_mode) & ~0x80,
-+ &dispmode->disp_mode);
-+ break;
-+ case 1:
-+ // Get out of power save mode
-+ writeb(0x00, &pwrsave->cfg);
-+ writeb(readb(&dispmode->disp_mode) | 0x80,
-+ &dispmode->disp_mode);
-+ break;
-+ // No support for turning off horiz or vert sync, so just treat
-+ // it as a power off.
-+ case 2:
-+ case 3:
-+ case 4:
-+ writeb(0x01, &pwrsave->cfg);
-+ break;
++ case 32:
++ {
++ /* 32bpp True color.
++ * These must be set to MATCH WINCTRL[FORM] */
++ int idx;
++ idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
++ var->red = rgb_bitfields[idx][0];
++ var->green = rgb_bitfields[idx][1];
++ var->blue = rgb_bitfields[idx][2];
++ var->transp = rgb_bitfields[idx][3];
++ break;
++ }
++ default:
++ print_dbg("Unsupported depth %dbpp", var->bits_per_pixel);
++ return -EINVAL;
+ }
-+}
+
++ return 0;
++}
+
-+static int
-+e1356fb_updatevar(int con, struct fb_info* fb)
++/* fb_set_par
++ * Set hardware with var settings. This will enable the controller with a
++ * specific mode, normally validated with the fb_check_var method
++ */
++int au1200fb_fb_set_par(struct fb_info *fbi)
+{
-+ struct fb_info_e1356* i = (struct fb_info_e1356*)fb;
++ struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
+
-+ //DPRINTK("\n");
++ au1200fb_update_fbinfo(fbi);
++ au1200_setmode(fbdev);
+
-+ if ((con==currcon) && (!i->fix.nopan))
-+ do_pan_var(&fb_display[con].var,i);
+ return 0;
+}
+
-+static int
-+e1356fb_getcolreg(unsigned regno,
-+ unsigned* red,
-+ unsigned* green,
-+ unsigned* blue,
-+ unsigned* transp,
-+ struct fb_info* fb)
++/* fb_setcolreg
++ * Set color in LCD palette.
++ */
++int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
+{
-+ struct fb_info_e1356* i = (struct fb_info_e1356*)fb;
++ u32 *palette = lcd->palette;
++ u32 value;
+
-+ if (regno > i->current_par.cmap_len)
-+ return 1;
-+
-+ *red = i->palette[regno].red;
-+ *green = i->palette[regno].green;
-+ *blue = i->palette[regno].blue;
-+ *transp = 0;
++ if (regno > (AU1200_LCD_NBR_PALETTE_ENTRIES - 1))
++ return -EINVAL;
++
++ if (fbi->var.grayscale) {
++ /* Convert color to grayscale */
++ red = green = blue =
++ (19595 * red + 38470 * green + 7471 * blue) >> 16;
++ }
++
++ if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
++ /* Place color in the pseudopalette */
++ if (regno > 16)
++ return -EINVAL;
+
++ palette = (u32*)fbi->pseudo_palette;
++
++ red >>= (16 - fbi->var.red.length);
++ green >>= (16 - fbi->var.green.length);
++ blue >>= (16 - fbi->var.blue.length);
++
++ value = (red << fbi->var.red.offset) |
++ (green << fbi->var.green.offset)|
++ (blue << fbi->var.blue.offset);
++ value &= 0xFFFF;
++
++ } else if (1 /*FIX!!! panel_is_active(fbdev->panel)*/) {
++ /* COLOR TFT PALLETTIZED (use RGB 565) */
++ value = (red & 0xF800)|((green >> 5) &
++ 0x07E0)|((blue >> 11) & 0x001F);
++ value &= 0xFFFF;
++
++ } else if (0 /*panel_is_color(fbdev->panel)*/) {
++ /* COLOR STN MODE */
++ value = 0x1234;
++ value &= 0xFFF;
++ } else {
++ /* MONOCHROME MODE */
++ value = (green >> 12) & 0x000F;
++ value &= 0xF;
++ }
++
++ palette[regno] = value;
++
+ return 0;
+}
+
-+static int
-+e1356fb_setcolreg(unsigned regno,
-+ unsigned red,
-+ unsigned green,
-+ unsigned blue,
-+ unsigned transp,
-+ struct fb_info* info)
++/* fb_blank
++ * Blank the screen. Depending on the mode, the screen will be
++ * activated with the backlight color, or desactivated
++ */
++int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
+{
-+ struct fb_info_e1356* i = (struct fb_info_e1356*)info;
++ /* Short-circuit screen blanking */
++ if (noblanking)
++ return 0;
+
-+ if (regno > 255)
-+ return 1;
++ switch (blank_mode) {
+
-+ i->palette[regno].red = red;
-+ i->palette[regno].green = green;
-+ i->palette[regno].blue = blue;
-+
-+ switch(i->current_par.bpp) {
-+#ifdef FBCON_HAS_CFB8
-+ case 8:
-+ do_setpalentry(i->reg.lut, regno,
-+ (u8)(red>>8), (u8)(green>>8), (u8)(blue>>8));
++ case VESA_NO_BLANKING:
++ /* printk("turn on panel\n"); */
++ au1200_setpanel(panel);
+ break;
-+#endif
-+#ifdef FBCON_HAS_CFB16
-+ case 16:
-+ i->fbcon_cmap16[regno] = (regno << 10) | (regno << 5) | regno;
++
++ case VESA_VSYNC_SUSPEND:
++ case VESA_HSYNC_SUSPEND:
++ case VESA_POWERDOWN:
++ /* printk("turn off panel\n"); */
++ au1200_setpanel(NULL);
+ break;
-+#endif
-+ default:
-+ DPRINTK("bad depth %u\n", i->current_par.bpp);
++ default:
+ break;
++
+ }
+ return 0;
+}
+
-+static void
-+e1356fb_install_cmap(struct display *d, struct fb_info *info)
++/* fb_mmap
++ * Map video memory in user space. We don't use the generic fb_mmap
++ * method mainly to allow the use of the TLB streaming flag (CCA=6)
++ */
++int au1200fb_fb_mmap(struct fb_info *fbi, struct file *file, struct vm_area_struct *vma)
+{
-+ struct fb_info_e1356* i = (struct fb_info_e1356*)info;
++ unsigned int len;
++ unsigned long start=0, off;
++ struct au1200fb_device *fbdev = (struct au1200fb_device *)fbi;
+
-+ //DPRINTK("\n");
++#ifdef CONFIG_PM
++ au1xxx_pm_access(LCD_pm_dev);
++#endif
+
-+ if (d->cmap.len) {
-+ fb_set_cmap(&(d->cmap), 1, e1356fb_setcolreg, info);
-+ } else {
-+ fb_set_cmap(fb_default_cmap(i->current_par.cmap_len), 1,
-+ e1356fb_setcolreg, info);
++ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
++ return -EINVAL;
+ }
-+}
-+
-+static void
-+e1356fb_createcursorshape(struct display* p)
-+{
-+ int h,u;
-+
-+ h = fontheight(p);
++
++ start = fbdev->fb_phys & PAGE_MASK;
++ len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
+
-+ fb_info.cursor.type = p->conp->vc_cursor_type & CUR_HWMASK;
++ off = vma->vm_pgoff << PAGE_SHIFT;
+
-+ switch (fb_info.cursor.type) {
-+ case CUR_NONE:
-+ u = h;
-+ break;
-+ case CUR_UNDERLINE:
-+ u = h - 2;
-+ break;
-+ case CUR_LOWER_THIRD:
-+ u = (h * 2) / 3;
-+ break;
-+ case CUR_LOWER_HALF:
-+ u = h / 2;
-+ break;
-+ case CUR_TWO_THIRDS:
-+ u = h / 3;
-+ break;
-+ case CUR_BLOCK:
-+ default:
-+ u = 0;
-+ break;
++ if ((vma->vm_end - vma->vm_start + off) > len) {
++ return -EINVAL;
+ }
-+
-+ fb_info.cursor.w = fontwidth_x8(p);
-+ fb_info.cursor.u = u;
-+ fb_info.cursor.h = h;
-+}
++
++ off += start;
++ vma->vm_pgoff = off >> PAGE_SHIFT;
++
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++ pgprot_val(vma->vm_page_prot) |= _CACHE_MASK; /* CCA=7 */
++
++ vma->vm_flags |= VM_IO;
+
-+static void
-+e1356fb_createcursor(struct display *p)
-+{
-+ void* memcursor;
-+ int y, w, h, u;
-+
-+ e1356fb_createcursorshape(p);
++ return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++ vma->vm_end - vma->vm_start,
++ vma->vm_page_prot);
+
-+ h = fb_info.cursor.h;
-+ w = fb_info.cursor.w;
-+ u = fb_info.cursor.u;
-+ memcursor = fb_info.membase_virt + fb_info.fb_size;
-+
-+ // write cursor to display memory
-+ for (y=0; y<64; y++) {
-+ if (y >= h || y < u) {
-+ fbfill((u16*)memcursor, 0xaa, 16); // b/g
-+ } else {
-+ fbfill((u16*)memcursor, 0xff, w/4); // inverted b/g
-+ fbfill((u16*)memcursor + w/4, 0xaa, (64 - w)/4); // b/g
-+ }
-+ memcursor += 16;
++ return 0;
++}
++
++void set_global(u_int cmd, au1200_lcd_global_regs_t *pdata) {
++
++ unsigned int hi1, divider;
++
++ /* SCREEN_SIZE: user cannot reset size, must switch panel choice */
++
++ if (pdata->flags & SCREEN_BACKCOLOR)
++ lcd->backcolor = pdata->backcolor;
++
++ if (pdata->flags & SCREEN_BRIGHTNESS) {
++
++ // limit brightness pwm duty to >= 30/1600
++ if (pdata->brightness < 30) {
++ pdata->brightness = 30;
++ }
++ divider = (lcd->pwmdiv & 0x3FFFF) + 1;
++ hi1 = (lcd->pwmhi >> 16) + 1;
++ hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
++ lcd->pwmhi &= 0xFFFF;
++ lcd->pwmhi |= (hi1 << 16);
+ }
++
++ if (pdata->flags & SCREEN_COLORKEY)
++ lcd->colorkey = pdata->colorkey;
++
++ if (pdata->flags & SCREEN_MASK)
++ lcd->colorkeymsk = pdata->mask;
++ au_sync();
+}
-+
-+static void
-+e1356fb_hwcursor_init(struct fb_info_e1356* info)
-+{
-+ reg_inkcurs_t* inkcurs = (IS_PANEL(info->fix.disp_type)) ?
-+ info->reg.lcd_inkcurs : info->reg.crttv_inkcurs;
+
-+ fb_info.fb_size -= 1024;
-+ // program cursor base address
-+ writeb(0x00, &inkcurs->start_addr);
-+ printk("e1356fb: reserving 1024 bytes for the hwcursor at %p\n",
-+ fb_info.membase_virt + fb_info.fb_size);
++void get_global(u_int cmd, au1200_lcd_global_regs_t *pdata) {
++ unsigned int hi1, divider;
++
++ pdata->xsize = ((lcd->screen & LCD_SCREEN_SX) >> 19) + 1;
++ pdata->ysize = ((lcd->screen & LCD_SCREEN_SY) >> 8) + 1;
++
++ pdata->backcolor = lcd->backcolor;
++ pdata->colorkey = lcd->colorkey;
++ pdata->mask = lcd->colorkeymsk;
++
++ // brightness
++ hi1 = (lcd->pwmhi >> 16) + 1;
++ divider = (lcd->pwmdiv & 0x3FFFF) + 1;
++ pdata->brightness = ((hi1 << 8) / divider) - 1;
++ au_sync();
+}
+
-+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
++void print_global(au1200_lcd_global_regs_t *pdata) {
+
-+/*
-+ * Return indicates whether a page was freed so caller can adjust rss
-+ */
-+static inline void forget_pte(pte_t page)
-+{
-+ if (!pte_none(page)) {
-+ printk("forget_pte: old mapping existed!\n");
-+ BUG();
++ printk("pdata->xsize %x\n", pdata->xsize);
++ printk("pdata->ysize %x\n", pdata->ysize);
++ printk("pdata->backcolor %x\n", pdata->backcolor);
++ printk("pdata->brightness %x\n", pdata->brightness);
++ printk("pdata->colorkey %x\n", pdata->colorkey);
++ printk("pdata->mask %x\n", pdata->mask);
++}
++
++void set_window(unsigned int plane, au1200_lcd_window_regs_t *pdata) {
++
++ unsigned int val, bpp;
++
++ /* Window control register 0 */
++ if (pdata->flags & WIN_POSITION) {
++ val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_OX |
++ LCD_WINCTRL0_OY);
++ val |= ((pdata->xpos << 21) & LCD_WINCTRL0_OX);
++ val |= ((pdata->ypos << 10) & LCD_WINCTRL0_OY);
++ lcd->window[plane].winctrl0 = val;
++ }
++ if (pdata->flags & WIN_ALPHA_COLOR) {
++ val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_A);
++ val |= ((pdata->alpha_color << 2) & LCD_WINCTRL0_A);
++ lcd->window[plane].winctrl0 = val;
++ }
++ if (pdata->flags & WIN_ALPHA_MODE) {
++ val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_AEN);
++ val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN);
++ lcd->window[plane].winctrl0 = val;
++ }
++
++ /* Window control register 1 */
++ if (pdata->flags & WIN_PRIORITY) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PRI);
++ val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI);
++ lcd->window[plane].winctrl1 = val;
++ }
++ if (pdata->flags & WIN_CHANNEL) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PIPE);
++ val |= ((pdata->channel << 29) & LCD_WINCTRL1_PIPE);
++ lcd->window[plane].winctrl1 = val;
++ }
++ if (pdata->flags & WIN_BUFFER_FORMAT) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_FRM);
++ val |= ((pdata->buffer_format << 25) & LCD_WINCTRL1_FRM);
++ lcd->window[plane].winctrl1 = val;
++ }
++ if (pdata->flags & WIN_COLOR_ORDER) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_CCO);
++ val |= ((pdata->color_order << 24) & LCD_WINCTRL1_CCO);
++ lcd->window[plane].winctrl1 = val;
++ }
++ if (pdata->flags & WIN_PIXEL_ORDER) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PO);
++ val |= ((pdata->pixel_order << 22) & LCD_WINCTRL1_PO);
++ lcd->window[plane].winctrl1 = val;
++ }
++ if (pdata->flags & WIN_SIZE) {
++ val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_SZX |
++ LCD_WINCTRL1_SZY);
++ val |= (((pdata->xsize << 11) - 1) & LCD_WINCTRL1_SZX);
++ val |= (((pdata->ysize) - 1) & LCD_WINCTRL1_SZY);
++ lcd->window[plane].winctrl1 = val;
++ /* program buffer line width */
++ bpp = winbpp(val) / 8;
++ val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_BX);
++ val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX);
++ lcd->window[plane].winctrl2 = val;
++ }
++
++ /* Window control register 2 */
++ if (pdata->flags & WIN_COLORKEY_MODE) {
++ val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_CKMODE);
++ val |= ((pdata->colorkey_mode << 24) & LCD_WINCTRL2_CKMODE);
++ lcd->window[plane].winctrl2 = val;
++ }
++ if (pdata->flags & WIN_DOUBLE_BUFFER_MODE) {
++ val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_DBM);
++ val |= ((pdata->double_buffer_mode << 23) & LCD_WINCTRL2_DBM);
++ lcd->window[plane].winctrl2 = val;
++ }
++ if (pdata->flags & WIN_RAM_ARRAY_MODE) {
++ val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_RAM);
++ val |= ((pdata->ram_array_mode << 21) & LCD_WINCTRL2_RAM);
++ lcd->window[plane].winctrl2 = val;
++ }
++
++ /* Buffer line width programmed with WIN_SIZE */
++
++ if (pdata->flags & WIN_BUFFER_SCALE) {
++ val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_SCX |
++ LCD_WINCTRL2_SCY);
++ val |= ((pdata->xsize << 11) & LCD_WINCTRL2_SCX);
++ val |= ((pdata->ysize) & LCD_WINCTRL2_SCY);
++ lcd->window[plane].winctrl2 = val;
++ }
++
++ if (pdata->flags & WIN_ENABLE) {
++ val = lcd->winenable;
++ val &= ~(1<<plane);
++ val |= (pdata->enable & 1) << plane;
++ lcd->winenable = val;
+ }
++ au_sync();
+}
+
-+/*
-+ * maps a range of physical memory into the requested pages. the old
-+ * mappings are removed. any references to nonexistent pages results
-+ * in null mappings (currently treated as "copy-on-access")
-+ */
-+static inline void e1356_remap_pte_range(pte_t * pte, unsigned long address, unsigned long size,
-+ phys_t phys_addr, pgprot_t prot)
-+{
-+ unsigned long end;
-+
-+ address &= ~PMD_MASK;
-+ end = address + size;
-+ if (end > PMD_SIZE)
-+ end = PMD_SIZE;
-+ do {
-+ struct page *page;
-+ pte_t oldpage;
-+ oldpage = ptep_get_and_clear(pte);
-+
-+ page = virt_to_page(__va(phys_addr));
-+ if ((!VALID_PAGE(page)) || PageReserved(page))
-+ set_pte(pte, mk_pte_phys(phys_addr, prot));
-+ forget_pte(oldpage);
-+ address += PAGE_SIZE;
-+ phys_addr += PAGE_SIZE;
-+ pte++;
-+ } while (address && (address < end));
-+}
-+
-+static inline int e1356_remap_pmd_range(struct mm_struct *mm, pmd_t * pmd, unsigned long address, unsigned long size,
-+ phys_t phys_addr, pgprot_t prot)
-+{
-+ unsigned long end;
-+
-+ address &= ~PGDIR_MASK;
-+ end = address + size;
-+ if (end > PGDIR_SIZE)
-+ end = PGDIR_SIZE;
-+ phys_addr -= address;
-+ do {
-+ pte_t * pte = pte_alloc(mm, pmd, address);
-+ if (!pte)
-+ return -ENOMEM;
-+ e1356_remap_pte_range(pte, address, end - address, address + phys_addr, prot);
-+ address = (address + PMD_SIZE) & PMD_MASK;
-+ pmd++;
-+ } while (address && (address < end));
-+ return 0;
++void get_window(unsigned int plane, au1200_lcd_window_regs_t *pdata) {
++
++ /* Window control register 0 */
++ pdata->xpos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OX) >> 21;
++ pdata->ypos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OY) >> 10;
++ pdata->alpha_color = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_A) >> 2;
++ pdata->alpha_mode = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_AEN) >> 1;
++
++ /* Window control register 1 */
++ pdata->priority = (lcd->window[plane].winctrl1& LCD_WINCTRL1_PRI) >> 30;
++ pdata->channel = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PIPE) >> 29;
++ pdata->buffer_format = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_FRM) >> 25;
++ pdata->color_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_CCO) >> 24;
++ pdata->pixel_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PO) >> 22;
++ pdata->xsize = ((lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZX) >> 11) + 1;
++ pdata->ysize = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZY) + 1;
++
++ /* Window control register 2 */
++ pdata->colorkey_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_CKMODE) >> 24;
++ pdata->double_buffer_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_DBM) >> 23;
++ pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
++
++ pdata->enable = (lcd->winenable >> plane) & 1;
++ au_sync();
+}
+
-+/* Note: this is only safe if the mm semaphore is held when called. */
-+static int e1356_remap_page_range(unsigned long from, phys_t phys_addr, unsigned long size, pgprot_t prot)
++static int au1200fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
++ u_long arg, struct fb_info *info)
+{
-+ int error = 0;
-+ pgd_t * dir;
-+ phys_t beg = from;
-+ phys_t end = from + size;
-+ struct mm_struct *mm = current->mm;
-+
-+ phys_addr -= from;
-+ dir = pgd_offset(mm, from);
-+ flush_cache_range(mm, beg, end);
-+ if (from >= end)
-+ BUG();
++ int plane;
++ int val;
+
-+ spin_lock(&mm->page_table_lock);
-+ do {
-+ pmd_t *pmd = pmd_alloc(mm, dir, from);
-+ error = -ENOMEM;
-+ if (!pmd)
++#ifdef CONFIG_PM
++ au1xxx_pm_access(LCD_pm_dev);
++#endif
++
++ plane = fbinfo2index(info);
++ print_dbg("au1200fb: ioctl %d on plane %d\n", cmd, plane);
++
++ if (cmd == AU1200_LCD_FB_IOCTL) {
++ au1200_lcd_iodata_t iodata;
++
++ if (copy_from_user(&iodata, (void *) arg, sizeof(au1200_lcd_iodata_t)))
++ return -EFAULT;
++
++ print_dbg("FB IOCTL called\n");
++
++ switch (iodata.subcmd)
++ {
++
++ case AU1200_LCD_SET_SCREEN:
++ print_dbg("AU1200_LCD_SET_SCREEN\n");
++ set_global(cmd, &iodata.global);
+ break;
-+ error = e1356_remap_pmd_range(mm, pmd, from, end - from, phys_addr + from, prot);
-+ if (error)
++
++ case AU1200_LCD_GET_SCREEN:
++ print_dbg("AU1200_LCD_GET_SCREEN\n");
++ get_global(cmd, &iodata.global);
+ break;
-+ from = (from + PGDIR_SIZE) & PGDIR_MASK;
-+ dir++;
-+ } while (from && (from < end));
-+ spin_unlock(&mm->page_table_lock);
-+ flush_tlb_range(mm, beg, end);
-+ return error;
-+}
-+#endif
-diff -urpNX dontdiff linux-2.6.12/drivers/video/epson1356fb.h linux_HEAD/drivers/video/epson1356fb.h
---- linux-2.6.12/drivers/video/epson1356fb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/video/epson1356fb.h 2002-08-15 11:27:24.000000000 +0200
-@@ -0,0 +1,646 @@
-+/*
-+ * epson1356fb.h -- Epson SED1356 Framebuffer Driver
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ * stevel at mvista.com or source at mvista.com
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
++
++ case AU1200_LCD_SET_WINDOW:
++ print_dbg("AU1200_LCD_SET_WINDOW\n");
++ set_window(plane, &iodata.window);
++ break;
++
++ case AU1200_LCD_GET_WINDOW:
++ print_dbg("AU1200_LCD_GET_WINDOW\n");
++ get_window(plane, &iodata.window);
++ break;
++
++ case AU1200_LCD_SET_PANEL:
++ print_dbg("AU1200_LCD_SET_PANEL\n");
++ if ((iodata.global.panel_choice >= 0) &&
++ (iodata.global.panel_choice <
++ NUM_PANELS))
++ {
++ struct panel_settings *newpanel;
++ panel_index = iodata.global.panel_choice;
++ newpanel = &known_lcd_panels[panel_index];
++ au1200_setpanel(newpanel);
++ }
++ break;
++
++ case AU1200_LCD_GET_PANEL:
++ print_dbg("AU1200_LCD_GET_PANEL\n");
++ iodata.global.panel_choice = panel_index;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ val = copy_to_user((void *) arg, &iodata, sizeof(au1200_lcd_iodata_t));
++ if (val) {
++ print_dbg("error: could not copy %d bytes\n", val);
++ return -EFAULT;
++ }
++ }
++
++return 0;
++}
+
-+#ifdef E1356FB_DEBUG
-+#define DPRINTK(a,b...) printk(KERN_DEBUG "e1356fb: %s: " a, __FUNCTION__ , ## b)
-+#else
-+#define DPRINTK(a,b...)
-+#endif
+
-+#define E1356_REG_SIZE 0x200000
++static struct fb_ops au1200fb_fb_ops =
++{
++ .owner = THIS_MODULE,
++ .fb_open = au1200fb_fb_open,
++ .fb_release = au1200fb_fb_release,
++ .fb_check_var = au1200fb_fb_check_var,
++ .fb_set_par = au1200fb_fb_set_par,
++ .fb_setcolreg = au1200fb_fb_setcolreg,
++ .fb_blank = au1200fb_fb_blank,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_sync = NULL,
++ .fb_ioctl = au1200fb_ioctl,
++ .fb_mmap = au1200fb_fb_mmap,
++};
+
-+#define PICOS2KHZ(a) (1000000000UL/(a))
-+#define KHZ2PICOS(a) (1000000000UL/(a))
++/*-------------------------------------------------------------------------*/
+
-+#define MAX_PIXCLOCK 40000 // KHz
-+#define NTSC_PIXCLOCK 14318 // KHz
-+#define PAL_PIXCLOCK 17734 // KHz
++static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id, struct pt_regs *regs)
++{
++ /* Nothing to do for now, just clear any pending interrupt */
++ lcd->intstatus = lcd->intstatus;
++ au_sync();
++ return IRQ_HANDLED;
++}
+
-+/*
-+ * Maximum percent errors between desired pixel clock and
-+ * supported pixel clock. Lower-than and higher-than desired
-+ * clock percent errors.
-+ */
-+#define MAX_PCLK_ERROR_LOWER 10
-+#define MAX_PCLK_ERROR_HIGHER -1
++/*-------------------------------------------------------------------------*/
+
-+#define fontwidth_x8(p) (((fontwidth(p) + 7) >> 3) << 3)
++/* AU1200 LCD device probe helpers */
+
-+/*
-+ * Register Structures
-+ */
++static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
++{
++ struct fb_info *fbi = &fbdev->fb_info;
++ int bpp;
++
++ memset(fbi, 0, sizeof(struct fb_info));
++ fbi->fbops = &au1200fb_fb_ops;
++
++ bpp = winbpp(win->w[fbdev->plane].mode_winctrl1);
+
-+// Basic
-+#define REG_BASE_BASIC 0x00
-+typedef struct {
-+ u8 rev_code; // 00
-+ u8 misc; // 01
-+} reg_basic_t;
++ /* Copy monitor specs from panel data */
++ /* fixme: we're setting up LCD controller windows, so these dont give a
++ damn as to what the monitor specs are (the panel itself does, but that
++ isnt done here...so maybe need a generic catchall monitor setting??? */
++ memcpy(&fbi->monspecs, &panel->monspecs, sizeof(struct fb_monspecs));
++
++ /* We first try the user mode passed in argument. If that failed,
++ * or if no one has been specified, we default to the first mode of the
++ * panel list. Note that after this call, var data will be set */
++ if (!fb_find_mode(&fbi->var,
++ fbi,
++ NULL, /* drv_info.opt_mode, */
++ fbi->monspecs.modedb,
++ fbi->monspecs.modedb_len,
++ fbi->monspecs.modedb,
++ bpp)) {
+
-+// General IO Pins
-+#define REG_BASE_GENIO 0x04
-+typedef struct {
-+ u8 gpio_cfg; // 04
-+ u8 gpio_cfg2; // 05 SED13806
-+ u8 spacer[2]; // 06
-+ u8 gpio_ctrl; // 08
-+ u8 gpio_ctrl2; // 09 SED13806
-+} reg_genio_t;
++ print_err("Cannot find valid mode for panel %s", panel->name);
++ return -EFAULT;
++ }
+
-+// MD Config Readback
-+#define REG_BASE_MDCFG 0x0c
-+typedef struct {
-+ u8 md_cfg_stat0; // 0C
-+ u8 md_cfg_stat1; // 0D
-+} reg_mdcfg_t;
++ fbi->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
++ if (!fbi->pseudo_palette) {
++ return -ENOMEM;
++ }
++ memset(fbi->pseudo_palette, 0, sizeof(u32) * 16);
+
-+// Clock Config
-+#define REG_BASE_CLKCFG 0x10
-+typedef struct {
-+ u8 mem_clk_cfg; // 10
-+ u8 spacer1[3]; // 11
-+ u8 lcd_pclk_cfg; // 14
-+ u8 spacer2[3]; // 15
-+ u8 crttv_pclk_cfg; // 18
-+ u8 spacer3[3]; // 19
-+ u8 mpclk_cfg; // 1C
-+ u8 spacer4; // 1D
-+ u8 cpu2mem_wait_sel; // 1E
-+} reg_clkcfg_t;
++ if (fb_alloc_cmap(&fbi->cmap, AU1200_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
++ print_err("Fail to allocate colormap (%d entries)",
++ AU1200_LCD_NBR_PALETTE_ENTRIES);
++ kfree(fbi->pseudo_palette);
++ return -EFAULT;
++ }
+
-+// Memory Config
-+#define REG_BASE_MEMCFG 0x20
-+typedef struct {
-+ u8 mem_cfg; // 20
-+ u8 dram_refresh; // 21
-+ u8 spacer[8]; // 22
-+ u8 dram_timings_ctrl0; // 2A
-+ u8 dram_timings_ctrl1; // 2B
-+} reg_memcfg_t;
++ strncpy(fbi->fix.id, "AU1200", sizeof(fbi->fix.id));
++ fbi->fix.smem_start = fbdev->fb_phys;
++ fbi->fix.smem_len = fbdev->fb_len;
++ fbi->fix.type = FB_TYPE_PACKED_PIXELS;
++ fbi->fix.xpanstep = 1;
++ fbi->fix.ypanstep = 1;
++ fbi->fix.mmio_start = 0;
++ fbi->fix.mmio_len = 0;
++ fbi->fix.accel = FB_ACCEL_NONE;
+
-+// Panel Config
-+#define REG_BASE_PANELCFG 0x30
-+typedef struct {
-+ u8 panel_type; // 30
-+ u8 mod_rate; // 31
-+} reg_panelcfg_t;
-+
-+// LCD and CRTTV Display Config
-+#define REG_BASE_LCD_DISPCFG 0x32
-+#define REG_BASE_CRTTV_DISPCFG 0x50
-+typedef struct {
-+ u8 hdw; // 32 or 50
-+ u8 spacer1; // 33 or 51
-+ u8 hndp; // 34 or 52
-+ u8 hsync_start; // 35 or 53
-+ u8 hsync_pulse; // 36 or 54
-+ u8 spacer2; // 37 or 55
-+ u8 vdh0; // 38 or 56
-+ u8 vdh1; // 39 or 57
-+ u8 vndp; // 3A or 58
-+ u8 vsync_start; // 3B or 59
-+ u8 vsync_pulse; // 3C or 5A
-+ u8 tv_output_ctrl; // 5B (TV only)
-+} reg_dispcfg_t;
-+
-+// LCD and CRTTV Display Mode
-+#define REG_BASE_LCD_DISPMODE 0x40
-+#define REG_BASE_CRTTV_DISPMODE 0x60
-+typedef struct {
-+ u8 disp_mode; // 40 or 60
-+ u8 lcd_misc; // 41 (LCD only)
-+ u8 start_addr0; // 42 or 62
-+ u8 start_addr1; // 43 or 63
-+ u8 start_addr2; // 44 or 64
-+ u8 spacer1; // 45 or 65
-+ u8 mem_addr_offset0; // 46 or 66
-+ u8 mem_addr_offset1; // 47 or 67
-+ u8 pixel_panning; // 48 or 68
-+ u8 spacer2; // 49 or 69
-+ u8 fifo_high_thresh; // 4A or 6A
-+ u8 fifo_low_thresh; // 4B or 6B
-+} reg_dispmode_t;
-+
-+// LCD and CRTTV Ink/Cursor
-+#define REG_BASE_LCD_INKCURS 0x70
-+#define REG_BASE_CRTTV_INKCURS 0x80
-+typedef struct {
-+ u8 ctrl; // 70 or 80
-+ u8 start_addr; // 71 or 81
-+ u8 x_pos0; // 72 or 82
-+ u8 x_pos1; // 73 or 83
-+ u8 y_pos0; // 74 or 84
-+ u8 y_pos1; // 75 or 85
-+ u8 blue0; // 76 or 86
-+ u8 green0; // 77 or 87
-+ u8 red0; // 78 or 88
-+ u8 spacer1; // 79 or 89
-+ u8 blue1; // 7A or 8A
-+ u8 green1; // 7B or 8B
-+ u8 red1; // 7C or 8C
-+ u8 spacer2; // 7D or 8D
-+ u8 fifo; // 7E or 8E
-+} reg_inkcurs_t;
++ fbi->screen_base = fbdev->fb_mem;
+
-+// BitBlt Config
-+#define REG_BASE_BITBLT 0x100
-+typedef struct {
-+ u8 ctrl0; // 100
-+ u8 ctrl1; // 101
-+ u8 rop_code; // 102
-+ u8 operation; // 103
-+ u8 src_start_addr0; // 104
-+ u8 src_start_addr1; // 105
-+ u8 src_start_addr2; // 106
-+ u8 spacer1; // 107
-+ u8 dest_start_addr0; // 108
-+ u8 dest_start_addr1; // 109
-+ u8 dest_start_addr2; // 10A
-+ u8 spacer2; // 10B
-+ u8 mem_addr_offset0; // 10C
-+ u8 mem_addr_offset1; // 10D
-+ u8 spacer3[2]; // 10E
-+ u8 width0; // 110
-+ u8 width1; // 111
-+ u8 height0; // 112
-+ u8 height1; // 113
-+ u8 bg_color0; // 114
-+ u8 bg_color1; // 115
-+ u8 spacer4[2]; // 116
-+ u8 fg_color0; // 118
-+ u8 fg_color1; // 119
-+} reg_bitblt_t;
++ au1200fb_update_fbinfo(fbi);
+
-+// LUT
-+#define REG_BASE_LUT 0x1e0
-+typedef struct {
-+ u8 mode; // 1E0
-+ u8 spacer1; // 1E1
-+ u8 addr; // 1E2
-+ u8 spacer2; // 1E3
-+ u8 data; // 1E4
-+} reg_lut_t;
++ return 0;
++}
+
-+// Power Save Config
-+#define REG_BASE_PWRSAVE 0x1f0
-+typedef struct {
-+ u8 cfg; // 1F0
-+ u8 status; // 1F1
-+} reg_pwrsave_t;
++/*-------------------------------------------------------------------------*/
+
-+// Misc
-+#define REG_BASE_MISC 0x1f4
-+typedef struct {
-+ u8 cpu2mem_watchdog; // 1F4
-+ u8 spacer[7]; // 1F5
-+ u8 disp_mode; // 1FC
-+} reg_misc_t;
++/* AU1200 LCD controller device driver */
+
-+// MediaPlug
-+#define REG_BASE_MEDIAPLUG 0x1000
-+typedef struct {
-+ u8 lcmd; // 1000
-+ u8 spacer1; // 1001
-+ u8 reserved_lcmd; // 1002
-+ u8 spacer2; // 1003
-+ u8 cmd; // 1004
-+ u8 spacer3; // 1005
-+ u8 reserved_cmd; // 1006
-+ u8 spacer4; // 1007
-+ u8 data; // 1008
-+} reg_mediaplug_t;
++int au1200fb_drv_probe(struct device *dev)
++{
++ struct au1200fb_device *fbdev;
++ unsigned long page;
++ int bpp, plane, ret;
+
-+// BitBlt data register. 16-bit access only
-+#define REG_BASE_BITBLT_DATA 0x100000
++ if (!dev)
++ return -EINVAL;
+
-+typedef struct {
-+ reg_basic_t* basic;
-+ reg_genio_t* genio;
-+ reg_mdcfg_t* md_cfg;
-+ reg_clkcfg_t* clk_cfg;
-+ reg_memcfg_t* mem_cfg;
-+ reg_panelcfg_t* panel_cfg;
-+ reg_dispcfg_t* lcd_cfg;
-+ reg_dispcfg_t* crttv_cfg;
-+ reg_dispmode_t* lcd_mode;
-+ reg_dispmode_t* crttv_mode;
-+ reg_inkcurs_t* lcd_inkcurs;
-+ reg_inkcurs_t* crttv_inkcurs;
-+ reg_bitblt_t* bitblt;
-+ reg_lut_t* lut;
-+ reg_pwrsave_t* pwr_save;
-+ reg_misc_t* misc;
-+ reg_mediaplug_t* mediaplug;
-+ u16* bitblt_data;
-+} e1356_reg_t;
-+
-+
-+/*--------------------------------------------------------*/
-+
-+enum mem_type_t {
-+ MEM_TYPE_EDO_2CAS = 0,
-+ MEM_TYPE_FPM_2CAS,
-+ MEM_TYPE_EDO_2WE,
-+ MEM_TYPE_FPM_2WE,
-+ MEM_TYPE_EMBEDDED_SDRAM = 0x80
-+};
++ for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane)
++ {
++ bpp = winbpp(win->w[plane].mode_winctrl1);
++ if (win->w[plane].xres == 0)
++ win->w[plane].xres = panel->Xres;
++ if (win->w[plane].yres == 0)
++ win->w[plane].yres = panel->Yres;
++
++ fbdev = &_au1200fb_devices[plane];
++ memset((void *)fbdev, 0, sizeof(struct au1200fb_device));
++ fbdev->plane = plane;
++
++ /* Allocate the framebuffer to the maximum screen size */
++ fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8;
++
++ fbdev->fb_mem = dma_alloc_noncoherent(dev,
++ PAGE_ALIGN(fbdev->fb_len),
++ &fbdev->fb_phys, GFP_KERNEL);
++ if (!fbdev->fb_mem) {
++ print_err("fail to allocate frambuffer (size: %dK))",
++ fbdev->fb_len / 1024);
++ return -ENOMEM;
++ }
+
-+enum mem_smr_t {
-+ MEM_SMR_CBR = 0,
-+ MEM_SMR_SELF,
-+ MEM_SMR_NONE
-+};
++ /*
++ * Set page reserved so that mmap will work. This is necessary
++ * since we'll be remapping normal memory.
++ */
++ for (page = (unsigned long)fbdev->fb_phys;
++ page < PAGE_ALIGN((unsigned long)fbdev->fb_phys +
++ fbdev->fb_len);
++ page += PAGE_SIZE) {
++ SetPageReserved(pfn_to_page(page >> PAGE_SHIFT)); /* LCD DMA is NOT coherent on Au1200 */
++ }
++ print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
++ print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
++
++ /* Init FB data */
++ if ((ret = au1200fb_init_fbinfo(fbdev)) < 0)
++ goto failed;
++
++ /* Register new framebuffer */
++ if ((ret = register_framebuffer(&fbdev->fb_info)) < 0) {
++ print_err("cannot register new framebuffer");
++ goto failed;
++ }
++
++ au1200fb_fb_set_par(&fbdev->fb_info);
+
-+enum disp_type_t {
-+ DISP_TYPE_LCD = 0,
-+ DISP_TYPE_TFT,
-+ DISP_TYPE_CRT,
-+ DISP_TYPE_PAL,
-+ DISP_TYPE_NTSC
-+};
++#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
++ if (plane == 0)
++ if (fb_prepare_logo(&fbdev->fb_info, FB_ROTATE_UR)) {
++ /* Start display and show logo on boot */
++ fb_set_cmap(&fbdev->fb_info.cmap,
++ &fbdev->fb_info);
+
-+/*
-+ * Maximum timing values, as determined by the SED1356 register
-+ * field sizes. All are indexed by display type, except
-+ * max_hsync_start which is first indexed by color depth,
-+ * then by display type.
-+ */
-+static const int max_hndp[5] = {256, 256, 512, 511, 510};
-+static const int max_hsync_start[2][5] = {
-+ {0, 252, 507, 505, 505}, // 8 bpp
-+ {0, 254, 509, 507, 507} // 16 bpp
-+};
-+static const int max_hsync_width[5] = {0, 128, 128, 0, 0};
-+static const int max_vndp[5] = {64, 64, 128, 128, 128};
-+static const int max_vsync_start[5] = {0, 64, 128, 128, 128};
-+static const int max_vsync_width[5] = {0, 8, 8, 0, 0};
-+
-+#define IS_PANEL(disp_type) \
-+ (disp_type == DISP_TYPE_LCD || disp_type == DISP_TYPE_TFT)
-+#define IS_CRT(disp_type) (disp_type == DISP_TYPE_CRT)
-+#define IS_TV(disp_type) \
-+ (disp_type == DISP_TYPE_NTSC || disp_type == DISP_TYPE_PAL)
-+
-+
-+enum tv_filters_t {
-+ TV_FILT_LUM = 1,
-+ TV_FILT_CHROM = 2,
-+ TV_FILT_FLICKER = 4
-+};
++ fb_show_logo(&fbdev->fb_info, FB_ROTATE_UR);
++ }
++#endif
++ }
+
-+enum tv_format_t {
-+ TV_FMT_COMPOSITE = 0,
-+ TV_FMT_S_VIDEO
-+};
++ /* Now hook interrupt too */
++ if ((ret = request_irq(AU1200_LCD_INT, au1200fb_handle_irq,
++ SA_INTERRUPT | SA_SHIRQ, "lcd", (void *)dev)) < 0) {
++ print_err("fail to request interrupt line %d (err: %d)",
++ AU1200_LCD_INT, ret);
++ goto failed;
++ }
+
++ return 0;
+
-+struct e1356fb_fix {
-+ int system; // the number of a pre-packaged system
-+ u64 regbase_phys; // phys start address of registers
-+ u64 membase_phys; // phys start address of fb memory
-+
-+ // Memory parameters
-+ int mem_speed; // speed: 50, 60, 70, or 80 (nsec)
-+ int mem_type; // mem type: EDO-2CAS, FPM-2CAS, EDO-2WE, FPM-2WE
-+ int mem_refresh; // refresh rate in KHz
-+ int mem_smr; // suspend mode refresh: CAS_BEFORE_RAS, SELF, or NONE
-+ // Clocks
-+ int busclk; // BUSCLK frequency, in KHz
-+ int mclk; // MCLK freq, in KHz, will either be BUSCLK or BUSCLK/2
-+ int clki; // CLKI frequency, in KHz
-+ int clki2; // CLKI2 frequency, in KHz
-+
-+ int disp_type; // LCD, TFT, CRT, PAL, or NTSC
-+
-+ // TV Options
-+ u8 tv_filt; // TV Filter mask, LUM, CHROM, and FLICKER
-+ int tv_fmt; // TV output format, COMPOSITE or S_VIDEO
-+
-+ // Panel (LCD,TFT) Options
-+ int panel_el; // enable support for EL-type panels
-+ int panel_width; // Panel data width: LCD: 4/8/16, TFT: 9/12/18
-+
-+ // Misc
-+ int noaccel;
-+ int nopan;
-+#ifdef CONFIG_MTRR
-+ int nomtrr;
-+#endif
-+ int nohwcursor;
-+ int mmunalign; // force unaligned returned VA in mmap()
-+ char fontname[40];
++failed:
++ /* NOTE: This only does the current plane/window that failed; others are still active */
++ if (fbdev->fb_mem)
++ dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
++ fbdev->fb_mem, fbdev->fb_phys);
++ if (fbdev->fb_info.cmap.len != 0)
++ fb_dealloc_cmap(&fbdev->fb_info.cmap);
++ if (fbdev->fb_info.pseudo_palette)
++ kfree(fbdev->fb_info.pseudo_palette);
++ if (plane == 0)
++ free_irq(AU1200_LCD_INT, (void*)dev);
++ return ret;
++}
+
-+ char *mode_option;
-+};
++int au1200fb_drv_remove(struct device *dev)
++{
++ struct au1200fb_device *fbdev;
++ int plane;
+
++ if (!dev)
++ return -ENODEV;
+
-+typedef struct {
-+ int pixclk_d; // Desired Pixel Clock, KHz
-+ int pixclk; // Closest supported clock to desired clock, KHz
-+ int error; // percent error between pixclock and pixclock_d
-+ int clksrc; // equal to busclk, mclk, clki, or clki2, KHz
-+ int divisor; // pixclk = clksrc/divisor, where divisor = 1,2,3, or 4
-+ u8 pixclk_bits; // pixclock register value for above settings
-+} pixclock_info_t;
-+
-+
-+struct e1356fb_par {
-+ int width;
-+ int height;
-+ int width_virt; // Width in pixels
-+ int height_virt; // Height in lines
-+ int bpp; // bits-per-pixel
-+ int Bpp; // Bytes-per-pixel
-+
-+ // Timing
-+ pixclock_info_t ipclk;
-+ int horiz_ndp; // Horiz. Non-Display Period, pixels
-+ int vert_ndp; // Vert. Non-Display Period, lines
-+ int hsync_pol; // Polarity of horiz. sync signal (HRTC for CRT/TV,
-+ // FPLINE for TFT). 0=active lo, 1=active hi
-+ int hsync_start; // Horiz. Sync Start position, pixels
-+ int hsync_width; // Horiz. Sync Pulse width, pixels
-+ int hsync_freq; // calculated horizontal sync frequency
-+ int vsync_pol; // Polarity of vert. sync signal (VRTC for CRT/TV,
-+ // FPFRAME for TFT). 0=active lo, 1=active hi
-+ int vsync_start; // Vert. Sync Start position, lines
-+ int vsync_width; // Vert. Sync Pulse width, lines
-+ int vsync_freq; // calculated vertical sync frequency
++ /* Turn off the panel */
++ au1200_setpanel(NULL);
+
-+ int cmap_len; // color-map length
-+};
++ for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane)
++ {
++ fbdev = &_au1200fb_devices[plane];
+
++ /* Clean up all probe data */
++ unregister_framebuffer(&fbdev->fb_info);
++ if (fbdev->fb_mem)
++ dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len),
++ fbdev->fb_mem, fbdev->fb_phys);
++ if (fbdev->fb_info.cmap.len != 0)
++ fb_dealloc_cmap(&fbdev->fb_info.cmap);
++ if (fbdev->fb_info.pseudo_palette)
++ kfree(fbdev->fb_info.pseudo_palette);
++ }
+
++ free_irq(AU1200_LCD_INT, (void *)dev);
+
-+struct fb_info_e1356 {
-+ struct fb_info fb_info;
++ return 0;
++}
+
-+ void *regbase_virt;
-+ unsigned long regbase_size;
-+ void *membase_virt;
-+ unsigned long fb_size;
++int au1200fb_drv_suspend(struct device *dev, u32 state, u32 level)
++{
++ /* TODO */
++ return 0;
++}
+
-+ e1356_reg_t reg;
++int au1200fb_drv_resume(struct device *dev, u32 level)
++{
++ /* TODO */
++ return 0;
++}
+
-+ void* putcs_buffer;
-+
-+ int max_pixclock; // Max supported pixel clock, KHz
-+ int open, mmaped; // open count, is mmap'ed
-+
-+ u8 chip_rev;
-+
-+#ifdef CONFIG_MTRR
-+ int mtrr_idx;
++static struct device_driver au1200fb_driver = {
++ .name = "au1200-lcd",
++ .bus = &platform_bus_type,
++ .probe = au1200fb_drv_probe,
++ .remove = au1200fb_drv_remove,
++#ifdef CONFIG_PM
++ .suspend = au1200fb_drv_suspend,
++ .resume = au1200fb_drv_resume,
+#endif
++};
+
-+#ifdef SHADOW_FRAME_BUFFER
-+ struct {
-+ void* fb;
-+ struct timer_list timer;
-+ } shadow;
-+#endif
++/*-------------------------------------------------------------------------*/
+
-+ struct { unsigned red, green, blue, pad; } palette[256];
-+ struct display disp;
++/* Kernel driver */
+
-+#if defined(FBCON_HAS_CFB16)
-+ u16 fbcon_cmap16[16];
-+#endif
-+
-+ struct {
-+ int type;
-+ int state;
-+ int w,h,u;
-+ int x,y,redraw;
-+ unsigned long enable,disable;
-+ struct timer_list timer;
-+ spinlock_t lock;
-+ } cursor;
-+
-+ struct e1356fb_fix fix;
-+ struct e1356fb_par default_par;
-+ struct e1356fb_par current_par;
-+};
++static void au1200fb_setup(void)
++{
++ char* options = NULL;
++ char* this_opt;
++ int num_panels = ARRAY_SIZE(known_lcd_panels);
++ int panel_idx = -1;
+
++ fb_get_options(DRIVER_NAME, &options);
+
-+// The following are boot options for particular SED1356-based target systems
++ if (options) {
++ while ((this_opt = strsep(&options,",")) != NULL) {
++ /* Panel option - can be panel name,
++ * "bs" for board-switch, or number/index */
++ if (!strncmp(this_opt, "panel:", 6)) {
++ int i;
++ long int li;
++ char *endptr;
++ this_opt += 6;
++ /* First check for index, which allows
++ * to short circuit this mess */
++ li = simple_strtol(this_opt, &endptr, 0);
++ if (*endptr == '\0') {
++ panel_idx = (int)li;
++ }
++ else if (strcmp(this_opt, "bs") == 0) {
++ extern int board_au1200fb_panel(void);
++ panel_idx = board_au1200fb_panel();
++ }
+
-+enum {
-+ SYS_NULL,
-+ SYS_PB1000,
-+ SYS_PB1500,
-+ SYS_SDU1356,
-+ SYS_CLIO1050,
-+ NUM_SYSTEMS // must be last
-+};
++ else
++ for (i = 0; i < num_panels; i++) {
++ if (!strcmp(this_opt, known_lcd_panels[i].name)) {
++ panel_idx = i;
++ break;
++ }
++ }
+
-+static struct {
-+ struct e1356fb_fix fix;
-+ struct e1356fb_par par;
-+} systems[NUM_SYSTEMS] = {
++ if ((panel_idx < 0) || (panel_idx >= num_panels)) {
++ print_warn("Panel %s not supported!", this_opt);
++ }
++ else
++ panel_index = panel_idx;
++ }
+
-+ /*
-+ * NULL system to help us detect missing options
-+ * when the driver is compiled as a module.
-+ */
-+ {
-+ { // fix
-+ SYS_NULL,
-+ },
-+ { // par
++ else if (strncmp(this_opt, "nohwcursor", 10) == 0) {
++ nohwcursor = 1;
++ }
++
++ /* Unsupported option */
++ else {
++ print_warn("Unsupported option \"%s\"", this_opt);
++ }
+ }
-+ },
++ }
++}
+
-+ /*
-+ * Alchemy Pb1000 evaluation board, SED1356
-+ */
-+ {
-+ { // fix
-+ SYS_PB1000,
-+ /*
-+ * Note!: these are "pseudo" physical addresses;
-+ * the SED1356 is not actually mapped here, but rather
-+ * at the 36-bit address of 0xE 0000 0000. There is an
-+ * ugly hack in the Au1000 TLB refill handler that will
-+ * translate pte_t's in the range 0xE000 0000 -->
-+ * 0xEFFF FFFF to the 36-bit range 0xE 0000 0000 -->
-+ * 0xE 0FFF FFFF. The long-term solution is to support
-+ * 36-bit physical addresses in linux-mips32 mm, since
-+ * the mips32 specification specifically supports this.
-+ */
-+ 0xE00000000, 0xE00200000,
-+ 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
-+ 0, 0, // BUSCLK and MCLK are calculated at run-time
-+ 40000, 14318, // CLKI, CLKI2
-+#ifdef CONFIG_PB1000_CRT
-+ DISP_TYPE_CRT,
-+ 0, 0, // TV Options
-+ 0, 0, // Panel options
-+#elif defined (CONFIG_PB1000_NTSC)
-+ DISP_TYPE_NTSC,
-+ TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM,
-+ TV_FMT_COMPOSITE,
-+ 0, 0, // Panel options
-+#elif defined (CONFIG_PB1000_TFT)
-+ DISP_TYPE_TFT,
-+ 0, 0, // TV Options
-+ 0, 12, // Panel options, EL panel?, data width?
-+#else
-+ DISP_TYPE_PAL,
-+ TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM,
-+ TV_FMT_COMPOSITE,
-+ 0, 0, // Panel options
-+#endif
-+ 0, 0,
-+#ifdef CONFIG_MTRR
-+ 0,
-+#endif
-+ 0,
-+ 0,
-+ {0},
-+ "800x600 at 60"
-+ },
-+ { // par
-+ 0, 0, 800, 600, 8, 1,
-+ // timings will be set by modedb
-+ {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+ 256
++#ifdef CONFIG_PM
++int au1200fb_pm_callback(au1xxx_power_dev_t *dev,
++ au1xxx_request_t request, void *data) {
++ int retval = -1;
++ unsigned int d = 0;
++ unsigned int brightness = 0;
++
++ if (request == AU1XXX_PM_SLEEP) {
++ board_au1200fb_panel_shutdown();
++ }
++ else if (request == AU1XXX_PM_WAKEUP) {
++ if(dev->prev_state == SLEEP_STATE)
++ {
++ int plane;
++ au1200_setpanel(panel);
++ for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) {
++ struct au1200fb_device *fbdev;
++ fbdev = &_au1200fb_devices[plane];
++ au1200fb_fb_set_par(&fbdev->fb_info);
++ }
+ }
-+ },
+
-+ /*
-+ * Alchemy Pb1500 evaluation board, SED13806
-+ */
-+ {
-+ { // fix
-+ SYS_PB1500,
-+ /*
-+ * Note!: these are "pseudo" physical addresses;
-+ * the SED1356 is not actually mapped here, but rather
-+ * at the 36-bit address of 0xE 0000 0000. There is an
-+ * ugly hack in the Au1000 TLB refill handler that will
-+ * translate pte_t's in the range 0xE000 0000 -->
-+ * 0xEFFF FFFF to the 36-bit range 0xE 0000 0000 -->
-+ * 0xE 0FFF FFFF. The long-term solution is to support
-+ * 36-bit physical addresses in linux-mips32 mm, since
-+ * the mips32 specification specifically supports this.
-+ */
-+ 0xE1B000000, 0xE1B200000,
-+ 50, MEM_TYPE_EMBEDDED_SDRAM, 64, MEM_SMR_CBR,
-+ 0, 0, // BUSCLK and MCLK are calculated at run-time
-+ 40000, 14318, // CLKI, CLKI2
-+#ifdef CONFIG_PB1500_CRT
-+ DISP_TYPE_CRT,
-+ 0, 0, // TV Options
-+ 0, 0, // Panel options
-+#else
-+ DISP_TYPE_TFT,
-+ 0, 0, // TV Options
-+ 0, 12, // Panel options, EL panel?, data width?
-+#endif
-+ 0, 0,
-+#ifdef CONFIG_MTRR
-+ 0,
-+#endif
-+ 0,
-+ 0,
-+ {0},
-+ "800x600 at 60"
-+ },
-+ { // par
-+ 0, 0, 800, 600, 8, 1,
-+ // timings will be set by modedb
-+ {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+ 256
++ d = *((unsigned int*)data);
++ if(d <=10) brightness = 26;
++ else if(d<=20) brightness = 51;
++ else if(d<=30) brightness = 77;
++ else if(d<=40) brightness = 102;
++ else if(d<=50) brightness = 128;
++ else if(d<=60) brightness = 153;
++ else if(d<=70) brightness = 179;
++ else if(d<=80) brightness = 204;
++ else if(d<=90) brightness = 230;
++ else brightness = 255;
++ set_brightness(brightness);
++ }
++ else if (request == AU1XXX_PM_GETSTATUS) {
++ return dev->cur_state;
++ }
++ else if (request == AU1XXX_PM_ACCESS) {
++ if (dev->cur_state != SLEEP_STATE)
++ return retval;
++ else {
++ au1200_setpanel(panel);
+ }
-+ },
++ }
++ else if (request == AU1XXX_PM_IDLE) {
++ }
++ else if (request == AU1XXX_PM_CLEANUP) {
++ }
+
-+ /*
-+ * Epson SDU1356B0C PCI eval card. These settings assume the
-+ * card is configured for PCI, the MediaPlug is disabled,
-+ * and the onboard clock synthesizer is at the power-up
-+ * clock settings.
-+ */
-+ {
-+ { // fix
-+ SYS_SDU1356,
-+ 0x0, 0x0, // addresses obtained from PCI config space
-+ // FIXME: just guess for now
-+ 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
-+ 33000, 0, 40000, 25175, // BUSCLK, MCLK, CLKI, CLKI2
-+ DISP_TYPE_CRT,
-+ 0, 0,
-+ 0, 0,
-+ 0, 0,
-+#ifdef CONFIG_MTRR
-+ 0,
++ return retval;
++}
+#endif
-+ 0,
-+ 0,
-+ {0},
-+ "800x600 at 60"
-+ },
-+ { // par
-+ 0, 0, 1024, 768, 8, 1,
-+ // timings will be set by modedb
-+ {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+ 256
-+ }
-+ },
+
-+ /*
-+ * Vadem Clio 1050 - this is for the benefit of the Linux-VR project.
-+ * FIXME: Most of these settings are just guesses, until I can get a
-+ * Clio 1050 and dump the registers that WinCE has setup.
-+ */
++int __init au1200fb_init(void)
++{
++ print_info("" DRIVER_DESC "");
++
++ /* Setup driver with options */
++ au1200fb_setup();
++
++ /* Point to the panel selected */
++ panel = &known_lcd_panels[panel_index];
++ win = &windows[window_index];
++
++ printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
++ printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
++
++ /* Kickstart the panel, the framebuffers/windows come soon enough */
++ au1200_setpanel(panel);
++
++ #ifdef CONFIG_PM
++ LCD_pm_dev = new_au1xxx_power_device("LCD", &au1200fb_pm_callback, NULL);
++ if ( LCD_pm_dev == NULL)
++ printk(KERN_INFO "Unable to create a power management device entry for the au1200fb.\n");
++ else
++ printk(KERN_INFO "Power management device entry for the au1200fb loaded.\n");
++ #endif
++
++ return driver_register(&au1200fb_driver);
++}
++
++void __exit au1200fb_cleanup(void)
++{
++ driver_unregister(&au1200fb_driver);
++}
++
++module_init(au1200fb_init);
++module_exit(au1200fb_cleanup);
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL");
+diff -urN --ignore-space-change kernel.org/drivers/video/au1200fb.h linux-mips/drivers/video/au1200fb.h
+--- kernel.org/drivers/video/au1200fb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/video/au1200fb.h 2006-01-10 11:21:49.000000000 +0000
+@@ -0,0 +1,288 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ * Hardware definitions for the Au1200 LCD controller
++ *
++ * Copyright 2004 AMD
++ * Author: AMD
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#ifndef _AU1200LCD_H
++#define _AU1200LCD_H
++
++/********************************************************************/
++#define AU1200_LCD_ADDR 0xB5000000
++
++#define uint8 unsigned char
++#define uint32 unsigned int
++
++typedef volatile struct
++{
++ uint32 reserved0;
++ uint32 screen;
++ uint32 backcolor;
++ uint32 horztiming;
++ uint32 verttiming;
++ uint32 clkcontrol;
++ uint32 pwmdiv;
++ uint32 pwmhi;
++ uint32 reserved1;
++ uint32 winenable;
++ uint32 colorkey;
++ uint32 colorkeymsk;
++ struct
+ {
-+ { // fix
-+ SYS_CLIO1050,
-+ 0x0a000000, 0x0a200000,
-+ 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
-+ 40000, 40000, 14318, 14318,
-+ DISP_TYPE_TFT,
-+ 0, 0,
-+ 0, 16,
-+ 0, 0,
-+#ifdef CONFIG_MTRR
-+ 0,
-+#endif
-+ 0,
-+ 0,
-+ {0},
-+ "640x480 at 85"
-+ },
-+ { // par
-+ 0, 0, 1024, 768, 16, 2,
-+ // timings will be set by modedb
-+ {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+ 16
-+ }
-+ }
-+};
-diff -urpNX dontdiff linux-2.6.12/drivers/video/gbefb.c linux_HEAD/drivers/video/gbefb.c
---- linux-2.6.12/drivers/video/gbefb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/gbefb.c 2005-07-10 12:28:27.000000000 +0200
-@@ -1126,7 +1126,7 @@ static int __init gbefb_probe(struct dev
- gbefb_setup(options);
- #endif
-
-- if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
-+ if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
- printk(KERN_ERR "gbefb: couldn't reserve mmio region\n");
- ret = -EBUSY;
- goto out_release_framebuffer;
-@@ -1152,12 +1152,24 @@ static int __init gbefb_probe(struct dev
- if (gbe_mem_phys) {
- /* memory was allocated at boot time */
- gbe_mem = ioremap_nocache(gbe_mem_phys, gbe_mem_size);
-+ if (!gbe_mem) {
-+ printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
-+ ret = -ENOMEM;
-+ goto out_tiles_free;
-+ }
++ uint32 cursorctrl;
++ uint32 cursorpos;
++ uint32 cursorcolor0;
++ uint32 cursorcolor1;
++ uint32 cursorcolor2;
++ uint32 cursorcolor3;
++ } hwc;
++ uint32 intstatus;
++ uint32 intenable;
++ uint32 outmask;
++ uint32 fifoctrl;
++ uint32 reserved2[(0x0100-0x0058)/4];
++ struct
++ {
++ uint32 winctrl0;
++ uint32 winctrl1;
++ uint32 winctrl2;
++ uint32 winbuf0;
++ uint32 winbuf1;
++ uint32 winbufctrl;
++ uint32 winreserved0;
++ uint32 winreserved1;
++ } window[4];
++
++ uint32 reserved3[(0x0400-0x0180)/4];
++
++ uint32 palette[(0x0800-0x0400)/4];
++
++ uint8 cursorpattern[256];
++
++} AU1200_LCD;
++
++/* lcd_screen */
++#define LCD_SCREEN_SEN (1<<31)
++#define LCD_SCREEN_SX (0x07FF<<19)
++#define LCD_SCREEN_SY (0x07FF<< 8)
++#define LCD_SCREEN_SWP (1<<7)
++#define LCD_SCREEN_SWD (1<<6)
++#define LCD_SCREEN_PT (7<<0)
++#define LCD_SCREEN_PT_TFT (0<<0)
++#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
++#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
++#define LCD_SCREEN_PT_CSTN (1<<0)
++#define LCD_SCREEN_PT_CDSTN (2<<0)
++#define LCD_SCREEN_PT_M8STN (3<<0)
++#define LCD_SCREEN_PT_M4STN (4<<0)
++
++/* lcd_backcolor */
++#define LCD_BACKCOLOR_SBGR (0xFF<<16)
++#define LCD_BACKCOLOR_SBGG (0xFF<<8)
++#define LCD_BACKCOLOR_SBGB (0xFF<<0)
++#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16)
++#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8)
++#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0)
++
++/* lcd_winenable */
++#define LCD_WINENABLE_WEN3 (1<<3)
++#define LCD_WINENABLE_WEN2 (1<<2)
++#define LCD_WINENABLE_WEN1 (1<<1)
++#define LCD_WINENABLE_WEN0 (1<<0)
++
++/* lcd_colorkey */
++#define LCD_COLORKEY_CKR (0xFF<<16)
++#define LCD_COLORKEY_CKG (0xFF<<8)
++#define LCD_COLORKEY_CKB (0xFF<<0)
++#define LCD_COLORKEY_CKR_N(N) ((N)<<16)
++#define LCD_COLORKEY_CKG_N(N) ((N)<<8)
++#define LCD_COLORKEY_CKB_N(N) ((N)<<0)
++
++/* lcd_colorkeymsk */
++#define LCD_COLORKEYMSK_CKMR (0xFF<<16)
++#define LCD_COLORKEYMSK_CKMG (0xFF<<8)
++#define LCD_COLORKEYMSK_CKMB (0xFF<<0)
++#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16)
++#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8)
++#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0)
++
++/* lcd windows control 0 */
++#define LCD_WINCTRL0_OX (0x07FF<<21)
++#define LCD_WINCTRL0_OY (0x07FF<<10)
++#define LCD_WINCTRL0_A (0x00FF<<2)
++#define LCD_WINCTRL0_AEN (1<<1)
++#define LCD_WINCTRL0_OX_N(N) ((N)<<21)
++#define LCD_WINCTRL0_OY_N(N) ((N)<<10)
++#define LCD_WINCTRL0_A_N(N) ((N)<<2)
++
++/* lcd windows control 1 */
++#define LCD_WINCTRL1_PRI (3<<30)
++#define LCD_WINCTRL1_PIPE (1<<29)
++#define LCD_WINCTRL1_FRM (0xF<<25)
++#define LCD_WINCTRL1_CCO (1<<24)
++#define LCD_WINCTRL1_PO (3<<22)
++#define LCD_WINCTRL1_SZX (0x07FF<<11)
++#define LCD_WINCTRL1_SZY (0x07FF<<0)
++#define LCD_WINCTRL1_FRM_1BPP (0<<25)
++#define LCD_WINCTRL1_FRM_2BPP (1<<25)
++#define LCD_WINCTRL1_FRM_4BPP (2<<25)
++#define LCD_WINCTRL1_FRM_8BPP (3<<25)
++#define LCD_WINCTRL1_FRM_12BPP (4<<25)
++#define LCD_WINCTRL1_FRM_16BPP655 (5<<25)
++#define LCD_WINCTRL1_FRM_16BPP565 (6<<25)
++#define LCD_WINCTRL1_FRM_16BPP556 (7<<25)
++#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25)
++#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25)
++#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25)
++#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25)
++#define LCD_WINCTRL1_FRM_24BPP (12<<25)
++#define LCD_WINCTRL1_FRM_32BPP (13<<25)
++#define LCD_WINCTRL1_PRI_N(N) ((N)<<30)
++#define LCD_WINCTRL1_PO_00 (0<<22)
++#define LCD_WINCTRL1_PO_01 (1<<22)
++#define LCD_WINCTRL1_PO_10 (2<<22)
++#define LCD_WINCTRL1_PO_11 (3<<22)
++#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11)
++#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0)
++
++/* lcd windows control 2 */
++#define LCD_WINCTRL2_CKMODE (3<<24)
++#define LCD_WINCTRL2_DBM (1<<23)
++#define LCD_WINCTRL2_RAM (3<<21)
++#define LCD_WINCTRL2_BX (0x1FFF<<8)
++#define LCD_WINCTRL2_SCX (0xF<<4)
++#define LCD_WINCTRL2_SCY (0xF<<0)
++#define LCD_WINCTRL2_CKMODE_00 (0<<24)
++#define LCD_WINCTRL2_CKMODE_01 (1<<24)
++#define LCD_WINCTRL2_CKMODE_10 (2<<24)
++#define LCD_WINCTRL2_CKMODE_11 (3<<24)
++#define LCD_WINCTRL2_RAM_NONE (0<<21)
++#define LCD_WINCTRL2_RAM_PALETTE (1<<21)
++#define LCD_WINCTRL2_RAM_GAMMA (2<<21)
++#define LCD_WINCTRL2_RAM_BUFFER (3<<21)
++#define LCD_WINCTRL2_BX_N(N) ((N)<<8)
++#define LCD_WINCTRL2_SCX_1 (0<<4)
++#define LCD_WINCTRL2_SCX_2 (1<<4)
++#define LCD_WINCTRL2_SCX_4 (2<<4)
++#define LCD_WINCTRL2_SCY_1 (0<<0)
++#define LCD_WINCTRL2_SCY_2 (1<<0)
++#define LCD_WINCTRL2_SCY_4 (2<<0)
++
++/* lcd windows buffer control */
++#define LCD_WINBUFCTRL_DB (1<<1)
++#define LCD_WINBUFCTRL_DBN (1<<0)
++
++/* lcd_intstatus, lcd_intenable */
++#define LCD_INT_IFO (0xF<<14)
++#define LCD_INT_IFU (0xF<<10)
++#define LCD_INT_OFO (1<<9)
++#define LCD_INT_OFU (1<<8)
++#define LCD_INT_WAIT (1<<3)
++#define LCD_INT_SD (1<<2)
++#define LCD_INT_SA (1<<1)
++#define LCD_INT_SS (1<<0)
++
++/* lcd_horztiming */
++#define LCD_HORZTIMING_HND2 (0x1FF<<18)
++#define LCD_HORZTIMING_HND1 (0x1FF<<9)
++#define LCD_HORZTIMING_HPW (0x1FF<<0)
++#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
++#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
++#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0)
++
++/* lcd_verttiming */
++#define LCD_VERTTIMING_VND2 (0x1FF<<18)
++#define LCD_VERTTIMING_VND1 (0x1FF<<9)
++#define LCD_VERTTIMING_VPW (0x1FF<<0)
++#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
++#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
++#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0)
++
++/* lcd_clkcontrol */
++#define LCD_CLKCONTROL_EXT (1<<22)
++#define LCD_CLKCONTROL_DELAY (3<<20)
++#define LCD_CLKCONTROL_CDD (1<<19)
++#define LCD_CLKCONTROL_IB (1<<18)
++#define LCD_CLKCONTROL_IC (1<<17)
++#define LCD_CLKCONTROL_IH (1<<16)
++#define LCD_CLKCONTROL_IV (1<<15)
++#define LCD_CLKCONTROL_BF (0x1F<<10)
++#define LCD_CLKCONTROL_PCD (0x3FF<<0)
++#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
++#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
++
++/* lcd_pwmdiv */
++#define LCD_PWMDIV_EN (1<<31)
++#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0)
++#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0)
++
++/* lcd_pwmhi */
++#define LCD_PWMHI_PWMHI1 (0xFFFF<<16)
++#define LCD_PWMHI_PWMHI0 (0xFFFF<<0)
++#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16)
++#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
++
++/* lcd_hwccon */
++#define LCD_HWCCON_EN (1<<0)
++
++/* lcd_cursorpos */
++#define LCD_CURSORPOS_HWCXOFF (0x1F<<27)
++#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16)
++#define LCD_CURSORPOS_HWCYOFF (0x1F<<11)
++#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0)
++#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27)
++#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16)
++#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11)
++#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0)
++
++/* lcd_cursorcolor */
++#define LCD_CURSORCOLOR_HWCA (0xFF<<24)
++#define LCD_CURSORCOLOR_HWCR (0xFF<<16)
++#define LCD_CURSORCOLOR_HWCG (0xFF<<8)
++#define LCD_CURSORCOLOR_HWCB (0xFF<<0)
++#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24)
++#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16)
++#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8)
++#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0)
++
++/* lcd_fifoctrl */
++#define LCD_FIFOCTRL_F3IF (1<<29)
++#define LCD_FIFOCTRL_F3REQ (0x1F<<24)
++#define LCD_FIFOCTRL_F2IF (1<<29)
++#define LCD_FIFOCTRL_F2REQ (0x1F<<16)
++#define LCD_FIFOCTRL_F1IF (1<<29)
++#define LCD_FIFOCTRL_F1REQ (0x1F<<8)
++#define LCD_FIFOCTRL_F0IF (1<<29)
++#define LCD_FIFOCTRL_F0REQ (0x1F<<0)
++#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24)
++#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16)
++#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8)
++#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0)
+
- gbe_dma_addr = 0;
- } else {
- /* try to allocate memory with the classical allocator
- * this has high chance to fail on low memory machines */
- gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr,
- GFP_KERNEL);
-+ if (!gbe_mem) {
-+ printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n");
-+ ret = -ENOMEM;
-+ goto out_tiles_free;
-+ }
++/* lcd_outmask */
++#define LCD_OUTMASK_MASK (0x00FFFFFF)
+
- gbe_mem_phys = (unsigned long) gbe_dma_addr;
- }
-
-@@ -1165,12 +1177,6 @@ static int __init gbefb_probe(struct dev
- mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1);
- #endif
-
-- if (!gbe_mem) {
-- printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
-- ret = -ENXIO;
-- goto out_tiles_free;
-- }
--
- /* map framebuffer memory into tiles table */
- for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++)
- gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i;
-diff -urpNX dontdiff linux-2.6.12/drivers/video/pmag-aa-fb.c linux_HEAD/drivers/video/pmag-aa-fb.c
---- linux-2.6.12/drivers/video/pmag-aa-fb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/pmag-aa-fb.c 2005-07-10 12:28:27.000000000 +0200
-@@ -413,7 +413,7 @@ static struct fb_ops aafb_ops = {
-
- static int __init init_one(int slot)
- {
-- unsigned long base_addr = get_tc_base_addr(slot);
-+ unsigned long base_addr = CKSEG1ADDR(get_tc_base_addr(slot));
- struct aafb_info *ip = &my_fb_info[slot];
-
- memset(ip, 0, sizeof(struct aafb_info));
-diff -urpNX dontdiff linux-2.6.12/drivers/video/pmag-ba-fb.c linux_HEAD/drivers/video/pmag-ba-fb.c
---- linux-2.6.12/drivers/video/pmag-ba-fb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/pmag-ba-fb.c 2005-07-10 12:28:27.000000000 +0200
-@@ -122,7 +122,7 @@ static struct fb_ops pmagbafb_ops = {
-
- int __init pmagbafb_init_one(int slot)
- {
-- unsigned long base_addr = get_tc_base_addr(slot);
-+ unsigned long base_addr = CKSEG1ADDR(get_tc_base_addr(slot));
- struct fb_info *info = &pmagba_fb_info[slot];
- struct display *disp = &pmagba_disp[slot];
-
-diff -urpNX dontdiff linux-2.6.12/drivers/video/pmagb-b-fb.c linux_HEAD/drivers/video/pmagb-b-fb.c
---- linux-2.6.12/drivers/video/pmagb-b-fb.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/drivers/video/pmagb-b-fb.c 2005-07-03 16:44:35.000000000 +0200
-@@ -123,7 +123,7 @@ static struct fb_ops pmagbbfb_ops = {
-
- int __init pmagbbfb_init_one(int slot)
- {
-- unsigned long base_addr = get_tc_base_addr(slot);
-+ unsigned long base_addr = CKSEG1ADDR(get_tc_base_addr(slot));
- struct fb_info *info = &pmagbb_fb_info[slot];
-
- printk("PMAGB-BA framebuffer in slot %d\n", slot);
-diff -urpNX dontdiff linux-2.6.12/drivers/video/smivgxfb.c linux_HEAD/drivers/video/smivgxfb.c
---- linux-2.6.12/drivers/video/smivgxfb.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/video/smivgxfb.c 2005-04-21 07:02:30.000000000 +0200
-@@ -0,0 +1,316 @@
++/********************************************************************/
++#endif /* _AU1200LCD_H */
+diff -urN --ignore-space-change kernel.org/drivers/video/smivgxfb.c linux-mips/drivers/video/smivgxfb.c
+--- kernel.org/drivers/video/smivgxfb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/drivers/video/smivgxfb.c 2006-01-10 11:21:51.000000000 +0000
+@@ -0,0 +1,387 @@
+/***************************************************************************
-+ * Silicon Motion VoyaagerGX framebuffer driver
++ * Silicon Motion VoyagerGX framebuffer driver
+ *
+ * ported to 2.6 by Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
@@ -68994,7 +20016,6 @@
+ * *
+ ***************************************************************************/
+
-+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
@@ -69013,21 +20034,19 @@
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
-+static char *SMIRegs; // point to virtual Memory Map IO starting address
-+static char *SMILFB; // point to virtual video memory starting address
++static char __iomem *SMIRegs; // point to virtual Memory Map IO starting address
++static char __iomem *SMILFB; // point to virtual video memory starting address
+
-+static struct fb_fix_screeninfo smifb_fix __initdata = {
++static struct fb_fix_screeninfo smifb_fix __devinitdata = {
+ .id = "smivgx",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .ywrapstep = 0,
-+ .xpanstep = 1,
-+ .ypanstep = 1,
+ .line_length = 1024 * 2, /* (bbp * xres)/8 */
+ .accel = FB_ACCEL_NONE,
+};
+
-+static struct fb_var_screeninfo smifb_var = {
++static struct fb_var_screeninfo smifb_var __devinitdata = {
+ .xres = 1024,
+ .yres = 768,
+ .xres_virtual = 1024,
@@ -69040,12 +20059,92 @@
+ .height = -1,
+ .width = -1,
+ .vmode = FB_VMODE_NONINTERLACED,
-+};
++};
+
+
+static struct fb_info info;
+
-+#include "smivgxfb.h"
++#define smi_mmiowb(dat,reg) writeb(dat, (SMIRegs + reg))
++#define smi_mmioww(dat,reg) writew(dat, (SMIRegs + reg))
++#define smi_mmiowl(dat,reg) writel(dat, (SMIRegs + reg))
++
++#define smi_mmiorb(reg) readb(SMIRegs + reg)
++#define smi_mmiorw(reg) readw(SMIRegs + reg)
++#define smi_mmiorl(reg) readl(SMIRegs + reg)
++
++/* Address space offsets for various control/status registers.
++*/
++#define MISC_CTRL 0x000004
++#define GPIO_LO_CTRL 0x000008
++#define GPIO_HI_CTRL 0x00000c
++#define DRAM_CTRL 0x000010
++#define CURRENT_POWER_GATE 0x000038
++#define CURRENT_POWER_CLOCK 0x00003C
++#define POWER_MODE1_GATE 0x000048
++#define POWER_MODE1_CLOCK 0x00004C
++#define POWER_MODE_CTRL 0x000054
++
++#define GPIO_DATA_LO 0x010000
++#define GPIO_DATA_HI 0x010004
++#define GPIO_DATA_DIR_LO 0x010008
++#define GPIO_DATA_DIR_HI 0x01000c
++#define I2C_BYTE_COUNT 0x010040
++#define I2C_CONTROL 0x010041
++#define I2C_STATUS_RESET 0x010042
++#define I2C_SLAVE_ADDRESS 0x010043
++#define I2C_DATA 0x010044
++
++#define DE_COLOR_COMPARE 0x100020
++#define DE_COLOR_COMPARE_MASK 0x100024
++#define DE_MASKS 0x100028
++#define DE_WRAP 0x10004C
++
++#define PANEL_DISPLAY_CTRL 0x080000
++#define PANEL_PAN_CTRL 0x080004
++#define PANEL_COLOR_KEY 0x080008
++#define PANEL_FB_ADDRESS 0x08000C
++#define PANEL_FB_WIDTH 0x080010
++#define PANEL_WINDOW_WIDTH 0x080014
++#define PANEL_WINDOW_HEIGHT 0x080018
++#define PANEL_PLANE_TL 0x08001C
++#define PANEL_PLANE_BR 0x080020
++#define PANEL_HORIZONTAL_TOTAL 0x080024
++#define PANEL_HORIZONTAL_SYNC 0x080028
++#define PANEL_VERTICAL_TOTAL 0x08002C
++#define PANEL_VERTICAL_SYNC 0x080030
++#define PANEL_CURRENT_LINE 0x080034
++#define VIDEO_DISPLAY_CTRL 0x080040
++#define VIDEO_DISPLAY_FB0 0x080044
++#define VIDEO_DISPLAY_FBWIDTH 0x080048
++#define VIDEO_DISPLAY_FB0LAST 0x08004C
++#define VIDEO_DISPLAY_TL 0x080050
++#define VIDEO_DISPLAY_BR 0x080054
++#define VIDEO_SCALE 0x080058
++#define VIDEO_INITIAL_SCALE 0x08005C
++#define VIDEO_YUV_CONSTANTS 0x080060
++#define VIDEO_DISPLAY_FB1 0x080064
++#define VIDEO_DISPLAY_FB1LAST 0x080068
++#define VIDEO_ALPHA_CTRL 0x080080
++#define PANEL_HWC_ADDRESS 0x0800F0
++#define CRT_DISPLAY_CTRL 0x080200
++#define CRT_FB_ADDRESS 0x080204
++#define CRT_FB_WIDTH 0x080208
++#define CRT_HORIZONTAL_TOTAL 0x08020c
++#define CRT_HORIZONTAL_SYNC 0x080210
++#define CRT_VERTICAL_TOTAL 0x080214
++#define CRT_VERTICAL_SYNC 0x080218
++#define CRT_HWC_ADDRESS 0x080230
++#define CRT_HWC_LOCATION 0x080234
++
++#define ZV_CAPTURE_CTRL 0x090000
++#define ZV_CAPTURE_CLIP 0x090004
++#define ZV_CAPTURE_SIZE 0x090008
++#define ZV_CAPTURE_BUF0 0x09000c
++#define ZV_CAPTURE_BUF1 0x090010
++#define ZV_CAPTURE_OFFSET 0x090014
++#define ZV_FIFO_CTRL 0x090018
++
++#define waitforvsync() udelay(400)
+
+static int initdone = 0;
+static int crt_out = 1;
@@ -69059,7 +20158,7 @@
+ if (regno > 255)
+ return 1;
+
-+ ((u16 *)(info->pseudo_palette))[regno] =
++ ((u32 *)(info->pseudo_palette))[regno] =
+ ((red & 0xf800) >> 0) |
+ ((green & 0xfc00) >> 5) |
+ ((blue & 0xf800) >> 11);
@@ -69071,8 +20170,7 @@
+ * different output devices (CRT or LCD) and resolutions.
+ * Currently hard-coded for 1024x768 LCD panel.
+ */
-+void
-+smi_setmode(void)
++static void smi_setmode(void)
+{
+ if (initdone)
+ return;
@@ -69128,7 +20226,6 @@
+ smi_mmiowl(0x00010305, CRT_DISPLAY_CTRL);
+ smi_mmiowl(0x00000001, MISC_CTRL);
+ }
-+
+}
+
+/*
@@ -69157,10 +20254,9 @@
+ }
+}
+
-+void
-+vgxfb_setup (char *options)
++static void vgxfb_setup(char *options)
+{
-+
++
+ if (!options || !*options)
+ return;
+
@@ -69179,7 +20275,6 @@
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
-+ .fb_cursor = soft_cursor,
+};
+
+static int __devinit vgx_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
@@ -69207,7 +20302,7 @@
+ smifb_fix.smem_len = 0x00800000;
+ SMILFB = ioremap(smifb_fix.smem_start, smifb_fix.smem_len);
+
-+ memset((void *)SMILFB, 0, smifb_fix.smem_len);
++ memset_io(SMILFB, 0, smifb_fix.smem_len);
+
+ info.screen_base = SMILFB;
+ info.fbops = &smifb_ops;
@@ -69219,7 +20314,7 @@
+ if (!info.pseudo_palette) {
+ return -ENOMEM;
+ }
-+ memset((void *)info.pseudo_palette, 0, sizeof(u32) *16);
++ memset(info.pseudo_palette, 0, sizeof(u32) *16);
+
+ fb_alloc_cmap(&info.cmap,256,0);
+
@@ -69246,13 +20341,12 @@
+ smi_unmap_mmio();
+}
+
-+/*
-+ * Rev. AA is 0x501, Rev. B is 0x510.
-+ */
+static struct pci_device_id vgx_devices[] = {
-+ {0x126f, 0x510, PCI_ANY_ID, PCI_ANY_ID,0,0,0},
-+ {0x126f, 0x501, PCI_ANY_ID, PCI_ANY_ID,0,0,0},
-+ {0,}
++ {PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA,
++ PCI_ANY_ID, PCI_ANY_ID},
++ {PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B,
++ PCI_ANY_ID, PCI_ANY_ID},
++ {0}
+};
+
+MODULE_DEVICE_TABLE(pci, vgx_devices);
@@ -69264,7 +20358,7 @@
+ .remove = __devexit_p(vgx_pci_remove),
+};
+
-+int __init vgxfb_init(void)
++static int __init vgxfb_init(void)
+{
+ char *option = NULL;
+
@@ -69276,7 +20370,7 @@
+ return pci_module_init(&vgxfb_pci_driver);
+}
+
-+void __exit vgxfb_exit(void)
++static void __exit vgxfb_exit(void)
+{
+ pci_unregister_driver(&vgxfb_pci_driver);
+}
@@ -69287,272 +20381,701 @@
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("Framebuffer driver for SMI Voyager");
+MODULE_LICENSE("GPL");
-+
-diff -urpNX dontdiff linux-2.6.12/drivers/video/smivgxfb.h linux_HEAD/drivers/video/smivgxfb.h
---- linux-2.6.12/drivers/video/smivgxfb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/drivers/video/smivgxfb.h 2005-04-21 07:02:30.000000000 +0200
-@@ -0,0 +1,128 @@
-+/***************************************************************************
-+ * Silicon Motion VoyagerGX framebuffer driver
-+ *
-+ * port to 2.6 by Embedded Alley Solutions, Inc
-+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
-+ *
-+ * based on:
-+ copyright : (C) 2001 by Szu-Tao Huang
-+ email : johuang at siliconmotion.com
-+
-+ Updated to SM501 by Eric.Devolder at amd.com and dan at embeddededge.com
-+ for the AMD Mirage Portable Tablet. 20 Oct 2003
-+ ***************************************************************************/
-+
-+/***************************************************************************
-+ * *
-+ * This program is free software; you can redistribute it and/or modify *
-+ * it under the terms of the GNU General Public License as published by *
-+ * the Free Software Foundation; either version 2 of the License, or *
-+ * (at your option) any later version. *
-+ * *
-+ ***************************************************************************/
-+#include <linux/config.h>
-+
-+#define smi_mmiowb(dat,reg) writeb(dat, (SMIRegs + reg))
-+#define smi_mmioww(dat,reg) writew(dat, (SMIRegs + reg))
-+#define smi_mmiowl(dat,reg) writel(dat, (SMIRegs + reg))
-+
-+#define smi_mmiorb(reg) readb(SMIRegs + reg)
-+#define smi_mmiorw(reg) readw(SMIRegs + reg)
-+#define smi_mmiorl(reg) readl(SMIRegs + reg)
-+
-+#define NR_PALETTE 256
-+
-+/* Address space offsets for various control/status registers.
-+*/
-+#define MISC_CTRL 0x000004
-+#define GPIO_LO_CTRL 0x000008
-+#define GPIO_HI_CTRL 0x00000c
-+#define DRAM_CTRL 0x000010
-+#define CURRENT_POWER_GATE 0x000038
-+#define CURRENT_POWER_CLOCK 0x00003C
-+#define POWER_MODE1_GATE 0x000048
-+#define POWER_MODE1_CLOCK 0x00004C
-+#define POWER_MODE_CTRL 0x000054
-+
-+#define GPIO_DATA_LO 0x010000
-+#define GPIO_DATA_HI 0x010004
-+#define GPIO_DATA_DIR_LO 0x010008
-+#define GPIO_DATA_DIR_HI 0x01000c
-+#define I2C_BYTE_COUNT 0x010040
-+#define I2C_CONTROL 0x010041
-+#define I2C_STATUS_RESET 0x010042
-+#define I2C_SLAVE_ADDRESS 0x010043
-+#define I2C_DATA 0x010044
-+
-+#define DE_COLOR_COMPARE 0x100020
-+#define DE_COLOR_COMPARE_MASK 0x100024
-+#define DE_MASKS 0x100028
-+#define DE_WRAP 0x10004C
-+
-+#define PANEL_DISPLAY_CTRL 0x080000
-+#define PANEL_PAN_CTRL 0x080004
-+#define PANEL_COLOR_KEY 0x080008
-+#define PANEL_FB_ADDRESS 0x08000C
-+#define PANEL_FB_WIDTH 0x080010
-+#define PANEL_WINDOW_WIDTH 0x080014
-+#define PANEL_WINDOW_HEIGHT 0x080018
-+#define PANEL_PLANE_TL 0x08001C
-+#define PANEL_PLANE_BR 0x080020
-+#define PANEL_HORIZONTAL_TOTAL 0x080024
-+#define PANEL_HORIZONTAL_SYNC 0x080028
-+#define PANEL_VERTICAL_TOTAL 0x08002C
-+#define PANEL_VERTICAL_SYNC 0x080030
-+#define PANEL_CURRENT_LINE 0x080034
-+#define VIDEO_DISPLAY_CTRL 0x080040
-+#define VIDEO_DISPLAY_FB0 0x080044
-+#define VIDEO_DISPLAY_FBWIDTH 0x080048
-+#define VIDEO_DISPLAY_FB0LAST 0x08004C
-+#define VIDEO_DISPLAY_TL 0x080050
-+#define VIDEO_DISPLAY_BR 0x080054
-+#define VIDEO_SCALE 0x080058
-+#define VIDEO_INITIAL_SCALE 0x08005C
-+#define VIDEO_YUV_CONSTANTS 0x080060
-+#define VIDEO_DISPLAY_FB1 0x080064
-+#define VIDEO_DISPLAY_FB1LAST 0x080068
-+#define VIDEO_ALPHA_CTRL 0x080080
-+#define PANEL_HWC_ADDRESS 0x0800F0
-+#define CRT_DISPLAY_CTRL 0x080200
-+#define CRT_FB_ADDRESS 0x080204
-+#define CRT_FB_WIDTH 0x080208
-+#define CRT_HORIZONTAL_TOTAL 0x08020c
-+#define CRT_HORIZONTAL_SYNC 0x080210
-+#define CRT_VERTICAL_TOTAL 0x080214
-+#define CRT_VERTICAL_SYNC 0x080218
-+#define CRT_HWC_ADDRESS 0x080230
-+#define CRT_HWC_LOCATION 0x080234
-+
-+#define ZV_CAPTURE_CTRL 0x090000
-+#define ZV_CAPTURE_CLIP 0x090004
-+#define ZV_CAPTURE_SIZE 0x090008
-+#define ZV_CAPTURE_BUF0 0x09000c
-+#define ZV_CAPTURE_BUF1 0x090010
-+#define ZV_CAPTURE_OFFSET 0x090014
-+#define ZV_FIFO_CTRL 0x090018
-+
-+#define waitforvsync() udelay(100); udelay(100); udelay(100); udelay(100);
+diff -urN --ignore-space-change kernel.org/include/asm-mips/atomic.h linux-mips/include/asm-mips/atomic.h
+--- kernel.org/include/asm-mips/atomic.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/atomic.h 2006-01-10 11:21:59.000000000 +0000
+@@ -24,10 +24,9 @@
+ #define _ASM_ATOMIC_H
+
+ #include <asm/cpu-features.h>
++#include <asm/interrupt.h>
+ #include <asm/war.h>
+
+-extern spinlock_t atomic_lock;
+-
+ typedef struct { volatile int counter; } atomic_t;
+
+ #define ATOMIC_INIT(i) { (i) }
+@@ -85,9 +84,9 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ v->counter += i;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+ }
+
+@@ -127,9 +126,9 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ v->counter -= i;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+ }
+
+@@ -173,11 +172,11 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result += i;
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+@@ -220,11 +219,11 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result -= i;
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+@@ -277,12 +276,12 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result -= i;
+ if (result >= 0)
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+@@ -432,9 +431,9 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ v->counter += i;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+ }
+
+@@ -474,9 +473,9 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ v->counter -= i;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+ }
+
+@@ -520,11 +519,11 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result += i;
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+@@ -567,11 +566,11 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result -= i;
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+@@ -624,12 +623,12 @@
+ } else {
+ unsigned long flags;
+
+- spin_lock_irqsave(&atomic_lock, flags);
++ local_irq_save(flags);
+ result = v->counter;
+ result -= i;
+ if (result >= 0)
+ v->counter = result;
+- spin_unlock_irqrestore(&atomic_lock, flags);
++ local_irq_restore(flags);
+ }
+
+ return result;
+diff -urN --ignore-space-change kernel.org/include/asm-mips/cpu-features.h linux-mips/include/asm-mips/cpu-features.h
+--- kernel.org/include/asm-mips/cpu-features.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/cpu-features.h 2006-01-10 11:21:59.000000000 +0000
+@@ -116,6 +116,27 @@
+ #endif
+ #endif
+
++# ifndef cpu_has_mips32r1
++# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
++# endif
++# ifndef cpu_has_mips32r2
++# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
++# endif
++# ifndef cpu_has_mips64r1
++# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
++# endif
++# ifndef cpu_has_mips64r2
++# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
++# endif
+
+/*
-+ * Minimum X and Y resolutions
++ * Shortcuts ...
++ */
++#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
++#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
++#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
++#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
++
+ #ifndef cpu_has_dsp
+ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
+ #endif
+diff -urN --ignore-space-change kernel.org/include/asm-mips/cpu.h linux-mips/include/asm-mips/cpu.h
+--- kernel.org/include/asm-mips/cpu.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/cpu.h 2006-01-10 11:21:59.000000000 +0000
+@@ -204,16 +204,18 @@
+ */
+ #define MIPS_CPU_ISA_I 0x00000001
+ #define MIPS_CPU_ISA_II 0x00000002
+-#define MIPS_CPU_ISA_III 0x00008003
+-#define MIPS_CPU_ISA_IV 0x00008004
+-#define MIPS_CPU_ISA_V 0x00008005
+-#define MIPS_CPU_ISA_M32 0x00000020
+-#define MIPS_CPU_ISA_M64 0x00008040
++#define MIPS_CPU_ISA_III 0x00000003
++#define MIPS_CPU_ISA_IV 0x00000004
++#define MIPS_CPU_ISA_V 0x00000005
++#define MIPS_CPU_ISA_M32R1 0x00000020
++#define MIPS_CPU_ISA_M32R2 0x00000040
++#define MIPS_CPU_ISA_M64R1 0x00000080
++#define MIPS_CPU_ISA_M64R2 0x00000100
+
+-/*
+- * Bit 15 encodes if an ISA level supports 64-bit operations.
+- */
+-#define MIPS_CPU_ISA_64BIT 0x00008000
++#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
++ MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
++#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
++ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
+
+ /*
+ * CPU Option encodings
+diff -urN --ignore-space-change kernel.org/include/asm-mips/delay.h linux-mips/include/asm-mips/delay.h
+--- kernel.org/include/asm-mips/delay.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/delay.h 2006-01-10 11:21:59.000000000 +0000
+@@ -52,13 +52,11 @@
+ unsigned long lo;
+
+ /*
+- * The common rates of 1000 and 128 are rounded wrongly by the
+- * catchall case for 64-bit. Excessive precission? Probably ...
++ * The rates of 128 is rounded wrongly by the catchall case
++ * for 64-bit. Excessive precission? Probably ...
+ */
+ #if defined(CONFIG_64BIT) && (HZ == 128)
+ usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
+-#elif defined(CONFIG_64BIT) && (HZ == 1000)
+- usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */
+ #elif defined(CONFIG_64BIT)
+ usecs *= (0x8000000000000000UL / (500000 / HZ));
+ #else /* 32-bit junk follows here */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/dsp.h linux-mips/include/asm-mips/dsp.h
+--- kernel.org/include/asm-mips/dsp.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/dsp.h 2006-01-10 11:21:59.000000000 +0000
+@@ -16,7 +16,7 @@
+ #include <asm/mipsregs.h>
+
+ #define DSP_DEFAULT 0x00000000
+-#define DSP_MASK 0x1f
++#define DSP_MASK 0x3ff
+
+ #define __enable_dsp_hazard() \
+ do { \
+@@ -48,6 +48,7 @@
+ tsk->thread.dsp.dspr[3] = mflo2(); \
+ tsk->thread.dsp.dspr[4] = mfhi3(); \
+ tsk->thread.dsp.dspr[5] = mflo3(); \
++ tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
+ } while (0)
+
+ #define save_dsp(tsk) \
+@@ -64,6 +65,7 @@
+ mtlo2(tsk->thread.dsp.dspr[3]); \
+ mthi3(tsk->thread.dsp.dspr[4]); \
+ mtlo3(tsk->thread.dsp.dspr[5]); \
++ wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
+ } while (0)
+
+ #define restore_dsp(tsk) \
+diff -urN --ignore-space-change kernel.org/include/asm-mips/elf.h linux-mips/include/asm-mips/elf.h
+--- kernel.org/include/asm-mips/elf.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/elf.h 2006-01-10 11:21:59.000000000 +0000
+@@ -277,12 +277,12 @@
+
+ struct task_struct;
+
+-extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
++extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
+ extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
+ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
+
+ #define ELF_CORE_COPY_REGS(elf_regs, regs) \
+- dump_regs((elf_greg_t *)&(elf_regs), regs);
++ elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
+ #define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
+ #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
+ dump_task_fpu(tsk, elf_fpregs)
+diff -urN --ignore-space-change kernel.org/include/asm-mips/hazards.h linux-mips/include/asm-mips/hazards.h
+--- kernel.org/include/asm-mips/hazards.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/hazards.h 2006-01-10 11:21:59.000000000 +0000
+@@ -233,15 +233,25 @@
+ #endif
+
+ #ifdef CONFIG_CPU_MIPSR2
++/*
++ * gcc has a tradition of misscompiling the previous construct using the
++ * address of a label as argument to inline assembler. Gas otoh has the
++ * annoying difference between la and dla which are only usable for 32-bit
++ * rsp. 64-bit code, so can't be used without conditional compilation.
++ * The alterantive is switching the assembler to 64-bit code which happens
++ * to work right even for 32-bit code ...
+ */
-+#define MIN_XRES 640
-+#define MIN_YRES 480
+ #define instruction_hazard() \
+ do { \
+-__label__ __next; \
++ unsigned long tmp; \
++ \
+ __asm__ __volatile__( \
++ " .set mips64r2 \n" \
++ " dla %0, 1f \n" \
+ " jr.hb %0 \n" \
+- : \
+- : "r" (&&__next)); \
+-__next: \
+- ; \
++ " .set mips0 \n" \
++ "1: \n" \
++ : "=r" (tmp)); \
+ } while (0)
+
+ #else
+diff -urN --ignore-space-change kernel.org/include/asm-mips/interrupt.h linux-mips/include/asm-mips/interrupt.h
+--- kernel.org/include/asm-mips/interrupt.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/interrupt.h 2006-01-10 11:21:59.000000000 +0000
+@@ -93,6 +93,7 @@
+ " .set noat \n"
+ #ifdef CONFIG_CPU_MIPSR2
+ " di \\result \n"
++ " andi \\result, 1 \n"
+ #else
+ " mfc0 \\result, $12 \n"
+ " ori $1, \\result, 1 \n"
+diff -urN --ignore-space-change kernel.org/include/asm-mips/io.h linux-mips/include/asm-mips/io.h
+--- kernel.org/include/asm-mips/io.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/io.h 2006-01-10 11:21:59.000000000 +0000
+@@ -535,34 +535,6 @@
+ }
+
+ /*
+- * Memory Mapped I/O
+- */
+-#define ioread8(addr) readb(addr)
+-#define ioread16(addr) readw(addr)
+-#define ioread32(addr) readl(addr)
+-
+-#define iowrite8(b,addr) writeb(b,addr)
+-#define iowrite16(w,addr) writew(w,addr)
+-#define iowrite32(l,addr) writel(l,addr)
+-
+-#define ioread8_rep(a,b,c) readsb(a,b,c)
+-#define ioread16_rep(a,b,c) readsw(a,b,c)
+-#define ioread32_rep(a,b,c) readsl(a,b,c)
+-
+-#define iowrite8_rep(a,b,c) writesb(a,b,c)
+-#define iowrite16_rep(a,b,c) writesw(a,b,c)
+-#define iowrite32_rep(a,b,c) writesl(a,b,c)
+-
+-/* Create a virtual mapping cookie for an IO port range */
+-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+-extern void ioport_unmap(void __iomem *);
+-
+-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+-struct pci_dev;
+-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+-
+-/*
+ * ISA space is 'always mapped' on currently supported MIPS systems, no need
+ * to explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-au1x00/au1000.h linux-mips/include/asm-mips/mach-au1x00/au1000.h
+--- kernel.org/include/asm-mips/mach-au1x00/au1000.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-au1x00/au1000.h 2006-01-10 11:21:59.000000000 +0000
+@@ -838,6 +838,7 @@
+ #define UART3_ADDR 0xB1400000
+
+ #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
++#define USB_OHCI_LEN 0x00060000
+ #define USB_HOST_CONFIG 0xB4027ffc
+
+ #define AU1550_ETH0_BASE 0xB0500000
+@@ -1017,10 +1018,12 @@
+ #define I2S_CONTROL_D (1<<1)
+ #define I2S_CONTROL_CE (1<<0)
+
+-#ifndef CONFIG_SOC_AU1200
+-
+ /* USB Host Controller */
++#ifndef USB_OHCI_LEN
+ #define USB_OHCI_LEN 0x00100000
++#endif
+
-+/*
-+* Private structure
-+*/
-+struct smifb_par
-+{
-+ /*
-+ * Hardware
-+ */
-+ u16 chipID;
++#ifndef CONFIG_SOC_AU1200
+
+ /* USB Device Controller */
+ #define USBD_EP0RD 0xB0200000
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-mips/include/asm-mips/mach-au1x00/au1xxx_ide.h
+--- kernel.org/include/asm-mips/mach-au1x00/au1xxx_ide.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-au1x00/au1xxx_ide.h 2006-01-10 11:21:59.000000000 +0000
+@@ -84,6 +84,11 @@
+ } _auide_hwif;
+
+ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
++struct drive_list_entry {
++ const char *id_model;
++ const char *id_firmware;
++};
++
+ /* HD white list */
+ static const struct drive_list_entry dma_white_list [] = {
+ /*
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-generic/timex.h linux-mips/include/asm-mips/mach-generic/timex.h
+--- kernel.org/include/asm-mips/mach-generic/timex.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-generic/timex.h 2006-01-10 11:21:59.000000000 +0000
+@@ -3,20 +3,11 @@
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+- * Copyright (C) 2003 by Ralf Baechle
++ * Copyright (C) 2003, 2005 by Ralf Baechle
+ */
+ #ifndef __ASM_MACH_GENERIC_TIMEX_H
+ #define __ASM_MACH_GENERIC_TIMEX_H
+
+-#include <linux/config.h>
+-
+-/*
+- * Last remaining user of the i8254 PIC, will be converted, too ...
+- */
+-#ifdef CONFIG_SNI_RM200_PCI
+-#define CLOCK_TICK_RATE 1193182
+-#else
+ #define CLOCK_TICK_RATE 500000
+-#endif
+
+ #endif /* __ASM_MACH_GENERIC_TIMEX_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-ip22/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-ip22/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-ip22/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -34,4 +34,9 @@
+ #define cpu_has_nofpuex 0
+ #define cpu_has_64bits 1
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
+ #endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-ip27/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -37,4 +37,9 @@
+ #define cpu_icache_line_size() 64
+ #define cpu_scache_line_size() 128
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
+ #endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-ip32/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-ip32/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-ip32/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -39,4 +39,9 @@
+ #define cpu_has_ic_fills_f_dc 0
+ #define cpu_has_dsp 0
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
+
-+ u_int width;
-+ u_int height;
-+ u_int hz;
-+};
-diff -urpNX dontdiff linux-2.6.12/include/linux/ds17287rtc.h linux_HEAD/include/linux/ds17287rtc.h
---- linux-2.6.12/include/linux/ds17287rtc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/linux/ds17287rtc.h 2003-04-07 04:28:45.000000000 +0200
-@@ -0,0 +1,68 @@
-+/*
-+ * ds17287rtc.h - register definitions for the ds1728[57] RTC / CMOS RAM
-+ *
+ #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-ja/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-ja/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-ja/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-ja/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -37,4 +37,9 @@
+ #define cpu_icache_line_size() 32
+ #define cpu_scache_line_size() 32
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
+ #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -40,4 +40,9 @@
+ #define cpu_icache_line_size() 32
+ #define cpu_scache_line_size() 32
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
+ #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-rm200/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-rm200/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-rm200/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -40,4 +40,9 @@
+ #define cpu_icache_line_size() 32
+ #define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
+ #endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-rm200/timex.h linux-mips/include/asm-mips/mach-rm200/timex.h
+--- kernel.org/include/asm-mips/mach-rm200/timex.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/include/asm-mips/mach-rm200/timex.h 2006-01-10 11:21:59.000000000 +0000
+@@ -0,0 +1,13 @@
++/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
-+ *
-+ * (C) 2003 Guido Guenther <agx at sigxcpu.org>
+ *
++ * Copyright (C) 2003, 2005 by Ralf Baechle
+ */
++#ifndef __ASM_MACH_RM200_TIMEX_H
++#define __ASM_MACH_RM200_TIMEX_H
+
-+#ifndef _DS17287RTC_H
-+#define _DS17287RTC_H
++#define CLOCK_TICK_RATE 1193182
+
-+#include <asm/io.h>
-+#include <linux/rtc.h> /* get the user-level API */
-+#include <linux/spinlock.h> /* spinlock_t */
-+#include <linux/mc146818rtc.h>
-+
-+/* Register A */
-+#define DS_REGA_DV2 0x40 /* countdown chain */
-+#define DS_REGA_DV1 0x20 /* oscillator enable */
-+#define DS_REGA_DV0 0x10 /* bank select */
-+
-+/* bank 1 registers */
-+#define DS_B1_MODEL 0x40 /* model number byte */
-+#define DS_B1_SN1 0x41 /* serial number byte 1 */
-+#define DS_B1_SN2 0x42 /* serial number byte 2 */
-+#define DS_B1_SN3 0x43 /* serial number byte 3 */
-+#define DS_B1_SN4 0x44 /* serial number byte 4 */
-+#define DS_B1_SN5 0x45 /* serial number byte 5 */
-+#define DS_B1_SN6 0x46 /* serial number byte 6 */
-+#define DS_B1_CRC 0x47 /* CRC byte */
-+#define DS_B1_CENTURY 0x48 /* Century byte */
-+#define DS_B1_DALARM 0x49 /* date alarm */
-+#define DS_B1_XCTRL4A 0x4a /* extendec control register 4a */
-+#define DS_B1_XCTRL4B 0x4b /* extendec control register 4b */
-+#define DS_B1_RTCADDR2 0x4e /* rtc address 2 */
-+#define DS_B1_RTCADDR3 0x4f /* rtc address 3 */
-+#define DS_B1_RAMLSB 0x50 /* extended ram LSB */
-+#define DS_B1_RAMMSB 0x51 /* extended ram MSB */
-+#define DS_B1_RAMDPORT 0x53 /* extended ram data port */
-+
-+/* register details */
-+/* extended control register 4a */
-+#define DS_XCTRL4A_VRT2 0x80 /* valid ram and time */
-+#define DS_XCTRL4A_INCR 0x40 /* increment progress status */
-+#define DS_XCTRL4A_BME 0x20 /* burst mode enable */
-+#define DS_XCTRL4A_PAB 0x08 /* power active bar ctrl */
-+#define DS_XCTRL4A_RF 0x04 /* ram clear flag */
-+#define DS_XCTRL4A_WF 0x02 /* wake up alarm flag */
-+#define DS_XCTRL4A_KF 0x01 /* kickstart flag */
-+/* interrupt causes */
-+#define DS_XCTRL4A_IFS (DS_XCTRL4A_RF|DS_XCTRL4A_WF|DS_XCTRL4A_KF)
-+
-+/* extended control register 4b */
-+#define DS_XCTRL4B_ABE 0x80 /* auxiliary battery enable */
-+#define DS_XCTRL4B_E32K 0x40 /* enable 32.768 kHz Output */
-+#define DS_XCTRL4B_CS 0x20 /* crystal select */
-+#define DS_XCTRL4B_RCE 0x10 /* ram clear enable */
-+#define DS_XCTRL4B_PRS 0x08 /* PAB resec select */
-+#define DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */
-+#define DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */
-+#define DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */
-+/* interrupt enable bits */
-+#define DS_XCTRL4B_IFES (DS_XCTRL4B_RIE|DS_XCTRL4B_WFE|DS_XCTRL4B_KFE)
-+
-+#endif /* _DS17287RTC_H */
-diff -urpNX dontdiff linux-2.6.12/include/linux/ds1742rtc.h linux_HEAD/include/linux/ds1742rtc.h
---- linux-2.6.12/include/linux/ds1742rtc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/include/linux/ds1742rtc.h 2003-11-18 06:15:20.000000000 +0100
-@@ -0,0 +1,53 @@
++#endif /* __ASM_MACH_RM200_TIMEX_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-vr41xx/timex.h linux-mips/include/asm-mips/mach-vr41xx/timex.h
+--- kernel.org/include/asm-mips/mach-vr41xx/timex.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/include/asm-mips/mach-vr41xx/timex.h 2006-01-10 11:21:59.000000000 +0000
+@@ -0,0 +1,18 @@
+/*
-+ * ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
-+ *
-+ * Copyright (C) 1999-2001 Toshiba Corporation
-+ * Copyright (C) 2003 Ralf Baechle (ralf at linux-mips.org)
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
+ *
-+ * Permission is hereby granted to copy, modify and redistribute this code
-+ * in terms of the GNU Library General Public License, Version 2 or later,
-+ * at your option.
-+ */
-+#ifndef __LINUX_DS1742RTC_H
-+#define __LINUX_DS1742RTC_H
-+
-+#include <asm/ds1742.h>
-+
-+#define RTC_BRAM_SIZE 0x800
-+#define RTC_OFFSET 0x7f8
-+
-+/*
-+ * Register summary
++ * Copyright (C) 2003 by Ralf Baechle
+ */
-+#define RTC_CONTROL (RTC_OFFSET + 0)
-+#define RTC_CENTURY (RTC_OFFSET + 0)
-+#define RTC_SECONDS (RTC_OFFSET + 1)
-+#define RTC_MINUTES (RTC_OFFSET + 2)
-+#define RTC_HOURS (RTC_OFFSET + 3)
-+#define RTC_DAY (RTC_OFFSET + 4)
-+#define RTC_DATE (RTC_OFFSET + 5)
-+#define RTC_MONTH (RTC_OFFSET + 6)
-+#define RTC_YEAR (RTC_OFFSET + 7)
-+
-+#define RTC_CENTURY_MASK 0x3f
-+#define RTC_SECONDS_MASK 0x7f
-+#define RTC_DAY_MASK 0x07
-+
+/*
-+ * Bits in the Control/Century register
++ * Changes:
++ * Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
++ * - CLOCK_TICK_RATE is changed into 32768 from 6144000.
+ */
-+#define RTC_WRITE 0x80
-+#define RTC_READ 0x40
++#ifndef __ASM_MACH_VR41XX_TIMEX_H
++#define __ASM_MACH_VR41XX_TIMEX_H
+
-+/*
-+ * Bits in the Seconds register
-+ */
-+#define RTC_STOP 0x80
++#define CLOCK_TICK_RATE 32768
+
-+/*
-+ * Bits in the Day register
-+ */
-+#define RTC_BATT_FLAG 0x80
-+#define RTC_FREQ_TEST 0x40
++#endif /* __ASM_MACH_VR41XX_TIMEX_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mach-yosemite/cpu-feature-overrides.h linux-mips/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+--- kernel.org/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2006-01-10 11:21:59.000000000 +0000
+@@ -37,4 +37,9 @@
+ #define cpu_icache_line_size() 32
+ #define cpu_scache_line_size() 32
+
++#define cpu_has_mips32r1 0
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
+
-+#endif /* __LINUX_DS1742RTC_H */
-diff -urpNX dontdiff linux-2.6.12/include/linux/elf.h linux_HEAD/include/linux/elf.h
---- linux-2.6.12/include/linux/elf.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/elf.h 2005-02-17 21:50:55.000000000 +0100
-@@ -66,7 +66,7 @@ typedef __s64 Elf64_Sxword;
+ #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/mipsregs.h linux-mips/include/asm-mips/mipsregs.h
+--- kernel.org/include/asm-mips/mipsregs.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/mipsregs.h 2006-01-10 11:21:59.000000000 +0000
+@@ -1059,7 +1059,7 @@
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # wrdsp $1, %x1 \n" \
+- " .word 0x7c2004f8 | (%x1 << 15) \n" \
++ " .word 0x7c2004f8 | (%x1 << 11) \n" \
+ " .set pop \n" \
+ : \
+ : "r" (val), "i" (mask)); \
+diff -urN --ignore-space-change kernel.org/include/asm-mips/processor.h linux-mips/include/asm-mips/processor.h
+--- kernel.org/include/asm-mips/processor.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/processor.h 2006-01-10 11:30:59.000000000 +0000
+@@ -103,7 +103,6 @@
+ struct mips_dsp_state {
+ dspreg_t dspr[NUM_DSP_REGS];
+ unsigned int dspcontrol;
+- unsigned short used_dsp;
+ };
+
+ #define INIT_DSP {{0,},}
+diff -urN --ignore-space-change kernel.org/include/asm-mips/vr41xx/siu.h linux-mips/include/asm-mips/vr41xx/siu.h
+--- kernel.org/include/asm-mips/vr41xx/siu.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/vr41xx/siu.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,50 +0,0 @@
+-/*
+- * Include file for NEC VR4100 series Serial Interface Unit.
+- *
+- * Copyright (C) 2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+- */
+-#ifndef __NEC_VR41XX_SIU_H
+-#define __NEC_VR41XX_SIU_H
+-
+-typedef enum {
+- SIU_INTERFACE_RS232C,
+- SIU_INTERFACE_IRDA,
+-} siu_interface_t;
+-
+-extern void vr41xx_select_siu_interface(siu_interface_t interface);
+-
+-typedef enum {
+- SIU_USE_IRDA,
+- FIR_USE_IRDA,
+-} irda_use_t;
+-
+-extern void vr41xx_use_irda(irda_use_t use);
+-
+-typedef enum {
+- SHARP_IRDA,
+- TEMIC_IRDA,
+- HP_IRDA,
+-} irda_module_t;
+-
+-typedef enum {
+- IRDA_TX_1_5MBPS,
+- IRDA_TX_4MBPS,
+-} irda_speed_t;
+-
+-extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
+-
+-#endif /* __NEC_VR41XX_SIU_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/vr41xx/tb0287.h linux-mips/include/asm-mips/vr41xx/tb0287.h
+--- kernel.org/include/asm-mips/vr41xx/tb0287.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/vr41xx/tb0287.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,43 +0,0 @@
+-/*
+- * tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
+- *
+- * Copyright (C) 2005 Media Lab Inc. <ito at mlb.co.jp>
+- *
+- * This code is largely based on tb0219.h.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+- */
+-#ifndef __TANBAC_TB0287_H
+-#define __TANBAC_TB0287_H
+-
+-#include <asm/vr41xx/vr41xx.h>
+-
+-/*
+- * General-Purpose I/O Pin Number
+- */
+-#define TB0287_PCI_SLOT_PIN 2
+-#define TB0287_SM501_PIN 3
+-#define TB0287_SIL680A_PIN 8
+-#define TB0287_RTL8110_PIN 13
+-
+-/*
+- * Interrupt Number
+- */
+-#define TB0287_PCI_SLOT_IRQ GIU_IRQ(TB0287_PCI_SLOT_PIN)
+-#define TB0287_SM501_IRQ GIU_IRQ(TB0287_SM501_PIN)
+-#define TB0287_SIL680A_IRQ GIU_IRQ(TB0287_SIL680A_PIN)
+-#define TB0287_RTL8110_IRQ GIU_IRQ(TB0287_RTL8110_PIN)
+-
+-#endif /* __TANBAC_TB0287_H */
+diff -urN --ignore-space-change kernel.org/include/asm-mips/vr41xx/vr41xx.h linux-mips/include/asm-mips/vr41xx/vr41xx.h
+--- kernel.org/include/asm-mips/vr41xx/vr41xx.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/asm-mips/vr41xx/vr41xx.h 2006-01-10 11:21:59.000000000 +0000
+@@ -7,7 +7,7 @@
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+- * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
++ * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa at hh.iij4u.or.jp>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+diff -urN --ignore-space-change kernel.org/include/linux/elf.h linux-mips/include/linux/elf.h
+--- kernel.org/include/linux/elf.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/linux/elf.h 2006-01-10 11:30:59.000000000 +0000
+@@ -67,7 +67,7 @@
#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
@@ -69561,10 +21084,10 @@
#define EM_PARISC 15 /* HPPA */
-diff -urpNX dontdiff linux-2.6.12/include/linux/mc146818rtc.h linux_HEAD/include/linux/mc146818rtc.h
---- linux-2.6.12/include/linux/mc146818rtc.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/mc146818rtc.h 2004-12-04 20:57:43.000000000 +0100
-@@ -89,4 +89,12 @@ extern spinlock_t rtc_lock; /* serializ
+diff -urN --ignore-space-change kernel.org/include/linux/mc146818rtc.h linux-mips/include/linux/mc146818rtc.h
+--- kernel.org/include/linux/mc146818rtc.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/linux/mc146818rtc.h 2006-01-10 11:22:03.000000000 +0000
+@@ -89,4 +89,12 @@
# define RTC_VRT 0x80 /* valid RAM and time */
/**********************************************************************/
@@ -69577,35 +21100,23 @@
+#endif
+
#endif /* _MC146818RTC_H */
-diff -urpNX dontdiff linux-2.6.12/include/linux/pci.h linux_HEAD/include/linux/pci.h
---- linux-2.6.12/include/linux/pci.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/pci.h 2005-07-01 12:10:41.000000000 +0200
-@@ -1037,7 +1037,7 @@ enum pci_fixup_pass {
-
- /* Anonymous variables would be nice... */
- #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
-- static struct pci_fixup __pci_fixup_##name __attribute_used__ \
-+ static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
- __attribute__((__section__(#section))) = { vendor, device, hook };
- #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
- DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
-diff -urpNX dontdiff linux-2.6.12/include/linux/pci_ids.h linux_HEAD/include/linux/pci_ids.h
---- linux-2.6.12/include/linux/pci_ids.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/pci_ids.h 2005-07-10 12:16:34.000000000 +0200
-@@ -2120,6 +2120,9 @@
- #define PCI_DEVICE_ID_ENE_1410 0x1410
- #define PCI_DEVICE_ID_ENE_1420 0x1420
-
-+#define PCI_VENDOR_ID_MIPS 0x153f
-+#define PCI_DEVICE_ID_SOC_IT 0x0001
-+
- #define PCI_VENDOR_ID_SYBA 0x1592
- #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782
- #define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783
-diff -urpNX dontdiff linux-2.6.12/include/linux/serial.h linux_HEAD/include/linux/serial.h
---- linux-2.6.12/include/linux/serial.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/serial.h 2005-07-10 12:16:38.000000000 +0200
-@@ -75,7 +75,8 @@ struct serial_struct {
+diff -urN --ignore-space-change kernel.org/include/linux/pci_ids.h linux-mips/include/linux/pci_ids.h
+--- kernel.org/include/linux/pci_ids.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/linux/pci_ids.h 2006-01-10 11:22:04.000000000 +0000
+@@ -1530,6 +1530,9 @@
+ #define PCI_VENDOR_ID_SATSAGEM 0x1267
+ #define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016
+
++#define PCI_VENDOR_ID_SILICON_MOTION 0x126f
++#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA 0x0501
++#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B 0x0510
+
+ #define PCI_VENDOR_ID_ENSONIQ 0x1274
+ #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
+diff -urN --ignore-space-change kernel.org/include/linux/serial.h linux-mips/include/linux/serial.h
+--- kernel.org/include/linux/serial.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/linux/serial.h 2006-01-10 11:30:59.000000000 +0000
+@@ -76,7 +76,8 @@
#define PORT_16654 11
#define PORT_16850 12
#define PORT_RSA 13 /* RSA-DV II/S card */
@@ -69615,90 +21126,55 @@
#define SERIAL_IO_PORT 0
#define SERIAL_IO_HUB6 1
-diff -urpNX dontdiff linux-2.6.12/include/linux/serial_core.h linux_HEAD/include/linux/serial_core.h
---- linux-2.6.12/include/linux/serial_core.h 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/include/linux/serial_core.h 2005-07-10 12:16:38.000000000 +0200
-@@ -104,7 +104,7 @@
- #define PORT_MPSC 63
-
- /* TXX9 type number */
--#define PORT_TXX9 64
-+#define PORT_TXX9 64
-
- /* NEC VR4100 series SIU/DSIU */
- #define PORT_VR41XX_SIU 65
-diff -urpNX dontdiff linux-2.6.12/scripts/genksyms/Makefile linux_HEAD/scripts/genksyms/Makefile
---- linux-2.6.12/scripts/genksyms/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/scripts/genksyms/Makefile 2004-09-21 13:12:23.000000000 +0200
-@@ -47,3 +47,5 @@ clean-files += parse.output
- endif
-
- targets += keywords.c lex.c parse.c parse.h
-+
-+clean-files := keywords.c lex.c parse.c parse.h
-diff -urpNX dontdiff linux-2.6.12/scripts/kallsyms.c linux_HEAD/scripts/kallsyms.c
---- linux-2.6.12/scripts/kallsyms.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/scripts/kallsyms.c 2005-07-01 12:10:54.000000000 +0200
-@@ -156,6 +156,9 @@ read_symbol(FILE *in, struct sym_entry *
- else if (toupper(s->type) == 'U' ||
- is_arm_mapping_symbol(sym))
- return -1;
-+ /* exclude also MIPS ELF local symbols ($L123 instead of .L123) */
-+ else if (str[0] == '$')
-+ return -1;
-
- /* include the type field in the symbol name, so that it gets
- * compressed together */
-diff -urpNX dontdiff linux-2.6.12/sound/oss/Kconfig linux_HEAD/sound/oss/Kconfig
---- linux-2.6.12/sound/oss/Kconfig 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/sound/oss/Kconfig 2005-07-01 12:10:55.000000000 +0200
-@@ -202,7 +202,7 @@ config SOUND_HAL2
- depends on SOUND_PRIME!=n && SOUND && SGI_IP22 && EXPERIMENTAL
- help
- Say Y or M if you have an SGI Indy system and want to be able to
-- use it's on-board A2 audio system.
-+ use it's on-board A2 audio system
-
- config SOUND_IT8172
- tristate "IT8172G Sound"
-@@ -224,6 +224,10 @@ config SOUND_AU1550_AC97
+diff -urN --ignore-space-change kernel.org/include/linux/serial_ip3106.h linux-mips/include/linux/serial_ip3106.h
+--- kernel.org/include/linux/serial_ip3106.h 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/include/linux/serial_ip3106.h 2006-01-10 11:22:04.000000000 +0000
+@@ -78,4 +78,16 @@
+ #define IP3106_UART_FIFO_RXFIFO 0x00001F00
+ #define IP3106_UART_FIFO_RBRTHR 0x000000FF
+
++#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
++#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
++#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
++#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
++#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
++#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
++#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
++#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
++#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
++#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
++#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
++
+ #endif
+diff -urN --ignore-space-change kernel.org/sound/oss/Kconfig linux-mips/sound/oss/Kconfig
+--- kernel.org/sound/oss/Kconfig 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/sound/oss/Kconfig 2006-01-10 11:22:07.000000000 +0000
+@@ -239,6 +239,10 @@
tristate "Au1550 AC97 Sound"
- depends on SOUND_PRIME!=n && SOC_AU1550 && SOUND
+ depends on SOUND_PRIME && SOC_AU1550
+config SOUND_AU1550_I2S
+ tristate "Au1550 I2S Sound"
-+ depends on SOUND_PRIME!=n && SOC_AU1550 && SOUND
++ depends on SOUND_PRIME && SOC_AU1550
+
config SOUND_TRIDENT
tristate "Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core"
- depends on SOUND_PRIME!=n && SOUND
-diff -urpNX dontdiff linux-2.6.12/sound/oss/Makefile linux_HEAD/sound/oss/Makefile
---- linux-2.6.12/sound/oss/Makefile 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/sound/oss/Makefile 2005-07-10 12:26:12.000000000 +0200
-@@ -64,8 +64,9 @@ endif
- obj-$(CONFIG_SOUND_ES1370) += es1370.o
- obj-$(CONFIG_SOUND_ES1371) += es1371.o ac97_codec.o
+ depends on SOUND_PRIME && PCI
+diff -urN --ignore-space-change kernel.org/sound/oss/Makefile linux-mips/sound/oss/Makefile
+--- kernel.org/sound/oss/Makefile 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/sound/oss/Makefile 2006-01-10 11:22:07.000000000 +0000
+@@ -66,6 +66,7 @@
obj-$(CONFIG_SOUND_VRC5477) += nec_vrc5477.o ac97_codec.o
--obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o
--obj-$(CONFIG_SOUND_AU1550_AC97) += au1550_ac97.o ac97_codec.o
-+obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o
-+obj-$(CONFIG_SOUND_AU1550_AC97) += au1550_ac97.o ac97_codec.o
-+obj-$(CONFIG_SOUND_AU1550_I2S) += au1550_i2s.o
+ obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o
+ obj-$(CONFIG_SOUND_AU1550_AC97) += au1550_ac97.o ac97_codec.o
++obj-$(CONFIG_SOUND_AU1550_I2S) += au1550_i2s.o
obj-$(CONFIG_SOUND_ESSSOLO1) += esssolo1.o
obj-$(CONFIG_SOUND_FUSION) += cs46xx.o ac97_codec.o
obj-$(CONFIG_SOUND_MAESTRO) += maestro.o
-diff -urpNX dontdiff linux-2.6.12/sound/oss/au1550_ac97.c linux_HEAD/sound/oss/au1550_ac97.c
---- linux-2.6.12/sound/oss/au1550_ac97.c 2005-06-17 21:48:29.000000000 +0200
-+++ linux_HEAD/sound/oss/au1550_ac97.c 2005-07-10 12:28:27.000000000 +0200
-@@ -35,7 +35,6 @@
-
- #undef DEBUG
-
--#include <linux/version.h>
- #include <linux/module.h>
- #include <linux/string.h>
- #include <linux/ioport.h>
-@@ -59,6 +58,7 @@
+diff -urN --ignore-space-change kernel.org/sound/oss/au1550_ac97.c linux-mips/sound/oss/au1550_ac97.c
+--- kernel.org/sound/oss/au1550_ac97.c 2006-01-03 03:21:10.000000000 +0000
++++ linux-mips/sound/oss/au1550_ac97.c 2006-01-10 11:22:07.000000000 +0000
+@@ -58,6 +58,7 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
@@ -69706,9 +21182,9 @@
#undef OSS_DOCUMENTED_MIXER_SEMANTICS
-diff -urpNX dontdiff linux-2.6.12/sound/oss/au1550_i2s.c linux_HEAD/sound/oss/au1550_i2s.c
---- linux-2.6.12/sound/oss/au1550_i2s.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux_HEAD/sound/oss/au1550_i2s.c 2005-04-14 16:40:19.000000000 +0200
+diff -urN --ignore-space-change kernel.org/sound/oss/au1550_i2s.c linux-mips/sound/oss/au1550_i2s.c
+--- kernel.org/sound/oss/au1550_i2s.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-mips/sound/oss/au1550_i2s.c 2006-01-10 11:22:07.000000000 +0000
@@ -0,0 +1,2029 @@
+/*
+ * au1550_i2s.c -- Sound driver for Alchemy Au1550 MIPS
@@ -69725,7 +21201,7 @@
+ * WM8731 mixer support, codec framework, cleanup, and 2.6 port
+ * Matt Porter <mporter at kernel.crashing.org>
+ *
-+ * The SMBus (I2C) is required for the control of the
++ * The SMBus (I2C) is required for the control of the
+ * appears at I2C address 0x36 (I2C binary 0011011). The Pb1550
+ * uses the Wolfson WM8731 codec, which is controlled over the I2C.
+ * It's connected to a 12MHz clock, so we can only reliably support
@@ -69872,7 +21348,7 @@
+ * The ls bit of the first byte is the ms bit of the data.
+ */
+ rcnt = 0;
-+ while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
++ while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
+ && (rcnt < 50)) {
+ rcnt++;
+ }
@@ -70471,7 +21947,7 @@
+ default: /* read a specific mixer */
+ i = _IOC_NR(cmd);
+
-+ if (!i2s_supported_mixer(codec, i))
++ if (!i2s_supported_mixer(codec, i))
+ return -EINVAL;
+
+ val = codec->mixer_state[i];
@@ -70496,7 +21972,7 @@
+ default: /* write a specific mixer */
+ i = _IOC_NR(cmd);
+
-+ if (!i2s_supported_mixer(codec, i))
++ if (!i2s_supported_mixer(codec, i))
+ return -EINVAL;
+
+ codec->set_mixer(codec, i, val);
@@ -70803,7 +22279,7 @@
+
+ count *= db->cnt_factor;
+
-+ down(&s->sem);
++ down(&s->sem);
+ add_wait_queue(&db->wait, &wait);
+
+ while (count > 0) {
@@ -70903,7 +22379,7 @@
+ }
+
+ spin_lock_irqsave(&s->lock, flags);
-+
++
+ if (file->f_mode & FMODE_READ) {
+ if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
+ mask |= POLLIN | POLLRDNORM;
@@ -70911,7 +22387,7 @@
+ if (file->f_mode & FMODE_WRITE) {
+ if (s->dma_dac.mapped) {
+ if (s->dma_dac.count >=
-+ (signed)s->dma_dac.dma_fragsize)
++ (signed)s->dma_dac.dma_fragsize)
+ mask |= POLLOUT | POLLWRNORM;
+ } else {
+ if ((signed) s->dma_dac.dmasize >=
@@ -71413,7 +22889,7 @@
+ else
+ dbg(__FUNCTION__ ": blocking");
+#endif
-+
++
+ file->private_data = s;
+ /* wait for device to become free */
+ down(&s->open_sem);
@@ -71477,7 +22953,7 @@
+ struct au1550_state *s = (struct au1550_state *)file->private_data;
+
+ lock_kernel();
-+
++
+ if (file->f_mode & FMODE_WRITE) {
+ unlock_kernel();
+ drain_dac(s, file->f_flags & O_NONBLOCK);
Added: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/15_interrupt.dpatch
==============================================================================
--- (empty file)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/15_interrupt.dpatch Mon Jan 16 17:33:25 2006
@@ -0,0 +1,61 @@
+#! /bin/sh -e
+## 15_interrupt.dpatch by Ed Martini <martini at c2micro.com>
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Catch runaway assembler directive.
+
+if [ $# -lt 1 ]; then
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+ -patch) patch -p0 ${patch_opts} < $0;;
+ -unpatch) patch -R -p0 ${patch_opts} < $0;;
+ *)
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1;;
+esac
+
+exit 0
+
+In include/asm-mips/interrupt.h, the definition for local_irq_restore is
+inconsistent in its use of .reorder/.noreorder assembler directives.
+Other asm macros in interrupt.h are wrapped with '.set push' and '.set pop'.
+
+It doesn't seem to be a problem with the 2.96 mipsel-linux- assembler,
+but it caused me a problem with my 4.0-based toolchain. (As it was the
+local_irq_restore left the assembler in 'reorder' mode and a stack
+pointer post-inc was reordered out of the return delay slot where it
+belonged.) Luckily we have a sharp compiler guy who figured it out.
+Thanks.
+
+As usual, there may be a reason for this, but it took me a whole day to
+find it, and I thought I'd point it out.
+
+Ed Martini
+
+diff -urN linux-mips/include/asm-mips/interrupt.h new/include/asm-mips/interrupt.h
+--- linux-mips/include/asm-mips/interrupt.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/interrupt.h 2006-01-16 16:35:39.000000000 +0000
+@@ -114,6 +114,7 @@
+
+ __asm__ (
+ " .macro local_irq_restore flags \n"
++ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+@@ -141,8 +142,7 @@
+ " mtc0 \\flags, $12 \n"
+ #endif
+ " irq_disable_hazard \n"
+- " .set at \n"
+- " .set reorder \n"
++ " .set pop \n"
+ " .endm \n");
+
+ #define local_irq_restore(flags) \
Added: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/18_gettimeofday.dpatch
==============================================================================
--- (empty file)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/18_gettimeofday.dpatch Mon Jan 16 17:33:25 2006
@@ -0,0 +1,343 @@
+#! /bin/sh -e
+## 18_gettimeofday.dpatch by Dave Johnson <djohnson+linuxmips at sw.starentnetworks.com>
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: gettimeofday jumps backwards then forwards.
+
+if [ $# -lt 1 ]; then
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+ -patch) patch -p1 ${patch_opts} < $0;;
+ -unpatch) patch -R -p1 ${patch_opts} < $0;;
+ *)
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1;;
+esac
+
+exit 0
+
+Below are 2 fixes I made to 2.6.12 to do with time jumping around
+as reported by gettimeofday(). One is SB1250 specific and one appears
+generic.
+
+The symptom is revealed by running multile copies (1 per cpu) of a
+simple test program that calls gettimeofday() as fast as possible
+looking for time to go backwards.
+
+When a jump is detected the program outputs a few samples before and
+after each jump:
+
+value delta
+1121781527.912525: 1
+1121781527.912525: 0
+1121781527.912526: 1
+1121781527.912526: 0
+1121781527.912527: 1
+1121781527.912527: 0
+1121781527.912527: 0
+1121781527.912527: 0
+1121781527.911528: -999
+1121781527.911529: 1
+1121781527.911530: 1
+1121781527.912532: 1002
+1121781527.912533: 1
+1121781527.912533: 0
+1121781527.912534: 1
+1121781527.912534: 0
+1121781527.912535: 1
+1121781527.912536: 1
+
+value delta
+1121781545.635524: 1
+1121781545.635524: 0
+1121781545.635525: 1
+1121781545.635525: 0
+1121781545.635526: 1
+1121781545.635526: 0
+1121781545.635527: 1
+1121781545.635527: 0
+1121781545.634527: -1000
+1121781545.635527: 1000
+1121781545.635528: 1
+1121781545.635529: 1
+1121781545.635529: 0
+1121781545.635530: 1
+1121781545.635530: 0
+1121781545.635531: 1
+1121781545.635531: 0
+1121781545.635532: 1
+1121781545.635533: 1
+
+Time jumps backwards 1msec then forwards 1msec a few usec
+later. Usually lasts < 2us but I've seen it as long as 5us if the
+system is under load.
+
+--
+
+First problem I found is that sb1250_gettimeoffset() simply reads the
+current cpu 0 timer remaining value, however once this counter reaches
+0 and the interrupt is raised, it immediately resets and begins to
+count down again.
+
+If sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday()
+after the timer has reset but prior to cpu 0 processing the interrupt
+and taking write_seqlock() in timer_interrupt() it will return a
+full value (or close to it) causing time to jump backwards 1ms. Once
+cpu 0 handles the interrupt and timer_interrupt() gets far enough
+along it will jump forward 1ms.
+
+To fix this problem I implemented mips_hpt_*() on sb1250 using a spare
+timer unrelated to the existing periodic interrupt timers. It runs at
+1Mhz with a full 23bit counter. This eliminated the custom
+do_gettimeoffset() for sb1250 and allowed use of the generic
+fixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo.
+
+--
+
+The second problem is that more of timer_interrupt() needs to be
+protected by xtime_lock:
+
+* do_timer() expects the arch-specific handler to take the lock as it
+ modifies jiffies[_64] and xtime.
+* writing timerhi/lo in timer_interrupt() will mess up
+ fixed_rate_gettimeoffset() which reads timerhi/lo.
+
+--
+
+With both changes do_gettimeofday() works correctly on both cpu 0 and
+cpu 1.
+
+--
+
+Other changes/cleanups:
+
+The existing sb1250 periodic timers were slow by 999ppm (given a
+perfect 100mhz reference). The timers need to be loaded with 1 less
+than the desired interval not the interval itself.
+
+M_SCD_TIMER_INIT and M_SCD_TIMER_CNT had the wrong field width (should
+be 23 bits not 20 bits)
+
+============
+
+diff -urN linux-mips/arch/mips/kernel/time.c new/arch/mips/kernel/time.c
+--- linux-mips/arch/mips/kernel/time.c 2006-01-10 11:21:15.000000000 +0000
++++ new/arch/mips/kernel/time.c 2006-01-16 16:40:10.000000000 +0000
+@@ -423,6 +423,8 @@
+ unsigned long j;
+ unsigned int count;
+
++ write_seqlock(&xtime_lock);
++
+ count = mips_hpt_read();
+ mips_timer_ack();
+
+@@ -440,7 +442,6 @@
+ * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
+ * called as close as possible to 500 ms before the new second starts.
+ */
+- write_seqlock(&xtime_lock);
+ if (ntp_synced() &&
+ xtime.tv_sec > last_rtc_update + 660 &&
+ (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
+@@ -452,7 +453,6 @@
+ last_rtc_update = xtime.tv_sec - 600;
+ }
+ }
+- write_sequnlock(&xtime_lock);
+
+ /*
+ * If jiffies has overflown in this timer_interrupt, we must
+@@ -495,6 +495,8 @@
+ }
+ }
+
++ write_sequnlock(&xtime_lock);
++
+ /*
+ * In UP mode, we call local_timer_interrupt() to do profiling
+ * and process accouting.
+diff -urN linux-mips/arch/mips/sibyte/sb1250/time.c new/arch/mips/sibyte/sb1250/time.c
+--- linux-mips/arch/mips/sibyte/sb1250/time.c 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/sibyte/sb1250/time.c 2006-01-16 16:39:27.000000000 +0000
+@@ -47,23 +47,51 @@
+ #define IMR_IP3_VAL K_INT_MAP_I1
+ #define IMR_IP4_VAL K_INT_MAP_I2
+
++#define SB1250_HPT_NUM 3
++#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
++#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
++
++
+ extern int sb1250_steal_irq(int irq);
+
++static unsigned int sb1250_hpt_read(void);
++static void sb1250_hpt_init(unsigned int);
++
++static unsigned int hpt_offset;
++
++void __init sb1250_hpt_setup(void)
++{
++ int cpu = smp_processor_id();
++
++ if (!cpu) {
++ /* Setup hpt using timer #3 but do not enable irq for it */
++ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
++ __raw_writeq(SB1250_HPT_VALUE,
++ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
++ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
++ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
++
++ /*
++ * we need to fill 32 bits, so just use the upper 23 bits and pretend
++ * the timer is going 512Mhz instead of 1Mhz
++ */
++ mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
++ mips_hpt_init = sb1250_hpt_init;
++ mips_hpt_read = sb1250_hpt_read;
++ }
++}
++
++
+ void sb1250_time_init(void)
+ {
+ int cpu = smp_processor_id();
+ int irq = K_INT_TIMER_0+cpu;
+
+- /* Only have 4 general purpose timers */
+- if (cpu > 3) {
++ /* Only have 4 general purpose timers, and we use last one as hpt */
++ if (cpu > 2) {
+ BUG();
+ }
+
+- if (!cpu) {
+- /* Use our own gettimeoffset() routine */
+- do_gettimeoffset = sb1250_gettimeoffset;
+- }
+-
+ sb1250_mask_irq(cpu, irq);
+
+ /* Map the timer interrupt to ip[4] of this cpu */
+@@ -75,10 +103,10 @@
+ /* Disable the timer and set up the count */
+ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+ #ifdef CONFIG_SIMULATION
+- __raw_writeq(50000 / HZ,
++ __raw_writeq((50000 / HZ) - 1,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
+ #else
+- __raw_writeq(1000000 / HZ,
++ __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
+ #endif
+
+@@ -103,7 +131,7 @@
+ int cpu = smp_processor_id();
+ int irq = K_INT_TIMER_0 + cpu;
+
+- /* Reset the timer */
++ /* ACK interrupt */
+ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+
+@@ -122,15 +150,26 @@
+ }
+
+ /*
+- * We use our own do_gettimeoffset() instead of the generic one,
+- * because the generic one does not work for SMP case.
+- * In addition, since we use general timer 0 for system time,
+- * we can get accurate intra-jiffy offset without calibration.
++ * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
++ * again. There's no easy way to set to a specific value so store init value
++ * in hpt_offset and subtract each time.
++ *
++ * Note: Timer isn't full 32bits so shift it into the upper part making
++ * it appear to run at a higher frequency.
+ */
+-unsigned long sb1250_gettimeoffset(void)
++static unsigned int sb1250_hpt_read(void)
+ {
+- unsigned long count =
+- __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
++ unsigned int count;
+
+- return 1000000/HZ - count;
+- }
++ count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
++
++ count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
++
++ return count - hpt_offset;
++}
++
++static void sb1250_hpt_init(unsigned int count)
++{
++ hpt_offset = count;
++ return;
++}
+diff -urN linux-mips/arch/mips/sibyte/swarm/setup.c new/arch/mips/sibyte/swarm/setup.c
+--- linux-mips/arch/mips/sibyte/swarm/setup.c 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/sibyte/swarm/setup.c 2006-01-16 16:39:27.000000000 +0000
+@@ -70,6 +70,12 @@
+ return "SiByte " SIBYTE_BOARD_NAME;
+ }
+
++void __init swarm_time_init(void)
++{
++ /* Setup HPT */
++ sb1250_hpt_setup();
++}
++
+ void __init swarm_timer_setup(struct irqaction *irq)
+ {
+ /*
+@@ -109,6 +115,7 @@
+
+ panic_timeout = 5; /* For debug. */
+
++ board_time_init = swarm_time_init;
+ board_timer_setup = swarm_timer_setup;
+ board_be_handler = swarm_be_handler;
+
+diff -urN linux-mips/include/asm-mips/sibyte/sb1250.h new/include/asm-mips/sibyte/sb1250.h
+--- linux-mips/include/asm-mips/sibyte/sb1250.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/sibyte/sb1250.h 2006-01-16 16:39:27.000000000 +0000
+@@ -45,8 +45,8 @@
+ extern unsigned int periph_rev;
+ extern unsigned int zbbus_mhz;
+
++extern void sb1250_hpt_setup(void);
+ extern void sb1250_time_init(void);
+-extern unsigned long sb1250_gettimeoffset(void);
+ extern void sb1250_mask_irq(int cpu, int irq);
+ extern void sb1250_unmask_irq(int cpu, int irq);
+ extern void sb1250_smp_finish(void);
+diff -urN linux-mips/include/asm-mips/sibyte/sb1250_scd.h new/include/asm-mips/sibyte/sb1250_scd.h
+--- linux-mips/include/asm-mips/sibyte/sb1250_scd.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/sibyte/sb1250_scd.h 2006-01-16 16:39:27.000000000 +0000
+@@ -359,14 +359,15 @@
+ */
+
+ #define V_SCD_TIMER_FREQ 1000000
++#define V_SCD_TIMER_WIDTH 23
+
+ #define S_SCD_TIMER_INIT 0
+-#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
++#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
+ #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
+ #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
+
+ #define S_SCD_TIMER_CNT 0
+-#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
++#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
+ #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
+ #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
+
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/20_ioc3.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/20_ioc3.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/20_ioc3.dpatch Mon Jan 16 17:33:25 2006
@@ -3,7 +3,7 @@
##
## All lines beginning with `## DP:' are a description of the patch.
## DP: Improved ioc3 driver, from
-## DP: ftp://ftp.linux-mips.org/pub/linux/mips/people/skylark/linux-mips-2.6.12-ioc3-r23.patch.bz2
+## DP: ftp://ftp.linux-mips.org/pub/linux/mips/people/skylark/linux-mips-2.6.14-ioc3-r26.patch.bz2
if [ $# -lt 1 ]; then
echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
@@ -23,10 +23,10 @@
exit 0
-diff -urN linux-2.6.12/arch/mips/Kconfig linux-2.6.12-ioc3/arch/mips/Kconfig
---- linux-2.6.12/arch/mips/Kconfig 2005-07-08 13:12:04.000000000 +0200
-+++ linux-2.6.12-ioc3/arch/mips/Kconfig 2005-07-09 13:35:08.000000000 +0200
-@@ -1309,6 +1309,14 @@
+diff -urN linux-mips/arch/mips/Kconfig new/arch/mips/Kconfig
+--- linux-mips/arch/mips/Kconfig 2006-01-10 11:21:15.000000000 +0000
++++ new/arch/mips/Kconfig 2006-01-16 17:21:41.000000000 +0000
+@@ -1662,6 +1662,14 @@
source "drivers/pci/Kconfig"
@@ -41,18 +41,18 @@
#
# ISA support is now enabled via select. Too many systems still have the one
# or other ISA chip on the board that users don't know about so don't expect
-diff -urN linux-2.6.12/arch/mips/pci/Makefile linux-2.6.12-ioc3/arch/mips/pci/Makefile
---- linux-2.6.12/arch/mips/pci/Makefile 2004-12-18 03:23:50.000000000 +0100
-+++ linux-2.6.12-ioc3/arch/mips/pci/Makefile 2005-07-09 13:35:08.000000000 +0200
-@@ -52,3 +52,5 @@
- obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
+diff -urN linux-mips/arch/mips/pci/Makefile new/arch/mips/pci/Makefile
+--- linux-mips/arch/mips/pci/Makefile 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/pci/Makefile 2006-01-16 17:21:41.000000000 +0000
+@@ -55,3 +55,5 @@
+ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
+
+obj-$(CONFIG_SGI_IOC3) += ioc3.o
-diff -urN linux-2.6.12/arch/mips/pci/ioc3.c linux-2.6.12-ioc3/arch/mips/pci/ioc3.c
---- linux-2.6.12/arch/mips/pci/ioc3.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ioc3/arch/mips/pci/ioc3.c 2005-07-11 07:32:52.000000000 +0200
+diff -urN linux-mips/arch/mips/pci/ioc3.c new/arch/mips/pci/ioc3.c
+--- linux-mips/arch/mips/pci/ioc3.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/pci/ioc3.c 2006-01-16 17:21:41.000000000 +0000
@@ -0,0 +1,801 @@
+/*
+ * SGI IOC3 master driver and IRQ demuxer
@@ -821,8 +821,8 @@
+ {0}
+};
+
-+static struct pci_driver __devinitdata ioc3_driver = {
-+ .name = "IOC3",
++static struct pci_driver ioc3_driver = {
++ .name = "SGI IOC3",
+ .id_table = ioc3_id_table,
+ .probe = ioc3_probe,
+ .remove = ioc3_remove,
@@ -855,171 +855,21 @@
+
+EXPORT_SYMBOL(ioc3_register_submodule);
+EXPORT_SYMBOL(ioc3_unregister_submodule);
-diff -urN linux-2.6.12/drivers/char/Kconfig linux-2.6.12-ioc3/drivers/char/Kconfig
---- linux-2.6.12/drivers/char/Kconfig 2005-07-08 13:13:13.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/char/Kconfig 2005-07-09 13:35:08.000000000 +0200
-@@ -390,6 +390,13 @@
- Documentation on the Zilog 85C350 serial communications controller
- is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
-
-+config SGI_IOC3_UART
-+ bool "SGI IOC3 UART support"
-+ depends on SGI_IOC3 && SERIAL_8250
-+ help
-+ Enable this if you have a SGI Origin or Octane machine. This module
-+ provides serial port support for IOC3 chips on those systems.
-+
- config QTRONIX_KEYBOARD
- bool "Enable Qtronix 990P Keyboard Support"
- depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
-diff -urN linux-2.6.12/drivers/char/Makefile linux-2.6.12-ioc3/drivers/char/Makefile
---- linux-2.6.12/drivers/char/Makefile 2005-07-08 13:13:13.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/char/Makefile 2005-07-09 13:35:08.000000000 +0200
-@@ -64,6 +64,7 @@
- obj-$(CONFIG_EFI_RTC) += efirtc.o
- obj-$(CONFIG_SGI_DS1286) += ds1286.o
- obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
-+obj-$(CONFIG_SGI_IOC3_UART) += ioc3uart.o
- obj-$(CONFIG_DS1302) += ds1302.o
- obj-$(CONFIG_S3C2410_RTC) += s3c2410-rtc.o
- ifeq ($(CONFIG_GENERIC_NVRAM),y)
-diff -urN linux-2.6.12/drivers/char/ioc3uart.c linux-2.6.12-ioc3/drivers/char/ioc3uart.c
---- linux-2.6.12/drivers/char/ioc3uart.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ioc3/drivers/char/ioc3uart.c 2005-07-09 13:35:08.000000000 +0200
-@@ -0,0 +1,130 @@
-+/*
-+ * SGI IOC3 bridge for UARTs
-+ *
-+ * Copyright (C) 2005 Stanislaw Skowronek <skylark at linux-mips.org>
-+ */
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/serio.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/err.h>
-+#include <linux/pci.h>
-+
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/system.h>
-+#include <linux/ioc3.h>
-+
-+#include <linux/serial.h>
-+#include <asm/serial.h>
-+#define IOC3_BAUD (22000000 / (3*16))
-+
-+MODULE_AUTHOR("Stanislaw Skowronek <skylark at linux-mips.org>");
-+MODULE_DESCRIPTION("SGI IOC3 UART driver");
-+MODULE_LICENSE("GPL");
-+
-+/* !!! write dynirq support for IP27 !!! */
-+#ifdef CONFIG_SGI_IP30
-+int new_dynamic_irq(void);
-+void call_dynamic_irq(int irq, struct pt_regs *regs);
-+void delete_dynamic_irq(int irq);
-+#else
-+int new_dynamic_irq(void) { return 0; }
-+void call_dynamic_irq(int irq, struct pt_regs *regs) { }
-+void delete_dynamic_irq(int irq) { }
-+#endif
-+
-+struct ioc3uart_data {
-+ int line_a, line_b;
-+ int irq;
-+};
-+
-+static int ioc3uart_intr(struct ioc3_submodule *is, struct ioc3_driver_data *idd, unsigned int irq, struct pt_regs *regs)
-+{
-+ struct ioc3uart_data *d = (struct ioc3uart_data *)(idd->data[is->id]);
-+
-+ ioc3_ack(is, idd, irq);
-+ call_dynamic_irq(d->irq, regs);
-+
-+ return 0;
-+}
-+
-+static int ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
-+{
-+ struct serial_struct req;
-+ struct ioc3uart_data *d;
-+ memset(&req, 0, sizeof(req));
-+
-+ /* check for UART-less add-on boards */
-+ if(idd->class == IOC3_CLASS_MENET_4 || idd->class == IOC3_CLASS_CADDUO)
-+ return 1;
-+
-+ /* set PIO mode for SuperIO UARTs */
-+ idd->vma->sscr_a = 0;
-+ idd->vma->sscr_b = 0;
-+ udelay(1000);
-+ idd->vma->sregs.uarta.iu_fcr = 0;
-+ idd->vma->sregs.uartb.iu_fcr = 0;
-+ udelay(1000);
-+
-+ d = kmalloc(sizeof(struct ioc3uart_data), GFP_KERNEL);
-+ idd->data[is->id] = d;
-+ d->irq = new_dynamic_irq();
-+
-+ /* register serial ports with 8250.c */
-+ req.irq = d->irq;
-+ req.flags = 0;
-+ req.io_type = SERIAL_IO_IOC3;
-+ req.iomem_reg_shift = 0;
-+ req.baud_base = IOC3_BAUD;
-+ req.iomem_base = (unsigned char *) &idd->vma->sregs.uarta;
-+ req.iomap_base = ((unsigned long) req.iomem_base) & 0xFFFFFFFFFF;
-+ d->line_a = register_serial(&req);
-+
-+ req.iomem_base = (unsigned char *) &idd->vma->sregs.uartb;
-+ req.iomap_base = ((unsigned long) req.iomem_base) & 0xFFFFFFFFFF;
-+ d->line_b = register_serial(&req);
-+
-+ ioc3_enable(is, idd);
-+ return 0;
-+}
-+
-+static int ioc3uart_remove(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
-+{
-+ struct ioc3uart_data *d = (struct ioc3uart_data *)(idd->data[is->id]);
-+ unregister_serial(d->line_a);
-+ unregister_serial(d->line_b);
-+ delete_dynamic_irq(d->irq);
-+ kfree(d);
-+ idd->data[is->id] = NULL;
-+ return 0;
-+}
-+
-+static struct ioc3_submodule ioc3uart_submodule = {
-+ .name = "uart",
-+ .probe = ioc3uart_probe,
-+ .remove = ioc3uart_remove,
-+ .irq_mask = SIO_IR_SA_INT | SIO_IR_SB_INT,
-+ .intr = ioc3uart_intr,
-+ .owner = THIS_MODULE,
-+};
-+
-+static int __init ioc3uart_init(void)
-+{
-+ ioc3_register_submodule(&ioc3uart_submodule);
-+ return 0;
-+}
-+
-+static void __exit ioc3uart_exit(void)
-+{
-+ ioc3_unregister_submodule(&ioc3uart_submodule);
-+}
-+
-+module_init(ioc3uart_init);
-+module_exit(ioc3uart_exit);
-diff -urN linux-2.6.12/drivers/input/serio/Kconfig linux-2.6.12-ioc3/drivers/input/serio/Kconfig
---- linux-2.6.12/drivers/input/serio/Kconfig 2005-03-18 21:40:38.000000000 +0100
-+++ linux-2.6.12-ioc3/drivers/input/serio/Kconfig 2005-07-09 13:35:08.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip27/ip27-console.c new/arch/mips/sgi-ip27/ip27-console.c
+--- linux-mips/arch/mips/sgi-ip27/ip27-console.c 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/sgi-ip27/ip27-console.c 2006-01-16 17:21:41.000000000 +0000
+@@ -64,7 +64,7 @@
+ up.irq = 0;
+ up.uartclk = IOC3_CLK;
+ up.regshift = 0;
+- up.iotype = UPIO_MEM;
++ up.iotype = UPIO_IOC3;
+ up.flags = IOC3_FLAGS;
+ up.line = 0;
+
+diff -urN linux-mips/drivers/input/serio/Kconfig new/drivers/input/serio/Kconfig
+--- linux-mips/drivers/input/serio/Kconfig 2006-01-10 11:21:35.000000000 +0000
++++ new/drivers/input/serio/Kconfig 2006-01-16 17:21:41.000000000 +0000
@@ -18,6 +18,13 @@
if SERIO
@@ -1034,9 +884,9 @@
config SERIO_I8042
tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
default y
-diff -urN linux-2.6.12/drivers/input/serio/Makefile linux-2.6.12-ioc3/drivers/input/serio/Makefile
---- linux-2.6.12/drivers/input/serio/Makefile 2005-03-18 21:40:38.000000000 +0100
-+++ linux-2.6.12-ioc3/drivers/input/serio/Makefile 2005-07-09 13:35:08.000000000 +0200
+diff -urN linux-mips/drivers/input/serio/Makefile new/drivers/input/serio/Makefile
+--- linux-mips/drivers/input/serio/Makefile 2006-01-10 11:21:35.000000000 +0000
++++ new/drivers/input/serio/Makefile 2006-01-16 17:21:41.000000000 +0000
@@ -19,5 +19,6 @@
obj-$(CONFIG_HIL_MLC) += hp_sdc_mlc.o hil_mlc.o
obj-$(CONFIG_SERIO_PCIPS2) += pcips2.o
@@ -1044,9 +894,9 @@
+obj-$(CONFIG_SERIO_SGI_IOC3) += ioc3kbd.o
obj-$(CONFIG_SERIO_LIBPS2) += libps2.o
obj-$(CONFIG_SERIO_RAW) += serio_raw.o
-diff -urN linux-2.6.12/drivers/input/serio/ioc3kbd.c linux-2.6.12-ioc3/drivers/input/serio/ioc3kbd.c
---- linux-2.6.12/drivers/input/serio/ioc3kbd.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ioc3/drivers/input/serio/ioc3kbd.c 2005-07-09 13:35:08.000000000 +0200
+diff -urN linux-mips/drivers/input/serio/ioc3kbd.c new/drivers/input/serio/ioc3kbd.c
+--- linux-mips/drivers/input/serio/ioc3kbd.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/input/serio/ioc3kbd.c 2006-01-16 17:21:41.000000000 +0000
@@ -0,0 +1,172 @@
+/*
+ * SGI IOC3 PS/2 controller driver for linux
@@ -1220,10 +1070,10 @@
+
+module_init(ioc3kbd_init);
+module_exit(ioc3kbd_exit);
-diff -urN linux-2.6.12/drivers/net/Kconfig linux-2.6.12-ioc3/drivers/net/Kconfig
---- linux-2.6.12/drivers/net/Kconfig 2005-07-08 13:14:10.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/net/Kconfig 2005-07-09 13:35:08.000000000 +0200
-@@ -449,7 +449,7 @@
+diff -urN linux-mips/drivers/net/Kconfig new/drivers/net/Kconfig
+--- linux-mips/drivers/net/Kconfig 2006-01-10 11:21:37.000000000 +0000
++++ new/drivers/net/Kconfig 2006-01-16 17:19:34.000000000 +0000
+@@ -451,7 +451,7 @@
config SGI_IOC3_ETH
bool "SGI IOC3 Ethernet"
@@ -1232,9 +1082,9 @@
select CRC32
select MII
help
-diff -urN linux-2.6.12/drivers/net/ioc3-eth.c linux-2.6.12-ioc3/drivers/net/ioc3-eth.c
---- linux-2.6.12/drivers/net/ioc3-eth.c 2005-07-08 13:14:29.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/net/ioc3-eth.c 2005-07-09 13:35:08.000000000 +0200
+diff -urN linux-mips/drivers/net/ioc3-eth.c new/drivers/net/ioc3-eth.c
+--- linux-mips/drivers/net/ioc3-eth.c 2006-01-10 11:21:38.000000000 +0000
++++ new/drivers/net/ioc3-eth.c 2006-01-16 17:21:41.000000000 +0000
@@ -5,6 +5,7 @@
*
* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
@@ -1260,21 +1110,19 @@
#include <linux/config.h>
#include <linux/init.h>
-@@ -45,13 +44,6 @@
+@@ -45,11 +44,6 @@
#include <linux/tcp.h>
#include <linux/udp.h>
-#ifdef CONFIG_SERIAL_8250
--#include <linux/serial.h>
--#include <asm/serial.h>
--#define IOC3_BAUD (22000000 / (3*16))
--#define IOC3_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+-#include <linux/serial_core.h>
+-#include <linux/serial_8250.h>
-#endif
-
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
-@@ -63,14 +55,19 @@
+@@ -61,14 +55,19 @@
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/uaccess.h>
@@ -1295,7 +1143,7 @@
/*
* 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
-@@ -83,6 +80,7 @@
+@@ -81,6 +80,7 @@
/* Private per NIC data of the driver. */
struct ioc3_private {
@@ -1303,7 +1151,7 @@
struct ioc3 *regs;
unsigned long *rxr; /* pointer to receiver ring */
struct ioc3_etxd *txr;
-@@ -151,8 +149,15 @@
+@@ -149,8 +149,15 @@
return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
((unsigned long)ptr & TO_PHYS_MASK);
#else
@@ -1319,7 +1167,7 @@
}
/* BEWARE: The IOC3 documentation documents the size of rx buffers as
-@@ -228,219 +233,6 @@
+@@ -226,219 +233,6 @@
#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
@@ -1539,14 +1387,14 @@
/*
* Ok, this is hosed by design. It's necessary to know what machine the
* NIC is in in order to know how to read the NIC address. We also have
-@@ -448,12 +240,16 @@
+@@ -446,12 +240,16 @@
*/
static void ioc3_get_eaddr(struct ioc3_private *ip)
{
- int i;
--
+ int i,nz=0;
+-
- ioc3_get_eaddr_nic(ip);
+ for(i=0;i<6;i++)
+ nz |= (priv_netdev(ip)->dev_addr[i] = ip->idd->nic_mac[i]);
@@ -1559,7 +1407,7 @@
for (i = 0; i < 6; i++) {
printk("%02x", priv_netdev(ip)->dev_addr[i]);
if (i < 5)
-@@ -752,9 +548,9 @@
+@@ -750,9 +548,9 @@
/* The interrupt handler does all of the Rx thread work and cleans up
after the Tx thread. */
@@ -1571,7 +1419,7 @@
struct ioc3_private *ip = netdev_priv(dev);
struct ioc3 *ioc3 = ip->regs;
const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
-@@ -775,7 +571,7 @@
+@@ -773,7 +571,7 @@
if (eisr & EISR_TXEXPLICIT)
ioc3_tx(ip);
@@ -1580,7 +1428,7 @@
}
static inline void ioc3_setup_duplex(struct ioc3_private *ip)
-@@ -842,6 +638,7 @@
+@@ -840,6 +638,7 @@
ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
ip->ioc3_timer.data = (unsigned long) ip;
ip->ioc3_timer.function = &ioc3_timer;
@@ -1588,7 +1436,7 @@
add_timer(&ip->ioc3_timer);
out:
-@@ -1028,7 +825,7 @@
+@@ -1026,7 +825,7 @@
(void) ioc3_r_emcr();
/* Misc registers */
@@ -1597,7 +1445,7 @@
ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
#else
ioc3_w_erbar(0); /* Let PCI API get it right */
-@@ -1065,12 +862,6 @@
+@@ -1063,12 +862,6 @@
{
struct ioc3_private *ip = netdev_priv(dev);
@@ -1610,7 +1458,7 @@
ip->ehar_h = 0;
ip->ehar_l = 0;
ioc3_init(dev);
-@@ -1088,101 +879,12 @@
+@@ -1086,105 +879,12 @@
netif_stop_queue(dev);
ioc3_stop(ip);
@@ -1672,12 +1520,11 @@
- * around ioc3 oddities in this respect.
- *
- * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
-- * (IOC3_BAUD = (22000000 / (3*16)))
- */
-
-static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
-{
-- struct serial_struct req;
+- struct uart_port port;
-
- /*
- * We need to recognice and treat the fourth MENET serial as it
@@ -1691,20 +1538,25 @@
- if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
- return;
-
-- /* Register to interrupt zero because we share the interrupt with
-- the serial driver which we don't properly support yet. */
-- memset(&req, 0, sizeof(req));
-- req.irq = 0;
-- req.flags = IOC3_COM_FLAGS;
-- req.io_type = SERIAL_IO_MEM;
-- req.iomem_reg_shift = 0;
-- req.baud_base = IOC3_BAUD;
+- /*
+- * Register to interrupt zero because we share the interrupt with
+- * the serial driver which we don't properly support yet.
+- *
+- * Can't use UPF_IOREMAP as the whole of IOC3 resources have already
+- * been registered.
+- */
+- memset(&port, 0, sizeof(port));
+- port.irq = 0;
+- port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
+- port.iotype = UPIO_MEM;
+- port.regshift = 0;
+- port.uartclk = 22000000 / 3;
-
-- req.iomem_base = (unsigned char *) &ioc3->sregs.uarta;
-- register_serial(&req);
+- port.membase = (unsigned char *) &ioc3->sregs.uarta;
+- serial8250_register_port(&port);
-
-- req.iomem_base = (unsigned char *) &ioc3->sregs.uartb;
-- register_serial(&req);
+- port.membase = (unsigned char *) &ioc3->sregs.uartb;
+- serial8250_register_port(&port);
-}
-#endif
-
@@ -1713,7 +1565,7 @@
{
unsigned int sw_physid1, sw_physid2;
struct net_device *dev = NULL;
-@@ -1192,63 +894,29 @@
+@@ -1194,63 +894,29 @@
u32 vendor, model, rev;
int err, pci_using_dac;
@@ -1787,7 +1639,7 @@
spin_lock_init(&ip->ioc3_lock);
init_timer(&ip->ioc3_timer);
-@@ -1256,7 +924,7 @@
+@@ -1258,7 +924,7 @@
ioc3_stop(ip);
ioc3_init(dev);
@@ -1796,7 +1648,7 @@
ip->mii.phy_id_mask = 0x1f;
ip->mii.reg_num_mask = 0x1f;
-@@ -1268,7 +936,7 @@
+@@ -1270,7 +936,7 @@
if (ip->mii.phy_id == -1) {
printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
@@ -1805,7 +1657,7 @@
err = -ENODEV;
goto out_stop;
}
-@@ -1314,56 +982,40 @@
+@@ -1316,56 +982,40 @@
out_stop:
ioc3_stop(ip);
ioc3_free_rings(ip);
@@ -1863,7 +1715,7 @@
static int __init ioc3_init_module(void)
{
-- return pci_module_init(&ioc3_driver);
+- return pci_register_driver(&ioc3_driver);
+ ioc3_register_submodule(&ioc3eth_submodule);
+ return 0;
}
@@ -1875,10 +1727,10 @@
}
static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
-diff -urN linux-2.6.12/drivers/serial/8250.c linux-2.6.12-ioc3/drivers/serial/8250.c
---- linux-2.6.12/drivers/serial/8250.c 2005-07-08 13:15:18.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/serial/8250.c 2005-07-10 22:21:00.000000000 +0200
-@@ -277,6 +277,9 @@
+diff -urN linux-mips/drivers/serial/8250.c new/drivers/serial/8250.c
+--- linux-mips/drivers/serial/8250.c 2006-01-10 11:21:48.000000000 +0000
++++ new/drivers/serial/8250.c 2006-01-16 17:21:41.000000000 +0000
+@@ -308,6 +308,9 @@
case UPIO_MEM:
return readb(up->port.membase + offset);
@@ -1888,7 +1740,7 @@
case UPIO_MEM32:
return readl(up->port.membase + offset);
-@@ -300,6 +303,10 @@
+@@ -336,6 +339,10 @@
writeb(value, up->port.membase + offset);
break;
@@ -1899,7 +1751,7 @@
case UPIO_MEM32:
writel(value, up->port.membase + offset);
break;
-@@ -1821,6 +1828,8 @@
+@@ -1917,6 +1924,8 @@
int ret = 0;
switch (up->port.iotype) {
@@ -1908,7 +1760,7 @@
case UPIO_MEM:
if (!up->port.mapbase)
break;
-@@ -1853,6 +1862,8 @@
+@@ -1949,6 +1958,8 @@
unsigned int size = 8 << up->port.regshift;
switch (up->port.iotype) {
@@ -1917,7 +1769,7 @@
case UPIO_MEM:
if (!up->port.mapbase)
break;
-@@ -2219,8 +2230,10 @@
+@@ -2322,8 +2333,10 @@
add_preferred_console("ttyS", line, options);
printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
@@ -1930,10 +1782,175 @@
(unsigned long) port->iobase, options);
if (!(serial8250_console.flags & CON_ENABLED)) {
serial8250_console.flags &= ~CON_PRINTBUFFER;
-diff -urN linux-2.6.12/drivers/serial/serial_core.c linux-2.6.12-ioc3/drivers/serial/serial_core.c
---- linux-2.6.12/drivers/serial/serial_core.c 2005-07-08 13:15:20.000000000 +0200
-+++ linux-2.6.12-ioc3/drivers/serial/serial_core.c 2005-07-09 13:35:08.000000000 +0200
-@@ -1606,9 +1606,10 @@
+diff -urN linux-mips/drivers/serial/Kconfig new/drivers/serial/Kconfig
+--- linux-mips/drivers/serial/Kconfig 2006-01-10 11:21:48.000000000 +0000
++++ new/drivers/serial/Kconfig 2006-01-16 17:21:41.000000000 +0000
+@@ -215,6 +215,13 @@
+ to this option. The driver can handle 1 or 2 serial ports.
+ If unsure, say N.
+
++config SGI_IOC3_UART
++ bool "SGI IOC3 UART support"
++ depends on SGI_IOC3 && SERIAL_8250
++ help
++ Enable this if you have a SGI Origin or Octane machine. This module
++ provides serial port support for IOC3 chips on those systems.
++
+ comment "Non-8250 serial port support"
+
+ config SERIAL_AMBA_PL010
+diff -urN linux-mips/drivers/serial/Makefile new/drivers/serial/Makefile
+--- linux-mips/drivers/serial/Makefile 2006-01-10 11:21:48.000000000 +0000
++++ new/drivers/serial/Makefile 2006-01-16 17:21:41.000000000 +0000
+@@ -57,4 +57,5 @@
+ obj-$(CONFIG_SERIAL_JSM) += jsm/
+ obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
+ obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
++obj-$(CONFIG_SGI_IOC3_UART) += ioc3uart.o
+ obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
+diff -urN linux-mips/drivers/serial/ioc3uart.c new/drivers/serial/ioc3uart.c
+--- linux-mips/drivers/serial/ioc3uart.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/serial/ioc3uart.c 2006-01-16 17:21:41.000000000 +0000
+@@ -0,0 +1,135 @@
++/*
++ * SGI IOC3 bridge for UARTs
++ *
++ * Copyright (C) 2005 Stanislaw Skowronek <skylark at linux-mips.org>
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/err.h>
++#include <linux/pci.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++#include <linux/ioc3.h>
++
++#include <linux/serial.h>
++#include <asm/serial.h>
++
++#include "8250.h"
++
++#define IOC3_UARTCLK (22000000 / 3)
++
++MODULE_AUTHOR("Stanislaw Skowronek <skylark at linux-mips.org>");
++MODULE_DESCRIPTION("SGI IOC3 UART driver");
++MODULE_LICENSE("GPL");
++
++/* !!! write dynirq support for IP27 !!! */
++#ifdef CONFIG_SGI_IP30
++int new_dynamic_irq(void);
++void call_dynamic_irq(int irq, struct pt_regs *regs);
++void delete_dynamic_irq(int irq);
++#else
++int new_dynamic_irq(void) { return 0; }
++void call_dynamic_irq(int irq, struct pt_regs *regs) { }
++void delete_dynamic_irq(int irq) { }
++#endif
++
++struct ioc3uart_data {
++ int line_a, line_b;
++ int irq;
++};
++
++static int ioc3uart_intr(struct ioc3_submodule *is, struct ioc3_driver_data *idd, unsigned int irq, struct pt_regs *regs)
++{
++ struct ioc3uart_data *d = (struct ioc3uart_data *)(idd->data[is->id]);
++
++ ioc3_ack(is, idd, irq);
++ call_dynamic_irq(d->irq, regs);
++
++ return 0;
++}
++
++static int ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
++{
++ struct uart_port port;
++ struct ioc3uart_data *d;
++
++ /* check for UART-less add-on boards */
++ if(idd->class == IOC3_CLASS_MENET_4 || idd->class == IOC3_CLASS_CADDUO)
++ return 1;
++
++ /* set PIO mode for SuperIO UARTs */
++ idd->vma->sscr_a = 0;
++ idd->vma->sscr_b = 0;
++ udelay(1000);
++ idd->vma->sregs.uarta.iu_fcr = 0;
++ idd->vma->sregs.uartb.iu_fcr = 0;
++ udelay(1000);
++
++ d = kmalloc(sizeof(struct ioc3uart_data), GFP_KERNEL);
++ idd->data[is->id] = d;
++ d->irq = new_dynamic_irq();
++
++ /* register serial ports with 8250.c */
++ memset(&port, 0, sizeof(struct uart_port));
++ port.irq = d->irq;
++ port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
++ port.uartclk = IOC3_UARTCLK;
++ port.iotype = UPIO_IOC3;
++ port.regshift = 0;
++ port.dev = &(idd->pdev->dev);
++
++ port.membase = (unsigned char *) &idd->vma->sregs.uarta;
++ port.mapbase = ((unsigned long) port.membase) & 0xFFFFFFFFFF;
++ d->line_a = serial8250_register_port(&port);
++
++ port.membase = (unsigned char *) &idd->vma->sregs.uartb;
++ port.mapbase = ((unsigned long) port.membase) & 0xFFFFFFFFFF;
++ d->line_b = serial8250_register_port(&port);
++
++ ioc3_enable(is, idd);
++ return 0;
++}
++
++static int ioc3uart_remove(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
++{
++ struct ioc3uart_data *d = (struct ioc3uart_data *)(idd->data[is->id]);
++ serial8250_unregister_port(d->line_a);
++ serial8250_unregister_port(d->line_b);
++ delete_dynamic_irq(d->irq);
++ kfree(d);
++ idd->data[is->id] = NULL;
++ return 0;
++}
++
++static struct ioc3_submodule ioc3uart_submodule = {
++ .name = "uart",
++ .probe = ioc3uart_probe,
++ .remove = ioc3uart_remove,
++ .irq_mask = SIO_IR_SA_INT | SIO_IR_SB_INT,
++ .intr = ioc3uart_intr,
++ .owner = THIS_MODULE,
++};
++
++static int __init ioc3uart_init(void)
++{
++ ioc3_register_submodule(&ioc3uart_submodule);
++ return 0;
++}
++
++static void __exit ioc3uart_exit(void)
++{
++ ioc3_unregister_submodule(&ioc3uart_submodule);
++}
++
++module_init(ioc3uart_init);
++module_exit(ioc3uart_exit);
+diff -urN linux-mips/drivers/serial/serial_core.c new/drivers/serial/serial_core.c
+--- linux-mips/drivers/serial/serial_core.c 2006-01-10 11:21:48.000000000 +0000
++++ new/drivers/serial/serial_core.c 2006-01-16 17:21:41.000000000 +0000
+@@ -1632,9 +1632,10 @@
ret = sprintf(buf, "%d: uart:%s %s%08lX irq:%d",
port->line, uart_type(port),
@@ -1947,17 +1964,18 @@
port->irq);
if (port->type == PORT_UNKNOWN) {
-@@ -1928,6 +1929,9 @@
- case UPIO_MEM32:
- printk("MMIO 0x%lx", port->mapbase);
+@@ -1977,6 +1978,10 @@
+ snprintf(address, sizeof(address),
+ "MMIO 0x%lx", port->mapbase);
break;
+ case UPIO_IOC3:
-+ printk("IOC3 0x%lx", port->mapbase);
++ snprintf(address, sizeof(address), "IOC3 0x%lx",
++ port->mapbase);
+ break;
- }
- printk(" (irq = %d) is a %s\n", port->irq, uart_type(port));
- }
-@@ -2245,6 +2249,7 @@
+ default:
+ strlcpy(address, "*unknown*", sizeof(address));
+ break;
+@@ -2307,6 +2312,7 @@
return (port1->iobase == port2->iobase) &&
(port1->hub6 == port2->hub6);
case UPIO_MEM:
@@ -1965,9 +1983,9 @@
return (port1->membase == port2->membase);
}
return 0;
-diff -urN linux-2.6.12/include/asm-mips/mach-ip27/mangle-port.h linux-2.6.12-ioc3/include/asm-mips/mach-ip27/mangle-port.h
---- linux-2.6.12/include/asm-mips/mach-ip27/mangle-port.h 2004-08-19 16:32:00.000000000 +0200
-+++ linux-2.6.12-ioc3/include/asm-mips/mach-ip27/mangle-port.h 2005-07-10 22:32:11.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip27/mangle-port.h new/include/asm-mips/mach-ip27/mangle-port.h
+--- linux-mips/include/asm-mips/mach-ip27/mangle-port.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/mach-ip27/mangle-port.h 2006-01-16 17:21:41.000000000 +0000
@@ -8,7 +8,7 @@
#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
#define __ASM_MACH_IP27_MANGLE_PORT_H
@@ -1977,9 +1995,9 @@
#define __swizzle_addr_w(port) ((port) ^ 2)
#define __swizzle_addr_l(port) (port)
#define __swizzle_addr_q(port) (port)
-diff -urN linux-2.6.12/include/linux/ioc3.h linux-2.6.12-ioc3/include/linux/ioc3.h
---- linux-2.6.12/include/linux/ioc3.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ioc3/include/linux/ioc3.h 2005-07-09 13:35:08.000000000 +0200
+diff -urN linux-mips/include/linux/ioc3.h new/include/linux/ioc3.h
+--- linux-mips/include/linux/ioc3.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/linux/ioc3.h 2006-01-16 17:21:41.000000000 +0000
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -2068,25 +2086,25 @@
+extern void ioc3_gpio(struct ioc3_driver_data *, unsigned int, unsigned int);
+
+#endif
-diff -urN linux-2.6.12/include/linux/serial.h linux-2.6.12-ioc3/include/linux/serial.h
---- linux-2.6.12/include/linux/serial.h 2005-01-07 15:50:19.000000000 +0100
-+++ linux-2.6.12-ioc3/include/linux/serial.h 2005-07-09 13:35:08.000000000 +0200
-@@ -81,6 +81,7 @@
+diff -urN linux-mips/include/linux/serial.h new/include/linux/serial.h
+--- linux-mips/include/linux/serial.h 2006-01-10 11:30:59.000000000 +0000
++++ new/include/linux/serial.h 2006-01-16 17:21:41.000000000 +0000
+@@ -82,6 +82,7 @@
#define SERIAL_IO_PORT 0
#define SERIAL_IO_HUB6 1
#define SERIAL_IO_MEM 2
-+#define SERIAL_IO_IOC3 4
++#define SERIAL_IO_IOC3 5
struct serial_uart_config {
char *name;
-diff -urN linux-2.6.12/include/linux/serial_core.h linux-2.6.12-ioc3/include/linux/serial_core.h
---- linux-2.6.12/include/linux/serial_core.h 2005-07-08 13:16:59.000000000 +0200
-+++ linux-2.6.12-ioc3/include/linux/serial_core.h 2005-07-09 13:35:08.000000000 +0200
-@@ -208,6 +208,7 @@
- #define UPIO_HUB6 (1)
+diff -urN linux-mips/include/linux/serial_core.h new/include/linux/serial_core.h
+--- linux-mips/include/linux/serial_core.h 2006-01-10 11:22:04.000000000 +0000
++++ new/include/linux/serial_core.h 2006-01-16 17:21:41.000000000 +0000
+@@ -215,6 +215,7 @@
#define UPIO_MEM (2)
#define UPIO_MEM32 (3)
-+#define UPIO_IOC3 (4)
+ #define UPIO_AU (4) /* Au1x00 type IO */
++#define UPIO_IOC3 (5)
unsigned int read_status_mask; /* driver specific */
unsigned int ignore_status_mask; /* driver specific */
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/21_ip30.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/21_ip30.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/21_ip30.dpatch Mon Jan 16 17:33:25 2006
@@ -1,9 +1,8 @@
#! /bin/sh -e
## 21_ip30.dpatch by Stanislaw Skowronek <skylark at linux-mips.org>
##
-## All lines beginning with `## DP:' are a description of the patch.
## DP: Improved ioc3 driver, from
-## DP: ftp://ftp.linux-mips.org/pub/linux/mips/people/skylark/linux-mips-2.6.12-ip30-r25.patch.bz2
+## DP: ftp://ftp.linux-mips.org/pub/linux/mips/people/skylark/linux-mips-2.6.14-ip30-r27.patch.bz2
if [ $# -lt 1 ]; then
echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
@@ -23,10 +22,11 @@
exit 0
-diff -urN linux-2.6.12-ioc3/arch/mips/Kconfig linux-2.6.12-ip30/arch/mips/Kconfig
---- linux-2.6.12-ioc3/arch/mips/Kconfig 2005-07-09 13:35:08.000000000 +0200
-+++ linux-2.6.12-ip30/arch/mips/Kconfig 2005-07-10 15:42:33.000000000 +0200
-@@ -484,6 +484,21 @@
+
+diff -urN linux-mips/arch/mips/Kconfig new/arch/mips/Kconfig
+--- linux-mips/arch/mips/Kconfig 2006-01-10 11:21:15.000000000 +0000
++++ new/arch/mips/Kconfig 2006-01-16 17:28:08.000000000 +0000
+@@ -577,6 +577,21 @@
workstations. To compile a Linux kernel that runs on these, say Y
here.
@@ -38,7 +38,7 @@
+ select DMA_IP30
+ select HW_HAS_PCI
+ select PCI_DOMAINS
-+ select QL_ISP_A64
++ select SYS_HAS_CPU_R10000
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ help
@@ -48,7 +48,7 @@
config SGI_IP32
bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
depends on EXPERIMENTAL
-@@ -671,6 +686,9 @@
+@@ -815,6 +830,9 @@
config DMA_IP27
bool
@@ -57,8 +57,8 @@
+
config DMA_IP32
bool
-
-@@ -847,7 +865,7 @@
+ select DMA_NEED_PCI_MAP_STATE
+@@ -1009,7 +1027,7 @@
config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION
@@ -67,7 +67,7 @@
default "5"
config HAVE_STD_PC_SERIAL_PORT
-@@ -862,12 +880,12 @@
+@@ -1024,12 +1042,12 @@
config ARC_MEMORY
bool
@@ -82,19 +82,27 @@
default y
config ARC64
-@@ -1207,7 +1225,7 @@
+@@ -1576,7 +1594,7 @@
config SMP
bool "Multi-Processing support"
-- depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
-+ depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 || SGI_IP30
+- depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
++ depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || SGI_IP30 || MIPS_MT_SMP
---help---
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
-diff -urN linux-2.6.12-ioc3/arch/mips/Makefile linux-2.6.12-ip30/arch/mips/Makefile
---- linux-2.6.12-ioc3/arch/mips/Makefile 2005-07-08 13:12:04.000000000 +0200
-+++ linux-2.6.12-ip30/arch/mips/Makefile 2005-07-09 13:36:14.000000000 +0200
-@@ -601,6 +601,15 @@
+@@ -1601,6 +1619,7 @@
+ range 2 64
+ depends on SMP
+ default "64" if SGI_IP27
++ default "4" if SGI_IP30
+ default "2"
+ help
+ This allows you to specify the maximum number of CPUs which this
+diff -urN linux-mips/arch/mips/Makefile new/arch/mips/Makefile
+--- linux-mips/arch/mips/Makefile 2006-01-10 11:30:59.000000000 +0000
++++ new/arch/mips/Makefile 2006-01-16 17:28:08.000000000 +0000
+@@ -632,6 +632,15 @@
endif
#
@@ -110,10 +118,10 @@
# SGI-IP32 (O2)
#
# Set the load address to >= 80069000 if you want to leave space for symmon,
-diff -urN linux-2.6.12-ioc3/arch/mips/kernel/setup.c linux-2.6.12-ip30/arch/mips/kernel/setup.c
---- linux-2.6.12-ioc3/arch/mips/kernel/setup.c 2005-07-08 13:12:08.000000000 +0200
-+++ linux-2.6.12-ip30/arch/mips/kernel/setup.c 2005-07-09 13:36:14.000000000 +0200
-@@ -150,7 +150,6 @@
+diff -urN linux-mips/arch/mips/kernel/setup.c new/arch/mips/kernel/setup.c
+--- linux-mips/arch/mips/kernel/setup.c 2006-01-10 11:30:59.000000000 +0000
++++ new/arch/mips/kernel/setup.c 2006-01-16 17:28:08.000000000 +0000
+@@ -152,7 +152,6 @@
printk("Determined physical RAM map:\n");
print_memory_map();
@@ -121,7 +129,7 @@
for (;;) {
/*
* "mem=XXX[kKmM]" defines a memory region from
-@@ -300,7 +299,7 @@
+@@ -302,7 +301,7 @@
* Partially used pages are not usable - thus
* we are rounding upwards.
*/
@@ -130,7 +138,7 @@
#ifndef CONFIG_SGI_IP27
/* Find the highest page frame number we have available. */
-@@ -422,11 +421,11 @@
+@@ -426,11 +425,11 @@
printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
(void *)initrd_start, initrd_size);
@@ -144,7 +152,7 @@
sizeof(long) * 2,
(unsigned long long)PFN_PHYS(max_low_pfn));
initrd_start = initrd_end = 0;
-@@ -434,7 +433,7 @@
+@@ -438,7 +437,7 @@
}
if (initrd_reserve_bootmem)
@@ -153,7 +161,7 @@
}
#endif /* CONFIG_BLK_DEV_INITRD */
}
-@@ -448,10 +447,10 @@
+@@ -452,10 +451,10 @@
* The 64bit code in 32bit object format trick can't represent
* 64bit wide relocations for linker script symbols.
*/
@@ -168,7 +176,7 @@
#else
code_resource.start = virt_to_phys(&_text);
code_resource.end = virt_to_phys(&_etext) - 1;
-@@ -524,6 +523,10 @@
+@@ -530,6 +529,10 @@
/* call board setup routine */
plat_setup();
@@ -179,9 +187,9 @@
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
-diff -urN linux-2.6.12-ioc3/arch/mips/mm/Makefile linux-2.6.12-ip30/arch/mips/mm/Makefile
---- linux-2.6.12-ioc3/arch/mips/mm/Makefile 2005-07-08 13:12:09.000000000 +0200
-+++ linux-2.6.12-ip30/arch/mips/mm/Makefile 2005-07-10 15:37:40.000000000 +0200
+diff -urN linux-mips/arch/mips/mm/Makefile new/arch/mips/mm/Makefile
+--- linux-mips/arch/mips/mm/Makefile 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/mm/Makefile 2006-01-16 17:28:08.000000000 +0000
@@ -39,6 +39,7 @@
obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
endif
@@ -190,9 +198,9 @@
obj-$(CONFIG_DMA_IP32) += dma-ip32.o
EXTRA_AFLAGS := $(CFLAGS)
-diff -urN linux-2.6.12-ioc3/arch/mips/mm/dma-ip30.c linux-2.6.12-ip30/arch/mips/mm/dma-ip30.c
---- linux-2.6.12-ioc3/arch/mips/mm/dma-ip30.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/mm/dma-ip30.c 2005-07-12 11:02:08.000000000 +0200
+diff -urN linux-mips/arch/mips/mm/dma-ip30.c new/arch/mips/mm/dma-ip30.c
+--- linux-mips/arch/mips/mm/dma-ip30.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/mm/dma-ip30.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,279 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -473,9 +481,9 @@
+}
+
+EXPORT_SYMBOL(pci_dac_dma_sync_single_for_device);
-diff -urN linux-2.6.12-ioc3/arch/mips/mm/init.c linux-2.6.12-ip30/arch/mips/mm/init.c
---- linux-2.6.12-ioc3/arch/mips/mm/init.c 2005-03-18 21:40:38.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/mm/init.c 2005-07-11 18:16:03.000000000 +0200
+diff -urN linux-mips/arch/mips/mm/init.c new/arch/mips/mm/init.c
+--- linux-mips/arch/mips/mm/init.c 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/mm/init.c 2006-01-16 17:28:08.000000000 +0000
@@ -160,8 +160,19 @@
zones_size[ZONE_NORMAL] = low - max_dma;
}
@@ -496,14 +504,14 @@
#ifdef CONFIG_HIGHMEM
if (cpu_has_dc_aliases) {
printk(KERN_WARNING "This processor doesn't support highmem.");
-@@ -262,13 +273,22 @@
+@@ -261,13 +272,22 @@
}
- #endif /* !CONFIG_DISCONTIGMEM */
+ #endif /* !CONFIG_NEED_MULTIPLE_NODES */
-+#ifdef CONFIG_MIPS64
++#ifdef CONFIG_64BIT
+unsigned long kernel_physaddr(unsigned long kva)
+{
-+ if((kva & ~0xffffffffUL) == ~0xffffffffUL)
++ if(kva&0xffffffff00000000UL==0xffffffff00000000UL)
+ return CPHYSADDR(kva);
+ return XPHYSADDR(kva);
+}
@@ -512,7 +520,7 @@
#ifdef CONFIG_BLK_DEV_INITRD
void free_initrd_mem(unsigned long start, unsigned long end)
{
- #ifdef CONFIG_MIPS64
+ #ifdef CONFIG_64BIT
/* Switch from KSEG0 to XKPHYS addresses */
- start = (unsigned long)phys_to_virt(CPHYSADDR(start));
- end = (unsigned long)phys_to_virt(CPHYSADDR(end));
@@ -521,29 +529,29 @@
#endif
if (start < end)
printk(KERN_INFO "Freeing initrd memory: %ldk freed\n",
-@@ -294,7 +314,7 @@
+@@ -293,7 +313,7 @@
addr = (unsigned long) &__init_begin;
while (addr < (unsigned long) &__init_end) {
- #ifdef CONFIG_MIPS64
+ #ifdef CONFIG_64BIT
- page = PAGE_OFFSET | CPHYSADDR(addr);
+ page = PAGE_OFFSET | kernel_physaddr(addr);
#else
page = addr;
#endif
-diff -urN linux-2.6.12-ioc3/arch/mips/pci/Makefile linux-2.6.12-ip30/arch/mips/pci/Makefile
---- linux-2.6.12-ioc3/arch/mips/pci/Makefile 2005-07-09 13:35:08.000000000 +0200
-+++ linux-2.6.12-ip30/arch/mips/pci/Makefile 2005-07-09 13:36:14.000000000 +0200
-@@ -43,6 +43,7 @@
+diff -urN linux-mips/arch/mips/pci/Makefile new/arch/mips/pci/Makefile
+--- linux-mips/arch/mips/pci/Makefile 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/pci/Makefile 2006-01-16 17:28:08.000000000 +0000
+@@ -44,6 +44,7 @@
obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
pci-yosemite.o
obj-$(CONFIG_SGI_IP27) += pci-ip27.o
+obj-$(CONFIG_SGI_IP30) += pci-ip30.o
obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
- obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
-diff -urN linux-2.6.12-ioc3/arch/mips/pci/pci-ip30.c linux-2.6.12-ip30/arch/mips/pci/pci-ip30.c
---- linux-2.6.12-ioc3/arch/mips/pci/pci-ip30.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/pci/pci-ip30.c 2005-07-13 08:19:23.000000000 +0200
+ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
+diff -urN linux-mips/arch/mips/pci/pci-ip30.c new/arch/mips/pci/pci-ip30.c
+--- linux-mips/arch/mips/pci/pci-ip30.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/pci/pci-ip30.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,484 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -1029,9 +1037,9 @@
+ pci_disable_swapping_dma);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_RAD1,
+ pci_disable_swapping_dma);
-diff -urN linux-2.6.12-ioc3/arch/mips/pci/pci.c linux-2.6.12-ip30/arch/mips/pci/pci.c
---- linux-2.6.12-ioc3/arch/mips/pci/pci.c 2004-12-16 13:55:01.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/pci/pci.c 2005-07-10 13:32:04.000000000 +0200
+diff -urN linux-mips/arch/mips/pci/pci.c new/arch/mips/pci/pci.c
+--- linux-mips/arch/mips/pci/pci.c 2006-01-10 11:21:16.000000000 +0000
++++ new/arch/mips/pci/pci.c 2006-01-16 17:28:08.000000000 +0000
@@ -119,6 +119,10 @@
/* Scan all of the recorded PCI controllers. */
for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
@@ -1043,18 +1051,18 @@
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
goto out;
if (request_resource(&ioport_resource, hose->io_resource) < 0)
-@@ -131,6 +135,10 @@
- hose->bus = bus;
+@@ -135,6 +139,10 @@
hose->need_domain_info = need_domain_info;
- next_busno = bus->subordinate + 1;
-+
-+ if (hose->post_scan)
-+ hose->post_scan(hose, bus);
-+
- /* Don't allow 8-bit bus number overflow inside the hose -
- reserve some space for bridges. */
- if (next_busno > 224) {
-@@ -161,6 +169,7 @@
+ if (bus) {
+ next_busno = bus->subordinate + 1;
++
++ if (hose->post_scan)
++ hose->post_scan(hose, bus);
++
+ /* Don't allow 8-bit bus number overflow inside the hose -
+ reserve some space for bridges. */
+ if (next_busno > 224) {
+@@ -166,6 +174,7 @@
u16 cmd, old_cmd;
int idx;
struct resource *r;
@@ -1062,7 +1070,7 @@
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
-@@ -169,6 +178,10 @@
+@@ -174,6 +183,10 @@
if (!(mask & (1<<idx)))
continue;
@@ -1073,9 +1081,9 @@
r = &dev->resource[idx];
if (!r->start && r->end) {
printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/Makefile linux-2.6.12-ip30/arch/mips/sgi-ip30/Makefile
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/Makefile 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/Makefile new/arch/mips/sgi-ip30/Makefile
+--- linux-mips/arch/mips/sgi-ip30/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/Makefile 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,8 @@
+#
+# Makefile for the IP30 specific kernel interface routines under Linux.
@@ -1085,9 +1093,9 @@
+obj-$(CONFIG_SMP) += ip30-smp.o ip30-smp-glue.o
+
+EXTRA_AFLAGS := $(CFLAGS)
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-err.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-err.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-err.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-err.c 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-err.c new/arch/mips/sgi-ip30/ip30-err.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-err.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-err.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,37 @@
+/*
+ * ip30-err.c: HEART error handling for IP30 architecture.
@@ -1126,9 +1134,9 @@
+ printk(" interrupt #%d\n",i);
+ irq_exit();
+}
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-irq-glue.S linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-irq-glue.S
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-irq-glue.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-irq-glue.S 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-irq-glue.S new/arch/mips/sgi-ip30/ip30-irq-glue.S
+--- linux-mips/arch/mips/sgi-ip30/ip30-irq-glue.S 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-irq-glue.S 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2004,5 Stanislaw Skowronek
@@ -1184,9 +1192,9 @@
+1:
+ j ret_from_irq
+ END(ip30_irq)
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-irq.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-irq.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-irq.c 2005-07-13 10:00:38.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-irq.c new/arch/mips/sgi-ip30/ip30-irq.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-irq.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-irq.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,307 @@
+/*
+ * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
@@ -1495,9 +1503,9 @@
+ *HEART_IMR(pcpu)=0x0000000000000000;
+ change_c0_status(ST0_IM, STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6);
+}
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-power.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-power.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-power.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-power.c 2005-07-13 10:00:30.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-power.c new/arch/mips/sgi-ip30/ip30-power.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-power.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-power.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,124 @@
+/*
+ * ip30-power.c: Software powerdown and reset handling for IP30 architecture.
@@ -1623,9 +1631,9 @@
+}
+
+subsys_initcall(reboot_setup);
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-setup.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-setup.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-setup.c 2005-07-11 18:07:34.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-setup.c new/arch/mips/sgi-ip30/ip30-setup.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-setup.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -1701,9 +1709,9 @@
+#endif
+ return 0;
+}
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-smp-glue.S linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-smp-glue.S
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-smp-glue.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-smp-glue.S 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-smp-glue.S new/arch/mips/sgi-ip30/ip30-smp-glue.S
+--- linux-mips/arch/mips/sgi-ip30/ip30-smp-glue.S 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-smp-glue.S 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2005 Stanislaw Skowronek
@@ -1722,9 +1730,9 @@
+ move gp, a0
+ j smp_bootstrap
+ END(ip30_smp_bootstrap)
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-smp.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-smp.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-smp.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-smp.c 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-smp.c new/arch/mips/sgi-ip30/ip30-smp.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-smp.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-smp.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,142 @@
+/*
+ * ip30-smp.c: SMP on IP30 architecture.
@@ -1868,9 +1876,9 @@
+ if(request_irq(IRQ_IPI_P(cpu),ip30_mailbox_irq,0,"SMP IPI",NULL))
+ printk("IP30: IPI allocation for CPU%d failed.\n",cpu);
+}
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-timer.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-timer.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-timer.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-timer.c 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-timer.c new/arch/mips/sgi-ip30/ip30-timer.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-timer.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-timer.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,47 @@
+/*
+ * ip30-timer.c: Timer handling for IP30 architecture.
@@ -1919,9 +1927,9 @@
+{
+ setup_irq(TIMER_IRQ, irq);
+}
-diff -urN linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-xtalk.c linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-xtalk.c
---- linux-2.6.12-ioc3/arch/mips/sgi-ip30/ip30-xtalk.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/arch/mips/sgi-ip30/ip30-xtalk.c 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/arch/mips/sgi-ip30/ip30-xtalk.c new/arch/mips/sgi-ip30/ip30-xtalk.c
+--- linux-mips/arch/mips/sgi-ip30/ip30-xtalk.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/sgi-ip30/ip30-xtalk.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,174 @@
+/*
+ * ip30-xtalk.c
@@ -2097,12 +2105,12 @@
+ while((i=ip30_xtalk_find(PCIBR_XTALK_MFGR,PCIBR_XTALK_PART,i))!=-1)
+ bridge_probe(0, i, IP30_WIDGET_HEART);
+}
-diff -urN linux-2.6.12-ioc3/drivers/char/Kconfig linux-2.6.12-ip30/drivers/char/Kconfig
---- linux-2.6.12-ioc3/drivers/char/Kconfig 2005-07-09 13:35:08.000000000 +0200
-+++ linux-2.6.12-ip30/drivers/char/Kconfig 2005-07-09 13:36:14.000000000 +0200
-@@ -397,6 +397,14 @@
- Enable this if you have a SGI Origin or Octane machine. This module
- provides serial port support for IOC3 chips on those systems.
+diff -urN linux-mips/drivers/char/Kconfig new/drivers/char/Kconfig
+--- linux-mips/drivers/char/Kconfig 2006-01-10 11:21:25.000000000 +0000
++++ new/drivers/char/Kconfig 2006-01-16 17:28:08.000000000 +0000
+@@ -390,6 +390,14 @@
+ Documentation on the Zilog 85C350 serial communications controller
+ is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
+config SGI_IP30_LEDS
+ bool "SGI Octane LED support"
@@ -2115,7 +2123,7 @@
config QTRONIX_KEYBOARD
bool "Enable Qtronix 990P Keyboard Support"
depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
-@@ -789,6 +797,17 @@
+@@ -782,6 +790,17 @@
via the file /proc/rtc and its behaviour is set by various ioctls on
/dev/rtc.
@@ -2132,22 +2140,22 @@
+
config GEN_RTC
tristate "Generic /dev/rtc emulation"
- depends on RTC!=y && !IA64 && !ARM
-diff -urN linux-2.6.12-ioc3/drivers/char/Makefile linux-2.6.12-ip30/drivers/char/Makefile
---- linux-2.6.12-ioc3/drivers/char/Makefile 2005-07-09 13:35:08.000000000 +0200
-+++ linux-2.6.12-ip30/drivers/char/Makefile 2005-07-09 13:36:14.000000000 +0200
+ depends on RTC!=y && !IA64 && !ARM && !M32R && !SPARC
+diff -urN linux-mips/drivers/char/Makefile new/drivers/char/Makefile
+--- linux-mips/drivers/char/Makefile 2006-01-10 11:21:25.000000000 +0000
++++ new/drivers/char/Makefile 2006-01-16 17:28:08.000000000 +0000
@@ -64,6 +64,8 @@
obj-$(CONFIG_EFI_RTC) += efirtc.o
obj-$(CONFIG_SGI_DS1286) += ds1286.o
obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
+obj-$(CONFIG_SGI_IP30_LEDS) += ip30-leds.o
+obj-$(CONFIG_SGI_IP30_RTC) += ip30-rtc.o
- obj-$(CONFIG_SGI_IOC3_UART) += ioc3uart.o
obj-$(CONFIG_DS1302) += ds1302.o
obj-$(CONFIG_S3C2410_RTC) += s3c2410-rtc.o
-diff -urN linux-2.6.12-ioc3/drivers/char/ip30-leds.c linux-2.6.12-ip30/drivers/char/ip30-leds.c
---- linux-2.6.12-ioc3/drivers/char/ip30-leds.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/drivers/char/ip30-leds.c 2005-07-13 08:16:54.000000000 +0200
+ obj-$(CONFIG_RTC_VR41XX) += vr41xx_rtc.o
+diff -urN linux-mips/drivers/char/ip30-leds.c new/drivers/char/ip30-leds.c
+--- linux-mips/drivers/char/ip30-leds.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/char/ip30-leds.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,270 @@
+/*
+ * Driver for the LEDs in SGI Octane.
@@ -2419,9 +2427,9 @@
+
+module_init(leds_init);
+module_exit(leds_exit);
-diff -urN linux-2.6.12-ioc3/drivers/char/ip30-rtc.c linux-2.6.12-ip30/drivers/char/ip30-rtc.c
---- linux-2.6.12-ioc3/drivers/char/ip30-rtc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/drivers/char/ip30-rtc.c 2005-07-13 09:34:21.000000000 +0200
+diff -urN linux-mips/drivers/char/ip30-rtc.c new/drivers/char/ip30-rtc.c
+--- linux-mips/drivers/char/ip30-rtc.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/char/ip30-rtc.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,395 @@
+/*
+ * Driver for the Maxim/Dallas DS1687 real time clock in SGI Octane.
@@ -2818,10 +2826,23 @@
+
+module_init(rtc_init);
+module_exit(rtc_exit);
-diff -urN linux-2.6.12-ioc3/drivers/video/Kconfig linux-2.6.12-ip30/drivers/video/Kconfig
---- linux-2.6.12-ioc3/drivers/video/Kconfig 2005-07-08 13:15:43.000000000 +0200
-+++ linux-2.6.12-ip30/drivers/video/Kconfig 2005-07-09 13:36:14.000000000 +0200
-@@ -552,6 +552,20 @@
+diff -urN linux-mips/drivers/usb/host/pci-quirks.c new/drivers/usb/host/pci-quirks.c
+--- linux-mips/drivers/usb/host/pci-quirks.c 2006-01-10 11:21:48.000000000 +0000
++++ new/drivers/usb/host/pci-quirks.c 2006-01-16 17:28:08.000000000 +0000
+@@ -152,6 +152,9 @@
+ unsigned long base = 0;
+ int i;
+
++ if (!pci_enable_device(pdev))
++ return;
++
+ if (!pio_enabled(pdev))
+ return;
+
+diff -urN linux-mips/drivers/video/Kconfig new/drivers/video/Kconfig
+--- linux-mips/drivers/video/Kconfig 2006-01-10 11:21:49.000000000 +0000
++++ new/drivers/video/Kconfig 2006-01-16 17:28:08.000000000 +0000
+@@ -525,6 +525,20 @@
This is the amount of memory reserved for the framebuffer,
which can be any value between 1MB and 8MB.
@@ -2842,22 +2863,22 @@
config BUS_I2C
bool
depends on (FB = y) && VISWS
-diff -urN linux-2.6.12-ioc3/drivers/video/Makefile linux-2.6.12-ip30/drivers/video/Makefile
---- linux-2.6.12-ioc3/drivers/video/Makefile 2005-07-08 13:15:43.000000000 +0200
-+++ linux-2.6.12-ip30/drivers/video/Makefile 2005-07-09 13:36:14.000000000 +0200
-@@ -92,6 +92,8 @@
- obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
+diff -urN linux-mips/drivers/video/Makefile new/drivers/video/Makefile
+--- linux-mips/drivers/video/Makefile 2006-01-10 11:30:59.000000000 +0000
++++ new/drivers/video/Makefile 2006-01-16 17:28:08.000000000 +0000
+@@ -96,6 +96,8 @@
obj-$(CONFIG_FB_IMX) += imxfb.o
obj-$(CONFIG_FB_SMIVGX) += smivgxfb.o
+ obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
+obj-$(CONFIG_FB_IMPACTSR) += impactsr.o
+obj-$(CONFIG_FB_ODYSSEY) += odyssey.o
# Platform or fallback drivers go here
obj-$(CONFIG_FB_VESA) += vesafb.o
-diff -urN linux-2.6.12-ioc3/drivers/video/impactsr.c linux-2.6.12-ip30/drivers/video/impactsr.c
---- linux-2.6.12-ioc3/drivers/video/impactsr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/drivers/video/impactsr.c 2005-07-09 13:36:14.000000000 +0200
-@@ -0,0 +1,919 @@
+diff -urN linux-mips/drivers/video/impactsr.c new/drivers/video/impactsr.c
+--- linux-mips/drivers/video/impactsr.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/video/impactsr.c 2006-01-16 17:28:08.000000000 +0000
+@@ -0,0 +1,911 @@
+/*
+ * linux/drivers/video/impactsr.c -- SGI Octane MardiGras (IMPACTSR) graphics
+ *
@@ -2905,6 +2926,7 @@
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/font.h>
++#include <linux/platform_device.h>
+
+#include <asm/mach-ip30/xtalk.h>
+#include <video/impactsr.h>
@@ -2929,7 +2951,6 @@
+ unsigned int num_ge, num_rss;
+ /* locks to prevent simultaneous user and kernel access */
+ int open_flag;
-+ int mmap_flag;
+ spinlock_t lock;
+};
+
@@ -3135,6 +3156,8 @@
+ SetPageReserved(virt_to_page(PAR.kpool_virt[pool][i]));
+ PAR.kpool_phys[pool][i]=dma_handle;
+ PAR.pool_txtbl[pool][i]=PAR.kpool_phys[pool][i]>>PAGE_SHIFT;
++ if(!PAR.kpool_virt[pool][i])
++ printk(KERN_ERR "impactsr: Page allocation failed!\n");
+ }
+ impactsr_writetxtbl(p,pool);
+ PAR.kpool_size[pool]=pages*PAGE_SIZE;
@@ -3496,7 +3519,6 @@
+ if (remap_pfn_range(vma, vma->vm_start, offset>>PAGE_SHIFT, size, vma->vm_page_prot))
+ return -EAGAIN;
+ vma->vm_file = file;
-+ PAR.mmap_flag = 1;
+ return 0;
+ case 0x1000000:
+ case 0x2000000:
@@ -3507,7 +3529,7 @@
+ case 0xb000000:
+ if(size>0x1000000)
+ return EINVAL;
-+ pool=offset>>24;
++ pool=(offset>>24)&3;
+ impactsr_resizekpool(&info,pool,size,offset&0x8000000);
+ n=(size+PAGE_SIZE-1)>>PAGE_SHIFT;
+ for(i=0;i<n;i++) {
@@ -3516,7 +3538,6 @@
+ start += PAGE_SIZE;
+ }
+ vma->vm_file = file;
-+ PAR.mmap_flag = 1;
+ return 0;
+ default:
+ return -EINVAL;
@@ -3539,15 +3560,8 @@
+{
+ unsigned long flags;
+ spin_lock_irqsave(&PAR.lock,flags);
-+ if (user && PAR.open_flag) {
++ if (user && PAR.open_flag)
+ PAR.open_flag--;
-+ if (PAR.open_flag == 0) {
-+ impactsr_resizekpool(&info,1,8192,0);
-+ impactsr_resizekpool(&info,2,8192,0);
-+ impactsr_resizekpool(&info,3,8192,0);
-+ PAR.mmap_flag = 0;
-+ }
-+ }
+ spin_unlock_irqrestore(&PAR.lock,flags);
+ return 0;
+}
@@ -3701,7 +3715,6 @@
+ return -ENODEV;
+
+ current_par.open_flag = 0;
-+ current_par.mmap_flag = 0;
+ current_par.lock = SPIN_LOCK_UNLOCKED;
+
+ current_par.mmio_base = ip30_xtalk_swin(xwid);
@@ -3777,10 +3790,10 @@
+module_exit(impactsr_exit);
+
+MODULE_LICENSE("GPL");
-diff -urN linux-2.6.12-ioc3/drivers/video/logo/Kconfig linux-2.6.12-ip30/drivers/video/logo/Kconfig
---- linux-2.6.12-ioc3/drivers/video/logo/Kconfig 2005-07-08 13:15:56.000000000 +0200
-+++ linux-2.6.12-ip30/drivers/video/logo/Kconfig 2005-07-09 13:36:14.000000000 +0200
-@@ -40,7 +40,7 @@
+diff -urN linux-mips/drivers/video/logo/Kconfig new/drivers/video/logo/Kconfig
+--- linux-mips/drivers/video/logo/Kconfig 2006-01-10 11:21:50.000000000 +0000
++++ new/drivers/video/logo/Kconfig 2006-01-16 17:28:08.000000000 +0000
+@@ -42,7 +42,7 @@
config LOGO_SGI_CLUT224
bool "224-color SGI Linux logo"
@@ -3789,10 +3802,10 @@
default y
config LOGO_SUN_CLUT224
-diff -urN linux-2.6.12-ioc3/drivers/video/odyssey.c linux-2.6.12-ip30/drivers/video/odyssey.c
---- linux-2.6.12-ioc3/drivers/video/odyssey.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/drivers/video/odyssey.c 2005-07-09 13:36:14.000000000 +0200
-@@ -0,0 +1,966 @@
+diff -urN linux-mips/drivers/video/odyssey.c new/drivers/video/odyssey.c
+--- linux-mips/drivers/video/odyssey.c 1970-01-01 01:00:00.000000000 +0100
++++ new/drivers/video/odyssey.c 2006-01-16 17:28:08.000000000 +0000
+@@ -0,0 +1,967 @@
+/*
+ * linux/drivers/video/odyssey.c -- SGI Octane Odyssey graphics
+ *
@@ -3827,6 +3840,7 @@
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/font.h>
++#include <linux/platform_device.h>
+
+#include <asm/mach-ip30/xtalk.h>
+#include <video/odyssey.h>
@@ -4759,27 +4773,27 @@
+module_exit(odyssey_exit);
+
+MODULE_LICENSE("GPL");
-diff -urN linux-2.6.12-ioc3/include/asm-mips/addrspace.h linux-2.6.12-ip30/include/asm-mips/addrspace.h
---- linux-2.6.12-ioc3/include/asm-mips/addrspace.h 2005-07-08 13:16:45.000000000 +0200
-+++ linux-2.6.12-ip30/include/asm-mips/addrspace.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/asm-mips/addrspace.h new/include/asm-mips/addrspace.h
+--- linux-mips/include/asm-mips/addrspace.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/addrspace.h 2006-01-16 17:28:08.000000000 +0000
@@ -51,6 +51,14 @@
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_LLCONST_(0x000000ffffffffff))
+#ifndef __ASSEMBLY__
-+#ifdef CONFIG_MIPS64
++#ifdef CONFIG_64BIT
+unsigned long kernel_physaddr(unsigned long);
+#else
+#define kernel_physaddr CPHYSADDR
+#endif
+#endif
+
- #ifdef CONFIG_MIPS64
+ #ifdef CONFIG_64BIT
/*
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/addrs.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/addrs.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/addrs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/addrs.h 2005-07-10 14:51:01.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/addrs.h new/include/asm-mips/mach-ip30/addrs.h
+--- linux-mips/include/asm-mips/mach-ip30/addrs.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/addrs.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -4814,10 +4828,10 @@
+#define BWIN_SIZE 0x1000000000L
+
+#endif /* _ASM_SGI_IP30_ADDRS_H */
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/cpu-feature-overrides.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/cpu-feature-overrides.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/cpu-feature-overrides.h 2005-07-09 13:36:14.000000000 +0200
-@@ -0,0 +1,28 @@
+diff -urN linux-mips/include/asm-mips/mach-ip30/cpu-feature-overrides.h new/include/asm-mips/mach-ip30/cpu-feature-overrides.h
+--- linux-mips/include/asm-mips/mach-ip30/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/cpu-feature-overrides.h 2006-01-16 17:28:08.000000000 +0000
+@@ -0,0 +1,31 @@
+#ifndef __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
+
@@ -4839,6 +4853,9 @@
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits 1
+
++#define cpu_has_4kex 1
++#define cpu_has_4k_cache 1
++
+#define cpu_has_subset_pcaches 1
+
+#define cpu_dcache_line_size() 32
@@ -4846,9 +4863,9 @@
+#define cpu_scache_line_size() 128
+
+#endif
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/heart.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/heart.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/heart.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/heart.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/heart.h new/include/asm-mips/mach-ip30/heart.h
+--- linux-mips/include/asm-mips/mach-ip30/heart.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/heart.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2004,5 Stanislaw Skowronek
@@ -5063,9 +5080,9 @@
+#define HC_COR_MEM_ERR ((unsigned long) 0x1 << 0)
+
+#endif /* _HEART_H */
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/mangle-port.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/mangle-port.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/mangle-port.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/mangle-port.h 2005-07-10 22:18:15.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/mangle-port.h new/include/asm-mips/mach-ip30/mangle-port.h
+--- linux-mips/include/asm-mips/mach-ip30/mangle-port.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/mangle-port.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
@@ -5083,9 +5100,9 @@
+#define __swizzle_addr_q(port) (port)
+
+#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/pcibr.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/pcibr.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/pcibr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/pcibr.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/pcibr.h new/include/asm-mips/mach-ip30/pcibr.h
+--- linux-mips/include/asm-mips/mach-ip30/pcibr.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/pcibr.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,24 @@
+/*
+ * Definitions for the built-in PCI bridge
@@ -5111,9 +5128,9 @@
+extern unsigned int ip30_irq_in_bridge[64];
+
+#endif
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/racermp.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/racermp.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/racermp.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/racermp.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/racermp.h new/include/asm-mips/mach-ip30/racermp.h
+--- linux-mips/include/asm-mips/mach-ip30/racermp.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/racermp.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2005 Stanislaw Skowronek
@@ -5143,9 +5160,9 @@
+#define MP_IDLEFLAG(x) (*(volatile unsigned int *)(MPCONF(x)+0x58))
+
+#endif
-diff -urN linux-2.6.12-ioc3/include/asm-mips/mach-ip30/xtalk.h linux-2.6.12-ip30/include/asm-mips/mach-ip30/xtalk.h
---- linux-2.6.12-ioc3/include/asm-mips/mach-ip30/xtalk.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/mach-ip30/xtalk.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/asm-mips/mach-ip30/xtalk.h new/include/asm-mips/mach-ip30/xtalk.h
+--- linux-mips/include/asm-mips/mach-ip30/xtalk.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/asm-mips/mach-ip30/xtalk.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2004,5 Stanislaw Skowronek
@@ -5160,9 +5177,9 @@
+int ip30_xtalk_find(unsigned mfgr, unsigned part, int last);
+
+#endif /* _XTALK_H */
-diff -urN linux-2.6.12-ioc3/include/asm-mips/pci/bridge.h linux-2.6.12-ip30/include/asm-mips/pci/bridge.h
---- linux-2.6.12-ioc3/include/asm-mips/pci/bridge.h 2004-08-30 00:34:25.000000000 +0200
-+++ linux-2.6.12-ip30/include/asm-mips/pci/bridge.h 2005-07-10 15:33:12.000000000 +0200
+diff -urN linux-mips/include/asm-mips/pci/bridge.h new/include/asm-mips/pci/bridge.h
+--- linux-mips/include/asm-mips/pci/bridge.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/pci/bridge.h 2006-01-16 17:28:08.000000000 +0000
@@ -840,6 +840,17 @@
unsigned int irq_cpu;
dma64_addr_t baddr;
@@ -5181,9 +5198,9 @@
};
#define BRIDGE_CONTROLLER(bus) \
-diff -urN linux-2.6.12-ioc3/include/asm-mips/pci.h linux-2.6.12-ip30/include/asm-mips/pci.h
---- linux-2.6.12-ioc3/include/asm-mips/pci.h 2005-03-18 21:40:41.000000000 +0100
-+++ linux-2.6.12-ip30/include/asm-mips/pci.h 2005-07-10 13:00:19.000000000 +0200
+diff -urN linux-mips/include/asm-mips/pci.h new/include/asm-mips/pci.h
+--- linux-mips/include/asm-mips/pci.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/pci.h 2006-01-16 17:28:08.000000000 +0000
@@ -39,6 +39,13 @@
and XFree86. Eventually will be removed. */
unsigned int need_domain_info;
@@ -5196,12 +5213,12 @@
+ int (*pre_enable)(struct pci_controller *, struct pci_dev *, int);
+
int iommu;
- };
-diff -urN linux-2.6.12-ioc3/include/linux/fb.h linux-2.6.12-ip30/include/linux/fb.h
---- linux-2.6.12-ioc3/include/linux/fb.h 2005-07-08 13:16:56.000000000 +0200
-+++ linux-2.6.12-ip30/include/linux/fb.h 2005-07-09 13:36:14.000000000 +0200
-@@ -116,6 +116,8 @@
+ /* Optional access methods for reading/writing the bus number
+diff -urN linux-mips/include/linux/fb.h new/include/linux/fb.h
+--- linux-mips/include/linux/fb.h 2006-01-10 11:22:03.000000000 +0000
++++ new/include/linux/fb.h 2006-01-16 17:28:08.000000000 +0000
+@@ -118,6 +118,8 @@
#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
@@ -5210,9 +5227,9 @@
#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
-diff -urN linux-2.6.12-ioc3/include/linux/leds.h linux-2.6.12-ip30/include/linux/leds.h
---- linux-2.6.12-ioc3/include/linux/leds.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/linux/leds.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/linux/leds.h new/include/linux/leds.h
+--- linux-mips/include/linux/leds.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/linux/leds.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,29 @@
+#ifndef LEDS_H
+#define LEDS_H
@@ -5243,9 +5260,9 @@
+ */
+
+#endif
-diff -urN linux-2.6.12-ioc3/include/linux/miscdevice.h linux-2.6.12-ip30/include/linux/miscdevice.h
---- linux-2.6.12-ioc3/include/linux/miscdevice.h 2005-01-13 15:06:53.000000000 +0100
-+++ linux-2.6.12-ip30/include/linux/miscdevice.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/linux/miscdevice.h new/include/linux/miscdevice.h
+--- linux-mips/include/linux/miscdevice.h 2006-01-10 11:22:03.000000000 +0000
++++ new/include/linux/miscdevice.h 2006-01-16 17:28:08.000000000 +0000
@@ -12,6 +12,7 @@
#define APOLLO_MOUSE_MINOR 7
#define PC110PAD_MINOR 9
@@ -5254,10 +5271,10 @@
#define WATCHDOG_MINOR 130 /* Watchdog timer */
#define TEMP_MINOR 131 /* Temperature Sensor */
#define RTC_MINOR 135
-diff -urN linux-2.6.12-ioc3/include/linux/pci_ids.h linux-2.6.12-ip30/include/linux/pci_ids.h
---- linux-2.6.12-ioc3/include/linux/pci_ids.h 2005-07-08 13:16:58.000000000 +0200
-+++ linux-2.6.12-ip30/include/linux/pci_ids.h 2005-07-09 13:36:14.000000000 +0200
-@@ -985,6 +985,7 @@
+diff -urN linux-mips/include/linux/pci_ids.h new/include/linux/pci_ids.h
+--- linux-mips/include/linux/pci_ids.h 2006-01-10 11:22:04.000000000 +0000
++++ new/include/linux/pci_ids.h 2006-01-16 17:28:08.000000000 +0000
+@@ -889,6 +889,7 @@
#define PCI_VENDOR_ID_SGI 0x10a9
#define PCI_DEVICE_ID_SGI_IOC3 0x0003
@@ -5265,9 +5282,9 @@
#define PCI_DEVICE_ID_SGI_IOC4 0x100a
#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002
-diff -urN linux-2.6.12-ioc3/include/sound/rad1.h linux-2.6.12-ip30/include/sound/rad1.h
---- linux-2.6.12-ioc3/include/sound/rad1.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/sound/rad1.h 2005-07-25 07:10:34.000000000 +0200
+diff -urN linux-mips/include/sound/rad1.h new/include/sound/rad1.h
+--- linux-mips/include/sound/rad1.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/sound/rad1.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,111 @@
+#ifndef _RAD1_H
+#define _RAD1_H
@@ -5380,9 +5397,9 @@
+};
+
+#endif
-diff -urN linux-2.6.12-ioc3/include/video/impactsr.h linux-2.6.12-ip30/include/video/impactsr.h
---- linux-2.6.12-ioc3/include/video/impactsr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/video/impactsr.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/video/impactsr.h new/include/video/impactsr.h
+--- linux-mips/include/video/impactsr.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/video/impactsr.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,138 @@
+/*
+ * linux/drivers/video/impactsr.h -- SGI Octane MardiGras (IMPACTSR) graphics
@@ -5522,9 +5539,9 @@
+#define IMPACTSR_BLEND_ALPHA 0x0704c900
+
+#endif /* IMPACTSR_H */
-diff -urN linux-2.6.12-ioc3/include/video/odyssey.h linux-2.6.12-ip30/include/video/odyssey.h
---- linux-2.6.12-ioc3/include/video/odyssey.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/include/video/odyssey.h 2005-07-09 13:36:14.000000000 +0200
+diff -urN linux-mips/include/video/odyssey.h new/include/video/odyssey.h
+--- linux-mips/include/video/odyssey.h 1970-01-01 01:00:00.000000000 +0100
++++ new/include/video/odyssey.h 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * linux/drivers/video/odyssey.h -- SGI Octane Odyssey graphics
@@ -5578,9 +5595,9 @@
+#define ODY_LO_SET 15
+
+#endif /* ODYSSEY_H */
-diff -urN linux-2.6.12-ioc3/sound/core/oss/linear.c linux-2.6.12-ip30/sound/core/oss/linear.c
---- linux-2.6.12-ioc3/sound/core/oss/linear.c 2002-11-01 23:08:37.000000000 +0100
-+++ linux-2.6.12-ip30/sound/core/oss/linear.c 2005-07-24 19:46:55.000000000 +0200
+diff -urN linux-mips/sound/core/oss/linear.c new/sound/core/oss/linear.c
+--- linux-mips/sound/core/oss/linear.c 2006-01-10 11:22:06.000000000 +0000
++++ new/sound/core/oss/linear.c 2006-01-16 17:28:08.000000000 +0000
@@ -26,6 +26,10 @@
#include <sound/pcm.h>
#include "pcm_plugin.h"
@@ -5592,9 +5609,9 @@
/*
* Basic linear conversion plugin
*/
-diff -urN linux-2.6.12-ioc3/sound/core/oss/mulaw.c linux-2.6.12-ip30/sound/core/oss/mulaw.c
---- linux-2.6.12-ioc3/sound/core/oss/mulaw.c 2005-01-13 15:07:10.000000000 +0100
-+++ linux-2.6.12-ip30/sound/core/oss/mulaw.c 2005-07-24 19:47:08.000000000 +0200
+diff -urN linux-mips/sound/core/oss/mulaw.c new/sound/core/oss/mulaw.c
+--- linux-mips/sound/core/oss/mulaw.c 2006-01-10 11:22:06.000000000 +0000
++++ new/sound/core/oss/mulaw.c 2006-01-16 17:28:08.000000000 +0000
@@ -27,6 +27,10 @@
#include <sound/pcm.h>
#include "pcm_plugin.h"
@@ -5606,9 +5623,9 @@
#define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
#define QUANT_MASK (0xf) /* Quantization field mask. */
#define NSEGS (8) /* Number of u-law segments. */
-diff -urN linux-2.6.12-ioc3/sound/core/oss/plugin_ops.h linux-2.6.12-ip30/sound/core/oss/plugin_ops.h
---- linux-2.6.12-ioc3/sound/core/oss/plugin_ops.h 2003-08-15 17:14:41.000000000 +0200
-+++ linux-2.6.12-ip30/sound/core/oss/plugin_ops.h 2005-07-25 08:48:00.000000000 +0200
+diff -urN linux-mips/sound/core/oss/plugin_ops.h new/sound/core/oss/plugin_ops.h
+--- linux-mips/sound/core/oss/plugin_ops.h 2006-01-10 11:22:06.000000000 +0000
++++ new/sound/core/oss/plugin_ops.h 2006-01-16 17:28:08.000000000 +0000
@@ -19,6 +19,20 @@
*
*/
@@ -5796,9 +5813,9 @@
put_u24s: as_u24(dst) = swab32(sample ^ 0x80); goto PUT_END;
put_s32h: as_s32(dst) = sample; goto PUT_END;
put_u32h: as_u32(dst) = sample ^ 0x80000000; goto PUT_END;
-diff -urN linux-2.6.12-ioc3/sound/core/oss/rate.c linux-2.6.12-ip30/sound/core/oss/rate.c
---- linux-2.6.12-ioc3/sound/core/oss/rate.c 2005-01-13 15:07:10.000000000 +0100
-+++ linux-2.6.12-ip30/sound/core/oss/rate.c 2005-07-24 19:47:17.000000000 +0200
+diff -urN linux-mips/sound/core/oss/rate.c new/sound/core/oss/rate.c
+--- linux-mips/sound/core/oss/rate.c 2006-01-10 11:22:06.000000000 +0000
++++ new/sound/core/oss/rate.c 2006-01-16 17:28:08.000000000 +0000
@@ -25,6 +25,10 @@
#include <sound/pcm.h>
#include "pcm_plugin.h"
@@ -5810,9 +5827,9 @@
#define SHIFT 11
#define BITS (1<<SHIFT)
#define R_MASK (BITS-1)
-diff -urN linux-2.6.12-ioc3/sound/core/oss/route.c linux-2.6.12-ip30/sound/core/oss/route.c
---- linux-2.6.12-ioc3/sound/core/oss/route.c 2005-01-13 15:07:10.000000000 +0100
-+++ linux-2.6.12-ip30/sound/core/oss/route.c 2005-07-24 19:47:22.000000000 +0200
+diff -urN linux-mips/sound/core/oss/route.c new/sound/core/oss/route.c
+--- linux-mips/sound/core/oss/route.c 2006-01-10 11:22:06.000000000 +0000
++++ new/sound/core/oss/route.c 2006-01-16 17:28:08.000000000 +0000
@@ -26,6 +26,10 @@
#include <sound/pcm.h>
#include "pcm_plugin.h"
@@ -5824,10 +5841,10 @@
/* The best possible hack to support missing optimization in gcc 2.7.2.3 */
#if ROUTE_PLUGIN_RESOLUTION & (ROUTE_PLUGIN_RESOLUTION - 1) != 0
#define div(a) a /= ROUTE_PLUGIN_RESOLUTION
-diff -urN linux-2.6.12-ioc3/sound/pci/Kconfig linux-2.6.12-ip30/sound/pci/Kconfig
---- linux-2.6.12-ioc3/sound/pci/Kconfig 2005-03-18 21:40:42.000000000 +0100
-+++ linux-2.6.12-ip30/sound/pci/Kconfig 2005-07-09 13:36:14.000000000 +0200
-@@ -525,4 +525,10 @@
+diff -urN linux-mips/sound/pci/Kconfig new/sound/pci/Kconfig
+--- linux-mips/sound/pci/Kconfig 2006-01-10 11:22:09.000000000 +0000
++++ new/sound/pci/Kconfig 2006-01-16 17:28:08.000000000 +0000
+@@ -547,4 +547,10 @@
To compile this driver as a module, choose M here: the module
will be called snd-hda-intel.
@@ -5838,10 +5855,10 @@
+ Say 'Y' or 'M' to include support for SGI RAD1 Pro Audio in Octane.
+
endmenu
-diff -urN linux-2.6.12-ioc3/sound/pci/Makefile linux-2.6.12-ip30/sound/pci/Makefile
---- linux-2.6.12-ioc3/sound/pci/Makefile 2005-03-18 21:40:42.000000000 +0100
-+++ linux-2.6.12-ip30/sound/pci/Makefile 2005-07-09 13:36:14.000000000 +0200
-@@ -18,6 +18,7 @@
+diff -urN linux-mips/sound/pci/Makefile new/sound/pci/Makefile
+--- linux-mips/sound/pci/Makefile 2006-01-10 11:22:09.000000000 +0000
++++ new/sound/pci/Makefile 2006-01-16 17:28:08.000000000 +0000
+@@ -19,6 +19,7 @@
snd-intel8x0-objs := intel8x0.o
snd-intel8x0m-objs := intel8x0m.o
snd-maestro3-objs := maestro3.o
@@ -5849,7 +5866,7 @@
snd-rme32-objs := rme32.o
snd-rme96-objs := rme96.o
snd-sonicvibes-objs := sonicvibes.o
-@@ -40,6 +41,7 @@
+@@ -42,6 +43,7 @@
obj-$(CONFIG_SND_INTEL8X0) += snd-intel8x0.o
obj-$(CONFIG_SND_INTEL8X0M) += snd-intel8x0m.o
obj-$(CONFIG_SND_MAESTRO3) += snd-maestro3.o
@@ -5857,9 +5874,9 @@
obj-$(CONFIG_SND_RME32) += snd-rme32.o
obj-$(CONFIG_SND_RME96) += snd-rme96.o
obj-$(CONFIG_SND_SONICVIBES) += snd-sonicvibes.o
-diff -urN linux-2.6.12-ioc3/sound/pci/rad1.c linux-2.6.12-ip30/sound/pci/rad1.c
---- linux-2.6.12-ioc3/sound/pci/rad1.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.12-ip30/sound/pci/rad1.c 2005-07-25 08:33:37.000000000 +0200
+diff -urN linux-mips/sound/pci/rad1.c new/sound/pci/rad1.c
+--- linux-mips/sound/pci/rad1.c 1970-01-01 01:00:00.000000000 +0100
++++ new/sound/pci/rad1.c 2006-01-16 17:28:08.000000000 +0000
@@ -0,0 +1,1147 @@
+/*
+ * rad1.c - ALSA driver for SGI RAD1 (as found in Octane and Octane2)
Added: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/25_cobalt-network.dpatch
==============================================================================
--- (empty file)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/25_cobalt-network.dpatch Mon Jan 16 17:33:25 2006
@@ -0,0 +1,168 @@
+#! /bin/sh -e
+## 25_cobalt-network.dpatch by Jim Gifford <maillist at jg555.com>
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Tulip - fixes compile on MIPS64.
+
+if [ $# -lt 1 ]; then
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+ -patch) patch -p1 ${patch_opts} < $0;;
+ -unpatch) patch -R -p1 ${patch_opts} < $0;;
+ *)
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1;;
+esac
+
+exit 0
+
+I have been working on getting the RaQ2 to build using 64 bit. I ran
+into numerous issues. After I got the kernel to compile, the tulip
+driver didn't work. It kept showing error messages like
+tulip_stop_rxtx() failed
+
+This patch fixes the compile issue, this patch was create by Grant
+Grundler of linux-parsic. This patch matches the tulip driver follow the
+specs laid out by the manufacture. On 32 bit this patch seemed to make
+the tulip more responsive on my RaQ2 systems.
+
+diff -urN linux-mips/drivers/net/tulip/de2104x.c new/drivers/net/tulip/de2104x.c
+--- linux-mips/drivers/net/tulip/de2104x.c 2006-01-10 11:21:43.000000000 +0000
++++ new/drivers/net/tulip/de2104x.c 2006-01-16 16:54:50.000000000 +0000
+@@ -1787,15 +1787,10 @@
+ /* DEC now has a specification but early board makers
+ just put the address in the first EEPROM locations. */
+ /* This does memcmp(eedata, eedata+16, 8) */
+-
+-#ifndef CONFIG_MIPS_COBALT
+-
+ for (i = 0; i < 8; i ++)
+ if (ee_data[i] != ee_data[16+i])
+ sa_offset = 20;
+
+-#endif
+-
+ /* store MAC address */
+ for (i = 0; i < 6; i ++)
+ de->dev->dev_addr[i] = ee_data[i + sa_offset];
+@@ -1932,7 +1927,7 @@
+ goto fill_defaults;
+ }
+
+-static int __init de_init_one (struct pci_dev *pdev,
++static int __devinit de_init_one (struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+ {
+ struct net_device *dev;
+diff -urN linux-mips/drivers/net/tulip/de4x5.c new/drivers/net/tulip/de4x5.c
+--- linux-mips/drivers/net/tulip/de4x5.c 2006-01-10 11:21:43.000000000 +0000
++++ new/drivers/net/tulip/de4x5.c 2006-01-16 16:54:50.000000000 +0000
+@@ -2124,7 +2124,6 @@
+ .remove = __devexit_p (de4x5_eisa_remove),
+ }
+ };
+-MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
+ #endif
+
+ #ifdef CONFIG_PCI
+diff -urN linux-mips/drivers/net/tulip/media.c new/drivers/net/tulip/media.c
+--- linux-mips/drivers/net/tulip/media.c 2006-01-10 11:21:43.000000000 +0000
++++ new/drivers/net/tulip/media.c 2006-01-16 16:54:50.000000000 +0000
+@@ -44,8 +44,10 @@
+
+ /* MII transceiver control section.
+ Read and write the MII registers using software-generated serial
+- MDIO protocol. See the MII specifications or DP83840A data sheet
+- for details. */
++ MDIO protocol.
++ See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
++ or DP83840A data sheet for more details.
++ */
+
+ int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
+ {
+@@ -272,13 +274,29 @@
+ int reset_length = p[2 + init_length];
+ misc_info = (u16*)(reset_sequence + reset_length);
+ if (startup) {
++ int timeout = 10; /* max 1 ms */
+ iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
+ for (i = 0; i < reset_length; i++)
+ iowrite32(reset_sequence[i], ioaddr + CSR12);
++
++ /* flush posted writes */
++ ioread32(ioaddr + CSR12);
++
++ /* Sect 3.10.3 in DP83840A.pdf (p39) */
++ udelay(500);
++
++ /* Section 4.2 in DP83840A.pdf (p43) */
++ /* and IEEE 802.3 "22.2.4.1.1 Reset" */
++ while (timeout-- &&
++ (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
++ udelay(100);
+ }
+ for (i = 0; i < init_length; i++)
+ iowrite32(init_sequence[i], ioaddr + CSR12);
++
++ ioread32(ioaddr + CSR12); /* flush posted writes */
+ }
++
+ tmp_info = get_u16(&misc_info[1]);
+ if (tmp_info)
+ tp->advertising[phy_num] = tmp_info | 1;
+@@ -365,8 +383,6 @@
+
+ tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
+
+- mdelay(1);
+-
+ return;
+ }
+
+diff -urN linux-mips/drivers/net/tulip/tulip.h new/drivers/net/tulip/tulip.h
+--- linux-mips/drivers/net/tulip/tulip.h 2006-01-10 11:21:43.000000000 +0000
++++ new/drivers/net/tulip/tulip.h 2006-01-16 16:54:50.000000000 +0000
+@@ -474,8 +474,11 @@
+ udelay(10);
+
+ if (!i)
+- printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
+- pci_name(tp->pdev));
++ printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
++ " (CSR5 0x%x CSR6 0x%x)\n",
++ pci_name(tp->pdev),
++ ioread32(ioaddr + CSR5),
++ ioread32(ioaddr + CSR6));
+ }
+ }
+
+diff -urN linux-mips/drivers/net/tulip/tulip_core.c new/drivers/net/tulip/tulip_core.c
+--- linux-mips/drivers/net/tulip/tulip_core.c 2006-01-10 11:21:43.000000000 +0000
++++ new/drivers/net/tulip/tulip_core.c 2006-01-16 16:54:50.000000000 +0000
+@@ -22,7 +22,7 @@
+ #else
+ #define DRV_VERSION "1.1.13"
+ #endif
+-#define DRV_RELDATE "May 11, 2002"
++#define DRV_RELDATE "December 15, 2004"
+
+
+ #include <linux/module.h>
+@@ -1505,8 +1505,8 @@
+ (PCI_SLOT(pdev->devfn) == 12))) {
+ /* Cobalt MAC address in first EEPROM locations. */
+ sa_offset = 0;
+- /* Ensure our media table fixup get's applied */
+- memcpy(ee_data + 16, ee_data, 8);
++ /* No media table either */
++ tp->flags &= ~HAS_MEDIA_TABLE;
+ }
+ #endif
+ #ifdef CONFIG_GSC
Added: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/36_sb1-addrspace.dpatch
==============================================================================
--- (empty file)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/36_sb1-addrspace.dpatch Mon Jan 16 17:33:25 2006
@@ -0,0 +1,45 @@
+#! /bin/sh -e
+## 36_sb1-addrspace.dpatch by "Mark Mason" <mason at broadcom.com>
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Missing addrspace defines for sb-1.
+
+if [ $# -lt 1 ]; then
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+ -patch) patch -p0 ${patch_opts} < $0;;
+ -unpatch) patch -R -p0 ${patch_opts} < $0;;
+ *)
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1;;
+esac
+
+exit 0
+
+Here's the patch for that particular problem. There's also a few other
+patches for the SB1 floating around (check the email archives), but
+there appears to be a backlog with getting them committed to the CVS
+repository.
+
+Index: include/asm-mips/addrspace.h
+===================================================================
+RCS file: /home/cvs/linux/include/asm-mips/addrspace.h,v
+retrieving revision 1.18
+diff -u -p -r1.18 addrspace.h
+--- include/asm-mips/addrspace.h 14 Jul 2005 12:05:08 -0000 1.18
++++ include/asm-mips/addrspace.h 15 Sep 2005 21:46:56 -0000
+@@ -131,6 +131,8 @@
+ || defined (CONFIG_CPU_R5000) \
+ || defined (CONFIG_CPU_NEVADA) \
+ || defined (CONFIG_CPU_TX49XX) \
++ || defined (CONFIG_CPU_SB1) \
++ || defined (CONFIG_CPU_SB1A) \
+ || defined (CONFIG_CPU_MIPS64)
+ #define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
+ #define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
Modified: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/51_iomap.dpatch
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/51_iomap.dpatch (original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/51_iomap.dpatch Mon Jan 16 17:33:25 2006
@@ -23,22 +23,22 @@
exit 0
-diff -urN -X dontdiff a-orig/arch/mips/lib/Makefile a/arch/mips/lib/Makefile
---- a-orig/arch/mips/lib/Makefile Mon Jan 5 17:27:29 2004
-+++ a/arch/mips/lib/Makefile Wed Jan 12 01:10:23 2005
+diff -urN linux-mips/arch/mips/lib/Makefile new/arch/mips/lib/Makefile
+--- linux-mips/arch/mips/lib/Makefile 2006-01-10 11:21:15.000000000 +0000
++++ new/arch/mips/lib/Makefile 2006-01-16 16:45:26.000000000 +0000
@@ -2,7 +2,7 @@
# Makefile for MIPS-specific library files..
#
--lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o strlen_user.o \
-- strncpy_user.o strnlen_user.o uncached.o
-+lib-y += csum_partial_copy.o dec_and_lock.o iomap.o memcpy.o promlib.o \
-+ strlen_user.o strncpy_user.o strnlen_user.o uncached.o
+-lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \
+- strnlen_user.o uncached.o
++lib-y += csum_partial_copy.o iomap.o memcpy.o promlib.o strlen_user.o \
++ strncpy_user.o strnlen_user.o uncached.o
EXTRA_AFLAGS := $(CFLAGS)
-diff -urN -X dontdiff a-orig/arch/mips/lib/iomap.c a/arch/mips/lib/iomap.c
---- a-orig/arch/mips/lib/iomap.c Thu Jan 1 09:00:00 1970
-+++ a/arch/mips/lib/iomap.c Thu Jan 13 01:14:11 2005
+diff -urN linux-mips/arch/mips/lib/iomap.c new/arch/mips/lib/iomap.c
+--- linux-mips/arch/mips/lib/iomap.c 1970-01-01 01:00:00.000000000 +0100
++++ new/arch/mips/lib/iomap.c 2006-01-16 16:45:35.000000000 +0000
@@ -0,0 +1,78 @@
+/*
+ * iomap.c, Memory Mapped I/O routines for MIPS architecture.
@@ -118,11 +118,11 @@
+}
+EXPORT_SYMBOL(pci_iomap);
+EXPORT_SYMBOL(pci_iounmap);
-diff -urN -X dontdiff a-orig/include/asm-mips/io.h a/include/asm-mips/io.h
---- a-orig/include/asm-mips/io.h Mon Dec 27 15:22:30 2004
-+++ a/include/asm-mips/io.h Thu Jan 13 01:35:51 2005
-@@ -478,6 +478,34 @@
- #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+diff -urN linux-mips/include/asm-mips/io.h new/include/asm-mips/io.h
+--- linux-mips/include/asm-mips/io.h 2006-01-10 11:21:59.000000000 +0000
++++ new/include/asm-mips/io.h 2006-01-16 16:45:35.000000000 +0000
+@@ -535,6 +535,34 @@
+ }
/*
+ * Memory Mapped I/O
@@ -157,6 +157,3 @@
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
-
-
-
Added: dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/56_corefile-o32.dpatch
==============================================================================
--- (empty file)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/56_corefile-o32.dpatch Mon Jan 16 17:33:25 2006
@@ -0,0 +1,73 @@
+#! /bin/sh -e
+## 56_corefile-o32.dpatch by Dave Johnson <djohnson+linuxmips at sw.starentnetworks.com>
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: gdb gets confused with o32 core files, WANT_COMPAT_REG_H needed?
+
+if [ $# -lt 1 ]; then
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+ -patch) patch -p1 ${patch_opts} < $0;;
+ -unpatch) patch -R -p1 ${patch_opts} < $0;;
+ *)
+ echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+ exit 1;;
+esac
+
+exit 0
+
+I've been trying to fix core file support for 64bit kernel with o32
+userspace (working against 2.6.12 cvs tag).
+
+After applying the patch posted on 13 Feb 2005 from Daniel Jacobowitz
+to fix binfmt_elfo32.c (any reason this didn't make it into CVS?),
+I still ran into trouble with gdb not understanding the NT_PRSTATUS
+header in the core file.
+
+While Dan's fix makes the kernel use elf32 definitions, gdb was still
+getting confused by pr_reg contained in the core file.
+
+Dan's definition of ELF_CORE_COPY_REGS in binfmt_elfo32.c is copying
+the registers using EF_R0 as 0 not 6 producing results into offset 0
+through 37 not 6 through 43 as gdb expects for 32bit core files.
+
+Below patch (applied after Dan's patch) writes the registers at offset
+6 making gdb much happier.
+
+=======================
+
+Fix o32 core files under 64bit kernel to use correct register
+offset in NT_PRSTATUS
+
+Signed-off-by: Dave Johnson <djohnson+linuxmips at sw.starentnetworks.com>
+
+
+diff -urN linux-mips/arch/mips/kernel/binfmt_elfo32.c new/arch/mips/kernel/binfmt_elfo32.c
+--- linux-mips/arch/mips/kernel/binfmt_elfo32.c 2006-01-10 11:21:15.000000000 +0000
++++ new/arch/mips/kernel/binfmt_elfo32.c 2006-01-16 17:00:22.000000000 +0000
+@@ -51,6 +51,7 @@
+ #define TASK32_SIZE 0x7fff8000UL
+ #undef ELF_ET_DYN_BASE
+ #define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2)
++#define WANT_COMPAT_REG_H
+
+ #include <asm/processor.h>
+ #include <linux/module.h>
+diff -urN linux-mips/include/asm-mips/reg.h new/include/asm-mips/reg.h
+--- linux-mips/include/asm-mips/reg.h 2006-01-10 11:30:59.000000000 +0000
++++ new/include/asm-mips/reg.h 2006-01-16 17:01:15.000000000 +0000
+@@ -70,7 +70,7 @@
+
+ #endif
+
+-#ifdef CONFIG_64BIT
++#if defined(CONFIG_MIPS64) && !defined(WANT_COMPAT_REG_H)
+
+ #define EF_R0 0
+ #define EF_R1 1
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