[kernel] r7598 - in people/dannf/kernel-source-2.6.8-2.6.8/debian: . patches patches/series
Dann Frazier
dannf at costa.debian.org
Wed Oct 11 16:41:04 UTC 2006
Author: dannf
Date: Wed Oct 11 16:40:55 2006
New Revision: 7598
Added:
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/amd64-atomic_add_return-define.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/bnx2-1.4.43-backport.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/broadcom-mii-constants.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/i386-atomic_add_return-define.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mii-gige-support.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mmiowb-define.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mptscsih-use-common-msleep_interruptible.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/msleep_interruptible-add.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-cloned.dpatch
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-release.dpatch
Modified:
people/dannf/kernel-source-2.6.8-2.6.8/debian/changelog
people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/series/2.6.8-16sarge5dannf1
Log:
* Add interfaces needed for bnx2 driver backport:
- msleep-interruptible-add.dpatch
- mptscsih-use-common-msleep_interruptible.dpatch
- skb-header-release.dpatch
- skb-header-cloned.dpatch
- broadcom-mii-constants.dpatch
- mii-gige-support.dpatch
- mmiowb-define.dpatch
- i386-atomic_add_return-define.dpatch
- amd64-atomic_add_return-define.dpatch
* bnx2-1.4.43-backport.dpatch
Backport of bnx2 driver to 2.6.8
Modified: people/dannf/kernel-source-2.6.8-2.6.8/debian/changelog
==============================================================================
--- people/dannf/kernel-source-2.6.8-2.6.8/debian/changelog (original)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/changelog Wed Oct 11 16:40:55 2006
@@ -14,6 +14,18 @@
Update cciss driver to 2.6.10 to add support for new devices
* ata-update-to-2.6.10.dpatch
Backport the ata subsystem from 2.6.10, adding support for new devices
+ * Add interfaces needed for bnx2 driver backport:
+ - msleep-interruptible-add.dpatch
+ - mptscsih-use-common-msleep_interruptible.dpatch
+ - skb-header-release.dpatch
+ - skb-header-cloned.dpatch
+ - broadcom-mii-constants.dpatch
+ - mii-gige-support.dpatch
+ - mmiowb-define.dpatch
+ - i386-atomic_add_return-define.dpatch
+ - amd64-atomic_add_return-define.dpatch
+ * bnx2-1.4.43-backport.dpatch
+ Backport of bnx2 driver to 2.6.8
-- dann frazier <dannf at debian.org> Mon, 18 Sep 2006 16:09:32 -0600
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/amd64-atomic_add_return-define.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/amd64-atomic_add_return-define.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,49 @@
+diff -Naru a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h
+--- a/include/asm-x86_64/atomic.h 2006-09-20 23:54:34 -07:00
++++ b/include/asm-x86_64/atomic.h 2006-09-20 23:54:34 -07:00
+@@ -338,6 +338,31 @@
+ return c;
+ }
+
++/**
++ * atomic_add_return - add and return
++ * @v: pointer of type atomic_t
++ * @i: integer value to add
++ *
++ * Atomically adds @i to @v and returns @i + @v
++ */
++static __inline__ int atomic_add_return(int i, atomic_t *v)
++{
++ int __i = i;
++ __asm__ __volatile__(
++ LOCK "xaddl %0, %1;"
++ :"=r"(i)
++ :"m"(v->counter), "0"(i));
++ return i + __i;
++}
++
++static __inline__ int atomic_sub_return(int i, atomic_t *v)
++{
++ return atomic_add_return(-i,v);
++}
++
++#define atomic_inc_return(v) (atomic_add_return(1,v))
++#define atomic_dec_return(v) (atomic_sub_return(1,v))
++
+ /* These are x86-specific, used by some header files */
+ #define atomic_clear_mask(mask, addr) \
+ __asm__ __volatile__(LOCK "andl %0,%1" \
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2004/10/20 08:13:29-07:00 kaigai at ak.jp.nec.com
+# [PATCH] atomic_inc_return() for x86_64
+#
+# Signed-off-by: KaiGai, Kohei <kaigai at ak.jp.nec.com>
+# Signed-off-by: Andrew Morton <akpm at osdl.org>
+# Signed-off-by: Linus Torvalds <torvalds at osdl.org>
+#
+# include/asm-x86_64/atomic.h
+# 2004/10/20 01:12:08-07:00 kaigai at ak.jp.nec.com +25 -0
+# atomic_inc_return() for x86_64
+#
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/bnx2-1.4.43-backport.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/bnx2-1.4.43-backport.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,13268 @@
+#
+# Backport of bnx2 driver to Debian's 2.6.8 by dann frazier <dannf at hp.com>
+#
+# This patch was created by reviewing all of the changesets between the
+# introduction of the bnx2 driver and the current state in 2.6.18-rc7.
+#
+# 43 changesets were included, and required only offset adjustments
+# (the first patch excepted, it needed additional tweaks which are noted
+# in its description below). The remaining 19 changesets were too intrusive
+# for a simple backport.
+#
+# The GIT descriptions of the patches that make up this consolidated patch
+# are included below for reference.
+#
+# The changesets that were *not* included are:
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=829ca9a30a2ddb727981d80fabdbff2ea86bc9ea
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=24b8e05dc1b03c1f80828e642838511c16e17250
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b4558ea93d66a43f7990d26f145fd4c54a01c9bf
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=f71e130966ba429dbd24be08ddbcdf263df9a5ad
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=13daffa2f2ba65674e7816a0e95e7b93246cb686
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=3fdfcc2c95ffc7ee04b480a4c1fd4809b5ff2f7c
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=0f31f99446270e66c6f18c7d87aadd7db1dad214
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=e19360f2945f54eb44ae170ec9c33910d29834a2
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=932ff279a43ab7257942cddff2595acd541cc49b
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=c86a31f452f7dd132a1765d6d7160b0947f37b14
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=7967168cefdbc63bf332d6b1548eca7cd65ebbcc
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b11d6213529b33d81c21eeba97343e3b714e62e7
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=6ab3d5624e172c553004ecc862bfeac16d9d68b7
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=1fb9df5d3069064c037c81c0ab8bf783ffa5e373
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=2e8a538d865de0eb9813c8a0f2284e920299c0cc
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=9b91cf9daac41eeaaea57ecfe68dc13bb0305fa9
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=89114afd435a486deb8583e89f490fc274444d18
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=2f8af120a159a843948749ea88bcacda9779b132
+# http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=932f3772cf76cc1b1fd1538ceee3edba9bf2164f
+#
+
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 26 May 2005 20:03:09 +0000 (-0700)
+Subject: [BNX2]: New Broadcom gigabit network driver.
+X-Git-Tag: v2.6.12-rc6
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b6016b767397258b58163494a869f8f1199e6897
+
+[BNX2]: New Broadcom gigabit network driver.
+
+A new driver bnx2 for Broadcom bcm5706 is available.
+
+The patch also includes new 1000BASE-X advertisement bit definitions in
+mii.h
+
+Thanks to David Miller and Jeff Garzik for reviewing and their valuable
+feedback.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+
+#
+# Backported to Debian's 2.6.8 by dann frazier <dannf at hp.com>
+# * Use magic numbers instead of the NETDEV_TX_* macros that don't exist yet
+# * Include BMCR_SPEED1000 definition in mii.h which was originally added
+# upstream as part of an update to the gianfar driver
+# * remove an __iomem reference since this wasn't defined in 2.6.8
+#
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 26 May 2005 20:03:09 +0000 (-0700)
+Subject: [BNX2]: New Broadcom gigabit network driver.
+X-Git-Tag: v2.6.12-rc6
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b6016b767397258b58163494a869f8f1199e6897
+
+[BNX2]: New Broadcom gigabit network driver.
+
+A new driver bnx2 for Broadcom bcm5706 is available.
+
+The patch also includes new 1000BASE-X advertisement bit definitions in
+mii.h
+
+Thanks to David Miller and Jeff Garzik for reviewing and their valuable
+feedback.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Peter Hagervall <hager at cs.umu.se>
+Date: Wed, 10 Aug 2005 21:18:16 +0000 (-0700)
+Subject: [BNX2]: Possible sparse fixes, take two
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=14ab9b867aa6c107b4886bdc5b23f277ab10792e
+
+[BNX2]: Possible sparse fixes, take two
+
+This patch contains the following possible cleanups/fixes:
+
+- use C99 struct initializers
+- make a few arrays and structs static
+- remove a few uses of literal 0 as NULL pointer
+- use convenience function instead of cast+dereference in bnx2_ioctl()
+- remove superfluous casts to u8 * in calls to readl/writel
+
+Signed-off-by: Peter Hagervall <hager at cs.umu.se>
+Acked-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 25 Aug 2005 22:34:29 +0000 (-0700)
+Subject: [BNX2]: Fix rtnl deadlock in bnx2_close
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=afdc08b9f9a7174d7912a160f657f39d46379b5e
+
+[BNX2]: Fix rtnl deadlock in bnx2_close
+
+This fixes an rtnl deadlock problem when flush_scheduled_work() is
+called from bnx2_close(). In rare cases, linkwatch_event() may be on
+the workqueue from a previous close of a different device and it will
+try to get the rtnl lock which is already held by dev_close().
+
+The fix is to set a flag if we are in the reset task which is run
+from the workqueue. bnx2_close() will loop until the flag is cleared.
+As suggested by Jeff Garzik, the loop is changed to call msleep(1)
+instead of yield() in the original patch.
+
+flush_scheduled_work() is also moved to bnx2_remove_one() before the
+netdev is freed.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 25 Aug 2005 22:35:24 +0000 (-0700)
+Subject: [BNX2]: speedup serdes linkup
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=cd339a0ed61097d92ce03b6d1042b1e4d58535e7
+
+[BNX2]: speedup serdes linkup
+
+This speeds up link-up time on 5706 SerDes if the link partner does
+not autoneg, a rather common scenario in blade servers. Some blade
+servers use IPMI for keyboard input and it's important to minimize
+link disruptions.
+
+The speedup is achieved by shortening the timer to (HZ / 3) during
+the transient period right after initiating a SerDes autoneg. If
+autoneg does not complete, parallel detect can be done sooner. After
+the transient period is over, the timer goes back to its normal HZ
+interval.
+
+As suggested by Jeff Garzik, the timer initialization is moved to
+bnx2_init_board() from bnx2_open().
+
+An eeprom bit is also added to allow default forced SerDes speed for
+even faster link-up time.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 25 Aug 2005 22:36:58 +0000 (-0700)
+Subject: [BNX2]: remove atomics in tx
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=e89bbf1049aac3625fdafe3657ed8d7d5373d351
+
+[BNX2]: remove atomics in tx
+
+Remove atomic operations in the fast tx path. Expensive atomic
+operations were used to keep track of the number of available tx
+descriptors. The new code uses the difference between the consumer
+and producer index to determine the number of free tx descriptors.
+
+As suggested by Jeff Garzik, the name of the inline function is
+changed to all lower case.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 25 Aug 2005 22:38:39 +0000 (-0700)
+Subject: [BNX2]: change irq locks to bh locks
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=c770a65cee7cc250d7bccd99fa55e742988ae4e0
+
+[BNX2]: change irq locks to bh locks
+
+Change all locks from spin_lock_irqsave() to spin_lock_bh(). All
+places that require spinlocks are in BH context.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 25 Aug 2005 22:39:15 +0000 (-0700)
+Subject: [BNX2]: update version and minor fixes
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=73eef4cddb2738c4e8c5ef157ebb1b19d6c9272f
+
+[BNX2]: update version and minor fixes
+
+Update version and add 4 minor fixes, the last 2 were suggested by
+Jeff Garzik:
+
+1. check for a valid ethernet address before setting it
+2. zero out bp->regview if init_one encounters an error and unmaps
+ the IO address. This prevents remove_one from unmapping again.
+3. use netif_rx_schedule() instead of hand coding the same.
+4. use IRQ_HANDLED and IRQ_NONE.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 8 Sep 2005 20:15:32 +0000 (-0700)
+Subject: [BNX2]: Fix bug in irq handler and add prefetch
+X-Git-Tag: v2.6.14-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=c921e4c4dbb043f9435414c4e661e7f0a783053d
+
+[BNX2]: Fix bug in irq handler and add prefetch
+
+Fix bug in bnx2_interrupt() that caused an unnecessary register read.
+The BNX2_PCICFG_MISC_STATUS should only be read when the status tag
+has not changed.
+
+Add prefetch of the status block in bnx2_msi() similar to tg3_msi().
+The status block is not touched in bnx2_msi() and prefetching it will
+speed up bnx2_poll() that will run on the same CPU that received the
+MSI.
+
+Update version.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:45:49 +0000 (-0800)
+Subject: [PATCH] bnx2: add 5708 support
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=5b0c76ad94faf95ca50fa0de9ab07460bea19568
+
+[PATCH] bnx2: add 5708 support
+
+Add 5708 copper and serdes basic support, including 2.5 Gbps support
+on 5708 serdes. SPEED_2500 is also added to ethtool.h
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:49:17 +0000 (-0800)
+Subject: [PATCH] bnx2: update nvram code for 5708
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=371377091dff14090cbe995d0a9291364f8583cb
+
+[PATCH] bnx2: update nvram code for 5708
+
+Update bnx2 nvram code with support for 5708.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:51:21 +0000 (-0800)
+Subject: [PATCH] bnx2: update firmware handshake for 5708
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=e3648b3d8de3b37fae7acbb57db1e001a19cd3b7
+
+[PATCH] bnx2: update firmware handshake for 5708
+
+Dynamically determine the shared memory location where eeprom
+parameters are stored instead of using a fixed location.
+
+Add speed reporting to management firmware. This allows management
+firmware to know the current speed without contending for MII
+registers.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:53:48 +0000 (-0800)
+Subject: [PATCH] bnx2: refine bnx2_poll
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=f4e418f7f3286f854883f9f7e3bbf7005340d2de
+
+[PATCH] bnx2: refine bnx2_poll
+
+Refine bnx2_poll() logic to write back the most up-to-date status tag
+when all work has been processed. This eliminates some occasional
+extra interrupts when a older status tag is written even though all
+work has been processed.
+
+The idea is to read the status tag just before exiting bnx2_poll() and
+then check again for any new work. If no new work is pending, the
+status tag written back will not generate any extra interrupt. This
+logic is similar to the changes David Miller did to tg3_poll().
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:53:48 +0000 (-0800)
+Subject: [PATCH] bnx2: update version and minor fixes
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=05d0f1cf69fd589634b38b6f6e4b8cfdaace9ca0
+
+[PATCH] bnx2: update version and minor fixes
+
+Some book keeping and a style fix.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: John W. Linville <linville at tuxdriver.com>
+Date: Thu, 10 Nov 2005 20:57:33 +0000 (-0800)
+Subject: [BNX2]: output driver name as prefix in error message
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=2f23c523f32324e5b5f39565cbcb0a8ff8923019
+
+[BNX2]: output driver name as prefix in error message
+
+Output driver name as prefix to "Unknown flash/EEPROM type." message.
+
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: John W. Linville <linville at tuxdriver.com>
+Date: Thu, 10 Nov 2005 20:58:00 +0000 (-0800)
+Subject: [BNX2]: check return of dev_alloc_skb in bnx2_test_loopback
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b6cbc3b6fe588c0ea1341d10413e12c2a96a6032
+
+[BNX2]: check return of dev_alloc_skb in bnx2_test_loopback
+
+Check return of dev_alloc_skb in bnx2_test_loopback, and handle
+appropriately.
+
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: John W. Linville <linville at tuxdriver.com>
+Date: Thu, 10 Nov 2005 20:58:24 +0000 (-0800)
+Subject: [BNX2]: simplify parameter checks in bnx2_{get,set}_eeprom
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=1064e944d03eb7a72c0fa11236d5e69cfd877a71
+
+[BNX2]: simplify parameter checks in bnx2_{get,set}_eeprom
+
+Remove the superfluous parameter checking in bnx2_{get,set}_eeprom.
+The parameters are already validated in ethtool_{get,set}_eeprom.
+
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:06:06 +0000 (-0800)
+Subject: [BNX2]: Fix VLAN on ASF
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=e29054f92d7d575631691865c1b95bee5bc974cc
+
+[BNX2]: Fix VLAN on ASF
+
+Always set up the device to strip incoming VLAN tags when ASF is
+enabled. ASF firmware will not parse packets correctly if VLAN tags
+are not stripped.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:07:10 +0000 (-0800)
+Subject: [BNX2]: Improve handshake with firmware
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=b090ae2b59f3db57732340c6af3beceec8d6c148
+
+[BNX2]: Improve handshake with firmware
+
+Improve handshake with bootcode with the following changes:
+
+1. Increase timeout to 100msec and use msleep instead of udelay.
+
+2. Add more error checking for timeouts and errors.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Fri, 4 Nov 2005 16:48:02 +0000 (-0800)
+Subject: [PATCH] bnx2: update firmware for 5708
+X-Git-Tag: v2.6.15-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=12d30d89e57d467e4c134906a4682719813d40ad
+
+[PATCH] bnx2: update firmware for 5708
+
+Update bnx2 firmware with support for 5708.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:08:14 +0000 (-0800)
+Subject: [BNX2]: Misc. fixes
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=dda1e390bf9e2889a3abc48590a015b307637753
+
+[BNX2]: Misc. fixes
+
+Some misc. fixes for WoL, 5708 B1, and a typo '=' instead of '=='.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:09:51 +0000 (-0800)
+Subject: [BNX2]: Fix UDP checksum verification
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=ade2bfe7d1f0ea804d2e63209cc6318ad8bf17ae
+
+[BNX2]: Fix UDP checksum verification
+
+Fix TCP/UDP checksum verification. Use status bits in the buffer
+descriptor instead of the checksum value to verify rx checksum.
+Using the checksum value will be incorrect if the UDP packet has
+zero in the UDP checksum field.
+
+Firmware update required for this fix.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:11:03 +0000 (-0800)
+Subject: [BNX2]: Workaround hw interrupt bug
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=1269a8a64a37c8a06af672f4cff4fed16a478734
+
+[BNX2]: Workaround hw interrupt bug
+
+Add workaround for a hardware interrupt issue. When using INTA,
+unmasking of the interrupt and the tag update should be done
+separately to avoid some spurious interrupts,
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:11:42 +0000 (-0800)
+Subject: [BNX2]: Fix nvram sizing
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=1122db717ab5443ca9043fc0d23c1e862cfb3a61
+
+[BNX2]: Fix nvram sizing
+
+Add code to correctly determine nvram size.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:12:43 +0000 (-0800)
+Subject: [BNX2]: Use netdev_priv()
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=972ec0d4ba67bf0ec7f00cd93fbac47452f80d25
+
+[BNX2]: Use netdev_priv()
+
+Replace dev->priv with netdev_priv(dev)
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:13:22 +0000 (-0800)
+Subject: [BNX2]: Add PHY loopback test
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=bc5a0690e917206b423c7b565c997b06675fb572
+
+[BNX2]: Add PHY loopback test
+
+Enhance the ethtool loopback test with PHY loopback test.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 24 Jan 2006 00:14:05 +0000 (-0800)
+Subject: [BNX2]: Update version and copyright year
+X-Git-Tag: v2.6.16-rc2
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=206cc83ccdc29e4a73786e9093f9eeec25868441
+
+[BNX2]: Update version and copyright year
+
+Update version to 1.4.31 and add 2006 copyright.
+
+Skip the last digit when reporting the firmware version.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 21 Mar 2006 01:48:32 +0000 (-0800)
+Subject: [BNX2]: Reduce register test size
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=6b39777c5924b9db2406c5769a044da383782d0e
+
+[BNX2]: Reduce register test size
+
+Eliminate some of the registers in ethtool register test to reduce
+driver size.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 21 Mar 2006 01:48:46 +0000 (-0800)
+Subject: [BNX2]: Add ethtool -d support
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=244ac4f446ac6a19caf5eb692c4844f29e6478bf
+
+[BNX2]: Add ethtool -d support
+
+Add ETHTOOL_GREGS support.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 21 Mar 2006 01:49:02 +0000 (-0800)
+Subject: [BNX2]: Fix bug when rx ring is full
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=236b6394bb49ea58465c6f935a286d2342576f8d
+
+[BNX2]: Fix bug when rx ring is full
+
+Fix the rx code path that does not handle the full rx ring correctly.
+
+When the rx ring is set to the max. size (i.e. 255), the consumer and
+producer indices will be the same when completing an rx packet. Fix
+the rx code to handle this condition properly.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 21 Mar 2006 01:50:08 +0000 (-0800)
+Subject: [BNX2]: Update version
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=1d60290f27e7dc4bce2c43922d0bfa9abd246fc9
+
+[BNX2]: Update version
+
+Update version to 1.4.37.
+
+Add missing flush_scheduled_work() in bnx2_suspend as noted by Jeff
+Garzik.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 21 Mar 2006 01:55:25 +0000 (-0800)
+Subject: [BNX2]: include <linux/vmalloc.h>
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=0d36f37bb1e1cbadca6dc90a840bb2bc9ab51c44
+
+[BNX2]: include <linux/vmalloc.h>
+
+Include <linux/vmalloc.h> so that it compiles properly on all archs.
+
+Update version to 1.4.38.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 23 Mar 2006 09:11:56 +0000 (-0800)
+Subject: [BNX2]: Fix link change handling
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=bf5295bba804a6aead9bc1c0d5970173a9d4e08e
+
+[BNX2]: Fix link change handling
+
+Fix some link-related problems by doing a coalesce_now after link
+change interrupt to flush out the transient link status.
+
+To facilitate this, the host coalesce cmd register value is cached in
+the device structure.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 23 Mar 2006 09:13:12 +0000 (-0800)
+Subject: [BNX2]: Move .h files to bnx2.c
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=f2a4f05216e95f3b8c06b858abc0fe9a77500816
+
+[BNX2]: Move .h files to bnx2.c
+
+Move all #include <> from bnx2.h to bnx2.c.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 23 Mar 2006 09:13:43 +0000 (-0800)
+Subject: [BNX2]: Separate tx producer and consumer fields
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=29b12174ac14f110225d6d9ebb66c30df5023baf
+
+[BNX2]: Separate tx producer and consumer fields
+
+Put the tx producer and consumer fields in separate cache lines in
+the device structure, similar to the VJ net channel queue structure.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 23 Mar 2006 09:14:09 +0000 (-0800)
+Subject: [BNX2]: Update version and reldate
+X-Git-Tag: v2.6.17-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=5e2e71141ca93a3e2543966ced6a6077d4fb8fd8
+
+[BNX2]: Update version and reldate
+
+Update version to 1.4.39.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Mon, 22 May 2006 23:38:38 +0000 (-0700)
+Subject: [BNX2]: Fix bug in bnx2_nvram_write()
+X-Git-Tag: v2.6.17-rc5
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=bae25761c92c5eec781b6ea72bbe7e98fc8382a0
+
+[BNX2]: Fix bug in bnx2_nvram_write()
+
+Fix a bug in bnx2_nvram_write() caused by a counter variable not
+correctly incremented by 4.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Mon, 22 May 2006 23:39:20 +0000 (-0700)
+Subject: [BNX2]: Use kmalloc instead of array
+X-Git-Tag: v2.6.17-rc5
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=ae181bc44c65fdc93d0d2d908534b22e43f60f56
+
+[BNX2]: Use kmalloc instead of array
+
+Use kmalloc() instead of a local array in bnx2_nvram_write().
+
+Update version to 1.4.40.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Alexey Dobriyan <adobriyan at gmail.com>
+Date: Mon, 12 Jun 2006 03:57:17 +0000 (-0700)
+Subject: [BNX2]: Endian fixes.
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=d1e100ba69131bb788e89a07b94b08f6e006725a
+
+[BNX2]: Endian fixes.
+
+Signed-off-by: Alexey Dobriyan <adobriyan at gmail.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 13 Jun 2006 05:16:13 +0000 (-0700)
+Subject: [BNX2]: Add an rx drop counter
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=cea94db9b496d7fe25bbd3ebd0f24afaac2069d5
+
+[BNX2]: Add an rx drop counter
+
+Add a counter for packets dropped by firmware.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 13 Jun 2006 05:22:17 +0000 (-0700)
+Subject: [BNX2]: Use compressed firmware
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=7a6400cd3dbcfc3bbffcdb6dac4ffc957fb50e19
+
+[BNX2]: Use compressed firmware
+
+Change bnx2_fw.h to use compressed text for all CPU images.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 13 Jun 2006 05:16:43 +0000 (-0700)
+Subject: [BNX2]: Allow WoL settings on new 5708 chips
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=160882722cb21cbe5cead55cf38a5e70fc3af63e
+
+[BNX2]: Allow WoL settings on new 5708 chips
+
+Allow WOL settings on 5708 B2 and newer chips that have the problem
+fixed.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 13 Jun 2006 05:21:25 +0000 (-0700)
+Subject: [BNX2]: Add firmware decompression
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=fba9fe911bb4213c3de1d142fe0ee127cd361a78
+
+[BNX2]: Add firmware decompression
+
+Add functions to decompress firmware before loading to the internal
+CPUs. Compressing the firmware reduces the driver size significantly.
+
+Added file name length sanity check in the gzip header to prevent
+going past the end of buffer [suggested by DaveM].
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Tue, 13 Jun 2006 22:04:12 +0000 (-0700)
+Subject: [BNX2]: Update version and reldate
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=9e1881dec9e3e8f8408551cddfda489857a7ec99
+
+[BNX2]: Update version and reldate
+
+Update driver version to 1.4.42.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 29 Jun 2006 19:37:41 +0000 (-0700)
+Subject: [BNX2]: Use dev_kfree_skb() instead of the _irq version
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=745720e58303f940e12944bf7fab52bc9ce48bda
+
+[BNX2]: Use dev_kfree_skb() instead of the _irq version
+
+Change all dev_kfree_skb_irq() and dev_kfree_skb_any() to
+dev_kfree_skb(). These calls are never used in irq context.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+From: Michael Chan <mchan at broadcom.com>
+Date: Thu, 29 Jun 2006 19:38:15 +0000 (-0700)
+Subject: [BNX2]: Turn off link during shutdown
+X-Git-Tag: v2.6.18-rc1
+X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=6c4f095eae35e83eb6148dec7f72874eeadf0c9b
+
+[BNX2]: Turn off link during shutdown
+
+Minor change in shutdown logic to effect a link down.
+
+Update version to 1.4.43.
+
+Signed-off-by: Michael Chan <mchan at broadcom.com>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+diff -urN kernel-source-2.6.8-2.6.8.orig/drivers/net/Kconfig kernel-source-2.6.8-2.6.8/drivers/net/Kconfig
+--- kernel-source-2.6.8-2.6.8.orig/drivers/net/Kconfig 2006-09-19 17:45:11.927160000 -0600
++++ kernel-source-2.6.8-2.6.8/drivers/net/Kconfig 2006-09-19 17:56:05.583160000 -0600
+@@ -2090,6 +2090,17 @@
+ To compile this driver as a module, choose M here: the module
+ will be called tg3. This is recommended.
+
++config BNX2
++ tristate "Broadcom NetXtremeII support"
++ depends on PCI
++ select CRC32
++ select ZLIB_INFLATE
++ help
++ This driver supports Broadcom NetXtremeII gigabit Ethernet cards.
++
++ To compile this driver as a module, choose M here: the module
++ will be called bnx2. This is recommended.
++
+ config MV64340_ETH
+ tristate "MV-64340 Ethernet support"
+ depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || PPC_CHRP
+diff -urN kernel-source-2.6.8-2.6.8.orig/drivers/net/Makefile kernel-source-2.6.8-2.6.8/drivers/net/Makefile
+--- kernel-source-2.6.8-2.6.8.orig/drivers/net/Makefile 2006-09-19 17:45:07.971160000 -0600
++++ kernel-source-2.6.8-2.6.8/drivers/net/Makefile 2006-09-19 17:48:23.471160000 -0600
+@@ -48,6 +48,7 @@
+ obj-$(CONFIG_STNIC) += stnic.o 8390.o
+ obj-$(CONFIG_FEALNX) += fealnx.o
+ obj-$(CONFIG_TIGON3) += tg3.o
++obj-$(CONFIG_BNX2) += bnx2.o
+ obj-$(CONFIG_TC35815) += tc35815.o
+ obj-$(CONFIG_SK98LIN) += sk98lin/
+ obj-$(CONFIG_SKFP) += skfp/
+diff -urN kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2.c kernel-source-2.6.8-2.6.8/drivers/net/bnx2.c
+--- kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2.c 1969-12-31 17:00:00.000000000 -0700
++++ kernel-source-2.6.8-2.6.8/drivers/net/bnx2.c 2006-09-19 17:56:59.695160000 -0600
+@@ -0,0 +1,5973 @@
++/* bnx2.c: Broadcom NX2 network driver.
++ *
++ * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation.
++ *
++ * Written by: Michael Chan (mchan at broadcom.com)
++ */
++
++#include <linux/config.h>
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++
++#include <linux/kernel.h>
++#include <linux/timer.h>
++#include <linux/errno.h>
++#include <linux/ioport.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/interrupt.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/dma-mapping.h>
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <linux/delay.h>
++#include <asm/byteorder.h>
++#include <linux/time.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#ifdef NETIF_F_HW_VLAN_TX
++#include <linux/if_vlan.h>
++#define BCM_VLAN 1
++#endif
++#ifdef NETIF_F_TSO
++#include <net/ip.h>
++#include <net/tcp.h>
++#include <net/checksum.h>
++#define BCM_TSO 1
++#endif
++#include <linux/workqueue.h>
++#include <linux/crc32.h>
++#include <linux/prefetch.h>
++#include <linux/cache.h>
++#include <linux/zlib.h>
++
++#include "bnx2.h"
++#include "bnx2_fw.h"
++
++#define DRV_MODULE_NAME "bnx2"
++#define PFX DRV_MODULE_NAME ": "
++#define DRV_MODULE_VERSION "1.4.43"
++#define DRV_MODULE_RELDATE "June 28, 2006"
++
++#define RUN_AT(x) (jiffies + (x))
++
++/* Time in jiffies before concluding the transmitter is hung. */
++#define TX_TIMEOUT (5*HZ)
++
++static char version[] __devinitdata =
++ "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
++
++MODULE_AUTHOR("Michael Chan <mchan at broadcom.com>");
++MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRV_MODULE_VERSION);
++
++static int disable_msi = 0;
++
++module_param(disable_msi, int, 0);
++MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
++
++typedef enum {
++ BCM5706 = 0,
++ NC370T,
++ NC370I,
++ BCM5706S,
++ NC370F,
++ BCM5708,
++ BCM5708S,
++} board_t;
++
++/* indexed by board_t, above */
++static struct {
++ char *name;
++} board_info[] __devinitdata = {
++ { "Broadcom NetXtreme II BCM5706 1000Base-T" },
++ { "HP NC370T Multifunction Gigabit Server Adapter" },
++ { "HP NC370i Multifunction Gigabit Server Adapter" },
++ { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
++ { "HP NC370F Multifunction Gigabit Server Adapter" },
++ { "Broadcom NetXtreme II BCM5708 1000Base-T" },
++ { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
++ };
++
++static struct pci_device_id bnx2_pci_tbl[] = {
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
++ PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
++ PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
++ PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
++ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
++ { 0, }
++};
++
++static struct flash_spec flash_table[] =
++{
++ /* Slow EEPROM */
++ {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
++ 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
++ SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
++ "EEPROM - slow"},
++ /* Expansion entry 0001 */
++ {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 0001"},
++ /* Saifun SA25F010 (non-buffered flash) */
++ /* strap, cfg1, & write1 need updates */
++ {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
++ "Non-buffered flash (128kB)"},
++ /* Saifun SA25F020 (non-buffered flash) */
++ /* strap, cfg1, & write1 need updates */
++ {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
++ "Non-buffered flash (256kB)"},
++ /* Expansion entry 0100 */
++ {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 0100"},
++ /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
++ {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
++ 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
++ ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
++ "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
++ /* Entry 0110: ST M45PE20 (non-buffered flash)*/
++ {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
++ 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
++ ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
++ "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
++ /* Saifun SA25F005 (non-buffered flash) */
++ /* strap, cfg1, & write1 need updates */
++ {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
++ "Non-buffered flash (64kB)"},
++ /* Fast EEPROM */
++ {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
++ 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
++ SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
++ "EEPROM - fast"},
++ /* Expansion entry 1001 */
++ {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 1001"},
++ /* Expansion entry 1010 */
++ {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 1010"},
++ /* ATMEL AT45DB011B (buffered flash) */
++ {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
++ 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
++ BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
++ "Buffered flash (128kB)"},
++ /* Expansion entry 1100 */
++ {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 1100"},
++ /* Expansion entry 1101 */
++ {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
++ 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
++ SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 1101"},
++ /* Ateml Expansion entry 1110 */
++ {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
++ 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
++ BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
++ "Entry 1110 (Atmel)"},
++ /* ATMEL AT45DB021B (buffered flash) */
++ {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
++ 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
++ BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
++ "Buffered flash (256kB)"},
++};
++
++MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
++
++static inline u32 bnx2_tx_avail(struct bnx2 *bp)
++{
++ u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
++
++ if (diff > MAX_TX_DESC_CNT)
++ diff = (diff & MAX_TX_DESC_CNT) - 1;
++ return (bp->tx_ring_size - diff);
++}
++
++static u32
++bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
++{
++ REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
++ return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
++}
++
++static void
++bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
++{
++ REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
++ REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
++}
++
++static void
++bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
++{
++ offset += cid_addr;
++ REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
++ REG_WR(bp, BNX2_CTX_DATA, val);
++}
++
++static int
++bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
++{
++ u32 val1;
++ int i, ret;
++
++ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++ val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
++
++ REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
++ REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++
++ udelay(40);
++ }
++
++ val1 = (bp->phy_addr << 21) | (reg << 16) |
++ BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
++ BNX2_EMAC_MDIO_COMM_START_BUSY;
++ REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
++
++ for (i = 0; i < 50; i++) {
++ udelay(10);
++
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
++ if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
++ udelay(5);
++
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
++ val1 &= BNX2_EMAC_MDIO_COMM_DATA;
++
++ break;
++ }
++ }
++
++ if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
++ *val = 0x0;
++ ret = -EBUSY;
++ }
++ else {
++ *val = val1;
++ ret = 0;
++ }
++
++ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++ val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
++
++ REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
++ REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++
++ udelay(40);
++ }
++
++ return ret;
++}
++
++static int
++bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
++{
++ u32 val1;
++ int i, ret;
++
++ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++ val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
++
++ REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
++ REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++
++ udelay(40);
++ }
++
++ val1 = (bp->phy_addr << 21) | (reg << 16) | val |
++ BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
++ BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
++ REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
++
++ for (i = 0; i < 50; i++) {
++ udelay(10);
++
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
++ if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
++ udelay(5);
++ break;
++ }
++ }
++
++ if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
++ ret = -EBUSY;
++ else
++ ret = 0;
++
++ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
++ val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++ val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
++
++ REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
++ REG_RD(bp, BNX2_EMAC_MDIO_MODE);
++
++ udelay(40);
++ }
++
++ return ret;
++}
++
++static void
++bnx2_disable_int(struct bnx2 *bp)
++{
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
++ REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
++}
++
++static void
++bnx2_enable_int(struct bnx2 *bp)
++{
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
++
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
++
++ REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
++}
++
++static void
++bnx2_disable_int_sync(struct bnx2 *bp)
++{
++ atomic_inc(&bp->intr_sem);
++ bnx2_disable_int(bp);
++ synchronize_irq(bp->pdev->irq);
++}
++
++static void
++bnx2_netif_stop(struct bnx2 *bp)
++{
++ bnx2_disable_int_sync(bp);
++ if (netif_running(bp->dev)) {
++ netif_poll_disable(bp->dev);
++ netif_tx_disable(bp->dev);
++ bp->dev->trans_start = jiffies; /* prevent tx timeout */
++ }
++}
++
++static void
++bnx2_netif_start(struct bnx2 *bp)
++{
++ if (atomic_dec_and_test(&bp->intr_sem)) {
++ if (netif_running(bp->dev)) {
++ netif_wake_queue(bp->dev);
++ netif_poll_enable(bp->dev);
++ bnx2_enable_int(bp);
++ }
++ }
++}
++
++static void
++bnx2_free_mem(struct bnx2 *bp)
++{
++ if (bp->stats_blk) {
++ pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
++ bp->stats_blk, bp->stats_blk_mapping);
++ bp->stats_blk = NULL;
++ }
++ if (bp->status_blk) {
++ pci_free_consistent(bp->pdev, sizeof(struct status_block),
++ bp->status_blk, bp->status_blk_mapping);
++ bp->status_blk = NULL;
++ }
++ if (bp->tx_desc_ring) {
++ pci_free_consistent(bp->pdev,
++ sizeof(struct tx_bd) * TX_DESC_CNT,
++ bp->tx_desc_ring, bp->tx_desc_mapping);
++ bp->tx_desc_ring = NULL;
++ }
++ if (bp->tx_buf_ring) {
++ kfree(bp->tx_buf_ring);
++ bp->tx_buf_ring = NULL;
++ }
++ if (bp->rx_desc_ring) {
++ pci_free_consistent(bp->pdev,
++ sizeof(struct rx_bd) * RX_DESC_CNT,
++ bp->rx_desc_ring, bp->rx_desc_mapping);
++ bp->rx_desc_ring = NULL;
++ }
++ if (bp->rx_buf_ring) {
++ kfree(bp->rx_buf_ring);
++ bp->rx_buf_ring = NULL;
++ }
++}
++
++static int
++bnx2_alloc_mem(struct bnx2 *bp)
++{
++ bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
++ GFP_KERNEL);
++ if (bp->tx_buf_ring == NULL)
++ return -ENOMEM;
++
++ memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
++ bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
++ sizeof(struct tx_bd) *
++ TX_DESC_CNT,
++ &bp->tx_desc_mapping);
++ if (bp->tx_desc_ring == NULL)
++ goto alloc_mem_err;
++
++ bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
++ GFP_KERNEL);
++ if (bp->rx_buf_ring == NULL)
++ goto alloc_mem_err;
++
++ memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
++ bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
++ sizeof(struct rx_bd) *
++ RX_DESC_CNT,
++ &bp->rx_desc_mapping);
++ if (bp->rx_desc_ring == NULL)
++ goto alloc_mem_err;
++
++ bp->status_blk = pci_alloc_consistent(bp->pdev,
++ sizeof(struct status_block),
++ &bp->status_blk_mapping);
++ if (bp->status_blk == NULL)
++ goto alloc_mem_err;
++
++ memset(bp->status_blk, 0, sizeof(struct status_block));
++
++ bp->stats_blk = pci_alloc_consistent(bp->pdev,
++ sizeof(struct statistics_block),
++ &bp->stats_blk_mapping);
++ if (bp->stats_blk == NULL)
++ goto alloc_mem_err;
++
++ memset(bp->stats_blk, 0, sizeof(struct statistics_block));
++
++ return 0;
++
++alloc_mem_err:
++ bnx2_free_mem(bp);
++ return -ENOMEM;
++}
++
++static void
++bnx2_report_fw_link(struct bnx2 *bp)
++{
++ u32 fw_link_status = 0;
++
++ if (bp->link_up) {
++ u32 bmsr;
++
++ switch (bp->line_speed) {
++ case SPEED_10:
++ if (bp->duplex == DUPLEX_HALF)
++ fw_link_status = BNX2_LINK_STATUS_10HALF;
++ else
++ fw_link_status = BNX2_LINK_STATUS_10FULL;
++ break;
++ case SPEED_100:
++ if (bp->duplex == DUPLEX_HALF)
++ fw_link_status = BNX2_LINK_STATUS_100HALF;
++ else
++ fw_link_status = BNX2_LINK_STATUS_100FULL;
++ break;
++ case SPEED_1000:
++ if (bp->duplex == DUPLEX_HALF)
++ fw_link_status = BNX2_LINK_STATUS_1000HALF;
++ else
++ fw_link_status = BNX2_LINK_STATUS_1000FULL;
++ break;
++ case SPEED_2500:
++ if (bp->duplex == DUPLEX_HALF)
++ fw_link_status = BNX2_LINK_STATUS_2500HALF;
++ else
++ fw_link_status = BNX2_LINK_STATUS_2500FULL;
++ break;
++ }
++
++ fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
++
++ if (bp->autoneg) {
++ fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
++
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++
++ if (!(bmsr & BMSR_ANEGCOMPLETE) ||
++ bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
++ fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
++ else
++ fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
++ }
++ }
++ else
++ fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
++
++ REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
++}
++
++static void
++bnx2_report_link(struct bnx2 *bp)
++{
++ if (bp->link_up) {
++ netif_carrier_on(bp->dev);
++ printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
++
++ printk("%d Mbps ", bp->line_speed);
++
++ if (bp->duplex == DUPLEX_FULL)
++ printk("full duplex");
++ else
++ printk("half duplex");
++
++ if (bp->flow_ctrl) {
++ if (bp->flow_ctrl & FLOW_CTRL_RX) {
++ printk(", receive ");
++ if (bp->flow_ctrl & FLOW_CTRL_TX)
++ printk("& transmit ");
++ }
++ else {
++ printk(", transmit ");
++ }
++ printk("flow control ON");
++ }
++ printk("\n");
++ }
++ else {
++ netif_carrier_off(bp->dev);
++ printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
++ }
++
++ bnx2_report_fw_link(bp);
++}
++
++static void
++bnx2_resolve_flow_ctrl(struct bnx2 *bp)
++{
++ u32 local_adv, remote_adv;
++
++ bp->flow_ctrl = 0;
++ if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
++ (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
++
++ if (bp->duplex == DUPLEX_FULL) {
++ bp->flow_ctrl = bp->req_flow_ctrl;
++ }
++ return;
++ }
++
++ if (bp->duplex != DUPLEX_FULL) {
++ return;
++ }
++
++ if ((bp->phy_flags & PHY_SERDES_FLAG) &&
++ (CHIP_NUM(bp) == CHIP_NUM_5708)) {
++ u32 val;
++
++ bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
++ if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
++ bp->flow_ctrl |= FLOW_CTRL_TX;
++ if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
++ bp->flow_ctrl |= FLOW_CTRL_RX;
++ return;
++ }
++
++ bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
++ bnx2_read_phy(bp, MII_LPA, &remote_adv);
++
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ u32 new_local_adv = 0;
++ u32 new_remote_adv = 0;
++
++ if (local_adv & ADVERTISE_1000XPAUSE)
++ new_local_adv |= ADVERTISE_PAUSE_CAP;
++ if (local_adv & ADVERTISE_1000XPSE_ASYM)
++ new_local_adv |= ADVERTISE_PAUSE_ASYM;
++ if (remote_adv & ADVERTISE_1000XPAUSE)
++ new_remote_adv |= ADVERTISE_PAUSE_CAP;
++ if (remote_adv & ADVERTISE_1000XPSE_ASYM)
++ new_remote_adv |= ADVERTISE_PAUSE_ASYM;
++
++ local_adv = new_local_adv;
++ remote_adv = new_remote_adv;
++ }
++
++ /* See Table 28B-3 of 802.3ab-1999 spec. */
++ if (local_adv & ADVERTISE_PAUSE_CAP) {
++ if(local_adv & ADVERTISE_PAUSE_ASYM) {
++ if (remote_adv & ADVERTISE_PAUSE_CAP) {
++ bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
++ }
++ else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
++ bp->flow_ctrl = FLOW_CTRL_RX;
++ }
++ }
++ else {
++ if (remote_adv & ADVERTISE_PAUSE_CAP) {
++ bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
++ }
++ }
++ }
++ else if (local_adv & ADVERTISE_PAUSE_ASYM) {
++ if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
++ (remote_adv & ADVERTISE_PAUSE_ASYM)) {
++
++ bp->flow_ctrl = FLOW_CTRL_TX;
++ }
++ }
++}
++
++static int
++bnx2_5708s_linkup(struct bnx2 *bp)
++{
++ u32 val;
++
++ bp->link_up = 1;
++ bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
++ switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
++ case BCM5708S_1000X_STAT1_SPEED_10:
++ bp->line_speed = SPEED_10;
++ break;
++ case BCM5708S_1000X_STAT1_SPEED_100:
++ bp->line_speed = SPEED_100;
++ break;
++ case BCM5708S_1000X_STAT1_SPEED_1G:
++ bp->line_speed = SPEED_1000;
++ break;
++ case BCM5708S_1000X_STAT1_SPEED_2G5:
++ bp->line_speed = SPEED_2500;
++ break;
++ }
++ if (val & BCM5708S_1000X_STAT1_FD)
++ bp->duplex = DUPLEX_FULL;
++ else
++ bp->duplex = DUPLEX_HALF;
++
++ return 0;
++}
++
++static int
++bnx2_5706s_linkup(struct bnx2 *bp)
++{
++ u32 bmcr, local_adv, remote_adv, common;
++
++ bp->link_up = 1;
++ bp->line_speed = SPEED_1000;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ if (bmcr & BMCR_FULLDPLX) {
++ bp->duplex = DUPLEX_FULL;
++ }
++ else {
++ bp->duplex = DUPLEX_HALF;
++ }
++
++ if (!(bmcr & BMCR_ANENABLE)) {
++ return 0;
++ }
++
++ bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
++ bnx2_read_phy(bp, MII_LPA, &remote_adv);
++
++ common = local_adv & remote_adv;
++ if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
++
++ if (common & ADVERTISE_1000XFULL) {
++ bp->duplex = DUPLEX_FULL;
++ }
++ else {
++ bp->duplex = DUPLEX_HALF;
++ }
++ }
++
++ return 0;
++}
++
++static int
++bnx2_copper_linkup(struct bnx2 *bp)
++{
++ u32 bmcr;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ if (bmcr & BMCR_ANENABLE) {
++ u32 local_adv, remote_adv, common;
++
++ bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
++ bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
++
++ common = local_adv & (remote_adv >> 2);
++ if (common & ADVERTISE_1000FULL) {
++ bp->line_speed = SPEED_1000;
++ bp->duplex = DUPLEX_FULL;
++ }
++ else if (common & ADVERTISE_1000HALF) {
++ bp->line_speed = SPEED_1000;
++ bp->duplex = DUPLEX_HALF;
++ }
++ else {
++ bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
++ bnx2_read_phy(bp, MII_LPA, &remote_adv);
++
++ common = local_adv & remote_adv;
++ if (common & ADVERTISE_100FULL) {
++ bp->line_speed = SPEED_100;
++ bp->duplex = DUPLEX_FULL;
++ }
++ else if (common & ADVERTISE_100HALF) {
++ bp->line_speed = SPEED_100;
++ bp->duplex = DUPLEX_HALF;
++ }
++ else if (common & ADVERTISE_10FULL) {
++ bp->line_speed = SPEED_10;
++ bp->duplex = DUPLEX_FULL;
++ }
++ else if (common & ADVERTISE_10HALF) {
++ bp->line_speed = SPEED_10;
++ bp->duplex = DUPLEX_HALF;
++ }
++ else {
++ bp->line_speed = 0;
++ bp->link_up = 0;
++ }
++ }
++ }
++ else {
++ if (bmcr & BMCR_SPEED100) {
++ bp->line_speed = SPEED_100;
++ }
++ else {
++ bp->line_speed = SPEED_10;
++ }
++ if (bmcr & BMCR_FULLDPLX) {
++ bp->duplex = DUPLEX_FULL;
++ }
++ else {
++ bp->duplex = DUPLEX_HALF;
++ }
++ }
++
++ return 0;
++}
++
++static int
++bnx2_set_mac_link(struct bnx2 *bp)
++{
++ u32 val;
++
++ REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
++ if (bp->link_up && (bp->line_speed == SPEED_1000) &&
++ (bp->duplex == DUPLEX_HALF)) {
++ REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
++ }
++
++ /* Configure the EMAC mode register. */
++ val = REG_RD(bp, BNX2_EMAC_MODE);
++
++ val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
++ BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
++ BNX2_EMAC_MODE_25G);
++
++ if (bp->link_up) {
++ switch (bp->line_speed) {
++ case SPEED_10:
++ if (CHIP_NUM(bp) == CHIP_NUM_5708) {
++ val |= BNX2_EMAC_MODE_PORT_MII_10;
++ break;
++ }
++ /* fall through */
++ case SPEED_100:
++ val |= BNX2_EMAC_MODE_PORT_MII;
++ break;
++ case SPEED_2500:
++ val |= BNX2_EMAC_MODE_25G;
++ /* fall through */
++ case SPEED_1000:
++ val |= BNX2_EMAC_MODE_PORT_GMII;
++ break;
++ }
++ }
++ else {
++ val |= BNX2_EMAC_MODE_PORT_GMII;
++ }
++
++ /* Set the MAC to operate in the appropriate duplex mode. */
++ if (bp->duplex == DUPLEX_HALF)
++ val |= BNX2_EMAC_MODE_HALF_DUPLEX;
++ REG_WR(bp, BNX2_EMAC_MODE, val);
++
++ /* Enable/disable rx PAUSE. */
++ bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
++
++ if (bp->flow_ctrl & FLOW_CTRL_RX)
++ bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
++ REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
++
++ /* Enable/disable tx PAUSE. */
++ val = REG_RD(bp, BNX2_EMAC_TX_MODE);
++ val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
++
++ if (bp->flow_ctrl & FLOW_CTRL_TX)
++ val |= BNX2_EMAC_TX_MODE_FLOW_EN;
++ REG_WR(bp, BNX2_EMAC_TX_MODE, val);
++
++ /* Acknowledge the interrupt. */
++ REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
++
++ return 0;
++}
++
++static int
++bnx2_set_link(struct bnx2 *bp)
++{
++ u32 bmsr;
++ u8 link_up;
++
++ if (bp->loopback == MAC_LOOPBACK) {
++ bp->link_up = 1;
++ return 0;
++ }
++
++ link_up = bp->link_up;
++
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++
++ if ((bp->phy_flags & PHY_SERDES_FLAG) &&
++ (CHIP_NUM(bp) == CHIP_NUM_5706)) {
++ u32 val;
++
++ val = REG_RD(bp, BNX2_EMAC_STATUS);
++ if (val & BNX2_EMAC_STATUS_LINK)
++ bmsr |= BMSR_LSTATUS;
++ else
++ bmsr &= ~BMSR_LSTATUS;
++ }
++
++ if (bmsr & BMSR_LSTATUS) {
++ bp->link_up = 1;
++
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ if (CHIP_NUM(bp) == CHIP_NUM_5706)
++ bnx2_5706s_linkup(bp);
++ else if (CHIP_NUM(bp) == CHIP_NUM_5708)
++ bnx2_5708s_linkup(bp);
++ }
++ else {
++ bnx2_copper_linkup(bp);
++ }
++ bnx2_resolve_flow_ctrl(bp);
++ }
++ else {
++ if ((bp->phy_flags & PHY_SERDES_FLAG) &&
++ (bp->autoneg & AUTONEG_SPEED)) {
++
++ u32 bmcr;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ if (!(bmcr & BMCR_ANENABLE)) {
++ bnx2_write_phy(bp, MII_BMCR, bmcr |
++ BMCR_ANENABLE);
++ }
++ }
++ bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
++ bp->link_up = 0;
++ }
++
++ if (bp->link_up != link_up) {
++ bnx2_report_link(bp);
++ }
++
++ bnx2_set_mac_link(bp);
++
++ return 0;
++}
++
++static int
++bnx2_reset_phy(struct bnx2 *bp)
++{
++ int i;
++ u32 reg;
++
++ bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
++
++#define PHY_RESET_MAX_WAIT 100
++ for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
++ udelay(10);
++
++ bnx2_read_phy(bp, MII_BMCR, ®);
++ if (!(reg & BMCR_RESET)) {
++ udelay(20);
++ break;
++ }
++ }
++ if (i == PHY_RESET_MAX_WAIT) {
++ return -EBUSY;
++ }
++ return 0;
++}
++
++static u32
++bnx2_phy_get_pause_adv(struct bnx2 *bp)
++{
++ u32 adv = 0;
++
++ if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
++ (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
++
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ adv = ADVERTISE_1000XPAUSE;
++ }
++ else {
++ adv = ADVERTISE_PAUSE_CAP;
++ }
++ }
++ else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ adv = ADVERTISE_1000XPSE_ASYM;
++ }
++ else {
++ adv = ADVERTISE_PAUSE_ASYM;
++ }
++ }
++ else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
++ }
++ else {
++ adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
++ }
++ }
++ return adv;
++}
++
++static int
++bnx2_setup_serdes_phy(struct bnx2 *bp)
++{
++ u32 adv, bmcr, up1;
++ u32 new_adv = 0;
++
++ if (!(bp->autoneg & AUTONEG_SPEED)) {
++ u32 new_bmcr;
++ int force_link_down = 0;
++
++ if (CHIP_NUM(bp) == CHIP_NUM_5708) {
++ bnx2_read_phy(bp, BCM5708S_UP1, &up1);
++ if (up1 & BCM5708S_UP1_2G5) {
++ up1 &= ~BCM5708S_UP1_2G5;
++ bnx2_write_phy(bp, BCM5708S_UP1, up1);
++ force_link_down = 1;
++ }
++ }
++
++ bnx2_read_phy(bp, MII_ADVERTISE, &adv);
++ adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ new_bmcr = bmcr & ~BMCR_ANENABLE;
++ new_bmcr |= BMCR_SPEED1000;
++ if (bp->req_duplex == DUPLEX_FULL) {
++ adv |= ADVERTISE_1000XFULL;
++ new_bmcr |= BMCR_FULLDPLX;
++ }
++ else {
++ adv |= ADVERTISE_1000XHALF;
++ new_bmcr &= ~BMCR_FULLDPLX;
++ }
++ if ((new_bmcr != bmcr) || (force_link_down)) {
++ /* Force a link down visible on the other side */
++ if (bp->link_up) {
++ bnx2_write_phy(bp, MII_ADVERTISE, adv &
++ ~(ADVERTISE_1000XFULL |
++ ADVERTISE_1000XHALF));
++ bnx2_write_phy(bp, MII_BMCR, bmcr |
++ BMCR_ANRESTART | BMCR_ANENABLE);
++
++ bp->link_up = 0;
++ netif_carrier_off(bp->dev);
++ bnx2_write_phy(bp, MII_BMCR, new_bmcr);
++ }
++ bnx2_write_phy(bp, MII_ADVERTISE, adv);
++ bnx2_write_phy(bp, MII_BMCR, new_bmcr);
++ }
++ return 0;
++ }
++
++ if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
++ bnx2_read_phy(bp, BCM5708S_UP1, &up1);
++ up1 |= BCM5708S_UP1_2G5;
++ bnx2_write_phy(bp, BCM5708S_UP1, up1);
++ }
++
++ if (bp->advertising & ADVERTISED_1000baseT_Full)
++ new_adv |= ADVERTISE_1000XFULL;
++
++ new_adv |= bnx2_phy_get_pause_adv(bp);
++
++ bnx2_read_phy(bp, MII_ADVERTISE, &adv);
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++
++ bp->serdes_an_pending = 0;
++ if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
++ /* Force a link down visible on the other side */
++ if (bp->link_up) {
++ int i;
++
++ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
++ for (i = 0; i < 110; i++) {
++ udelay(100);
++ }
++ }
++
++ bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
++ bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
++ BMCR_ANENABLE);
++ if (CHIP_NUM(bp) == CHIP_NUM_5706) {
++ /* Speed up link-up time when the link partner
++ * does not autonegotiate which is very common
++ * in blade servers. Some blade servers use
++ * IPMI for kerboard input and it's important
++ * to minimize link disruptions. Autoneg. involves
++ * exchanging base pages plus 3 next pages and
++ * normally completes in about 120 msec.
++ */
++ bp->current_interval = SERDES_AN_TIMEOUT;
++ bp->serdes_an_pending = 1;
++ mod_timer(&bp->timer, jiffies + bp->current_interval);
++ }
++ }
++
++ return 0;
++}
++
++#define ETHTOOL_ALL_FIBRE_SPEED \
++ (ADVERTISED_1000baseT_Full)
++
++#define ETHTOOL_ALL_COPPER_SPEED \
++ (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
++ ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
++ ADVERTISED_1000baseT_Full)
++
++#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
++ ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
++
++#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
++
++static int
++bnx2_setup_copper_phy(struct bnx2 *bp)
++{
++ u32 bmcr;
++ u32 new_bmcr;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++
++ if (bp->autoneg & AUTONEG_SPEED) {
++ u32 adv_reg, adv1000_reg;
++ u32 new_adv_reg = 0;
++ u32 new_adv1000_reg = 0;
++
++ bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
++ adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
++ ADVERTISE_PAUSE_ASYM);
++
++ bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
++ adv1000_reg &= PHY_ALL_1000_SPEED;
++
++ if (bp->advertising & ADVERTISED_10baseT_Half)
++ new_adv_reg |= ADVERTISE_10HALF;
++ if (bp->advertising & ADVERTISED_10baseT_Full)
++ new_adv_reg |= ADVERTISE_10FULL;
++ if (bp->advertising & ADVERTISED_100baseT_Half)
++ new_adv_reg |= ADVERTISE_100HALF;
++ if (bp->advertising & ADVERTISED_100baseT_Full)
++ new_adv_reg |= ADVERTISE_100FULL;
++ if (bp->advertising & ADVERTISED_1000baseT_Full)
++ new_adv1000_reg |= ADVERTISE_1000FULL;
++
++ new_adv_reg |= ADVERTISE_CSMA;
++
++ new_adv_reg |= bnx2_phy_get_pause_adv(bp);
++
++ if ((adv1000_reg != new_adv1000_reg) ||
++ (adv_reg != new_adv_reg) ||
++ ((bmcr & BMCR_ANENABLE) == 0)) {
++
++ bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
++ bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
++ bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
++ BMCR_ANENABLE);
++ }
++ else if (bp->link_up) {
++ /* Flow ctrl may have changed from auto to forced */
++ /* or vice-versa. */
++
++ bnx2_resolve_flow_ctrl(bp);
++ bnx2_set_mac_link(bp);
++ }
++ return 0;
++ }
++
++ new_bmcr = 0;
++ if (bp->req_line_speed == SPEED_100) {
++ new_bmcr |= BMCR_SPEED100;
++ }
++ if (bp->req_duplex == DUPLEX_FULL) {
++ new_bmcr |= BMCR_FULLDPLX;
++ }
++ if (new_bmcr != bmcr) {
++ u32 bmsr;
++ int i = 0;
++
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++
++ if (bmsr & BMSR_LSTATUS) {
++ /* Force link down */
++ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
++ do {
++ udelay(100);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ i++;
++ } while ((bmsr & BMSR_LSTATUS) && (i < 620));
++ }
++
++ bnx2_write_phy(bp, MII_BMCR, new_bmcr);
++
++ /* Normally, the new speed is setup after the link has
++ * gone down and up again. In some cases, link will not go
++ * down so we need to set up the new speed here.
++ */
++ if (bmsr & BMSR_LSTATUS) {
++ bp->line_speed = bp->req_line_speed;
++ bp->duplex = bp->req_duplex;
++ bnx2_resolve_flow_ctrl(bp);
++ bnx2_set_mac_link(bp);
++ }
++ }
++ return 0;
++}
++
++static int
++bnx2_setup_phy(struct bnx2 *bp)
++{
++ if (bp->loopback == MAC_LOOPBACK)
++ return 0;
++
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ return (bnx2_setup_serdes_phy(bp));
++ }
++ else {
++ return (bnx2_setup_copper_phy(bp));
++ }
++}
++
++static int
++bnx2_init_5708s_phy(struct bnx2 *bp)
++{
++ u32 val;
++
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
++ bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
++
++ bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
++ val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
++ bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
++
++ bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
++ val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
++ bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
++
++ if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
++ bnx2_read_phy(bp, BCM5708S_UP1, &val);
++ val |= BCM5708S_UP1_2G5;
++ bnx2_write_phy(bp, BCM5708S_UP1, val);
++ }
++
++ if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
++ /* increase tx signal amplitude */
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
++ BCM5708S_BLK_ADDR_TX_MISC);
++ bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
++ val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
++ bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
++ }
++
++ val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
++ BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
++
++ if (val) {
++ u32 is_backplane;
++
++ is_backplane = REG_RD_IND(bp, bp->shmem_base +
++ BNX2_SHARED_HW_CFG_CONFIG);
++ if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
++ BCM5708S_BLK_ADDR_TX_MISC);
++ bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
++ bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
++ BCM5708S_BLK_ADDR_DIG);
++ }
++ }
++ return 0;
++}
++
++static int
++bnx2_init_5706s_phy(struct bnx2 *bp)
++{
++ bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
++
++ if (CHIP_NUM(bp) == CHIP_NUM_5706) {
++ REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
++ }
++
++ if (bp->dev->mtu > 1500) {
++ u32 val;
++
++ /* Set extended packet length bit */
++ bnx2_write_phy(bp, 0x18, 0x7);
++ bnx2_read_phy(bp, 0x18, &val);
++ bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
++
++ bnx2_write_phy(bp, 0x1c, 0x6c00);
++ bnx2_read_phy(bp, 0x1c, &val);
++ bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
++ }
++ else {
++ u32 val;
++
++ bnx2_write_phy(bp, 0x18, 0x7);
++ bnx2_read_phy(bp, 0x18, &val);
++ bnx2_write_phy(bp, 0x18, val & ~0x4007);
++
++ bnx2_write_phy(bp, 0x1c, 0x6c00);
++ bnx2_read_phy(bp, 0x1c, &val);
++ bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
++ }
++
++ return 0;
++}
++
++static int
++bnx2_init_copper_phy(struct bnx2 *bp)
++{
++ u32 val;
++
++ bp->phy_flags |= PHY_CRC_FIX_FLAG;
++
++ if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
++ bnx2_write_phy(bp, 0x18, 0x0c00);
++ bnx2_write_phy(bp, 0x17, 0x000a);
++ bnx2_write_phy(bp, 0x15, 0x310b);
++ bnx2_write_phy(bp, 0x17, 0x201f);
++ bnx2_write_phy(bp, 0x15, 0x9506);
++ bnx2_write_phy(bp, 0x17, 0x401f);
++ bnx2_write_phy(bp, 0x15, 0x14e2);
++ bnx2_write_phy(bp, 0x18, 0x0400);
++ }
++
++ if (bp->dev->mtu > 1500) {
++ /* Set extended packet length bit */
++ bnx2_write_phy(bp, 0x18, 0x7);
++ bnx2_read_phy(bp, 0x18, &val);
++ bnx2_write_phy(bp, 0x18, val | 0x4000);
++
++ bnx2_read_phy(bp, 0x10, &val);
++ bnx2_write_phy(bp, 0x10, val | 0x1);
++ }
++ else {
++ bnx2_write_phy(bp, 0x18, 0x7);
++ bnx2_read_phy(bp, 0x18, &val);
++ bnx2_write_phy(bp, 0x18, val & ~0x4007);
++
++ bnx2_read_phy(bp, 0x10, &val);
++ bnx2_write_phy(bp, 0x10, val & ~0x1);
++ }
++
++ /* ethernet at wirespeed */
++ bnx2_write_phy(bp, 0x18, 0x7007);
++ bnx2_read_phy(bp, 0x18, &val);
++ bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
++ return 0;
++}
++
++
++static int
++bnx2_init_phy(struct bnx2 *bp)
++{
++ u32 val;
++ int rc = 0;
++
++ bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
++ bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
++
++ REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
++
++ bnx2_reset_phy(bp);
++
++ bnx2_read_phy(bp, MII_PHYSID1, &val);
++ bp->phy_id = val << 16;
++ bnx2_read_phy(bp, MII_PHYSID2, &val);
++ bp->phy_id |= val & 0xffff;
++
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ if (CHIP_NUM(bp) == CHIP_NUM_5706)
++ rc = bnx2_init_5706s_phy(bp);
++ else if (CHIP_NUM(bp) == CHIP_NUM_5708)
++ rc = bnx2_init_5708s_phy(bp);
++ }
++ else {
++ rc = bnx2_init_copper_phy(bp);
++ }
++
++ bnx2_setup_phy(bp);
++
++ return rc;
++}
++
++static int
++bnx2_set_mac_loopback(struct bnx2 *bp)
++{
++ u32 mac_mode;
++
++ mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
++ mac_mode &= ~BNX2_EMAC_MODE_PORT;
++ mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
++ REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
++ bp->link_up = 1;
++ return 0;
++}
++
++static int bnx2_test_link(struct bnx2 *);
++
++static int
++bnx2_set_phy_loopback(struct bnx2 *bp)
++{
++ u32 mac_mode;
++ int rc, i;
++
++ spin_lock_bh(&bp->phy_lock);
++ rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
++ BMCR_SPEED1000);
++ spin_unlock_bh(&bp->phy_lock);
++ if (rc)
++ return rc;
++
++ for (i = 0; i < 10; i++) {
++ if (bnx2_test_link(bp) == 0)
++ break;
++ udelay(10);
++ }
++
++ mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
++ mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
++ BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
++ BNX2_EMAC_MODE_25G);
++
++ mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
++ REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
++ bp->link_up = 1;
++ return 0;
++}
++
++static int
++bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
++{
++ int i;
++ u32 val;
++
++ bp->fw_wr_seq++;
++ msg_data |= bp->fw_wr_seq;
++
++ REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
++
++ /* wait for an acknowledgement. */
++ for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
++ msleep(10);
++
++ val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
++
++ if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
++ break;
++ }
++ if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
++ return 0;
++
++ /* If we timed out, inform the firmware that this is the case. */
++ if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
++ if (!silent)
++ printk(KERN_ERR PFX "fw sync timeout, reset code = "
++ "%x\n", msg_data);
++
++ msg_data &= ~BNX2_DRV_MSG_CODE;
++ msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
++
++ REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
++
++ return -EBUSY;
++ }
++
++ if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
++ return -EIO;
++
++ return 0;
++}
++
++static void
++bnx2_init_context(struct bnx2 *bp)
++{
++ u32 vcid;
++
++ vcid = 96;
++ while (vcid) {
++ u32 vcid_addr, pcid_addr, offset;
++
++ vcid--;
++
++ if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
++ u32 new_vcid;
++
++ vcid_addr = GET_PCID_ADDR(vcid);
++ if (vcid & 0x8) {
++ new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
++ }
++ else {
++ new_vcid = vcid;
++ }
++ pcid_addr = GET_PCID_ADDR(new_vcid);
++ }
++ else {
++ vcid_addr = GET_CID_ADDR(vcid);
++ pcid_addr = vcid_addr;
++ }
++
++ REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
++ REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
++
++ /* Zero out the context. */
++ for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
++ CTX_WR(bp, 0x00, offset, 0);
++ }
++
++ REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
++ REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
++ }
++}
++
++static int
++bnx2_alloc_bad_rbuf(struct bnx2 *bp)
++{
++ u16 *good_mbuf;
++ u32 good_mbuf_cnt;
++ u32 val;
++
++ good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
++ if (good_mbuf == NULL) {
++ printk(KERN_ERR PFX "Failed to allocate memory in "
++ "bnx2_alloc_bad_rbuf\n");
++ return -ENOMEM;
++ }
++
++ REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
++ BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
++
++ good_mbuf_cnt = 0;
++
++ /* Allocate a bunch of mbufs and save the good ones in an array. */
++ val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
++ while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
++ REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
++
++ val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
++
++ val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
++
++ /* The addresses with Bit 9 set are bad memory blocks. */
++ if (!(val & (1 << 9))) {
++ good_mbuf[good_mbuf_cnt] = (u16) val;
++ good_mbuf_cnt++;
++ }
++
++ val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
++ }
++
++ /* Free the good ones back to the mbuf pool thus discarding
++ * all the bad ones. */
++ while (good_mbuf_cnt) {
++ good_mbuf_cnt--;
++
++ val = good_mbuf[good_mbuf_cnt];
++ val = (val << 9) | val | 1;
++
++ REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
++ }
++ kfree(good_mbuf);
++ return 0;
++}
++
++static void
++bnx2_set_mac_addr(struct bnx2 *bp)
++{
++ u32 val;
++ u8 *mac_addr = bp->dev->dev_addr;
++
++ val = (mac_addr[0] << 8) | mac_addr[1];
++
++ REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
++
++ val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
++ (mac_addr[4] << 8) | mac_addr[5];
++
++ REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
++}
++
++static inline int
++bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
++{
++ struct sk_buff *skb;
++ struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
++ dma_addr_t mapping;
++ struct rx_bd *rxbd = &bp->rx_desc_ring[index];
++ unsigned long align;
++
++ skb = dev_alloc_skb(bp->rx_buf_size);
++ if (skb == NULL) {
++ return -ENOMEM;
++ }
++
++ if (unlikely((align = (unsigned long) skb->data & 0x7))) {
++ skb_reserve(skb, 8 - align);
++ }
++
++ skb->dev = bp->dev;
++ mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
++ PCI_DMA_FROMDEVICE);
++
++ rx_buf->skb = skb;
++ pci_unmap_addr_set(rx_buf, mapping, mapping);
++
++ rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
++ rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
++
++ bp->rx_prod_bseq += bp->rx_buf_use_size;
++
++ return 0;
++}
++
++static void
++bnx2_phy_int(struct bnx2 *bp)
++{
++ u32 new_link_state, old_link_state;
++
++ new_link_state = bp->status_blk->status_attn_bits &
++ STATUS_ATTN_BITS_LINK_STATE;
++ old_link_state = bp->status_blk->status_attn_bits_ack &
++ STATUS_ATTN_BITS_LINK_STATE;
++ if (new_link_state != old_link_state) {
++ if (new_link_state) {
++ REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
++ STATUS_ATTN_BITS_LINK_STATE);
++ }
++ else {
++ REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
++ STATUS_ATTN_BITS_LINK_STATE);
++ }
++ bnx2_set_link(bp);
++ }
++}
++
++static void
++bnx2_tx_int(struct bnx2 *bp)
++{
++ struct status_block *sblk = bp->status_blk;
++ u16 hw_cons, sw_cons, sw_ring_cons;
++ int tx_free_bd = 0;
++
++ hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
++ if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
++ hw_cons++;
++ }
++ sw_cons = bp->tx_cons;
++
++ while (sw_cons != hw_cons) {
++ struct sw_bd *tx_buf;
++ struct sk_buff *skb;
++ int i, last;
++
++ sw_ring_cons = TX_RING_IDX(sw_cons);
++
++ tx_buf = &bp->tx_buf_ring[sw_ring_cons];
++ skb = tx_buf->skb;
++#ifdef BCM_TSO
++ /* partial BD completions possible with TSO packets */
++ if (skb_shinfo(skb)->tso_size) {
++ u16 last_idx, last_ring_idx;
++
++ last_idx = sw_cons +
++ skb_shinfo(skb)->nr_frags + 1;
++ last_ring_idx = sw_ring_cons +
++ skb_shinfo(skb)->nr_frags + 1;
++ if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
++ last_idx++;
++ }
++ if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
++ break;
++ }
++ }
++#endif
++ pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
++ skb_headlen(skb), PCI_DMA_TODEVICE);
++
++ tx_buf->skb = NULL;
++ last = skb_shinfo(skb)->nr_frags;
++
++ for (i = 0; i < last; i++) {
++ sw_cons = NEXT_TX_BD(sw_cons);
++
++ pci_unmap_page(bp->pdev,
++ pci_unmap_addr(
++ &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
++ mapping),
++ skb_shinfo(skb)->frags[i].size,
++ PCI_DMA_TODEVICE);
++ }
++
++ sw_cons = NEXT_TX_BD(sw_cons);
++
++ tx_free_bd += last + 1;
++
++ dev_kfree_skb(skb);
++
++ hw_cons = bp->hw_tx_cons =
++ sblk->status_tx_quick_consumer_index0;
++
++ if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
++ hw_cons++;
++ }
++ }
++
++ bp->tx_cons = sw_cons;
++
++ if (unlikely(netif_queue_stopped(bp->dev))) {
++ spin_lock(&bp->tx_lock);
++ if ((netif_queue_stopped(bp->dev)) &&
++ (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
++
++ netif_wake_queue(bp->dev);
++ }
++ spin_unlock(&bp->tx_lock);
++ }
++}
++
++static inline void
++bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
++ u16 cons, u16 prod)
++{
++ struct sw_bd *cons_rx_buf, *prod_rx_buf;
++ struct rx_bd *cons_bd, *prod_bd;
++
++ cons_rx_buf = &bp->rx_buf_ring[cons];
++ prod_rx_buf = &bp->rx_buf_ring[prod];
++
++ pci_dma_sync_single_for_device(bp->pdev,
++ pci_unmap_addr(cons_rx_buf, mapping),
++ bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
++
++ bp->rx_prod_bseq += bp->rx_buf_use_size;
++
++ prod_rx_buf->skb = skb;
++
++ if (cons == prod)
++ return;
++
++ pci_unmap_addr_set(prod_rx_buf, mapping,
++ pci_unmap_addr(cons_rx_buf, mapping));
++
++ cons_bd = &bp->rx_desc_ring[cons];
++ prod_bd = &bp->rx_desc_ring[prod];
++ prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
++ prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
++}
++
++static int
++bnx2_rx_int(struct bnx2 *bp, int budget)
++{
++ struct status_block *sblk = bp->status_blk;
++ u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
++ struct l2_fhdr *rx_hdr;
++ int rx_pkt = 0;
++
++ hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
++ if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
++ hw_cons++;
++ }
++ sw_cons = bp->rx_cons;
++ sw_prod = bp->rx_prod;
++
++ /* Memory barrier necessary as speculative reads of the rx
++ * buffer can be ahead of the index in the status block
++ */
++ rmb();
++ while (sw_cons != hw_cons) {
++ unsigned int len;
++ u32 status;
++ struct sw_bd *rx_buf;
++ struct sk_buff *skb;
++ dma_addr_t dma_addr;
++
++ sw_ring_cons = RX_RING_IDX(sw_cons);
++ sw_ring_prod = RX_RING_IDX(sw_prod);
++
++ rx_buf = &bp->rx_buf_ring[sw_ring_cons];
++ skb = rx_buf->skb;
++
++ rx_buf->skb = NULL;
++
++ dma_addr = pci_unmap_addr(rx_buf, mapping);
++
++ pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
++ bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
++
++ rx_hdr = (struct l2_fhdr *) skb->data;
++ len = rx_hdr->l2_fhdr_pkt_len - 4;
++
++ if ((status = rx_hdr->l2_fhdr_status) &
++ (L2_FHDR_ERRORS_BAD_CRC |
++ L2_FHDR_ERRORS_PHY_DECODE |
++ L2_FHDR_ERRORS_ALIGNMENT |
++ L2_FHDR_ERRORS_TOO_SHORT |
++ L2_FHDR_ERRORS_GIANT_FRAME)) {
++
++ goto reuse_rx;
++ }
++
++ /* Since we don't have a jumbo ring, copy small packets
++ * if mtu > 1500
++ */
++ if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
++ struct sk_buff *new_skb;
++
++ new_skb = dev_alloc_skb(len + 2);
++ if (new_skb == NULL)
++ goto reuse_rx;
++
++ /* aligned copy */
++ memcpy(new_skb->data,
++ skb->data + bp->rx_offset - 2,
++ len + 2);
++
++ skb_reserve(new_skb, 2);
++ skb_put(new_skb, len);
++ new_skb->dev = bp->dev;
++
++ bnx2_reuse_rx_skb(bp, skb,
++ sw_ring_cons, sw_ring_prod);
++
++ skb = new_skb;
++ }
++ else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
++ pci_unmap_single(bp->pdev, dma_addr,
++ bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
++
++ skb_reserve(skb, bp->rx_offset);
++ skb_put(skb, len);
++ }
++ else {
++reuse_rx:
++ bnx2_reuse_rx_skb(bp, skb,
++ sw_ring_cons, sw_ring_prod);
++ goto next_rx;
++ }
++
++ skb->protocol = eth_type_trans(skb, bp->dev);
++
++ if ((len > (bp->dev->mtu + ETH_HLEN)) &&
++ (ntohs(skb->protocol) != 0x8100)) {
++
++ dev_kfree_skb(skb);
++ goto next_rx;
++
++ }
++
++ skb->ip_summed = CHECKSUM_NONE;
++ if (bp->rx_csum &&
++ (status & (L2_FHDR_STATUS_TCP_SEGMENT |
++ L2_FHDR_STATUS_UDP_DATAGRAM))) {
++
++ if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
++ L2_FHDR_ERRORS_UDP_XSUM)) == 0))
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ }
++
++#ifdef BCM_VLAN
++ if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
++ vlan_hwaccel_receive_skb(skb, bp->vlgrp,
++ rx_hdr->l2_fhdr_vlan_tag);
++ }
++ else
++#endif
++ netif_receive_skb(skb);
++
++ bp->dev->last_rx = jiffies;
++ rx_pkt++;
++
++next_rx:
++ sw_cons = NEXT_RX_BD(sw_cons);
++ sw_prod = NEXT_RX_BD(sw_prod);
++
++ if ((rx_pkt == budget))
++ break;
++
++ /* Refresh hw_cons to see if there is new work */
++ if (sw_cons == hw_cons) {
++ hw_cons = bp->hw_rx_cons =
++ sblk->status_rx_quick_consumer_index0;
++ if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
++ hw_cons++;
++ rmb();
++ }
++ }
++ bp->rx_cons = sw_cons;
++ bp->rx_prod = sw_prod;
++
++ REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
++
++ REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
++
++ mmiowb();
++
++ return rx_pkt;
++
++}
++
++/* MSI ISR - The only difference between this and the INTx ISR
++ * is that the MSI interrupt is always serviced.
++ */
++static irqreturn_t
++bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
++{
++ struct net_device *dev = dev_instance;
++ struct bnx2 *bp = netdev_priv(dev);
++
++ prefetch(bp->status_blk);
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
++
++ /* Return here if interrupt is disabled. */
++ if (unlikely(atomic_read(&bp->intr_sem) != 0))
++ return IRQ_HANDLED;
++
++ netif_rx_schedule(dev);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t
++bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
++{
++ struct net_device *dev = dev_instance;
++ struct bnx2 *bp = netdev_priv(dev);
++
++ /* When using INTx, it is possible for the interrupt to arrive
++ * at the CPU before the status block posted prior to the
++ * interrupt. Reading a register will flush the status block.
++ * When using MSI, the MSI message will always complete after
++ * the status block write.
++ */
++ if ((bp->status_blk->status_idx == bp->last_status_idx) &&
++ (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
++ BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
++ return IRQ_NONE;
++
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
++
++ /* Return here if interrupt is shared and is disabled. */
++ if (unlikely(atomic_read(&bp->intr_sem) != 0))
++ return IRQ_HANDLED;
++
++ netif_rx_schedule(dev);
++
++ return IRQ_HANDLED;
++}
++
++static inline int
++bnx2_has_work(struct bnx2 *bp)
++{
++ struct status_block *sblk = bp->status_blk;
++
++ if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
++ (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
++ return 1;
++
++ if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
++ bp->link_up)
++ return 1;
++
++ return 0;
++}
++
++static int
++bnx2_poll(struct net_device *dev, int *budget)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if ((bp->status_blk->status_attn_bits &
++ STATUS_ATTN_BITS_LINK_STATE) !=
++ (bp->status_blk->status_attn_bits_ack &
++ STATUS_ATTN_BITS_LINK_STATE)) {
++
++ spin_lock(&bp->phy_lock);
++ bnx2_phy_int(bp);
++ spin_unlock(&bp->phy_lock);
++
++ /* This is needed to take care of transient status
++ * during link changes.
++ */
++ REG_WR(bp, BNX2_HC_COMMAND,
++ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
++ REG_RD(bp, BNX2_HC_COMMAND);
++ }
++
++ if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
++ bnx2_tx_int(bp);
++
++ if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
++ int orig_budget = *budget;
++ int work_done;
++
++ if (orig_budget > dev->quota)
++ orig_budget = dev->quota;
++
++ work_done = bnx2_rx_int(bp, orig_budget);
++ *budget -= work_done;
++ dev->quota -= work_done;
++ }
++
++ bp->last_status_idx = bp->status_blk->status_idx;
++ rmb();
++
++ if (!bnx2_has_work(bp)) {
++ netif_rx_complete(dev);
++ if (likely(bp->flags & USING_MSI_FLAG)) {
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
++ bp->last_status_idx);
++ return 0;
++ }
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
++ BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
++ bp->last_status_idx);
++
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
++ BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
++ bp->last_status_idx);
++ return 0;
++ }
++
++ return 1;
++}
++
++/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
++ * from set_multicast.
++ */
++static void
++bnx2_set_rx_mode(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ u32 rx_mode, sort_mode;
++ int i;
++
++ spin_lock_bh(&bp->phy_lock);
++
++ rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
++ BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
++ sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
++#ifdef BCM_VLAN
++ if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
++ rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
++#else
++ if (!(bp->flags & ASF_ENABLE_FLAG))
++ rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
++#endif
++ if (dev->flags & IFF_PROMISC) {
++ /* Promiscuous mode. */
++ rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
++ sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
++ }
++ else if (dev->flags & IFF_ALLMULTI) {
++ for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
++ REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
++ 0xffffffff);
++ }
++ sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
++ }
++ else {
++ /* Accept one or more multicast(s). */
++ struct dev_mc_list *mclist;
++ u32 mc_filter[NUM_MC_HASH_REGISTERS];
++ u32 regidx;
++ u32 bit;
++ u32 crc;
++
++ memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
++
++ for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
++ i++, mclist = mclist->next) {
++
++ crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
++ bit = crc & 0xff;
++ regidx = (bit & 0xe0) >> 5;
++ bit &= 0x1f;
++ mc_filter[regidx] |= (1 << bit);
++ }
++
++ for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
++ REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
++ mc_filter[i]);
++ }
++
++ sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
++ }
++
++ if (rx_mode != bp->rx_mode) {
++ bp->rx_mode = rx_mode;
++ REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
++ }
++
++ REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
++ REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
++ REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
++
++ spin_unlock_bh(&bp->phy_lock);
++}
++
++#define FW_BUF_SIZE 0x8000
++
++static int
++bnx2_gunzip_init(struct bnx2 *bp)
++{
++ if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
++ goto gunzip_nomem1;
++
++ if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
++ goto gunzip_nomem2;
++
++ bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
++ if (bp->strm->workspace == NULL)
++ goto gunzip_nomem3;
++
++ return 0;
++
++gunzip_nomem3:
++ kfree(bp->strm);
++ bp->strm = NULL;
++
++gunzip_nomem2:
++ vfree(bp->gunzip_buf);
++ bp->gunzip_buf = NULL;
++
++gunzip_nomem1:
++ printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
++ "uncompression.\n", bp->dev->name);
++ return -ENOMEM;
++}
++
++static void
++bnx2_gunzip_end(struct bnx2 *bp)
++{
++ kfree(bp->strm->workspace);
++
++ kfree(bp->strm);
++ bp->strm = NULL;
++
++ if (bp->gunzip_buf) {
++ vfree(bp->gunzip_buf);
++ bp->gunzip_buf = NULL;
++ }
++}
++
++static int
++bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
++{
++ int n, rc;
++
++ /* check gzip header */
++ if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
++ return -EINVAL;
++
++ n = 10;
++
++#define FNAME 0x8
++ if (zbuf[3] & FNAME)
++ while ((zbuf[n++] != 0) && (n < len));
++
++ bp->strm->next_in = zbuf + n;
++ bp->strm->avail_in = len - n;
++ bp->strm->next_out = bp->gunzip_buf;
++ bp->strm->avail_out = FW_BUF_SIZE;
++
++ rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
++ if (rc != Z_OK)
++ return rc;
++
++ rc = zlib_inflate(bp->strm, Z_FINISH);
++
++ *outlen = FW_BUF_SIZE - bp->strm->avail_out;
++ *outbuf = bp->gunzip_buf;
++
++ if ((rc != Z_OK) && (rc != Z_STREAM_END))
++ printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
++ bp->dev->name, bp->strm->msg);
++
++ zlib_inflateEnd(bp->strm);
++
++ if (rc == Z_STREAM_END)
++ return 0;
++
++ return rc;
++}
++
++static void
++load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
++ u32 rv2p_proc)
++{
++ int i;
++ u32 val;
++
++
++ for (i = 0; i < rv2p_code_len; i += 8) {
++ REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
++ rv2p_code++;
++ REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
++ rv2p_code++;
++
++ if (rv2p_proc == RV2P_PROC1) {
++ val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
++ REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
++ }
++ else {
++ val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
++ REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
++ }
++ }
++
++ /* Reset the processor, un-stall is done later. */
++ if (rv2p_proc == RV2P_PROC1) {
++ REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
++ }
++ else {
++ REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
++ }
++}
++
++static void
++load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
++{
++ u32 offset;
++ u32 val;
++
++ /* Halt the CPU. */
++ val = REG_RD_IND(bp, cpu_reg->mode);
++ val |= cpu_reg->mode_value_halt;
++ REG_WR_IND(bp, cpu_reg->mode, val);
++ REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
++
++ /* Load the Text area. */
++ offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
++ if (fw->text) {
++ int j;
++
++ for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
++ REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
++ }
++ }
++
++ /* Load the Data area. */
++ offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
++ if (fw->data) {
++ int j;
++
++ for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
++ REG_WR_IND(bp, offset, fw->data[j]);
++ }
++ }
++
++ /* Load the SBSS area. */
++ offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
++ if (fw->sbss) {
++ int j;
++
++ for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
++ REG_WR_IND(bp, offset, fw->sbss[j]);
++ }
++ }
++
++ /* Load the BSS area. */
++ offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
++ if (fw->bss) {
++ int j;
++
++ for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
++ REG_WR_IND(bp, offset, fw->bss[j]);
++ }
++ }
++
++ /* Load the Read-Only area. */
++ offset = cpu_reg->spad_base +
++ (fw->rodata_addr - cpu_reg->mips_view_base);
++ if (fw->rodata) {
++ int j;
++
++ for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
++ REG_WR_IND(bp, offset, fw->rodata[j]);
++ }
++ }
++
++ /* Clear the pre-fetch instruction. */
++ REG_WR_IND(bp, cpu_reg->inst, 0);
++ REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
++
++ /* Start the CPU. */
++ val = REG_RD_IND(bp, cpu_reg->mode);
++ val &= ~cpu_reg->mode_value_halt;
++ REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
++ REG_WR_IND(bp, cpu_reg->mode, val);
++}
++
++static int
++bnx2_init_cpus(struct bnx2 *bp)
++{
++ struct cpu_reg cpu_reg;
++ struct fw_info fw;
++ int rc = 0;
++ void *text;
++ u32 text_len;
++
++ if ((rc = bnx2_gunzip_init(bp)) != 0)
++ return rc;
++
++ /* Initialize the RV2P processor. */
++ rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
++ &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
++
++ rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
++ &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
++
++ /* Initialize the RX Processor. */
++ cpu_reg.mode = BNX2_RXP_CPU_MODE;
++ cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
++ cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
++ cpu_reg.state = BNX2_RXP_CPU_STATE;
++ cpu_reg.state_value_clear = 0xffffff;
++ cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
++ cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
++ cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
++ cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
++ cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
++ cpu_reg.spad_base = BNX2_RXP_SCRATCH;
++ cpu_reg.mips_view_base = 0x8000000;
++
++ fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
++ fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
++ fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
++ fw.start_addr = bnx2_RXP_b06FwStartAddr;
++
++ fw.text_addr = bnx2_RXP_b06FwTextAddr;
++ fw.text_len = bnx2_RXP_b06FwTextLen;
++ fw.text_index = 0;
++
++ rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
++ &text, &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ fw.text = text;
++
++ fw.data_addr = bnx2_RXP_b06FwDataAddr;
++ fw.data_len = bnx2_RXP_b06FwDataLen;
++ fw.data_index = 0;
++ fw.data = bnx2_RXP_b06FwData;
++
++ fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
++ fw.sbss_len = bnx2_RXP_b06FwSbssLen;
++ fw.sbss_index = 0;
++ fw.sbss = bnx2_RXP_b06FwSbss;
++
++ fw.bss_addr = bnx2_RXP_b06FwBssAddr;
++ fw.bss_len = bnx2_RXP_b06FwBssLen;
++ fw.bss_index = 0;
++ fw.bss = bnx2_RXP_b06FwBss;
++
++ fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
++ fw.rodata_len = bnx2_RXP_b06FwRodataLen;
++ fw.rodata_index = 0;
++ fw.rodata = bnx2_RXP_b06FwRodata;
++
++ load_cpu_fw(bp, &cpu_reg, &fw);
++
++ /* Initialize the TX Processor. */
++ cpu_reg.mode = BNX2_TXP_CPU_MODE;
++ cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
++ cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
++ cpu_reg.state = BNX2_TXP_CPU_STATE;
++ cpu_reg.state_value_clear = 0xffffff;
++ cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
++ cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
++ cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
++ cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
++ cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
++ cpu_reg.spad_base = BNX2_TXP_SCRATCH;
++ cpu_reg.mips_view_base = 0x8000000;
++
++ fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
++ fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
++ fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
++ fw.start_addr = bnx2_TXP_b06FwStartAddr;
++
++ fw.text_addr = bnx2_TXP_b06FwTextAddr;
++ fw.text_len = bnx2_TXP_b06FwTextLen;
++ fw.text_index = 0;
++
++ rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
++ &text, &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ fw.text = text;
++
++ fw.data_addr = bnx2_TXP_b06FwDataAddr;
++ fw.data_len = bnx2_TXP_b06FwDataLen;
++ fw.data_index = 0;
++ fw.data = bnx2_TXP_b06FwData;
++
++ fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
++ fw.sbss_len = bnx2_TXP_b06FwSbssLen;
++ fw.sbss_index = 0;
++ fw.sbss = bnx2_TXP_b06FwSbss;
++
++ fw.bss_addr = bnx2_TXP_b06FwBssAddr;
++ fw.bss_len = bnx2_TXP_b06FwBssLen;
++ fw.bss_index = 0;
++ fw.bss = bnx2_TXP_b06FwBss;
++
++ fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
++ fw.rodata_len = bnx2_TXP_b06FwRodataLen;
++ fw.rodata_index = 0;
++ fw.rodata = bnx2_TXP_b06FwRodata;
++
++ load_cpu_fw(bp, &cpu_reg, &fw);
++
++ /* Initialize the TX Patch-up Processor. */
++ cpu_reg.mode = BNX2_TPAT_CPU_MODE;
++ cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
++ cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
++ cpu_reg.state = BNX2_TPAT_CPU_STATE;
++ cpu_reg.state_value_clear = 0xffffff;
++ cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
++ cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
++ cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
++ cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
++ cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
++ cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
++ cpu_reg.mips_view_base = 0x8000000;
++
++ fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
++ fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
++ fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
++ fw.start_addr = bnx2_TPAT_b06FwStartAddr;
++
++ fw.text_addr = bnx2_TPAT_b06FwTextAddr;
++ fw.text_len = bnx2_TPAT_b06FwTextLen;
++ fw.text_index = 0;
++
++ rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
++ &text, &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ fw.text = text;
++
++ fw.data_addr = bnx2_TPAT_b06FwDataAddr;
++ fw.data_len = bnx2_TPAT_b06FwDataLen;
++ fw.data_index = 0;
++ fw.data = bnx2_TPAT_b06FwData;
++
++ fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
++ fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
++ fw.sbss_index = 0;
++ fw.sbss = bnx2_TPAT_b06FwSbss;
++
++ fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
++ fw.bss_len = bnx2_TPAT_b06FwBssLen;
++ fw.bss_index = 0;
++ fw.bss = bnx2_TPAT_b06FwBss;
++
++ fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
++ fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
++ fw.rodata_index = 0;
++ fw.rodata = bnx2_TPAT_b06FwRodata;
++
++ load_cpu_fw(bp, &cpu_reg, &fw);
++
++ /* Initialize the Completion Processor. */
++ cpu_reg.mode = BNX2_COM_CPU_MODE;
++ cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
++ cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
++ cpu_reg.state = BNX2_COM_CPU_STATE;
++ cpu_reg.state_value_clear = 0xffffff;
++ cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
++ cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
++ cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
++ cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
++ cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
++ cpu_reg.spad_base = BNX2_COM_SCRATCH;
++ cpu_reg.mips_view_base = 0x8000000;
++
++ fw.ver_major = bnx2_COM_b06FwReleaseMajor;
++ fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
++ fw.ver_fix = bnx2_COM_b06FwReleaseFix;
++ fw.start_addr = bnx2_COM_b06FwStartAddr;
++
++ fw.text_addr = bnx2_COM_b06FwTextAddr;
++ fw.text_len = bnx2_COM_b06FwTextLen;
++ fw.text_index = 0;
++
++ rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
++ &text, &text_len);
++ if (rc)
++ goto init_cpu_err;
++
++ fw.text = text;
++
++ fw.data_addr = bnx2_COM_b06FwDataAddr;
++ fw.data_len = bnx2_COM_b06FwDataLen;
++ fw.data_index = 0;
++ fw.data = bnx2_COM_b06FwData;
++
++ fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
++ fw.sbss_len = bnx2_COM_b06FwSbssLen;
++ fw.sbss_index = 0;
++ fw.sbss = bnx2_COM_b06FwSbss;
++
++ fw.bss_addr = bnx2_COM_b06FwBssAddr;
++ fw.bss_len = bnx2_COM_b06FwBssLen;
++ fw.bss_index = 0;
++ fw.bss = bnx2_COM_b06FwBss;
++
++ fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
++ fw.rodata_len = bnx2_COM_b06FwRodataLen;
++ fw.rodata_index = 0;
++ fw.rodata = bnx2_COM_b06FwRodata;
++
++ load_cpu_fw(bp, &cpu_reg, &fw);
++
++init_cpu_err:
++ bnx2_gunzip_end(bp);
++ return rc;
++}
++
++static int
++bnx2_set_power_state(struct bnx2 *bp, int state)
++{
++ u16 pmcsr;
++
++ pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
++
++ switch (state) {
++ case 0: {
++ u32 val;
++
++ pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
++ (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
++ PCI_PM_CTRL_PME_STATUS);
++
++ if (pmcsr & PCI_PM_CTRL_STATE_MASK)
++ /* delay required during transition out of D3hot */
++ msleep(20);
++
++ val = REG_RD(bp, BNX2_EMAC_MODE);
++ val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
++ val &= ~BNX2_EMAC_MODE_MPKT;
++ REG_WR(bp, BNX2_EMAC_MODE, val);
++
++ val = REG_RD(bp, BNX2_RPM_CONFIG);
++ val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
++ REG_WR(bp, BNX2_RPM_CONFIG, val);
++ break;
++ }
++ case 3: {
++ int i;
++ u32 val, wol_msg;
++
++ if (bp->wol) {
++ u32 advertising;
++ u8 autoneg;
++
++ autoneg = bp->autoneg;
++ advertising = bp->advertising;
++
++ bp->autoneg = AUTONEG_SPEED;
++ bp->advertising = ADVERTISED_10baseT_Half |
++ ADVERTISED_10baseT_Full |
++ ADVERTISED_100baseT_Half |
++ ADVERTISED_100baseT_Full |
++ ADVERTISED_Autoneg;
++
++ bnx2_setup_copper_phy(bp);
++
++ bp->autoneg = autoneg;
++ bp->advertising = advertising;
++
++ bnx2_set_mac_addr(bp);
++
++ val = REG_RD(bp, BNX2_EMAC_MODE);
++
++ /* Enable port mode. */
++ val &= ~BNX2_EMAC_MODE_PORT;
++ val |= BNX2_EMAC_MODE_PORT_MII |
++ BNX2_EMAC_MODE_MPKT_RCVD |
++ BNX2_EMAC_MODE_ACPI_RCVD |
++ BNX2_EMAC_MODE_MPKT;
++
++ REG_WR(bp, BNX2_EMAC_MODE, val);
++
++ /* receive all multicast */
++ for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
++ REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
++ 0xffffffff);
++ }
++ REG_WR(bp, BNX2_EMAC_RX_MODE,
++ BNX2_EMAC_RX_MODE_SORT_MODE);
++
++ val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
++ BNX2_RPM_SORT_USER0_MC_EN;
++ REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
++ REG_WR(bp, BNX2_RPM_SORT_USER0, val);
++ REG_WR(bp, BNX2_RPM_SORT_USER0, val |
++ BNX2_RPM_SORT_USER0_ENA);
++
++ /* Need to enable EMAC and RPM for WOL. */
++ REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
++ BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
++ BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
++ BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
++
++ val = REG_RD(bp, BNX2_RPM_CONFIG);
++ val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
++ REG_WR(bp, BNX2_RPM_CONFIG, val);
++
++ wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
++ }
++ else {
++ wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
++ }
++
++ if (!(bp->flags & NO_WOL_FLAG))
++ bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
++
++ pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
++ if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
++ (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
++
++ if (bp->wol)
++ pmcsr |= 3;
++ }
++ else {
++ pmcsr |= 3;
++ }
++ if (bp->wol) {
++ pmcsr |= PCI_PM_CTRL_PME_ENABLE;
++ }
++ pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
++ pmcsr);
++
++ /* No more memory access after this point until
++ * device is brought back to D0.
++ */
++ udelay(50);
++ break;
++ }
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int
++bnx2_acquire_nvram_lock(struct bnx2 *bp)
++{
++ u32 val;
++ int j;
++
++ /* Request access to the flash interface. */
++ REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ val = REG_RD(bp, BNX2_NVM_SW_ARB);
++ if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
++ break;
++
++ udelay(5);
++ }
++
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++
++ return 0;
++}
++
++static int
++bnx2_release_nvram_lock(struct bnx2 *bp)
++{
++ int j;
++ u32 val;
++
++ /* Relinquish nvram interface. */
++ REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
++
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ val = REG_RD(bp, BNX2_NVM_SW_ARB);
++ if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
++ break;
++
++ udelay(5);
++ }
++
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++
++ return 0;
++}
++
++
++static int
++bnx2_enable_nvram_write(struct bnx2 *bp)
++{
++ u32 val;
++
++ val = REG_RD(bp, BNX2_MISC_CFG);
++ REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
++
++ if (!bp->flash_info->buffered) {
++ int j;
++
++ REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
++ REG_WR(bp, BNX2_NVM_COMMAND,
++ BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
++
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ udelay(5);
++
++ val = REG_RD(bp, BNX2_NVM_COMMAND);
++ if (val & BNX2_NVM_COMMAND_DONE)
++ break;
++ }
++
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++ }
++ return 0;
++}
++
++static void
++bnx2_disable_nvram_write(struct bnx2 *bp)
++{
++ u32 val;
++
++ val = REG_RD(bp, BNX2_MISC_CFG);
++ REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
++}
++
++
++static void
++bnx2_enable_nvram_access(struct bnx2 *bp)
++{
++ u32 val;
++
++ val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
++ /* Enable both bits, even on read. */
++ REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
++ val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
++}
++
++static void
++bnx2_disable_nvram_access(struct bnx2 *bp)
++{
++ u32 val;
++
++ val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
++ /* Disable both bits, even after read. */
++ REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
++ val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
++ BNX2_NVM_ACCESS_ENABLE_WR_EN));
++}
++
++static int
++bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
++{
++ u32 cmd;
++ int j;
++
++ if (bp->flash_info->buffered)
++ /* Buffered flash, no erase needed */
++ return 0;
++
++ /* Build an erase command */
++ cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
++ BNX2_NVM_COMMAND_DOIT;
++
++ /* Need to clear DONE bit separately. */
++ REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
++
++ /* Address of the NVRAM to read from. */
++ REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
++
++ /* Issue an erase command. */
++ REG_WR(bp, BNX2_NVM_COMMAND, cmd);
++
++ /* Wait for completion. */
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ u32 val;
++
++ udelay(5);
++
++ val = REG_RD(bp, BNX2_NVM_COMMAND);
++ if (val & BNX2_NVM_COMMAND_DONE)
++ break;
++ }
++
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++
++ return 0;
++}
++
++static int
++bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
++{
++ u32 cmd;
++ int j;
++
++ /* Build the command word. */
++ cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
++
++ /* Calculate an offset of a buffered flash. */
++ if (bp->flash_info->buffered) {
++ offset = ((offset / bp->flash_info->page_size) <<
++ bp->flash_info->page_bits) +
++ (offset % bp->flash_info->page_size);
++ }
++
++ /* Need to clear DONE bit separately. */
++ REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
++
++ /* Address of the NVRAM to read from. */
++ REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
++
++ /* Issue a read command. */
++ REG_WR(bp, BNX2_NVM_COMMAND, cmd);
++
++ /* Wait for completion. */
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ u32 val;
++
++ udelay(5);
++
++ val = REG_RD(bp, BNX2_NVM_COMMAND);
++ if (val & BNX2_NVM_COMMAND_DONE) {
++ val = REG_RD(bp, BNX2_NVM_READ);
++
++ val = be32_to_cpu(val);
++ memcpy(ret_val, &val, 4);
++ break;
++ }
++ }
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++
++ return 0;
++}
++
++
++static int
++bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
++{
++ u32 cmd, val32;
++ int j;
++
++ /* Build the command word. */
++ cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
++
++ /* Calculate an offset of a buffered flash. */
++ if (bp->flash_info->buffered) {
++ offset = ((offset / bp->flash_info->page_size) <<
++ bp->flash_info->page_bits) +
++ (offset % bp->flash_info->page_size);
++ }
++
++ /* Need to clear DONE bit separately. */
++ REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
++
++ memcpy(&val32, val, 4);
++ val32 = cpu_to_be32(val32);
++
++ /* Write the data. */
++ REG_WR(bp, BNX2_NVM_WRITE, val32);
++
++ /* Address of the NVRAM to write to. */
++ REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
++
++ /* Issue the write command. */
++ REG_WR(bp, BNX2_NVM_COMMAND, cmd);
++
++ /* Wait for completion. */
++ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
++ udelay(5);
++
++ if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
++ break;
++ }
++ if (j >= NVRAM_TIMEOUT_COUNT)
++ return -EBUSY;
++
++ return 0;
++}
++
++static int
++bnx2_init_nvram(struct bnx2 *bp)
++{
++ u32 val;
++ int j, entry_count, rc;
++ struct flash_spec *flash;
++
++ /* Determine the selected interface. */
++ val = REG_RD(bp, BNX2_NVM_CFG1);
++
++ entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
++
++ rc = 0;
++ if (val & 0x40000000) {
++
++ /* Flash interface has been reconfigured */
++ for (j = 0, flash = &flash_table[0]; j < entry_count;
++ j++, flash++) {
++ if ((val & FLASH_BACKUP_STRAP_MASK) ==
++ (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
++ bp->flash_info = flash;
++ break;
++ }
++ }
++ }
++ else {
++ u32 mask;
++ /* Not yet been reconfigured */
++
++ if (val & (1 << 23))
++ mask = FLASH_BACKUP_STRAP_MASK;
++ else
++ mask = FLASH_STRAP_MASK;
++
++ for (j = 0, flash = &flash_table[0]; j < entry_count;
++ j++, flash++) {
++
++ if ((val & mask) == (flash->strapping & mask)) {
++ bp->flash_info = flash;
++
++ /* Request access to the flash interface. */
++ if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
++ return rc;
++
++ /* Enable access to flash interface */
++ bnx2_enable_nvram_access(bp);
++
++ /* Reconfigure the flash interface */
++ REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
++ REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
++ REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
++ REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
++
++ /* Disable access to flash interface */
++ bnx2_disable_nvram_access(bp);
++ bnx2_release_nvram_lock(bp);
++
++ break;
++ }
++ }
++ } /* if (val & 0x40000000) */
++
++ if (j == entry_count) {
++ bp->flash_info = NULL;
++ printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
++ return -ENODEV;
++ }
++
++ val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
++ val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
++ if (val)
++ bp->flash_size = val;
++ else
++ bp->flash_size = bp->flash_info->total_size;
++
++ return rc;
++}
++
++static int
++bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
++ int buf_size)
++{
++ int rc = 0;
++ u32 cmd_flags, offset32, len32, extra;
++
++ if (buf_size == 0)
++ return 0;
++
++ /* Request access to the flash interface. */
++ if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
++ return rc;
++
++ /* Enable access to flash interface */
++ bnx2_enable_nvram_access(bp);
++
++ len32 = buf_size;
++ offset32 = offset;
++ extra = 0;
++
++ cmd_flags = 0;
++
++ if (offset32 & 3) {
++ u8 buf[4];
++ u32 pre_len;
++
++ offset32 &= ~3;
++ pre_len = 4 - (offset & 3);
++
++ if (pre_len >= len32) {
++ pre_len = len32;
++ cmd_flags = BNX2_NVM_COMMAND_FIRST |
++ BNX2_NVM_COMMAND_LAST;
++ }
++ else {
++ cmd_flags = BNX2_NVM_COMMAND_FIRST;
++ }
++
++ rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
++
++ if (rc)
++ return rc;
++
++ memcpy(ret_buf, buf + (offset & 3), pre_len);
++
++ offset32 += 4;
++ ret_buf += pre_len;
++ len32 -= pre_len;
++ }
++ if (len32 & 3) {
++ extra = 4 - (len32 & 3);
++ len32 = (len32 + 4) & ~3;
++ }
++
++ if (len32 == 4) {
++ u8 buf[4];
++
++ if (cmd_flags)
++ cmd_flags = BNX2_NVM_COMMAND_LAST;
++ else
++ cmd_flags = BNX2_NVM_COMMAND_FIRST |
++ BNX2_NVM_COMMAND_LAST;
++
++ rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
++
++ memcpy(ret_buf, buf, 4 - extra);
++ }
++ else if (len32 > 0) {
++ u8 buf[4];
++
++ /* Read the first word. */
++ if (cmd_flags)
++ cmd_flags = 0;
++ else
++ cmd_flags = BNX2_NVM_COMMAND_FIRST;
++
++ rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
++
++ /* Advance to the next dword. */
++ offset32 += 4;
++ ret_buf += 4;
++ len32 -= 4;
++
++ while (len32 > 4 && rc == 0) {
++ rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
++
++ /* Advance to the next dword. */
++ offset32 += 4;
++ ret_buf += 4;
++ len32 -= 4;
++ }
++
++ if (rc)
++ return rc;
++
++ cmd_flags = BNX2_NVM_COMMAND_LAST;
++ rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
++
++ memcpy(ret_buf, buf, 4 - extra);
++ }
++
++ /* Disable access to flash interface */
++ bnx2_disable_nvram_access(bp);
++
++ bnx2_release_nvram_lock(bp);
++
++ return rc;
++}
++
++static int
++bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
++ int buf_size)
++{
++ u32 written, offset32, len32;
++ u8 *buf, start[4], end[4], *flash_buffer = NULL;
++ int rc = 0;
++ int align_start, align_end;
++
++ buf = data_buf;
++ offset32 = offset;
++ len32 = buf_size;
++ align_start = align_end = 0;
++
++ if ((align_start = (offset32 & 3))) {
++ offset32 &= ~3;
++ len32 += align_start;
++ if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
++ return rc;
++ }
++
++ if (len32 & 3) {
++ if ((len32 > 4) || !align_start) {
++ align_end = 4 - (len32 & 3);
++ len32 += align_end;
++ if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
++ end, 4))) {
++ return rc;
++ }
++ }
++ }
++
++ if (align_start || align_end) {
++ buf = kmalloc(len32, GFP_KERNEL);
++ if (buf == 0)
++ return -ENOMEM;
++ if (align_start) {
++ memcpy(buf, start, 4);
++ }
++ if (align_end) {
++ memcpy(buf + len32 - 4, end, 4);
++ }
++ memcpy(buf + align_start, data_buf, buf_size);
++ }
++
++ if (bp->flash_info->buffered == 0) {
++ flash_buffer = kmalloc(264, GFP_KERNEL);
++ if (flash_buffer == NULL) {
++ rc = -ENOMEM;
++ goto nvram_write_end;
++ }
++ }
++
++ written = 0;
++ while ((written < len32) && (rc == 0)) {
++ u32 page_start, page_end, data_start, data_end;
++ u32 addr, cmd_flags;
++ int i;
++
++ /* Find the page_start addr */
++ page_start = offset32 + written;
++ page_start -= (page_start % bp->flash_info->page_size);
++ /* Find the page_end addr */
++ page_end = page_start + bp->flash_info->page_size;
++ /* Find the data_start addr */
++ data_start = (written == 0) ? offset32 : page_start;
++ /* Find the data_end addr */
++ data_end = (page_end > offset32 + len32) ?
++ (offset32 + len32) : page_end;
++
++ /* Request access to the flash interface. */
++ if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
++ goto nvram_write_end;
++
++ /* Enable access to flash interface */
++ bnx2_enable_nvram_access(bp);
++
++ cmd_flags = BNX2_NVM_COMMAND_FIRST;
++ if (bp->flash_info->buffered == 0) {
++ int j;
++
++ /* Read the whole page into the buffer
++ * (non-buffer flash only) */
++ for (j = 0; j < bp->flash_info->page_size; j += 4) {
++ if (j == (bp->flash_info->page_size - 4)) {
++ cmd_flags |= BNX2_NVM_COMMAND_LAST;
++ }
++ rc = bnx2_nvram_read_dword(bp,
++ page_start + j,
++ &flash_buffer[j],
++ cmd_flags);
++
++ if (rc)
++ goto nvram_write_end;
++
++ cmd_flags = 0;
++ }
++ }
++
++ /* Enable writes to flash interface (unlock write-protect) */
++ if ((rc = bnx2_enable_nvram_write(bp)) != 0)
++ goto nvram_write_end;
++
++ /* Erase the page */
++ if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
++ goto nvram_write_end;
++
++ /* Re-enable the write again for the actual write */
++ bnx2_enable_nvram_write(bp);
++
++ /* Loop to write back the buffer data from page_start to
++ * data_start */
++ i = 0;
++ if (bp->flash_info->buffered == 0) {
++ for (addr = page_start; addr < data_start;
++ addr += 4, i += 4) {
++
++ rc = bnx2_nvram_write_dword(bp, addr,
++ &flash_buffer[i], cmd_flags);
++
++ if (rc != 0)
++ goto nvram_write_end;
++
++ cmd_flags = 0;
++ }
++ }
++
++ /* Loop to write the new data from data_start to data_end */
++ for (addr = data_start; addr < data_end; addr += 4, i += 4) {
++ if ((addr == page_end - 4) ||
++ ((bp->flash_info->buffered) &&
++ (addr == data_end - 4))) {
++
++ cmd_flags |= BNX2_NVM_COMMAND_LAST;
++ }
++ rc = bnx2_nvram_write_dword(bp, addr, buf,
++ cmd_flags);
++
++ if (rc != 0)
++ goto nvram_write_end;
++
++ cmd_flags = 0;
++ buf += 4;
++ }
++
++ /* Loop to write back the buffer data from data_end
++ * to page_end */
++ if (bp->flash_info->buffered == 0) {
++ for (addr = data_end; addr < page_end;
++ addr += 4, i += 4) {
++
++ if (addr == page_end-4) {
++ cmd_flags = BNX2_NVM_COMMAND_LAST;
++ }
++ rc = bnx2_nvram_write_dword(bp, addr,
++ &flash_buffer[i], cmd_flags);
++
++ if (rc != 0)
++ goto nvram_write_end;
++
++ cmd_flags = 0;
++ }
++ }
++
++ /* Disable writes to flash interface (lock write-protect) */
++ bnx2_disable_nvram_write(bp);
++
++ /* Disable access to flash interface */
++ bnx2_disable_nvram_access(bp);
++ bnx2_release_nvram_lock(bp);
++
++ /* Increment written */
++ written += data_end - data_start;
++ }
++
++nvram_write_end:
++ if (bp->flash_info->buffered == 0)
++ kfree(flash_buffer);
++
++ if (align_start || align_end)
++ kfree(buf);
++ return rc;
++}
++
++static int
++bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
++{
++ u32 val;
++ int i, rc = 0;
++
++ /* Wait for the current PCI transaction to complete before
++ * issuing a reset. */
++ REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
++ BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
++ BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
++ BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
++ BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
++ val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
++ udelay(5);
++
++ /* Wait for the firmware to tell us it is ok to issue a reset. */
++ bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
++
++ /* Deposit a driver reset signature so the firmware knows that
++ * this is a soft reset. */
++ REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
++ BNX2_DRV_RESET_SIGNATURE_MAGIC);
++
++ /* Do a dummy read to force the chip to complete all current transaction
++ * before we issue a reset. */
++ val = REG_RD(bp, BNX2_MISC_ID);
++
++ val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
++ BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
++ BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
++
++ /* Chip reset. */
++ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
++
++ if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
++ (CHIP_ID(bp) == CHIP_ID_5706_A1))
++ msleep(15);
++
++ /* Reset takes approximate 30 usec */
++ for (i = 0; i < 10; i++) {
++ val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
++ if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
++ BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
++ break;
++ }
++ udelay(10);
++ }
++
++ if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
++ BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
++ printk(KERN_ERR PFX "Chip reset did not complete\n");
++ return -EBUSY;
++ }
++
++ /* Make sure byte swapping is properly configured. */
++ val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
++ if (val != 0x01020304) {
++ printk(KERN_ERR PFX "Chip not in correct endian mode\n");
++ return -ENODEV;
++ }
++
++ /* Wait for the firmware to finish its initialization. */
++ rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
++ if (rc)
++ return rc;
++
++ if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
++ /* Adjust the voltage regular to two steps lower. The default
++ * of this register is 0x0000000e. */
++ REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
++
++ /* Remove bad rbuf memory from the free pool. */
++ rc = bnx2_alloc_bad_rbuf(bp);
++ }
++
++ return rc;
++}
++
++static int
++bnx2_init_chip(struct bnx2 *bp)
++{
++ u32 val;
++ int rc;
++
++ /* Make sure the interrupt is not active. */
++ REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
++
++ val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
++ BNX2_DMA_CONFIG_DATA_WORD_SWAP |
++#ifdef __BIG_ENDIAN
++ BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
++#endif
++ BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
++ DMA_READ_CHANS << 12 |
++ DMA_WRITE_CHANS << 16;
++
++ val |= (0x2 << 20) | (1 << 11);
++
++ if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
++ val |= (1 << 23);
++
++ if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
++ (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
++ val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
++
++ REG_WR(bp, BNX2_DMA_CONFIG, val);
++
++ if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
++ val = REG_RD(bp, BNX2_TDMA_CONFIG);
++ val |= BNX2_TDMA_CONFIG_ONE_DMA;
++ REG_WR(bp, BNX2_TDMA_CONFIG, val);
++ }
++
++ if (bp->flags & PCIX_FLAG) {
++ u16 val16;
++
++ pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
++ &val16);
++ pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
++ val16 & ~PCI_X_CMD_ERO);
++ }
++
++ REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
++ BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
++ BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
++ BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
++
++ /* Initialize context mapping and zero out the quick contexts. The
++ * context block must have already been enabled. */
++ bnx2_init_context(bp);
++
++ if ((rc = bnx2_init_cpus(bp)) != 0)
++ return rc;
++
++ bnx2_init_nvram(bp);
++
++ bnx2_set_mac_addr(bp);
++
++ val = REG_RD(bp, BNX2_MQ_CONFIG);
++ val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
++ val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
++ REG_WR(bp, BNX2_MQ_CONFIG, val);
++
++ val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
++ REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
++ REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
++
++ val = (BCM_PAGE_BITS - 8) << 24;
++ REG_WR(bp, BNX2_RV2P_CONFIG, val);
++
++ /* Configure page size. */
++ val = REG_RD(bp, BNX2_TBDR_CONFIG);
++ val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
++ val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
++ REG_WR(bp, BNX2_TBDR_CONFIG, val);
++
++ val = bp->mac_addr[0] +
++ (bp->mac_addr[1] << 8) +
++ (bp->mac_addr[2] << 16) +
++ bp->mac_addr[3] +
++ (bp->mac_addr[4] << 8) +
++ (bp->mac_addr[5] << 16);
++ REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
++
++ /* Program the MTU. Also include 4 bytes for CRC32. */
++ val = bp->dev->mtu + ETH_HLEN + 4;
++ if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
++ val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
++ REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
++
++ bp->last_status_idx = 0;
++ bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
++
++ /* Set up how to generate a link change interrupt. */
++ REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
++
++ REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
++ (u64) bp->status_blk_mapping & 0xffffffff);
++ REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
++
++ REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
++ (u64) bp->stats_blk_mapping & 0xffffffff);
++ REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
++ (u64) bp->stats_blk_mapping >> 32);
++
++ REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
++ (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
++
++ REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
++ (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
++
++ REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
++ (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
++
++ REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
++
++ REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
++
++ REG_WR(bp, BNX2_HC_COM_TICKS,
++ (bp->com_ticks_int << 16) | bp->com_ticks);
++
++ REG_WR(bp, BNX2_HC_CMD_TICKS,
++ (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
++
++ REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
++ REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
++
++ if (CHIP_ID(bp) == CHIP_ID_5706_A1)
++ REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
++ else {
++ REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
++ BNX2_HC_CONFIG_TX_TMR_MODE |
++ BNX2_HC_CONFIG_COLLECT_STATS);
++ }
++
++ /* Clear internal stats counters. */
++ REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
++
++ REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
++
++ if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
++ BNX2_PORT_FEATURE_ASF_ENABLED)
++ bp->flags |= ASF_ENABLE_FLAG;
++
++ /* Initialize the receive filter. */
++ bnx2_set_rx_mode(bp->dev);
++
++ rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
++ 0);
++
++ REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
++ REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
++
++ udelay(20);
++
++ bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
++
++ return rc;
++}
++
++
++static void
++bnx2_init_tx_ring(struct bnx2 *bp)
++{
++ struct tx_bd *txbd;
++ u32 val;
++
++ txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
++
++ txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
++ txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
++
++ bp->tx_prod = 0;
++ bp->tx_cons = 0;
++ bp->hw_tx_cons = 0;
++ bp->tx_prod_bseq = 0;
++
++ val = BNX2_L2CTX_TYPE_TYPE_L2;
++ val |= BNX2_L2CTX_TYPE_SIZE_L2;
++ CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
++
++ val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
++ val |= 8 << 16;
++ CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
++
++ val = (u64) bp->tx_desc_mapping >> 32;
++ CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
++
++ val = (u64) bp->tx_desc_mapping & 0xffffffff;
++ CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
++}
++
++static void
++bnx2_init_rx_ring(struct bnx2 *bp)
++{
++ struct rx_bd *rxbd;
++ int i;
++ u16 prod, ring_prod;
++ u32 val;
++
++ /* 8 for CRC and VLAN */
++ bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
++ /* 8 for alignment */
++ bp->rx_buf_size = bp->rx_buf_use_size + 8;
++
++ ring_prod = prod = bp->rx_prod = 0;
++ bp->rx_cons = 0;
++ bp->hw_rx_cons = 0;
++ bp->rx_prod_bseq = 0;
++
++ rxbd = &bp->rx_desc_ring[0];
++ for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
++ rxbd->rx_bd_len = bp->rx_buf_use_size;
++ rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
++ }
++
++ rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
++ rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
++
++ val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
++ val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
++ val |= 0x02 << 8;
++ CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
++
++ val = (u64) bp->rx_desc_mapping >> 32;
++ CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
++
++ val = (u64) bp->rx_desc_mapping & 0xffffffff;
++ CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
++
++ for (i = 0; i < bp->rx_ring_size; i++) {
++ if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
++ break;
++ }
++ prod = NEXT_RX_BD(prod);
++ ring_prod = RX_RING_IDX(prod);
++ }
++ bp->rx_prod = prod;
++
++ REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
++
++ REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
++}
++
++static void
++bnx2_free_tx_skbs(struct bnx2 *bp)
++{
++ int i;
++
++ if (bp->tx_buf_ring == NULL)
++ return;
++
++ for (i = 0; i < TX_DESC_CNT; ) {
++ struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
++ struct sk_buff *skb = tx_buf->skb;
++ int j, last;
++
++ if (skb == NULL) {
++ i++;
++ continue;
++ }
++
++ pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
++ skb_headlen(skb), PCI_DMA_TODEVICE);
++
++ tx_buf->skb = NULL;
++
++ last = skb_shinfo(skb)->nr_frags;
++ for (j = 0; j < last; j++) {
++ tx_buf = &bp->tx_buf_ring[i + j + 1];
++ pci_unmap_page(bp->pdev,
++ pci_unmap_addr(tx_buf, mapping),
++ skb_shinfo(skb)->frags[j].size,
++ PCI_DMA_TODEVICE);
++ }
++ dev_kfree_skb(skb);
++ i += j + 1;
++ }
++
++}
++
++static void
++bnx2_free_rx_skbs(struct bnx2 *bp)
++{
++ int i;
++
++ if (bp->rx_buf_ring == NULL)
++ return;
++
++ for (i = 0; i < RX_DESC_CNT; i++) {
++ struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
++ struct sk_buff *skb = rx_buf->skb;
++
++ if (skb == NULL)
++ continue;
++
++ pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
++ bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
++
++ rx_buf->skb = NULL;
++
++ dev_kfree_skb(skb);
++ }
++}
++
++static void
++bnx2_free_skbs(struct bnx2 *bp)
++{
++ bnx2_free_tx_skbs(bp);
++ bnx2_free_rx_skbs(bp);
++}
++
++static int
++bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
++{
++ int rc;
++
++ rc = bnx2_reset_chip(bp, reset_code);
++ bnx2_free_skbs(bp);
++ if (rc)
++ return rc;
++
++ if ((rc = bnx2_init_chip(bp)) != 0)
++ return rc;
++
++ bnx2_init_tx_ring(bp);
++ bnx2_init_rx_ring(bp);
++ return 0;
++}
++
++static int
++bnx2_init_nic(struct bnx2 *bp)
++{
++ int rc;
++
++ if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
++ return rc;
++
++ bnx2_init_phy(bp);
++ bnx2_set_link(bp);
++ return 0;
++}
++
++static int
++bnx2_test_registers(struct bnx2 *bp)
++{
++ int ret;
++ int i;
++ static struct {
++ u16 offset;
++ u16 flags;
++ u32 rw_mask;
++ u32 ro_mask;
++ } reg_tbl[] = {
++ { 0x006c, 0, 0x00000000, 0x0000003f },
++ { 0x0090, 0, 0xffffffff, 0x00000000 },
++ { 0x0094, 0, 0x00000000, 0x00000000 },
++
++ { 0x0404, 0, 0x00003f00, 0x00000000 },
++ { 0x0418, 0, 0x00000000, 0xffffffff },
++ { 0x041c, 0, 0x00000000, 0xffffffff },
++ { 0x0420, 0, 0x00000000, 0x80ffffff },
++ { 0x0424, 0, 0x00000000, 0x00000000 },
++ { 0x0428, 0, 0x00000000, 0x00000001 },
++ { 0x0450, 0, 0x00000000, 0x0000ffff },
++ { 0x0454, 0, 0x00000000, 0xffffffff },
++ { 0x0458, 0, 0x00000000, 0xffffffff },
++
++ { 0x0808, 0, 0x00000000, 0xffffffff },
++ { 0x0854, 0, 0x00000000, 0xffffffff },
++ { 0x0868, 0, 0x00000000, 0x77777777 },
++ { 0x086c, 0, 0x00000000, 0x77777777 },
++ { 0x0870, 0, 0x00000000, 0x77777777 },
++ { 0x0874, 0, 0x00000000, 0x77777777 },
++
++ { 0x0c00, 0, 0x00000000, 0x00000001 },
++ { 0x0c04, 0, 0x00000000, 0x03ff0001 },
++ { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
++
++ { 0x1000, 0, 0x00000000, 0x00000001 },
++ { 0x1004, 0, 0x00000000, 0x000f0001 },
++
++ { 0x1408, 0, 0x01c00800, 0x00000000 },
++ { 0x149c, 0, 0x8000ffff, 0x00000000 },
++ { 0x14a8, 0, 0x00000000, 0x000001ff },
++ { 0x14ac, 0, 0x0fffffff, 0x10000000 },
++ { 0x14b0, 0, 0x00000002, 0x00000001 },
++ { 0x14b8, 0, 0x00000000, 0x00000000 },
++ { 0x14c0, 0, 0x00000000, 0x00000009 },
++ { 0x14c4, 0, 0x00003fff, 0x00000000 },
++ { 0x14cc, 0, 0x00000000, 0x00000001 },
++ { 0x14d0, 0, 0xffffffff, 0x00000000 },
++
++ { 0x1800, 0, 0x00000000, 0x00000001 },
++ { 0x1804, 0, 0x00000000, 0x00000003 },
++
++ { 0x2800, 0, 0x00000000, 0x00000001 },
++ { 0x2804, 0, 0x00000000, 0x00003f01 },
++ { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
++ { 0x2810, 0, 0xffff0000, 0x00000000 },
++ { 0x2814, 0, 0xffff0000, 0x00000000 },
++ { 0x2818, 0, 0xffff0000, 0x00000000 },
++ { 0x281c, 0, 0xffff0000, 0x00000000 },
++ { 0x2834, 0, 0xffffffff, 0x00000000 },
++ { 0x2840, 0, 0x00000000, 0xffffffff },
++ { 0x2844, 0, 0x00000000, 0xffffffff },
++ { 0x2848, 0, 0xffffffff, 0x00000000 },
++ { 0x284c, 0, 0xf800f800, 0x07ff07ff },
++
++ { 0x2c00, 0, 0x00000000, 0x00000011 },
++ { 0x2c04, 0, 0x00000000, 0x00030007 },
++
++ { 0x3c00, 0, 0x00000000, 0x00000001 },
++ { 0x3c04, 0, 0x00000000, 0x00070000 },
++ { 0x3c08, 0, 0x00007f71, 0x07f00000 },
++ { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
++ { 0x3c10, 0, 0xffffffff, 0x00000000 },
++ { 0x3c14, 0, 0x00000000, 0xffffffff },
++ { 0x3c18, 0, 0x00000000, 0xffffffff },
++ { 0x3c1c, 0, 0xfffff000, 0x00000000 },
++ { 0x3c20, 0, 0xffffff00, 0x00000000 },
++
++ { 0x5004, 0, 0x00000000, 0x0000007f },
++ { 0x5008, 0, 0x0f0007ff, 0x00000000 },
++ { 0x500c, 0, 0xf800f800, 0x07ff07ff },
++
++ { 0x5c00, 0, 0x00000000, 0x00000001 },
++ { 0x5c04, 0, 0x00000000, 0x0003000f },
++ { 0x5c08, 0, 0x00000003, 0x00000000 },
++ { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
++ { 0x5c10, 0, 0x00000000, 0xffffffff },
++ { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
++ { 0x5c84, 0, 0x00000000, 0x0000f333 },
++ { 0x5c88, 0, 0x00000000, 0x00077373 },
++ { 0x5c8c, 0, 0x00000000, 0x0007f737 },
++
++ { 0x6808, 0, 0x0000ff7f, 0x00000000 },
++ { 0x680c, 0, 0xffffffff, 0x00000000 },
++ { 0x6810, 0, 0xffffffff, 0x00000000 },
++ { 0x6814, 0, 0xffffffff, 0x00000000 },
++ { 0x6818, 0, 0xffffffff, 0x00000000 },
++ { 0x681c, 0, 0xffffffff, 0x00000000 },
++ { 0x6820, 0, 0x00ff00ff, 0x00000000 },
++ { 0x6824, 0, 0x00ff00ff, 0x00000000 },
++ { 0x6828, 0, 0x00ff00ff, 0x00000000 },
++ { 0x682c, 0, 0x03ff03ff, 0x00000000 },
++ { 0x6830, 0, 0x03ff03ff, 0x00000000 },
++ { 0x6834, 0, 0x03ff03ff, 0x00000000 },
++ { 0x6838, 0, 0x03ff03ff, 0x00000000 },
++ { 0x683c, 0, 0x0000ffff, 0x00000000 },
++ { 0x6840, 0, 0x00000ff0, 0x00000000 },
++ { 0x6844, 0, 0x00ffff00, 0x00000000 },
++ { 0x684c, 0, 0xffffffff, 0x00000000 },
++ { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
++ { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
++ { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
++ { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
++ { 0x6908, 0, 0x00000000, 0x0001ff0f },
++ { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
++
++ { 0xffff, 0, 0x00000000, 0x00000000 },
++ };
++
++ ret = 0;
++ for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
++ u32 offset, rw_mask, ro_mask, save_val, val;
++
++ offset = (u32) reg_tbl[i].offset;
++ rw_mask = reg_tbl[i].rw_mask;
++ ro_mask = reg_tbl[i].ro_mask;
++
++ save_val = readl(bp->regview + offset);
++
++ writel(0, bp->regview + offset);
++
++ val = readl(bp->regview + offset);
++ if ((val & rw_mask) != 0) {
++ goto reg_test_err;
++ }
++
++ if ((val & ro_mask) != (save_val & ro_mask)) {
++ goto reg_test_err;
++ }
++
++ writel(0xffffffff, bp->regview + offset);
++
++ val = readl(bp->regview + offset);
++ if ((val & rw_mask) != rw_mask) {
++ goto reg_test_err;
++ }
++
++ if ((val & ro_mask) != (save_val & ro_mask)) {
++ goto reg_test_err;
++ }
++
++ writel(save_val, bp->regview + offset);
++ continue;
++
++reg_test_err:
++ writel(save_val, bp->regview + offset);
++ ret = -ENODEV;
++ break;
++ }
++ return ret;
++}
++
++static int
++bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
++{
++ static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
++ 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
++ int i;
++
++ for (i = 0; i < sizeof(test_pattern) / 4; i++) {
++ u32 offset;
++
++ for (offset = 0; offset < size; offset += 4) {
++
++ REG_WR_IND(bp, start + offset, test_pattern[i]);
++
++ if (REG_RD_IND(bp, start + offset) !=
++ test_pattern[i]) {
++ return -ENODEV;
++ }
++ }
++ }
++ return 0;
++}
++
++static int
++bnx2_test_memory(struct bnx2 *bp)
++{
++ int ret = 0;
++ int i;
++ static struct {
++ u32 offset;
++ u32 len;
++ } mem_tbl[] = {
++ { 0x60000, 0x4000 },
++ { 0xa0000, 0x3000 },
++ { 0xe0000, 0x4000 },
++ { 0x120000, 0x4000 },
++ { 0x1a0000, 0x4000 },
++ { 0x160000, 0x4000 },
++ { 0xffffffff, 0 },
++ };
++
++ for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
++ if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
++ mem_tbl[i].len)) != 0) {
++ return ret;
++ }
++ }
++
++ return ret;
++}
++
++#define BNX2_MAC_LOOPBACK 0
++#define BNX2_PHY_LOOPBACK 1
++
++static int
++bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
++{
++ unsigned int pkt_size, num_pkts, i;
++ struct sk_buff *skb, *rx_skb;
++ unsigned char *packet;
++ u16 rx_start_idx, rx_idx;
++ dma_addr_t map;
++ struct tx_bd *txbd;
++ struct sw_bd *rx_buf;
++ struct l2_fhdr *rx_hdr;
++ int ret = -ENODEV;
++
++ if (loopback_mode == BNX2_MAC_LOOPBACK) {
++ bp->loopback = MAC_LOOPBACK;
++ bnx2_set_mac_loopback(bp);
++ }
++ else if (loopback_mode == BNX2_PHY_LOOPBACK) {
++ bp->loopback = 0;
++ bnx2_set_phy_loopback(bp);
++ }
++ else
++ return -EINVAL;
++
++ pkt_size = 1514;
++ skb = dev_alloc_skb(pkt_size);
++ if (!skb)
++ return -ENOMEM;
++ packet = skb_put(skb, pkt_size);
++ memcpy(packet, bp->mac_addr, 6);
++ memset(packet + 6, 0x0, 8);
++ for (i = 14; i < pkt_size; i++)
++ packet[i] = (unsigned char) (i & 0xff);
++
++ map = pci_map_single(bp->pdev, skb->data, pkt_size,
++ PCI_DMA_TODEVICE);
++
++ REG_WR(bp, BNX2_HC_COMMAND,
++ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
++
++ REG_RD(bp, BNX2_HC_COMMAND);
++
++ udelay(5);
++ rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
++
++ num_pkts = 0;
++
++ txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
++
++ txbd->tx_bd_haddr_hi = (u64) map >> 32;
++ txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
++ txbd->tx_bd_mss_nbytes = pkt_size;
++ txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
++
++ num_pkts++;
++ bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
++ bp->tx_prod_bseq += pkt_size;
++
++ REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
++ REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
++
++ udelay(100);
++
++ REG_WR(bp, BNX2_HC_COMMAND,
++ bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
++
++ REG_RD(bp, BNX2_HC_COMMAND);
++
++ udelay(5);
++
++ pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
++ dev_kfree_skb(skb);
++
++ if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
++ goto loopback_test_done;
++ }
++
++ rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
++ if (rx_idx != rx_start_idx + num_pkts) {
++ goto loopback_test_done;
++ }
++
++ rx_buf = &bp->rx_buf_ring[rx_start_idx];
++ rx_skb = rx_buf->skb;
++
++ rx_hdr = (struct l2_fhdr *) rx_skb->data;
++ skb_reserve(rx_skb, bp->rx_offset);
++
++ pci_dma_sync_single_for_cpu(bp->pdev,
++ pci_unmap_addr(rx_buf, mapping),
++ bp->rx_buf_size, PCI_DMA_FROMDEVICE);
++
++ if (rx_hdr->l2_fhdr_status &
++ (L2_FHDR_ERRORS_BAD_CRC |
++ L2_FHDR_ERRORS_PHY_DECODE |
++ L2_FHDR_ERRORS_ALIGNMENT |
++ L2_FHDR_ERRORS_TOO_SHORT |
++ L2_FHDR_ERRORS_GIANT_FRAME)) {
++
++ goto loopback_test_done;
++ }
++
++ if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
++ goto loopback_test_done;
++ }
++
++ for (i = 14; i < pkt_size; i++) {
++ if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
++ goto loopback_test_done;
++ }
++ }
++
++ ret = 0;
++
++loopback_test_done:
++ bp->loopback = 0;
++ return ret;
++}
++
++#define BNX2_MAC_LOOPBACK_FAILED 1
++#define BNX2_PHY_LOOPBACK_FAILED 2
++#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
++ BNX2_PHY_LOOPBACK_FAILED)
++
++static int
++bnx2_test_loopback(struct bnx2 *bp)
++{
++ int rc = 0;
++
++ if (!netif_running(bp->dev))
++ return BNX2_LOOPBACK_FAILED;
++
++ bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
++ spin_lock_bh(&bp->phy_lock);
++ bnx2_init_phy(bp);
++ spin_unlock_bh(&bp->phy_lock);
++ if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
++ rc |= BNX2_MAC_LOOPBACK_FAILED;
++ if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
++ rc |= BNX2_PHY_LOOPBACK_FAILED;
++ return rc;
++}
++
++#define NVRAM_SIZE 0x200
++#define CRC32_RESIDUAL 0xdebb20e3
++
++static int
++bnx2_test_nvram(struct bnx2 *bp)
++{
++ u32 buf[NVRAM_SIZE / 4];
++ u8 *data = (u8 *) buf;
++ int rc = 0;
++ u32 magic, csum;
++
++ if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
++ goto test_nvram_done;
++
++ magic = be32_to_cpu(buf[0]);
++ if (magic != 0x669955aa) {
++ rc = -ENODEV;
++ goto test_nvram_done;
++ }
++
++ if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
++ goto test_nvram_done;
++
++ csum = ether_crc_le(0x100, data);
++ if (csum != CRC32_RESIDUAL) {
++ rc = -ENODEV;
++ goto test_nvram_done;
++ }
++
++ csum = ether_crc_le(0x100, data + 0x100);
++ if (csum != CRC32_RESIDUAL) {
++ rc = -ENODEV;
++ }
++
++test_nvram_done:
++ return rc;
++}
++
++static int
++bnx2_test_link(struct bnx2 *bp)
++{
++ u32 bmsr;
++
++ spin_lock_bh(&bp->phy_lock);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ bnx2_read_phy(bp, MII_BMSR, &bmsr);
++ spin_unlock_bh(&bp->phy_lock);
++
++ if (bmsr & BMSR_LSTATUS) {
++ return 0;
++ }
++ return -ENODEV;
++}
++
++static int
++bnx2_test_intr(struct bnx2 *bp)
++{
++ int i;
++ u16 status_idx;
++
++ if (!netif_running(bp->dev))
++ return -ENODEV;
++
++ status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
++
++ /* This register is not touched during run-time. */
++ REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
++ REG_RD(bp, BNX2_HC_COMMAND);
++
++ for (i = 0; i < 10; i++) {
++ if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
++ status_idx) {
++
++ break;
++ }
++
++ msleep_interruptible(10);
++ }
++ if (i < 10)
++ return 0;
++
++ return -ENODEV;
++}
++
++static void
++bnx2_timer(unsigned long data)
++{
++ struct bnx2 *bp = (struct bnx2 *) data;
++ u32 msg;
++
++ if (!netif_running(bp->dev))
++ return;
++
++ if (atomic_read(&bp->intr_sem) != 0)
++ goto bnx2_restart_timer;
++
++ msg = (u32) ++bp->fw_drv_pulse_wr_seq;
++ REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
++
++ bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
++
++ if ((bp->phy_flags & PHY_SERDES_FLAG) &&
++ (CHIP_NUM(bp) == CHIP_NUM_5706)) {
++
++ spin_lock(&bp->phy_lock);
++ if (bp->serdes_an_pending) {
++ bp->serdes_an_pending--;
++ }
++ else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
++ u32 bmcr;
++
++ bp->current_interval = bp->timer_interval;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++
++ if (bmcr & BMCR_ANENABLE) {
++ u32 phy1, phy2;
++
++ bnx2_write_phy(bp, 0x1c, 0x7c00);
++ bnx2_read_phy(bp, 0x1c, &phy1);
++
++ bnx2_write_phy(bp, 0x17, 0x0f01);
++ bnx2_read_phy(bp, 0x15, &phy2);
++ bnx2_write_phy(bp, 0x17, 0x0f01);
++ bnx2_read_phy(bp, 0x15, &phy2);
++
++ if ((phy1 & 0x10) && /* SIGNAL DETECT */
++ !(phy2 & 0x20)) { /* no CONFIG */
++
++ bmcr &= ~BMCR_ANENABLE;
++ bmcr |= BMCR_SPEED1000 |
++ BMCR_FULLDPLX;
++ bnx2_write_phy(bp, MII_BMCR, bmcr);
++ bp->phy_flags |=
++ PHY_PARALLEL_DETECT_FLAG;
++ }
++ }
++ }
++ else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
++ (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
++ u32 phy2;
++
++ bnx2_write_phy(bp, 0x17, 0x0f01);
++ bnx2_read_phy(bp, 0x15, &phy2);
++ if (phy2 & 0x20) {
++ u32 bmcr;
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ bmcr |= BMCR_ANENABLE;
++ bnx2_write_phy(bp, MII_BMCR, bmcr);
++
++ bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
++
++ }
++ }
++ else
++ bp->current_interval = bp->timer_interval;
++
++ spin_unlock(&bp->phy_lock);
++ }
++
++bnx2_restart_timer:
++ mod_timer(&bp->timer, jiffies + bp->current_interval);
++}
++
++/* Called with rtnl_lock */
++static int
++bnx2_open(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ int rc;
++
++ bnx2_set_power_state(bp, 0);
++ bnx2_disable_int(bp);
++
++ rc = bnx2_alloc_mem(bp);
++ if (rc)
++ return rc;
++
++ if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
++ (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
++ !disable_msi) {
++
++ if (pci_enable_msi(bp->pdev) == 0) {
++ bp->flags |= USING_MSI_FLAG;
++ rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
++ dev);
++ }
++ else {
++ rc = request_irq(bp->pdev->irq, bnx2_interrupt,
++ SA_SHIRQ, dev->name, dev);
++ }
++ }
++ else {
++ rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
++ dev->name, dev);
++ }
++ if (rc) {
++ bnx2_free_mem(bp);
++ return rc;
++ }
++
++ rc = bnx2_init_nic(bp);
++
++ if (rc) {
++ free_irq(bp->pdev->irq, dev);
++ if (bp->flags & USING_MSI_FLAG) {
++ pci_disable_msi(bp->pdev);
++ bp->flags &= ~USING_MSI_FLAG;
++ }
++ bnx2_free_skbs(bp);
++ bnx2_free_mem(bp);
++ return rc;
++ }
++
++ mod_timer(&bp->timer, jiffies + bp->current_interval);
++
++ atomic_set(&bp->intr_sem, 0);
++
++ bnx2_enable_int(bp);
++
++ if (bp->flags & USING_MSI_FLAG) {
++ /* Test MSI to make sure it is working
++ * If MSI test fails, go back to INTx mode
++ */
++ if (bnx2_test_intr(bp) != 0) {
++ printk(KERN_WARNING PFX "%s: No interrupt was generated"
++ " using MSI, switching to INTx mode. Please"
++ " report this failure to the PCI maintainer"
++ " and include system chipset information.\n",
++ bp->dev->name);
++
++ bnx2_disable_int(bp);
++ free_irq(bp->pdev->irq, dev);
++ pci_disable_msi(bp->pdev);
++ bp->flags &= ~USING_MSI_FLAG;
++
++ rc = bnx2_init_nic(bp);
++
++ if (!rc) {
++ rc = request_irq(bp->pdev->irq, bnx2_interrupt,
++ SA_SHIRQ, dev->name, dev);
++ }
++ if (rc) {
++ bnx2_free_skbs(bp);
++ bnx2_free_mem(bp);
++ del_timer_sync(&bp->timer);
++ return rc;
++ }
++ bnx2_enable_int(bp);
++ }
++ }
++ if (bp->flags & USING_MSI_FLAG) {
++ printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
++ }
++
++ netif_start_queue(dev);
++
++ return 0;
++}
++
++static void
++bnx2_reset_task(void *data)
++{
++ struct bnx2 *bp = data;
++
++ if (!netif_running(bp->dev))
++ return;
++
++ bp->in_reset_task = 1;
++ bnx2_netif_stop(bp);
++
++ bnx2_init_nic(bp);
++
++ atomic_set(&bp->intr_sem, 1);
++ bnx2_netif_start(bp);
++ bp->in_reset_task = 0;
++}
++
++static void
++bnx2_tx_timeout(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ /* This allows the netif to be shutdown gracefully before resetting */
++ schedule_work(&bp->reset_task);
++}
++
++#ifdef BCM_VLAN
++/* Called with rtnl_lock */
++static void
++bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ bnx2_netif_stop(bp);
++
++ bp->vlgrp = vlgrp;
++ bnx2_set_rx_mode(dev);
++
++ bnx2_netif_start(bp);
++}
++
++/* Called with rtnl_lock */
++static void
++bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ bnx2_netif_stop(bp);
++
++ if (bp->vlgrp)
++ bp->vlgrp->vlan_devices[vid] = NULL;
++ bnx2_set_rx_mode(dev);
++
++ bnx2_netif_start(bp);
++}
++#endif
++
++/* Called with dev->xmit_lock.
++ * hard_start_xmit is pseudo-lockless - a lock is only required when
++ * the tx queue is full. This way, we get the benefit of lockless
++ * operations most of the time without the complexities to handle
++ * netif_stop_queue/wake_queue race conditions.
++ */
++static int
++bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ dma_addr_t mapping;
++ struct tx_bd *txbd;
++ struct sw_bd *tx_buf;
++ u32 len, vlan_tag_flags, last_frag, mss;
++ u16 prod, ring_prod;
++ int i;
++
++ if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
++ netif_stop_queue(dev);
++ printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
++ dev->name);
++
++ return 1;
++ }
++ len = skb_headlen(skb);
++ prod = bp->tx_prod;
++ ring_prod = TX_RING_IDX(prod);
++
++ vlan_tag_flags = 0;
++ if (skb->ip_summed == CHECKSUM_HW) {
++ vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
++ }
++
++ if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
++ vlan_tag_flags |=
++ (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
++ }
++#ifdef BCM_TSO
++ if ((mss = skb_shinfo(skb)->tso_size) &&
++ (skb->len > (bp->dev->mtu + ETH_HLEN))) {
++ u32 tcp_opt_len, ip_tcp_len;
++
++ if (skb_header_cloned(skb) &&
++ pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
++ dev_kfree_skb(skb);
++ return 0;
++ }
++
++ tcp_opt_len = ((skb->h.th->doff - 5) * 4);
++ vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
++
++ tcp_opt_len = 0;
++ if (skb->h.th->doff > 5) {
++ tcp_opt_len = (skb->h.th->doff - 5) << 2;
++ }
++ ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
++
++ skb->nh.iph->check = 0;
++ skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
++ skb->h.th->check =
++ ~csum_tcpudp_magic(skb->nh.iph->saddr,
++ skb->nh.iph->daddr,
++ 0, IPPROTO_TCP, 0);
++
++ if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
++ vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
++ (tcp_opt_len >> 2)) << 8;
++ }
++ }
++ else
++#endif
++ {
++ mss = 0;
++ }
++
++ mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
++
++ tx_buf = &bp->tx_buf_ring[ring_prod];
++ tx_buf->skb = skb;
++ pci_unmap_addr_set(tx_buf, mapping, mapping);
++
++ txbd = &bp->tx_desc_ring[ring_prod];
++
++ txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
++ txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
++ txbd->tx_bd_mss_nbytes = len | (mss << 16);
++ txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
++
++ last_frag = skb_shinfo(skb)->nr_frags;
++
++ for (i = 0; i < last_frag; i++) {
++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
++
++ prod = NEXT_TX_BD(prod);
++ ring_prod = TX_RING_IDX(prod);
++ txbd = &bp->tx_desc_ring[ring_prod];
++
++ len = frag->size;
++ mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
++ len, PCI_DMA_TODEVICE);
++ pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
++ mapping, mapping);
++
++ txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
++ txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
++ txbd->tx_bd_mss_nbytes = len | (mss << 16);
++ txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
++
++ }
++ txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
++
++ prod = NEXT_TX_BD(prod);
++ bp->tx_prod_bseq += skb->len;
++
++ REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
++ REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
++
++ mmiowb();
++
++ bp->tx_prod = prod;
++ dev->trans_start = jiffies;
++
++ if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
++ spin_lock(&bp->tx_lock);
++ netif_stop_queue(dev);
++
++ if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
++ netif_wake_queue(dev);
++ spin_unlock(&bp->tx_lock);
++ }
++
++ return 0;
++}
++
++/* Called with rtnl_lock */
++static int
++bnx2_close(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ u32 reset_code;
++
++ /* Calling flush_scheduled_work() may deadlock because
++ * linkwatch_event() may be on the workqueue and it will try to get
++ * the rtnl_lock which we are holding.
++ */
++ while (bp->in_reset_task)
++ msleep(1);
++
++ bnx2_netif_stop(bp);
++ del_timer_sync(&bp->timer);
++ if (bp->flags & NO_WOL_FLAG)
++ reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
++ else if (bp->wol)
++ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
++ else
++ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
++ bnx2_reset_chip(bp, reset_code);
++ free_irq(bp->pdev->irq, dev);
++ if (bp->flags & USING_MSI_FLAG) {
++ pci_disable_msi(bp->pdev);
++ bp->flags &= ~USING_MSI_FLAG;
++ }
++ bnx2_free_skbs(bp);
++ bnx2_free_mem(bp);
++ bp->link_up = 0;
++ netif_carrier_off(bp->dev);
++ bnx2_set_power_state(bp, 3);
++ return 0;
++}
++
++#define GET_NET_STATS64(ctr) \
++ (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
++ (unsigned long) (ctr##_lo)
++
++#define GET_NET_STATS32(ctr) \
++ (ctr##_lo)
++
++#if (BITS_PER_LONG == 64)
++#define GET_NET_STATS GET_NET_STATS64
++#else
++#define GET_NET_STATS GET_NET_STATS32
++#endif
++
++static struct net_device_stats *
++bnx2_get_stats(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ struct statistics_block *stats_blk = bp->stats_blk;
++ struct net_device_stats *net_stats = &bp->net_stats;
++
++ if (bp->stats_blk == NULL) {
++ return net_stats;
++ }
++ net_stats->rx_packets =
++ GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
++ GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
++ GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
++
++ net_stats->tx_packets =
++ GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
++ GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
++ GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
++
++ net_stats->rx_bytes =
++ GET_NET_STATS(stats_blk->stat_IfHCInOctets);
++
++ net_stats->tx_bytes =
++ GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
++
++ net_stats->multicast =
++ GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
++
++ net_stats->collisions =
++ (unsigned long) stats_blk->stat_EtherStatsCollisions;
++
++ net_stats->rx_length_errors =
++ (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
++ stats_blk->stat_EtherStatsOverrsizePkts);
++
++ net_stats->rx_over_errors =
++ (unsigned long) stats_blk->stat_IfInMBUFDiscards;
++
++ net_stats->rx_frame_errors =
++ (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
++
++ net_stats->rx_crc_errors =
++ (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
++
++ net_stats->rx_errors = net_stats->rx_length_errors +
++ net_stats->rx_over_errors + net_stats->rx_frame_errors +
++ net_stats->rx_crc_errors;
++
++ net_stats->tx_aborted_errors =
++ (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
++ stats_blk->stat_Dot3StatsLateCollisions);
++
++ if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_A0))
++ net_stats->tx_carrier_errors = 0;
++ else {
++ net_stats->tx_carrier_errors =
++ (unsigned long)
++ stats_blk->stat_Dot3StatsCarrierSenseErrors;
++ }
++
++ net_stats->tx_errors =
++ (unsigned long)
++ stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
++ +
++ net_stats->tx_aborted_errors +
++ net_stats->tx_carrier_errors;
++
++ net_stats->rx_missed_errors =
++ (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
++ stats_blk->stat_FwRxDrop);
++
++ return net_stats;
++}
++
++/* All ethtool functions called with rtnl_lock */
++
++static int
++bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ cmd->supported = SUPPORTED_Autoneg;
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ cmd->supported |= SUPPORTED_1000baseT_Full |
++ SUPPORTED_FIBRE;
++
++ cmd->port = PORT_FIBRE;
++ }
++ else {
++ cmd->supported |= SUPPORTED_10baseT_Half |
++ SUPPORTED_10baseT_Full |
++ SUPPORTED_100baseT_Half |
++ SUPPORTED_100baseT_Full |
++ SUPPORTED_1000baseT_Full |
++ SUPPORTED_TP;
++
++ cmd->port = PORT_TP;
++ }
++
++ cmd->advertising = bp->advertising;
++
++ if (bp->autoneg & AUTONEG_SPEED) {
++ cmd->autoneg = AUTONEG_ENABLE;
++ }
++ else {
++ cmd->autoneg = AUTONEG_DISABLE;
++ }
++
++ if (netif_carrier_ok(dev)) {
++ cmd->speed = bp->line_speed;
++ cmd->duplex = bp->duplex;
++ }
++ else {
++ cmd->speed = -1;
++ cmd->duplex = -1;
++ }
++
++ cmd->transceiver = XCVR_INTERNAL;
++ cmd->phy_address = bp->phy_addr;
++
++ return 0;
++}
++
++static int
++bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ u8 autoneg = bp->autoneg;
++ u8 req_duplex = bp->req_duplex;
++ u16 req_line_speed = bp->req_line_speed;
++ u32 advertising = bp->advertising;
++
++ if (cmd->autoneg == AUTONEG_ENABLE) {
++ autoneg |= AUTONEG_SPEED;
++
++ cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
++
++ /* allow advertising 1 speed */
++ if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
++ (cmd->advertising == ADVERTISED_10baseT_Full) ||
++ (cmd->advertising == ADVERTISED_100baseT_Half) ||
++ (cmd->advertising == ADVERTISED_100baseT_Full)) {
++
++ if (bp->phy_flags & PHY_SERDES_FLAG)
++ return -EINVAL;
++
++ advertising = cmd->advertising;
++
++ }
++ else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
++ advertising = cmd->advertising;
++ }
++ else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
++ return -EINVAL;
++ }
++ else {
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ advertising = ETHTOOL_ALL_FIBRE_SPEED;
++ }
++ else {
++ advertising = ETHTOOL_ALL_COPPER_SPEED;
++ }
++ }
++ advertising |= ADVERTISED_Autoneg;
++ }
++ else {
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ if ((cmd->speed != SPEED_1000) ||
++ (cmd->duplex != DUPLEX_FULL)) {
++ return -EINVAL;
++ }
++ }
++ else if (cmd->speed == SPEED_1000) {
++ return -EINVAL;
++ }
++ autoneg &= ~AUTONEG_SPEED;
++ req_line_speed = cmd->speed;
++ req_duplex = cmd->duplex;
++ advertising = 0;
++ }
++
++ bp->autoneg = autoneg;
++ bp->advertising = advertising;
++ bp->req_line_speed = req_line_speed;
++ bp->req_duplex = req_duplex;
++
++ spin_lock_bh(&bp->phy_lock);
++
++ bnx2_setup_phy(bp);
++
++ spin_unlock_bh(&bp->phy_lock);
++
++ return 0;
++}
++
++static void
++bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ strcpy(info->driver, DRV_MODULE_NAME);
++ strcpy(info->version, DRV_MODULE_VERSION);
++ strcpy(info->bus_info, pci_name(bp->pdev));
++ info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
++ info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
++ info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
++ info->fw_version[1] = info->fw_version[3] = '.';
++ info->fw_version[5] = 0;
++}
++
++#define BNX2_REGDUMP_LEN (32 * 1024)
++
++static int
++bnx2_get_regs_len(struct net_device *dev)
++{
++ return BNX2_REGDUMP_LEN;
++}
++
++static void
++bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
++{
++ u32 *p = _p, i, offset;
++ u8 *orig_p = _p;
++ struct bnx2 *bp = netdev_priv(dev);
++ u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
++ 0x0800, 0x0880, 0x0c00, 0x0c10,
++ 0x0c30, 0x0d08, 0x1000, 0x101c,
++ 0x1040, 0x1048, 0x1080, 0x10a4,
++ 0x1400, 0x1490, 0x1498, 0x14f0,
++ 0x1500, 0x155c, 0x1580, 0x15dc,
++ 0x1600, 0x1658, 0x1680, 0x16d8,
++ 0x1800, 0x1820, 0x1840, 0x1854,
++ 0x1880, 0x1894, 0x1900, 0x1984,
++ 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
++ 0x1c80, 0x1c94, 0x1d00, 0x1d84,
++ 0x2000, 0x2030, 0x23c0, 0x2400,
++ 0x2800, 0x2820, 0x2830, 0x2850,
++ 0x2b40, 0x2c10, 0x2fc0, 0x3058,
++ 0x3c00, 0x3c94, 0x4000, 0x4010,
++ 0x4080, 0x4090, 0x43c0, 0x4458,
++ 0x4c00, 0x4c18, 0x4c40, 0x4c54,
++ 0x4fc0, 0x5010, 0x53c0, 0x5444,
++ 0x5c00, 0x5c18, 0x5c80, 0x5c90,
++ 0x5fc0, 0x6000, 0x6400, 0x6428,
++ 0x6800, 0x6848, 0x684c, 0x6860,
++ 0x6888, 0x6910, 0x8000 };
++
++ regs->version = 0;
++
++ memset(p, 0, BNX2_REGDUMP_LEN);
++
++ if (!netif_running(bp->dev))
++ return;
++
++ i = 0;
++ offset = reg_boundaries[0];
++ p += offset;
++ while (offset < BNX2_REGDUMP_LEN) {
++ *p++ = REG_RD(bp, offset);
++ offset += 4;
++ if (offset == reg_boundaries[i + 1]) {
++ offset = reg_boundaries[i + 2];
++ p = (u32 *) (orig_p + offset);
++ i += 2;
++ }
++ }
++}
++
++static void
++bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (bp->flags & NO_WOL_FLAG) {
++ wol->supported = 0;
++ wol->wolopts = 0;
++ }
++ else {
++ wol->supported = WAKE_MAGIC;
++ if (bp->wol)
++ wol->wolopts = WAKE_MAGIC;
++ else
++ wol->wolopts = 0;
++ }
++ memset(&wol->sopass, 0, sizeof(wol->sopass));
++}
++
++static int
++bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (wol->wolopts & ~WAKE_MAGIC)
++ return -EINVAL;
++
++ if (wol->wolopts & WAKE_MAGIC) {
++ if (bp->flags & NO_WOL_FLAG)
++ return -EINVAL;
++
++ bp->wol = 1;
++ }
++ else {
++ bp->wol = 0;
++ }
++ return 0;
++}
++
++static int
++bnx2_nway_reset(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ u32 bmcr;
++
++ if (!(bp->autoneg & AUTONEG_SPEED)) {
++ return -EINVAL;
++ }
++
++ spin_lock_bh(&bp->phy_lock);
++
++ /* Force a link down visible on the other side */
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
++ spin_unlock_bh(&bp->phy_lock);
++
++ msleep(20);
++
++ spin_lock_bh(&bp->phy_lock);
++ if (CHIP_NUM(bp) == CHIP_NUM_5706) {
++ bp->current_interval = SERDES_AN_TIMEOUT;
++ bp->serdes_an_pending = 1;
++ mod_timer(&bp->timer, jiffies + bp->current_interval);
++ }
++ }
++
++ bnx2_read_phy(bp, MII_BMCR, &bmcr);
++ bmcr &= ~BMCR_LOOPBACK;
++ bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
++
++ spin_unlock_bh(&bp->phy_lock);
++
++ return 0;
++}
++
++static int
++bnx2_get_eeprom_len(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (bp->flash_info == NULL)
++ return 0;
++
++ return (int) bp->flash_size;
++}
++
++static int
++bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
++ u8 *eebuf)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ int rc;
++
++ /* parameters already validated in ethtool_get_eeprom */
++
++ rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
++
++ return rc;
++}
++
++static int
++bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
++ u8 *eebuf)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ int rc;
++
++ /* parameters already validated in ethtool_set_eeprom */
++
++ rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
++
++ return rc;
++}
++
++static int
++bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ memset(coal, 0, sizeof(struct ethtool_coalesce));
++
++ coal->rx_coalesce_usecs = bp->rx_ticks;
++ coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
++ coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
++ coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
++
++ coal->tx_coalesce_usecs = bp->tx_ticks;
++ coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
++ coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
++ coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
++
++ coal->stats_block_coalesce_usecs = bp->stats_ticks;
++
++ return 0;
++}
++
++static int
++bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
++ if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
++
++ bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
++ if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
++
++ bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
++ if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
++
++ bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
++ if (bp->rx_quick_cons_trip_int > 0xff)
++ bp->rx_quick_cons_trip_int = 0xff;
++
++ bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
++ if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
++
++ bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
++ if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
++
++ bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
++ if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
++
++ bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
++ if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
++ 0xff;
++
++ bp->stats_ticks = coal->stats_block_coalesce_usecs;
++ if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
++ bp->stats_ticks &= 0xffff00;
++
++ if (netif_running(bp->dev)) {
++ bnx2_netif_stop(bp);
++ bnx2_init_nic(bp);
++ bnx2_netif_start(bp);
++ }
++
++ return 0;
++}
++
++static void
++bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ ering->rx_max_pending = MAX_RX_DESC_CNT;
++ ering->rx_mini_max_pending = 0;
++ ering->rx_jumbo_max_pending = 0;
++
++ ering->rx_pending = bp->rx_ring_size;
++ ering->rx_mini_pending = 0;
++ ering->rx_jumbo_pending = 0;
++
++ ering->tx_max_pending = MAX_TX_DESC_CNT;
++ ering->tx_pending = bp->tx_ring_size;
++}
++
++static int
++bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
++ (ering->tx_pending > MAX_TX_DESC_CNT) ||
++ (ering->tx_pending <= MAX_SKB_FRAGS)) {
++
++ return -EINVAL;
++ }
++ bp->rx_ring_size = ering->rx_pending;
++ bp->tx_ring_size = ering->tx_pending;
++
++ if (netif_running(bp->dev)) {
++ bnx2_netif_stop(bp);
++ bnx2_init_nic(bp);
++ bnx2_netif_start(bp);
++ }
++
++ return 0;
++}
++
++static void
++bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
++ epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
++ epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
++}
++
++static int
++bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ bp->req_flow_ctrl = 0;
++ if (epause->rx_pause)
++ bp->req_flow_ctrl |= FLOW_CTRL_RX;
++ if (epause->tx_pause)
++ bp->req_flow_ctrl |= FLOW_CTRL_TX;
++
++ if (epause->autoneg) {
++ bp->autoneg |= AUTONEG_FLOW_CTRL;
++ }
++ else {
++ bp->autoneg &= ~AUTONEG_FLOW_CTRL;
++ }
++
++ spin_lock_bh(&bp->phy_lock);
++
++ bnx2_setup_phy(bp);
++
++ spin_unlock_bh(&bp->phy_lock);
++
++ return 0;
++}
++
++static u32
++bnx2_get_rx_csum(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ return bp->rx_csum;
++}
++
++static int
++bnx2_set_rx_csum(struct net_device *dev, u32 data)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ bp->rx_csum = data;
++ return 0;
++}
++
++#define BNX2_NUM_STATS 46
++
++static struct {
++ char string[ETH_GSTRING_LEN];
++} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
++ { "rx_bytes" },
++ { "rx_error_bytes" },
++ { "tx_bytes" },
++ { "tx_error_bytes" },
++ { "rx_ucast_packets" },
++ { "rx_mcast_packets" },
++ { "rx_bcast_packets" },
++ { "tx_ucast_packets" },
++ { "tx_mcast_packets" },
++ { "tx_bcast_packets" },
++ { "tx_mac_errors" },
++ { "tx_carrier_errors" },
++ { "rx_crc_errors" },
++ { "rx_align_errors" },
++ { "tx_single_collisions" },
++ { "tx_multi_collisions" },
++ { "tx_deferred" },
++ { "tx_excess_collisions" },
++ { "tx_late_collisions" },
++ { "tx_total_collisions" },
++ { "rx_fragments" },
++ { "rx_jabbers" },
++ { "rx_undersize_packets" },
++ { "rx_oversize_packets" },
++ { "rx_64_byte_packets" },
++ { "rx_65_to_127_byte_packets" },
++ { "rx_128_to_255_byte_packets" },
++ { "rx_256_to_511_byte_packets" },
++ { "rx_512_to_1023_byte_packets" },
++ { "rx_1024_to_1522_byte_packets" },
++ { "rx_1523_to_9022_byte_packets" },
++ { "tx_64_byte_packets" },
++ { "tx_65_to_127_byte_packets" },
++ { "tx_128_to_255_byte_packets" },
++ { "tx_256_to_511_byte_packets" },
++ { "tx_512_to_1023_byte_packets" },
++ { "tx_1024_to_1522_byte_packets" },
++ { "tx_1523_to_9022_byte_packets" },
++ { "rx_xon_frames" },
++ { "rx_xoff_frames" },
++ { "tx_xon_frames" },
++ { "tx_xoff_frames" },
++ { "rx_mac_ctrl_frames" },
++ { "rx_filtered_packets" },
++ { "rx_discards" },
++ { "rx_fw_discards" },
++};
++
++#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
++
++static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
++ STATS_OFFSET32(stat_IfHCInOctets_hi),
++ STATS_OFFSET32(stat_IfHCInBadOctets_hi),
++ STATS_OFFSET32(stat_IfHCOutOctets_hi),
++ STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
++ STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
++ STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
++ STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
++ STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
++ STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
++ STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
++ STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
++ STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
++ STATS_OFFSET32(stat_Dot3StatsFCSErrors),
++ STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
++ STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
++ STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
++ STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
++ STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
++ STATS_OFFSET32(stat_Dot3StatsLateCollisions),
++ STATS_OFFSET32(stat_EtherStatsCollisions),
++ STATS_OFFSET32(stat_EtherStatsFragments),
++ STATS_OFFSET32(stat_EtherStatsJabbers),
++ STATS_OFFSET32(stat_EtherStatsUndersizePkts),
++ STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
++ STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
++ STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
++ STATS_OFFSET32(stat_XonPauseFramesReceived),
++ STATS_OFFSET32(stat_XoffPauseFramesReceived),
++ STATS_OFFSET32(stat_OutXonSent),
++ STATS_OFFSET32(stat_OutXoffSent),
++ STATS_OFFSET32(stat_MacControlFramesReceived),
++ STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
++ STATS_OFFSET32(stat_IfInMBUFDiscards),
++ STATS_OFFSET32(stat_FwRxDrop),
++};
++
++/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
++ * skipped because of errata.
++ */
++static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
++ 8,0,8,8,8,8,8,8,8,8,
++ 4,0,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,
++};
++
++static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
++ 8,0,8,8,8,8,8,8,8,8,
++ 4,4,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,4,4,4,4,
++ 4,4,4,4,4,4,
++};
++
++#define BNX2_NUM_TESTS 6
++
++static struct {
++ char string[ETH_GSTRING_LEN];
++} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
++ { "register_test (offline)" },
++ { "memory_test (offline)" },
++ { "loopback_test (offline)" },
++ { "nvram_test (online)" },
++ { "interrupt_test (online)" },
++ { "link_test (online)" },
++};
++
++static int
++bnx2_self_test_count(struct net_device *dev)
++{
++ return BNX2_NUM_TESTS;
++}
++
++static void
++bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
++ if (etest->flags & ETH_TEST_FL_OFFLINE) {
++ bnx2_netif_stop(bp);
++ bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
++ bnx2_free_skbs(bp);
++
++ if (bnx2_test_registers(bp) != 0) {
++ buf[0] = 1;
++ etest->flags |= ETH_TEST_FL_FAILED;
++ }
++ if (bnx2_test_memory(bp) != 0) {
++ buf[1] = 1;
++ etest->flags |= ETH_TEST_FL_FAILED;
++ }
++ if ((buf[2] = bnx2_test_loopback(bp)) != 0)
++ etest->flags |= ETH_TEST_FL_FAILED;
++
++ if (!netif_running(bp->dev)) {
++ bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
++ }
++ else {
++ bnx2_init_nic(bp);
++ bnx2_netif_start(bp);
++ }
++
++ /* wait for link up */
++ msleep_interruptible(3000);
++ if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
++ msleep_interruptible(4000);
++ }
++
++ if (bnx2_test_nvram(bp) != 0) {
++ buf[3] = 1;
++ etest->flags |= ETH_TEST_FL_FAILED;
++ }
++ if (bnx2_test_intr(bp) != 0) {
++ buf[4] = 1;
++ etest->flags |= ETH_TEST_FL_FAILED;
++ }
++
++ if (bnx2_test_link(bp) != 0) {
++ buf[5] = 1;
++ etest->flags |= ETH_TEST_FL_FAILED;
++
++ }
++}
++
++static void
++bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
++{
++ switch (stringset) {
++ case ETH_SS_STATS:
++ memcpy(buf, bnx2_stats_str_arr,
++ sizeof(bnx2_stats_str_arr));
++ break;
++ case ETH_SS_TEST:
++ memcpy(buf, bnx2_tests_str_arr,
++ sizeof(bnx2_tests_str_arr));
++ break;
++ }
++}
++
++static int
++bnx2_get_stats_count(struct net_device *dev)
++{
++ return BNX2_NUM_STATS;
++}
++
++static void
++bnx2_get_ethtool_stats(struct net_device *dev,
++ struct ethtool_stats *stats, u64 *buf)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ int i;
++ u32 *hw_stats = (u32 *) bp->stats_blk;
++ u8 *stats_len_arr = NULL;
++
++ if (hw_stats == NULL) {
++ memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
++ return;
++ }
++
++ if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
++ (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
++ (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_A0))
++ stats_len_arr = bnx2_5706_stats_len_arr;
++ else
++ stats_len_arr = bnx2_5708_stats_len_arr;
++
++ for (i = 0; i < BNX2_NUM_STATS; i++) {
++ if (stats_len_arr[i] == 0) {
++ /* skip this counter */
++ buf[i] = 0;
++ continue;
++ }
++ if (stats_len_arr[i] == 4) {
++ /* 4-byte counter */
++ buf[i] = (u64)
++ *(hw_stats + bnx2_stats_offset_arr[i]);
++ continue;
++ }
++ /* 8-byte counter */
++ buf[i] = (((u64) *(hw_stats +
++ bnx2_stats_offset_arr[i])) << 32) +
++ *(hw_stats + bnx2_stats_offset_arr[i] + 1);
++ }
++}
++
++static int
++bnx2_phys_id(struct net_device *dev, u32 data)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++ int i;
++ u32 save;
++
++ if (data == 0)
++ data = 2;
++
++ save = REG_RD(bp, BNX2_MISC_CFG);
++ REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
++
++ for (i = 0; i < (data * 2); i++) {
++ if ((i % 2) == 0) {
++ REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
++ }
++ else {
++ REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
++ BNX2_EMAC_LED_1000MB_OVERRIDE |
++ BNX2_EMAC_LED_100MB_OVERRIDE |
++ BNX2_EMAC_LED_10MB_OVERRIDE |
++ BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
++ BNX2_EMAC_LED_TRAFFIC);
++ }
++ msleep_interruptible(500);
++ if (signal_pending(current))
++ break;
++ }
++ REG_WR(bp, BNX2_EMAC_LED, 0);
++ REG_WR(bp, BNX2_MISC_CFG, save);
++ return 0;
++}
++
++static struct ethtool_ops bnx2_ethtool_ops = {
++ .get_settings = bnx2_get_settings,
++ .set_settings = bnx2_set_settings,
++ .get_drvinfo = bnx2_get_drvinfo,
++ .get_regs_len = bnx2_get_regs_len,
++ .get_regs = bnx2_get_regs,
++ .get_wol = bnx2_get_wol,
++ .set_wol = bnx2_set_wol,
++ .nway_reset = bnx2_nway_reset,
++ .get_link = ethtool_op_get_link,
++ .get_eeprom_len = bnx2_get_eeprom_len,
++ .get_eeprom = bnx2_get_eeprom,
++ .set_eeprom = bnx2_set_eeprom,
++ .get_coalesce = bnx2_get_coalesce,
++ .set_coalesce = bnx2_set_coalesce,
++ .get_ringparam = bnx2_get_ringparam,
++ .set_ringparam = bnx2_set_ringparam,
++ .get_pauseparam = bnx2_get_pauseparam,
++ .set_pauseparam = bnx2_set_pauseparam,
++ .get_rx_csum = bnx2_get_rx_csum,
++ .set_rx_csum = bnx2_set_rx_csum,
++ .get_tx_csum = ethtool_op_get_tx_csum,
++ .set_tx_csum = ethtool_op_set_tx_csum,
++ .get_sg = ethtool_op_get_sg,
++ .set_sg = ethtool_op_set_sg,
++#ifdef BCM_TSO
++ .get_tso = ethtool_op_get_tso,
++ .set_tso = ethtool_op_set_tso,
++#endif
++ .self_test_count = bnx2_self_test_count,
++ .self_test = bnx2_self_test,
++ .get_strings = bnx2_get_strings,
++ .phys_id = bnx2_phys_id,
++ .get_stats_count = bnx2_get_stats_count,
++ .get_ethtool_stats = bnx2_get_ethtool_stats,
++};
++
++/* Called with rtnl_lock */
++static int
++bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++ struct mii_ioctl_data *data = if_mii(ifr);
++ struct bnx2 *bp = netdev_priv(dev);
++ int err;
++
++ switch(cmd) {
++ case SIOCGMIIPHY:
++ data->phy_id = bp->phy_addr;
++
++ /* fallthru */
++ case SIOCGMIIREG: {
++ u32 mii_regval;
++
++ spin_lock_bh(&bp->phy_lock);
++ err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
++ spin_unlock_bh(&bp->phy_lock);
++
++ data->val_out = mii_regval;
++
++ return err;
++ }
++
++ case SIOCSMIIREG:
++ if (!capable(CAP_NET_ADMIN))
++ return -EPERM;
++
++ spin_lock_bh(&bp->phy_lock);
++ err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
++ spin_unlock_bh(&bp->phy_lock);
++
++ return err;
++
++ default:
++ /* do nothing */
++ break;
++ }
++ return -EOPNOTSUPP;
++}
++
++/* Called with rtnl_lock */
++static int
++bnx2_change_mac_addr(struct net_device *dev, void *p)
++{
++ struct sockaddr *addr = p;
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (!is_valid_ether_addr(addr->sa_data))
++ return -EINVAL;
++
++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
++ if (netif_running(dev))
++ bnx2_set_mac_addr(bp);
++
++ return 0;
++}
++
++/* Called with rtnl_lock */
++static int
++bnx2_change_mtu(struct net_device *dev, int new_mtu)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
++ ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
++ return -EINVAL;
++
++ dev->mtu = new_mtu;
++ if (netif_running(dev)) {
++ bnx2_netif_stop(bp);
++
++ bnx2_init_nic(bp);
++
++ bnx2_netif_start(bp);
++ }
++ return 0;
++}
++
++#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
++static void
++poll_bnx2(struct net_device *dev)
++{
++ struct bnx2 *bp = netdev_priv(dev);
++
++ disable_irq(bp->pdev->irq);
++ bnx2_interrupt(bp->pdev->irq, dev, NULL);
++ enable_irq(bp->pdev->irq);
++}
++#endif
++
++static int __devinit
++bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
++{
++ struct bnx2 *bp;
++ unsigned long mem_len;
++ int rc;
++ u32 reg;
++
++ SET_MODULE_OWNER(dev);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++ bp = netdev_priv(dev);
++
++ bp->flags = 0;
++ bp->phy_flags = 0;
++
++ /* enable device (incl. PCI PM wakeup), and bus-mastering */
++ rc = pci_enable_device(pdev);
++ if (rc) {
++ printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
++ goto err_out;
++ }
++
++ if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
++ printk(KERN_ERR PFX "Cannot find PCI device base address, "
++ "aborting.\n");
++ rc = -ENODEV;
++ goto err_out_disable;
++ }
++
++ rc = pci_request_regions(pdev, DRV_MODULE_NAME);
++ if (rc) {
++ printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
++ goto err_out_disable;
++ }
++
++ pci_set_master(pdev);
++
++ bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
++ if (bp->pm_cap == 0) {
++ printk(KERN_ERR PFX "Cannot find power management capability, "
++ "aborting.\n");
++ rc = -EIO;
++ goto err_out_release;
++ }
++
++ bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
++ if (bp->pcix_cap == 0) {
++ printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
++ rc = -EIO;
++ goto err_out_release;
++ }
++
++ if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
++ bp->flags |= USING_DAC_FLAG;
++ if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
++ printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
++ "failed, aborting.\n");
++ rc = -EIO;
++ goto err_out_release;
++ }
++ }
++ else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
++ printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
++ rc = -EIO;
++ goto err_out_release;
++ }
++
++ bp->dev = dev;
++ bp->pdev = pdev;
++
++ spin_lock_init(&bp->phy_lock);
++ spin_lock_init(&bp->tx_lock);
++ INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
++
++ dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
++ mem_len = MB_GET_CID_ADDR(17);
++ dev->mem_end = dev->mem_start + mem_len;
++ dev->irq = pdev->irq;
++
++ bp->regview = ioremap_nocache(dev->base_addr, mem_len);
++
++ if (!bp->regview) {
++ printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
++ rc = -ENOMEM;
++ goto err_out_release;
++ }
++
++ /* Configure byte swap and enable write to the reg_window registers.
++ * Rely on CPU to do target byte swapping on big endian systems
++ * The chip's target access swapping will not swap all accesses
++ */
++ pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
++ BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
++ BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
++
++ bnx2_set_power_state(bp, 0);
++
++ bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
++
++ /* Get bus information. */
++ reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
++ if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
++ u32 clkreg;
++
++ bp->flags |= PCIX_FLAG;
++
++ clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
++
++ clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
++ switch (clkreg) {
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
++ bp->bus_speed_mhz = 133;
++ break;
++
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
++ bp->bus_speed_mhz = 100;
++ break;
++
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
++ bp->bus_speed_mhz = 66;
++ break;
++
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
++ bp->bus_speed_mhz = 50;
++ break;
++
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
++ case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
++ bp->bus_speed_mhz = 33;
++ break;
++ }
++ }
++ else {
++ if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
++ bp->bus_speed_mhz = 66;
++ else
++ bp->bus_speed_mhz = 33;
++ }
++
++ if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
++ bp->flags |= PCI_32BIT_FLAG;
++
++ /* 5706A0 may falsely detect SERR and PERR. */
++ if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
++ reg = REG_RD(bp, PCI_COMMAND);
++ reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
++ REG_WR(bp, PCI_COMMAND, reg);
++ }
++ else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
++ !(bp->flags & PCIX_FLAG)) {
++
++ printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
++ "aborting.\n");
++ goto err_out_unmap;
++ }
++
++ bnx2_init_nvram(bp);
++
++ reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
++
++ if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
++ BNX2_SHM_HDR_SIGNATURE_SIG)
++ bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
++ else
++ bp->shmem_base = HOST_VIEW_SHMEM_BASE;
++
++ /* Get the permanent MAC address. First we need to make sure the
++ * firmware is actually running.
++ */
++ reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
++
++ if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
++ BNX2_DEV_INFO_SIGNATURE_MAGIC) {
++ printk(KERN_ERR PFX "Firmware not running, aborting.\n");
++ rc = -ENODEV;
++ goto err_out_unmap;
++ }
++
++ bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
++
++ reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
++ bp->mac_addr[0] = (u8) (reg >> 8);
++ bp->mac_addr[1] = (u8) reg;
++
++ reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
++ bp->mac_addr[2] = (u8) (reg >> 24);
++ bp->mac_addr[3] = (u8) (reg >> 16);
++ bp->mac_addr[4] = (u8) (reg >> 8);
++ bp->mac_addr[5] = (u8) reg;
++
++ bp->tx_ring_size = MAX_TX_DESC_CNT;
++ bp->rx_ring_size = 100;
++
++ bp->rx_csum = 1;
++
++ bp->rx_offset = sizeof(struct l2_fhdr) + 2;
++
++ bp->tx_quick_cons_trip_int = 20;
++ bp->tx_quick_cons_trip = 20;
++ bp->tx_ticks_int = 80;
++ bp->tx_ticks = 80;
++
++ bp->rx_quick_cons_trip_int = 6;
++ bp->rx_quick_cons_trip = 6;
++ bp->rx_ticks_int = 18;
++ bp->rx_ticks = 18;
++
++ bp->stats_ticks = 1000000 & 0xffff00;
++
++ bp->timer_interval = HZ;
++ bp->current_interval = HZ;
++
++ bp->phy_addr = 1;
++
++ /* Disable WOL support if we are running on a SERDES chip. */
++ if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
++ bp->phy_flags |= PHY_SERDES_FLAG;
++ bp->flags |= NO_WOL_FLAG;
++ if (CHIP_NUM(bp) == CHIP_NUM_5708) {
++ bp->phy_addr = 2;
++ reg = REG_RD_IND(bp, bp->shmem_base +
++ BNX2_SHARED_HW_CFG_CONFIG);
++ if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
++ bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
++ }
++ }
++
++ if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
++ (CHIP_ID(bp) == CHIP_ID_5708_B1))
++ bp->flags |= NO_WOL_FLAG;
++
++ if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
++ bp->tx_quick_cons_trip_int =
++ bp->tx_quick_cons_trip;
++ bp->tx_ticks_int = bp->tx_ticks;
++ bp->rx_quick_cons_trip_int =
++ bp->rx_quick_cons_trip;
++ bp->rx_ticks_int = bp->rx_ticks;
++ bp->comp_prod_trip_int = bp->comp_prod_trip;
++ bp->com_ticks_int = bp->com_ticks;
++ bp->cmd_ticks_int = bp->cmd_ticks;
++ }
++
++ bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
++ bp->req_line_speed = 0;
++ if (bp->phy_flags & PHY_SERDES_FLAG) {
++ bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
++
++ reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
++ reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
++ if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
++ bp->autoneg = 0;
++ bp->req_line_speed = bp->line_speed = SPEED_1000;
++ bp->req_duplex = DUPLEX_FULL;
++ }
++ }
++ else {
++ bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
++ }
++
++ bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
++
++ init_timer(&bp->timer);
++ bp->timer.expires = RUN_AT(bp->timer_interval);
++ bp->timer.data = (unsigned long) bp;
++ bp->timer.function = bnx2_timer;
++
++ return 0;
++
++err_out_unmap:
++ if (bp->regview) {
++ iounmap(bp->regview);
++ bp->regview = NULL;
++ }
++
++err_out_release:
++ pci_release_regions(pdev);
++
++err_out_disable:
++ pci_disable_device(pdev);
++ pci_set_drvdata(pdev, NULL);
++
++err_out:
++ return rc;
++}
++
++static int __devinit
++bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++ static int version_printed = 0;
++ struct net_device *dev = NULL;
++ struct bnx2 *bp;
++ int rc, i;
++
++ if (version_printed++ == 0)
++ printk(KERN_INFO "%s", version);
++
++ /* dev zeroed in init_etherdev */
++ dev = alloc_etherdev(sizeof(*bp));
++
++ if (!dev)
++ return -ENOMEM;
++
++ rc = bnx2_init_board(pdev, dev);
++ if (rc < 0) {
++ free_netdev(dev);
++ return rc;
++ }
++
++ dev->open = bnx2_open;
++ dev->hard_start_xmit = bnx2_start_xmit;
++ dev->stop = bnx2_close;
++ dev->get_stats = bnx2_get_stats;
++ dev->set_multicast_list = bnx2_set_rx_mode;
++ dev->do_ioctl = bnx2_ioctl;
++ dev->set_mac_address = bnx2_change_mac_addr;
++ dev->change_mtu = bnx2_change_mtu;
++ dev->tx_timeout = bnx2_tx_timeout;
++ dev->watchdog_timeo = TX_TIMEOUT;
++#ifdef BCM_VLAN
++ dev->vlan_rx_register = bnx2_vlan_rx_register;
++ dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
++#endif
++ dev->poll = bnx2_poll;
++ dev->ethtool_ops = &bnx2_ethtool_ops;
++ dev->weight = 64;
++
++ bp = netdev_priv(dev);
++
++#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
++ dev->poll_controller = poll_bnx2;
++#endif
++
++ if ((rc = register_netdev(dev))) {
++ printk(KERN_ERR PFX "Cannot register net device\n");
++ if (bp->regview)
++ iounmap(bp->regview);
++ pci_release_regions(pdev);
++ pci_disable_device(pdev);
++ pci_set_drvdata(pdev, NULL);
++ free_netdev(dev);
++ return rc;
++ }
++
++ pci_set_drvdata(pdev, dev);
++
++ memcpy(dev->dev_addr, bp->mac_addr, 6);
++ bp->name = board_info[ent->driver_data].name,
++ printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
++ "IRQ %d, ",
++ dev->name,
++ bp->name,
++ ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
++ ((CHIP_ID(bp) & 0x0ff0) >> 4),
++ ((bp->flags & PCIX_FLAG) ? "-X" : ""),
++ ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
++ bp->bus_speed_mhz,
++ dev->base_addr,
++ bp->pdev->irq);
++
++ printk("node addr ");
++ for (i = 0; i < 6; i++)
++ printk("%2.2x", dev->dev_addr[i]);
++ printk("\n");
++
++ dev->features |= NETIF_F_SG;
++ if (bp->flags & USING_DAC_FLAG)
++ dev->features |= NETIF_F_HIGHDMA;
++ dev->features |= NETIF_F_IP_CSUM;
++#ifdef BCM_VLAN
++ dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
++#endif
++#ifdef BCM_TSO
++ dev->features |= NETIF_F_TSO;
++#endif
++
++ netif_carrier_off(bp->dev);
++
++ return 0;
++}
++
++static void __devexit
++bnx2_remove_one(struct pci_dev *pdev)
++{
++ struct net_device *dev = pci_get_drvdata(pdev);
++ struct bnx2 *bp = netdev_priv(dev);
++
++ flush_scheduled_work();
++
++ unregister_netdev(dev);
++
++ if (bp->regview)
++ iounmap(bp->regview);
++
++ free_netdev(dev);
++ pci_release_regions(pdev);
++ pci_disable_device(pdev);
++ pci_set_drvdata(pdev, NULL);
++}
++
++static int
++bnx2_suspend(struct pci_dev *pdev, u32 state)
++{
++ struct net_device *dev = pci_get_drvdata(pdev);
++ struct bnx2 *bp = netdev_priv(dev);
++ u32 reset_code;
++
++ if (!netif_running(dev))
++ return 0;
++
++ flush_scheduled_work();
++ bnx2_netif_stop(bp);
++ netif_device_detach(dev);
++ del_timer_sync(&bp->timer);
++ if (bp->flags & NO_WOL_FLAG)
++ reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
++ else if (bp->wol)
++ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
++ else
++ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
++ bnx2_reset_chip(bp, reset_code);
++ bnx2_free_skbs(bp);
++ bnx2_set_power_state(bp, state);
++ return 0;
++}
++
++static int
++bnx2_resume(struct pci_dev *pdev)
++{
++ struct net_device *dev = pci_get_drvdata(pdev);
++ struct bnx2 *bp = netdev_priv(dev);
++
++ if (!netif_running(dev))
++ return 0;
++
++ bnx2_set_power_state(bp, 0);
++ netif_device_attach(dev);
++ bnx2_init_nic(bp);
++ bnx2_netif_start(bp);
++ return 0;
++}
++
++static struct pci_driver bnx2_pci_driver = {
++ .name = DRV_MODULE_NAME,
++ .id_table = bnx2_pci_tbl,
++ .probe = bnx2_init_one,
++ .remove = __devexit_p(bnx2_remove_one),
++ .suspend = bnx2_suspend,
++ .resume = bnx2_resume,
++};
++
++static int __init bnx2_init(void)
++{
++ return pci_module_init(&bnx2_pci_driver);
++}
++
++static void __exit bnx2_cleanup(void)
++{
++ pci_unregister_driver(&bnx2_pci_driver);
++}
++
++module_init(bnx2_init);
++module_exit(bnx2_cleanup);
++
++
++
+diff -urN kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2.h kernel-source-2.6.8-2.6.8/drivers/net/bnx2.h
+--- kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2.h 1969-12-31 17:00:00.000000000 -0700
++++ kernel-source-2.6.8-2.6.8/drivers/net/bnx2.h 2006-09-19 17:56:59.703160000 -0600
+@@ -0,0 +1,4442 @@
++/* bnx2.h: Broadcom NX2 network driver.
++ *
++ * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation.
++ *
++ * Written by: Michael Chan (mchan at broadcom.com)
++ */
++
++
++#ifndef BNX2_H
++#define BNX2_H
++
++/* Hardware data structures and register definitions automatically
++ * generated from RTL code. Do not modify.
++ */
++
++/*
++ * tx_bd definition
++ */
++struct tx_bd {
++ u32 tx_bd_haddr_hi;
++ u32 tx_bd_haddr_lo;
++ u32 tx_bd_mss_nbytes;
++ u32 tx_bd_vlan_tag_flags;
++ #define TX_BD_FLAGS_CONN_FAULT (1<<0)
++ #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
++ #define TX_BD_FLAGS_IP_CKSUM (1<<2)
++ #define TX_BD_FLAGS_VLAN_TAG (1<<3)
++ #define TX_BD_FLAGS_COAL_NOW (1<<4)
++ #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
++ #define TX_BD_FLAGS_END (1<<6)
++ #define TX_BD_FLAGS_START (1<<7)
++ #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
++ #define TX_BD_FLAGS_SW_FLAGS (1<<13)
++ #define TX_BD_FLAGS_SW_SNAP (1<<14)
++ #define TX_BD_FLAGS_SW_LSO (1<<15)
++
++};
++
++
++/*
++ * rx_bd definition
++ */
++struct rx_bd {
++ u32 rx_bd_haddr_hi;
++ u32 rx_bd_haddr_lo;
++ u32 rx_bd_len;
++ u32 rx_bd_flags;
++ #define RX_BD_FLAGS_NOPUSH (1<<0)
++ #define RX_BD_FLAGS_DUMMY (1<<1)
++ #define RX_BD_FLAGS_END (1<<2)
++ #define RX_BD_FLAGS_START (1<<3)
++
++};
++
++
++/*
++ * status_block definition
++ */
++struct status_block {
++ u32 status_attn_bits;
++ #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
++ #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
++ #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
++ #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
++ #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
++ #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
++ #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
++ #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
++ #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
++ #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
++ #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
++ #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
++ #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
++ #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
++ #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
++ #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
++ #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
++ #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
++ #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
++ #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
++ #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
++ #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
++ #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
++ #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
++ #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
++ #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
++ #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
++ #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
++ #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
++
++ u32 status_attn_bits_ack;
++#if defined(__BIG_ENDIAN)
++ u16 status_tx_quick_consumer_index0;
++ u16 status_tx_quick_consumer_index1;
++ u16 status_tx_quick_consumer_index2;
++ u16 status_tx_quick_consumer_index3;
++ u16 status_rx_quick_consumer_index0;
++ u16 status_rx_quick_consumer_index1;
++ u16 status_rx_quick_consumer_index2;
++ u16 status_rx_quick_consumer_index3;
++ u16 status_rx_quick_consumer_index4;
++ u16 status_rx_quick_consumer_index5;
++ u16 status_rx_quick_consumer_index6;
++ u16 status_rx_quick_consumer_index7;
++ u16 status_rx_quick_consumer_index8;
++ u16 status_rx_quick_consumer_index9;
++ u16 status_rx_quick_consumer_index10;
++ u16 status_rx_quick_consumer_index11;
++ u16 status_rx_quick_consumer_index12;
++ u16 status_rx_quick_consumer_index13;
++ u16 status_rx_quick_consumer_index14;
++ u16 status_rx_quick_consumer_index15;
++ u16 status_completion_producer_index;
++ u16 status_cmd_consumer_index;
++ u16 status_idx;
++ u16 status_unused;
++#elif defined(__LITTLE_ENDIAN)
++ u16 status_tx_quick_consumer_index1;
++ u16 status_tx_quick_consumer_index0;
++ u16 status_tx_quick_consumer_index3;
++ u16 status_tx_quick_consumer_index2;
++ u16 status_rx_quick_consumer_index1;
++ u16 status_rx_quick_consumer_index0;
++ u16 status_rx_quick_consumer_index3;
++ u16 status_rx_quick_consumer_index2;
++ u16 status_rx_quick_consumer_index5;
++ u16 status_rx_quick_consumer_index4;
++ u16 status_rx_quick_consumer_index7;
++ u16 status_rx_quick_consumer_index6;
++ u16 status_rx_quick_consumer_index9;
++ u16 status_rx_quick_consumer_index8;
++ u16 status_rx_quick_consumer_index11;
++ u16 status_rx_quick_consumer_index10;
++ u16 status_rx_quick_consumer_index13;
++ u16 status_rx_quick_consumer_index12;
++ u16 status_rx_quick_consumer_index15;
++ u16 status_rx_quick_consumer_index14;
++ u16 status_cmd_consumer_index;
++ u16 status_completion_producer_index;
++ u16 status_unused;
++ u16 status_idx;
++#endif
++};
++
++
++/*
++ * statistics_block definition
++ */
++struct statistics_block {
++ u32 stat_IfHCInOctets_hi;
++ u32 stat_IfHCInOctets_lo;
++ u32 stat_IfHCInBadOctets_hi;
++ u32 stat_IfHCInBadOctets_lo;
++ u32 stat_IfHCOutOctets_hi;
++ u32 stat_IfHCOutOctets_lo;
++ u32 stat_IfHCOutBadOctets_hi;
++ u32 stat_IfHCOutBadOctets_lo;
++ u32 stat_IfHCInUcastPkts_hi;
++ u32 stat_IfHCInUcastPkts_lo;
++ u32 stat_IfHCInMulticastPkts_hi;
++ u32 stat_IfHCInMulticastPkts_lo;
++ u32 stat_IfHCInBroadcastPkts_hi;
++ u32 stat_IfHCInBroadcastPkts_lo;
++ u32 stat_IfHCOutUcastPkts_hi;
++ u32 stat_IfHCOutUcastPkts_lo;
++ u32 stat_IfHCOutMulticastPkts_hi;
++ u32 stat_IfHCOutMulticastPkts_lo;
++ u32 stat_IfHCOutBroadcastPkts_hi;
++ u32 stat_IfHCOutBroadcastPkts_lo;
++ u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
++ u32 stat_Dot3StatsCarrierSenseErrors;
++ u32 stat_Dot3StatsFCSErrors;
++ u32 stat_Dot3StatsAlignmentErrors;
++ u32 stat_Dot3StatsSingleCollisionFrames;
++ u32 stat_Dot3StatsMultipleCollisionFrames;
++ u32 stat_Dot3StatsDeferredTransmissions;
++ u32 stat_Dot3StatsExcessiveCollisions;
++ u32 stat_Dot3StatsLateCollisions;
++ u32 stat_EtherStatsCollisions;
++ u32 stat_EtherStatsFragments;
++ u32 stat_EtherStatsJabbers;
++ u32 stat_EtherStatsUndersizePkts;
++ u32 stat_EtherStatsOverrsizePkts;
++ u32 stat_EtherStatsPktsRx64Octets;
++ u32 stat_EtherStatsPktsRx65Octetsto127Octets;
++ u32 stat_EtherStatsPktsRx128Octetsto255Octets;
++ u32 stat_EtherStatsPktsRx256Octetsto511Octets;
++ u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
++ u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
++ u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
++ u32 stat_EtherStatsPktsTx64Octets;
++ u32 stat_EtherStatsPktsTx65Octetsto127Octets;
++ u32 stat_EtherStatsPktsTx128Octetsto255Octets;
++ u32 stat_EtherStatsPktsTx256Octetsto511Octets;
++ u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
++ u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
++ u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
++ u32 stat_XonPauseFramesReceived;
++ u32 stat_XoffPauseFramesReceived;
++ u32 stat_OutXonSent;
++ u32 stat_OutXoffSent;
++ u32 stat_FlowControlDone;
++ u32 stat_MacControlFramesReceived;
++ u32 stat_XoffStateEntered;
++ u32 stat_IfInFramesL2FilterDiscards;
++ u32 stat_IfInRuleCheckerDiscards;
++ u32 stat_IfInFTQDiscards;
++ u32 stat_IfInMBUFDiscards;
++ u32 stat_IfInRuleCheckerP4Hit;
++ u32 stat_CatchupInRuleCheckerDiscards;
++ u32 stat_CatchupInFTQDiscards;
++ u32 stat_CatchupInMBUFDiscards;
++ u32 stat_CatchupInRuleCheckerP4Hit;
++ u32 stat_GenStat00;
++ u32 stat_GenStat01;
++ u32 stat_GenStat02;
++ u32 stat_GenStat03;
++ u32 stat_GenStat04;
++ u32 stat_GenStat05;
++ u32 stat_GenStat06;
++ u32 stat_GenStat07;
++ u32 stat_GenStat08;
++ u32 stat_GenStat09;
++ u32 stat_GenStat10;
++ u32 stat_GenStat11;
++ u32 stat_GenStat12;
++ u32 stat_GenStat13;
++ u32 stat_GenStat14;
++ u32 stat_GenStat15;
++ u32 stat_FwRxDrop;
++};
++
++
++/*
++ * l2_fhdr definition
++ */
++struct l2_fhdr {
++ u32 l2_fhdr_status;
++ #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
++ #define L2_FHDR_STATUS_RULE_P2 (1<<3)
++ #define L2_FHDR_STATUS_RULE_P3 (1<<4)
++ #define L2_FHDR_STATUS_RULE_P4 (1<<5)
++ #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
++ #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
++ #define L2_FHDR_STATUS_RSS_HASH (1<<8)
++ #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
++ #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
++ #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
++
++ #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
++ #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
++ #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
++ #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
++ #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
++ #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
++ #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
++
++ u32 l2_fhdr_hash;
++#if defined(__BIG_ENDIAN)
++ u16 l2_fhdr_pkt_len;
++ u16 l2_fhdr_vlan_tag;
++ u16 l2_fhdr_ip_xsum;
++ u16 l2_fhdr_tcp_udp_xsum;
++#elif defined(__LITTLE_ENDIAN)
++ u16 l2_fhdr_vlan_tag;
++ u16 l2_fhdr_pkt_len;
++ u16 l2_fhdr_tcp_udp_xsum;
++ u16 l2_fhdr_ip_xsum;
++#endif
++};
++
++
++/*
++ * l2_context definition
++ */
++#define BNX2_L2CTX_TYPE 0x00000000
++#define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
++#define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
++#define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
++#define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
++
++#define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
++#define BNX2_L2CTX_EST_NBD 0x00000088
++#define BNX2_L2CTX_CMD_TYPE 0x00000088
++#define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
++#define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
++#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
++
++#define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
++#define BNX2_L2CTX_TSCH_BSEQ 0x00000094
++#define BNX2_L2CTX_TBDR_BSEQ 0x00000098
++#define BNX2_L2CTX_TBDR_BOFF 0x0000009c
++#define BNX2_L2CTX_TBDR_BIDX 0x0000009c
++#define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
++#define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
++#define BNX2_L2CTX_TXP_BOFF 0x000000a8
++#define BNX2_L2CTX_TXP_BIDX 0x000000a8
++#define BNX2_L2CTX_TXP_BSEQ 0x000000ac
++
++
++/*
++ * l2_bd_chain_context definition
++ */
++#define BNX2_L2CTX_BD_PRE_READ 0x00000000
++#define BNX2_L2CTX_CTX_SIZE 0x00000000
++#define BNX2_L2CTX_CTX_TYPE 0x00000000
++#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
++#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
++#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
++#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
++
++#define BNX2_L2CTX_HOST_BDIDX 0x00000004
++#define BNX2_L2CTX_HOST_BSEQ 0x00000008
++#define BNX2_L2CTX_NX_BSEQ 0x0000000c
++#define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
++#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
++#define BNX2_L2CTX_NX_BDIDX 0x00000018
++
++
++/*
++ * pci_config_l definition
++ * offset: 0000
++ */
++#define BNX2_PCICFG_MISC_CONFIG 0x00000068
++#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
++#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
++#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
++#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
++#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
++#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
++#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
++#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
++#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
++#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
++
++#define BNX2_PCICFG_MISC_STATUS 0x0000006c
++#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
++#define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
++#define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
++#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
++
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
++#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
++
++#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
++#define BNX2_PCICFG_REG_WINDOW 0x00000080
++#define BNX2_PCICFG_INT_ACK_CMD 0x00000084
++#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
++#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
++#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
++#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
++
++#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
++#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
++#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
++#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
++
++
++/*
++ * pci_reg definition
++ * offset: 0x400
++ */
++#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
++#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
++
++#define BNX2_PCI_CONFIG_1 0x00000404
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
++#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
++#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
++
++#define BNX2_PCI_CONFIG_2 0x00000408
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
++#define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
++#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
++#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
++#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
++#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
++#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
++#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
++#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
++#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
++#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
++#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
++#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
++#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
++
++#define BNX2_PCI_CONFIG_3 0x0000040c
++#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
++#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
++#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
++#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
++#define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
++#define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
++#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
++
++#define BNX2_PCI_PM_DATA_A 0x00000410
++#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
++#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
++#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
++#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
++
++#define BNX2_PCI_PM_DATA_B 0x00000414
++#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
++#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
++#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
++#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
++
++#define BNX2_PCI_SWAP_DIAG0 0x00000418
++#define BNX2_PCI_SWAP_DIAG1 0x0000041c
++#define BNX2_PCI_EXP_ROM_ADDR 0x00000420
++#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
++#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
++
++#define BNX2_PCI_EXP_ROM_DATA 0x00000424
++#define BNX2_PCI_VPD_INTF 0x00000428
++#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
++
++#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
++#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
++#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
++
++#define BNX2_PCI_VPD_DATA 0x00000430
++#define BNX2_PCI_ID_VAL1 0x00000434
++#define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
++#define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
++
++#define BNX2_PCI_ID_VAL2 0x00000438
++#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
++#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
++
++#define BNX2_PCI_ID_VAL3 0x0000043c
++#define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
++#define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
++
++#define BNX2_PCI_ID_VAL4 0x00000440
++#define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
++#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
++#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
++#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
++#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
++#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
++#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
++#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
++#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
++#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
++#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
++#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
++#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
++#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
++#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
++
++#define BNX2_PCI_ID_VAL5 0x00000444
++#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
++#define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
++#define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
++#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
++#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
++#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
++
++#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
++#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
++#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
++#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
++#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
++
++#define BNX2_PCI_ID_VAL6 0x0000044c
++#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
++#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
++#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
++
++#define BNX2_PCI_MSI_DATA 0x00000450
++#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
++
++#define BNX2_PCI_MSI_ADDR_H 0x00000454
++#define BNX2_PCI_MSI_ADDR_L 0x00000458
++
++
++/*
++ * misc_reg definition
++ * offset: 0x800
++ */
++#define BNX2_MISC_COMMAND 0x00000800
++#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
++#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
++#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
++#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
++#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
++#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
++
++#define BNX2_MISC_CFG 0x00000804
++#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
++#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
++#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
++#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
++#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
++#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
++#define BNX2_MISC_CFG_BIST_EN (1L<<3)
++#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
++#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
++#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
++#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
++#define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
++#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
++#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
++#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
++
++#define BNX2_MISC_ID 0x00000808
++#define BNX2_MISC_ID_BOND_ID (0xfL<<0)
++#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
++#define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
++#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
++
++#define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
++#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
++#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
++#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
++#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
++#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
++#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
++#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
++#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
++#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
++#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
++#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
++#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
++
++#define BNX2_MISC_ENABLE_SET_BITS 0x00000810
++#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
++#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
++#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
++#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
++#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
++#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
++#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
++#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
++#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
++#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
++#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
++#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
++#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
++#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
++
++#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
++#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
++#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
++#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
++#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
++#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
++#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
++#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
++#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
++#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
++#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
++#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
++#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
++#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
++
++#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
++#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
++
++#define BNX2_MISC_GPIO 0x0000081c
++#define BNX2_MISC_GPIO_VALUE (0xffL<<0)
++#define BNX2_MISC_GPIO_SET (0xffL<<8)
++#define BNX2_MISC_GPIO_CLR (0xffL<<16)
++#define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
++
++#define BNX2_MISC_GPIO_INT 0x00000820
++#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
++#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
++#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
++#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
++
++#define BNX2_MISC_CONFIG_LFSR 0x00000824
++#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
++
++#define BNX2_MISC_LFSR_MASK_BITS 0x00000828
++#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
++#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
++#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
++#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
++#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
++#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
++#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
++#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
++#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
++#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
++#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
++#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
++#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
++#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
++
++#define BNX2_MISC_ARB_REQ0 0x0000082c
++#define BNX2_MISC_ARB_REQ1 0x00000830
++#define BNX2_MISC_ARB_REQ2 0x00000834
++#define BNX2_MISC_ARB_REQ3 0x00000838
++#define BNX2_MISC_ARB_REQ4 0x0000083c
++#define BNX2_MISC_ARB_FREE0 0x00000840
++#define BNX2_MISC_ARB_FREE1 0x00000844
++#define BNX2_MISC_ARB_FREE2 0x00000848
++#define BNX2_MISC_ARB_FREE3 0x0000084c
++#define BNX2_MISC_ARB_FREE4 0x00000850
++#define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
++#define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
++#define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
++#define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
++#define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
++#define BNX2_MISC_ARB_GNT0 0x00000868
++#define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
++#define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
++#define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
++#define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
++#define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
++#define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
++#define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
++#define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
++
++#define BNX2_MISC_ARB_GNT1 0x0000086c
++#define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
++#define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
++#define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
++#define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
++#define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
++#define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
++#define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
++#define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
++
++#define BNX2_MISC_ARB_GNT2 0x00000870
++#define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
++#define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
++#define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
++#define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
++#define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
++#define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
++#define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
++#define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
++
++#define BNX2_MISC_ARB_GNT3 0x00000874
++#define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
++#define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
++#define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
++#define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
++#define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
++#define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
++#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
++#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
++
++#define BNX2_MISC_PRBS_CONTROL 0x00000878
++#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
++#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
++#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
++#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
++#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
++#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
++#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
++#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
++#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
++
++#define BNX2_MISC_PRBS_STATUS 0x0000087c
++#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
++#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
++#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
++#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
++
++#define BNX2_MISC_SM_ASF_CONTROL 0x00000880
++#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
++#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
++#define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
++#define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
++#define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
++#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
++#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
++#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
++#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
++#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
++#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
++#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
++
++#define BNX2_MISC_SMB_IN 0x00000884
++#define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
++#define BNX2_MISC_SMB_IN_RDY (1L<<8)
++#define BNX2_MISC_SMB_IN_DONE (1L<<9)
++#define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
++#define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
++#define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
++#define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
++#define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
++#define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
++#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
++
++#define BNX2_MISC_SMB_OUT 0x00000888
++#define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
++#define BNX2_MISC_SMB_OUT_RDY (1L<<8)
++#define BNX2_MISC_SMB_OUT_START (1L<<9)
++#define BNX2_MISC_SMB_OUT_LAST (1L<<10)
++#define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
++#define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
++#define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
++#define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
++#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
++
++#define BNX2_MISC_SMB_WATCHDOG 0x0000088c
++#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
++
++#define BNX2_MISC_SMB_HEARTBEAT 0x00000890
++#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
++
++#define BNX2_MISC_SMB_POLL_ASF 0x00000894
++#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
++
++#define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
++#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
++
++#define BNX2_MISC_SMB_RETRAN 0x0000089c
++#define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
++
++#define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
++#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
++
++#define BNX2_MISC_PERR_ENA0 0x000008a4
++#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
++#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
++#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
++#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
++#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
++#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
++#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
++#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
++#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
++#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
++#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
++#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
++#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
++#define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
++#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
++#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
++#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
++#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
++#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
++
++#define BNX2_MISC_PERR_ENA1 0x000008a8
++#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
++#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
++#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
++#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
++#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
++#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
++#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
++#define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
++#define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
++#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
++#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
++#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
++#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
++#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
++#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
++#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
++#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
++#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
++#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
++#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
++#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
++#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
++#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
++#define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
++#define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
++#define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
++#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
++#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
++#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
++#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
++#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
++#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
++
++#define BNX2_MISC_PERR_ENA2 0x000008ac
++#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
++#define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
++#define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
++#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
++#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
++#define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
++#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
++#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
++#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
++
++#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
++#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
++#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
++
++#define BNX2_MISC_VREG_CONTROL 0x000008b4
++#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
++#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
++
++#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
++#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
++
++#define BNX2_MISC_UNUSED0 0x000008bc
++
++
++/*
++ * nvm_reg definition
++ * offset: 0x6400
++ */
++#define BNX2_NVM_COMMAND 0x00006400
++#define BNX2_NVM_COMMAND_RST (1L<<0)
++#define BNX2_NVM_COMMAND_DONE (1L<<3)
++#define BNX2_NVM_COMMAND_DOIT (1L<<4)
++#define BNX2_NVM_COMMAND_WR (1L<<5)
++#define BNX2_NVM_COMMAND_ERASE (1L<<6)
++#define BNX2_NVM_COMMAND_FIRST (1L<<7)
++#define BNX2_NVM_COMMAND_LAST (1L<<8)
++#define BNX2_NVM_COMMAND_WREN (1L<<16)
++#define BNX2_NVM_COMMAND_WRDI (1L<<17)
++#define BNX2_NVM_COMMAND_EWSR (1L<<18)
++#define BNX2_NVM_COMMAND_WRSR (1L<<19)
++
++#define BNX2_NVM_STATUS 0x00006404
++#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
++#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
++#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
++
++#define BNX2_NVM_WRITE 0x00006408
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
++#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
++
++#define BNX2_NVM_ADDR 0x0000640c
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
++#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
++
++#define BNX2_NVM_READ 0x00006410
++#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
++#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
++
++#define BNX2_NVM_CFG1 0x00006414
++#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
++#define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
++#define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
++#define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
++#define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
++#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
++#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
++#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
++#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
++#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
++#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
++#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
++
++#define BNX2_NVM_CFG2 0x00006418
++#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
++#define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
++#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
++
++#define BNX2_NVM_CFG3 0x0000641c
++#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
++#define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
++#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
++#define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
++
++#define BNX2_NVM_SW_ARB 0x00006420
++#define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
++#define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
++#define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
++#define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
++#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
++#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
++#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
++#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
++#define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
++#define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
++#define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
++#define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
++#define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
++#define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
++#define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
++#define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
++
++#define BNX2_NVM_ACCESS_ENABLE 0x00006424
++#define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
++#define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
++
++#define BNX2_NVM_WRITE1 0x00006428
++#define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
++#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
++#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
++
++
++
++/*
++ * dma_reg definition
++ * offset: 0xc00
++ */
++#define BNX2_DMA_COMMAND 0x00000c00
++#define BNX2_DMA_COMMAND_ENABLE (1L<<0)
++
++#define BNX2_DMA_STATUS 0x00000c04
++#define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
++#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
++#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
++#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
++#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
++#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
++#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
++#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
++#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
++#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
++#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
++
++#define BNX2_DMA_CONFIG 0x00000c08
++#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
++#define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
++#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
++#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
++#define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
++#define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
++#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
++#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
++#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
++#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
++#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
++#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
++#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
++#define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
++#define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
++#define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
++#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
++#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
++#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
++
++#define BNX2_DMA_BLACKOUT 0x00000c0c
++#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
++#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
++#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
++
++#define BNX2_DMA_RCHAN_STAT 0x00000c30
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
++#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
++#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
++
++#define BNX2_DMA_WCHAN_STAT 0x00000c34
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
++#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
++#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
++
++#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
++#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
++#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
++
++#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
++#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
++#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
++
++#define BNX2_DMA_RCHAN_STAT_00 0x00000c40
++#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
++
++#define BNX2_DMA_RCHAN_STAT_01 0x00000c44
++#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
++
++#define BNX2_DMA_RCHAN_STAT_02 0x00000c48
++#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
++#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
++#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
++#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
++
++#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
++#define BNX2_DMA_RCHAN_STAT_11 0x00000c50
++#define BNX2_DMA_RCHAN_STAT_12 0x00000c54
++#define BNX2_DMA_RCHAN_STAT_20 0x00000c58
++#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
++#define BNX2_DMA_RCHAN_STAT_22 0x00000c60
++#define BNX2_DMA_RCHAN_STAT_30 0x00000c64
++#define BNX2_DMA_RCHAN_STAT_31 0x00000c68
++#define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
++#define BNX2_DMA_RCHAN_STAT_40 0x00000c70
++#define BNX2_DMA_RCHAN_STAT_41 0x00000c74
++#define BNX2_DMA_RCHAN_STAT_42 0x00000c78
++#define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
++#define BNX2_DMA_RCHAN_STAT_51 0x00000c80
++#define BNX2_DMA_RCHAN_STAT_52 0x00000c84
++#define BNX2_DMA_RCHAN_STAT_60 0x00000c88
++#define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
++#define BNX2_DMA_RCHAN_STAT_62 0x00000c90
++#define BNX2_DMA_RCHAN_STAT_70 0x00000c94
++#define BNX2_DMA_RCHAN_STAT_71 0x00000c98
++#define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
++#define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
++#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
++
++#define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
++#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
++
++#define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
++#define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
++#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
++#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
++#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
++
++#define BNX2_DMA_WCHAN_STAT_10 0x00000cac
++#define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
++#define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
++#define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
++#define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
++#define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
++#define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
++#define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
++#define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
++#define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
++#define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
++#define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
++#define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
++#define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
++#define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
++#define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
++#define BNX2_DMA_WCHAN_STAT_61 0x00000cec
++#define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
++#define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
++#define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
++#define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
++#define BNX2_DMA_ARB_STAT_00 0x00000d00
++#define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
++#define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
++#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
++
++#define BNX2_DMA_ARB_STAT_01 0x00000d04
++#define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
++#define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
++#define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
++#define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
++#define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
++#define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
++#define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
++#define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
++
++#define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
++#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
++#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
++#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
++#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
++#define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
++
++#define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
++#define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
++#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
++#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
++#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
++#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
++#define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
++
++#define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
++#define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
++#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
++#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
++#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
++#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
++#define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
++
++#define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
++
++
++/*
++ * context_reg definition
++ * offset: 0x1000
++ */
++#define BNX2_CTX_COMMAND 0x00001000
++#define BNX2_CTX_COMMAND_ENABLED (1L<<0)
++
++#define BNX2_CTX_STATUS 0x00001004
++#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
++#define BNX2_CTX_STATUS_READ_STAT (1L<<16)
++#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
++#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
++#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
++
++#define BNX2_CTX_VIRT_ADDR 0x00001008
++#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
++
++#define BNX2_CTX_PAGE_TBL 0x0000100c
++#define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
++
++#define BNX2_CTX_DATA_ADR 0x00001010
++#define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
++
++#define BNX2_CTX_DATA 0x00001014
++#define BNX2_CTX_LOCK 0x00001018
++#define BNX2_CTX_LOCK_TYPE (0x7L<<0)
++#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
++#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
++#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
++#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
++#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
++#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
++#define BNX2_CTX_LOCK_GRANTED (1L<<26)
++#define BNX2_CTX_LOCK_MODE (0x7L<<27)
++#define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
++#define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
++#define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
++#define BNX2_CTX_LOCK_STATUS (1L<<30)
++#define BNX2_CTX_LOCK_REQ (1L<<31)
++
++#define BNX2_CTX_ACCESS_STATUS 0x00001040
++#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
++#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
++#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
++#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
++#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
++
++#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
++#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
++#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
++
++#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
++#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
++#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
++#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
++
++#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
++#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
++#define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
++#define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
++#define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
++#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
++#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
++#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
++
++
++/*
++ * emac_reg definition
++ * offset: 0x1400
++ */
++#define BNX2_EMAC_MODE 0x00001400
++#define BNX2_EMAC_MODE_RESET (1L<<0)
++#define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
++#define BNX2_EMAC_MODE_PORT (0x3L<<2)
++#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
++#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
++#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
++#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
++#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
++#define BNX2_EMAC_MODE_25G (1L<<5)
++#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
++#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
++#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
++#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
++#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
++#define BNX2_EMAC_MODE_MPKT (1L<<18)
++#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
++#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
++
++#define BNX2_EMAC_STATUS 0x00001404
++#define BNX2_EMAC_STATUS_LINK (1L<<11)
++#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
++#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
++#define BNX2_EMAC_STATUS_MI_INT (1L<<23)
++#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
++#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
++
++#define BNX2_EMAC_ATTENTION_ENA 0x00001408
++#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
++#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
++#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
++#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
++
++#define BNX2_EMAC_LED 0x0000140c
++#define BNX2_EMAC_LED_OVERRIDE (1L<<0)
++#define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
++#define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
++#define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
++#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
++#define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
++#define BNX2_EMAC_LED_TRAFFIC (1L<<6)
++#define BNX2_EMAC_LED_1000MB (1L<<7)
++#define BNX2_EMAC_LED_100MB (1L<<8)
++#define BNX2_EMAC_LED_10MB (1L<<9)
++#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
++#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
++#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
++
++#define BNX2_EMAC_MAC_MATCH0 0x00001410
++#define BNX2_EMAC_MAC_MATCH1 0x00001414
++#define BNX2_EMAC_MAC_MATCH2 0x00001418
++#define BNX2_EMAC_MAC_MATCH3 0x0000141c
++#define BNX2_EMAC_MAC_MATCH4 0x00001420
++#define BNX2_EMAC_MAC_MATCH5 0x00001424
++#define BNX2_EMAC_MAC_MATCH6 0x00001428
++#define BNX2_EMAC_MAC_MATCH7 0x0000142c
++#define BNX2_EMAC_MAC_MATCH8 0x00001430
++#define BNX2_EMAC_MAC_MATCH9 0x00001434
++#define BNX2_EMAC_MAC_MATCH10 0x00001438
++#define BNX2_EMAC_MAC_MATCH11 0x0000143c
++#define BNX2_EMAC_MAC_MATCH12 0x00001440
++#define BNX2_EMAC_MAC_MATCH13 0x00001444
++#define BNX2_EMAC_MAC_MATCH14 0x00001448
++#define BNX2_EMAC_MAC_MATCH15 0x0000144c
++#define BNX2_EMAC_MAC_MATCH16 0x00001450
++#define BNX2_EMAC_MAC_MATCH17 0x00001454
++#define BNX2_EMAC_MAC_MATCH18 0x00001458
++#define BNX2_EMAC_MAC_MATCH19 0x0000145c
++#define BNX2_EMAC_MAC_MATCH20 0x00001460
++#define BNX2_EMAC_MAC_MATCH21 0x00001464
++#define BNX2_EMAC_MAC_MATCH22 0x00001468
++#define BNX2_EMAC_MAC_MATCH23 0x0000146c
++#define BNX2_EMAC_MAC_MATCH24 0x00001470
++#define BNX2_EMAC_MAC_MATCH25 0x00001474
++#define BNX2_EMAC_MAC_MATCH26 0x00001478
++#define BNX2_EMAC_MAC_MATCH27 0x0000147c
++#define BNX2_EMAC_MAC_MATCH28 0x00001480
++#define BNX2_EMAC_MAC_MATCH29 0x00001484
++#define BNX2_EMAC_MAC_MATCH30 0x00001488
++#define BNX2_EMAC_MAC_MATCH31 0x0000148c
++#define BNX2_EMAC_BACKOFF_SEED 0x00001498
++#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
++
++#define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
++#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
++#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
++
++#define BNX2_EMAC_SERDES_CNTL 0x000014a4
++#define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
++#define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
++#define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
++#define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
++#define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
++#define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
++#define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
++#define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
++#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
++#define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
++#define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
++#define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
++#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
++#define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
++#define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
++#define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
++
++#define BNX2_EMAC_SERDES_STATUS 0x000014a8
++#define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
++#define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
++
++#define BNX2_EMAC_MDIO_COMM 0x000014ac
++#define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
++#define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
++#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
++#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
++#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
++#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
++#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
++#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
++#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
++#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
++#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
++
++#define BNX2_EMAC_MDIO_STATUS 0x000014b0
++#define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
++#define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
++
++#define BNX2_EMAC_MDIO_MODE 0x000014b4
++#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
++#define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
++#define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
++#define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
++#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
++#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
++#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
++#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
++
++#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
++#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
++
++#define BNX2_EMAC_TX_MODE 0x000014bc
++#define BNX2_EMAC_TX_MODE_RESET (1L<<0)
++#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
++#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
++#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
++#define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
++#define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
++
++#define BNX2_EMAC_TX_STATUS 0x000014c0
++#define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
++#define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
++#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
++#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
++#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
++
++#define BNX2_EMAC_TX_LENGTHS 0x000014c4
++#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
++#define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
++#define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
++
++#define BNX2_EMAC_RX_MODE 0x000014c8
++#define BNX2_EMAC_RX_MODE_RESET (1L<<0)
++#define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
++#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
++#define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
++#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
++#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
++#define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
++#define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
++#define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
++#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
++#define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
++#define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
++
++#define BNX2_EMAC_RX_STATUS 0x000014cc
++#define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
++#define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
++#define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
++
++#define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
++#define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
++#define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
++#define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
++#define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
++#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
++#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
++#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
++#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
++#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
++#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
++#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
++#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
++#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
++#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
++#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
++#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
++#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
++#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
++#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
++#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
++#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
++#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
++#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
++#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
++#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
++#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
++#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
++#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
++#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
++#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
++#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
++#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
++
++#define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
++#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
++#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
++#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
++#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
++#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
++#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
++#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
++
++#define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
++#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
++#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
++
++#define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
++#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
++#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
++#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
++#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
++#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
++#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
++#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
++#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
++
++#define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
++#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
++#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
++#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
++#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
++#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
++#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
++#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
++#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
++#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
++#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
++
++#define BNX2_EMAC_RX_STAT_AC0 0x00001580
++#define BNX2_EMAC_RX_STAT_AC1 0x00001584
++#define BNX2_EMAC_RX_STAT_AC2 0x00001588
++#define BNX2_EMAC_RX_STAT_AC3 0x0000158c
++#define BNX2_EMAC_RX_STAT_AC4 0x00001590
++#define BNX2_EMAC_RX_STAT_AC5 0x00001594
++#define BNX2_EMAC_RX_STAT_AC6 0x00001598
++#define BNX2_EMAC_RX_STAT_AC7 0x0000159c
++#define BNX2_EMAC_RX_STAT_AC8 0x000015a0
++#define BNX2_EMAC_RX_STAT_AC9 0x000015a4
++#define BNX2_EMAC_RX_STAT_AC10 0x000015a8
++#define BNX2_EMAC_RX_STAT_AC11 0x000015ac
++#define BNX2_EMAC_RX_STAT_AC12 0x000015b0
++#define BNX2_EMAC_RX_STAT_AC13 0x000015b4
++#define BNX2_EMAC_RX_STAT_AC14 0x000015b8
++#define BNX2_EMAC_RX_STAT_AC15 0x000015bc
++#define BNX2_EMAC_RX_STAT_AC16 0x000015c0
++#define BNX2_EMAC_RX_STAT_AC17 0x000015c4
++#define BNX2_EMAC_RX_STAT_AC18 0x000015c8
++#define BNX2_EMAC_RX_STAT_AC19 0x000015cc
++#define BNX2_EMAC_RX_STAT_AC20 0x000015d0
++#define BNX2_EMAC_RX_STAT_AC21 0x000015d4
++#define BNX2_EMAC_RX_STAT_AC22 0x000015d8
++#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
++#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
++#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
++#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
++#define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
++#define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
++#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
++#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
++#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
++#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
++#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
++#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
++#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
++#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
++#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
++#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
++#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
++#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
++#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
++#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
++#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
++#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
++#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
++#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
++#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
++#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
++#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
++
++#define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
++#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
++#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
++#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
++
++#define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
++#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
++#define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
++#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
++#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
++
++#define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
++#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
++#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
++#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
++#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
++#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
++#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
++#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
++#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
++#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
++#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
++#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
++#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
++
++#define BNX2_EMAC_TX_STAT_AC0 0x00001680
++#define BNX2_EMAC_TX_STAT_AC1 0x00001684
++#define BNX2_EMAC_TX_STAT_AC2 0x00001688
++#define BNX2_EMAC_TX_STAT_AC3 0x0000168c
++#define BNX2_EMAC_TX_STAT_AC4 0x00001690
++#define BNX2_EMAC_TX_STAT_AC5 0x00001694
++#define BNX2_EMAC_TX_STAT_AC6 0x00001698
++#define BNX2_EMAC_TX_STAT_AC7 0x0000169c
++#define BNX2_EMAC_TX_STAT_AC8 0x000016a0
++#define BNX2_EMAC_TX_STAT_AC9 0x000016a4
++#define BNX2_EMAC_TX_STAT_AC10 0x000016a8
++#define BNX2_EMAC_TX_STAT_AC11 0x000016ac
++#define BNX2_EMAC_TX_STAT_AC12 0x000016b0
++#define BNX2_EMAC_TX_STAT_AC13 0x000016b4
++#define BNX2_EMAC_TX_STAT_AC14 0x000016b8
++#define BNX2_EMAC_TX_STAT_AC15 0x000016bc
++#define BNX2_EMAC_TX_STAT_AC16 0x000016c0
++#define BNX2_EMAC_TX_STAT_AC17 0x000016c4
++#define BNX2_EMAC_TX_STAT_AC18 0x000016c8
++#define BNX2_EMAC_TX_STAT_AC19 0x000016cc
++#define BNX2_EMAC_TX_STAT_AC20 0x000016d0
++#define BNX2_EMAC_TX_STAT_AC21 0x000016d4
++#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
++
++
++/*
++ * rpm_reg definition
++ * offset: 0x1800
++ */
++#define BNX2_RPM_COMMAND 0x00001800
++#define BNX2_RPM_COMMAND_ENABLED (1L<<0)
++#define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
++
++#define BNX2_RPM_STATUS 0x00001804
++#define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
++#define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
++
++#define BNX2_RPM_CONFIG 0x00001808
++#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
++#define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
++#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
++#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
++#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
++#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
++
++#define BNX2_RPM_VLAN_MATCH0 0x00001810
++#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
++
++#define BNX2_RPM_VLAN_MATCH1 0x00001814
++#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
++
++#define BNX2_RPM_VLAN_MATCH2 0x00001818
++#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
++
++#define BNX2_RPM_VLAN_MATCH3 0x0000181c
++#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
++
++#define BNX2_RPM_SORT_USER0 0x00001820
++#define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
++#define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
++#define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
++#define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
++#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
++#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
++#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
++#define BNX2_RPM_SORT_USER0_ENA (1L<<31)
++
++#define BNX2_RPM_SORT_USER1 0x00001824
++#define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
++#define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
++#define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
++#define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
++#define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
++#define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
++#define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
++#define BNX2_RPM_SORT_USER1_ENA (1L<<31)
++
++#define BNX2_RPM_SORT_USER2 0x00001828
++#define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
++#define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
++#define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
++#define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
++#define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
++#define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
++#define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
++#define BNX2_RPM_SORT_USER2_ENA (1L<<31)
++
++#define BNX2_RPM_SORT_USER3 0x0000182c
++#define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
++#define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
++#define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
++#define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
++#define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
++#define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
++#define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
++#define BNX2_RPM_SORT_USER3_ENA (1L<<31)
++
++#define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
++#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
++#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
++#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
++#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
++#define BNX2_RPM_STAT_AC0 0x00001880
++#define BNX2_RPM_STAT_AC1 0x00001884
++#define BNX2_RPM_STAT_AC2 0x00001888
++#define BNX2_RPM_STAT_AC3 0x0000188c
++#define BNX2_RPM_STAT_AC4 0x00001890
++#define BNX2_RPM_RC_CNTL_0 0x00001900
++#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
++#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
++#define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
++#define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
++#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
++#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
++#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
++#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
++#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
++#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
++#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
++#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
++#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
++#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
++#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
++#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
++#define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
++#define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
++#define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
++
++#define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
++#define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
++#define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
++
++#define BNX2_RPM_RC_CNTL_1 0x00001908
++#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
++#define BNX2_RPM_RC_CNTL_2 0x00001910
++#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
++#define BNX2_RPM_RC_CNTL_3 0x00001918
++#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
++#define BNX2_RPM_RC_CNTL_4 0x00001920
++#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
++#define BNX2_RPM_RC_CNTL_5 0x00001928
++#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
++#define BNX2_RPM_RC_CNTL_6 0x00001930
++#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
++#define BNX2_RPM_RC_CNTL_7 0x00001938
++#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
++#define BNX2_RPM_RC_CNTL_8 0x00001940
++#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
++#define BNX2_RPM_RC_CNTL_9 0x00001948
++#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
++#define BNX2_RPM_RC_CNTL_10 0x00001950
++#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
++#define BNX2_RPM_RC_CNTL_11 0x00001958
++#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
++#define BNX2_RPM_RC_CNTL_12 0x00001960
++#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
++#define BNX2_RPM_RC_CNTL_13 0x00001968
++#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
++#define BNX2_RPM_RC_CNTL_14 0x00001970
++#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
++#define BNX2_RPM_RC_CNTL_15 0x00001978
++#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
++#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
++
++#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
++#define BNX2_RPM_RC_CONFIG 0x00001980
++#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
++#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
++
++#define BNX2_RPM_DEBUG0 0x00001984
++#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
++#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
++#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
++#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
++#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
++#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
++#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
++#define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
++#define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
++#define BNX2_RPM_DEBUG0_DONE (1L<<24)
++#define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
++#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
++#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
++#define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
++#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
++
++#define BNX2_RPM_DEBUG1 0x00001988
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
++#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
++#define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
++#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
++#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
++#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
++#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
++
++#define BNX2_RPM_DEBUG2 0x0000198c
++#define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
++#define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
++#define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
++#define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
++#define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
++#define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
++#define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
++#define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
++#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
++#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
++
++#define BNX2_RPM_DEBUG3 0x00001990
++#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
++#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
++#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
++#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
++#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
++#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
++#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
++#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
++#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
++#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
++#define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
++#define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
++#define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
++#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
++#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
++#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
++#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
++#define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
++#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
++#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
++#define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
++#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
++#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
++#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
++
++#define BNX2_RPM_DEBUG4 0x00001994
++#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
++#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
++#define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
++#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
++
++#define BNX2_RPM_DEBUG5 0x00001998
++#define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
++#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
++#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
++#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
++#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
++#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
++#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
++#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
++#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
++#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
++#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
++#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
++#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
++#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
++#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
++#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
++
++#define BNX2_RPM_DEBUG6 0x0000199c
++#define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
++#define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
++
++#define BNX2_RPM_DEBUG7 0x000019a0
++#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
++
++#define BNX2_RPM_DEBUG8 0x000019a4
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
++#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
++#define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
++#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
++#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
++#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
++#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
++#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
++#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
++#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
++#define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
++#define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
++#define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
++#define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
++#define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
++#define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
++
++#define BNX2_RPM_DEBUG9 0x000019a8
++#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
++#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
++#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
++#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
++#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
++#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
++#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
++
++#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
++#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
++#define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
++#define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
++#define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
++#define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
++#define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
++#define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
++#define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
++#define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
++#define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
++#define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
++#define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
++#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
++#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
++#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
++
++
++/*
++ * rbuf_reg definition
++ * offset: 0x200000
++ */
++#define BNX2_RBUF_COMMAND 0x00200000
++#define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
++#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
++#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
++#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
++#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
++
++#define BNX2_RBUF_STATUS1 0x00200004
++#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
++
++#define BNX2_RBUF_STATUS2 0x00200008
++#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
++#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
++
++#define BNX2_RBUF_CONFIG 0x0020000c
++#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
++#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
++
++#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
++#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
++
++#define BNX2_RBUF_FW_BUF_FREE 0x00200014
++#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
++#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
++#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
++
++#define BNX2_RBUF_FW_BUF_SEL 0x00200018
++#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
++#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
++#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
++
++#define BNX2_RBUF_CONFIG2 0x0020001c
++#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
++#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
++
++#define BNX2_RBUF_CONFIG3 0x00200020
++#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
++#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
++
++#define BNX2_RBUF_PKT_DATA 0x00208000
++#define BNX2_RBUF_CLIST_DATA 0x00210000
++#define BNX2_RBUF_BUF_DATA 0x00220000
++
++
++/*
++ * rv2p_reg definition
++ * offset: 0x2800
++ */
++#define BNX2_RV2P_COMMAND 0x00002800
++#define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
++#define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
++#define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
++#define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
++#define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
++#define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
++#define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
++#define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
++#define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
++#define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
++#define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
++#define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
++
++#define BNX2_RV2P_STATUS 0x00002804
++#define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
++#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
++
++#define BNX2_RV2P_CONFIG 0x00002808
++#define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
++#define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
++#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
++#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
++#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
++
++#define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
++#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
++
++#define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
++#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
++
++#define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
++#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
++
++#define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
++#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
++
++#define BNX2_RV2P_INSTR_HIGH 0x00002830
++#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
++
++#define BNX2_RV2P_INSTR_LOW 0x00002834
++#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
++#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
++#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
++
++#define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
++#define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
++#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
++
++#define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
++#define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
++#define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
++#define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
++#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_RV2P_PFTQ_DATA 0x00002b40
++#define BNX2_RV2P_PFTQ_CMD 0x00002b78
++#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
++#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_RV2P_PFTQ_CTL 0x00002b7c
++#define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_RV2P_TFTQ_DATA 0x00002b80
++#define BNX2_RV2P_TFTQ_CMD 0x00002bb8
++#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
++#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_RV2P_TFTQ_CTL 0x00002bbc
++#define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_RV2P_MFTQ_DATA 0x00002bc0
++#define BNX2_RV2P_MFTQ_CMD 0x00002bf8
++#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
++#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_RV2P_MFTQ_CTL 0x00002bfc
++#define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++
++
++/*
++ * mq_reg definition
++ * offset: 0x3c00
++ */
++#define BNX2_MQ_COMMAND 0x00003c00
++#define BNX2_MQ_COMMAND_ENABLED (1L<<0)
++#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
++#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
++#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
++
++#define BNX2_MQ_STATUS 0x00003c04
++#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
++#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
++#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
++
++#define BNX2_MQ_CONFIG 0x00003c08
++#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
++#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
++#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
++#define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
++#define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
++
++#define BNX2_MQ_ENQUEUE1 0x00003c0c
++#define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
++#define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
++#define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
++#define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
++
++#define BNX2_MQ_ENQUEUE2 0x00003c10
++#define BNX2_MQ_BAD_WR_ADDR 0x00003c14
++#define BNX2_MQ_BAD_RD_ADDR 0x00003c18
++#define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
++#define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
++
++#define BNX2_MQ_KNL_WIND_END 0x00003c20
++#define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
++
++#define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
++#define BNX2_MQ_KNL_TX_MASK1 0x00003c28
++#define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
++#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
++#define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
++#define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
++#define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
++#define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
++#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
++#define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
++#define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
++#define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
++#define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
++#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
++#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
++#define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
++#define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
++#define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
++#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
++#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
++#define BNX2_MQ_MEM_WR_ADDR 0x00003c74
++#define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
++
++#define BNX2_MQ_MEM_WR_DATA0 0x00003c78
++#define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
++
++#define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
++#define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
++
++#define BNX2_MQ_MEM_WR_DATA2 0x00003c80
++#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
++
++#define BNX2_MQ_MEM_RD_ADDR 0x00003c84
++#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
++
++#define BNX2_MQ_MEM_RD_DATA0 0x00003c88
++#define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
++
++#define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
++#define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
++
++#define BNX2_MQ_MEM_RD_DATA2 0x00003c90
++#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
++
++
++
++/*
++ * tbdr_reg definition
++ * offset: 0x5000
++ */
++#define BNX2_TBDR_COMMAND 0x00005000
++#define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
++#define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
++#define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
++
++#define BNX2_TBDR_STATUS 0x00005004
++#define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
++#define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
++#define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
++#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
++#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
++#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
++#define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
++
++#define BNX2_TBDR_CONFIG 0x00005008
++#define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
++#define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
++#define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
++#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
++#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
++
++#define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
++#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_TBDR_FTQ_DATA 0x000053c0
++#define BNX2_TBDR_FTQ_CMD 0x000053f8
++#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
++#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_TBDR_FTQ_CTL 0x000053fc
++#define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++
++
++/*
++ * tdma_reg definition
++ * offset: 0x5c00
++ */
++#define BNX2_TDMA_COMMAND 0x00005c00
++#define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
++#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
++#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
++
++#define BNX2_TDMA_STATUS 0x00005c04
++#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
++#define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
++#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
++#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
++#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
++#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
++
++#define BNX2_TDMA_CONFIG 0x00005c08
++#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
++#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
++#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
++#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
++#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
++#define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
++#define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
++#define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
++#define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
++#define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
++#define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
++#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
++#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
++#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
++#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
++
++#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
++#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
++
++#define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
++#define BNX2_TDMA_DBG_TRIGGER 0x00005c14
++#define BNX2_TDMA_DMAD_FSM 0x00005c80
++#define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
++#define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
++#define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
++#define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
++#define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
++#define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
++#define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
++
++#define BNX2_TDMA_DMAD_STATUS 0x00005c84
++#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
++#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
++#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
++#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
++
++#define BNX2_TDMA_DR_INTF_FSM 0x00005c88
++#define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
++#define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
++#define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
++#define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
++#define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
++
++#define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
++#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
++#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
++#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
++#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
++#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
++
++#define BNX2_TDMA_FTQ_DATA 0x00005fc0
++#define BNX2_TDMA_FTQ_CMD 0x00005ff8
++#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
++#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_TDMA_FTQ_CTL 0x00005ffc
++#define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++
++
++/*
++ * hc_reg definition
++ * offset: 0x6800
++ */
++#define BNX2_HC_COMMAND 0x00006800
++#define BNX2_HC_COMMAND_ENABLE (1L<<0)
++#define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
++#define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
++#define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
++#define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
++#define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
++#define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
++#define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
++#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
++#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
++#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
++
++#define BNX2_HC_STATUS 0x00006804
++#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
++#define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
++#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
++#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
++#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
++#define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
++#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
++#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
++#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
++#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
++
++#define BNX2_HC_CONFIG 0x00006808
++#define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
++#define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
++#define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
++#define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
++#define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
++#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
++#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
++#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
++
++#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
++#define BNX2_HC_STATUS_ADDR_L 0x00006810
++#define BNX2_HC_STATUS_ADDR_H 0x00006814
++#define BNX2_HC_STATISTICS_ADDR_L 0x00006818
++#define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
++#define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
++#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
++#define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
++
++#define BNX2_HC_COMP_PROD_TRIP 0x00006824
++#define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
++#define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
++
++#define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
++#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
++#define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
++
++#define BNX2_HC_RX_TICKS 0x0000682c
++#define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
++#define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
++
++#define BNX2_HC_TX_TICKS 0x00006830
++#define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
++#define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
++
++#define BNX2_HC_COM_TICKS 0x00006834
++#define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
++#define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
++
++#define BNX2_HC_CMD_TICKS 0x00006838
++#define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
++#define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
++
++#define BNX2_HC_PERIODIC_TICKS 0x0000683c
++#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
++
++#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
++#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
++
++#define BNX2_HC_STATS_TICKS 0x00006844
++#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
++
++#define BNX2_HC_STAT_MEM_DATA 0x0000684c
++#define BNX2_HC_STAT_GEN_SEL_0 0x00006850
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
++#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
++
++#define BNX2_HC_STAT_GEN_SEL_1 0x00006854
++#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
++#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
++#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
++#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
++
++#define BNX2_HC_STAT_GEN_SEL_2 0x00006858
++#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
++#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
++#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
++#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
++
++#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
++#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
++#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
++#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
++#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
++
++#define BNX2_HC_STAT_GEN_STAT0 0x00006888
++#define BNX2_HC_STAT_GEN_STAT1 0x0000688c
++#define BNX2_HC_STAT_GEN_STAT2 0x00006890
++#define BNX2_HC_STAT_GEN_STAT3 0x00006894
++#define BNX2_HC_STAT_GEN_STAT4 0x00006898
++#define BNX2_HC_STAT_GEN_STAT5 0x0000689c
++#define BNX2_HC_STAT_GEN_STAT6 0x000068a0
++#define BNX2_HC_STAT_GEN_STAT7 0x000068a4
++#define BNX2_HC_STAT_GEN_STAT8 0x000068a8
++#define BNX2_HC_STAT_GEN_STAT9 0x000068ac
++#define BNX2_HC_STAT_GEN_STAT10 0x000068b0
++#define BNX2_HC_STAT_GEN_STAT11 0x000068b4
++#define BNX2_HC_STAT_GEN_STAT12 0x000068b8
++#define BNX2_HC_STAT_GEN_STAT13 0x000068bc
++#define BNX2_HC_STAT_GEN_STAT14 0x000068c0
++#define BNX2_HC_STAT_GEN_STAT15 0x000068c4
++#define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
++#define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
++#define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
++#define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
++#define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
++#define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
++#define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
++#define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
++#define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
++#define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
++#define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
++#define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
++#define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
++#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
++#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
++#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
++#define BNX2_HC_VIS 0x00006908
++#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
++#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
++#define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
++#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
++#define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
++#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
++#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
++#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
++#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
++
++#define BNX2_HC_VIS_1 0x0000690c
++#define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
++#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
++#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
++#define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
++#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
++#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
++#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
++#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
++#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
++#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
++#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
++#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
++#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
++#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
++#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
++#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
++#define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
++#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
++#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
++#define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
++#define BNX2_HC_VIS_1_INT_B (1L<<27)
++
++#define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
++#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++
++
++/*
++ * txp_reg definition
++ * offset: 0x40000
++ */
++#define BNX2_TXP_CPU_MODE 0x00045000
++#define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_TXP_CPU_STATE 0x00045004
++#define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_TXP_CPU_EVENT_MASK 0x00045008
++#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
++#define BNX2_TXP_CPU_INSTRUCTION 0x00045020
++#define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
++#define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
++#define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
++#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
++#define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
++#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
++#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_TXP_CPU_REG_FILE 0x00045200
++#define BNX2_TXP_FTQ_DATA 0x000453c0
++#define BNX2_TXP_FTQ_CMD 0x000453f8
++#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_TXP_FTQ_CMD_POP (1L<<30)
++#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_TXP_FTQ_CTL 0x000453fc
++#define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_TXP_SCRATCH 0x00060000
++
++
++/*
++ * tpat_reg definition
++ * offset: 0x80000
++ */
++#define BNX2_TPAT_CPU_MODE 0x00085000
++#define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_TPAT_CPU_STATE 0x00085004
++#define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
++#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
++#define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
++#define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
++#define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
++#define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
++#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
++#define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
++#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
++#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_TPAT_CPU_REG_FILE 0x00085200
++#define BNX2_TPAT_FTQ_DATA 0x000853c0
++#define BNX2_TPAT_FTQ_CMD 0x000853f8
++#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
++#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_TPAT_FTQ_CTL 0x000853fc
++#define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_TPAT_SCRATCH 0x000a0000
++
++
++/*
++ * rxp_reg definition
++ * offset: 0xc0000
++ */
++#define BNX2_RXP_CPU_MODE 0x000c5000
++#define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_RXP_CPU_STATE 0x000c5004
++#define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
++#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
++#define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
++#define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
++#define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
++#define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
++#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
++#define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
++#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
++#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_RXP_CPU_REG_FILE 0x000c5200
++#define BNX2_RXP_CFTQ_DATA 0x000c5380
++#define BNX2_RXP_CFTQ_CMD 0x000c53b8
++#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
++#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_RXP_CFTQ_CTL 0x000c53bc
++#define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_RXP_FTQ_DATA 0x000c53c0
++#define BNX2_RXP_FTQ_CMD 0x000c53f8
++#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_RXP_FTQ_CMD_POP (1L<<30)
++#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_RXP_FTQ_CTL 0x000c53fc
++#define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_RXP_SCRATCH 0x000e0000
++
++
++/*
++ * com_reg definition
++ * offset: 0x100000
++ */
++#define BNX2_COM_CPU_MODE 0x00105000
++#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_COM_CPU_STATE 0x00105004
++#define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_COM_CPU_EVENT_MASK 0x00105008
++#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
++#define BNX2_COM_CPU_INSTRUCTION 0x00105020
++#define BNX2_COM_CPU_DATA_ACCESS 0x00105024
++#define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
++#define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
++#define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
++#define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
++#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
++#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_COM_CPU_REG_FILE 0x00105200
++#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
++#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
++#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
++#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
++#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
++#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
++#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
++#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
++#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
++#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
++#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
++#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
++#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_COM_SCRATCH 0x00120000
++
++#define BNX2_FW_RX_DROP_COUNT 0x00120084
++
++
++/*
++ * cp_reg definition
++ * offset: 0x180000
++ */
++#define BNX2_CP_CPU_MODE 0x00185000
++#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_CP_CPU_STATE 0x00185004
++#define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_CP_CPU_EVENT_MASK 0x00185008
++#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
++#define BNX2_CP_CPU_INSTRUCTION 0x00185020
++#define BNX2_CP_CPU_DATA_ACCESS 0x00185024
++#define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
++#define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
++#define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
++#define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
++#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
++#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_CP_CPU_REG_FILE 0x00185200
++#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
++#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
++#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
++#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
++#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_CP_SCRATCH 0x001a0000
++
++
++/*
++ * mcp_reg definition
++ * offset: 0x140000
++ */
++#define BNX2_MCP_CPU_MODE 0x00145000
++#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
++#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
++#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
++#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
++#define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
++#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
++#define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
++#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
++#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
++#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
++#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
++
++#define BNX2_MCP_CPU_STATE 0x00145004
++#define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
++#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
++#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
++#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
++#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
++#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
++#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
++#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
++#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
++#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
++#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
++#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
++#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
++#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
++
++#define BNX2_MCP_CPU_EVENT_MASK 0x00145008
++#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
++#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
++#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
++#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
++#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
++#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
++#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
++#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
++#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
++#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
++#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
++
++#define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
++#define BNX2_MCP_CPU_INSTRUCTION 0x00145020
++#define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
++#define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
++#define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
++#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
++#define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
++#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
++#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
++
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
++#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
++
++#define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
++#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
++#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
++#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
++#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
++
++#define BNX2_MCP_CPU_REG_FILE 0x00145200
++#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
++#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
++#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
++#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
++#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
++#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
++#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
++#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
++#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
++#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
++#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
++#define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
++#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
++
++#define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
++#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
++#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
++#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
++#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
++#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
++
++#define BNX2_MCP_ROM 0x00150000
++#define BNX2_MCP_SCRATCH 0x00160000
++
++#define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
++#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
++#define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
++#define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
++#define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
++
++#define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
++#define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
++
++
++#define NUM_MC_HASH_REGISTERS 8
++
++
++/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
++#define PHY_BCM5706_PHY_ID 0x00206160
++
++#define PHY_ID(id) ((id) & 0xfffffff0)
++#define PHY_REV_ID(id) ((id) & 0xf)
++
++/* 5708 Serdes PHY registers */
++
++#define BCM5708S_UP1 0xb
++
++#define BCM5708S_UP1_2G5 0x1
++
++#define BCM5708S_BLK_ADDR 0x1f
++
++#define BCM5708S_BLK_ADDR_DIG 0x0000
++#define BCM5708S_BLK_ADDR_DIG3 0x0002
++#define BCM5708S_BLK_ADDR_TX_MISC 0x0005
++
++/* Digital Block */
++#define BCM5708S_1000X_CTL1 0x10
++
++#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
++#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
++
++#define BCM5708S_1000X_CTL2 0x11
++
++#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
++
++#define BCM5708S_1000X_STAT1 0x14
++
++#define BCM5708S_1000X_STAT1_SGMII 0x0001
++#define BCM5708S_1000X_STAT1_LINK 0x0002
++#define BCM5708S_1000X_STAT1_FD 0x0004
++#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
++#define BCM5708S_1000X_STAT1_SPEED_10 0x0000
++#define BCM5708S_1000X_STAT1_SPEED_100 0x0008
++#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
++#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
++#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
++#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
++
++/* Digital3 Block */
++#define BCM5708S_DIG_3_0 0x10
++
++#define BCM5708S_DIG_3_0_USE_IEEE 0x0001
++
++/* Tx/Misc Block */
++#define BCM5708S_TX_ACTL1 0x15
++
++#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
++
++#define BCM5708S_TX_ACTL3 0x17
++
++#define MIN_ETHERNET_PACKET_SIZE 60
++#define MAX_ETHERNET_PACKET_SIZE 1514
++#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
++
++#define RX_COPY_THRESH 92
++
++#define DMA_READ_CHANS 5
++#define DMA_WRITE_CHANS 3
++
++#define BCM_PAGE_BITS 12
++#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
++
++#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
++#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
++
++#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
++#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
++
++#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
++ (MAX_TX_DESC_CNT - 1)) ? \
++ (x) + 2 : (x) + 1
++
++#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
++
++#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
++ (MAX_RX_DESC_CNT - 1)) ? \
++ (x) + 2 : (x) + 1
++
++#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT)
++
++
++/* Context size. */
++#define CTX_SHIFT 7
++#define CTX_SIZE (1 << CTX_SHIFT)
++#define CTX_MASK (CTX_SIZE - 1)
++#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
++#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
++
++#define PHY_CTX_SHIFT 6
++#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
++#define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
++#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
++#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
++
++#define MB_KERNEL_CTX_SHIFT 8
++#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
++#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
++#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
++
++#define MAX_CID_CNT 0x4000
++#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
++#define INVALID_CID_ADDR 0xffffffff
++
++#define TX_CID 16
++#define RX_CID 0
++
++#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
++#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
++
++struct sw_bd {
++ struct sk_buff *skb;
++ DECLARE_PCI_UNMAP_ADDR(mapping)
++};
++
++/* Buffered flash (Atmel: AT45DB011B) specific information */
++#define SEEPROM_PAGE_BITS 2
++#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
++#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
++#define SEEPROM_PAGE_SIZE 4
++#define SEEPROM_TOTAL_SIZE 65536
++
++#define BUFFERED_FLASH_PAGE_BITS 9
++#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
++#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
++#define BUFFERED_FLASH_PAGE_SIZE 264
++#define BUFFERED_FLASH_TOTAL_SIZE 0x21000
++
++#define SAIFUN_FLASH_PAGE_BITS 8
++#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
++#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
++#define SAIFUN_FLASH_PAGE_SIZE 256
++#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
++
++#define ST_MICRO_FLASH_PAGE_BITS 8
++#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
++#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
++#define ST_MICRO_FLASH_PAGE_SIZE 256
++#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
++
++#define NVRAM_TIMEOUT_COUNT 30000
++
++
++#define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
++ BNX2_NVM_CFG1_BUFFER_MODE | \
++ BNX2_NVM_CFG1_PROTECT_MODE | \
++ BNX2_NVM_CFG1_FLASH_SIZE)
++
++#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
++
++struct flash_spec {
++ u32 strapping;
++ u32 config1;
++ u32 config2;
++ u32 config3;
++ u32 write1;
++ u32 buffered;
++ u32 page_bits;
++ u32 page_size;
++ u32 addr_mask;
++ u32 total_size;
++ u8 *name;
++};
++
++struct bnx2 {
++ /* Fields used in the tx and intr/napi performance paths are grouped */
++ /* together in the beginning of the structure. */
++ void *regview;
++
++ struct net_device *dev;
++ struct pci_dev *pdev;
++
++ atomic_t intr_sem;
++
++ struct status_block *status_blk;
++ u32 last_status_idx;
++
++ /* Put tx producer and consumer fields in separate cache lines. */
++
++ u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
++ u16 tx_prod;
++
++ struct tx_bd *tx_desc_ring;
++ struct sw_bd *tx_buf_ring;
++ int tx_ring_size;
++
++ u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
++ u16 hw_tx_cons;
++
++#ifdef BCM_VLAN
++ struct vlan_group *vlgrp;
++#endif
++
++ u32 rx_offset;
++ u32 rx_buf_use_size; /* useable size */
++ u32 rx_buf_size; /* with alignment */
++ struct rx_bd *rx_desc_ring;
++ struct sw_bd *rx_buf_ring;
++ u32 rx_prod_bseq;
++ u16 rx_prod;
++ u16 rx_cons;
++ u16 hw_rx_cons;
++
++ u32 rx_csum;
++
++ /* Only used to synchronize netif_stop_queue/wake_queue when tx */
++ /* ring is full */
++ spinlock_t tx_lock;
++
++ /* End of fileds used in the performance code paths. */
++
++ char *name;
++
++ int timer_interval;
++ int current_interval;
++ struct timer_list timer;
++ struct work_struct reset_task;
++ int in_reset_task;
++
++ /* Used to synchronize phy accesses. */
++ spinlock_t phy_lock;
++
++ u32 flags;
++#define PCIX_FLAG 1
++#define PCI_32BIT_FLAG 2
++#define ONE_TDMA_FLAG 4 /* no longer used */
++#define NO_WOL_FLAG 8
++#define USING_DAC_FLAG 0x10
++#define USING_MSI_FLAG 0x20
++#define ASF_ENABLE_FLAG 0x40
++
++ u32 phy_flags;
++#define PHY_SERDES_FLAG 1
++#define PHY_CRC_FIX_FLAG 2
++#define PHY_PARALLEL_DETECT_FLAG 4
++#define PHY_2_5G_CAPABLE_FLAG 8
++#define PHY_INT_MODE_MASK_FLAG 0x300
++#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
++#define PHY_INT_MODE_LINK_READY_FLAG 0x200
++
++ u32 chip_id;
++ /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
++#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
++#define CHIP_NUM_5706 0x57060000
++#define CHIP_NUM_5708 0x57080000
++
++#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
++#define CHIP_REV_Ax 0x00000000
++#define CHIP_REV_Bx 0x00001000
++#define CHIP_REV_Cx 0x00002000
++
++#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
++#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
++
++#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
++#define CHIP_ID_5706_A0 0x57060000
++#define CHIP_ID_5706_A1 0x57060010
++#define CHIP_ID_5706_A2 0x57060020
++#define CHIP_ID_5708_A0 0x57080000
++#define CHIP_ID_5708_B0 0x57081000
++#define CHIP_ID_5708_B1 0x57081010
++
++#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
++
++/* A serdes chip will have the first bit of the bond id set. */
++#define CHIP_BOND_ID_SERDES_BIT 0x01
++
++ u32 phy_addr;
++ u32 phy_id;
++
++ u16 bus_speed_mhz;
++ u8 wol;
++
++ u8 pad;
++
++ u16 fw_wr_seq;
++ u16 fw_drv_pulse_wr_seq;
++
++ dma_addr_t tx_desc_mapping;
++
++
++ int rx_ring_size;
++ dma_addr_t rx_desc_mapping;
++
++ u16 tx_quick_cons_trip;
++ u16 tx_quick_cons_trip_int;
++ u16 rx_quick_cons_trip;
++ u16 rx_quick_cons_trip_int;
++ u16 comp_prod_trip;
++ u16 comp_prod_trip_int;
++ u16 tx_ticks;
++ u16 tx_ticks_int;
++ u16 com_ticks;
++ u16 com_ticks_int;
++ u16 cmd_ticks;
++ u16 cmd_ticks_int;
++ u16 rx_ticks;
++ u16 rx_ticks_int;
++
++ u32 stats_ticks;
++
++ dma_addr_t status_blk_mapping;
++
++ struct statistics_block *stats_blk;
++ dma_addr_t stats_blk_mapping;
++
++ u32 hc_cmd;
++ u32 rx_mode;
++
++ u16 req_line_speed;
++ u8 req_duplex;
++
++ u8 link_up;
++
++ u16 line_speed;
++ u8 duplex;
++ u8 flow_ctrl; /* actual flow ctrl settings */
++ /* may be different from */
++ /* req_flow_ctrl if autoneg */
++#define FLOW_CTRL_TX 1
++#define FLOW_CTRL_RX 2
++
++ u32 advertising;
++
++ u8 req_flow_ctrl; /* flow ctrl advertisement */
++ /* settings or forced */
++ /* settings */
++ u8 autoneg;
++#define AUTONEG_SPEED 1
++#define AUTONEG_FLOW_CTRL 2
++
++ u8 loopback;
++#define MAC_LOOPBACK 1
++#define PHY_LOOPBACK 2
++
++ u8 serdes_an_pending;
++#define SERDES_AN_TIMEOUT (HZ / 3)
++
++ u8 mac_addr[8];
++
++ u32 shmem_base;
++
++ u32 fw_ver;
++
++ int pm_cap;
++ int pcix_cap;
++
++ struct net_device_stats net_stats;
++
++ struct flash_spec *flash_info;
++ u32 flash_size;
++
++ struct z_stream_s *strm;
++ void *gunzip_buf;
++};
++
++static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
++static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
++
++#define REG_RD(bp, offset) \
++ readl(bp->regview + offset)
++
++#define REG_WR(bp, offset, val) \
++ writel(val, bp->regview + offset)
++
++#define REG_WR16(bp, offset, val) \
++ writew(val, bp->regview + offset)
++
++#define REG_RD_IND(bp, offset) \
++ bnx2_reg_rd_ind(bp, offset)
++
++#define REG_WR_IND(bp, offset, val) \
++ bnx2_reg_wr_ind(bp, offset, val)
++
++/* Indirect context access. Unlike the MBQ_WR, these macros will not
++ * trigger a chip event. */
++static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
++
++#define CTX_WR(bp, cid_addr, offset, val) \
++ bnx2_ctx_wr(bp, cid_addr, offset, val)
++
++struct cpu_reg {
++ u32 mode;
++ u32 mode_value_halt;
++ u32 mode_value_sstep;
++
++ u32 state;
++ u32 state_value_clear;
++
++ u32 gpr0;
++ u32 evmask;
++ u32 pc;
++ u32 inst;
++ u32 bp;
++
++ u32 spad_base;
++
++ u32 mips_view_base;
++};
++
++struct fw_info {
++ u32 ver_major;
++ u32 ver_minor;
++ u32 ver_fix;
++
++ u32 start_addr;
++
++ /* Text section. */
++ u32 text_addr;
++ u32 text_len;
++ u32 text_index;
++ u32 *text;
++
++ /* Data section. */
++ u32 data_addr;
++ u32 data_len;
++ u32 data_index;
++ u32 *data;
++
++ /* SBSS section. */
++ u32 sbss_addr;
++ u32 sbss_len;
++ u32 sbss_index;
++ u32 *sbss;
++
++ /* BSS section. */
++ u32 bss_addr;
++ u32 bss_len;
++ u32 bss_index;
++ u32 *bss;
++
++ /* Read-only section. */
++ u32 rodata_addr;
++ u32 rodata_len;
++ u32 rodata_index;
++ u32 *rodata;
++};
++
++#define RV2P_PROC1 0
++#define RV2P_PROC2 1
++
++
++/* This value (in milliseconds) determines the frequency of the driver
++ * issuing the PULSE message code. The firmware monitors this periodic
++ * pulse to determine when to switch to an OS-absent mode. */
++#define DRV_PULSE_PERIOD_MS 250
++
++/* This value (in milliseconds) determines how long the driver should
++ * wait for an acknowledgement from the firmware before timing out. Once
++ * the firmware has timed out, the driver will assume there is no firmware
++ * running and there won't be any firmware-driver synchronization during a
++ * driver reset. */
++#define FW_ACK_TIME_OUT_MS 100
++
++
++#define BNX2_DRV_RESET_SIGNATURE 0x00000000
++#define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
++//#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
++
++#define BNX2_DRV_MB 0x00000004
++#define BNX2_DRV_MSG_CODE 0xff000000
++#define BNX2_DRV_MSG_CODE_RESET 0x01000000
++#define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
++#define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
++#define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
++#define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
++#define BNX2_DRV_MSG_CODE_PULSE 0x06000000
++#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
++#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
++#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
++
++#define BNX2_DRV_MSG_DATA 0x00ff0000
++#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
++#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
++#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
++#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
++
++#define BNX2_DRV_MSG_SEQ 0x0000ffff
++
++#define BNX2_FW_MB 0x00000008
++#define BNX2_FW_MSG_ACK 0x0000ffff
++#define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
++#define BNX2_FW_MSG_STATUS_OK 0x00000000
++#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
++
++#define BNX2_LINK_STATUS 0x0000000c
++#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
++#define BNX2_LINK_STATUS_LINK_UP 0x1
++#define BNX2_LINK_STATUS_LINK_DOWN 0x0
++#define BNX2_LINK_STATUS_SPEED_MASK 0x1e
++#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
++#define BNX2_LINK_STATUS_10HALF (1<<1)
++#define BNX2_LINK_STATUS_10FULL (2<<1)
++#define BNX2_LINK_STATUS_100HALF (3<<1)
++#define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
++#define BNX2_LINK_STATUS_100FULL (5<<1)
++#define BNX2_LINK_STATUS_1000HALF (6<<1)
++#define BNX2_LINK_STATUS_1000FULL (7<<1)
++#define BNX2_LINK_STATUS_2500HALF (8<<1)
++#define BNX2_LINK_STATUS_2500FULL (9<<1)
++#define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
++#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
++#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
++#define BNX2_LINK_STATUS_RESERVED (1<<8)
++#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
++#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
++#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
++#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
++#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
++#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
++#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
++#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
++#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
++#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
++#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
++#define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
++#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
++#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
++
++#define BNX2_DRV_PULSE_MB 0x00000010
++#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
++
++/* Indicate to the firmware not to go into the
++ * OS absent when it is not getting driver pulse.
++ * This is used for debugging. */
++#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
++
++#define BNX2_DEV_INFO_SIGNATURE 0x00000020
++#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
++#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
++#define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
++#define BNX2_DEV_INFO_SECONDARY_PORT 0x80
++#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
++
++#define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
++
++#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
++#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
++#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
++#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
++#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
++
++#define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
++#define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
++#define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
++#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
++#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
++#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
++#define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
++#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
++#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
++#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
++#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
++#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
++#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
++
++#define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
++#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
++
++#define BNX2_DEV_INFO_BC_REV 0x0000004c
++
++#define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
++#define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
++
++#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
++#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
++#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
++#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
++#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
++#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
++#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
++
++#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
++#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
++#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
++#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
++#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
++#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
++
++#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
++
++#define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
++#define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
++#define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
++
++#define BNX2_SHARED_FEATURE 0x000000c8
++#define BNX2_SHARED_FEATURE_MASK 0xffffffff
++
++#define BNX2_PORT_FEATURE 0x000000d8
++#define BNX2_PORT2_FEATURE 0x00000014c
++#define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
++#define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
++#define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
++#define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
++#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
++#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
++#define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
++#define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
++#define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
++#define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
++#define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
++#define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
++#define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
++#define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
++#define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
++#define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
++#define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
++#define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
++#define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
++#define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
++#define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
++
++#define BNX2_PORT_FEATURE_WOL 0xdc
++#define BNX2_PORT2_FEATURE_WOL 0x150
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
++#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
++#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
++#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
++#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
++#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
++
++#define BNX2_PORT_FEATURE_MBA 0xe0
++#define BNX2_PORT2_FEATURE_MBA 0x154
++#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
++#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
++#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
++#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
++#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
++#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
++#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
++#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
++#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
++#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
++#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
++#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
++#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
++
++#define BNX2_PORT_FEATURE_IMD 0xe4
++#define BNX2_PORT2_FEATURE_IMD 0x158
++#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
++#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
++
++#define BNX2_PORT_FEATURE_VLAN 0xe8
++#define BNX2_PORT2_FEATURE_VLAN 0x15c
++#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
++#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
++
++#define BNX2_BC_STATE_RESET_TYPE 0x000001c0
++#define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
++#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
++#define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ 0x00010000)
++#define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ 0x00020000)
++#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ 0x00030000)
++#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
++#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ DRV_MSG_CODE_RESET)
++#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ DRV_MSG_CODE_UNLOAD)
++#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ DRV_MSG_CODE_SHUTDOWN)
++#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ DRV_MSG_CODE_WOL)
++#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ DRV_MSG_CODE_DIAG)
++#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
++ (msg))
++
++#define BNX2_BC_STATE 0x000001c4
++#define BNX2_BC_STATE_ERR_MASK 0x0000ff00
++#define BNX2_BC_STATE_SIGN 0x42530000
++#define BNX2_BC_STATE_SIGN_MASK 0xffff0000
++#define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
++#define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
++#define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
++#define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
++#define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
++#define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
++#define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
++#define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
++#define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
++#define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
++#define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
++#define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
++#define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
++#define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
++#define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
++#define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
++#define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
++#define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
++#define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
++#define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
++#define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
++#define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
++#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
++#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
++#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
++
++#define BNX2_BC_STATE_DEBUG_CMD 0x1dc
++#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
++#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
++#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
++#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
++
++#define HOST_VIEW_SHMEM_BASE 0x167c00
++
++#endif
+diff -urN kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2_fw.h kernel-source-2.6.8-2.6.8/drivers/net/bnx2_fw.h
+--- kernel-source-2.6.8-2.6.8.orig/drivers/net/bnx2_fw.h 1969-12-31 17:00:00.000000000 -0700
++++ kernel-source-2.6.8-2.6.8/drivers/net/bnx2_fw.h 2006-09-19 17:53:01.339160000 -0600
+@@ -0,0 +1,1966 @@
++/* bnx2_fw.h: Broadcom NX2 network driver.
++ *
++ * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, except as noted below.
++ *
++ * This file contains firmware data derived from proprietary unpublished
++ * source code, Copyright (c) 2004, 2005, 2006 Broadcom Corporation.
++ *
++ * Permission is hereby granted for the distribution of this firmware data
++ * in hexadecimal or equivalent format, provided this copyright notice is
++ * accompanying it.
++ */
++
++static int bnx2_COM_b06FwReleaseMajor = 0x1;
++static int bnx2_COM_b06FwReleaseMinor = 0x0;
++static int bnx2_COM_b06FwReleaseFix = 0x0;
++static u32 bnx2_COM_b06FwStartAddr = 0x080008b4;
++static u32 bnx2_COM_b06FwTextAddr = 0x08000000;
++static int bnx2_COM_b06FwTextLen = 0x57bc;
++static u32 bnx2_COM_b06FwDataAddr = 0x08005840;
++static int bnx2_COM_b06FwDataLen = 0x0;
++static u32 bnx2_COM_b06FwRodataAddr = 0x080057c0;
++static int bnx2_COM_b06FwRodataLen = 0x58;
++static u32 bnx2_COM_b06FwBssAddr = 0x08005860;
++static int bnx2_COM_b06FwBssLen = 0x88;
++static u32 bnx2_COM_b06FwSbssAddr = 0x08005840;
++static int bnx2_COM_b06FwSbssLen = 0x1c;
++static u8 bnx2_COM_b06FwText[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x09, 0x83, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5b, 0x7d, 0x6c,
++ 0x5b, 0xd7, 0x75, 0x3f, 0xef, 0xf1, 0x51, 0x7a, 0x96, 0x68, 0xf9, 0x99,
++ 0x7e, 0x96, 0x59, 0x4f, 0xb1, 0x49, 0xf1, 0xc9, 0xd2, 0x62, 0x2d, 0x63,
++ 0x34, 0x35, 0xd1, 0x3a, 0x26, 0x66, 0x48, 0xda, 0x71, 0x36, 0x67, 0xa0,
++ 0x1d, 0x05, 0x51, 0x51, 0xaf, 0xd0, 0x48, 0xd9, 0xcd, 0xb2, 0x0c, 0x73,
++ 0x96, 0xb4, 0x70, 0xbc, 0xb4, 0xa1, 0x25, 0x79, 0xf5, 0x06, 0x45, 0xcf,
++ 0xb3, 0x34, 0x39, 0xc0, 0x82, 0x41, 0x10, 0x9d, 0x3a, 0x7f, 0x30, 0xa5,
++ 0xed, 0x7c, 0x19, 0xe8, 0x12, 0x29, 0xb2, 0x93, 0xb5, 0x43, 0xd0, 0xa6,
++ 0x68, 0xff, 0xe8, 0x8a, 0x6e, 0x30, 0x52, 0x0c, 0xf3, 0x3a, 0xa0, 0x30,
++ 0xfa, 0xc7, 0xe6, 0x2d, 0x1f, 0xdc, 0xef, 0xdc, 0x77, 0x1f, 0xf9, 0x48,
++ 0x51, 0x96, 0x1c, 0x34, 0x5d, 0xb7, 0x99, 0x80, 0xf0, 0xde, 0xbd, 0xf7,
++ 0xbc, 0x7b, 0xcf, 0x3d, 0xdf, 0xe7, 0xdc, 0xab, 0x5f, 0x53, 0xa9, 0x85,
++ 0xe4, 0x6f, 0x2d, 0xfe, 0xc2, 0x7f, 0xf4, 0xc7, 0xb9, 0xdb, 0x3e, 0x7d,
++ 0x5b, 0x1f, 0x5e, 0x07, 0x54, 0xdd, 0xaf, 0x72, 0xbf, 0x0f, 0x7f, 0x26,
++ 0xfe, 0xfa, 0xe4, 0x7b, 0xa3, 0x9f, 0x81, 0xbf, 0x2b, 0x18, 0x1c, 0xfe,
++ 0x09, 0x91, 0xb2, 0x0c, 0x8c, 0xf7, 0x57, 0x2e, 0x5f, 0x7f, 0x9c, 0x17,
++ 0x0e, 0xaf, 0x62, 0x9e, 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf,
++ 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf, 0xff, 0x3f, 0x3f, 0x9f, 0x13, 0x72,
++ 0x88, 0x98, 0x85, 0xff, 0x48, 0x57, 0xe3, 0x89, 0xa1, 0xa4, 0x45, 0xba,
++ 0x2f, 0x7e, 0x65, 0x28, 0x67, 0x11, 0x25, 0x8a, 0xdb, 0xc3, 0x29, 0xfa,
++ 0xb0, 0x9c, 0x37, 0x35, 0xe2, 0xfe, 0x5b, 0xe2, 0x1f, 0x3c, 0xfd, 0xfa,
++ 0x9d, 0x91, 0xab, 0xb3, 0x3e, 0xd2, 0x8d, 0xf8, 0xcb, 0xba, 0xb1, 0x8d,
++ 0xf4, 0x0e, 0x7c, 0xf3, 0x5c, 0xf7, 0x7f, 0xa8, 0xd4, 0xe6, 0xce, 0x75,
++ 0xa5, 0xfc, 0x7a, 0x37, 0xe5, 0x37, 0xc7, 0x75, 0x52, 0xe3, 0x5d, 0x3f,
++ 0x48, 0xfa, 0x8c, 0x61, 0x5f, 0xdc, 0xa0, 0xf9, 0x12, 0x65, 0x0e, 0x4c,
++ 0xf0, 0x1a, 0xb1, 0x75, 0xf7, 0x62, 0x2e, 0x2d, 0x3e, 0x3c, 0xf4, 0x67,
++ 0xd6, 0xd3, 0x65, 0xd5, 0xb2, 0x7a, 0xe6, 0x28, 0x30, 0xf0, 0x7c, 0x3f,
++ 0xc6, 0x8b, 0x91, 0x1e, 0xa2, 0x3b, 0x49, 0xb5, 0xf2, 0x01, 0x9f, 0xa5,
++ 0x53, 0xb2, 0x64, 0x51, 0xaa, 0x44, 0xf4, 0x77, 0x45, 0x85, 0x9e, 0xb7,
++ 0xda, 0x69, 0xae, 0xf7, 0x83, 0x72, 0x02, 0xb8, 0xbc, 0x6d, 0x0d, 0x0f,
++ 0x8d, 0x5b, 0x3c, 0x57, 0x7c, 0x9d, 0x83, 0x6f, 0x6f, 0x5b, 0xce, 0xd2,
++ 0x68, 0xb4, 0xc8, 0x7d, 0xbd, 0x2d, 0xdc, 0xe7, 0x8f, 0x3f, 0x1c, 0x7c,
++ 0xde, 0x0a, 0xc8, 0xbe, 0x1f, 0xa5, 0x92, 0x98, 0x6f, 0xac, 0xc8, 0xb0,
++ 0xcf, 0xde, 0x91, 0xb3, 0x4c, 0xd9, 0x6f, 0xc5, 0x93, 0x56, 0x08, 0xfd,
++ 0x1d, 0x72, 0x2c, 0xbd, 0x2e, 0x67, 0x59, 0x72, 0xac, 0x88, 0x6f, 0x7a,
++ 0x65, 0xff, 0x3b, 0xa9, 0x9c, 0x15, 0x93, 0xfd, 0x57, 0x93, 0x49, 0xab,
++ 0x5f, 0xf6, 0x1f, 0xbe, 0x2b, 0x67, 0xc5, 0x65, 0xff, 0xf7, 0x81, 0x8b,
++ 0x41, 0xc7, 0x8a, 0x61, 0xfc, 0x25, 0x30, 0xfe, 0x9a, 0x41, 0x6d, 0x19,
++ 0x8c, 0x61, 0xef, 0xb6, 0x4e, 0x97, 0x7d, 0x21, 0x7a, 0xbd, 0xfb, 0x32,
++ 0x68, 0x63, 0xd0, 0xd9, 0x12, 0x29, 0x99, 0xee, 0x10, 0x68, 0x62, 0xd2,
++ 0xb9, 0x52, 0x2b, 0xf9, 0x4e, 0xfa, 0xb0, 0xe7, 0xcf, 0x51, 0xd6, 0xd4,
++ 0x69, 0xfd, 0x8c, 0x42, 0x9d, 0x7d, 0x6b, 0x28, 0x61, 0xe4, 0x29, 0xd5,
++ 0x8d, 0x28, 0x6e, 0xd2, 0x24, 0x6d, 0x66, 0x71, 0xbd, 0x8a, 0x1e, 0x95,
++ 0x22, 0xa1, 0x2c, 0x28, 0x3c, 0x72, 0xfa, 0x5d, 0x8e, 0x39, 0xb1, 0x26,
++ 0xff, 0x85, 0x29, 0x35, 0x71, 0x2b, 0x0d, 0x1b, 0x8c, 0x0f, 0x80, 0x05,
++ 0x1f, 0x74, 0x25, 0x79, 0x2a, 0x44, 0xc7, 0xec, 0x80, 0x92, 0x3a, 0x75,
++ 0x37, 0x25, 0x63, 0x64, 0xaa, 0xd4, 0x25, 0xbe, 0x2d, 0x14, 0x43, 0x34,
++ 0x6e, 0x93, 0x92, 0xb4, 0x99, 0x5e, 0xed, 0x18, 0x6f, 0x13, 0xb0, 0xe8,
++ 0xeb, 0xf0, 0x51, 0x97, 0x91, 0x22, 0x9d, 0x71, 0x46, 0x7f, 0x50, 0x49,
++ 0x8b, 0x39, 0x44, 0x7f, 0x78, 0x8c, 0x02, 0x74, 0xba, 0x68, 0x4a, 0xd8,
++ 0x72, 0x39, 0x19, 0x33, 0x00, 0x07, 0xda, 0xd9, 0x26, 0x0d, 0xe3, 0x39,
++ 0x6a, 0xf3, 0xfa, 0x21, 0xc8, 0xcc, 0xb7, 0x87, 0xb2, 0xd3, 0x62, 0xbe,
++ 0xb0, 0x2f, 0xce, 0xf3, 0x75, 0x00, 0xee, 0x1d, 0xe0, 0xa5, 0x90, 0x26,
++ 0x78, 0x95, 0xa0, 0xec, 0x84, 0x02, 0x79, 0xc2, 0x53, 0xd0, 0x2d, 0x0d,
++ 0xfc, 0x35, 0xb2, 0xfa, 0x14, 0xca, 0x59, 0x9b, 0x28, 0x6f, 0xa0, 0x5d,
++ 0xbc, 0xa0, 0x26, 0xed, 0x66, 0x4a, 0x69, 0x61, 0xec, 0x5f, 0xc8, 0x0a,
++ 0x8d, 0xe1, 0x1b, 0xd5, 0x62, 0x98, 0x9f, 0x61, 0xef, 0xc3, 0x82, 0xfe,
++ 0x4d, 0xf1, 0xfd, 0x74, 0x69, 0x22, 0xaf, 0x26, 0x4b, 0xed, 0xe4, 0x9b,
++ 0x89, 0x40, 0x9a, 0xc7, 0xd5, 0xd4, 0x19, 0x8d, 0xfc, 0x93, 0x0a, 0x41,
++ 0x3e, 0x0c, 0x5f, 0xfc, 0xb8, 0xba, 0xb3, 0x74, 0x41, 0x4d, 0x95, 0xf8,
++ 0x1b, 0xc0, 0x16, 0x55, 0xd0, 0x96, 0xdf, 0xb7, 0x83, 0x96, 0x34, 0xac,
++ 0xc6, 0x75, 0x3d, 0x51, 0x64, 0x99, 0xe5, 0x6f, 0xc1, 0x0f, 0xec, 0xe5,
++ 0x9c, 0x0d, 0xfe, 0x08, 0x7e, 0x85, 0xc1, 0xaf, 0x6f, 0x82, 0x5f, 0xfd,
++ 0xe0, 0x53, 0x8c, 0xde, 0x28, 0xf5, 0xd2, 0x6b, 0xa5, 0x1e, 0x7a, 0x15,
++ 0x32, 0xf9, 0x4a, 0x29, 0x4c, 0x2f, 0x97, 0x3a, 0xe8, 0xa5, 0x52, 0x88,
++ 0xce, 0x0b, 0x1e, 0xa6, 0x21, 0xff, 0x82, 0xaf, 0xfa, 0x26, 0xf0, 0xa4,
++ 0x1d, 0x3c, 0x59, 0x0f, 0x79, 0xd9, 0x08, 0xf9, 0x9b, 0xee, 0xd6, 0x69,
++ 0xaa, 0x9b, 0x12, 0x41, 0xf4, 0x6f, 0x89, 0x6b, 0x82, 0x4e, 0x1a, 0xc6,
++ 0xc7, 0x26, 0xfc, 0x94, 0x32, 0x4e, 0xd3, 0x7b, 0x93, 0x1a, 0x8d, 0x95,
++ 0xa6, 0x36, 0x3a, 0x7c, 0xe3, 0xf6, 0x2c, 0x5d, 0x44, 0x5f, 0xca, 0x98,
++ 0xa5, 0x4b, 0xdb, 0x54, 0x1a, 0x9d, 0xfe, 0x1b, 0x4a, 0x9e, 0x39, 0x4d,
++ 0x3f, 0xfe, 0x3a, 0x51, 0x06, 0x34, 0x51, 0xfb, 0x7e, 0x5a, 0x4e, 0x18,
++ 0xa0, 0x45, 0x5f, 0xaf, 0x90, 0x08, 0xb5, 0x8f, 0x79, 0x19, 0x86, 0xae,
++ 0x68, 0x4a, 0xca, 0x7e, 0x01, 0xfa, 0xd2, 0xaa, 0x24, 0xa7, 0x88, 0x72,
++ 0x53, 0x65, 0xca, 0xc5, 0xfc, 0xf4, 0x98, 0x51, 0xa6, 0x74, 0xac, 0x89,
++ 0xbe, 0x68, 0xb4, 0xd3, 0x68, 0xef, 0x6f, 0xf8, 0xdc, 0x5c, 0x65, 0xba,
++ 0xd4, 0x8f, 0x77, 0xee, 0x23, 0x9a, 0x12, 0xef, 0x4e, 0x7f, 0xbe, 0xe4,
++ 0xa7, 0x84, 0x99, 0x0f, 0x69, 0xf4, 0x8e, 0xcf, 0xc1, 0x29, 0xe1, 0x8e,
++ 0x81, 0x57, 0xc3, 0xb0, 0x0f, 0x8e, 0x0c, 0x66, 0x27, 0xd6, 0x5c, 0x4b,
++ 0x88, 0x6e, 0xc0, 0x0b, 0xd9, 0xd3, 0x18, 0x8f, 0x61, 0x25, 0x6e, 0x52,
++ 0xa7, 0xd0, 0x8d, 0x7e, 0xc0, 0x0c, 0x28, 0xfb, 0x4a, 0xcc, 0x6b, 0xbc,
++ 0x17, 0x19, 0xd7, 0xcd, 0x80, 0xd5, 0xf0, 0x4c, 0x48, 0x9c, 0xbd, 0x78,
++ 0xf2, 0x5c, 0x8c, 0x27, 0x3f, 0x7f, 0xcf, 0x83, 0xe7, 0xe7, 0x2b, 0xef,
++ 0x53, 0x9e, 0xf7, 0x7c, 0xe9, 0x4f, 0x03, 0x0e, 0x7e, 0x4c, 0xcf, 0x01,
++ 0x1a, 0x9d, 0x38, 0x2c, 0xd7, 0xc2, 0x7b, 0x91, 0xd7, 0x38, 0x0d, 0x3a,
++ 0x09, 0xc8, 0x15, 0xd6, 0x3a, 0xec, 0x59, 0xeb, 0x49, 0xcf, 0x5a, 0x4f,
++ 0x7a, 0xd6, 0xca, 0x83, 0xb6, 0xb4, 0x4e, 0xb5, 0xfc, 0xd0, 0x51, 0xee,
++ 0x39, 0x8e, 0x39, 0x9f, 0x03, 0x5f, 0xbe, 0x0a, 0x98, 0x38, 0x2d, 0xda,
++ 0xa0, 0xc7, 0x94, 0x46, 0x7b, 0x4d, 0x7e, 0x7f, 0xb1, 0xd5, 0xc1, 0x8b,
++ 0xdf, 0x2f, 0x48, 0x9c, 0x5a, 0x1d, 0xb8, 0xd2, 0x15, 0xa1, 0xff, 0xf3,
++ 0x25, 0xd6, 0x4f, 0x8a, 0xf9, 0x2c, 0x3a, 0x94, 0x8e, 0xb5, 0xd3, 0x98,
++ 0xa1, 0xc4, 0x46, 0x7b, 0x9a, 0x99, 0x8e, 0x09, 0xd5, 0x6a, 0x85, 0x0e,
++ 0x50, 0x58, 0x65, 0xdb, 0x25, 0xf0, 0x7b, 0x49, 0xe2, 0x61, 0x70, 0x3b,
++ 0xa3, 0x5a, 0xc1, 0xba, 0x7e, 0x96, 0xdf, 0x57, 0xf0, 0xce, 0x32, 0x9c,
++ 0xd4, 0x9c, 0xb5, 0x5f, 0x45, 0x9b, 0xed, 0xce, 0x66, 0xd9, 0x76, 0xc7,
++ 0xff, 0xa0, 0xa9, 0xb6, 0xfd, 0x05, 0xb3, 0xb6, 0xed, 0xea, 0x82, 0xd7,
++ 0x66, 0xf1, 0xde, 0xc2, 0xe4, 0xb3, 0x58, 0x8e, 0xfc, 0xc0, 0x35, 0x06,
++ 0x3d, 0x6c, 0x96, 0x38, 0x7c, 0x4b, 0xe2, 0x00, 0x5c, 0x01, 0x37, 0x5a,
++ 0xe2, 0x6f, 0x04, 0x4b, 0xea, 0xda, 0x4c, 0x43, 0xf7, 0x7d, 0xad, 0x18,
++ 0xbf, 0xec, 0xe3, 0x75, 0xdc, 0x27, 0x29, 0x69, 0xe8, 0xc9, 0xd8, 0xb4,
++ 0x46, 0xd9, 0xd8, 0x26, 0x21, 0xd7, 0xd9, 0x58, 0xd5, 0x06, 0x8c, 0x4e,
++ 0xd4, 0xdb, 0x00, 0xfe, 0x8e, 0x6d, 0x80, 0xa3, 0xfb, 0x63, 0xd3, 0x6c,
++ 0x0b, 0x1c, 0xdd, 0x3f, 0x36, 0xc1, 0x36, 0x41, 0xcc, 0x09, 0xfd, 0x67,
++ 0x3b, 0xe0, 0xda, 0x00, 0xfe, 0x86, 0x6d, 0x80, 0x0f, 0xf2, 0xcd, 0xf3,
++ 0xb9, 0x6b, 0x8f, 0xd7, 0xcd, 0x3b, 0xce, 0xb6, 0x45, 0xd9, 0xd9, 0xcd,
++ 0x30, 0xc7, 0xb1, 0x76, 0x80, 0x0a, 0xd3, 0xcc, 0xc3, 0x48, 0xe8, 0x08,
++ 0x1d, 0x17, 0x36, 0xef, 0xf4, 0x04, 0x25, 0x0e, 0x9e, 0x18, 0xa0, 0x34,
++ 0x6c, 0xc0, 0xdc, 0xc4, 0xb5, 0x32, 0xf8, 0x78, 0x47, 0x13, 0x59, 0xb0,
++ 0x75, 0xf0, 0x93, 0xfd, 0x7e, 0xf2, 0xc5, 0xe3, 0x90, 0xb7, 0x98, 0xf0,
++ 0x5d, 0xd5, 0x9f, 0xa6, 0xed, 0xaa, 0x69, 0x37, 0xc1, 0x3f, 0x62, 0xde,
++ 0xfe, 0x98, 0x90, 0x4d, 0xef, 0x2f, 0x09, 0x1b, 0x94, 0x8c, 0x7d, 0x08,
++ 0xf9, 0x75, 0x69, 0xe4, 0xea, 0x1f, 0xdb, 0xfa, 0x2b, 0x1e, 0x1f, 0xb2,
++ 0x05, 0x76, 0xdf, 0x84, 0x3c, 0xb9, 0x76, 0x9f, 0xed, 0x71, 0x88, 0x6d,
++ 0x26, 0xf4, 0x8d, 0x6d, 0x70, 0x80, 0xd4, 0x19, 0x4d, 0xda, 0x69, 0x5d,
++ 0xda, 0xe9, 0x00, 0x6c, 0x34, 0xb7, 0x0d, 0xd9, 0x36, 0x45, 0x1b, 0xf6,
++ 0x1a, 0xf6, 0x70, 0x77, 0x3a, 0x35, 0xc1, 0xfe, 0x10, 0xbe, 0x7b, 0x86,
++ 0x75, 0xf8, 0xdb, 0x43, 0x23, 0xd3, 0xc2, 0x07, 0xb0, 0xff, 0x80, 0x65,
++ 0x66, 0x1b, 0xce, 0xb6, 0x1c, 0xfb, 0x2e, 0x62, 0xdd, 0x8a, 0xad, 0x64,
++ 0x39, 0xf1, 0xe2, 0xc5, 0x38, 0xad, 0x21, 0xf5, 0xa4, 0x43, 0x6b, 0x35,
++ 0xfe, 0xa8, 0x46, 0x2d, 0x4c, 0x63, 0xc6, 0x7f, 0x2b, 0x70, 0xe6, 0x7d,
++ 0xfd, 0x4f, 0xe0, 0xcc, 0xeb, 0xd6, 0xe3, 0x4d, 0x7a, 0x6b, 0xfc, 0xac,
++ 0xfe, 0xf0, 0x33, 0xa4, 0x37, 0xc7, 0xcf, 0xd2, 0xbf, 0x58, 0x74, 0x9f,
++ 0x0e, 0x3f, 0xdb, 0xad, 0xc0, 0xcf, 0x16, 0xa1, 0xef, 0x53, 0x3a, 0x1d,
++ 0x3c, 0x15, 0xc9, 0xfc, 0x2b, 0x45, 0x61, 0x3f, 0x76, 0xd0, 0xc8, 0x94,
++ 0x42, 0x7a, 0x17, 0xb5, 0xc3, 0x7f, 0xf4, 0x37, 0x61, 0xfe, 0x5d, 0x44,
++ 0x9b, 0x1d, 0xbf, 0xd9, 0x15, 0x1e, 0x05, 0xff, 0xd3, 0x2f, 0x7e, 0x05,
++ 0xdf, 0x3c, 0x4d, 0x07, 0xa7, 0x0e, 0x2b, 0x39, 0xfb, 0x08, 0xe0, 0x97,
++ 0x83, 0xd5, 0x01, 0x9b, 0x07, 0xec, 0x97, 0x31, 0xef, 0xd3, 0xa4, 0xdf,
++ 0x1e, 0x19, 0x48, 0x28, 0xc0, 0xe3, 0x45, 0x01, 0x2f, 0x7d, 0x71, 0x97,
++ 0xb1, 0x53, 0xf0, 0x3f, 0x40, 0xef, 0x15, 0x2f, 0x80, 0xbe, 0xbd, 0xf0,
++ 0x39, 0x91, 0x67, 0x61, 0x93, 0xe1, 0x8f, 0x22, 0x57, 0x31, 0x2d, 0x7c,
++ 0x11, 0x29, 0x0f, 0x76, 0xa7, 0x41, 0xef, 0x38, 0xfc, 0xd3, 0x00, 0xfc,
++ 0x53, 0x0c, 0xbe, 0xa9, 0x07, 0x7e, 0xc9, 0x82, 0x5f, 0x0a, 0x83, 0x1f,
++ 0x06, 0xcd, 0xc2, 0x47, 0xcd, 0x42, 0xfe, 0xe7, 0x66, 0x48, 0x19, 0x04,
++ 0xad, 0xcf, 0xc1, 0x3f, 0x26, 0x63, 0x77, 0x42, 0xcf, 0x22, 0x17, 0x66,
++ 0xd5, 0x41, 0xca, 0xc1, 0x9f, 0x77, 0x6e, 0x8b, 0x62, 0xbd, 0x26, 0x4a,
++ 0x84, 0x5c, 0x1d, 0xe5, 0xdf, 0x7e, 0x85, 0xac, 0x7f, 0x06, 0xef, 0x22,
++ 0x61, 0xa2, 0x3d, 0x94, 0xb5, 0xa3, 0x46, 0xa7, 0xda, 0x03, 0x18, 0x6e,
++ 0x87, 0x95, 0x03, 0x53, 0x11, 0x05, 0xfb, 0x03, 0xcd, 0x27, 0x60, 0xeb,
++ 0xcb, 0x34, 0x1e, 0x63, 0x3d, 0x29, 0xd3, 0xf3, 0xb1, 0xc8, 0x40, 0x9e,
++ 0x5a, 0xe9, 0x98, 0x39, 0x21, 0x7c, 0xbc, 0x16, 0x3f, 0x21, 0x74, 0x2c,
++ 0x67, 0xe1, 0x59, 0xec, 0x54, 0xb2, 0x53, 0xbc, 0x7e, 0x14, 0x5a, 0xee,
++ 0xc7, 0x93, 0xe7, 0x07, 0xdd, 0xfa, 0x49, 0x39, 0xd8, 0x9d, 0x87, 0x77,
++ 0x88, 0x18, 0x8b, 0x58, 0x39, 0x35, 0x11, 0x0d, 0x45, 0x55, 0x8d, 0x86,
++ 0x35, 0x85, 0x46, 0x61, 0x6f, 0xd2, 0xb1, 0xff, 0x2c, 0x1f, 0x33, 0x79,
++ 0xbc, 0x99, 0xbe, 0x2a, 0xfc, 0x0d, 0xd6, 0x2e, 0x4c, 0x63, 0x5d, 0x3f,
++ 0xf8, 0xcb, 0xeb, 0xf2, 0x3c, 0x68, 0xc3, 0xf6, 0x6b, 0x56, 0xe4, 0xd9,
++ 0x3c, 0xed, 0x00, 0x6d, 0xd9, 0x66, 0xc1, 0x3e, 0x0c, 0x60, 0xed, 0x5e,
++ 0xd8, 0x4f, 0x3c, 0x93, 0xbd, 0x1c, 0x07, 0x05, 0x68, 0xd8, 0x64, 0x79,
++ 0xd4, 0xe5, 0x98, 0xe9, 0x19, 0xf3, 0xcb, 0xb1, 0x20, 0xfe, 0xe0, 0x7f,
++ 0x4d, 0x96, 0x19, 0x6e, 0x73, 0x4c, 0xc6, 0x34, 0x09, 0xd3, 0xdc, 0x64,
++ 0x02, 0x34, 0x8b, 0x9c, 0x4d, 0x10, 0xd3, 0x0c, 0x46, 0x7b, 0x7f, 0x82,
++ 0xbe, 0x64, 0xaf, 0xf7, 0x3b, 0xb6, 0xb0, 0x55, 0x49, 0xc1, 0x17, 0xa8,
++ 0x56, 0x0b, 0x7c, 0x45, 0x98, 0x5e, 0x15, 0xb0, 0x64, 0xa8, 0xf1, 0x68,
++ 0xe8, 0x4b, 0x74, 0xab, 0xb0, 0x11, 0x09, 0xc3, 0x4b, 0xe3, 0xff, 0x52,
++ 0xc9, 0x72, 0xbf, 0x69, 0xa5, 0xec, 0x20, 0xf3, 0x89, 0xd7, 0x33, 0x68,
++ 0xae, 0xe4, 0xbc, 0xfb, 0x10, 0xa3, 0x16, 0x60, 0x6b, 0xce, 0x4f, 0xaa,
++ 0xf4, 0xf8, 0x1d, 0xf0, 0x65, 0xb1, 0x6d, 0x58, 0xcb, 0xc4, 0x78, 0x1e,
++ 0x6d, 0x15, 0x6d, 0xe8, 0x99, 0x11, 0x02, 0x8f, 0xb9, 0x9f, 0xe1, 0x4c,
++ 0xfc, 0xbd, 0xcf, 0xb1, 0x75, 0x3e, 0xab, 0xde, 0x4a, 0x14, 0x64, 0x7a,
++ 0xc5, 0x40, 0x2b, 0xcb, 0x50, 0xd5, 0x6d, 0xc2, 0x5f, 0x3b, 0xb6, 0xc4,
++ 0x82, 0x2e, 0xc2, 0xe6, 0xf6, 0x79, 0x75, 0x91, 0xe3, 0x09, 0x57, 0x17,
++ 0x23, 0xa1, 0x84, 0x0a, 0x5b, 0xdc, 0xa7, 0xd1, 0x09, 0xd1, 0x56, 0x28,
++ 0x31, 0x18, 0x09, 0x2d, 0xa8, 0x1c, 0x4b, 0x33, 0x6c, 0x18, 0xf1, 0x4a,
++ 0x40, 0xc2, 0x22, 0x9e, 0xb3, 0xdd, 0x98, 0x30, 0x84, 0x7e, 0x53, 0xf4,
++ 0x1f, 0xab, 0xe8, 0xa8, 0x13, 0xff, 0xa9, 0x88, 0x11, 0x0b, 0x88, 0x11,
++ 0x53, 0x42, 0x47, 0x8d, 0x04, 0x72, 0x04, 0xd0, 0xdc, 0xd1, 0xcf, 0x42,
++ 0x91, 0x71, 0xc9, 0xb1, 0x5c, 0x0e, 0x00, 0x99, 0x13, 0x8e, 0x7d, 0xa4,
++ 0x3c, 0xc7, 0x91, 0xa3, 0xea, 0x53, 0x34, 0x5c, 0x60, 0x3f, 0x8e, 0x3f,
++ 0x9b, 0x6d, 0x2d, 0xec, 0xa3, 0xf0, 0xc5, 0x51, 0xf0, 0x39, 0x0f, 0x1a,
++ 0xac, 0x97, 0x74, 0xdd, 0x4f, 0x07, 0xec, 0x3d, 0xa0, 0x79, 0x9c, 0x46,
++ 0x4e, 0x8d, 0xb0, 0xcc, 0xf6, 0x14, 0x28, 0xd2, 0x73, 0x8c, 0xb6, 0x1b,
++ 0x73, 0x2c, 0xdf, 0x83, 0xe5, 0x1d, 0xe0, 0x85, 0xd0, 0x51, 0xc8, 0x20,
++ 0x65, 0x0b, 0x23, 0xf4, 0x58, 0x89, 0xfb, 0xf2, 0xa0, 0x1d, 0xe2, 0xda,
++ 0xfe, 0xfd, 0x52, 0xce, 0x31, 0x9f, 0xe6, 0xce, 0x37, 0x22, 0xe7, 0x63,
++ 0x38, 0x86, 0xe1, 0x6f, 0xaa, 0xf3, 0xee, 0x14, 0x3c, 0x8d, 0x18, 0x5d,
++ 0x6a, 0x79, 0x87, 0x1f, 0xe3, 0xcf, 0xf7, 0xf3, 0x3b, 0xe6, 0x81, 0xef,
++ 0x6f, 0xb6, 0xf6, 0x00, 0x76, 0x10, 0x73, 0xfa, 0xa9, 0xb3, 0xdd, 0xc5,
++ 0x37, 0x81, 0xb5, 0xd9, 0xcf, 0x31, 0x9f, 0x1f, 0xa1, 0xec, 0xa9, 0x7c,
++ 0x8f, 0x0a, 0x19, 0x9b, 0xcd, 0x28, 0xe4, 0xb7, 0x1e, 0xa6, 0xdc, 0xa9,
++ 0xa3, 0x6c, 0x37, 0x40, 0xab, 0x3d, 0xb4, 0x6b, 0x22, 0xd2, 0x73, 0x80,
++ 0x34, 0xb1, 0xce, 0x5b, 0x24, 0xe8, 0x1f, 0x9b, 0x15, 0xbe, 0x20, 0x43,
++ 0xe9, 0x89, 0xed, 0xa1, 0x4b, 0xe8, 0x1b, 0x1e, 0x8c, 0x84, 0x17, 0xe8,
++ 0x09, 0xd0, 0xe5, 0x23, 0xf8, 0x22, 0xab, 0x67, 0x0c, 0x3a, 0x84, 0x9c,
++ 0x0a, 0xeb, 0x8f, 0x4a, 0xda, 0xe0, 0xbb, 0xcc, 0x51, 0xd0, 0x8f, 0xf2,
++ 0x0e, 0x4d, 0x99, 0x9e, 0x4c, 0xcb, 0xaf, 0xc0, 0xf6, 0x1c, 0x11, 0xb1,
++ 0x4b, 0x56, 0xd0, 0xee, 0xd2, 0x06, 0x47, 0x0e, 0x60, 0x8b, 0x30, 0xef,
++ 0xe5, 0x41, 0x85, 0xb6, 0x20, 0x4e, 0x3f, 0x24, 0x78, 0xeb, 0xa3, 0x7d,
++ 0x66, 0xd4, 0xd8, 0x47, 0xf3, 0x7e, 0x27, 0x56, 0xc0, 0x3c, 0x3d, 0xf7,
++ 0x60, 0x0f, 0x90, 0x53, 0xfb, 0xeb, 0xeb, 0xa8, 0x2d, 0x12, 0x4e, 0xa8,
++ 0x09, 0xfa, 0x93, 0xd2, 0xdd, 0xe4, 0xe8, 0x77, 0x2b, 0xdb, 0x7e, 0xf0,
++ 0xb0, 0xd3, 0x69, 0x5b, 0x78, 0x16, 0x3a, 0xb1, 0x1e, 0xe3, 0xfe, 0xac,
++ 0xc0, 0x7d, 0x84, 0xba, 0xa1, 0x6b, 0x22, 0x8f, 0x39, 0x51, 0x8b, 0x17,
++ 0xf3, 0xbc, 0x9e, 0xcf, 0x5f, 0xc6, 0x3c, 0xdc, 0xcf, 0x70, 0x78, 0x2f,
++ 0x3c, 0x41, 0x23, 0x90, 0xc7, 0x5c, 0x7f, 0x57, 0x68, 0x0c, 0xdf, 0xa4,
++ 0x4a, 0x4d, 0x74, 0x54, 0xe3, 0xf1, 0x48, 0x38, 0xaf, 0x1e, 0x42, 0xdc,
++ 0xf3, 0xb8, 0xea, 0xb7, 0x7e, 0xe6, 0x67, 0xbf, 0xe3, 0xb7, 0xae, 0x29,
++ 0xd5, 0xb9, 0x10, 0x87, 0x8a, 0xdc, 0x60, 0x41, 0x19, 0x2c, 0x5d, 0x52,
++ 0x92, 0x85, 0x6b, 0x4a, 0xaa, 0xc4, 0x30, 0x8e, 0xce, 0x67, 0xcf, 0x74,
++ 0x82, 0x4e, 0x1f, 0x89, 0xef, 0xe6, 0x7a, 0x8f, 0x50, 0xea, 0xd4, 0xad,
++ 0x94, 0x9e, 0xe6, 0xbc, 0x34, 0x02, 0x7c, 0x3f, 0x2a, 0xe7, 0x62, 0x41,
++ 0xca, 0x9d, 0xe1, 0x31, 0xb6, 0x5f, 0xd6, 0xd5, 0x45, 0x1f, 0xef, 0x9f,
++ 0xf9, 0x6f, 0x52, 0xc1, 0x7e, 0x53, 0xd2, 0x8f, 0xdf, 0x7d, 0x9c, 0x93,
++ 0xe1, 0xf7, 0x6f, 0x86, 0xd3, 0xb7, 0x95, 0x16, 0x36, 0xdc, 0xc8, 0x3e,
++ 0x57, 0xb3, 0xc7, 0x47, 0x7d, 0x7e, 0x6b, 0x7b, 0x13, 0xb5, 0x84, 0x80,
++ 0xc3, 0x4a, 0x7b, 0x64, 0x98, 0x5f, 0x87, 0x1c, 0xb0, 0x4d, 0xd9, 0x0d,
++ 0x7e, 0x5a, 0x6c, 0xc3, 0x60, 0x93, 0x76, 0x53, 0xae, 0xc4, 0xb2, 0x1d,
++ 0x35, 0x32, 0x90, 0xb1, 0x34, 0x75, 0xb1, 0x1e, 0xb9, 0xba, 0x07, 0xdb,
++ 0x9d, 0x87, 0xed, 0x46, 0x3c, 0x64, 0x53, 0xbe, 0x29, 0xce, 0x36, 0xbc,
++ 0x0b, 0xb2, 0x85, 0xbe, 0x62, 0x55, 0x17, 0x77, 0x2d, 0xc1, 0x5d, 0x5b,
++ 0xc2, 0xa3, 0x02, 0xd5, 0xe2, 0x3f, 0x4b, 0x8c, 0xff, 0x5f, 0x00, 0xff,
++ 0xcf, 0x01, 0x7f, 0xc6, 0xa9, 0x31, 0xfe, 0x3b, 0x2b, 0xf8, 0x33, 0x0c,
++ 0xfc, 0x1c, 0x64, 0xf1, 0x0d, 0xe8, 0xe2, 0x6b, 0x36, 0x7c, 0x9d, 0x0d,
++ 0xff, 0x67, 0xc3, 0xdf, 0xd9, 0xf0, 0x8b, 0x36, 0x7c, 0x1e, 0xf6, 0x74,
++ 0x0e, 0x36, 0xe9, 0xac, 0x9d, 0x34, 0x58, 0x9f, 0x92, 0x31, 0xf6, 0x9d,
++ 0xbb, 0x65, 0xde, 0x1d, 0x92, 0x71, 0xf7, 0xa7, 0x64, 0x2c, 0x7b, 0x00,
++ 0xb1, 0xec, 0x66, 0x1a, 0xed, 0xe1, 0x9c, 0xa4, 0x05, 0xcf, 0x75, 0x78,
++ 0x22, 0x6e, 0xed, 0x49, 0x48, 0xbd, 0xfc, 0x0c, 0x62, 0x5c, 0xd8, 0xff,
++ 0x1e, 0xe4, 0x37, 0x19, 0xc4, 0x6a, 0x56, 0x1f, 0xc7, 0xe5, 0xb0, 0x65,
++ 0xef, 0x37, 0x39, 0x76, 0xfe, 0x2e, 0x19, 0x03, 0xbb, 0xed, 0x56, 0xc0,
++ 0xa4, 0xd1, 0xd7, 0x8a, 0x6f, 0x7e, 0x07, 0xb2, 0xdf, 0x86, 0xf6, 0xce,
++ 0x3a, 0x18, 0xe4, 0xb3, 0x56, 0x16, 0x7d, 0x11, 0xc0, 0xb4, 0x61, 0x9d,
++ 0x0e, 0xb4, 0xf7, 0xa0, 0x7d, 0x8b, 0xb3, 0x8e, 0xf1, 0x2b, 0x68, 0xa7,
++ 0xea, 0xbe, 0xd9, 0x8a, 0xbe, 0x4c, 0x5d, 0xdf, 0x9b, 0xe8, 0x4b, 0xa2,
++ 0x6f, 0x51, 0x7e, 0x97, 0x47, 0x3b, 0x52, 0x07, 0xb3, 0x88, 0x3e, 0xc6,
++ 0xf1, 0x5b, 0x78, 0xde, 0x47, 0xa3, 0x19, 0x8e, 0x03, 0xdc, 0xb1, 0xdc,
++ 0x7a, 0x6a, 0xe3, 0xdc, 0xf7, 0x43, 0x21, 0x3b, 0xf3, 0xd2, 0x46, 0xa7,
++ 0x27, 0xd8, 0x4f, 0x8c, 0x20, 0xee, 0xe1, 0x71, 0xe1, 0x9c, 0x3c, 0xfd,
++ 0x1f, 0x00, 0xf6, 0x61, 0x8c, 0x21, 0x56, 0xb7, 0xcb, 0x4d, 0x8d, 0xc7,
++ 0x1f, 0xc5, 0xf8, 0x5f, 0xca, 0x6f, 0x2b, 0x73, 0x03, 0xfe, 0x1b, 0x75,
++ 0x7d, 0x6a, 0xb0, 0xb6, 0xbd, 0xd6, 0xf3, 0xbe, 0x4d, 0x5f, 0xfa, 0xfd,
++ 0x48, 0x1d, 0xfc, 0xef, 0x6e, 0xa8, 0x6d, 0x3f, 0xc5, 0xdf, 0x20, 0x87,
++ 0x70, 0xdb, 0x09, 0xc8, 0x1d, 0xdb, 0xa4, 0xfa, 0x79, 0x3e, 0x6b, 0xd4,
++ 0xf6, 0x6d, 0x32, 0x6b, 0xdb, 0x1c, 0x27, 0x31, 0x5c, 0x08, 0xf2, 0xde,
++ 0xa1, 0xec, 0xb2, 0x7f, 0x13, 0xe3, 0x61, 0xe5, 0x5e, 0xdb, 0x8b, 0x67,
++ 0x48, 0xe6, 0x46, 0xe1, 0x4a, 0xcc, 0x3b, 0x5f, 0x0a, 0x40, 0xae, 0x3e,
++ 0x0f, 0x9e, 0x73, 0xdc, 0x53, 0xd5, 0xf1, 0xf7, 0x68, 0x39, 0x1d, 0x67,
++ 0x1f, 0xc0, 0x31, 0xfe, 0x36, 0x11, 0x1f, 0xfb, 0xe2, 0x4f, 0x70, 0x0c,
++ 0xf6, 0xb4, 0xe3, 0x5b, 0x2c, 0xf8, 0x43, 0xb4, 0x4b, 0x7e, 0xc7, 0x6e,
++ 0x22, 0x9f, 0xc8, 0x16, 0xd8, 0x9f, 0xb1, 0x0f, 0x89, 0xc0, 0x4e, 0xb3,
++ 0x1f, 0xfd, 0x24, 0x7d, 0xc6, 0x5d, 0xcd, 0x6c, 0xfb, 0x34, 0xeb, 0x05,
++ 0xc4, 0x0b, 0x1c, 0xe7, 0xb1, 0xed, 0xc6, 0x7b, 0xd1, 0x8d, 0x57, 0xee,
++ 0xd7, 0xc8, 0xaa, 0xfa, 0x11, 0x67, 0x8f, 0x5b, 0x59, 0x37, 0x56, 0xb1,
++ 0xef, 0xc6, 0xb6, 0xed, 0xc7, 0x75, 0xb6, 0xe1, 0xb2, 0xb0, 0x0d, 0x0f,
++ 0x6a, 0x7e, 0xeb, 0xf7, 0x9b, 0x1d, 0x79, 0x6d, 0x6c, 0x1b, 0xee, 0xad,
++ 0xd8, 0x06, 0x57, 0x5e, 0xbd, 0x79, 0xeb, 0x0f, 0xc0, 0x1b, 0x0b, 0xbc,
++ 0xa9, 0xaf, 0xd5, 0x70, 0x8e, 0xe2, 0x87, 0x1f, 0xe2, 0x18, 0x91, 0x73,
++ 0xd9, 0x18, 0xe5, 0x62, 0x45, 0xc4, 0x6a, 0x91, 0xd9, 0xd9, 0x4a, 0x8e,
++ 0xf5, 0x35, 0x69, 0xbb, 0x6b, 0xe2, 0x22, 0x7a, 0xbc, 0x78, 0x09, 0xf8,
++ 0x73, 0xbc, 0xa5, 0x49, 0x1b, 0xc1, 0xfd, 0xe3, 0x12, 0x47, 0x7e, 0xe7,
++ 0x3a, 0x1e, 0x7c, 0x69, 0xf1, 0x47, 0xe0, 0x15, 0xc7, 0x7d, 0x51, 0x27,
++ 0xde, 0xab, 0x89, 0xa9, 0xd7, 0xf8, 0xc9, 0xe2, 0x78, 0x89, 0x61, 0x74,
++ 0x19, 0x2f, 0x05, 0x64, 0x5e, 0x63, 0xc8, 0x3c, 0x87, 0x63, 0x6d, 0xae,
++ 0xb1, 0xd6, 0xc7, 0x50, 0x0b, 0x43, 0xc1, 0x6d, 0xcc, 0x13, 0x8e, 0xa1,
++ 0xda, 0x28, 0x39, 0xe3, 0xc4, 0x50, 0x4e, 0x9d, 0xcd, 0xcd, 0x71, 0x5c,
++ 0x5c, 0xd9, 0x0f, 0xef, 0xc0, 0x3e, 0x45, 0x9e, 0x14, 0x74, 0xea, 0x7f,
++ 0x1a, 0xec, 0xf6, 0x51, 0xf4, 0x8f, 0xba, 0xfd, 0x9e, 0x5c, 0xc3, 0xc5,
++ 0x85, 0x7d, 0xbd, 0x1b, 0xd3, 0xed, 0x96, 0x31, 0x1d, 0x62, 0x18, 0xdb,
++ 0xc9, 0xbb, 0xf6, 0x16, 0x33, 0xe8, 0xe3, 0x75, 0x11, 0x1b, 0x12, 0xc7,
++ 0x49, 0x90, 0xaf, 0xfd, 0x91, 0x50, 0x58, 0xad, 0xc7, 0xab, 0x75, 0xa1,
++ 0x16, 0xaf, 0x41, 0xf1, 0xdd, 0xf8, 0x92, 0xef, 0x48, 0xc4, 0x92, 0xe3,
++ 0xf6, 0x10, 0xe8, 0xc5, 0xf8, 0xb9, 0xba, 0xe1, 0xc6, 0xc9, 0x8c, 0xd3,
++ 0x3f, 0x82, 0xc6, 0xbb, 0x15, 0xfe, 0x7e, 0xcc, 0xde, 0x2f, 0xe8, 0x96,
++ 0x15, 0xb8, 0x0e, 0x7b, 0x70, 0x1d, 0x91, 0xb8, 0xb2, 0x2e, 0xb0, 0x7e,
++ 0x78, 0x6b, 0x9a, 0xa6, 0xd8, 0x1b, 0x70, 0x0e, 0xf3, 0xb9, 0xb9, 0x6a,
++ 0x2d, 0x0c, 0xf9, 0xb6, 0xc1, 0x1f, 0x02, 0xd7, 0xac, 0x88, 0x43, 0x03,
++ 0x0b, 0xf5, 0x34, 0x1c, 0xc7, 0x5a, 0x88, 0xdb, 0x81, 0x8f, 0xcb, 0xf3,
++ 0x26, 0x89, 0xcf, 0x37, 0xc5, 0xdc, 0x63, 0xa2, 0x06, 0xea, 0xd3, 0x39,
++ 0x77, 0xc9, 0x0a, 0xde, 0x69, 0x92, 0x77, 0x8f, 0x56, 0xf0, 0x73, 0x78,
++ 0x1c, 0x90, 0x74, 0xe5, 0xdc, 0x95, 0x75, 0x5a, 0xf0, 0xa7, 0x9d, 0x73,
++ 0xd3, 0x41, 0x6a, 0x14, 0x23, 0x2f, 0x0c, 0xa9, 0xdb, 0x1c, 0x3a, 0x3a,
++ 0x31, 0xf2, 0xda, 0xba, 0x18, 0xf9, 0xb6, 0x20, 0xc7, 0x5a, 0xc3, 0x50,
++ 0x82, 0x79, 0xf8, 0xba, 0x97, 0x6d, 0xc8, 0x36, 0x70, 0x3d, 0x5f, 0x53,
++ 0xbb, 0xec, 0x59, 0xa6, 0xd6, 0x1c, 0x20, 0xdf, 0x0c, 0xfb, 0x0e, 0x0b,
++ 0x79, 0x06, 0x91, 0x36, 0xc9, 0x3a, 0xcb, 0xbe, 0xbd, 0x1a, 0x67, 0xcf,
++ 0x51, 0xa3, 0x18, 0xfb, 0x46, 0xfd, 0xfa, 0x79, 0xbf, 0xdf, 0x3a, 0xac,
++ 0x3b, 0x36, 0x73, 0x25, 0xbf, 0xee, 0xc2, 0xed, 0x41, 0x9c, 0xad, 0x50,
++ 0x93, 0x55, 0xc0, 0xfe, 0xde, 0xf0, 0x37, 0x5b, 0xae, 0x2e, 0x06, 0x68,
++ 0xfd, 0xcc, 0x2d, 0x42, 0x1f, 0x8d, 0xc9, 0xaa, 0x3e, 0x8e, 0x82, 0x37,
++ 0x19, 0xa7, 0x06, 0x60, 0xae, 0xa7, 0xeb, 0xd7, 0x0b, 0xc6, 0xed, 0x37,
++ 0xfd, 0xaa, 0xe5, 0xca, 0xc0, 0xf5, 0xf2, 0x91, 0x4f, 0xd5, 0xd1, 0xba,
++ 0x51, 0x4d, 0xf8, 0x2c, 0xe8, 0x1a, 0x47, 0xde, 0x1d, 0x79, 0x81, 0x10,
++ 0x3b, 0x39, 0x79, 0x78, 0x1a, 0xb9, 0x77, 0xe4, 0x02, 0xe7, 0xe3, 0x6e,
++ 0x7e, 0xfe, 0x6a, 0x29, 0x72, 0x36, 0x8f, 0x9c, 0x79, 0x1e, 0x39, 0xf9,
++ 0xcb, 0xc8, 0xc9, 0xcf, 0x97, 0x7a, 0x41, 0xff, 0x1e, 0x99, 0x8f, 0xb3,
++ 0x8e, 0x99, 0x74, 0x11, 0xb9, 0xd3, 0x77, 0x67, 0xd8, 0x46, 0x74, 0xd1,
++ 0x3d, 0xc8, 0x35, 0xbe, 0x3f, 0xa9, 0x68, 0x9d, 0x7d, 0x01, 0x5f, 0xc2,
++ 0xb8, 0x91, 0x38, 0x71, 0x29, 0x4f, 0x1a, 0xc7, 0x8a, 0x23, 0x4d, 0x7e,
++ 0x6b, 0xae, 0x95, 0x5a, 0xf6, 0x2c, 0xcb, 0x93, 0x6a, 0xac, 0xe8, 0xc2,
++ 0x19, 0xd4, 0xd9, 0xf7, 0x87, 0x9c, 0xdb, 0xc4, 0x48, 0xe4, 0xd3, 0xeb,
++ 0xe8, 0xed, 0x93, 0x65, 0xda, 0x19, 0xbb, 0x56, 0xbe, 0x68, 0xad, 0xa3,
++ 0x6c, 0xef, 0x43, 0x32, 0x97, 0x5c, 0x78, 0x28, 0x69, 0xe5, 0x43, 0x3e,
++ 0xf7, 0x7c, 0x62, 0x42, 0x47, 0x84, 0xc8, 0xbf, 0x20, 0xcd, 0x0d, 0x20,
++ 0x71, 0x6e, 0xd9, 0xfe, 0x02, 0x1f, 0x10, 0xb1, 0x6d, 0x9c, 0x33, 0x03,
++ 0xa2, 0xd6, 0xb6, 0xd1, 0xe2, 0x7e, 0x03, 0xfc, 0xbe, 0x8f, 0xe6, 0x90,
++ 0x43, 0x14, 0x44, 0x1e, 0xde, 0x0e, 0x78, 0x37, 0x0f, 0xbf, 0x1f, 0xb9,
++ 0x01, 0xd3, 0xd8, 0x04, 0xfc, 0x6f, 0x03, 0xc6, 0x6b, 0x43, 0x9f, 0x6b,
++ 0x22, 0xf1, 0x3d, 0x8f, 0xb7, 0x13, 0xd7, 0x65, 0xab, 0xf3, 0xf2, 0x9c,
++ 0x3c, 0xf6, 0x61, 0xf9, 0xf6, 0xbe, 0x3e, 0xcf, 0xdc, 0x6d, 0x9e, 0xb9,
++ 0xef, 0xf0, 0xcc, 0xed, 0xc3, 0xb7, 0x2e, 0x3e, 0x41, 0x7c, 0xeb, 0xae,
++ 0xf1, 0xb7, 0x9e, 0x35, 0x5c, 0xdc, 0xdb, 0x3d, 0xb8, 0xbf, 0x8f, 0xf9,
++ 0xb9, 0xcf, 0xf4, 0xf4, 0xf1, 0x9a, 0x1b, 0x68, 0x6e, 0xb0, 0x8d, 0x16,
++ 0x4f, 0x72, 0x5f, 0xd0, 0x83, 0x0b, 0xe3, 0x17, 0x90, 0x63, 0x6d, 0x74,
++ 0xf1, 0x64, 0x8b, 0xc0, 0x9b, 0xfd, 0xf9, 0xc6, 0xca, 0x9a, 0x57, 0xb0,
++ 0xa6, 0x3b, 0x97, 0x89, 0x6f, 0x19, 0x96, 0xf1, 0xe3, 0x31, 0xee, 0xe3,
++ 0xb1, 0x37, 0xcb, 0x5f, 0x33, 0x82, 0xce, 0x9e, 0x0d, 0xc6, 0xcd, 0xfd,
++ 0x56, 0x6b, 0x26, 0x8b, 0xdb, 0x9d, 0x34, 0x1b, 0xd4, 0xc0, 0x37, 0x55,
++ 0xfa, 0x28, 0xae, 0x23, 0xa8, 0x4a, 0xb4, 0x8f, 0xf9, 0xbc, 0x4e, 0xd6,
++ 0xaf, 0x5b, 0x30, 0x6f, 0xd8, 0xcd, 0xd1, 0x88, 0xe5, 0x38, 0x27, 0xec,
++ 0xbe, 0x26, 0xc7, 0xd9, 0xee, 0xb3, 0xdf, 0xc7, 0x53, 0xc8, 0xaa, 0x3c,
++ 0xaf, 0x29, 0xed, 0xa0, 0x83, 0x50, 0xcf, 0x8b, 0xb2, 0x9e, 0xb2, 0xe8,
++ 0xad, 0x99, 0x18, 0x4e, 0x1c, 0xe3, 0x9c, 0xed, 0xac, 0x85, 0xfe, 0xe0,
++ 0xbd, 0x98, 0x00, 0x1e, 0x61, 0x8a, 0xe2, 0xaf, 0x50, 0xca, 0xe3, 0x69,
++ 0xe1, 0xa9, 0xe0, 0xc9, 0xf5, 0x0c, 0x1d, 0x4f, 0xe8, 0x18, 0xec, 0x53,
++ 0xb4, 0xef, 0x92, 0x93, 0x3f, 0x41, 0x37, 0xde, 0x9e, 0x74, 0xea, 0x51,
++ 0x8b, 0xd6, 0x72, 0xf5, 0xa8, 0x3f, 0x67, 0x9e, 0x9c, 0x70, 0xeb, 0x51,
++ 0x8b, 0x24, 0xea, 0x51, 0x27, 0x56, 0xa8, 0x47, 0x25, 0x56, 0x5f, 0x8f,
++ 0xe2, 0xf9, 0x35, 0xda, 0xd7, 0x4f, 0xca, 0x17, 0x64, 0x3d, 0xea, 0x3d,
++ 0x72, 0xea, 0x51, 0x17, 0xa9, 0x71, 0x3d, 0xea, 0x78, 0x5d, 0x3d, 0x2a,
++ 0x28, 0xea, 0x51, 0x3c, 0x8f, 0x53, 0x8f, 0x12, 0xed, 0xbe, 0x88, 0xa7,
++ 0xee, 0x42, 0xf4, 0xee, 0x64, 0x07, 0x68, 0x66, 0xd0, 0xf7, 0x1a, 0xda,
++ 0x34, 0x45, 0xc8, 0xdb, 0x4a, 0x35, 0xd0, 0x07, 0x6e, 0xb8, 0xbe, 0xa2,
++ 0xd0, 0x06, 0xcc, 0x9b, 0xec, 0x7b, 0xd8, 0x53, 0x63, 0x61, 0x9a, 0xff,
++ 0x62, 0xea, 0x2c, 0x07, 0x45, 0x9d, 0xe5, 0x87, 0x6b, 0xbc, 0x75, 0x96,
++ 0x45, 0xba, 0x7e, 0x9d, 0xe5, 0x60, 0x83, 0x3a, 0xcb, 0x5b, 0x54, 0xad,
++ 0xb3, 0xbc, 0x45, 0xd5, 0x3a, 0xcb, 0xc1, 0x12, 0xe7, 0xe2, 0x3e, 0x89,
++ 0x5f, 0x06, 0xed, 0x41, 0xf1, 0xc7, 0xb5, 0x97, 0xc5, 0xca, 0x1e, 0x7e,
++ 0xd9, 0x6a, 0x2f, 0x6c, 0x03, 0x22, 0x17, 0x2e, 0xd7, 0xd4, 0x5e, 0xb8,
++ 0x0d, 0x9d, 0xb1, 0xd7, 0x08, 0x19, 0x99, 0x83, 0x7f, 0x5f, 0x9c, 0x0c,
++ 0x61, 0xce, 0x0e, 0xf8, 0x8c, 0x0e, 0xe4, 0x06, 0x61, 0xb4, 0x15, 0xda,
++ 0x64, 0x0d, 0xa1, 0x8f, 0xc7, 0xd9, 0x0e, 0x43, 0xb7, 0x6c, 0x77, 0x7f,
++ 0x0f, 0x48, 0x1a, 0x44, 0x68, 0xb8, 0x9d, 0xf4, 0x20, 0xfb, 0x8e, 0xc9,
++ 0x3d, 0x74, 0xc8, 0xde, 0x22, 0xf6, 0xbd, 0xc1, 0xaa, 0x95, 0xb9, 0xc1,
++ 0x1b, 0x90, 0xb9, 0xcc, 0xaa, 0x65, 0x8e, 0xe5, 0xcd, 0x39, 0xf7, 0xdd,
++ 0x60, 0xf1, 0xfa, 0x1d, 0x02, 0xa7, 0x77, 0x1b, 0xc8, 0xfb, 0x18, 0xec,
++ 0x8e, 0x33, 0xbf, 0x2e, 0xd7, 0xab, 0x8f, 0x87, 0x9f, 0x6d, 0x66, 0xff,
++ 0xbd, 0x72, 0x3d, 0xb1, 0xde, 0x7f, 0xaf, 0xe4, 0x47, 0x15, 0x61, 0x93,
++ 0xb3, 0x25, 0xae, 0xed, 0x7b, 0xf9, 0x33, 0x8f, 0x9c, 0x00, 0x7d, 0x42,
++ 0x0f, 0x98, 0xae, 0x41, 0xf0, 0x01, 0xeb, 0xd8, 0x4f, 0xc9, 0x5a, 0x16,
++ 0x9e, 0x05, 0x97, 0x7f, 0xad, 0xb0, 0x99, 0xee, 0x18, 0xdb, 0x01, 0x0b,
++ 0xfe, 0x8f, 0xeb, 0x28, 0x7c, 0x8e, 0xca, 0xfd, 0x2e, 0x5f, 0xbb, 0x2e,
++ 0xbc, 0xa7, 0x72, 0xbb, 0x5c, 0xce, 0x8a, 0x7a, 0x2d, 0xa9, 0x9d, 0x7d,
++ 0xd3, 0x2d, 0x6c, 0x6b, 0xb6, 0x58, 0xae, 0xcc, 0x26, 0xf0, 0xce, 0x7c,
++ 0x7d, 0x17, 0x36, 0x9c, 0xcf, 0xaa, 0xbf, 0x23, 0x6a, 0x04, 0x73, 0x36,
++ 0xdb, 0x6b, 0x8e, 0x41, 0x7f, 0x0b, 0xb2, 0xc4, 0xef, 0x51, 0x71, 0x2e,
++ 0x21, 0x6a, 0xf8, 0x83, 0xdc, 0x76, 0xed, 0x4a, 0x94, 0xed, 0x30, 0xf6,
++ 0x5c, 0xa5, 0x31, 0xe2, 0x23, 0xc8, 0x0c, 0xc7, 0xb1, 0x0c, 0xe7, 0xc6,
++ 0x9e, 0x9a, 0xa7, 0x66, 0xab, 0xcb, 0xb8, 0x88, 0x75, 0x39, 0x00, 0x9a,
++ 0xed, 0x10, 0x31, 0xea, 0xb8, 0x5d, 0xa6, 0xea, 0x19, 0x3f, 0xd3, 0xdc,
++ 0x39, 0xe7, 0x3f, 0x66, 0x2f, 0x47, 0xfb, 0xcd, 0x37, 0x48, 0x7b, 0x47,
++ 0x1f, 0x6b, 0xe9, 0xae, 0x23, 0x7e, 0x71, 0xe9, 0xee, 0xfa, 0xa8, 0x49,
++ 0x49, 0x83, 0xa8, 0xac, 0x2b, 0x7e, 0x5a, 0x9e, 0x29, 0xfd, 0x5f, 0xd8,
++ 0xaf, 0xe2, 0xd9, 0xaf, 0xab, 0xbb, 0xfb, 0xe4, 0x7e, 0xc3, 0x75, 0xba,
++ 0x1b, 0x97, 0x75, 0xb9, 0x5f, 0x84, 0xee, 0xba, 0x7b, 0xe2, 0xb5, 0xb7,
++ 0x5c, 0x67, 0xdd, 0x67, 0x48, 0x8d, 0xaf, 0x14, 0x7b, 0xff, 0xb4, 0xf9,
++ 0xe3, 0xc5, 0xde, 0x1f, 0x87, 0x9e, 0x5e, 0xbd, 0x65, 0x1a, 0xb6, 0x89,
++ 0xb8, 0xc2, 0xd1, 0x1f, 0xd8, 0xe3, 0x82, 0x9f, 0x16, 0x1e, 0xd2, 0xe9,
++ 0x9f, 0xee, 0xe4, 0xfa, 0xac, 0x26, 0x73, 0x7c, 0x6e, 0x7f, 0xb1, 0x95,
++ 0x63, 0xab, 0x4d, 0xd6, 0x77, 0x44, 0x6e, 0x95, 0x57, 0x4d, 0x8f, 0x1f,
++ 0x31, 0x30, 0xce, 0x63, 0x61, 0xba, 0x1c, 0xbc, 0x91, 0xb8, 0xbc, 0xcb,
++ 0x58, 0xf4, 0xad, 0x26, 0x2e, 0xbf, 0x55, 0xf7, 0x5b, 0x7f, 0xdd, 0x7a,
++ 0xbd, 0x3a, 0x47, 0x35, 0x2e, 0xe7, 0x7c, 0x3e, 0xe8, 0xd4, 0x18, 0x4c,
++ 0x8e, 0xcf, 0xd7, 0x4a, 0x9e, 0xf0, 0x3b, 0x72, 0x11, 0x1b, 0x79, 0x08,
++ 0x64, 0xfc, 0x55, 0xc8, 0xca, 0x2b, 0x36, 0xf2, 0x0e, 0x1b, 0xf9, 0x88,
++ 0x8d, 0xdc, 0xc3, 0x46, 0xee, 0x61, 0xf7, 0xc8, 0x1c, 0x26, 0x23, 0xeb,
++ 0x56, 0x7c, 0x46, 0xcb, 0xf9, 0x61, 0x5e, 0xc9, 0xd8, 0xe3, 0x7c, 0x1f,
++ 0x41, 0x4d, 0xc6, 0x36, 0xca, 0x78, 0xf0, 0x38, 0xdf, 0x77, 0x28, 0xab,
++ 0x71, 0xae, 0x45, 0x91, 0xaa, 0xc6, 0x6f, 0x87, 0x8f, 0xda, 0x0e, 0xbc,
++ 0x9a, 0x79, 0xdc, 0xa7, 0xc6, 0x5b, 0x99, 0x76, 0x8a, 0x1a, 0x5f, 0x2b,
++ 0xcf, 0x0d, 0x7a, 0x03, 0x0e, 0xfe, 0xdd, 0xdc, 0xd6, 0xd4, 0xf8, 0xdd,
++ 0xec, 0xd3, 0xc2, 0xa4, 0xba, 0xfd, 0xb7, 0x07, 0x98, 0xae, 0xa4, 0xde,
++ 0x16, 0xe0, 0xb8, 0x76, 0xde, 0xf6, 0x8b, 0x3b, 0x05, 0xc9, 0x18, 0xd7,
++ 0xcc, 0xb8, 0x5d, 0xa5, 0xab, 0xba, 0x2c, 0x5d, 0xfd, 0x95, 0xfa, 0x3f,
++ 0xd3, 0xd2, 0xc7, 0x70, 0xa2, 0x36, 0xc6, 0x34, 0x75, 0xe7, 0xe3, 0xf3,
++ 0x66, 0x5e, 0x47, 0xdc, 0x63, 0xc0, 0xf3, 0x60, 0x33, 0xb5, 0x0d, 0x0e,
++ 0xf9, 0x2d, 0xef, 0xba, 0x6c, 0x43, 0x76, 0x90, 0x37, 0xc7, 0x5a, 0x7e,
++ 0xcd, 0xa8, 0x38, 0x1b, 0x49, 0xf6, 0x47, 0x85, 0xec, 0xb0, 0xac, 0x69,
++ 0xe2, 0xce, 0xd5, 0x47, 0xe2, 0x1e, 0x09, 0xcb, 0x19, 0xcb, 0xf2, 0x78,
++ 0x7f, 0x57, 0x58, 0x53, 0x5b, 0xb0, 0x46, 0x98, 0xd2, 0x25, 0x71, 0x56,
++ 0x80, 0x7c, 0xe9, 0xdc, 0x3a, 0x6a, 0xfb, 0x07, 0xbd, 0x9a, 0xc7, 0x46,
++ 0x9d, 0xb3, 0x7a, 0xbb, 0xde, 0xff, 0x8d, 0x8a, 0x73, 0x65, 0xc7, 0x06,
++ 0xb9, 0xe7, 0xc3, 0xab, 0x3b, 0xff, 0xbe, 0xbe, 0x3e, 0xb5, 0xd4, 0xd7,
++ 0x0d, 0x24, 0x0d, 0x98, 0x36, 0x8d, 0xcf, 0xee, 0xe7, 0x4b, 0x7c, 0xaf,
++ 0x25, 0x12, 0xe3, 0xdc, 0x6d, 0x44, 0xdc, 0xf9, 0x50, 0x21, 0x85, 0x3a,
++ 0x8d, 0x19, 0x9c, 0xf3, 0x85, 0x86, 0x7d, 0x71, 0xca, 0x64, 0x27, 0x48,
++ 0x43, 0xac, 0x98, 0xa9, 0xd6, 0x03, 0x1f, 0x5c, 0x43, 0x96, 0x2b, 0x97,
++ 0x51, 0xce, 0x1f, 0x6a, 0xce, 0xed, 0x16, 0xe9, 0xb0, 0x72, 0xa0, 0x74,
++ 0x84, 0x0e, 0x34, 0x8c, 0x29, 0x1b, 0xd7, 0x03, 0x2f, 0xd6, 0xd5, 0x14,
++ 0x16, 0x44, 0x4d, 0x21, 0xb7, 0xc6, 0x6f, 0x3d, 0x19, 0x70, 0xee, 0xb5,
++ 0x34, 0xd6, 0x93, 0x5d, 0x15, 0x3d, 0x71, 0xe1, 0xf8, 0x2c, 0xbe, 0x8d,
++ 0x76, 0x8a, 0xb5, 0x0e, 0x2b, 0x59, 0xbb, 0x95, 0x76, 0x1a, 0x0e, 0xd6,
++ 0xa3, 0x36, 0xe3, 0x75, 0x58, 0x39, 0x68, 0xe7, 0x95, 0xb4, 0xa8, 0x3d,
++ 0x70, 0x8c, 0xbf, 0xe6, 0xda, 0x30, 0x95, 0xe9, 0xed, 0x98, 0xfb, 0x3d,
++ 0xc3, 0x78, 0x6b, 0x8a, 0x2e, 0x9d, 0xf8, 0x2e, 0x51, 0x58, 0xe6, 0x6f,
++ 0xce, 0x7c, 0xb9, 0x29, 0xae, 0x25, 0xde, 0x8f, 0xfd, 0x33, 0xfc, 0x6e,
++ 0x25, 0x39, 0x55, 0x2e, 0xa7, 0x31, 0x3e, 0xd6, 0x7b, 0xaf, 0xc8, 0x8d,
++ 0xd4, 0x38, 0x0d, 0x71, 0x8e, 0xac, 0x2d, 0xc9, 0x91, 0xd3, 0xd0, 0x35,
++ 0xc4, 0x20, 0x76, 0x13, 0xbe, 0x75, 0xe3, 0x91, 0xcf, 0xae, 0x75, 0x64,
++ 0xe4, 0xbb, 0x12, 0x0f, 0x1e, 0xff, 0xfb, 0x80, 0x7b, 0x0f, 0x28, 0x77,
++ 0x2a, 0x8d, 0xfd, 0x37, 0x51, 0xca, 0x74, 0xf2, 0xbb, 0xec, 0x99, 0x23,
++ 0x1b, 0x6a, 0xe1, 0xd1, 0x77, 0xca, 0x85, 0x0f, 0xd6, 0xc1, 0xf3, 0x19,
++ 0xd7, 0x5f, 0xd5, 0xc1, 0x07, 0x3d, 0xf0, 0x66, 0x1d, 0x3c, 0xe2, 0xae,
++ 0x33, 0xdf, 0xa8, 0x83, 0x37, 0x3d, 0xf0, 0xed, 0x75, 0xf0, 0xed, 0x80,
++ 0x7f, 0xa3, 0x0e, 0x1e, 0x7d, 0xa7, 0x90, 0x13, 0x08, 0xda, 0x70, 0x8c,
++ 0x74, 0x48, 0xe6, 0x89, 0x78, 0x2e, 0xb9, 0x1f, 0xc9, 0xf2, 0xd3, 0x01,
++ 0x1a, 0x7b, 0xeb, 0xb5, 0x09, 0xd8, 0xa8, 0xaa, 0x4c, 0x39, 0xfa, 0xea,
++ 0x95, 0x25, 0x96, 0xbd, 0x3c, 0xe4, 0x15, 0x7a, 0x54, 0x80, 0x3e, 0x15,
++ 0x5c, 0x5f, 0xca, 0x77, 0xaa, 0x22, 0xc7, 0x1d, 0x3d, 0x56, 0x68, 0xbd,
++ 0x35, 0x2f, 0x73, 0x91, 0xab, 0x8c, 0x3b, 0xfc, 0x86, 0xeb, 0x3b, 0xe8,
++ 0x84, 0x63, 0x57, 0x58, 0xbf, 0x79, 0x7e, 0x69, 0x5f, 0x4a, 0x2c, 0x87,
++ 0xce, 0x3a, 0xe9, 0x25, 0x32, 0x1b, 0x5e, 0x52, 0x77, 0xf1, 0xd5, 0xd9,
++ 0x77, 0x12, 0xf6, 0x3d, 0xd7, 0xe2, 0xb7, 0x36, 0xac, 0xbd, 0x9e, 0x7d,
++ 0xcf, 0x78, 0xec, 0x7b, 0x38, 0x58, 0xf5, 0xf9, 0x8f, 0x09, 0x9f, 0xdf,
++ 0xd1, 0xc0, 0x66, 0xac, 0xde, 0xe7, 0xef, 0xfd, 0xd8, 0x3e, 0x7f, 0xb9,
++ 0x75, 0x57, 0xe3, 0xf3, 0x1f, 0x69, 0xf9, 0x78, 0x3e, 0x9f, 0xd7, 0xac,
++ 0xaf, 0x65, 0x7a, 0xcf, 0x59, 0x8e, 0xca, 0x18, 0x7b, 0xb7, 0x27, 0xc6,
++ 0x66, 0xfc, 0xbe, 0x27, 0xef, 0x02, 0x9e, 0x5e, 0xeb, 0xc8, 0xdb, 0x51,
++ 0x19, 0xa7, 0x73, 0xec, 0x8d, 0xf7, 0xc2, 0x23, 0x90, 0xd1, 0x7c, 0x8f,
++ 0x8f, 0x54, 0x9a, 0x35, 0x9d, 0xb3, 0xed, 0x9f, 0x6f, 0xae, 0x17, 0xa1,
++ 0xcb, 0xc2, 0x9f, 0x24, 0x3e, 0x81, 0x5a, 0xea, 0x49, 0xc8, 0x8f, 0xbb,
++ 0xaf, 0x95, 0x6a, 0xa9, 0xf5, 0xe7, 0x1f, 0x7c, 0xee, 0x41, 0xca, 0x03,
++ 0x95, 0x73, 0x10, 0xaf, 0x4e, 0xe9, 0x94, 0x9d, 0x21, 0xdd, 0x8c, 0x93,
++ 0xb2, 0x8f, 0x71, 0x8e, 0xfd, 0xb0, 0x52, 0x6f, 0x3f, 0x24, 0x6b, 0x30,
++ 0xea, 0xb2, 0x77, 0x82, 0x7e, 0x02, 0x7c, 0x58, 0xaf, 0x9c, 0x1a, 0x8c,
++ 0xea, 0xdc, 0x09, 0x3a, 0xfe, 0xf3, 0xbb, 0x13, 0xc4, 0xf3, 0x6b, 0xb4,
++ 0xb7, 0xc1, 0x9d, 0x20, 0xdf, 0x2a, 0xef, 0x04, 0xad, 0x17, 0x35, 0x18,
++ 0x9e, 0xc7, 0xa9, 0xc1, 0x70, 0xbb, 0xb3, 0x8f, 0xe5, 0x3a, 0x4c, 0xa3,
++ 0x93, 0xb7, 0x88, 0x7b, 0xa8, 0x9d, 0x7d, 0xb5, 0xf2, 0xbd, 0xef, 0x13,
++ 0x8d, 0xa5, 0x79, 0xbd, 0xa3, 0x0d, 0xef, 0xb6, 0x24, 0x3f, 0xc1, 0x9a,
++ 0xcb, 0x21, 0x51, 0x73, 0xb9, 0xb3, 0xcd, 0x5b, 0x73, 0x51, 0x57, 0xb8,
++ 0xdb, 0x72, 0xa8, 0x41, 0xcd, 0xc5, 0xef, 0xb9, 0xdb, 0xe2, 0xf7, 0xdc,
++ 0x6d, 0x39, 0x24, 0xeb, 0x2b, 0xea, 0x2f, 0xd1, 0xdd, 0x96, 0xe4, 0x8a,
++ 0x77, 0x5b, 0xb6, 0x4a, 0x7d, 0xf5, 0xc2, 0xaf, 0xfe, 0xbc, 0x32, 0x55,
++ 0x67, 0xe7, 0x13, 0xc2, 0xce, 0xdf, 0xd5, 0xea, 0xb7, 0x9e, 0x69, 0xbb,
++ 0x9e, 0x9d, 0xdf, 0x57, 0xd1, 0x53, 0xbe, 0xa3, 0xcd, 0x77, 0xbe, 0x58,
++ 0x16, 0xf9, 0x7c, 0xa6, 0x89, 0x72, 0x03, 0xbf, 0x2a, 0x68, 0xf6, 0x58,
++ 0x6f, 0xed, 0x99, 0x63, 0xf5, 0x5e, 0xa4, 0xee, 0xb9, 0x17, 0x69, 0xa2,
++ 0x5f, 0xaf, 0xab, 0x87, 0x04, 0xe4, 0xdd, 0x7e, 0xf8, 0xc2, 0x19, 0x43,
++ 0xda, 0x5e, 0xc4, 0x70, 0x98, 0xae, 0x50, 0xe4, 0x3b, 0x95, 0x6d, 0xe4,
++ 0x9b, 0x71, 0xce, 0x4b, 0x54, 0x11, 0x63, 0x42, 0x8e, 0x8b, 0x7e, 0xe1,
++ 0x6f, 0xd4, 0xb8, 0x23, 0xb3, 0xe3, 0xf6, 0x05, 0xe0, 0xbf, 0x21, 0x51,
++ 0x6d, 0x9b, 0x95, 0x5a, 0xce, 0x58, 0xe5, 0x0e, 0xbf, 0x09, 0xfb, 0xe0,
++ 0xdc, 0x07, 0xca, 0x98, 0x7c, 0x67, 0xe4, 0x62, 0x5b, 0xf5, 0x3e, 0xd0,
++ 0x67, 0xa4, 0x9c, 0x3a, 0xf7, 0x81, 0x48, 0x4d, 0x40, 0x3e, 0x6e, 0xe4,
++ 0x3e, 0x50, 0xd7, 0x92, 0xfb, 0x40, 0x2b, 0xf3, 0x66, 0xe9, 0x7d, 0xa0,
++ 0xc6, 0xfc, 0xe1, 0xfb, 0x40, 0xff, 0xde, 0xe6, 0xdc, 0x43, 0x5d, 0x89,
++ 0x3f, 0x6e, 0x9c, 0xf4, 0x11, 0xe0, 0xf9, 0x3e, 0x50, 0xe5, 0x1e, 0x90,
++ 0xe7, 0x0e, 0x10, 0xdf, 0x25, 0x59, 0xee, 0x0c, 0xce, 0x7b, 0xff, 0xa4,
++ 0xa7, 0x72, 0xff, 0xe4, 0x7c, 0xc9, 0xf5, 0xed, 0xee, 0xb9, 0x1c, 0xc7,
++ 0x39, 0xbb, 0x44, 0x8e, 0x7a, 0xae, 0x54, 0x5b, 0xc3, 0x60, 0xbe, 0x8f,
++ 0x16, 0xcf, 0x81, 0x3e, 0x6f, 0x89, 0xdc, 0x00, 0x7c, 0xde, 0xe2, 0x23,
++ 0xe6, 0x1d, 0x29, 0xa0, 0x8b, 0x38, 0xcb, 0x75, 0xf8, 0xdd, 0x21, 0x64,
++ 0xc1, 0x91, 0x8b, 0xdd, 0x9e, 0xf3, 0xd0, 0xaa, 0x1c, 0x38, 0x67, 0xba,
++ 0x0e, 0xef, 0x6a, 0x65, 0x46, 0x9c, 0xdd, 0x0c, 0xed, 0xb5, 0x9c, 0xf3,
++ 0xc6, 0xa8, 0x38, 0xb7, 0x6d, 0xaf, 0xb3, 0x5b, 0x3a, 0xe4, 0x06, 0x31,
++ 0x67, 0x8c, 0xeb, 0xd5, 0x8c, 0xfb, 0x66, 0xc1, 0xe3, 0x46, 0x67, 0x71,
++ 0x2b, 0xd7, 0xf1, 0xdc, 0x9a, 0x0a, 0x21, 0x97, 0xd8, 0x9d, 0xce, 0x09,
++ 0xbb, 0xe9, 0xac, 0xdd, 0x29, 0xd6, 0xde, 0x58, 0x77, 0x96, 0xcd, 0x72,
++ 0xb5, 0x5c, 0x4c, 0x70, 0x3d, 0x9a, 0xde, 0xb3, 0x84, 0xa6, 0xb5, 0xba,
++ 0x84, 0xdc, 0xb5, 0x62, 0xe3, 0x3b, 0x2a, 0xba, 0x34, 0x2e, 0xee, 0x21,
++ 0xbb, 0xe7, 0xb5, 0x0e, 0xfd, 0xaa, 0xba, 0xb7, 0x5c, 0x3c, 0x53, 0x4f,
++ 0xbf, 0x4d, 0xff, 0x4b, 0xe8, 0x77, 0x15, 0xf4, 0xe3, 0x77, 0x03, 0xef,
++ 0xef, 0x8a, 0x7a, 0xc0, 0xb9, 0x52, 0xe4, 0x78, 0x9e, 0x38, 0x4e, 0x88,
++ 0xcc, 0x2e, 0x50, 0x0f, 0xe8, 0xc8, 0xff, 0xeb, 0xe2, 0xde, 0x9d, 0x60,
++ 0xfa, 0xb2, 0x7d, 0x8f, 0xbc, 0x70, 0x99, 0xd8, 0xc6, 0xdf, 0x8d, 0x7d,
++ 0x94, 0xcb, 0x2f, 0xc5, 0x5c, 0xfa, 0xb3, 0xee, 0x73, 0x9d, 0xaa, 0x76,
++ 0x5f, 0x7b, 0x57, 0xed, 0x53, 0x1d, 0xf9, 0xcc, 0x34, 0x90, 0xcf, 0x8c,
++ 0xdc, 0xa3, 0x6f, 0xa6, 0x71, 0xbc, 0x9a, 0x9a, 0xfc, 0xef, 0x5e, 0xae,
++ 0x26, 0xb6, 0x8d, 0x22, 0x0a, 0xbf, 0xac, 0xd7, 0x4e, 0xe3, 0xa4, 0x61,
++ 0x93, 0x3a, 0xad, 0x69, 0xd2, 0x60, 0xc7, 0x4b, 0x12, 0x29, 0xa5, 0xa4,
++ 0x52, 0x55, 0x45, 0x60, 0xa9, 0x21, 0x4e, 0xda, 0x0a, 0x71, 0x70, 0x0b,
++ 0x48, 0x51, 0xc5, 0x21, 0x4d, 0xd3, 0x7b, 0x85, 0x84, 0x54, 0xa1, 0x8a,
++ 0x46, 0x4e, 0x02, 0x15, 0x4a, 0xe5, 0x0a, 0x96, 0x72, 0x41, 0xa2, 0xd8,
++ 0x8e, 0x02, 0x52, 0x2a, 0xf7, 0xca, 0x85, 0xba, 0xbf, 0x08, 0x89, 0x03,
++ 0x70, 0x06, 0x29, 0x2a, 0x3f, 0xe2, 0xc0, 0x8d, 0x1b, 0x54, 0x5d, 0xde,
++ 0x37, 0xb3, 0x63, 0xaf, 0x77, 0xd7, 0x8e, 0x03, 0x11, 0x07, 0x27, 0xbb,
++ 0xf6, 0xcc, 0xce, 0xec, 0xcc, 0x37, 0x6f, 0xbe, 0xf7, 0x37, 0xfd, 0xbe,
++ 0x78, 0x8d, 0x5a, 0xdb, 0x5b, 0xf3, 0x55, 0xec, 0xe7, 0xaf, 0x37, 0x18,
++ 0x57, 0xed, 0xba, 0xe4, 0xa9, 0xf5, 0xe3, 0x9a, 0x72, 0xd9, 0x1b, 0xf0,
++ 0xfe, 0xc7, 0x68, 0x51, 0xd8, 0x86, 0x94, 0xad, 0xee, 0xc5, 0x40, 0x9b,
++ 0xd9, 0xff, 0x33, 0x16, 0x03, 0x3e, 0x9b, 0x68, 0xad, 0x6d, 0x8a, 0xed,
++ 0x71, 0xd9, 0x16, 0xde, 0xda, 0xc2, 0xb6, 0x10, 0x3c, 0x16, 0xfd, 0x9e,
++ 0xb1, 0xa8, 0xc9, 0xea, 0xa1, 0x16, 0xed, 0x74, 0x88, 0x21, 0xbf, 0x9d,
++ 0x67, 0x6c, 0x05, 0xca, 0xce, 0x4f, 0x5d, 0x36, 0x3c, 0xe0, 0x73, 0xdc,
++ 0x59, 0xeb, 0xc0, 0x27, 0xb5, 0x9d, 0x1a, 0x51, 0xed, 0x01, 0x8f, 0xc9,
++ 0xc5, 0x45, 0x82, 0xbe, 0x86, 0x36, 0xe3, 0x82, 0xe3, 0xfa, 0x39, 0x14,
++ 0x8f, 0xf1, 0xfa, 0x1b, 0x88, 0xe5, 0x70, 0xda, 0x3f, 0xd9, 0x76, 0xae,
++ 0x9c, 0xe5, 0xbd, 0x42, 0xd4, 0x63, 0xbd, 0xef, 0x52, 0xdb, 0x82, 0xa8,
++ 0x27, 0xe3, 0x20, 0x1c, 0x1d, 0xd0, 0xe1, 0xe2, 0x8d, 0x74, 0x3f, 0xff,
++ 0x9e, 0x13, 0xcc, 0xdd, 0x7f, 0xdd, 0x1d, 0x36, 0x3f, 0x34, 0x64, 0xae,
++ 0xde, 0x56, 0xdc, 0x5d, 0xd9, 0x89, 0x06, 0x85, 0xaf, 0xc1, 0xad, 0x7b,
++ 0x41, 0x76, 0x5d, 0xe0, 0x3d, 0x7c, 0xa8, 0xba, 0x7f, 0xef, 0x84, 0x7d,
++ 0xe8, 0x99, 0x16, 0x62, 0x1d, 0x44, 0x8e, 0xe5, 0x2b, 0x53, 0xc8, 0x45,
++ 0xaa, 0xe6, 0xef, 0x78, 0xf3, 0x3c, 0x20, 0x3f, 0x55, 0x9e, 0x87, 0xca,
++ 0x23, 0xc5, 0x7b, 0x24, 0x02, 0xf2, 0x3c, 0xdc, 0x32, 0x18, 0xf5, 0xea,
++ 0xdf, 0xc3, 0x2d, 0x7f, 0x57, 0x1c, 0xf9, 0x5b, 0xf0, 0xd8, 0xe3, 0x97,
++ 0xf3, 0x6a, 0x2d, 0x20, 0xe7, 0x43, 0xf1, 0x94, 0xde, 0x00, 0x9e, 0x12,
++ 0x9c, 0xeb, 0xa1, 0xa5, 0x2f, 0xf2, 0x5e, 0x7e, 0x08, 0x7b, 0xb9, 0x51,
++ 0x8b, 0xe9, 0x95, 0x72, 0xf0, 0xdc, 0x3a, 0x64, 0xa2, 0xca, 0xb9, 0x81,
++ 0x5c, 0x44, 0x2c, 0x3c, 0xe6, 0xba, 0xe4, 0x60, 0x11, 0xbf, 0xa9, 0x58,
++ 0x52, 0xa5, 0x47, 0xbd, 0x23, 0xf2, 0x0c, 0xbe, 0x1b, 0x3f, 0xcc, 0x1c,
++ 0x18, 0xf2, 0x13, 0x76, 0xa6, 0x43, 0x0e, 0x1f, 0xbe, 0xcc, 0xbf, 0x8d,
++ 0x39, 0xd7, 0x92, 0x8b, 0xca, 0x6b, 0xa5, 0x4b, 0xfd, 0xd0, 0x41, 0xe6,
++ 0x6f, 0x0e, 0x2f, 0xad, 0xb3, 0x41, 0xc4, 0x53, 0xda, 0xdb, 0x74, 0xa1,
++ 0xd8, 0x0c, 0x83, 0xf5, 0xf8, 0x4b, 0x79, 0x38, 0x4f, 0x42, 0x70, 0x9e,
++ 0x9f, 0x3a, 0xc2, 0xe6, 0x44, 0x4f, 0xb3, 0x38, 0x9c, 0x53, 0x55, 0xfc,
++ 0xa9, 0x72, 0xaa, 0x6f, 0x8f, 0x3a, 0x10, 0xa7, 0xe6, 0xc7, 0x04, 0xe6,
++ 0x1f, 0xfa, 0x9c, 0x5a, 0x87, 0xd0, 0xeb, 0x10, 0xf3, 0x87, 0x76, 0x8d,
++ 0x06, 0x6b, 0xb0, 0x66, 0x13, 0x2f, 0x50, 0x2b, 0xb1, 0x7f, 0xc9, 0xd1,
++ 0x0a, 0x9d, 0xed, 0x69, 0xa6, 0xf3, 0x9e, 0x08, 0xd4, 0x79, 0x83, 0x72,
++ 0xa4, 0xcc, 0x80, 0x1c, 0x29, 0x37, 0x0e, 0x75, 0x17, 0x0e, 0xe3, 0x2e,
++ 0x2e, 0x30, 0xc0, 0xdc, 0xb9, 0x8b, 0xf1, 0x04, 0xee, 0x1c, 0xa5, 0xd0,
++ 0x07, 0x6e, 0xee, 0xec, 0xf7, 0x13, 0x49, 0x5c, 0xfe, 0xdb, 0xdc, 0xa9,
++ 0xa0, 0x7e, 0x27, 0x7c, 0xfd, 0x86, 0x1c, 0x9f, 0x6c, 0xc8, 0x13, 0x82,
++ 0x38, 0xfe, 0x4e, 0xf7, 0xd3, 0xbb, 0xf6, 0xd1, 0xa6, 0x09, 0xfd, 0x70,
++ 0x74, 0xb1, 0xba, 0xee, 0x5f, 0xf0, 0xd9, 0xb9, 0xc1, 0x67, 0x43, 0xc2,
++ 0x27, 0xd7, 0x25, 0xf6, 0x90, 0x9d, 0x93, 0x61, 0x9d, 0x1e, 0x19, 0x66,
++ 0xf7, 0xd4, 0xec, 0xfc, 0x88, 0x21, 0xec, 0x73, 0x74, 0x0e, 0xb9, 0xef,
++ 0x14, 0x1a, 0xc6, 0xa5, 0xe2, 0x3b, 0xe9, 0x1b, 0x38, 0x77, 0x04, 0xb2,
++ 0x1b, 0xf2, 0xfc, 0xf4, 0x6c, 0xd8, 0x34, 0x1c, 0x1f, 0x03, 0xfc, 0x08,
++ 0xc0, 0xa9, 0x7a, 0x7e, 0x90, 0x0d, 0x3d, 0x68, 0x0e, 0x87, 0x7c, 0x73,
++ 0x28, 0xf1, 0x06, 0x6e, 0x8f, 0x58, 0xbc, 0x83, 0x9e, 0x38, 0xc5, 0x9d,
++ 0x18, 0x93, 0xee, 0x80, 0x78, 0x41, 0xc4, 0xfa, 0xf9, 0xfa, 0xcb, 0xef,
++ 0x7c, 0x51, 0xf3, 0xaf, 0xad, 0x49, 0x6d, 0xba, 0x3c, 0xad, 0x4d, 0x15,
++ 0x51, 0xee, 0xa2, 0x56, 0xdb, 0x97, 0x36, 0x5d, 0x1c, 0x11, 0x7c, 0x30,
++ 0x79, 0xad, 0x42, 0x78, 0x4f, 0xdb, 0xbe, 0x25, 0xb8, 0xed, 0x80, 0x0f,
++ 0xab, 0x8a, 0x73, 0x18, 0x2d, 0xbc, 0x97, 0xb4, 0xbd, 0xb8, 0xb9, 0x8e,
++ 0x5b, 0xbe, 0x3f, 0x1d, 0x20, 0xdf, 0x9b, 0xd9, 0x0a, 0x91, 0xbf, 0x29,
++ 0xe2, 0xb2, 0xa9, 0x68, 0x21, 0xde, 0xf1, 0x30, 0xe2, 0x7b, 0xe1, 0xd7,
++ 0xa8, 0x62, 0xe1, 0x6e, 0x30, 0x16, 0xaa, 0xf6, 0x60, 0x1d, 0xb9, 0xa3,
++ 0x2c, 0x8b, 0xc3, 0xe9, 0x5e, 0x0a, 0x99, 0x28, 0xff, 0x6c, 0xe2, 0x3e,
++ 0x1d, 0x73, 0x78, 0x09, 0xfc, 0x3c, 0xb2, 0xde, 0x4c, 0x0b, 0x76, 0xe1,
++ 0x60, 0x7f, 0x46, 0x84, 0x65, 0xf3, 0x67, 0xbd, 0xad, 0xf9, 0x33, 0x54,
++ 0x39, 0xd4, 0xed, 0xa2, 0x35, 0x0b, 0x71, 0x92, 0xf0, 0x2f, 0x75, 0x77,
++ 0xb4, 0x9b, 0x41, 0xf2, 0x4f, 0xc5, 0x7e, 0x82, 0x1f, 0xc9, 0xb9, 0xba,
++ 0x41, 0x98, 0x3b, 0x9b, 0xbe, 0x6f, 0x30, 0x57, 0xdb, 0xb1, 0x29, 0x37,
++ 0x9f, 0x2b, 0xc3, 0x33, 0x57, 0xd8, 0x8b, 0x9a, 0xcd, 0x95, 0xf2, 0x43,
++ 0x2a, 0xdf, 0xdc, 0x51, 0xc8, 0x93, 0x45, 0xf7, 0x5c, 0xed, 0x8c, 0x7f,
++ 0x4e, 0xce, 0xd9, 0x4e, 0xfb, 0xe0, 0x1a, 0x8f, 0x43, 0x34, 0xd0, 0x76,
++ 0x12, 0x2c, 0x33, 0xfc, 0x6b, 0xeb, 0x86, 0x5c, 0x5b, 0xcc, 0x2b, 0x9e,
++ 0x6f, 0xb8, 0xb6, 0xb0, 0x0f, 0x5c, 0x70, 0xf6, 0x81, 0xd3, 0x3e, 0x7d,
++ 0x51, 0xd9, 0xbc, 0xff, 0xab, 0xed, 0x0d, 0xcf, 0x7d, 0x22, 0xce, 0xe9,
++ 0xc8, 0x91, 0xdc, 0x47, 0xce, 0x37, 0xe4, 0x61, 0x3d, 0xdb, 0x5c, 0xa7,
++ 0x6a, 0xee, 0x91, 0x73, 0x01, 0x79, 0x99, 0xa5, 0xf3, 0xf9, 0xc7, 0x06,
++ 0x75, 0xf7, 0x53, 0xa4, 0x1a, 0xd3, 0x72, 0x40, 0xf0, 0x61, 0xb7, 0xbe,
++ 0xbc, 0xec, 0xe4, 0x28, 0xe6, 0x5c, 0x63, 0xb0, 0x9c, 0xcf, 0x36, 0x89,
++ 0xa7, 0x6f, 0x25, 0x9e, 0x63, 0xc0, 0x23, 0x37, 0xbd, 0x73, 0x35, 0xa1,
++ 0x65, 0xf2, 0xa8, 0xb3, 0x87, 0xce, 0xea, 0x9f, 0xf0, 0x18, 0x3d, 0xb1,
++ 0x23, 0xe2, 0x9c, 0x11, 0xe0, 0xd2, 0xb6, 0x97, 0xcd, 0x0e, 0x5a, 0x94,
++ 0x7e, 0x46, 0x9a, 0xfa, 0xf8, 0x12, 0x15, 0x85, 0x7f, 0x0b, 0xb9, 0x51,
++ 0xb0, 0x71, 0xc3, 0x47, 0x87, 0xe7, 0xf0, 0xf7, 0x1b, 0x13, 0x8e, 0xcc,
++ 0xfd, 0x93, 0x31, 0x8c, 0x7a, 0x38, 0x0b, 0x01, 0xeb, 0x9d, 0x34, 0xc9,
++ 0x31, 0xb9, 0x1d, 0x71, 0x4e, 0x80, 0x8c, 0xcd, 0xbb, 0x5d, 0xde, 0x8e,
++ 0x4f, 0xa1, 0x55, 0xbd, 0xe4, 0xeb, 0x68, 0xd8, 0xfc, 0x72, 0xcf, 0xf6,
++ 0x7d, 0x0a, 0x2a, 0x77, 0x5f, 0x71, 0x58, 0x75, 0x2d, 0x73, 0x69, 0xc1,
++ 0x99, 0xe7, 0xd7, 0x55, 0xde, 0x6d, 0x77, 0x40, 0xde, 0x6d, 0x88, 0xe6,
++ 0x84, 0xaf, 0x2e, 0x44, 0x39, 0x47, 0x37, 0x93, 0x9c, 0x5a, 0xd9, 0x6a,
++ 0x23, 0x4e, 0xfc, 0x29, 0xee, 0xdd, 0x39, 0xf9, 0x7c, 0x5f, 0x04, 0xcf,
++ 0x46, 0x4e, 0xb5, 0x2d, 0x62, 0xf1, 0x33, 0xa2, 0x5c, 0xa7, 0xa7, 0x1c,
++ 0xdf, 0x17, 0xd5, 0x33, 0x3b, 0xb9, 0x7c, 0x8a, 0x64, 0x0e, 0x7d, 0x27,
++ 0xcd, 0x15, 0x9b, 0xf5, 0x6b, 0x1f, 0xe2, 0x81, 0xe3, 0xf0, 0x95, 0x0a,
++ 0xbf, 0x95, 0xa1, 0xfa, 0x80, 0x3e, 0xb5, 0x57, 0xfb, 0x04, 0xf9, 0x14,
++ 0x12, 0x7e, 0x05, 0xbe, 0x76, 0xda, 0x99, 0x23, 0x77, 0xbf, 0xc2, 0xdc,
++ 0x2f, 0x3c, 0xa7, 0xd3, 0x55, 0xb6, 0xd3, 0x55, 0xb6, 0x36, 0x5e, 0x3a,
++ 0xeb, 0x54, 0x0b, 0xe5, 0x1f, 0x59, 0x2f, 0xfd, 0x56, 0xd8, 0xe6, 0xe6,
++ 0xb3, 0x06, 0x2d, 0xac, 0xf7, 0xf2, 0x27, 0xc6, 0x1f, 0x94, 0xdb, 0xcb,
++ 0xff, 0xdd, 0x9c, 0xa2, 0x5f, 0xc4, 0x02, 0xb6, 0xce, 0x07, 0x83, 0xf1,
++ 0x1f, 0xbc, 0x6e, 0x13, 0x01, 0xeb, 0xb6, 0xf9, 0xbe, 0x22, 0xf7, 0x93,
++ 0xe4, 0x95, 0x8a, 0x23, 0xaf, 0x36, 0x69, 0xd0, 0x27, 0xa7, 0x82, 0xd6,
++ 0x29, 0xfa, 0x78, 0xca, 0xe9, 0xe3, 0x9b, 0xa2, 0x3f, 0xe3, 0x54, 0xa8,
++ 0xe6, 0x0d, 0x1f, 0xe1, 0xeb, 0x98, 0xb2, 0xd1, 0x35, 0x90, 0xab, 0xdf,
++ 0x6c, 0x43, 0xc6, 0x04, 0x71, 0xb2, 0x03, 0x01, 0xfa, 0x80, 0xee, 0xd2,
++ 0x07, 0xe2, 0x55, 0x7d, 0x60, 0x45, 0xe8, 0x09, 0xbb, 0x1c, 0x1d, 0x34,
++ 0xd8, 0x16, 0x97, 0xcb, 0xe3, 0xcc, 0x1b, 0xd8, 0xf8, 0xa4, 0x1d, 0x7d,
++ 0xda, 0xaa, 0x9e, 0x99, 0xc3, 0xba, 0x65, 0x8d, 0x4b, 0xfb, 0xe5, 0x09,
++ 0xce, 0xac, 0xa8, 0xcc, 0x3e, 0x30, 0xa3, 0xa4, 0xa5, 0x93, 0xf1, 0xa9,
++ 0x50, 0x84, 0x16, 0xac, 0x28, 0x15, 0xac, 0x14, 0x73, 0x70, 0xf0, 0xe3,
++ 0xd0, 0x80, 0x46, 0x11, 0x96, 0x35, 0x11, 0x2a, 0x95, 0x94, 0x4e, 0x76,
++ 0x86, 0xc8, 0x2c, 0xc6, 0xa4, 0x0d, 0x9b, 0x71, 0x9a, 0x1f, 0x33, 0xe6,
++ 0x49, 0x43, 0xcc, 0x8b, 0x93, 0xa3, 0x0e, 0x0c, 0x8a, 0x38, 0x4b, 0xfd,
++ 0xe5, 0x91, 0x28, 0xb5, 0xa7, 0xa5, 0xcd, 0x68, 0x86, 0xdb, 0xf8, 0xc2,
++ 0x8a, 0xd1, 0x95, 0x7c, 0xd2, 0x38, 0xc1, 0xed, 0x64, 0xac, 0x64, 0x62,
++ 0x92, 0x9f, 0x5d, 0x2c, 0x45, 0x28, 0x67, 0x45, 0xa8, 0x50, 0x4a, 0x19,
++ 0x43, 0x6d, 0xa2, 0xcd, 0x18, 0xda, 0x7c, 0x49, 0x1f, 0x33, 0x4e, 0x92,
++ 0xbb, 0xcd, 0xaf, 0x9c, 0x36, 0xbd, 0x6d, 0xfd, 0x61, 0xe3, 0xfe, 0x44,
++ 0xa8, 0x32, 0x7b, 0x9f, 0xf1, 0x92, 0x5b, 0x9d, 0x60, 0xd9, 0x14, 0x13,
++ 0x67, 0xdb, 0x68, 0xe9, 0x34, 0xcb, 0x1d, 0x9c, 0x6d, 0x61, 0xd0, 0x62,
++ 0x39, 0x4e, 0xef, 0x57, 0xed, 0x07, 0x12, 0x43, 0x39, 0x91, 0x43, 0x84,
++ 0x33, 0x17, 0x2a, 0xb3, 0xbf, 0x9b, 0x5e, 0x7f, 0x3f, 0xeb, 0x5b, 0x1f,
++ 0xc5, 0x28, 0x72, 0x15, 0x71, 0xdd, 0x36, 0x5d, 0x1b, 0x4f, 0x5e, 0xd9,
++ 0x14, 0x79, 0x68, 0x09, 0x5a, 0x33, 0xa5, 0x3c, 0xcd, 0x71, 0xf9, 0x15,
++ 0x94, 0x5b, 0x4b, 0xd0, 0x3d, 0x91, 0x8f, 0xd6, 0x4e, 0x77, 0xf4, 0x18,
++ 0x85, 0x6e, 0x9a, 0xc6, 0xbc, 0xf0, 0x0b, 0x57, 0x66, 0x87, 0x86, 0x0d,
++ 0xd2, 0xae, 0xa2, 0x1e, 0xff, 0xbf, 0x89, 0xfb, 0x28, 0x61, 0x7e, 0x66,
++ 0xac, 0x31, 0x5e, 0x49, 0xc3, 0xf1, 0x12, 0x64, 0xf3, 0x41, 0x89, 0xa5,
++ 0x39, 0x23, 0x42, 0xd0, 0x5f, 0x61, 0x7b, 0xeb, 0x35, 0x27, 0x7b, 0xa4,
++ 0xfe, 0xe4, 0x3b, 0x9b, 0x43, 0x9f, 0x19, 0x71, 0x9f, 0xcf, 0x51, 0x7b,
++ 0x66, 0xc6, 0x92, 0xef, 0xb9, 0x52, 0xee, 0xa5, 0x25, 0x6e, 0x7b, 0x64,
++ 0xf8, 0x8c, 0x73, 0xa6, 0x0f, 0xff, 0xd9, 0x8b, 0x7b, 0x85, 0xb7, 0x7d,
++ 0x7d, 0x14, 0xc5, 0x3d, 0x0d, 0xe8, 0x3c, 0xc7, 0xb0, 0xe9, 0x87, 0xc5,
++ 0xb8, 0xa7, 0xe2, 0x98, 0xcb, 0xb9, 0xb8, 0x3a, 0x97, 0x08, 0x65, 0xba,
++ 0xe9, 0x91, 0xd5, 0x45, 0x3f, 0x8b, 0xf3, 0x47, 0xf8, 0xba, 0x84, 0x9c,
++ 0xa3, 0x36, 0xca, 0x64, 0xbb, 0x69, 0xb3, 0x14, 0x66, 0x71, 0x05, 0xec,
++ 0x44, 0xb9, 0x4c, 0x81, 0xa6, 0xd6, 0x5f, 0xeb, 0x83, 0x1f, 0x66, 0x52,
++ 0xab, 0x61, 0xe9, 0x51, 0x00, 0x96, 0x7e, 0xa9, 0xc3, 0xd2, 0xd1, 0xbe,
++ 0xe6, 0x58, 0xea, 0x77, 0x62, 0xd6, 0xa3, 0x14, 0x71, 0x70, 0xf4, 0x39,
++ 0xe3, 0xe8, 0x3d, 0xc6, 0xd1, 0xf1, 0x06, 0x38, 0xd2, 0x3c, 0x38, 0x3a,
++ 0x51, 0x87, 0xa3, 0x6c, 0x5f, 0x33, 0x1c, 0x1d, 0x0f, 0xa1, 0xff, 0xcd,
++ 0xd6, 0x32, 0xfa, 0xb0, 0x9f, 0x39, 0xbd, 0x49, 0xa5, 0xd5, 0xe4, 0xf8,
++ 0x24, 0x55, 0x90, 0x73, 0x92, 0x58, 0xa2, 0xb4, 0xe0, 0x76, 0x05, 0x81,
++ 0xbf, 0x2c, 0x8f, 0xc9, 0xae, 0x06, 0xe7, 0xaa, 0x24, 0x9c, 0x79, 0x93,
++ 0x73, 0x99, 0xc9, 0x57, 0x66, 0x1f, 0x32, 0x36, 0xee, 0x6d, 0xe8, 0x3a,
++ 0x7e, 0x0b, 0xb1, 0x8c, 0xbc, 0xbb, 0x81, 0x73, 0x5b, 0xe2, 0x74, 0xdf,
++ 0x1a, 0xa0, 0x7b, 0xd6, 0x7e, 0xba, 0x6b, 0x0d, 0xd2, 0x03, 0x0b, 0x6d,
++ 0x60, 0x0e, 0xf8, 0x5e, 0xcc, 0x81, 0x46, 0x33, 0x31, 0x2e, 0x53, 0xda,
++ 0x4f, 0x95, 0x92, 0xc2, 0x35, 0xb0, 0x03, 0x0c, 0x35, 0xc6, 0x4e, 0xa6,
++ 0x0e, 0x3b, 0xb2, 0x0e, 0x30, 0xb3, 0xe4, 0xb7, 0xad, 0xed, 0x32, 0xf8,
++ 0x5d, 0x0d, 0xc6, 0x56, 0x58, 0xc4, 0x91, 0x24, 0x47, 0x67, 0x42, 0x90,
++ 0x59, 0xb7, 0x18, 0x53, 0x3c, 0x17, 0x3c, 0x7e, 0xda, 0xf5, 0x41, 0x96,
++ 0x39, 0x4f, 0x09, 0x1b, 0xf4, 0x94, 0xa9, 0xc7, 0x33, 0x64, 0x5f, 0xd6,
++ 0xcc, 0x31, 0x91, 0xeb, 0xb6, 0x54, 0xf6, 0x9e, 0x31, 0x91, 0xe1, 0xb1,
++ 0x57, 0x78, 0xf4, 0xca, 0xa1, 0x76, 0xaa, 0x38, 0x31, 0x4c, 0x85, 0x55,
++ 0xdb, 0x7e, 0xc8, 0xfc, 0x7f, 0xcd, 0x84, 0xcc, 0xfe, 0xdb, 0xae, 0xc4,
++ 0x74, 0x5a, 0x36, 0x55, 0xdf, 0xee, 0x08, 0x7c, 0x31, 0x47, 0xa4, 0x77,
++ 0x37, 0xaa, 0xaf, 0xc4, 0xbf, 0xe3, 0xbb, 0xbf, 0x04, 0x97, 0x59, 0xab,
++ 0x96, 0x85, 0xed, 0xf8, 0xd2, 0xd8, 0xc2, 0x2a, 0xce, 0x7e, 0x7b, 0xfc,
++ 0xea, 0xf9, 0xd5, 0x5c, 0x1f, 0x4b, 0xd8, 0x94, 0x4e, 0x76, 0x68, 0x79,
++ 0x3c, 0xf7, 0x5c, 0x98, 0x86, 0x19, 0x97, 0x38, 0x83, 0x6b, 0x6c, 0x34,
++ 0x2c, 0xce, 0x38, 0xd9, 0xcd, 0x78, 0xc8, 0x0a, 0x3b, 0xfd, 0xd4, 0x91,
++ 0x09, 0x9a, 0x2c, 0xa7, 0xf9, 0x53, 0x3f, 0x7e, 0xb5, 0xb9, 0xe3, 0xe1,
++ 0x48, 0xe3, 0x37, 0x37, 0xff, 0xa8, 0xd5, 0x9d, 0xe6, 0xba, 0x33, 0x5b,
++ 0xd6, 0x55, 0xe7, 0x12, 0xfd, 0x03, 0x69, 0xae, 0x1b, 0xa3, 0xbc, 0x57,
++ 0x00, 0x00, 0x00 };
++
++static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_COM_b06FwRodata[(0x58/4) + 1] = {
++ 0x08002428, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c,
++ 0x08002380, 0x0800245c, 0x080023e4, 0x0800245c, 0x0800231c, 0x0800245c,
++ 0x0800245c, 0x0800245c, 0x08002328, 0x00000000, 0x08003240, 0x08003270,
++ 0x080032a0, 0x080032d0, 0x08003300, 0x00000000, 0x00000000 };
++static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
++static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
++
++static int bnx2_RXP_b06FwReleaseMajor = 0x1;
++static int bnx2_RXP_b06FwReleaseMinor = 0x0;
++static int bnx2_RXP_b06FwReleaseFix = 0x0;
++static u32 bnx2_RXP_b06FwStartAddr = 0x08003184;
++static u32 bnx2_RXP_b06FwTextAddr = 0x08000000;
++static int bnx2_RXP_b06FwTextLen = 0x588c;
++static u32 bnx2_RXP_b06FwDataAddr = 0x080058e0;
++static int bnx2_RXP_b06FwDataLen = 0x0;
++static u32 bnx2_RXP_b06FwRodataAddr = 0x08005890;
++static int bnx2_RXP_b06FwRodataLen = 0x28;
++static u32 bnx2_RXP_b06FwBssAddr = 0x08005900;
++static int bnx2_RXP_b06FwBssLen = 0x13a4;
++static u32 bnx2_RXP_b06FwSbssAddr = 0x080058e0;
++static int bnx2_RXP_b06FwSbssLen = 0x1c;
++static u8 bnx2_RXP_b06FwText[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x07, 0x87, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x5d, 0x6c,
++ 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x43, 0x71, 0x49, 0x91, 0xd4, 0x70, 0xb9,
++ 0x62, 0x57, 0x12, 0x65, 0xed, 0x8a, 0x43, 0x71, 0x6d, 0x31, 0xce, 0x50,
++ 0x58, 0xdb, 0x82, 0xb1, 0x48, 0xc7, 0xb3, 0xa4, 0xc8, 0x24, 0x02, 0x42,
++ 0x1b, 0x42, 0xab, 0xa4, 0xa9, 0xc1, 0x90, 0x72, 0x91, 0x22, 0x2c, 0xa0,
++ 0x1a, 0x79, 0xf0, 0x43, 0x10, 0x2f, 0x56, 0x3f, 0xa6, 0xd1, 0x8d, 0x96,
++ 0xb6, 0x1c, 0x53, 0x08, 0x82, 0x82, 0xe5, 0x52, 0x52, 0x0b, 0x2c, 0xb4,
++ 0x96, 0xed, 0x36, 0x7e, 0xa8, 0x23, 0x9a, 0x92, 0x8d, 0xa6, 0x68, 0x81,
++ 0x22, 0xad, 0xd1, 0xf4, 0x4d, 0x95, 0x9a, 0x4a, 0x75, 0x5f, 0xd4, 0xa2,
++ 0x48, 0xda, 0x46, 0xcd, 0xf4, 0xfb, 0xee, 0xcc, 0x88, 0xd4, 0x9a, 0xb2,
++ 0x2c, 0x3b, 0x0d, 0x62, 0x74, 0x0e, 0x30, 0xd8, 0xb9, 0x7f, 0xe7, 0xef,
++ 0x9e, 0x73, 0xee, 0x39, 0x77, 0x28, 0x7d, 0xa5, 0x43, 0xda, 0x25, 0x84,
++ 0x4e, 0x3c, 0x99, 0xc3, 0xcf, 0x3c, 0xfd, 0xe0, 0xc3, 0x0f, 0xee, 0xc1,
++ 0xeb, 0xb0, 0xa1, 0x6d, 0xd0, 0xa3, 0xfe, 0x18, 0x62, 0x88, 0x21, 0x86,
++ 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62,
++ 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21,
++ 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18,
++ 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0x18, 0x62, 0x88,
++ 0x21, 0x86, 0x18, 0x62, 0x88, 0x21, 0x86, 0xff, 0xef, 0x60, 0x88, 0x58,
++ 0xfc, 0xed, 0x0c, 0x1f, 0x49, 0xe8, 0x85, 0xcb, 0x07, 0x3d, 0x5b, 0x12,
++ 0x46, 0x61, 0x69, 0x66, 0xda, 0x16, 0x71, 0xeb, 0xbb, 0x33, 0x45, 0xf9,
++ 0x1f, 0xbf, 0x94, 0x32, 0x85, 0xfd, 0xdb, 0x0b, 0x37, 0x9f, 0x7d, 0xf3,
++ 0x91, 0xec, 0x8d, 0x05, 0x43, 0x12, 0x56, 0xe1, 0xe8, 0xb0, 0xb5, 0x4b,
++ 0x12, 0x7d, 0x58, 0xf3, 0xdd, 0xc1, 0xcf, 0x59, 0xd2, 0x15, 0xe1, 0xba,
++ 0xee, 0xbf, 0x39, 0x68, 0xc9, 0x2b, 0x8d, 0x94, 0x5c, 0x68, 0x6c, 0xdf,
++ 0x24, 0x5d, 0xd9, 0x52, 0x09, 0xfd, 0x6e, 0x8a, 0xe3, 0x96, 0x94, 0xab,
++ 0x2d, 0xe2, 0x2a, 0xba, 0x7d, 0x5a, 0x71, 0xfe, 0x3e, 0xcd, 0x9b, 0x7f,
++ 0x9e, 0xff, 0x1e, 0x24, 0xa5, 0xcb, 0x7d, 0x68, 0xf7, 0xa1, 0xcd, 0xf7,
++ 0x81, 0xf4, 0x94, 0x98, 0x72, 0xa4, 0x91, 0x90, 0xa3, 0xd5, 0x8c, 0xe8,
++ 0x05, 0x71, 0xbd, 0xbc, 0x9d, 0x2e, 0xa3, 0x6f, 0xea, 0x00, 0xdb, 0x29,
++ 0xe0, 0xf9, 0x0e, 0xd7, 0x59, 0x5e, 0x5e, 0x4a, 0xb7, 0xc6, 0x14, 0x0d,
++ 0x8e, 0xb1, 0x0f, 0xbf, 0x58, 0x5f, 0xae, 0x76, 0x00, 0x6f, 0xd6, 0x71,
++ 0x41, 0xdc, 0x73, 0x2c, 0xd0, 0xf6, 0xfd, 0xdf, 0x75, 0x32, 0xb2, 0xe2,
++ 0x74, 0x81, 0xa7, 0x16, 0x69, 0xb5, 0xc5, 0xd2, 0x0b, 0xb6, 0xb5, 0x22,
++ 0x6d, 0x1c, 0xeb, 0x34, 0x0a, 0xbe, 0x3f, 0x9d, 0x97, 0xae, 0xa0, 0x6f,
++ 0xb7, 0xe2, 0x63, 0x72, 0x42, 0xc3, 0xbc, 0x57, 0x49, 0x0f, 0x3a, 0xe2,
++ 0x3b, 0x7f, 0xf3, 0x52, 0xac, 0x6c, 0x97, 0xc9, 0x54, 0xf6, 0xa0, 0x1b,
++ 0xd0, 0x74, 0x3d, 0x67, 0x2b, 0x70, 0x6a, 0xe0, 0x4f, 0xdb, 0x81, 0xf5,
++ 0xee, 0x0a, 0x68, 0x1a, 0x85, 0xcd, 0x62, 0x6c, 0x66, 0x9f, 0xe8, 0x3b,
++ 0x87, 0x93, 0xe1, 0x78, 0x97, 0x36, 0x32, 0x6f, 0x88, 0x6e, 0xff, 0x81,
++ 0xe6, 0xd5, 0x7a, 0xe5, 0xd8, 0xbc, 0x8e, 0x77, 0x5d, 0xae, 0xe6, 0x4b,
++ 0x9a, 0xdb, 0xa8, 0x68, 0xde, 0xd9, 0x59, 0xad, 0x78, 0xd6, 0x94, 0xa3,
++ 0xb6, 0x7f, 0xe1, 0xb4, 0x73, 0x42, 0x1b, 0x39, 0x7b, 0x46, 0x1b, 0x3d,
++ 0xfb, 0x86, 0x36, 0xde, 0xd8, 0xb2, 0x49, 0xda, 0xb3, 0xd0, 0x1e, 0x71,
++ 0x90, 0xbf, 0x4f, 0x87, 0xba, 0xec, 0xa2, 0xde, 0x4a, 0xe4, 0x7d, 0x9f,
++ 0xf3, 0x86, 0xe6, 0x55, 0x6d, 0x8b, 0xfb, 0xe6, 0xa6, 0x22, 0x1a, 0xed,
++ 0x72, 0x74, 0xde, 0x94, 0x63, 0xd5, 0x94, 0x3c, 0x57, 0x2d, 0x29, 0x5a,
++ 0x86, 0x5d, 0xd2, 0xbc, 0x06, 0xc7, 0x2b, 0xa0, 0x75, 0x42, 0xdb, 0x07,
++ 0x9a, 0xde, 0x59, 0x29, 0x5d, 0x71, 0xe6, 0x40, 0xaf, 0x03, 0x78, 0xff,
++ 0x58, 0x1b, 0x6d, 0xf4, 0x6a, 0xde, 0xc9, 0x9b, 0xe2, 0x39, 0x59, 0xeb,
++ 0x4b, 0x62, 0xba, 0xb0, 0x01, 0xc8, 0x0c, 0xfd, 0x38, 0xd0, 0x49, 0xca,
++ 0xf7, 0xf5, 0x82, 0xff, 0x2c, 0x74, 0x6f, 0x5d, 0xa1, 0xfc, 0x8d, 0x5e,
++ 0x29, 0xcf, 0x53, 0xd7, 0xa6, 0x36, 0x52, 0xf5, 0x2f, 0x78, 0x8e, 0xf4,
++ 0x19, 0xe2, 0xfb, 0x47, 0x9d, 0x81, 0xf4, 0x21, 0x39, 0x03, 0xdc, 0x75,
++ 0xad, 0xd8, 0xa0, 0xae, 0xc1, 0xdf, 0x2d, 0x39, 0x02, 0xbd, 0x15, 0x9d,
++ 0x5e, 0x99, 0xb4, 0xb2, 0x2e, 0xf6, 0x68, 0x53, 0x20, 0x57, 0x32, 0xb4,
++ 0x17, 0xd2, 0xe7, 0xde, 0x67, 0xd3, 0x9e, 0xa1, 0xcb, 0x53, 0x2f, 0x3d,
++ 0xdf, 0xb3, 0x38, 0xb4, 0x91, 0x32, 0x43, 0xff, 0xf2, 0x45, 0xcf, 0xf6,
++ 0xb6, 0xb4, 0x48, 0x29, 0x6d, 0x48, 0x16, 0xfb, 0xb4, 0x43, 0x4e, 0x3b,
++ 0x22, 0x87, 0x2a, 0xd0, 0x8d, 0x6d, 0x5a, 0x8b, 0x62, 0x67, 0xca, 0x32,
++ 0x50, 0x32, 0x75, 0x74, 0x26, 0x49, 0x97, 0x3a, 0xd2, 0xe5, 0x7a, 0x9e,
++ 0x7a, 0xa2, 0x3d, 0x7f, 0x28, 0x5d, 0x69, 0xab, 0xba, 0x5a, 0xd5, 0xd3,
++ 0xf8, 0x2f, 0x5d, 0x4f, 0xd4, 0xc9, 0x72, 0x28, 0xb7, 0x03, 0xdc, 0x8f,
++ 0x40, 0x5f, 0xe2, 0xea, 0xc3, 0x0f, 0xb1, 0x6f, 0x93, 0x51, 0xb0, 0xd3,
++ 0x17, 0x61, 0x14, 0x7a, 0x61, 0x37, 0x64, 0x19, 0xa6, 0xee, 0xe0, 0xc3,
++ 0x1f, 0x49, 0x5e, 0xf9, 0xd5, 0x90, 0x97, 0xfc, 0xdb, 0x32, 0x55, 0x49,
++ 0x80, 0x06, 0x65, 0xd4, 0xe5, 0xbd, 0x7c, 0x64, 0x1b, 0x7b, 0x20, 0x5f,
++ 0x5e, 0xa6, 0xbe, 0x45, 0x7f, 0xa2, 0xfd, 0xf3, 0x9d, 0xb2, 0xfe, 0xcc,
++ 0xbf, 0xee, 0x7c, 0x92, 0xf6, 0x96, 0x7c, 0x27, 0xe4, 0x78, 0x35, 0xc9,
++ 0x3d, 0xd4, 0x56, 0x54, 0x6c, 0x8a, 0x64, 0x14, 0xdd, 0x28, 0x74, 0x48,
++ 0x51, 0xed, 0xf7, 0x5e, 0xd0, 0x43, 0x2c, 0xa8, 0xf2, 0xbd, 0xa0, 0x64,
++ 0x9b, 0xb6, 0xed, 0xcc, 0x11, 0xc9, 0xc2, 0xbe, 0x45, 0x8e, 0xcc, 0x99,
++ 0x32, 0x6d, 0xff, 0x63, 0xa7, 0xb4, 0x2f, 0xdf, 0x6f, 0xa8, 0xb8, 0xae,
++ 0xf7, 0x6e, 0x90, 0x4d, 0xe0, 0x77, 0xf9, 0x7e, 0x5d, 0xe4, 0xa6, 0x59,
++ 0xc8, 0x5a, 0x23, 0x08, 0xf6, 0x46, 0x81, 0xb1, 0x4c, 0x43, 0x2c, 0x93,
++ 0x44, 0x8b, 0x4d, 0x7d, 0xf9, 0xfe, 0xf8, 0xf0, 0xdd, 0xf5, 0x75, 0x64,
++ 0x9e, 0xb4, 0xa9, 0x2f, 0xc6, 0xa8, 0x12, 0xf4, 0xc1, 0xf8, 0x74, 0xbb,
++ 0xae, 0x8a, 0xa1, 0xae, 0x46, 0xfe, 0xef, 0xed, 0xc2, 0xf5, 0xaa, 0xa2,
++ 0x79, 0xce, 0xbb, 0xa1, 0x2f, 0xd8, 0x32, 0x02, 0x7f, 0x37, 0xec, 0x4f,
++ 0xcb, 0x91, 0x54, 0x76, 0xc2, 0x95, 0xc0, 0xe6, 0xaf, 0xad, 0xb1, 0xf9,
++ 0xd1, 0xbb, 0xc8, 0x75, 0x3c, 0x94, 0xcb, 0x0d, 0xe5, 0x1a, 0x85, 0x5c,
++ 0x63, 0x90, 0x6b, 0xe5, 0x23, 0xc8, 0xb5, 0xf2, 0x91, 0xe5, 0xd2, 0xa4,
++ 0xec, 0x3c, 0x08, 0x5a, 0xa6, 0xfc, 0xab, 0x13, 0xd8, 0xf2, 0xbf, 0x38,
++ 0x9f, 0x14, 0x19, 0x7c, 0x7f, 0x70, 0xd8, 0x16, 0xef, 0x5b, 0xe0, 0xd5,
++ 0x71, 0x40, 0x8b, 0xef, 0xef, 0x97, 0xe1, 0x6e, 0xfe, 0x38, 0x8b, 0x7d,
++ 0x5d, 0xcf, 0x1f, 0x29, 0x87, 0x3e, 0x7c, 0xef, 0xfe, 0xa8, 0x6b, 0x1f,
++ 0x55, 0x0e, 0xc6, 0x9c, 0x4f, 0x35, 0x9d, 0xab, 0x1f, 0x56, 0x86, 0xf5,
++ 0x63, 0xca, 0x2f, 0x4f, 0x86, 0xc7, 0x64, 0x72, 0x33, 0xed, 0xa9, 0xa4,
++ 0x8d, 0x0c, 0x92, 0xef, 0xb5, 0xfc, 0x4a, 0x26, 0xe0, 0x0d, 0x39, 0xd1,
++ 0xd2, 0x46, 0x39, 0xb2, 0x60, 0x49, 0x69, 0xe9, 0x4e, 0x71, 0x57, 0x03,
++ 0x6f, 0xb4, 0x47, 0xf6, 0x7d, 0xd2, 0x7c, 0x2a, 0xc8, 0x2b, 0x2e, 0x54,
++ 0x91, 0x83, 0x56, 0x13, 0x72, 0xd9, 0x48, 0xcb, 0x9b, 0x83, 0x87, 0xe5,
++ 0xf3, 0xd5, 0x24, 0xe8, 0x31, 0x9f, 0x2c, 0xe7, 0x10, 0x17, 0xb5, 0xb2,
++ 0x63, 0x08, 0x79, 0xaf, 0xd9, 0x9c, 0x13, 0xc4, 0x96, 0x72, 0x10, 0x83,
++ 0x5d, 0x6f, 0x50, 0xe5, 0x14, 0x90, 0x4f, 0x64, 0x0c, 0xb1, 0xb7, 0x66,
++ 0xb3, 0xcd, 0xfe, 0xa0, 0xef, 0xb3, 0x95, 0x5e, 0xad, 0xc8, 0xbc, 0x64,
++ 0xf0, 0xa6, 0x4c, 0x3b, 0x41, 0xdf, 0xe7, 0x2a, 0xa3, 0x9b, 0x98, 0x1f,
++ 0x1a, 0x05, 0xc9, 0x94, 0x9d, 0xf7, 0x7c, 0xd7, 0xba, 0x7d, 0xcd, 0xfa,
++ 0x78, 0xb2, 0x13, 0x81, 0xce, 0x45, 0xfb, 0xaa, 0xad, 0xf7, 0xb6, 0x4a,
++ 0x09, 0x27, 0x5d, 0xd6, 0x1a, 0x47, 0xe7, 0xbe, 0x4a, 0x79, 0x5b, 0xab,
++ 0xdc, 0x34, 0x80, 0x3f, 0x6d, 0x68, 0x62, 0x1e, 0xaa, 0x94, 0xbb, 0xd9,
++ 0xa6, 0xbe, 0x74, 0x4d, 0x12, 0xa3, 0x15, 0x5f, 0xae, 0x3a, 0x41, 0xee,
++ 0x63, 0x68, 0x7a, 0x6f, 0x5b, 0xb8, 0x56, 0xd7, 0x76, 0x39, 0x97, 0x44,
++ 0x3a, 0x0e, 0x55, 0xc4, 0x2a, 0x56, 0x76, 0x39, 0x6f, 0x4b, 0xb9, 0xa7,
++ 0x6d, 0x75, 0x5d, 0x8a, 0xeb, 0x76, 0x0e, 0xaf, 0x9d, 0xbb, 0xcb, 0xb9,
++ 0x28, 0xe5, 0x2d, 0x6d, 0xab, 0xb4, 0xd2, 0x58, 0xdb, 0x17, 0xac, 0xe5,
++ 0xf8, 0x66, 0x71, 0xbb, 0x39, 0x47, 0xef, 0x6d, 0xbf, 0x45, 0x43, 0x32,
++ 0xc5, 0x4a, 0xb9, 0xa7, 0x7d, 0x15, 0xaf, 0x4d, 0xbc, 0xde, 0x1a, 0xbc,
++ 0xc4, 0xd9, 0xbe, 0x8a, 0x33, 0x07, 0x9c, 0x43, 0xab, 0x38, 0x39, 0x7e,
++ 0x58, 0x8a, 0x38, 0xd3, 0x5a, 0x0a, 0x32, 0xbc, 0x54, 0xc9, 0x48, 0x79,
++ 0x28, 0x01, 0xdd, 0xf7, 0x1f, 0xfc, 0x9a, 0xaa, 0x43, 0xcc, 0x61, 0x0f,
++ 0xba, 0x32, 0x55, 0x5e, 0x87, 0xd8, 0x08, 0xdb, 0xf8, 0x5a, 0x5d, 0x86,
++ 0x17, 0xeb, 0xa6, 0x1c, 0x6f, 0x70, 0xbf, 0x98, 0xe3, 0x05, 0x75, 0xc6,
++ 0x85, 0x46, 0x4e, 0xdb, 0x87, 0xbd, 0x66, 0x9d, 0xb0, 0xaf, 0x61, 0x6a,
++ 0xa3, 0x3c, 0x1f, 0x80, 0x97, 0x76, 0x7e, 0xac, 0x41, 0xdb, 0x79, 0x03,
++ 0xb6, 0x41, 0xce, 0xa3, 0x9c, 0xbd, 0x95, 0xb9, 0x53, 0x66, 0xd1, 0x51,
++ 0x75, 0x88, 0x56, 0xcb, 0x77, 0x20, 0x07, 0x4d, 0xa0, 0xd6, 0x80, 0xcd,
++ 0xdb, 0x78, 0x6f, 0x70, 0xde, 0x32, 0xe6, 0x6d, 0xe0, 0x3c, 0xec, 0xcd,
++ 0x25, 0xe5, 0x0f, 0xa6, 0xcd, 0xf1, 0x77, 0xb1, 0xc7, 0x68, 0xd7, 0x59,
++ 0x57, 0x58, 0x02, 0x5f, 0xc1, 0x3e, 0xa2, 0x6e, 0x48, 0xed, 0x60, 0x7e,
++ 0x8f, 0xb9, 0x19, 0xcc, 0xcd, 0x66, 0x18, 0xcf, 0x3d, 0xfb, 0x99, 0x0e,
++ 0xe9, 0x42, 0xbb, 0xce, 0x35, 0xd9, 0x0c, 0x72, 0x5b, 0xdf, 0xcb, 0xb7,
++ 0xc9, 0x4a, 0xca, 0xbf, 0x60, 0xd8, 0xd1, 0xdc, 0x08, 0x6f, 0xf3, 0x5c,
++ 0xe6, 0xc5, 0xc4, 0xbd, 0x21, 0xcc, 0x83, 0xc7, 0xc5, 0x6d, 0xfc, 0x49,
++ 0xb7, 0x74, 0xb9, 0xf8, 0x8d, 0xe6, 0x4c, 0x6f, 0x0e, 0x6a, 0x2e, 0xbe,
++ 0xb7, 0x50, 0x3e, 0x17, 0xe7, 0xa1, 0x56, 0xac, 0x66, 0x26, 0x59, 0x1f,
++ 0x15, 0xeb, 0x6c, 0xef, 0x85, 0x3f, 0x04, 0x75, 0xd7, 0x85, 0x5b, 0xbe,
++ 0x70, 0x19, 0x7a, 0x4b, 0x43, 0x6f, 0x29, 0x39, 0xdf, 0x60, 0x9d, 0xe6,
++ 0x42, 0x5f, 0x19, 0xf1, 0x1a, 0xe3, 0x58, 0x2b, 0x87, 0x81, 0x03, 0x3a,
++ 0x17, 0x47, 0x2f, 0x64, 0x65, 0xca, 0xda, 0x1d, 0xf1, 0x00, 0x5c, 0x88,
++ 0x1f, 0x85, 0x36, 0xf4, 0xf1, 0x1d, 0x9a, 0x53, 0xff, 0x86, 0x7f, 0x94,
++ 0xed, 0x09, 0xbd, 0x30, 0xd6, 0xd4, 0xbf, 0x6e, 0xfc, 0xa1, 0x1c, 0x68,
++ 0x33, 0x06, 0x31, 0xfe, 0xe8, 0xa8, 0xf3, 0x18, 0x8b, 0x48, 0xd7, 0x92,
++ 0x23, 0x4b, 0x23, 0xdc, 0x37, 0x8b, 0xf1, 0xa7, 0x5c, 0xe7, 0x9e, 0x29,
++ 0x5c, 0xc0, 0x19, 0xad, 0xf1, 0xfd, 0x11, 0x87, 0x6b, 0x7c, 0x99, 0x70,
++ 0x3a, 0xc4, 0x48, 0x96, 0xb4, 0xc7, 0x07, 0x11, 0x7b, 0x1e, 0xe0, 0x3e,
++ 0x32, 0x06, 0x6d, 0x17, 0xb0, 0xea, 0xb4, 0x3c, 0x3c, 0xc8, 0x75, 0xa0,
++ 0xdd, 0x2a, 0x7a, 0x92, 0x34, 0xf3, 0x21, 0x4f, 0x43, 0xdd, 0x81, 0xbe,
++ 0x06, 0xac, 0x40, 0x7f, 0x9f, 0xe9, 0x5e, 0xd5, 0x1f, 0xd7, 0x35, 0xf3,
++ 0xcb, 0x18, 0x96, 0x90, 0x81, 0x33, 0x1b, 0x65, 0xe7, 0xa2, 0x25, 0xf6,
++ 0x99, 0x55, 0xfe, 0x76, 0x9e, 0x5b, 0xcb, 0x5f, 0xf4, 0x7f, 0x15, 0x5c,
++ 0xd0, 0xc5, 0x8e, 0xfa, 0x1e, 0x4b, 0x05, 0xb8, 0xa3, 0xf6, 0x7b, 0xe1,
++ 0x5e, 0xf1, 0xfd, 0x99, 0x70, 0x4f, 0xb0, 0x07, 0x88, 0x95, 0xe7, 0x6f,
++ 0xc5, 0xa9, 0x0c, 0xf6, 0x06, 0xb6, 0xa7, 0xe2, 0x11, 0xe3, 0x18, 0xed,
++ 0xbb, 0x63, 0xd2, 0x2c, 0xb0, 0x8e, 0xe6, 0x3e, 0xc9, 0x44, 0xb9, 0x22,
++ 0xa5, 0xad, 0x85, 0x67, 0x7d, 0xd8, 0xcf, 0xa4, 0xa5, 0x6c, 0xaf, 0x63,
++ 0xaf, 0x97, 0x37, 0xa0, 0x1b, 0x8c, 0xc1, 0x26, 0xf5, 0x42, 0x42, 0x8a,
++ 0x8d, 0x44, 0xc2, 0x3c, 0x31, 0xf0, 0x23, 0xcf, 0x48, 0x24, 0xf4, 0x13,
++ 0x81, 0x9d, 0x4d, 0xd6, 0x6f, 0x20, 0x56, 0x6a, 0x72, 0x74, 0xe8, 0x86,
++ 0xcf, 0x1a, 0xd8, 0xdb, 0x0b, 0x9b, 0x1b, 0x82, 0xcf, 0x80, 0x8f, 0x72,
++ 0xa3, 0xa3, 0x37, 0xe0, 0xed, 0x2b, 0x11, 0x8f, 0xa6, 0x8e, 0xdc, 0xd3,
++ 0xcb, 0xfb, 0xbe, 0x51, 0xd8, 0x90, 0x98, 0xce, 0x8f, 0x6f, 0xd1, 0xcf,
++ 0xed, 0xdf, 0x62, 0x9c, 0x2b, 0x6d, 0x01, 0x3e, 0xdd, 0xcb, 0xe3, 0xf7,
++ 0x9c, 0xc8, 0x44, 0x15, 0x3a, 0xdf, 0x03, 0x3d, 0x59, 0xf0, 0xc5, 0x3d,
++ 0xa6, 0xca, 0xd1, 0xf5, 0x3d, 0x2f, 0x6e, 0x0a, 0x70, 0xf0, 0xfd, 0x27,
++ 0x7e, 0x70, 0x86, 0x5e, 0x0e, 0xfb, 0x7e, 0x3f, 0xdc, 0x87, 0x5f, 0x45,
++ 0xb9, 0x78, 0x5e, 0x44, 0xb2, 0xad, 0x3d, 0x37, 0xb2, 0xe3, 0x25, 0x9c,
++ 0x33, 0xa7, 0x1d, 0xdf, 0x7f, 0x07, 0xcf, 0x35, 0xa7, 0xd9, 0x46, 0xde,
++ 0x7f, 0xf6, 0x31, 0x07, 0xf8, 0x2c, 0xce, 0xbd, 0xd1, 0xa6, 0xb3, 0xff,
++ 0x5e, 0xcf, 0xbd, 0x7b, 0x3f, 0xfb, 0xc9, 0xf3, 0x1d, 0x7d, 0xef, 0x03,
++ 0xce, 0xfe, 0x0f, 0x5c, 0x77, 0x0f, 0x3e, 0x1b, 0xd8, 0x6d, 0xb1, 0xd1,
++ 0x1c, 0x5f, 0xee, 0xd5, 0x7f, 0x7f, 0xad, 0xfb, 0x76, 0xff, 0xb5, 0xbb,
++ 0x6f, 0xf7, 0xdf, 0xcd, 0xdd, 0xbf, 0x18, 0xff, 0xcd, 0x01, 0x0f, 0x7d,
++ 0x70, 0xad, 0xff, 0xae, 0xe7, 0x93, 0xd4, 0xf7, 0xf3, 0x3d, 0xe5, 0xa1,
++ 0xce, 0x30, 0x1f, 0x52, 0xe7, 0xf5, 0x17, 0xa7, 0x6d, 0xef, 0x7e, 0x53,
++ 0x4a, 0xb9, 0x16, 0xc9, 0xe6, 0x6a, 0xb2, 0x43, 0x8e, 0x3b, 0x22, 0x4b,
++ 0xaa, 0x16, 0x31, 0x51, 0x8b, 0x0f, 0xa0, 0x3e, 0x0b, 0xf4, 0xba, 0xa4,
++ 0xf4, 0xf2, 0x02, 0x78, 0x89, 0xf0, 0x74, 0xdd, 0x05, 0x0f, 0x71, 0x10,
++ 0x17, 0xf1, 0x0c, 0xe2, 0x7c, 0xb7, 0xd7, 0xc1, 0x85, 0x73, 0xea, 0x25,
++ 0xd4, 0x64, 0xb6, 0xde, 0xa3, 0x07, 0x67, 0xb2, 0x5b, 0x96, 0xdd, 0xe9,
++ 0xeb, 0xf2, 0x05, 0x9e, 0x59, 0x0a, 0xae, 0xce, 0x21, 0x56, 0x0f, 0x8d,
++ 0x85, 0x75, 0xd2, 0xdc, 0x41, 0xcf, 0x8e, 0xee, 0x49, 0x78, 0x47, 0x92,
++ 0x90, 0x92, 0x9a, 0xb5, 0x04, 0x1d, 0x68, 0x72, 0x0d, 0x67, 0xd0, 0xd5,
++ 0xb9, 0x76, 0xe0, 0x45, 0xee, 0x77, 0x20, 0xbb, 0x57, 0xb4, 0x7e, 0xab,
++ 0x55, 0x6b, 0x87, 0x2f, 0x65, 0xc4, 0x55, 0x6d, 0x9e, 0xd3, 0xa7, 0x66,
++ 0x16, 0x2b, 0xc8, 0x03, 0x6d, 0x9c, 0xaf, 0x79, 0xbc, 0xd7, 0x49, 0x43,
++ 0x93, 0x2b, 0x73, 0xba, 0xfc, 0xd3, 0x9c, 0x21, 0xff, 0x8c, 0x3a, 0xf4,
++ 0x9a, 0x7d, 0x6a, 0xe6, 0xb4, 0x2d, 0xf7, 0x81, 0xd5, 0xf0, 0x0e, 0x4f,
++ 0x76, 0x9a, 0x42, 0x5b, 0x1d, 0x48, 0xff, 0x8e, 0x20, 0xff, 0xc1, 0x9a,
++ 0x2b, 0x73, 0xa4, 0xb5, 0x76, 0x8d, 0xf4, 0x22, 0x1f, 0x83, 0x5d, 0x0f,
++ 0x30, 0x27, 0xe2, 0x7c, 0xd4, 0xab, 0x03, 0xd6, 0x3e, 0xc5, 0x5b, 0x42,
++ 0x16, 0xeb, 0x9c, 0x6f, 0x82, 0xb7, 0x2e, 0x9c, 0x31, 0x59, 0x6b, 0x52,
++ 0xfe, 0xb0, 0x5b, 0xe5, 0xaa, 0x1a, 0xfb, 0x0d, 0xb5, 0xc7, 0xef, 0xef,
++ 0xe7, 0xde, 0x1b, 0x32, 0x95, 0x62, 0x9b, 0x63, 0x59, 0xd4, 0x9c, 0xc4,
++ 0x97, 0xdd, 0xeb, 0x0a, 0x79, 0x0e, 0xde, 0xaf, 0x08, 0x65, 0xdb, 0x6d,
++ 0x5d, 0x97, 0xd7, 0x7d, 0xf7, 0x00, 0xe5, 0x89, 0x72, 0x8b, 0x39, 0x9f,
++ 0xb1, 0xd8, 0x28, 0xcc, 0xc0, 0x8e, 0xbf, 0x2a, 0xdf, 0x6f, 0x1c, 0x92,
++ 0xef, 0x35, 0x26, 0xe5, 0xcf, 0x1a, 0x5f, 0x96, 0x3f, 0x6d, 0x1c, 0x94,
++ 0xd7, 0x1b, 0x07, 0xe4, 0xb5, 0xc6, 0x84, 0xbc, 0xda, 0xd8, 0x0f, 0x1b,
++ 0x1f, 0x87, 0x8d, 0x9f, 0x9a, 0x99, 0xac, 0xf7, 0xcb, 0xd4, 0x49, 0xc4,
++ 0x20, 0xe7, 0x1b, 0xba, 0xba, 0xe3, 0xb3, 0xe9, 0xe7, 0x2d, 0x32, 0xad,
++ 0xee, 0xaf, 0x34, 0xe4, 0x89, 0x2d, 0xbc, 0x2b, 0x7c, 0xc5, 0x33, 0x2e,
++ 0x87, 0xf1, 0xe8, 0xe1, 0x94, 0xb4, 0x03, 0xbf, 0xca, 0x4b, 0x4d, 0x9e,
++ 0xdb, 0x62, 0x86, 0xf7, 0x9c, 0x87, 0x24, 0xc9, 0xfb, 0xb0, 0x9c, 0x67,
++ 0xa0, 0xde, 0x5e, 0xd7, 0x27, 0x73, 0xb4, 0x65, 0xe8, 0xc6, 0x95, 0x43,
++ 0xb0, 0x53, 0xc3, 0x7e, 0xcb, 0xa5, 0x1e, 0x16, 0x97, 0x28, 0xf7, 0x46,
++ 0x59, 0x5c, 0xa0, 0x6f, 0xff, 0x1b, 0x64, 0x6c, 0x97, 0xda, 0x82, 0x89,
++ 0xb9, 0x6e, 0x98, 0xab, 0x6c, 0xa7, 0x3d, 0x00, 0x1f, 0xf1, 0x7e, 0x10,
++ 0x4e, 0xab, 0x09, 0x27, 0xf1, 0x24, 0x54, 0x0c, 0x08, 0x70, 0x5b, 0x52,
++ 0x5b, 0x4a, 0xca, 0xc2, 0x42, 0x0f, 0x9e, 0x94, 0x2c, 0xd4, 0x6d, 0x3c,
++ 0x39, 0x3c, 0x43, 0x78, 0xd2, 0xb0, 0x53, 0xca, 0xc8, 0xd8, 0x12, 0xc9,
++ 0x88, 0x78, 0x5c, 0xed, 0x0d, 0x6b, 0x2a, 0xf2, 0xa3, 0x85, 0xfc, 0x74,
++ 0x87, 0x7d, 0x1d, 0x52, 0xab, 0x38, 0x32, 0x55, 0xfd, 0x94, 0x3e, 0xa5,
++ 0x74, 0x07, 0xfc, 0x95, 0x21, 0xb4, 0xef, 0x0f, 0xdb, 0x8f, 0xca, 0xf4,
++ 0xbc, 0xc8, 0xca, 0xcb, 0x03, 0x7a, 0x51, 0xb5, 0xf7, 0xa2, 0xad, 0xa3,
++ 0x9d, 0x0d, 0xdb, 0xcc, 0x8f, 0x0e, 0xe0, 0x71, 0xd5, 0xf3, 0xf5, 0xea,
++ 0xb8, 0x3c, 0x55, 0xed, 0x77, 0x5e, 0x87, 0xcd, 0xbd, 0x65, 0x46, 0xf7,
++ 0xd2, 0x04, 0x24, 0x79, 0xf6, 0x56, 0x75, 0xf7, 0xf1, 0x04, 0xe2, 0xad,
++ 0x9b, 0x34, 0xe5, 0x6f, 0x4f, 0x64, 0xad, 0xa7, 0xf5, 0x5c, 0x52, 0xda,
++ 0x7d, 0xff, 0x71, 0x3b, 0x3b, 0x3b, 0xa9, 0x77, 0xca, 0xdf, 0xbf, 0x98,
++ 0x91, 0x85, 0xb3, 0x5b, 0x65, 0xa1, 0x06, 0x99, 0x1a, 0xbf, 0x8e, 0x7d,
++ 0x35, 0xe5, 0xea, 0x9e, 0x47, 0xb1, 0x27, 0x8c, 0x5d, 0x49, 0xe4, 0x6c,
++ 0x1b, 0xc4, 0xec, 0x25, 0x5d, 0x49, 0x98, 0x85, 0x9c, 0x1c, 0x81, 0xdf,
++ 0x4f, 0xdb, 0xb9, 0x1e, 0x69, 0xc7, 0x7b, 0x7d, 0x04, 0x7c, 0x5b, 0x32,
++ 0xd5, 0x6b, 0xc9, 0x99, 0xc1, 0x68, 0xff, 0xb6, 0x62, 0x6e, 0x46, 0x16,
++ 0xcf, 0x66, 0xf0, 0x9b, 0x83, 0xfd, 0xec, 0x94, 0x57, 0x6a, 0xfd, 0xb2,
++ 0x54, 0xdb, 0x2a, 0x8b, 0xb5, 0xe6, 0x7d, 0xe8, 0xec, 0x09, 0xe2, 0x1d,
++ 0xf1, 0xf4, 0x5b, 0x53, 0xfa, 0x56, 0x71, 0xcd, 0x7e, 0xeb, 0x29, 0xfd,
++ 0x1f, 0xe4, 0x31, 0x33, 0xa0, 0xa9, 0x17, 0x7e, 0xa4, 0xee, 0x84, 0x26,
++ 0x79, 0xf6, 0x2a, 0xbc, 0x4f, 0x26, 0x49, 0xfb, 0xf5, 0xc6, 0x07, 0xd1,
++ 0x59, 0xcb, 0xcf, 0x9d, 0x68, 0x52, 0x06, 0xe2, 0xec, 0xbf, 0x71, 0x52,
++ 0xef, 0x95, 0xe5, 0x6d, 0x0f, 0x58, 0x4f, 0xea, 0xad, 0x88, 0x01, 0x3f,
++ 0x97, 0x9f, 0xee, 0xd9, 0x24, 0x3f, 0xfc, 0xcd, 0xec, 0xa9, 0x6f, 0x22,
++ 0xd9, 0xbf, 0xb2, 0xa7, 0x83, 0x71, 0x01, 0xef, 0xec, 0xcf, 0xde, 0x70,
++ 0x75, 0xea, 0xe1, 0x2f, 0xa0, 0x87, 0xec, 0x9c, 0xba, 0x9b, 0x56, 0x3c,
++ 0x90, 0x3e, 0xf5, 0x52, 0x06, 0x6f, 0x18, 0xab, 0xf7, 0x03, 0x57, 0x59,
++ 0xe9, 0xf9, 0x09, 0x27, 0x7b, 0x03, 0xe9, 0xb0, 0xbf, 0x68, 0xf7, 0xa7,
++ 0x77, 0xea, 0x3b, 0x64, 0x32, 0xfd, 0x80, 0xf5, 0xb4, 0x6c, 0x21, 0xce,
++ 0xd9, 0x05, 0xc1, 0xda, 0x79, 0xe2, 0xfb, 0x2b, 0xe0, 0x0b, 0x70, 0x28,
++ 0xff, 0x51, 0x38, 0x77, 0x59, 0x5f, 0xd7, 0x79, 0xc6, 0x63, 0x0c, 0x71,
++ 0xe1, 0xe2, 0x10, 0x65, 0x40, 0x82, 0x95, 0xca, 0xa6, 0x5d, 0xfd, 0xc3,
++ 0xc8, 0x47, 0xfc, 0xfd, 0x56, 0x51, 0x27, 0x0f, 0xe7, 0xc0, 0xcb, 0x4f,
++ 0xc0, 0x7f, 0x3f, 0x70, 0xa2, 0xf6, 0x48, 0x47, 0x74, 0xff, 0x4e, 0xd1,
++ 0x7d, 0xad, 0x21, 0xe6, 0x2a, 0x5d, 0xf4, 0xd5, 0x75, 0xc8, 0xdd, 0x07,
++ 0x7b, 0xb5, 0xf0, 0xcb, 0xbd, 0xe9, 0x0c, 0xf7, 0x98, 0xeb, 0x22, 0xba,
++ 0x11, 0xbf, 0x5c, 0x73, 0x27, 0x1e, 0xee, 0x75, 0x3e, 0xea, 0xd4, 0x03,
++ 0x09, 0x79, 0xf7, 0x44, 0xb4, 0x37, 0x07, 0x64, 0xba, 0x0a, 0xdd, 0xed,
++ 0xea, 0x0f, 0xfc, 0x27, 0x1d, 0xf1, 0x40, 0xde, 0xff, 0x06, 0xbc, 0x07,
++ 0xb8, 0x5b, 0x0b, 0xcd, 0xba, 0xc3, 0x58, 0x3d, 0xa0, 0x31, 0xb6, 0x0e,
++ 0x4f, 0x57, 0xf6, 0x44, 0xbe, 0x98, 0x84, 0x5f, 0xed, 0xb6, 0x9e, 0x10,
++ 0xd6, 0x63, 0xc4, 0x9b, 0x94, 0x1f, 0xbe, 0x0c, 0x1e, 0x92, 0xf4, 0x93,
++ 0x7f, 0x5f, 0xe3, 0x27, 0x1c, 0xdb, 0x2a, 0x35, 0xd4, 0xd4, 0x5e, 0xde,
++ 0x94, 0x69, 0x25, 0x03, 0xda, 0x35, 0xfa, 0x77, 0x29, 0xf4, 0xef, 0x47,
++ 0x80, 0xa3, 0x5d, 0x8c, 0x47, 0x1f, 0xc7, 0x59, 0x9d, 0xcd, 0x2c, 0xeb,
++ 0xcc, 0x03, 0x76, 0x4b, 0x51, 0xdd, 0x4f, 0xdf, 0x8b, 0xee, 0xa2, 0xd8,
++ 0x94, 0x96, 0x8b, 0x95, 0x28, 0x2e, 0xa5, 0x71, 0x9e, 0xb4, 0xcb, 0xa5,
++ 0xb9, 0x28, 0xe6, 0xb5, 0xcb, 0x12, 0xf2, 0x9a, 0x95, 0x97, 0x2c, 0x8c,
++ 0x25, 0xe5, 0xe2, 0x5c, 0x12, 0x31, 0xab, 0x47, 0x56, 0xe6, 0x7a, 0x30,
++ 0x96, 0xc2, 0xba, 0x14, 0xe6, 0xdb, 0xb2, 0x52, 0xb1, 0x81, 0x27, 0x87,
++ 0x76, 0x0e, 0xed, 0x21, 0xb9, 0xa4, 0xbe, 0x17, 0x30, 0x2f, 0x18, 0x42,
++ 0xdc, 0x62, 0x5e, 0x30, 0x82, 0x18, 0x32, 0x81, 0x27, 0x8a, 0x5d, 0xa7,
++ 0x66, 0xa6, 0x2a, 0xbc, 0x73, 0x84, 0x0e, 0xac, 0x53, 0x33, 0xd3, 0xb6,
++ 0x89, 0xba, 0xed, 0x1b, 0xda, 0x54, 0x83, 0x72, 0x41, 0xb7, 0x43, 0x1d,
++ 0xa2, 0x3f, 0x4a, 0x9b, 0xe4, 0x79, 0x67, 0x20, 0xc6, 0x77, 0x01, 0x9f,
++ 0x23, 0xfa, 0x6f, 0xd0, 0x17, 0xa0, 0xc3, 0x27, 0xba, 0xe4, 0xd2, 0xcb,
++ 0x8c, 0x35, 0xae, 0xbc, 0x7a, 0x96, 0x3a, 0x2c, 0xf6, 0xac, 0xea, 0x90,
++ 0x63, 0x0f, 0xe1, 0x8c, 0xd8, 0x0f, 0x7b, 0x32, 0x33, 0x87, 0x90, 0xcb,
++ 0x7c, 0x1b, 0xf6, 0x59, 0x66, 0xcd, 0x9d, 0x0e, 0x6a, 0x84, 0x20, 0x06,
++ 0xa0, 0xdd, 0x47, 0x5d, 0xb1, 0xdd, 0x07, 0xbb, 0xe3, 0x58, 0x9f, 0x1a,
++ 0x5b, 0x04, 0x8e, 0x60, 0x8c, 0xed, 0xcd, 0xb2, 0xa8, 0xc6, 0x0e, 0xaa,
++ 0xb1, 0xb2, 0xb2, 0x0f, 0x8e, 0x1d, 0x52, 0xb1, 0xe9, 0x7c, 0x23, 0xea,
++ 0xdf, 0x88, 0x58, 0xc2, 0x7e, 0xf6, 0xe5, 0x61, 0xeb, 0x7b, 0x71, 0xae,
++ 0x15, 0x64, 0xa9, 0x81, 0x3a, 0x30, 0xff, 0x7b, 0x98, 0xcb, 0x3d, 0xc8,
++ 0x9e, 0x2a, 0xe9, 0xe4, 0xf1, 0x20, 0xce, 0x83, 0xfd, 0x21, 0xad, 0xb6,
++ 0x90, 0xaf, 0x03, 0x61, 0xbb, 0x25, 0xa4, 0x4d, 0x3c, 0x36, 0x70, 0x1c,
++ 0xc3, 0x5a, 0x17, 0x38, 0x18, 0x63, 0x11, 0x23, 0x52, 0x29, 0xe8, 0x82,
++ 0x34, 0xdb, 0xa4, 0xac, 0xde, 0xf7, 0xc3, 0x76, 0xb9, 0x16, 0x3a, 0xb4,
++ 0xa2, 0x75, 0xa5, 0x70, 0xcf, 0x53, 0xea, 0x9c, 0xd1, 0x93, 0x9b, 0xc3,
++ 0x9c, 0x10, 0x7a, 0x45, 0x9c, 0xd5, 0x93, 0x8c, 0x37, 0xef, 0x84, 0x76,
++ 0xda, 0x8b, 0xbe, 0x87, 0x44, 0xef, 0x65, 0xdf, 0x51, 0xe0, 0x61, 0xed,
++ 0x3c, 0x0c, 0x99, 0xd9, 0xe6, 0xfa, 0x6c, 0xd3, 0xfa, 0xc4, 0x3a, 0xeb,
++ 0x3b, 0x9a, 0xfa, 0x32, 0x52, 0x9b, 0xef, 0x52, 0xf1, 0xf2, 0x7c, 0x18,
++ 0x2f, 0x17, 0x6b, 0x94, 0x05, 0x7e, 0x96, 0x7f, 0x5b, 0xe9, 0xa2, 0x76,
++ 0x36, 0xb0, 0xf5, 0xa5, 0x93, 0x3c, 0x17, 0x57, 0xe7, 0xd5, 0xd4, 0xbc,
++ 0xdf, 0x06, 0xff, 0xba, 0x1c, 0x55, 0x32, 0x70, 0x3e, 0xe6, 0xd5, 0x02,
++ 0xbf, 0x31, 0x6c, 0xce, 0xa1, 0x8f, 0x44, 0x6b, 0x38, 0xff, 0xe7, 0xa8,
++ 0x55, 0xbe, 0xac, 0xd6, 0xac, 0xfa, 0x0c, 0xf9, 0x71, 0x42, 0x9e, 0x7b,
++ 0xc0, 0x5f, 0x67, 0x28, 0x43, 0x7b, 0x28, 0x03, 0xf1, 0xfd, 0x27, 0x70,
++ 0xb7, 0x61, 0x1e, 0x79, 0xdd, 0x86, 0x3e, 0xbe, 0xff, 0x17, 0xfa, 0x76,
++ 0x23, 0xff, 0x23, 0x6f, 0x89, 0x26, 0xde, 0xfe, 0x03, 0x63, 0x3d, 0x4a,
++ 0xb7, 0x35, 0xd4, 0x26, 0x53, 0xbc, 0xef, 0x48, 0xe1, 0x1c, 0x38, 0xb9,
++ 0x4d, 0xd1, 0xad, 0x9d, 0xbd, 0x86, 0xf1, 0x5e, 0xac, 0x89, 0xda, 0xcd,
++ 0xb2, 0xe9, 0x58, 0xfb, 0x53, 0x25, 0xcf, 0x62, 0xed, 0x4e, 0xf2, 0x6f,
++ 0x5b, 0x23, 0x3b, 0xe5, 0x26, 0x4f, 0xe4, 0xa7, 0x1f, 0x4f, 0x2b, 0x72,
++ 0x21, 0xd8, 0x6d, 0xd2, 0x90, 0xd1, 0x7c, 0x9a, 0xdf, 0xf9, 0x12, 0xbc,
++ 0x17, 0x1d, 0x19, 0xe4, 0x9e, 0xa1, 0xdd, 0x60, 0x4e, 0x47, 0x7f, 0x4b,
++ 0xc8, 0x31, 0xd4, 0x24, 0xe5, 0x85, 0x8c, 0x56, 0x3c, 0x99, 0x45, 0x16,
++ 0xad, 0xbe, 0xd5, 0xc9, 0x8b, 0x4b, 0xb6, 0x7c, 0x1b, 0x7e, 0x7a, 0xb2,
++ 0x9e, 0x4d, 0x7f, 0x13, 0xf9, 0xc1, 0x91, 0x25, 0xe6, 0x13, 0x3d, 0x29,
++ 0x65, 0x9b, 0xf3, 0x9a, 0x6c, 0x60, 0x4c, 0x9b, 0x47, 0x7e, 0x6a, 0xdd,
++ 0x2d, 0x47, 0x82, 0x9f, 0x57, 0xd7, 0xc6, 0x0c, 0xca, 0xb1, 0x36, 0x66,
++ 0x10, 0x0f, 0x63, 0xc6, 0x4e, 0xec, 0x13, 0x63, 0x06, 0xf6, 0xff, 0x24,
++ 0x63, 0x86, 0x8d, 0x75, 0x8c, 0x19, 0x79, 0x59, 0xac, 0x32, 0x66, 0xec,
++ 0x45, 0x9b, 0x31, 0xa3, 0x80, 0x76, 0x10, 0x2f, 0x16, 0x55, 0xbc, 0xc8,
++ 0x5a, 0xcb, 0xc2, 0x38, 0x81, 0x3c, 0xb1, 0x8a, 0x3c, 0xb1, 0x8a, 0x3c,
++ 0xb1, 0x8a, 0x3c, 0xb1, 0x8a, 0x3c, 0x11, 0xb6, 0xfe, 0x5a, 0x15, 0x79,
++ 0x22, 0xfc, 0xe7, 0x3c, 0x72, 0x92, 0xa0, 0xa6, 0x38, 0x8c, 0x9a, 0xc2,
++ 0xd5, 0xc6, 0xaa, 0xe3, 0xda, 0xbe, 0x2a, 0x6a, 0x43, 0xf5, 0x9d, 0x58,
++ 0x1f, 0xda, 0x80, 0xba, 0xa8, 0xe6, 0x6c, 0x01, 0x5f, 0xd7, 0xe0, 0x1b,
++ 0xd4, 0xd3, 0x56, 0x99, 0xca, 0xed, 0x80, 0x7c, 0xd8, 0x7f, 0xfb, 0xfb,
++ 0xe8, 0x43, 0x3e, 0x9f, 0x63, 0x0d, 0xc2, 0x78, 0xb5, 0x0f, 0x6d, 0x1d,
++ 0x6d, 0xec, 0xe9, 0x04, 0x7c, 0xc4, 0x7e, 0x90, 0xf9, 0x62, 0x7a, 0x41,
++ 0x9e, 0xdc, 0x1c, 0xd8, 0xf4, 0x6f, 0x31, 0x27, 0x5e, 0xd3, 0xde, 0x88,
++ 0x39, 0xf0, 0x17, 0xd8, 0x97, 0x5a, 0x03, 0x5c, 0xba, 0xfd, 0xe7, 0xc4,
++ 0xd1, 0xb7, 0xe1, 0xd6, 0x1c, 0xda, 0xd5, 0xf7, 0x9a, 0xfa, 0xb2, 0x98,
++ 0xcf, 0xef, 0xe2, 0x3b, 0xf0, 0xfb, 0x16, 0x7e, 0x61, 0x77, 0xf6, 0x05,
++ 0xcc, 0xe9, 0xc3, 0xef, 0x77, 0x9a, 0xe6, 0x42, 0x0a, 0xfb, 0x2f, 0xd1,
++ 0x77, 0x31, 0xa4, 0xc1, 0x6f, 0x89, 0x5f, 0x6a, 0xe2, 0xe3, 0x07, 0xe8,
++ 0xfb, 0x6b, 0xf4, 0xf9, 0xfe, 0xdb, 0x4e, 0xd4, 0x27, 0xa5, 0x96, 0x70,
++ 0xef, 0x46, 0xd5, 0xde, 0x69, 0xca, 0xe6, 0x8f, 0x2c, 0xe9, 0xaa, 0x0e,
++ 0x7a, 0xae, 0x8e, 0xea, 0x08, 0x71, 0xbe, 0xbc, 0x10, 0xd4, 0xad, 0xc7,
++ 0x51, 0x73, 0x16, 0xab, 0xb4, 0x91, 0x1c, 0xfa, 0x6d, 0x9c, 0x69, 0x32,
++ 0x69, 0xdc, 0xaa, 0x63, 0x13, 0x89, 0xc9, 0x7a, 0x9b, 0x48, 0x37, 0x69,
++ 0x32, 0x4f, 0x22, 0x8e, 0xd9, 0x99, 0xe2, 0xc2, 0xec, 0x8c, 0x07, 0x9c,
++ 0x63, 0x75, 0xae, 0xe5, 0x3c, 0x93, 0xf7, 0x63, 0x4d, 0x74, 0x69, 0x13,
++ 0x60, 0x06, 0xf4, 0x9e, 0xab, 0x93, 0x7e, 0x40, 0xb3, 0xac, 0x68, 0xda,
++ 0xe8, 0x8f, 0xea, 0xc7, 0x1c, 0x6a, 0x5d, 0x99, 0x64, 0xed, 0x5c, 0x0c,
++ 0x69, 0xba, 0x75, 0x49, 0x24, 0x0a, 0xcd, 0xf8, 0x82, 0x8c, 0xf3, 0xb9,
++ 0xfa, 0xec, 0x8c, 0xfe, 0x42, 0x36, 0xc7, 0x3b, 0x11, 0xd7, 0x9a, 0x9d,
++ 0x69, 0x1d, 0x48, 0xc8, 0x8f, 0x91, 0xbb, 0x1d, 0x53, 0x34, 0x66, 0x67,
++ 0x8c, 0x17, 0x02, 0x5b, 0x0c, 0xe8, 0xe0, 0x3c, 0xc9, 0xb7, 0x43, 0x4e,
++ 0xd2, 0x62, 0x4d, 0x1d, 0x8c, 0x4f, 0xaa, 0x7a, 0xd1, 0x94, 0x2b, 0x15,
++ 0x45, 0x3b, 0xac, 0xdb, 0xc9, 0xc3, 0xec, 0x8c, 0xfc, 0xd1, 0x2d, 0x1e,
++ 0xd6, 0x91, 0x87, 0x78, 0x49, 0x27, 0xd0, 0x5b, 0xc0, 0x7f, 0x12, 0xf5,
++ 0x7b, 0x54, 0xab, 0xfb, 0xfe, 0x8a, 0x93, 0x43, 0x5c, 0xe0, 0x3e, 0xb6,
++ 0xa8, 0x3c, 0xd7, 0x73, 0x32, 0xbc, 0xef, 0x9b, 0xe3, 0xdf, 0x39, 0x78,
++ 0xf9, 0x01, 0xd4, 0x4d, 0xbc, 0x1b, 0xa4, 0x7f, 0xe1, 0xf7, 0x36, 0xff,
++ 0xe2, 0x7c, 0xf6, 0x93, 0xe7, 0x81, 0xf4, 0x55, 0xf0, 0xe7, 0xe5, 0xd1,
++ 0x87, 0x58, 0x51, 0x6c, 0x44, 0xb8, 0x78, 0xc7, 0xce, 0x39, 0x2a, 0xff,
++ 0x6e, 0xf2, 0xd1, 0x96, 0xf0, 0xdc, 0xa5, 0x8e, 0xc8, 0x27, 0xf9, 0xe9,
++ 0x84, 0x4d, 0x90, 0x17, 0xce, 0x8f, 0xee, 0x25, 0xd8, 0xfe, 0xb8, 0x36,
++ 0x12, 0xdd, 0xa9, 0x7d, 0x9c, 0x3d, 0x8f, 0x74, 0x76, 0x37, 0x7e, 0x88,
++ 0x83, 0xb4, 0x23, 0xbe, 0x22, 0x9e, 0x88, 0x8f, 0xfc, 0x44, 0xbc, 0x28,
++ 0x1b, 0x5d, 0x97, 0x9f, 0x60, 0x5d, 0xc0, 0x4f, 0x69, 0x21, 0x0d, 0x9d,
++ 0x90, 0xa7, 0x11, 0x6d, 0xa4, 0xba, 0xde, 0x1d, 0xc7, 0x0f, 0x5c, 0xc6,
++ 0xd5, 0xb1, 0x06, 0xef, 0xa1, 0x48, 0x97, 0x7f, 0x3b, 0xb2, 0xa4, 0x8d,
++ 0x34, 0xf8, 0x9d, 0xa9, 0xae, 0xb9, 0x8d, 0x88, 0xde, 0x5a, 0x9d, 0x46,
++ 0xbf, 0xbc, 0x2b, 0xff, 0x0c, 0xf6, 0xa9, 0x3b, 0xf8, 0xbb, 0x14, 0x55,
++ 0x47, 0xb1, 0x6f, 0xb9, 0xd5, 0x73, 0xa2, 0xbf, 0xd3, 0xd9, 0x1f, 0xe6,
++ 0x43, 0x51, 0x6d, 0x1c, 0xd5, 0x59, 0xea, 0x9e, 0x7d, 0xaf, 0xe7, 0x68,
++ 0xc8, 0x4f, 0x99, 0x33, 0x05, 0x3a, 0x08, 0xf1, 0xde, 0x91, 0xcf, 0x91,
++ 0x26, 0x3e, 0x47, 0xc1, 0xe7, 0x3e, 0xf0, 0x39, 0x76, 0x8b, 0xcf, 0x5b,
++ 0xb6, 0x97, 0x29, 0xc3, 0xf6, 0x46, 0xd6, 0xb5, 0xbd, 0x55, 0x3a, 0xab,
++ 0x73, 0x83, 0xfb, 0x9a, 0x91, 0x86, 0x2f, 0xc7, 0x9d, 0x8f, 0x53, 0x37,
++ 0xb7, 0xcb, 0x99, 0x85, 0xbb, 0xd5, 0xb7, 0x11, 0xaf, 0x2a, 0x77, 0x94,
++ 0x4b, 0xf5, 0x80, 0x9f, 0x1f, 0x2f, 0xb1, 0x3d, 0x12, 0xea, 0x8a, 0x3a,
++ 0xcb, 0x3a, 0x25, 0xb9, 0x1b, 0x2f, 0xbf, 0xf8, 0x9c, 0x76, 0xa5, 0x12,
++ 0x9d, 0x4f, 0x5a, 0x78, 0xc6, 0xae, 0xe5, 0x29, 0xfa, 0x6e, 0x32, 0x66,
++ 0x45, 0xf7, 0x67, 0x22, 0xfc, 0xfe, 0xc0, 0xef, 0x75, 0x6b, 0xbf, 0x13,
++ 0xf0, 0x7c, 0x8a, 0x78, 0xd7, 0x53, 0x3c, 0x9f, 0xc6, 0x9c, 0x66, 0x19,
++ 0x5c, 0xd8, 0xa4, 0x9e, 0xe4, 0x98, 0xe7, 0xd0, 0x2f, 0x4c, 0xd0, 0x0c,
++ 0xee, 0xdd, 0x6a, 0x4b, 0xbe, 0x5c, 0x74, 0x36, 0x06, 0xe7, 0x28, 0x64,
++ 0xba, 0x6c, 0xf1, 0xfe, 0x0a, 0x31, 0x8c, 0x67, 0x83, 0xb2, 0xb5, 0x16,
++ 0xf5, 0x5c, 0x39, 0xd0, 0x0e, 0x1d, 0xb3, 0xdd, 0xd6, 0xcb, 0xfb, 0x0a,
++ 0xca, 0xbc, 0xa0, 0xf6, 0x21, 0xd2, 0x71, 0xf4, 0x7d, 0xae, 0x55, 0x96,
++ 0xc3, 0xbb, 0xad, 0xc5, 0x8a, 0xef, 0xbf, 0x83, 0x3c, 0xfc, 0x34, 0x74,
++ 0x5f, 0xae, 0xff, 0xcc, 0x5f, 0x4e, 0xf1, 0x6f, 0xa5, 0x22, 0x9b, 0xd8,
++ 0xd1, 0xcb, 0x7b, 0x20, 0xf8, 0x96, 0x1c, 0xaf, 0x87, 0x65, 0xbf, 0x70,
++ 0x9c, 0x7d, 0xff, 0x0d, 0xbe, 0x7d, 0xff, 0xf4, 0xaa, 0x9d, 0x02, 0xfe,
++ 0x17, 0x33, 0xe1, 0x9b, 0xdd, 0x90, 0x58, 0x00, 0x00, 0x00 };
++
++static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_RXP_b06FwRodata[(0x28/4) + 1] = {
++ 0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680,
++ 0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 };
++static u32 bnx2_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 };
++static u32 bnx2_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 };
++
++static u8 bnx2_rv2p_proc1[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x5e, 0xd0, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x56, 0xcf, 0x6b,
++ 0x13, 0x51, 0x10, 0x9e, 0xec, 0x6e, 0xb2, 0xdb, 0x74, 0xbb, 0x1b, 0x2b,
++ 0xda, 0xa0, 0xb1, 0x8d, 0x51, 0x6a, 0x7f, 0xa4, 0xb4, 0x11, 0x0f, 0x82,
++ 0x42, 0x25, 0x3d, 0x04, 0x54, 0x44, 0x7a, 0x28, 0x22, 0x82, 0x36, 0x8a,
++ 0xfe, 0x1b, 0xa1, 0x3f, 0xd2, 0x4b, 0x10, 0x7a, 0xb0, 0x58, 0xf1, 0x50,
++ 0x10, 0x2a, 0x68, 0x0f, 0xc9, 0xa1, 0x20, 0x52, 0x11, 0xda, 0x8b, 0x07,
++ 0x2f, 0x42, 0x0f, 0x7a, 0x69, 0xbd, 0xa8, 0xff, 0x82, 0x08, 0x4d, 0x7c,
++ 0x6f, 0x66, 0x9e, 0xee, 0x6e, 0xb2, 0x4d, 0x15, 0xc1, 0x85, 0xf6, 0xe3,
++ 0xbd, 0x9d, 0x79, 0x33, 0xf3, 0xcd, 0x37, 0xfb, 0x62, 0x01, 0x40, 0x04,
++ 0x60, 0xcd, 0x46, 0x2c, 0x8d, 0x26, 0x04, 0x1a, 0x30, 0x7e, 0x52, 0x62,
++ 0x16, 0xde, 0xa6, 0x25, 0x4e, 0x44, 0xc6, 0xd3, 0x49, 0x81, 0x7b, 0x0d,
++ 0x28, 0xc9, 0x75, 0x4f, 0xf5, 0x55, 0xad, 0x53, 0xa0, 0x06, 0xbb, 0xa3,
++ 0x80, 0xcf, 0x47, 0x9d, 0xf0, 0x7c, 0xd6, 0x42, 0x2c, 0x31, 0xc2, 0x48,
++ 0x02, 0x61, 0x7b, 0x51, 0xae, 0xad, 0x48, 0x69, 0xc4, 0x42, 0x3f, 0xd0,
++ 0x68, 0x7f, 0x67, 0xd1, 0x15, 0xff, 0x53, 0xf0, 0x39, 0x2f, 0xd7, 0x56,
++ 0x7c, 0x0e, 0xed, 0xaa, 0xec, 0x2f, 0xfe, 0xd0, 0xfe, 0xba, 0xf0, 0x03,
++ 0x7e, 0x94, 0x5f, 0x02, 0xcf, 0x29, 0x66, 0x65, 0x5e, 0xdd, 0x22, 0xa0,
++ 0xca, 0xc7, 0x46, 0x2c, 0xf5, 0x91, 0xb5, 0x89, 0xef, 0xbf, 0x8a, 0xbc,
++ 0x55, 0xdc, 0x76, 0xf1, 0x82, 0xf9, 0x06, 0xe3, 0x26, 0x91, 0x1f, 0x28,
++ 0xf9, 0xe3, 0x00, 0xc8, 0xfd, 0x4f, 0x8d, 0x5f, 0xfb, 0x83, 0xfe, 0xf7,
++ 0xbb, 0x43, 0xf2, 0xbc, 0x28, 0xc0, 0x90, 0xb4, 0xdb, 0xe6, 0x7c, 0xc6,
++ 0xe0, 0xb4, 0x96, 0xc4, 0xf7, 0x06, 0xfa, 0x1f, 0x11, 0xe7, 0x4a, 0xec,
++ 0x61, 0x3c, 0xce, 0x78, 0x95, 0xb1, 0xc2, 0xe8, 0x32, 0x3a, 0x8c, 0x5d,
++ 0x8c, 0x36, 0xe3, 0x26, 0x63, 0x9c, 0xb1, 0x83, 0xd1, 0x62, 0xdc, 0x63,
++ 0x8c, 0x31, 0x46, 0x19, 0x1b, 0x8c, 0x46, 0x84, 0x50, 0xe3, 0xf5, 0x63,
++ 0x46, 0xe0, 0xba, 0x23, 0x81, 0xba, 0x5f, 0xb3, 0x2e, 0x24, 0x6f, 0xfc,
++ 0x7e, 0x50, 0xd9, 0x31, 0xef, 0x58, 0xf7, 0x3a, 0xdb, 0x75, 0x57, 0x57,
++ 0x02, 0xfa, 0x49, 0xef, 0xab, 0x9b, 0x54, 0x8b, 0x3e, 0xb8, 0x58, 0xcf,
++ 0x9d, 0x82, 0x8b, 0x71, 0x9c, 0x18, 0xed, 0xab, 0xb4, 0x6e, 0xb8, 0x84,
++ 0xf7, 0xe2, 0x84, 0x5f, 0x18, 0xef, 0x77, 0x12, 0x4e, 0x77, 0xc9, 0x7c,
++ 0x0e, 0x8b, 0x80, 0xea, 0x1c, 0x95, 0x4f, 0xbb, 0x3c, 0xc2, 0xe2, 0xa9,
++ 0xbc, 0xda, 0xc5, 0x25, 0x2c, 0x6a, 0xfe, 0xfa, 0x9f, 0x8c, 0x11, 0x1a,
++ 0x39, 0x22, 0x75, 0xc9, 0x16, 0x3d, 0x83, 0x46, 0x63, 0xd9, 0x36, 0xe4,
++ 0xfa, 0xdc, 0xf2, 0x7b, 0xd4, 0xfb, 0xd9, 0xa5, 0x1a, 0xe7, 0xe7, 0x2a,
++ 0x9e, 0x69, 0x0e, 0x32, 0x40, 0xeb, 0x49, 0xe4, 0x1d, 0x04, 0x5a, 0xb8,
++ 0x86, 0x8c, 0xbf, 0x5f, 0xa4, 0x43, 0x9d, 0xfb, 0x31, 0xcb, 0xfd, 0x38,
++ 0x11, 0xd2, 0x8f, 0xb0, 0xb9, 0x68, 0x9e, 0xc7, 0xdb, 0xe9, 0x20, 0x6f,
++ 0x61, 0xf3, 0xa3, 0xf8, 0xa6, 0xdd, 0x3f, 0xe5, 0xf1, 0x01, 0xf3, 0x58,
++ 0x24, 0x1e, 0x93, 0xdf, 0x5a, 0xf2, 0x94, 0xf6, 0xf0, 0x24, 0xeb, 0xec,
++ 0x0d, 0xe9, 0x73, 0x58, 0x7d, 0xd9, 0xbf, 0xee, 0x73, 0x20, 0x3f, 0xb8,
++ 0x8b, 0xdf, 0x9b, 0x04, 0x14, 0x0b, 0x2a, 0x5f, 0x3f, 0xcf, 0xc7, 0xa8,
++ 0xdf, 0x30, 0x97, 0x93, 0xfb, 0x62, 0xfe, 0x36, 0x35, 0x5c, 0x1b, 0xf9,
++ 0x88, 0x04, 0xab, 0x98, 0x23, 0x7f, 0x47, 0xd3, 0x78, 0x7d, 0x50, 0x5d,
++ 0xa8, 0xbe, 0x4b, 0x8c, 0x41, 0x7e, 0x9a, 0xeb, 0xcc, 0x50, 0x3c, 0xd2,
++ 0x81, 0xc1, 0x3a, 0xc8, 0xf3, 0xf7, 0x28, 0xc8, 0x87, 0x55, 0x5d, 0x59,
++ 0xf4, 0xce, 0x75, 0x12, 0x8a, 0x39, 0xd2, 0x55, 0x73, 0x5f, 0x59, 0x6f,
++ 0x6b, 0xea, 0xbb, 0x84, 0xdb, 0xd5, 0x92, 0xee, 0xab, 0xf7, 0x12, 0x64,
++ 0xbd, 0x3c, 0x47, 0x5a, 0xe8, 0xa3, 0x5d, 0x1c, 0xdf, 0x79, 0x0e, 0x64,
++ 0x5b, 0x7d, 0x6f, 0x4c, 0xae, 0xeb, 0x0c, 0xeb, 0xfb, 0x68, 0x93, 0xbe,
++ 0xd5, 0x7d, 0xf5, 0xef, 0x74, 0xce, 0xf5, 0x9b, 0x68, 0x97, 0xda, 0x59,
++ 0xf7, 0xde, 0x4f, 0x71, 0xcf, 0xfd, 0x44, 0x6e, 0xa6, 0xca, 0xbb, 0xcf,
++ 0x7b, 0xaf, 0x1c, 0x0a, 0xe9, 0x83, 0xf7, 0x3e, 0x0a, 0xd6, 0xeb, 0xd7,
++ 0x23, 0xf5, 0x35, 0xce, 0xf5, 0x9b, 0x0d, 0xee, 0xc3, 0x54, 0xff, 0x0c,
++ 0xe9, 0x3f, 0x53, 0x90, 0xfa, 0x71, 0xc1, 0x31, 0xe9, 0x7c, 0x42, 0x71,
++ 0x8e, 0x66, 0x62, 0xde, 0xf3, 0x1a, 0xad, 0xe7, 0x67, 0xd0, 0x2f, 0x3e,
++ 0xa7, 0xf6, 0xf3, 0x48, 0xd8, 0xe4, 0x8b, 0x2d, 0xe2, 0xbd, 0xa6, 0xab,
++ 0xb9, 0x70, 0x91, 0xef, 0x01, 0x97, 0xec, 0xcc, 0x2b, 0x8a, 0x2f, 0xb9,
++ 0xaf, 0xc3, 0x12, 0xcd, 0xc5, 0xad, 0x47, 0x84, 0x37, 0xe1, 0x32, 0x9d,
++ 0xfb, 0xfb, 0xfb, 0x66, 0x21, 0x42, 0x97, 0x57, 0xc7, 0x51, 0xa1, 0x63,
++ 0x9c, 0x63, 0x25, 0x57, 0x78, 0xae, 0x11, 0x9f, 0xf3, 0xa4, 0x73, 0x8d,
++ 0xf3, 0xc3, 0xab, 0x45, 0x3e, 0xab, 0xba, 0xac, 0xf7, 0x9a, 0xd2, 0x1d,
++ 0x0c, 0x9b, 0x38, 0x3f, 0xa9, 0xca, 0x02, 0x2e, 0x7b, 0x1d, 0x46, 0xbb,
++ 0x4c, 0x18, 0xc3, 0xfc, 0x75, 0x78, 0x58, 0x93, 0x7e, 0x05, 0xbe, 0xdf,
++ 0x7e, 0xb0, 0x5e, 0x74, 0xa8, 0xf0, 0xef, 0x8b, 0x05, 0x7c, 0x3f, 0x01,
++ 0xcd, 0xf7, 0x1b, 0xc5, 0x29, 0x0f, 0x11, 0xda, 0xa7, 0xb8, 0xaf, 0xc3,
++ 0xd2, 0xce, 0x11, 0x7e, 0xdc, 0x3f, 0xec, 0xc3, 0x05, 0x8f, 0x3f, 0x42,
++ 0xe5, 0xc3, 0x40, 0x98, 0xbf, 0xb4, 0xff, 0xde, 0xe2, 0x3e, 0xa5, 0xf7,
++ 0x2f, 0xc9, 0x7e, 0xaa, 0xff, 0x19, 0xd7, 0x3f, 0xec, 0xd5, 0xbd, 0x8a,
++ 0xf7, 0xae, 0xbe, 0xff, 0x7d, 0xdc, 0xc1, 0x76, 0x5b, 0xfb, 0xd8, 0xd1,
++ 0xf1, 0xf9, 0x41, 0xef, 0xfd, 0xfd, 0xa6, 0x4e, 0x3c, 0x6d, 0xd4, 0xd5,
++ 0x5c, 0x6d, 0x84, 0xcc, 0xd5, 0xc5, 0xff, 0x3a, 0x57, 0x10, 0x98, 0xab,
++ 0xd5, 0xfa, 0xc1, 0xe6, 0x0a, 0xb8, 0x7e, 0x08, 0x99, 0xab, 0x18, 0xf3,
++ 0xf0, 0x94, 0xcf, 0x33, 0x20, 0xaa, 0xc7, 0xb0, 0x7d, 0xc6, 0x2c, 0xeb,
++ 0x92, 0xf4, 0x68, 0x47, 0xcb, 0xa8, 0x3f, 0xc7, 0x2e, 0x93, 0x9d, 0x41,
++ 0xfb, 0x49, 0x85, 0x0b, 0xb3, 0xf4, 0x7b, 0x4a, 0x83, 0x9f, 0x94, 0x15,
++ 0x12, 0x3d, 0x80, 0x0b, 0x00, 0x00, 0x00 };
++
++static u8 bnx2_rv2p_proc2[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x7e, 0xd1, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xcd, 0x58, 0x5b, 0x6c,
++ 0x54, 0x55, 0x14, 0x3d, 0xf3, 0xe8, 0xcc, 0x9d, 0xe9, 0xed, 0x9d, 0xf2,
++ 0xb2, 0x03, 0xad, 0x08, 0xe5, 0xd1, 0x56, 0x29, 0xe8, 0x54, 0xab, 0x18,
++ 0x15, 0x2c, 0x5a, 0x8c, 0x26, 0x68, 0xf0, 0xf9, 0x63, 0x14, 0x04, 0xda,
++ 0x9a, 0x56, 0x9b, 0x16, 0xfb, 0x81, 0xaf, 0x09, 0x14, 0x6a, 0x4c, 0x25,
++ 0xd6, 0x08, 0xc5, 0x47, 0xa0, 0x11, 0x1f, 0x84, 0xf0, 0xd3, 0x1f, 0x3b,
++ 0x8d, 0x7f, 0x0a, 0x24, 0x6a, 0x88, 0xc4, 0xa8, 0x9f, 0x24, 0x68, 0xa0,
++ 0x21, 0x0a, 0x58, 0x8b, 0x63, 0x4c, 0xb4, 0xf5, 0xec, 0xbd, 0xf6, 0xb9,
++ 0x73, 0xef, 0x6d, 0x8b, 0x1a, 0xf9, 0x70, 0x3e, 0xba, 0x7b, 0xce, 0xd9,
++ 0x67, 0x3f, 0xd6, 0xde, 0x67, 0x9f, 0x7d, 0xae, 0x52, 0xfc, 0xbb, 0xb6,
++ 0x94, 0xc9, 0x37, 0x83, 0x96, 0xfe, 0x1b, 0x51, 0x0f, 0x85, 0xd3, 0x3c,
++ 0x8e, 0x2a, 0xa2, 0x49, 0xa5, 0xb2, 0x5e, 0xea, 0x08, 0x7d, 0x44, 0xe8,
++ 0x70, 0x08, 0xf4, 0xb4, 0xd0, 0x77, 0x84, 0xfe, 0x2e, 0xf4, 0x80, 0xd0,
++ 0x0f, 0x85, 0xea, 0x5f, 0xd6, 0xd6, 0x7f, 0xf4, 0xb0, 0x46, 0x89, 0x7e,
++ 0x1b, 0xd3, 0x35, 0xb0, 0xe3, 0xc1, 0x05, 0xc4, 0x77, 0x61, 0xa2, 0xc0,
++ 0x87, 0xf9, 0x53, 0x7d, 0xa0, 0xd7, 0x60, 0xd7, 0xe1, 0xec, 0x0a, 0xb3,
++ 0x1f, 0x64, 0x43, 0x09, 0xe8, 0xc6, 0x08, 0xe8, 0xea, 0x65, 0x4c, 0x7a,
++ 0x9f, 0x0a, 0x63, 0xdc, 0xb8, 0x94, 0xf6, 0x87, 0x55, 0x83, 0x22, 0x3f,
++ 0x67, 0xaa, 0x68, 0x98, 0xc6, 0xf5, 0x56, 0x6c, 0x18, 0xeb, 0x8f, 0xa5,
++ 0x40, 0x37, 0x25, 0x41, 0xcf, 0x08, 0xdd, 0x52, 0x2c, 0x7a, 0x6c, 0x31,
++ 0xbf, 0x98, 0xf6, 0x25, 0x5c, 0x39, 0xc7, 0x6d, 0xe0, 0x96, 0x95, 0xfd,
++ 0x4a, 0xc1, 0xce, 0x03, 0xb2, 0x3e, 0xa3, 0x0a, 0xb3, 0xaf, 0x6f, 0xc1,
++ 0xb8, 0xfc, 0x20, 0xf9, 0xa7, 0xff, 0xcf, 0x62, 0x7e, 0xfa, 0xfd, 0xf8,
++ 0x15, 0xf6, 0x83, 0x96, 0x2f, 0xa2, 0x75, 0x27, 0xd3, 0x3f, 0x88, 0xf1,
++ 0xde, 0x25, 0x32, 0x1f, 0x36, 0xf8, 0x18, 0x79, 0x41, 0x5c, 0x99, 0x58,
++ 0xc7, 0x2a, 0x7d, 0xf2, 0x2b, 0x15, 0xe4, 0x2f, 0xc8, 0x2e, 0x35, 0xf2,
++ 0x81, 0xfb, 0xfa, 0x16, 0xb2, 0x73, 0x4c, 0xc7, 0x01, 0xb8, 0xcd, 0x0a,
++ 0x95, 0xb2, 0xdc, 0x7d, 0x83, 0x5e, 0x3d, 0x51, 0xad, 0x07, 0xfa, 0x54,
++ 0xa5, 0xc5, 0x20, 0x65, 0x97, 0x81, 0xaa, 0x5a, 0xbf, 0x1f, 0x7b, 0x97,
++ 0x18, 0x7b, 0x30, 0x9e, 0x9d, 0x01, 0xdd, 0x23, 0xf4, 0xaa, 0x3a, 0x26,
++ 0xcb, 0x7f, 0xb8, 0xc1, 0x62, 0x0c, 0xb2, 0xb5, 0xde, 0x7c, 0x38, 0x32,
++ 0x61, 0xf0, 0x52, 0x8b, 0x40, 0xce, 0x2e, 0x21, 0x3e, 0x1d, 0x9c, 0x4a,
++ 0xc8, 0x5d, 0xdf, 0x32, 0x55, 0x1e, 0x7d, 0x30, 0x45, 0x1e, 0x61, 0xff,
++ 0xb7, 0x2b, 0x7c, 0xf9, 0xa4, 0xda, 0x25, 0x4f, 0x36, 0x22, 0x8f, 0xac,
++ 0xa7, 0x3e, 0x91, 0x85, 0x6b, 0x13, 0xfa, 0xcf, 0x84, 0x7a, 0x32, 0x4e,
++ 0x01, 0x8a, 0x2b, 0x87, 0xfd, 0x53, 0xe2, 0xe7, 0x26, 0xed, 0x27, 0xd1,
++ 0x8a, 0x50, 0xb6, 0x36, 0xc1, 0x38, 0x35, 0xc4, 0xa0, 0xaf, 0x61, 0x03,
++ 0xb6, 0xaf, 0x46, 0x5c, 0x7b, 0x4f, 0x86, 0x8d, 0xfd, 0x51, 0xfa, 0x3b,
++ 0xd0, 0xb6, 0x9d, 0x47, 0x03, 0xd1, 0x1d, 0x4c, 0xed, 0x63, 0x95, 0x58,
++ 0xee, 0x8a, 0xf0, 0x7a, 0x72, 0x97, 0xcc, 0xf7, 0xec, 0xf0, 0xdb, 0xfd,
++ 0x02, 0xf2, 0xdb, 0x7e, 0x7e, 0x47, 0x88, 0xa8, 0x13, 0x73, 0xf9, 0x98,
++ 0x3a, 0x3b, 0xb7, 0x13, 0xff, 0x55, 0x6a, 0xd7, 0x20, 0x29, 0x4e, 0xab,
++ 0x0d, 0x6b, 0xb1, 0x6f, 0x77, 0x2c, 0xc5, 0xb8, 0x36, 0xad, 0x05, 0xfd,
++ 0x1e, 0xf3, 0xf3, 0x9d, 0x1e, 0xe2, 0x2f, 0x9d, 0xe7, 0x0c, 0x71, 0x5e,
++ 0xa9, 0x11, 0xce, 0xc7, 0x04, 0x65, 0x06, 0xff, 0xda, 0xaa, 0xc1, 0xdf,
++ 0xbc, 0x99, 0x15, 0xbf, 0xd9, 0x9a, 0xe7, 0x3c, 0x18, 0xe8, 0x18, 0x26,
++ 0x3f, 0xe7, 0xaa, 0x91, 0x4e, 0xa2, 0x51, 0xd5, 0xb0, 0x90, 0xf0, 0x5e,
++ 0x15, 0x36, 0x71, 0x3a, 0x7f, 0x33, 0xcd, 0xcf, 0xd3, 0xeb, 0x26, 0x1e,
++ 0x24, 0xd7, 0x92, 0x78, 0x45, 0x5d, 0x7c, 0xf2, 0x61, 0xf8, 0xdb, 0xcd,
++ 0x76, 0x5f, 0x97, 0xec, 0xe6, 0xfc, 0x4a, 0xaa, 0x26, 0x8e, 0x7f, 0xd4,
++ 0x6a, 0x1b, 0xc6, 0xfa, 0xf9, 0x8f, 0x8d, 0x5c, 0xd2, 0x53, 0x23, 0x75,
++ 0x44, 0xb9, 0x72, 0xa2, 0x37, 0x83, 0xee, 0x34, 0x7a, 0xeb, 0x88, 0x6f,
++ 0xb1, 0x42, 0xfe, 0x26, 0x26, 0xc9, 0x69, 0x03, 0xce, 0xf6, 0x33, 0xec,
++ 0xf7, 0x35, 0xf6, 0x85, 0x3e, 0x63, 0x2f, 0xe6, 0x2f, 0xfa, 0xf4, 0x95,
++ 0x7b, 0xf4, 0x11, 0x7f, 0x51, 0xf2, 0x02, 0xef, 0x9b, 0x63, 0x3d, 0x3b,
++ 0xcc, 0xb8, 0x58, 0xcf, 0x0c, 0x41, 0xfe, 0xc5, 0x21, 0xe2, 0x9f, 0x23,
++ 0x7a, 0xed, 0xff, 0x88, 0xe7, 0x9c, 0x30, 0xe4, 0x4c, 0x8f, 0x5f, 0xc1,
++ 0x6f, 0xe3, 0x17, 0xcb, 0xb5, 0x47, 0x73, 0x69, 0xe6, 0x33, 0xf1, 0xe8,
++ 0x0e, 0x73, 0x02, 0xa6, 0x1b, 0x16, 0xfa, 0x71, 0x33, 0xf6, 0x9c, 0xdf,
++ 0xcc, 0x79, 0x3e, 0xd1, 0x26, 0x75, 0x40, 0x71, 0x9d, 0xb9, 0x5d, 0xe2,
++ 0xa1, 0xf3, 0x3a, 0x04, 0xff, 0x46, 0x73, 0x2c, 0x3f, 0xd9, 0xc5, 0x79,
++ 0xb9, 0xd2, 0x8e, 0xe6, 0x38, 0x5e, 0xd6, 0xd9, 0x21, 0x6c, 0x2b, 0xd4,
++ 0x4f, 0xc8, 0x6b, 0xb6, 0x41, 0x9b, 0xa4, 0x8e, 0x9e, 0x15, 0xda, 0x6d,
++ 0x33, 0x3e, 0xba, 0x8e, 0x59, 0x2c, 0x3f, 0x9b, 0x32, 0xf7, 0x0c, 0xd6,
++ 0x9f, 0x16, 0x39, 0x3f, 0x0a, 0x55, 0x22, 0xa7, 0x55, 0xf6, 0x9f, 0xf3,
++ 0xc9, 0x89, 0x04, 0xe4, 0x84, 0x94, 0xc1, 0xcd, 0x9c, 0xef, 0x5d, 0x52,
++ 0xbf, 0xf7, 0xc5, 0xa6, 0xab, 0xb7, 0x7c, 0x0e, 0xdc, 0xba, 0x5a, 0x8e,
++ 0x3a, 0x53, 0x1f, 0x0d, 0xb3, 0xbf, 0x03, 0xdd, 0x3b, 0x80, 0x53, 0x8f,
++ 0xe0, 0x14, 0x07, 0x4e, 0xf3, 0x0a, 0xf5, 0x59, 0x14, 0xd4, 0x90, 0xfe,
++ 0x53, 0x21, 0xe3, 0xc7, 0xbe, 0x98, 0xaf, 0xfe, 0xf6, 0x9a, 0xfa, 0x5b,
++ 0xa8, 0xd3, 0xc4, 0xff, 0xb3, 0xa9, 0x6f, 0x5a, 0x9f, 0xd1, 0xff, 0x6f,
++ 0xf5, 0x72, 0x9c, 0x92, 0xdd, 0x7d, 0x26, 0xce, 0x98, 0x2e, 0xd4, 0xd9,
++ 0x22, 0x22, 0xcb, 0x46, 0x3a, 0x99, 0x5e, 0xdf, 0xbc, 0x15, 0xf3, 0x65,
++ 0x7c, 0x4e, 0x6e, 0x09, 0x01, 0xaf, 0xa8, 0x3a, 0xde, 0x87, 0xba, 0xae,
++ 0xe2, 0x2c, 0xaf, 0xe2, 0x28, 0xc7, 0x3f, 0xaa, 0xe5, 0x12, 0xdf, 0x67,
++ 0xa1, 0x42, 0x3e, 0x7a, 0xfd, 0xd9, 0xad, 0xf3, 0x84, 0xec, 0x88, 0xe9,
++ 0xbc, 0xa5, 0xb1, 0x3e, 0x47, 0xb6, 0xe4, 0xf9, 0x1a, 0xe6, 0xb3, 0xc7,
++ 0x22, 0x34, 0xff, 0x80, 0xd5, 0xd3, 0x87, 0xf9, 0x9f, 0x1a, 0x69, 0xbc,
++ 0xce, 0x7e, 0x0d, 0xe7, 0xcc, 0x7e, 0x0d, 0xf5, 0xcb, 0x2a, 0x3a, 0x88,
++ 0xba, 0xd6, 0x78, 0x10, 0xf2, 0x71, 0x4f, 0x7b, 0xfd, 0xf2, 0xe2, 0x47,
++ 0xe7, 0xe1, 0xb2, 0x38, 0xd9, 0xcf, 0x09, 0x4e, 0x97, 0x7c, 0xf1, 0x39,
++ 0x6c, 0xe2, 0xd3, 0x1b, 0x93, 0xf3, 0xd2, 0x7c, 0x29, 0xe8, 0x17, 0xf1,
++ 0x9d, 0x71, 0xef, 0x9d, 0xae, 0x95, 0xa0, 0xdd, 0x2b, 0xe5, 0x9c, 0xd6,
++ 0xf9, 0xf3, 0x6b, 0x3e, 0xea, 0xf2, 0xb8, 0x7b, 0x4f, 0x20, 0xbf, 0xac,
++ 0x9d, 0xf0, 0x4b, 0xbd, 0x28, 0x79, 0x3c, 0x2e, 0xf4, 0x65, 0xc9, 0xdf,
++ 0x6d, 0xd2, 0xb7, 0x98, 0xfe, 0xe2, 0x0f, 0xcc, 0x3b, 0xfd, 0x6e, 0x5f,
++ 0x60, 0xea, 0x36, 0x8d, 0x43, 0xca, 0x89, 0x13, 0x83, 0x36, 0xeb, 0x33,
++ 0x24, 0x4a, 0xcf, 0x1a, 0xe0, 0x35, 0x52, 0x07, 0xbe, 0xdd, 0x91, 0xb0,
++ 0x8c, 0x21, 0x6f, 0xac, 0xda, 0x77, 0x0f, 0xd7, 0x4f, 0xc6, 0x93, 0xe4,
++ 0xc6, 0xdc, 0xfa, 0x24, 0x79, 0xaf, 0x26, 0x84, 0x96, 0x2f, 0xbe, 0x2c,
++ 0xbe, 0x85, 0xfe, 0x64, 0xa9, 0x17, 0xdf, 0x97, 0x34, 0xbe, 0xbc, 0xaf,
++ 0xbe, 0xf9, 0x12, 0xa6, 0x4b, 0x6f, 0x05, 0xed, 0xbb, 0x95, 0xe7, 0x17,
++ 0xa3, 0xee, 0x11, 0x7e, 0x9c, 0x5f, 0xf5, 0x6f, 0x0c, 0x9a, 0x7e, 0x42,
++ 0xf0, 0x08, 0xf4, 0x41, 0x65, 0x77, 0x80, 0xbe, 0x29, 0x74, 0xce, 0x2a,
++ 0xd0, 0xbd, 0xab, 0xfc, 0x71, 0x88, 0xa5, 0x7c, 0x71, 0xac, 0x47, 0x1c,
++ 0x8f, 0x4c, 0x04, 0xeb, 0x81, 0xc4, 0x4b, 0xc7, 0x27, 0x70, 0xbf, 0x1b,
++ 0xfd, 0xe2, 0xce, 0xdf, 0xc5, 0xed, 0x4a, 0xc7, 0xab, 0x7b, 0x25, 0xee,
++ 0x93, 0x0e, 0xe9, 0x4b, 0xc7, 0xdc, 0xfb, 0xe2, 0x9f, 0xc4, 0x31, 0x7e,
++ 0x85, 0xe3, 0x78, 0xf7, 0xff, 0x2c, 0x8e, 0x9d, 0x12, 0xc7, 0x22, 0xb9,
++ 0x57, 0x4d, 0xbf, 0xd9, 0x2e, 0x7d, 0x18, 0xf5, 0x8d, 0x7e, 0xbd, 0x4f,
++ 0x70, 0x1f, 0x78, 0xb5, 0x5b, 0x8f, 0xe7, 0x33, 0x7f, 0x4e, 0xf6, 0x95,
++ 0xca, 0xbe, 0x7b, 0x26, 0xed, 0x3b, 0xc5, 0xf5, 0xee, 0xf1, 0xf1, 0xc9,
++ 0xef, 0x15, 0x9f, 0x9d, 0x59, 0x95, 0x02, 0xee, 0xa8, 0xe3, 0xb1, 0x29,
++ 0xde, 0x37, 0x86, 0x1f, 0xf9, 0xb5, 0x36, 0x85, 0xba, 0x05, 0xfe, 0xb9,
++ 0x9e, 0x7a, 0x4a, 0xe3, 0xfb, 0xc7, 0xa7, 0xef, 0x57, 0x8d, 0x3c, 0xc4,
++ 0x6d, 0x43, 0xb8, 0x84, 0xf9, 0x4e, 0xb7, 0xf3, 0x7d, 0xe7, 0xfa, 0xb7,
++ 0x9a, 0xfd, 0x3a, 0x2a, 0xfe, 0x55, 0x88, 0x7f, 0x7a, 0xb9, 0x96, 0xeb,
++ 0xbe, 0x75, 0xba, 0xdd, 0xeb, 0xdf, 0x9d, 0x97, 0xd1, 0xf7, 0x4f, 0xfb,
++ 0x63, 0xd1, 0x9b, 0x32, 0xfa, 0x49, 0x5e, 0xb9, 0xf4, 0x7d, 0xd4, 0x4f,
++ 0x62, 0x7e, 0x72, 0x9f, 0x41, 0xfa, 0x5b, 0x34, 0x5e, 0x72, 0xdf, 0x70,
++ 0x3e, 0x47, 0xac, 0xa3, 0x6c, 0x57, 0x5e, 0xf9, 0x71, 0x39, 0x23, 0x7c,
++ 0x53, 0xc5, 0x8d, 0xd6, 0x8b, 0x64, 0x7d, 0x2a, 0xbf, 0xc5, 0x4e, 0x37,
++ 0x1f, 0x64, 0x1f, 0xf3, 0x35, 0x0b, 0x5f, 0x34, 0x34, 0x39, 0xfe, 0x18,
++ 0xe5, 0xab, 0x38, 0xaf, 0xf7, 0x6f, 0xcb, 0x11, 0x9f, 0x76, 0x9e, 0xf3,
++ 0xf0, 0xfb, 0x80, 0x7d, 0xe9, 0x2b, 0x80, 0x23, 0xf1, 0xcd, 0x50, 0x4d,
++ 0xce, 0x74, 0x78, 0xe1, 0xdd, 0x30, 0x9a, 0x33, 0x78, 0xdb, 0xec, 0xe7,
++ 0x48, 0x27, 0xe9, 0x5f, 0x1d, 0xc0, 0x31, 0x2c, 0x38, 0x9e, 0x50, 0x7f,
++ 0x9f, 0xf7, 0xc6, 0x0f, 0x6f, 0x5e, 0x8c, 0xff, 0x19, 0xcc, 0xe3, 0x87,
++ 0xe5, 0x5d, 0xdd, 0x18, 0x03, 0xfd, 0x2e, 0x62, 0xec, 0x46, 0x5e, 0xdf,
++ 0xc3, 0xe7, 0xb5, 0x4a, 0xf5, 0xf2, 0xbb, 0xc3, 0x52, 0x0d, 0x6b, 0xc9,
++ 0xee, 0x94, 0xae, 0x7f, 0xc8, 0x77, 0x27, 0xee, 0xbd, 0xb7, 0x75, 0x0d,
++ 0x4c, 0xc4, 0x69, 0x58, 0x31, 0x33, 0xc1, 0x82, 0xde, 0xf8, 0xe2, 0x4b,
++ 0x5e, 0x7e, 0xaf, 0xbf, 0x18, 0xf3, 0x65, 0xf7, 0x91, 0x9c, 0x88, 0xda,
++ 0x8b, 0xba, 0xfb, 0xee, 0x1e, 0xd0, 0xb7, 0xd5, 0xbd, 0xd8, 0x3f, 0x73,
++ 0x3b, 0xd7, 0x51, 0xab, 0x4c, 0xf2, 0x2b, 0x0d, 0x5c, 0xd3, 0xa8, 0xc3,
++ 0x13, 0x13, 0xaa, 0x04, 0xf7, 0x9a, 0x79, 0x07, 0xab, 0x1a, 0xd1, 0x8b,
++ 0xfa, 0x68, 0x17, 0xde, 0xc1, 0x44, 0x8b, 0x83, 0x7d, 0x9f, 0x55, 0xe8,
++ 0xaf, 0x08, 0x8f, 0xf7, 0x5d, 0x1c, 0xd3, 0xe1, 0x60, 0x5d, 0xf2, 0xfa,
++ 0x15, 0x93, 0x73, 0xfd, 0xab, 0xfb, 0x6e, 0xee, 0xe1, 0x7e, 0x2a, 0x19,
++ 0xac, 0xcb, 0x01, 0xf9, 0xfb, 0x24, 0x7e, 0x49, 0x89, 0x5f, 0x54, 0xc7,
++ 0x0f, 0xef, 0xed, 0x4f, 0x7d, 0xef, 0x7a, 0xaa, 0x1b, 0xde, 0xbc, 0xfb,
++ 0xfc, 0x4f, 0x63, 0xd7, 0xf6, 0x98, 0xb7, 0x0e, 0x57, 0xbb, 0xe7, 0xae,
++ 0x43, 0xde, 0x8b, 0x5d, 0x87, 0x30, 0xce, 0x73, 0xbf, 0xbc, 0x38, 0xd3,
++ 0x21, 0x79, 0x74, 0x57, 0x44, 0xf2, 0x41, 0xec, 0xfb, 0x22, 0x62, 0xee,
++ 0x1b, 0x8c, 0xbf, 0x92, 0xfb, 0xee, 0x97, 0x2a, 0xf4, 0xd9, 0x17, 0x87,
++ 0xcc, 0xfb, 0xc4, 0xbc, 0x57, 0xb0, 0xbe, 0x3e, 0xae, 0x04, 0x67, 0xbe,
++ 0xff, 0xb5, 0x3f, 0x9c, 0xaf, 0x99, 0x8e, 0x61, 0x1f, 0x5e, 0x2a, 0x16,
++ 0x78, 0xbf, 0xc4, 0xe5, 0xfb, 0x45, 0xbf, 0xe0, 0xe1, 0xf0, 0xf9, 0x29,
++ 0xd5, 0xf6, 0x13, 0x4d, 0x65, 0x3a, 0x73, 0xb0, 0xa7, 0xd5, 0xed, 0x23,
++ 0xc1, 0x27, 0xd4, 0x79, 0x4b, 0xde, 0xc1, 0xf2, 0x5e, 0xd6, 0xef, 0x61,
++ 0xf4, 0x73, 0xad, 0x79, 0x8c, 0xc7, 0xd0, 0xb7, 0x39, 0xbf, 0xca, 0xbd,
++ 0xb5, 0x75, 0x9b, 0xe9, 0x4b, 0xa7, 0xde, 0x67, 0xee, 0xb9, 0xb6, 0x6a,
++ 0xd0, 0x16, 0xee, 0x5b, 0x1f, 0xb2, 0xf3, 0x92, 0x1f, 0x85, 0x77, 0x89,
++ 0xff, 0x3d, 0x62, 0xfa, 0x85, 0x73, 0xc5, 0xb8, 0x67, 0xf3, 0xbd, 0x34,
++ 0xa1, 0xdf, 0x23, 0x09, 0x6f, 0x9e, 0x25, 0x32, 0x65, 0x82, 0xfb, 0xec,
++ 0x9b, 0x40, 0xf7, 0xdc, 0x84, 0xbe, 0xbc, 0xb5, 0x4b, 0x70, 0xb8, 0x91,
++ 0x71, 0x5b, 0x3e, 0x9a, 0x0b, 0x7e, 0x67, 0x21, 0x5c, 0x7f, 0x73, 0xfb,
++ 0xd1, 0x73, 0x6c, 0xd7, 0xbc, 0x81, 0x3c, 0xf3, 0xcd, 0x55, 0xb3, 0xf8,
++ 0xfc, 0xa6, 0x9d, 0x51, 0xd8, 0x99, 0xe9, 0x17, 0xbf, 0xda, 0x6f, 0x01,
++ 0xed, 0x92, 0x3a, 0x73, 0xd2, 0x7d, 0x97, 0xc3, 0x4e, 0x53, 0x4f, 0x26,
++ 0xbf, 0x13, 0x30, 0x9e, 0x5b, 0xc7, 0x63, 0xd5, 0xbc, 0x95, 0xe4, 0x97,
++ 0x4c, 0x7a, 0xcf, 0x16, 0xe2, 0x6e, 0xf2, 0xc1, 0xe4, 0x8f, 0xf7, 0x1d,
++ 0x7b, 0x9b, 0xa7, 0x5e, 0xfa, 0xe3, 0xef, 0x70, 0xbe, 0x84, 0x65, 0x3d,
++ 0x96, 0xe9, 0xef, 0xbb, 0x3c, 0x3e, 0x6f, 0x01, 0x9f, 0x8c, 0xd8, 0x6d,
++ 0xb7, 0xf0, 0x3b, 0x74, 0x96, 0xda, 0x25, 0xf1, 0x39, 0x57, 0x2d, 0x75,
++ 0x50, 0xec, 0xfb, 0x49, 0xfa, 0x1f, 0xc4, 0x31, 0x6e, 0x6f, 0xc9, 0x49,
++ 0xdc, 0x24, 0x8f, 0x9e, 0x16, 0xbf, 0x7f, 0x84, 0xdf, 0xb6, 0xf1, 0xbb,
++ 0xc5, 0xf5, 0xdb, 0xd4, 0x59, 0xaf, 0x9c, 0x99, 0x3a, 0x1f, 0xb8, 0x5e,
++ 0xdb, 0x27, 0xf9, 0xdd, 0x53, 0x24, 0xe7, 0xa1, 0x42, 0xbe, 0x3b, 0x38,
++ 0xe2, 0x4f, 0x89, 0x6a, 0x5a, 0xee, 0xdd, 0x57, 0x2c, 0xfb, 0x92, 0x7a,
++ 0x1f, 0xe6, 0x71, 0xfe, 0xec, 0x29, 0xf0, 0x34, 0xdf, 0x11, 0x8c, 0xdc,
++ 0xe0, 0x39, 0xf2, 0xe2, 0xc7, 0x37, 0x13, 0xff, 0x50, 0x07, 0x74, 0x9c,
++ 0x6a, 0xcd, 0xf7, 0x07, 0xcc, 0xe3, 0xfc, 0x26, 0xf7, 0xb7, 0xa1, 0xaf,
++ 0xdc, 0xdf, 0x76, 0x48, 0xfa, 0x08, 0xc1, 0xe5, 0x81, 0x21, 0xb2, 0x43,
++ 0xc7, 0xae, 0xd2, 0x7f, 0xfe, 0x61, 0x47, 0x54, 0xec, 0x28, 0xf7, 0xd8,
++ 0x11, 0xd0, 0x7b, 0x1d, 0xcd, 0xaf, 0x50, 0x5f, 0x73, 0x1e, 0x2e, 0x57,
++ 0xeb, 0x29, 0x47, 0xf4, 0xbd, 0xb0, 0xae, 0x88, 0xc6, 0xcb, 0xd4, 0xab,
++ 0xf0, 0xb7, 0x37, 0x59, 0x84, 0x3a, 0x96, 0xdc, 0x49, 0xf3, 0x35, 0xea,
++ 0xd5, 0x3e, 0x0e, 0xc4, 0x2b, 0xea, 0x18, 0xea, 0x73, 0xe3, 0x41, 0xb6,
++ 0x47, 0x1d, 0x1f, 0x34, 0xf5, 0x7a, 0xca, 0xef, 0x98, 0xbd, 0xeb, 0xa4,
++ 0x5e, 0x9c, 0xc0, 0x77, 0x51, 0xfd, 0x5e, 0x23, 0xfe, 0xd9, 0xe6, 0x3d,
++ 0xb8, 0xfb, 0x98, 0xa1, 0x8b, 0x7c, 0xe3, 0xfd, 0x27, 0x96, 0x0a, 0xad,
++ 0xf2, 0x8d, 0x07, 0xd6, 0x55, 0x09, 0xad, 0x36, 0xe3, 0xe9, 0xbe, 0x2b,
++ 0x5e, 0x29, 0xf9, 0x62, 0xf7, 0x7b, 0xe2, 0xcf, 0x47, 0xe2, 0xcf, 0x59,
++ 0xe0, 0x9f, 0xdc, 0x28, 0x78, 0x2c, 0x0a, 0xea, 0x17, 0xbb, 0xdc, 0x73,
++ 0x63, 0xd6, 0x11, 0x8f, 0x47, 0xd5, 0x5f, 0x3f, 0x97, 0x8f, 0x31, 0xd8,
++ 0x17, 0x00, 0x00, 0x00 };
++
++static int bnx2_TPAT_b06FwReleaseMajor = 0x1;
++static int bnx2_TPAT_b06FwReleaseMinor = 0x0;
++static int bnx2_TPAT_b06FwReleaseFix = 0x0;
++static u32 bnx2_TPAT_b06FwStartAddr = 0x08000860;
++static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
++static int bnx2_TPAT_b06FwTextLen = 0x122c;
++static u32 bnx2_TPAT_b06FwDataAddr = 0x08001a60;
++static int bnx2_TPAT_b06FwDataLen = 0x0;
++static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
++static int bnx2_TPAT_b06FwRodataLen = 0x0;
++static u32 bnx2_TPAT_b06FwBssAddr = 0x08001aa0;
++static int bnx2_TPAT_b06FwBssLen = 0x250;
++static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001a60;
++static int bnx2_TPAT_b06FwSbssLen = 0x34;
++static u8 bnx2_TPAT_b06FwText[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x47, 0xd2, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x57, 0x4d, 0x68,
++ 0x1c, 0xe7, 0x19, 0x7e, 0xe7, 0x77, 0x47, 0x62, 0x25, 0x8d, 0x93, 0x3d,
++ 0xac, 0x5d, 0xa5, 0x99, 0x91, 0x46, 0x3f, 0x54, 0x26, 0x9e, 0x84, 0xa5,
++ 0x56, 0x61, 0x20, 0xe3, 0x99, 0x95, 0x2c, 0x0c, 0x05, 0x07, 0x42, 0x08,
++ 0xe4, 0xb2, 0x1d, 0x49, 0x36, 0x85, 0x1e, 0x5a, 0x9a, 0x43, 0xa0, 0x05,
++ 0x0f, 0x33, 0xeb, 0x34, 0x87, 0xc5, 0xdb, 0xaa, 0xc5, 0xbe, 0x94, 0xd6,
++ 0x95, 0xea, 0xe8, 0xb2, 0x68, 0xe2, 0x53, 0x0f, 0xc5, 0xd8, 0xb4, 0x54,
++ 0xd0, 0x53, 0x7b, 0x0a, 0x85, 0x5c, 0x4c, 0x69, 0x20, 0x85, 0x12, 0x44,
++ 0x0f, 0x21, 0xd4, 0xad, 0xa7, 0xcf, 0xfb, 0xcd, 0x8c, 0xbc, 0xbb, 0x95,
++ 0x5b, 0x1f, 0x02, 0x15, 0xac, 0x66, 0xe6, 0xfb, 0xde, 0xf7, 0xfb, 0x79,
++ 0x9f, 0xe7, 0x79, 0xbf, 0xf7, 0x6b, 0xca, 0x34, 0x49, 0xe5, 0xdf, 0x14,
++ 0x7e, 0x6f, 0x7f, 0xe3, 0xdb, 0x6f, 0x7f, 0xf5, 0xa5, 0x57, 0x2c, 0xa2,
++ 0x57, 0x5e, 0x92, 0x64, 0x5d, 0xa6, 0x2f, 0xe0, 0x4f, 0x21, 0x32, 0xab,
++ 0xf1, 0xf9, 0x47, 0x86, 0xec, 0x75, 0xce, 0x04, 0x0e, 0x19, 0x8a, 0x77,
++ 0x34, 0xbb, 0xe9, 0x10, 0xf9, 0x83, 0x15, 0x2b, 0xa4, 0x7f, 0xe5, 0x71,
++ 0x43, 0x25, 0x6e, 0x7f, 0xc1, 0xfb, 0xe7, 0xb9, 0x7b, 0xe7, 0xed, 0xa3,
++ 0xdb, 0x0a, 0x19, 0xa6, 0xd7, 0x31, 0xcc, 0x45, 0x32, 0x66, 0xe1, 0xf3,
++ 0xd3, 0xa5, 0x75, 0x8d, 0xa6, 0xab, 0xb1, 0x4c, 0x4a, 0xfa, 0x06, 0xad,
++ 0xf5, 0x30, 0x8e, 0xf3, 0x8e, 0x14, 0x66, 0xaa, 0x14, 0xde, 0x32, 0x48,
++ 0xf6, 0x7c, 0x29, 0xc8, 0x1c, 0xf4, 0x49, 0x14, 0xb8, 0x35, 0xf2, 0xcd,
++ 0x3c, 0xff, 0xa6, 0x2b, 0x93, 0xec, 0x3c, 0xce, 0xe7, 0x17, 0xd6, 0xa5,
++ 0x60, 0x7f, 0x43, 0x0a, 0xf7, 0x03, 0xde, 0x37, 0xd6, 0xb1, 0x2e, 0xf9,
++ 0xfb, 0xfc, 0xf4, 0x8c, 0xb0, 0x37, 0x4d, 0x9d, 0x06, 0xcd, 0xc8, 0x0e,
++ 0xfb, 0x5a, 0x14, 0xba, 0x2b, 0x4d, 0x85, 0xe6, 0xf1, 0x9b, 0xa0, 0x6d,
++ 0x97, 0xea, 0x81, 0x4b, 0xaa, 0xe2, 0xc8, 0x14, 0x36, 0x24, 0xfa, 0x65,
++ 0x4b, 0xc3, 0xef, 0x92, 0xd4, 0xde, 0xdf, 0x2a, 0xc7, 0x69, 0x50, 0x8a,
++ 0xb5, 0x44, 0x0d, 0x5e, 0x5b, 0xe1, 0x1f, 0xb8, 0x2b, 0xa6, 0x4c, 0xf3,
++ 0xf8, 0x4d, 0xe1, 0x3d, 0x82, 0x9d, 0x46, 0x41, 0x6b, 0xbc, 0x6f, 0x02,
++ 0xef, 0x58, 0x27, 0xc6, 0x0a, 0xc4, 0x3a, 0x2c, 0xac, 0xc3, 0xa1, 0x6e,
++ 0x7f, 0x03, 0xfb, 0x58, 0x68, 0x46, 0xa4, 0x53, 0x57, 0xac, 0x7d, 0x8a,
++ 0x12, 0x53, 0xa1, 0xe4, 0xac, 0x46, 0xfe, 0x65, 0x15, 0xdf, 0xcf, 0x51,
++ 0x6c, 0x4a, 0xb0, 0xe9, 0x96, 0xf8, 0xd5, 0xd0, 0xaf, 0xa3, 0x7d, 0x86,
++ 0x92, 0xc6, 0x29, 0x49, 0xf6, 0xbe, 0x8f, 0xf6, 0x05, 0x33, 0xa2, 0xef,
++ 0xe1, 0x29, 0xe1, 0xfb, 0x14, 0x8f, 0x87, 0x6f, 0x89, 0x14, 0x87, 0xcc,
++ 0x20, 0xb3, 0x28, 0xcd, 0x2a, 0x5f, 0x6e, 0x2f, 0xda, 0xe2, 0x6c, 0x1c,
++ 0x3b, 0xd8, 0xf5, 0x5f, 0xa5, 0x8e, 0x49, 0xb1, 0xea, 0xc1, 0xa6, 0xef,
++ 0x98, 0x6d, 0xe0, 0xe4, 0x0b, 0x3c, 0xbf, 0xc6, 0xed, 0xfc, 0x87, 0x76,
++ 0x8b, 0x14, 0xcf, 0x31, 0x43, 0x6a, 0x51, 0xd1, 0xd7, 0x30, 0x83, 0x5b,
++ 0x2f, 0x93, 0x2f, 0xe2, 0x61, 0xe0, 0xdd, 0xc4, 0x9e, 0x74, 0x60, 0x9b,
++ 0xf8, 0x32, 0xc5, 0x4d, 0x83, 0xec, 0xd5, 0x2d, 0xf4, 0x7c, 0xdc, 0x53,
++ 0x10, 0x67, 0xc6, 0x49, 0x2d, 0xfd, 0x18, 0xd7, 0xdf, 0x62, 0x5d, 0xb1,
++ 0x69, 0xd0, 0x0c, 0x75, 0x5e, 0xcf, 0xf3, 0x3b, 0x6e, 0x9e, 0xeb, 0x9e,
++ 0xb3, 0xfc, 0x3e, 0xad, 0x34, 0x35, 0x5a, 0x34, 0xf1, 0x44, 0xdc, 0x1c,
++ 0xc4, 0x46, 0x2d, 0xe7, 0x9f, 0x2a, 0xd7, 0xfa, 0x48, 0x42, 0xe8, 0xe9,
++ 0xcf, 0xbd, 0xdf, 0xf0, 0xde, 0x97, 0xd7, 0x85, 0x7d, 0x9e, 0xef, 0xae,
++ 0x3e, 0xcd, 0x5e, 0x93, 0x0b, 0xfb, 0x3c, 0x5f, 0x6b, 0xf1, 0x7c, 0x36,
++ 0xf6, 0xc6, 0x9c, 0x24, 0x5a, 0x1b, 0xb8, 0x46, 0xd4, 0xc3, 0xba, 0x1c,
++ 0x3c, 0x07, 0x4d, 0xac, 0xdd, 0x5e, 0xb6, 0x24, 0x83, 0x12, 0x27, 0x7f,
++ 0x11, 0x3c, 0xf0, 0x43, 0xc7, 0xfe, 0x53, 0xa8, 0xd4, 0x68, 0xcf, 0xad,
++ 0x53, 0x37, 0x6b, 0x52, 0x92, 0x75, 0x29, 0xc8, 0x64, 0x8c, 0x5f, 0xa3,
++ 0x5d, 0xe7, 0xf3, 0x7c, 0xcd, 0x75, 0x81, 0x33, 0xb1, 0x5f, 0x73, 0x8d,
++ 0x66, 0xd1, 0xbf, 0x62, 0x6e, 0x91, 0x8b, 0x98, 0xcb, 0x88, 0xc9, 0xbc,
++ 0x78, 0x4f, 0x32, 0x17, 0xfd, 0x14, 0xcb, 0x2d, 0xdb, 0x4c, 0xc8, 0x6e,
++ 0x06, 0x0a, 0x99, 0xb2, 0x67, 0xc2, 0x26, 0xa6, 0x76, 0x66, 0xd0, 0x43,
++ 0xe5, 0x1d, 0xc1, 0xe3, 0xb4, 0xff, 0x30, 0xbf, 0xb7, 0xd4, 0xa4, 0xfb,
++ 0x59, 0x83, 0xee, 0x66, 0x24, 0x47, 0x1c, 0xab, 0x86, 0x49, 0x1f, 0x64,
++ 0xd5, 0x3e, 0xc0, 0x65, 0x27, 0x39, 0xa3, 0x40, 0x67, 0x9b, 0xee, 0x03,
++ 0xb0, 0xc4, 0x06, 0x0e, 0x31, 0xf6, 0x5c, 0x3d, 0x79, 0x4f, 0xb7, 0xcf,
++ 0x6c, 0x3a, 0xf6, 0x7b, 0x21, 0xb3, 0xf3, 0x86, 0x8a, 0xd6, 0xe1, 0x38,
++ 0x7c, 0x1d, 0xfe, 0x26, 0x5d, 0x87, 0x5e, 0x64, 0xc4, 0x63, 0xee, 0xc0,
++ 0xa0, 0xfd, 0x5e, 0x8d, 0xac, 0x5d, 0x95, 0xa2, 0x7e, 0x83, 0xdc, 0x45,
++ 0xdb, 0x22, 0x59, 0x6e, 0xc8, 0x88, 0xdf, 0xdc, 0x6e, 0x4e, 0xeb, 0xae,
++ 0x46, 0x87, 0xce, 0x77, 0x75, 0x9a, 0x4e, 0x5c, 0x9d, 0xd8, 0xc6, 0xa0,
++ 0xb9, 0xf7, 0x0d, 0x29, 0xec, 0xf3, 0xfa, 0x39, 0xce, 0x46, 0x19, 0x67,
++ 0x55, 0x0a, 0x6e, 0xd5, 0x68, 0x7e, 0xe7, 0x6f, 0x79, 0xe0, 0x20, 0xc6,
++ 0xe0, 0xf1, 0x66, 0xcb, 0x56, 0x68, 0x12, 0x6d, 0xbb, 0xdc, 0x77, 0x54,
++ 0xb6, 0xf3, 0x18, 0x79, 0x1e, 0xb8, 0xcf, 0x53, 0xc0, 0xfc, 0x7e, 0x9d,
++ 0x7d, 0x6a, 0x34, 0xb7, 0xc3, 0xba, 0xc0, 0x73, 0x97, 0xbf, 0x79, 0x6d,
++ 0x13, 0x14, 0x61, 0x37, 0xd1, 0x72, 0x03, 0xfb, 0x97, 0x85, 0x06, 0x22,
++ 0xec, 0x56, 0x76, 0x26, 0xf1, 0x14, 0x71, 0x50, 0x0a, 0x3e, 0x73, 0x5e,
++ 0xa8, 0x53, 0x08, 0x5c, 0x55, 0xac, 0x67, 0x8b, 0x16, 0x9a, 0xdb, 0xa2,
++ 0x0f, 0x6d, 0x03, 0xee, 0x33, 0xc7, 0xfa, 0xf0, 0x3d, 0xa8, 0xd6, 0x20,
++ 0x03, 0xf3, 0x14, 0xb3, 0x68, 0x62, 0xaf, 0x6b, 0x2e, 0xdb, 0xb3, 0x6d,
++ 0xbc, 0xac, 0x91, 0xbd, 0xbc, 0x8b, 0xd1, 0xf7, 0x7b, 0xd8, 0xef, 0x4d,
++ 0xce, 0x35, 0x8e, 0xf5, 0x17, 0x62, 0xfb, 0x79, 0xec, 0x79, 0x61, 0x35,
++ 0xe5, 0xbe, 0x81, 0x46, 0xce, 0x4e, 0x6c, 0xaa, 0x88, 0xbd, 0x8c, 0xc0,
++ 0x87, 0x3f, 0xfc, 0x2c, 0xd7, 0x3c, 0x70, 0xb8, 0x35, 0x03, 0x6c, 0x6c,
++ 0x2b, 0x85, 0x9e, 0x1d, 0x8c, 0x9b, 0xb8, 0x0a, 0xfc, 0x0a, 0x8c, 0xd8,
++ 0x6e, 0xbd, 0x97, 0x53, 0x2a, 0xe6, 0xba, 0xc6, 0x73, 0x21, 0xe7, 0x38,
++ 0xab, 0xbf, 0x03, 0x27, 0x22, 0xaa, 0xd3, 0xe2, 0x41, 0x9d, 0xae, 0x0e,
++ 0xea, 0x34, 0x77, 0x43, 0x47, 0x1c, 0xf2, 0xbc, 0xdb, 0x62, 0x0d, 0x02,
++ 0x6b, 0x87, 0xed, 0xec, 0xa6, 0x22, 0xf3, 0x3a, 0xd0, 0x7f, 0x40, 0xb4,
++ 0x35, 0xd0, 0x11, 0x37, 0x75, 0x68, 0x6c, 0x99, 0x2e, 0xfe, 0x84, 0xe8,
++ 0xe2, 0x80, 0x7d, 0x79, 0xfc, 0xc2, 0x27, 0xc2, 0x9e, 0x65, 0x60, 0x7e,
++ 0x75, 0x20, 0x23, 0x1f, 0x20, 0x5f, 0xee, 0x07, 0xc8, 0x83, 0x6d, 0xfc,
++ 0xd6, 0x91, 0x1b, 0x19, 0x1b, 0xce, 0x13, 0x8f, 0x81, 0xcf, 0x06, 0xfa,
++ 0x2e, 0xa1, 0x8d, 0xf3, 0x16, 0xdb, 0xea, 0xd4, 0x76, 0xa7, 0x28, 0xad,
++ 0x72, 0x91, 0xc9, 0xb9, 0xe8, 0x14, 0xf8, 0x34, 0x81, 0xfc, 0x72, 0x47,
++ 0x19, 0xcd, 0x45, 0xc8, 0x59, 0x8d, 0xd3, 0xc8, 0x3d, 0x3f, 0x47, 0x3b,
++ 0x8f, 0xf7, 0x33, 0x3c, 0x27, 0xf0, 0x7d, 0x1a, 0xb6, 0xc3, 0x79, 0xa8,
++ 0xf2, 0x7b, 0x5a, 0x0e, 0x02, 0xef, 0x76, 0x0c, 0xd8, 0x5b, 0xd0, 0x0b,
++ 0xc7, 0xbb, 0x86, 0x7c, 0xc1, 0x31, 0xaf, 0x21, 0xa6, 0x3a, 0xe6, 0x36,
++ 0x69, 0xfe, 0x80, 0x62, 0xa5, 0xcc, 0x4f, 0xe1, 0x71, 0x7e, 0x6a, 0x0a,
++ 0x1e, 0x24, 0x99, 0x09, 0x1f, 0xd6, 0x6d, 0xa5, 0x53, 0xc6, 0x8e, 0xfc,
++ 0x00, 0x1a, 0x0e, 0x94, 0x3c, 0xdf, 0xc4, 0x19, 0x11, 0x01, 0x77, 0x1f,
++ 0xda, 0x8d, 0xa0, 0xdd, 0x70, 0x48, 0xbb, 0xe1, 0xff, 0xd4, 0x2e, 0x74,
++ 0x09, 0x8d, 0xdc, 0x05, 0xa7, 0x3e, 0xe8, 0x9f, 0xa4, 0x63, 0xd6, 0x30,
++ 0x6b, 0xd9, 0xa2, 0x7b, 0x4b, 0xcf, 0xa2, 0xe5, 0xbf, 0x3e, 0xab, 0x96,
++ 0x63, 0xd6, 0xb2, 0xca, 0x5a, 0x6e, 0x0c, 0x6b, 0xf9, 0x53, 0xf8, 0x17,
++ 0x9a, 0xbc, 0xa0, 0x36, 0x48, 0x5b, 0x04, 0x0e, 0x3b, 0x75, 0x52, 0x6e,
++ 0x3c, 0xe1, 0x1b, 0x73, 0x38, 0x1c, 0xe0, 0xdf, 0x81, 0x86, 0x3e, 0x69,
++ 0xb4, 0x1d, 0x39, 0x4f, 0xf5, 0xec, 0xe6, 0x96, 0xb0, 0x51, 0x49, 0x47,
++ 0xdc, 0xbf, 0xb3, 0x64, 0x5b, 0x96, 0x3c, 0xac, 0x79, 0xa8, 0x7e, 0x27,
++ 0xbf, 0xa6, 0x79, 0x3c, 0x4f, 0x6c, 0x81, 0xeb, 0xd6, 0x8f, 0x80, 0x51,
++ 0xda, 0x63, 0x9e, 0x3b, 0xe6, 0x9a, 0xe0, 0x17, 0xbe, 0xa1, 0x05, 0x0d,
++ 0x7c, 0xad, 0xc1, 0x4e, 0xdd, 0x29, 0xf4, 0x73, 0x17, 0xe3, 0xee, 0xf5,
++ 0x98, 0x5f, 0x06, 0xe9, 0x37, 0x9d, 0xe6, 0x55, 0x91, 0x73, 0xe7, 0xcd,
++ 0x75, 0x62, 0xed, 0xf1, 0x79, 0x87, 0xfe, 0x41, 0x8d, 0x14, 0xa1, 0xf7,
++ 0xc9, 0x52, 0xef, 0x2f, 0x20, 0x46, 0x93, 0xf8, 0x66, 0xcd, 0x9f, 0x2e,
++ 0x35, 0x3f, 0x8d, 0x27, 0xb7, 0x5d, 0x54, 0x0b, 0xee, 0x80, 0x87, 0x3b,
++ 0x8c, 0x6b, 0x1d, 0xf9, 0x8d, 0xe7, 0xff, 0x7b, 0xbe, 0xe9, 0x30, 0xb6,
++ 0x8e, 0xf5, 0x03, 0x5a, 0x80, 0xee, 0xd0, 0x7e, 0xc0, 0xb6, 0xec, 0x53,
++ 0xd9, 0x9a, 0xa5, 0xed, 0xa7, 0x63, 0xb6, 0x68, 0x3f, 0x60, 0x3b, 0xd6,
++ 0xc5, 0x73, 0xa4, 0xdc, 0xe4, 0xf3, 0x38, 0x60, 0x5d, 0xc0, 0xaf, 0x8d,
++ 0x36, 0xae, 0x19, 0xd8, 0x9f, 0xcf, 0x66, 0x5e, 0x27, 0xd7, 0x13, 0x7c,
++ 0x7e, 0x8f, 0x9d, 0xd3, 0xc7, 0xda, 0xb8, 0x00, 0xbe, 0x7f, 0x4b, 0xfd,
++ 0x4f, 0x6d, 0xbc, 0x06, 0x2d, 0x5c, 0x51, 0x0b, 0x6d, 0x6c, 0xe3, 0x79,
++ 0x01, 0xdf, 0xaf, 0x8d, 0x69, 0xa3, 0xf2, 0x7b, 0xfa, 0xf9, 0x9c, 0xf4,
++ 0x9b, 0xe2, 0x6c, 0xe5, 0xf9, 0x94, 0x1d, 0x8a, 0xb5, 0x52, 0x07, 0x6b,
++ 0xc7, 0x3a, 0x98, 0x44, 0xae, 0x18, 0xe1, 0xb8, 0x12, 0xba, 0xb6, 0x99,
++ 0x12, 0x6b, 0x62, 0xf8, 0xfc, 0xfa, 0x7f, 0xe9, 0x82, 0xc0, 0x23, 0x31,
++ 0x37, 0x6a, 0x0c, 0x3e, 0x0f, 0xf2, 0xfc, 0x8a, 0x8b, 0xfe, 0xaa, 0xd6,
++ 0x10, 0xd8, 0xf3, 0x59, 0xcb, 0x78, 0xa0, 0xbe, 0x73, 0xe6, 0xa1, 0x05,
++ 0xce, 0x01, 0x8f, 0xf3, 0x3d, 0x27, 0x40, 0x5b, 0x1b, 0xf1, 0x67, 0x4c,
++ 0x36, 0xa4, 0xf5, 0x7d, 0x83, 0xfd, 0xa0, 0xb3, 0x93, 0x6a, 0x2c, 0x1d,
++ 0x9a, 0x7a, 0x82, 0x13, 0xf3, 0x28, 0x1a, 0xc2, 0xa9, 0x23, 0x70, 0xfa,
++ 0xf0, 0x18, 0xa7, 0xa8, 0xc4, 0x29, 0x12, 0x38, 0xfd, 0xb1, 0xc4, 0xe9,
++ 0x0f, 0x4f, 0xc1, 0xe9, 0xc3, 0x67, 0xc0, 0xc9, 0xa0, 0x3d, 0xa7, 0x89,
++ 0x73, 0x56, 0x17, 0x35, 0xe9, 0xa1, 0x7b, 0x52, 0x4d, 0x75, 0x52, 0xdc,
++ 0x6d, 0x73, 0x8f, 0x86, 0xeb, 0x0e, 0xdb, 0x7a, 0x80, 0xf5, 0xa5, 0xc0,
++ 0xee, 0xfa, 0x58, 0xed, 0x91, 0xc0, 0xbe, 0x5d, 0xe2, 0x74, 0x1d, 0x38,
++ 0xb5, 0x4b, 0x9c, 0xb6, 0x87, 0x70, 0xda, 0x1e, 0xc1, 0x89, 0xf3, 0x49,
++ 0xcb, 0xd8, 0xee, 0x55, 0x18, 0x55, 0xf8, 0xe8, 0x74, 0xdb, 0x9c, 0xc6,
++ 0xfe, 0xcf, 0x51, 0xfa, 0x63, 0x95, 0xeb, 0x5a, 0x60, 0xf7, 0xaa, 0x2a,
++ 0x8b, 0xf3, 0x80, 0xdf, 0x9f, 0xd4, 0x27, 0x98, 0xcb, 0x0f, 0x5c, 0x8e,
++ 0x23, 0xea, 0x57, 0xa7, 0xca, 0x43, 0xcf, 0xab, 0xa8, 0xad, 0xf0, 0xcd,
++ 0x36, 0xaa, 0xd4, 0x86, 0xde, 0x15, 0xd4, 0xe5, 0xe1, 0x71, 0x5d, 0x5e,
++ 0xc4, 0xe0, 0x7a, 0x59, 0x97, 0xef, 0x39, 0x5c, 0x97, 0x2f, 0x6a, 0x34,
++ 0xb9, 0x51, 0x62, 0xc9, 0x9c, 0x9e, 0x42, 0xdf, 0x25, 0x81, 0x79, 0x8a,
++ 0xfc, 0xbd, 0x89, 0xfd, 0x47, 0x82, 0x9b, 0xa8, 0xb1, 0x4a, 0xde, 0xa2,
++ 0x86, 0xa5, 0x30, 0x2b, 0x62, 0xf5, 0xc5, 0xd6, 0x5d, 0x9f, 0x20, 0x4f,
++ 0x1b, 0x1d, 0x15, 0x75, 0xfd, 0xfd, 0x8c, 0xf3, 0x33, 0x5d, 0x4e, 0x7a,
++ 0x14, 0x9f, 0xf1, 0xae, 0xe5, 0xc0, 0xdc, 0x7f, 0xeb, 0x3c, 0x9f, 0x33,
++ 0xf5, 0xd5, 0xa0, 0x85, 0xf6, 0x81, 0x41, 0xa8, 0x7d, 0x70, 0x4f, 0xa1,
++ 0x38, 0x38, 0x2f, 0xa1, 0xc6, 0xc1, 0x37, 0x7c, 0x92, 0x6c, 0xb6, 0x23,
++ 0x7b, 0x4d, 0x70, 0x21, 0x26, 0x1f, 0xeb, 0xf4, 0x33, 0x71, 0x57, 0xe9,
++ 0x28, 0x9e, 0x81, 0xda, 0x92, 0x0c, 0x9c, 0xf3, 0x88, 0x89, 0x65, 0xa4,
++ 0x03, 0xd4, 0x41, 0x38, 0xfb, 0x83, 0x55, 0xc4, 0xe5, 0x2c, 0x70, 0xcb,
++ 0x54, 0xf8, 0xbe, 0xa9, 0x17, 0xf7, 0x1c, 0x54, 0x35, 0x22, 0x5e, 0x8f,
++ 0x4a, 0x7e, 0x88, 0x3a, 0x4b, 0x6a, 0xf7, 0xc9, 0x8a, 0x5c, 0xf0, 0x1c,
++ 0xe7, 0x48, 0x37, 0xe3, 0xda, 0xf9, 0xac, 0x21, 0xdf, 0xe0, 0x5c, 0x7e,
++ 0x88, 0x18, 0xe2, 0xfd, 0x80, 0xcf, 0x16, 0x85, 0xeb, 0x6f, 0xdc, 0x67,
++ 0x96, 0x90, 0x6b, 0x68, 0x0a, 0x79, 0x0f, 0x79, 0x77, 0x96, 0x71, 0xf2,
++ 0x23, 0xc6, 0x4b, 0x9c, 0x1b, 0xe7, 0xe4, 0x62, 0x9e, 0x5f, 0x6b, 0x05,
++ 0x7f, 0x71, 0x87, 0x41, 0xfc, 0x36, 0xfb, 0x2e, 0xe7, 0xdb, 0x2f, 0x2b,
++ 0x74, 0x44, 0x82, 0x8f, 0xe6, 0xcb, 0xc8, 0xc3, 0xe7, 0xe0, 0xe3, 0x0b,
++ 0x2d, 0x16, 0xf5, 0x56, 0xe5, 0xf3, 0xc9, 0xd8, 0x18, 0x1f, 0x29, 0xa3,
++ 0xdf, 0x3e, 0xf8, 0xbc, 0x52, 0xce, 0x57, 0xf1, 0xe3, 0x57, 0xe0, 0xc7,
++ 0x61, 0xd9, 0xcf, 0x77, 0x16, 0x1d, 0x36, 0xbc, 0x3e, 0xe6, 0x11, 0xdb,
++ 0x9b, 0xda, 0xe8, 0x18, 0x5f, 0x1a, 0xf3, 0xff, 0xfd, 0x90, 0xff, 0x34,
++ 0xef, 0xc9, 0x8c, 0x0a, 0x0e, 0xe2, 0xef, 0x3d, 0x7d, 0xd4, 0xf7, 0x17,
++ 0x6a, 0xf1, 0x7d, 0xb6, 0xe0, 0x9e, 0x83, 0x67, 0x76, 0x38, 0xb4, 0x36,
++ 0x75, 0x6c, 0xec, 0x87, 0x18, 0x7b, 0x15, 0x79, 0x84, 0x7c, 0x05, 0x77,
++ 0xa6, 0x90, 0xf0, 0x9e, 0x5d, 0xa9, 0xe2, 0x03, 0x4e, 0xd0, 0xe5, 0xb4,
++ 0xe4, 0x82, 0x5c, 0x70, 0x81, 0xeb, 0xb4, 0xd5, 0x4d, 0x70, 0x21, 0x05,
++ 0x17, 0xe0, 0xd7, 0xd1, 0xbc, 0x59, 0xe0, 0xcc, 0x39, 0x07, 0xdf, 0x19,
++ 0xf3, 0x82, 0x79, 0xc0, 0x9c, 0x78, 0xc2, 0x85, 0x2b, 0x3d, 0xc3, 0xd8,
++ 0xfd, 0x2f, 0x3c, 0x78, 0x57, 0xf0, 0x80, 0xf9, 0x58, 0xe4, 0x85, 0x2e,
++ 0x70, 0x48, 0xca, 0xbc, 0x50, 0xe8, 0x9c, 0xeb, 0x1b, 0xd6, 0x78, 0xa1,
++ 0x8d, 0x2d, 0x68, 0xa3, 0xad, 0x70, 0xbd, 0xc3, 0xba, 0x60, 0x3f, 0xd6,
++ 0xc6, 0x49, 0x7e, 0x85, 0x46, 0xd2, 0xbe, 0x6d, 0x55, 0xf9, 0x21, 0x85,
++ 0x2e, 0xba, 0xa5, 0x46, 0xd2, 0x52, 0x23, 0xb0, 0x89, 0x95, 0x16, 0xe7,
++ 0x7a, 0xdb, 0x0a, 0x91, 0x17, 0xba, 0x62, 0xcc, 0x98, 0x8a, 0x3b, 0x09,
++ 0xeb, 0x96, 0xf3, 0xe9, 0x50, 0x1e, 0x2d, 0xef, 0xa5, 0x1d, 0x71, 0x2f,
++ 0xfd, 0x8a, 0x3e, 0x9a, 0x47, 0x67, 0x90, 0x43, 0xf8, 0x5e, 0x3a, 0xa7,
++ 0xf3, 0xbd, 0x14, 0xba, 0xd3, 0x87, 0xef, 0xa5, 0xc9, 0xc8, 0xbd, 0xb4,
++ 0xf2, 0xe5, 0xf6, 0x93, 0xf2, 0x69, 0x15, 0x13, 0xce, 0xa9, 0x02, 0xf3,
++ 0x13, 0x6a, 0xbf, 0xca, 0x86, 0xf3, 0x0d, 0x6b, 0xb9, 0xcc, 0x51, 0xa8,
++ 0xb5, 0xee, 0x67, 0x15, 0xe7, 0xdf, 0xc0, 0x3c, 0xf8, 0xee, 0x9f, 0xc4,
++ 0x79, 0xa3, 0xe4, 0xfc, 0x54, 0xe1, 0xd3, 0x1f, 0xe6, 0xfd, 0x1b, 0xfa,
++ 0x28, 0xef, 0xab, 0x71, 0x2a, 0xde, 0x17, 0x63, 0x3e, 0x54, 0x9a, 0x38,
++ 0xdb, 0x96, 0x91, 0x6b, 0x66, 0xf8, 0xbe, 0x85, 0x5c, 0xe0, 0xd5, 0x71,
++ 0xef, 0x98, 0xe1, 0xb1, 0xd3, 0x0c, 0xe7, 0x4d, 0x03, 0xbc, 0x17, 0x9c,
++ 0x3d, 0x12, 0xf7, 0x01, 0xac, 0x7b, 0x86, 0xab, 0xab, 0x51, 0x2e, 0xbe,
++ 0x88, 0x0b, 0x45, 0xb5, 0x97, 0xaa, 0xcd, 0x19, 0x6a, 0x5b, 0x2e, 0xb1,
++ 0x2e, 0x62, 0xfd, 0xa0, 0xb8, 0x8f, 0xd3, 0x2e, 0x6a, 0xb1, 0x43, 0xd4,
++ 0x39, 0x77, 0x70, 0x9f, 0x4b, 0x06, 0x8f, 0xf2, 0x07, 0x0d, 0x95, 0xba,
++ 0xc7, 0x3e, 0x5d, 0xac, 0xd7, 0x36, 0x6f, 0xe3, 0xed, 0xdd, 0x41, 0x15,
++ 0x53, 0xee, 0xe7, 0xb6, 0x7f, 0xe0, 0xbc, 0x45, 0x1d, 0x37, 0x32, 0x67,
++ 0xf5, 0xce, 0x7f, 0xff, 0x06, 0x63, 0xe1, 0x4b, 0x7b, 0x30, 0x12, 0x00,
++ 0x00, 0x00 };
++
++static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
++static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
++
++static int bnx2_TXP_b06FwReleaseMajor = 0x1;
++static int bnx2_TXP_b06FwReleaseMinor = 0x0;
++static int bnx2_TXP_b06FwReleaseFix = 0x0;
++static u32 bnx2_TXP_b06FwStartAddr = 0x080034b0;
++static u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
++static int bnx2_TXP_b06FwTextLen = 0x5748;
++static u32 bnx2_TXP_b06FwDataAddr = 0x08005760;
++static int bnx2_TXP_b06FwDataLen = 0x0;
++static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
++static int bnx2_TXP_b06FwRodataLen = 0x0;
++static u32 bnx2_TXP_b06FwBssAddr = 0x080057a0;
++static int bnx2_TXP_b06FwBssLen = 0x1c4;
++static u32 bnx2_TXP_b06FwSbssAddr = 0x08005760;
++static int bnx2_TXP_b06FwSbssLen = 0x38;
++static u8 bnx2_TXP_b06FwText[] = {
++ 0x1f, 0x8b, 0x08, 0x08, 0x21, 0xd3, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65,
++ 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x6d, 0x6c,
++ 0x1b, 0xf7, 0x79, 0x7f, 0xee, 0x85, 0xd2, 0x51, 0x96, 0xe9, 0x93, 0xc2,
++ 0x78, 0x6c, 0xc0, 0xa6, 0x77, 0xd6, 0x51, 0x66, 0x20, 0xb5, 0xa0, 0x05,
++ 0x36, 0x55, 0x87, 0x43, 0x73, 0x3e, 0x52, 0x2f, 0x4e, 0x5c, 0x57, 0x71,
++ 0x94, 0x86, 0x6e, 0x0d, 0x8c, 0xa0, 0xec, 0xd8, 0xeb, 0x5a, 0x2c, 0x1f,
++ 0x8c, 0xd5, 0x68, 0xd1, 0x99, 0xa1, 0x68, 0xc7, 0xc9, 0x68, 0x51, 0xa9,
++ 0xe5, 0xa8, 0x43, 0x57, 0x80, 0x95, 0x64, 0xcb, 0x29, 0x4e, 0x3a, 0x65,
++ 0xcb, 0x16, 0x0c, 0x58, 0x16, 0xcd, 0x2f, 0x5d, 0x3f, 0x74, 0x80, 0x3f,
++ 0xec, 0x43, 0x3a, 0xec, 0x83, 0x91, 0x14, 0xad, 0x11, 0x6c, 0x59, 0xb0,
++ 0x2f, 0x33, 0xd6, 0x26, 0xb7, 0xdf, 0x73, 0x77, 0x94, 0x95, 0xc4, 0x4e,
++ 0xab, 0x7d, 0xbe, 0x07, 0x20, 0xee, 0x7f, 0xff, 0xd7, 0xe7, 0xfd, 0xe5,
++ 0x7f, 0x90, 0x06, 0xb7, 0x53, 0x17, 0x85, 0xb0, 0x1d, 0x3f, 0xed, 0x99,
++ 0x93, 0x27, 0x3e, 0xf7, 0xf9, 0xcf, 0x0d, 0xa1, 0x39, 0x4c, 0x4a, 0x4c,
++ 0xe4, 0xc1, 0x5b, 0x12, 0x51, 0xf9, 0x1d, 0x8a, 0x20, 0x82, 0x08, 0x22,
++ 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20,
++ 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08,
++ 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88,
++ 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82,
++ 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22, 0x88, 0x20, 0x82, 0x08, 0x22,
++ 0xf8, 0x9d, 0x20, 0x11, 0xa9, 0xfc, 0xdc, 0x1e, 0xfe, 0x48, 0x11, 0xcd,
++ 0xf2, 0x53, 0xb6, 0x41, 0x8a, 0x64, 0x1e, 0x39, 0x34, 0x65, 0x10, 0x59,
++ 0xce, 0x80, 0x56, 0xa0, 0xf7, 0xbd, 0x6a, 0x52, 0x26, 0xee, 0xff, 0xb4,
++ 0xf9, 0xdb, 0x53, 0xaf, 0x7f, 0x41, 0x7f, 0xaf, 0x25, 0x91, 0xa2, 0x9a,
++ 0x6b, 0x79, 0xb5, 0x9f, 0x94, 0x34, 0xd6, 0xfc, 0xd5, 0xee, 0xaf, 0xef,
++ 0xa0, 0x44, 0x7b, 0xaf, 0x24, 0xd5, 0x9b, 0xb7, 0xbc, 0xd7, 0x77, 0x27,
++ 0xe9, 0x15, 0x57, 0xa5, 0x35, 0x57, 0x16, 0x46, 0x9b, 0x0a, 0x4d, 0x37,
++ 0x1d, 0x3a, 0xdd, 0xa8, 0x52, 0xc1, 0xbd, 0x4c, 0xb5, 0x39, 0x35, 0x61,
++ 0x2f, 0xff, 0x84, 0xa6, 0xe7, 0x7a, 0x13, 0x85, 0x65, 0x87, 0x6a, 0x8d,
++ 0x54, 0xc2, 0x76, 0xd5, 0x44, 0x61, 0x3e, 0x89, 0xf7, 0xde, 0x84, 0x3d,
++ 0xaf, 0x57, 0x89, 0x76, 0x62, 0x4e, 0x2a, 0x51, 0x68, 0xea, 0x65, 0xa2,
++ 0xbe, 0xdc, 0x75, 0x4a, 0x27, 0x0a, 0xee, 0x82, 0xb0, 0xae, 0x0a, 0x54,
++ 0xfb, 0x2c, 0xa9, 0x09, 0xf3, 0xb6, 0xf7, 0x29, 0x43, 0xa5, 0x1e, 0x83,
++ 0x76, 0xec, 0x30, 0xe8, 0xd9, 0x94, 0xa9, 0x50, 0xe5, 0x7c, 0x9c, 0x2c,
++ 0x9f, 0x26, 0x95, 0x2a, 0xf3, 0x03, 0xea, 0x15, 0x8a, 0x91, 0x95, 0x6c,
++ 0xbf, 0x7b, 0x9e, 0x9d, 0xfb, 0x16, 0xff, 0x9d, 0x16, 0xce, 0xa2, 0xc4,
++ 0xa8, 0x4b, 0x64, 0x03, 0x2f, 0x3b, 0xf7, 0xbe, 0x17, 0xac, 0x51, 0x70,
++ 0xae, 0x9c, 0x18, 0x69, 0x7a, 0x5e, 0x31, 0x87, 0x33, 0x72, 0xed, 0xb5,
++ 0x31, 0x6a, 0x25, 0xad, 0xd6, 0x74, 0x2e, 0xbf, 0x23, 0xf8, 0x1b, 0x2f,
++ 0xa6, 0x91, 0xdf, 0x2d, 0x12, 0x8d, 0xaf, 0x50, 0x25, 0x49, 0xad, 0x5a,
++ 0xee, 0x61, 0x7a, 0x21, 0xd7, 0x4d, 0x67, 0xb1, 0xdf, 0xf3, 0x39, 0xf0,
++ 0xd1, 0x38, 0x29, 0xd8, 0xae, 0x9e, 0x22, 0xe1, 0x05, 0xb2, 0xe7, 0xfb,
++ 0xd4, 0x02, 0xe1, 0x6c, 0xc3, 0xfb, 0x8c, 0x9d, 0xc3, 0x79, 0x83, 0xff,
++ 0xeb, 0x59, 0x49, 0xbd, 0xdc, 0xa2, 0x14, 0xd5, 0x9a, 0x7d, 0xb9, 0x9f,
++ 0x93, 0x40, 0x9d, 0x06, 0xf3, 0xc7, 0xa3, 0xc7, 0x70, 0xae, 0x6d, 0xa0,
++ 0xdf, 0x25, 0x4b, 0xcc, 0xc4, 0xe8, 0x4f, 0x55, 0x5d, 0xb3, 0xa5, 0x5e,
++ 0xaa, 0x9d, 0xef, 0x04, 0x9e, 0x56, 0xaf, 0x88, 0xb9, 0x63, 0x79, 0x4a,
++ 0x6e, 0x23, 0x12, 0x24, 0x33, 0x83, 0x7d, 0x89, 0x6a, 0x4e, 0x0a, 0x6b,
++ 0x33, 0xc3, 0xef, 0xd0, 0x0e, 0xd2, 0x7a, 0x64, 0x9a, 0x76, 0xba, 0xc0,
++ 0xc7, 0x6e, 0xc8, 0x20, 0x33, 0xfc, 0x2e, 0x84, 0x22, 0x1a, 0x99, 0xd4,
++ 0x49, 0x2a, 0x0b, 0x05, 0xb7, 0x83, 0xa6, 0x33, 0x0a, 0xd5, 0x81, 0x47,
++ 0x3d, 0xf7, 0x35, 0xc1, 0x5e, 0x2e, 0x09, 0x85, 0x65, 0xcc, 0x73, 0x5f,
++ 0x0b, 0xff, 0x76, 0xad, 0x1b, 0xfb, 0x88, 0x54, 0xcb, 0x94, 0x30, 0xa6,
++ 0xd0, 0x14, 0xe6, 0x4d, 0x81, 0xa6, 0x69, 0x77, 0x07, 0xad, 0x4f, 0x26,
++ 0x13, 0xcc, 0xab, 0x1a, 0xc6, 0xbf, 0x32, 0x21, 0x90, 0x6a, 0x58, 0xf4,
++ 0xeb, 0x3c, 0x64, 0x38, 0xdf, 0xcb, 0x32, 0xa3, 0xd3, 0x4d, 0x4a, 0x8a,
++ 0x94, 0x49, 0x55, 0xe8, 0x32, 0x2d, 0x3a, 0x2c, 0x7f, 0xc8, 0x13, 0xf2,
++ 0xae, 0x39, 0xbc, 0x0e, 0x72, 0x6b, 0x16, 0xc1, 0x8f, 0x71, 0xe0, 0x70,
++ 0x50, 0x78, 0x6c, 0x71, 0x52, 0x18, 0x73, 0x7f, 0x93, 0xa0, 0xae, 0x93,
++ 0xc2, 0x01, 0xf7, 0xa8, 0x10, 0xf2, 0x1e, 0xb2, 0x53, 0xc8, 0x9a, 0x50,
++ 0xe8, 0x92, 0x1b, 0xc8, 0x6e, 0x01, 0xfa, 0x69, 0xa9, 0x16, 0xe4, 0x70,
++ 0x78, 0x63, 0x0e, 0x8f, 0xd5, 0x97, 0x65, 0x3a, 0xed, 0xf2, 0xfc, 0x3f,
++ 0x82, 0x7c, 0x14, 0x72, 0x76, 0x77, 0x53, 0x19, 0xfd, 0xb5, 0x79, 0xb2,
++ 0xec, 0x9c, 0x88, 0x35, 0x09, 0x92, 0x8c, 0x9d, 0xf8, 0x75, 0xd1, 0xd4,
++ 0x62, 0xa7, 0x25, 0x19, 0x49, 0x9a, 0x72, 0x99, 0x87, 0x78, 0x36, 0xdb,
++ 0x7c, 0x64, 0x5c, 0xb9, 0x9f, 0xd7, 0x71, 0xbf, 0x8a, 0xfe, 0xcd, 0x7d,
++ 0xac, 0x17, 0x09, 0xe0, 0xa3, 0x67, 0x59, 0x9f, 0x2b, 0xcd, 0x8c, 0x7a,
++ 0x80, 0x9f, 0x2e, 0xf3, 0xb6, 0xcd, 0x53, 0x19, 0x73, 0x45, 0xaa, 0x2c,
++ 0xe2, 0x9c, 0xf3, 0xbf, 0xf5, 0x62, 0x79, 0xbc, 0x1b, 0x1d, 0xa0, 0x8b,
++ 0xcf, 0x95, 0x81, 0x93, 0x48, 0xe5, 0x45, 0xde, 0x8b, 0xc7, 0x09, 0xb2,
++ 0xaf, 0xf5, 0x88, 0x94, 0x85, 0x7c, 0x75, 0x9c, 0x13, 0xc7, 0x9c, 0x6e,
++ 0xf0, 0x0f, 0xb4, 0x2e, 0xa3, 0x0d, 0xda, 0x45, 0x43, 0xc4, 0xfa, 0x4e,
++ 0x9a, 0xca, 0xb1, 0xbe, 0x30, 0x9e, 0xdb, 0xb0, 0x77, 0x9c, 0x8e, 0x9c,
++ 0x67, 0x7e, 0xc8, 0xf4, 0x3c, 0x70, 0x9c, 0x9e, 0xd7, 0xd5, 0x22, 0xe9,
++ 0xe0, 0x8d, 0x85, 0x79, 0x9d, 0x54, 0x56, 0x3d, 0x6f, 0x24, 0x37, 0xa0,
++ 0xbe, 0xec, 0xeb, 0xf9, 0x80, 0x9a, 0x11, 0xa8, 0xda, 0x61, 0xfe, 0x21,
++ 0x70, 0xd0, 0x4b, 0x44, 0xfc, 0xfe, 0xcf, 0x64, 0x4d, 0xb2, 0xfd, 0x24,
++ 0xf9, 0x2c, 0xd8, 0xd3, 0x4e, 0xe0, 0xcf, 0x36, 0x97, 0x86, 0x5c, 0x52,
++ 0xbe, 0x1d, 0x8c, 0xdc, 0xd5, 0x0e, 0xf4, 0xf1, 0x16, 0x6c, 0xa6, 0xb6,
++ 0x2c, 0xb3, 0xfd, 0xe5, 0xa0, 0x6e, 0xb4, 0xcd, 0x80, 0x6e, 0xf9, 0xb2,
++ 0xd9, 0x8f, 0xfd, 0x3d, 0xef, 0xcb, 0xb9, 0x00, 0xa7, 0xda, 0xbc, 0x85,
++ 0xb5, 0x32, 0xf8, 0xae, 0x1f, 0xd7, 0xfc, 0xf3, 0xf7, 0x87, 0xe7, 0xab,
++ 0x34, 0x05, 0xbc, 0x6b, 0x4d, 0x89, 0x0a, 0x2a, 0xef, 0xf1, 0x2e, 0xf7,
++ 0x97, 0x83, 0xbd, 0xa0, 0xb7, 0xe7, 0xfa, 0xd4, 0x7d, 0xb0, 0x25, 0xb6,
++ 0xb1, 0xda, 0x0a, 0xf3, 0x18, 0xfb, 0xe4, 0x99, 0xc7, 0xaa, 0x8f, 0xa3,
++ 0x3d, 0xcf, 0x7a, 0x44, 0x69, 0x89, 0x58, 0xcf, 0x2f, 0xb3, 0x2e, 0x41,
++ 0x3f, 0x03, 0xbd, 0xaa, 0x38, 0x2c, 0xff, 0x2f, 0x85, 0xf6, 0x29, 0x52,
++ 0x7f, 0x86, 0xf5, 0xfd, 0x05, 0x2a, 0xc0, 0xc6, 0xa7, 0x70, 0xd2, 0x22,
++ 0x68, 0x5a, 0x68, 0xf6, 0x81, 0x57, 0x6d, 0xbb, 0x83, 0x7c, 0x07, 0xff,
++ 0xc7, 0x0b, 0xe6, 0x77, 0x03, 0x27, 0xb6, 0x99, 0x9a, 0x2a, 0x52, 0x15,
++ 0x3f, 0xe8, 0x8d, 0xa1, 0x67, 0x6d, 0x49, 0x9f, 0x28, 0x03, 0x37, 0xe8,
++ 0x3d, 0xd9, 0x7b, 0x58, 0x9f, 0x31, 0xc7, 0xa5, 0xa1, 0xb6, 0x9d, 0x2d,
++ 0x38, 0x2c, 0xa7, 0x2e, 0x9c, 0xdb, 0xc6, 0x49, 0x46, 0x1f, 0xef, 0xa3,
++ 0x40, 0xe7, 0xdb, 0x3a, 0xc3, 0xfa, 0xa7, 0x5b, 0xeb, 0xd4, 0x41, 0xd9,
++ 0x0c, 0x7c, 0xd9, 0xbc, 0x08, 0xf9, 0xa5, 0xe1, 0x53, 0x64, 0x7a, 0xba,
++ 0x99, 0xa4, 0x63, 0x4d, 0xc6, 0xaf, 0x08, 0xbb, 0x83, 0x6f, 0x9b, 0x1f,
++ 0x85, 0x9d, 0x8d, 0x0b, 0x23, 0xb0, 0x89, 0x47, 0x17, 0x19, 0x27, 0x8f,
++ 0xd8, 0x2e, 0x8b, 0xcb, 0x65, 0x61, 0xd4, 0x2d, 0x09, 0xe3, 0xcb, 0x6c,
++ 0x27, 0x6c, 0x23, 0xba, 0xfa, 0x38, 0x31, 0x0d, 0x98, 0xe3, 0xfe, 0x22,
++ 0xc1, 0xb6, 0x5a, 0x3b, 0x17, 0x07, 0x1e, 0xdb, 0x80, 0x4f, 0x37, 0x6c,
++ 0x0f, 0xfa, 0x65, 0xe8, 0x13, 0xac, 0x33, 0xc5, 0x8c, 0xa1, 0xfd, 0x25,
++ 0x7d, 0x9c, 0x0f, 0x23, 0x1b, 0x7c, 0x18, 0x00, 0x4f, 0x3e, 0xcc, 0x87,
++ 0xfa, 0xc7, 0xf9, 0x60, 0x55, 0xc1, 0x87, 0x3a, 0xfc, 0x50, 0xdd, 0x65,
++ 0x9a, 0x3d, 0x12, 0xf7, 0x10, 0xb4, 0x93, 0xf6, 0x8a, 0x26, 0xeb, 0x28,
++ 0xdb, 0x49, 0x46, 0x9b, 0xc6, 0x0e, 0x4b, 0x4e, 0xb7, 0x6f, 0x1b, 0xa3,
++ 0x3e, 0x2f, 0x7e, 0x17, 0xbd, 0x4c, 0xdf, 0x1d, 0x9a, 0xc7, 0x17, 0xd9,
++ 0xdf, 0x40, 0xcf, 0x33, 0x86, 0x7a, 0x88, 0xee, 0xd0, 0xbd, 0xef, 0x0e,
++ 0xdd, 0x38, 0xa7, 0xed, 0x83, 0x98, 0xe6, 0xb6, 0x3f, 0x66, 0x5d, 0x79,
++ 0xc3, 0x93, 0x0c, 0x03, 0x32, 0x60, 0x7d, 0x61, 0x1c, 0x74, 0xf5, 0xcb,
++ 0xa0, 0xa7, 0x02, 0xbf, 0xc0, 0xb6, 0x54, 0xf6, 0xe7, 0x75, 0x50, 0xb9,
++ 0x27, 0x98, 0x3f, 0xd5, 0xf4, 0xfe, 0x4b, 0x34, 0x3f, 0xf0, 0xec, 0xbc,
++ 0x11, 0xda, 0xb8, 0x42, 0x7f, 0xb2, 0xa8, 0x97, 0x35, 0xa1, 0x9b, 0xaa,
++ 0xf7, 0xc3, 0xaf, 0x34, 0xd9, 0x3e, 0x76, 0xde, 0xc3, 0x97, 0xa5, 0x43,
++ 0x5f, 0xf6, 0x3e, 0x78, 0xcf, 0xb1, 0xe7, 0xe8, 0x07, 0xeb, 0x49, 0x7e,
++ 0x66, 0xd4, 0x09, 0x2a, 0x71, 0xbc, 0xd9, 0x21, 0xfa, 0xfe, 0xbb, 0x8f,
++ 0x63, 0x41, 0x55, 0x36, 0xe3, 0x54, 0xed, 0xa1, 0xaa, 0x64, 0xb2, 0x1d,
++ 0xb1, 0x6d, 0xb4, 0xf1, 0xde, 0x1e, 0xc6, 0xdd, 0x41, 0x89, 0x0c, 0x1e,
++ 0x47, 0x8c, 0x68, 0x32, 0x0d, 0xef, 0x87, 0xf2, 0x60, 0x7f, 0x4a, 0xb1,
++ 0x40, 0xdf, 0xf6, 0xc3, 0x5f, 0x32, 0x3f, 0x37, 0xeb, 0x0a, 0xfb, 0x51,
++ 0xd2, 0x44, 0x83, 0xfd, 0x28, 0xa9, 0x92, 0x79, 0x50, 0xb0, 0x16, 0xbf,
++ 0x26, 0x58, 0xe0, 0x9b, 0x05, 0xbe, 0x59, 0xe0, 0x9b, 0x0d, 0xbe, 0x15,
++ 0x5c, 0xc6, 0x85, 0xf1, 0x08, 0xf6, 0x2f, 0x06, 0xfb, 0x03, 0xc7, 0x9d,
++ 0x54, 0xf1, 0xed, 0x9b, 0x69, 0x85, 0x3f, 0xf6, 0x7d, 0xc1, 0xa8, 0x10,
++ 0xf8, 0x02, 0xde, 0x6f, 0x1c, 0xeb, 0x1f, 0x47, 0x8c, 0xb3, 0x44, 0xd1,
++ 0xb8, 0xc3, 0x8f, 0xfa, 0x26, 0x7e, 0x4c, 0x3b, 0xcc, 0x1f, 0x9e, 0xcf,
++ 0x76, 0xec, 0x40, 0xe6, 0x6d, 0x9e, 0xec, 0x07, 0x0e, 0x9d, 0x4c, 0x77,
++ 0x48, 0x07, 0xef, 0xdf, 0x1b, 0xee, 0x7f, 0x00, 0x7b, 0xb2, 0xdd, 0xde,
++ 0xed, 0x5c, 0x3e, 0x93, 0xe3, 0xe8, 0x27, 0xd1, 0x83, 0x3c, 0x02, 0x7e,
++ 0x66, 0x0d, 0x76, 0x76, 0x53, 0x4a, 0xd1, 0xeb, 0xbb, 0x6f, 0x20, 0xb7,
++ 0xa0, 0xea, 0x03, 0xa6, 0xa7, 0xc9, 0xe6, 0xfb, 0x5e, 0x3d, 0x0f, 0xdf,
++ 0x69, 0xea, 0x29, 0x5b, 0x1a, 0xa4, 0x37, 0xdc, 0x2c, 0xfd, 0x9d, 0x6b,
++ 0xd0, 0xdf, 0xba, 0x1a, 0xbd, 0xea, 0xa6, 0xe9, 0x6f, 0xdc, 0x14, 0xfd,
++ 0xb5, 0xdb, 0xce, 0x43, 0x92, 0xac, 0x47, 0x89, 0xa2, 0x7b, 0xb7, 0x5c,
++ 0x08, 0x3a, 0x8e, 0xbd, 0xec, 0xbc, 0x5c, 0x96, 0x4d, 0x3f, 0x3f, 0x98,
++ 0x98, 0x6e, 0x90, 0xb2, 0xd3, 0xa0, 0xed, 0xf7, 0x23, 0xef, 0x49, 0x9a,
++ 0xb4, 0xe3, 0x3e, 0x3c, 0x7b, 0x4d, 0xb2, 0x7a, 0xcc, 0x53, 0x9e, 0x68,
++ 0xb0, 0x1e, 0x75, 0x0f, 0x4f, 0xe5, 0xe3, 0x8c, 0xfb, 0xc4, 0x34, 0xfc,
++ 0x91, 0x8d, 0xb3, 0xaa, 0xd0, 0xc5, 0xaa, 0x7b, 0xe8, 0xfe, 0x20, 0x17,
++ 0x7a, 0x2f, 0xcc, 0x89, 0x38, 0xaf, 0x5a, 0x7f, 0x6a, 0xc2, 0x60, 0x3f,
++ 0x2b, 0x6c, 0xf2, 0xb3, 0x24, 0x14, 0x41, 0x53, 0x1d, 0xb8, 0x16, 0x41,
++ 0xe7, 0x57, 0x5d, 0x45, 0x28, 0x9c, 0xef, 0xa5, 0xe9, 0x45, 0x8e, 0x55,
++ 0x3c, 0x4f, 0x09, 0x73, 0x19, 0x7e, 0xef, 0xc0, 0x3b, 0x21, 0x7e, 0x14,
++ 0xb6, 0x53, 0x42, 0x7f, 0x73, 0x82, 0x9c, 0x30, 0x17, 0x89, 0xd1, 0x05,
++ 0x5f, 0x77, 0xb8, 0xdf, 0x2a, 0xfd, 0xb0, 0xff, 0x4e, 0xff, 0xf9, 0x8d,
++ 0xfe, 0x72, 0xe9, 0xeb, 0x1b, 0xfd, 0xef, 0xa8, 0x01, 0x4e, 0xc3, 0xc2,
++ 0xe3, 0xee, 0xf3, 0x61, 0xdf, 0x6d, 0xf0, 0xd3, 0xf3, 0xea, 0x88, 0x27,
++ 0x35, 0xe3, 0x36, 0x72, 0x1f, 0xf6, 0x29, 0x5b, 0xf1, 0x21, 0x1f, 0xf2,
++ 0x1f, 0xaa, 0x2d, 0xb1, 0x9c, 0x14, 0x0a, 0xf6, 0xe4, 0xf1, 0x4e, 0xf8,
++ 0x92, 0xdb, 0x68, 0x73, 0xec, 0x6a, 0xfb, 0x31, 0x9e, 0xc3, 0xeb, 0x6f,
++ 0xdd, 0x43, 0x96, 0x2a, 0x64, 0xb9, 0x35, 0x79, 0xd5, 0x1a, 0xa7, 0x42,
++ 0x9f, 0xd0, 0x3d, 0x6c, 0x43, 0x2e, 0x12, 0xe4, 0x52, 0x83, 0x5c, 0x0a,
++ 0xf7, 0x94, 0x0b, 0xce, 0xd8, 0xd0, 0x29, 0xc6, 0xa3, 0x2b, 0x3c, 0x9b,
++ 0x14, 0xd9, 0xac, 0x96, 0xea, 0xc6, 0xa7, 0x28, 0x66, 0x30, 0x1e, 0x06,
++ 0xf0, 0x38, 0x8a, 0xb5, 0x1c, 0xc3, 0x48, 0x89, 0x99, 0x2c, 0xcf, 0xdc,
++ 0x13, 0xb6, 0x71, 0xab, 0xb4, 0xe0, 0xdc, 0x2a, 0x5d, 0x34, 0xf8, 0xfd,
++ 0xf6, 0x64, 0x90, 0x37, 0x77, 0x3f, 0x89, 0xbc, 0x19, 0xeb, 0xd9, 0x1f,
++ 0x72, 0xff, 0x30, 0xe6, 0x71, 0x7c, 0xa0, 0x43, 0x35, 0xfc, 0xea, 0xfe,
++ 0xdc, 0x6b, 0x4f, 0xf0, 0xdc, 0x4e, 0x53, 0x9e, 0xfc, 0x35, 0x9e, 0x1d,
++ 0xa6, 0xf6, 0xe4, 0x4f, 0x0d, 0xde, 0x77, 0x78, 0xf2, 0xa2, 0xbf, 0x07,
++ 0x62, 0xa6, 0xbf, 0x36, 0xfb, 0x24, 0xaf, 0x7d, 0x0e, 0x3e, 0xf6, 0x0c,
++ 0xe2, 0xcb, 0x69, 0x47, 0x3b, 0x54, 0xc1, 0x6f, 0x8a, 0x71, 0x6a, 0xf2,
++ 0xb8, 0x85, 0x71, 0x19, 0xb1, 0x90, 0xdb, 0x0a, 0x1d, 0xc3, 0xbc, 0xa7,
++ 0x31, 0xef, 0xa8, 0x33, 0x8e, 0xbc, 0xbd, 0x4d, 0xd7, 0xbf, 0xc5, 0x0b,
++ 0xf3, 0xec, 0xcf, 0x91, 0xed, 0xaf, 0xfc, 0x7b, 0xdc, 0x86, 0x5f, 0x16,
++ 0x57, 0x6e, 0xc6, 0x0b, 0xa0, 0x5b, 0x5a, 0xf9, 0x45, 0xbc, 0x08, 0x3d,
++ 0x13, 0x0d, 0x09, 0x7e, 0xf9, 0x33, 0x54, 0x53, 0x3d, 0x7a, 0x19, 0xf1,
++ 0xab, 0x96, 0x85, 0xbf, 0x82, 0x34, 0x45, 0x03, 0x7e, 0x4c, 0x25, 0xa5,
++ 0xcb, 0x3c, 0xa9, 0x52, 0x57, 0x3e, 0x6e, 0x23, 0xde, 0xd4, 0x54, 0x09,
++ 0xfd, 0xfd, 0x78, 0x6e, 0xee, 0xff, 0x65, 0x1c, 0x7e, 0x0b, 0x3e, 0x82,
++ 0x14, 0x3b, 0xdf, 0x8d, 0xfd, 0xbf, 0x8d, 0x7e, 0x4c, 0xc8, 0x6c, 0xf4,
++ 0x3f, 0x1b, 0xf4, 0xdf, 0x02, 0x2e, 0xbc, 0x8e, 0xe3, 0x27, 0x29, 0x53,
++ 0x79, 0x15, 0x38, 0xf0, 0xdc, 0xa4, 0x3f, 0xb7, 0x38, 0xcf, 0x3c, 0xa8,
++ 0x96, 0x16, 0x8c, 0x34, 0x15, 0xe6, 0x92, 0x34, 0x3a, 0xa7, 0xd2, 0xd8,
++ 0x9c, 0x3e, 0xd1, 0x62, 0xfb, 0x01, 0xcd, 0x84, 0x1c, 0x41, 0x5c, 0x21,
++ 0x50, 0xac, 0xa7, 0x9e, 0xa6, 0xbe, 0xd4, 0x31, 0xfa, 0x6f, 0x0f, 0xb1,
++ 0x08, 0x71, 0xa8, 0x9b, 0x64, 0x7f, 0x9f, 0x54, 0xfb, 0x4c, 0x96, 0xd1,
++ 0x87, 0xce, 0x2d, 0xce, 0xdf, 0x6b, 0x5f, 0x28, 0xf1, 0x4a, 0xea, 0x23,
++ 0xfb, 0xbe, 0x1b, 0xee, 0xab, 0x62, 0xdf, 0x34, 0xf6, 0x64, 0x1a, 0xf5,
++ 0xf8, 0xc8, 0x79, 0xb2, 0x3a, 0x81, 0x5f, 0x31, 0x83, 0x98, 0x8f, 0x7d,
++ 0xce, 0xcc, 0xb1, 0xde, 0xd3, 0x4e, 0xfc, 0x06, 0x63, 0x94, 0xc9, 0x2e,
++ 0x23, 0x27, 0x18, 0xf1, 0xf7, 0x08, 0xf2, 0x05, 0x71, 0x65, 0x10, 0xf9,
++ 0xda, 0x3b, 0xc0, 0x87, 0xe3, 0x18, 0xd3, 0x2c, 0x83, 0xde, 0x41, 0xe4,
++ 0x09, 0x9c, 0xe3, 0x7b, 0xa7, 0xec, 0x1c, 0xda, 0xcb, 0x5a, 0xbc, 0x00,
++ 0xdb, 0x16, 0x4d, 0x7a, 0x50, 0xf2, 0x7d, 0x2c, 0xcb, 0x65, 0x10, 0x72,
++ 0x62, 0xbc, 0x73, 0x90, 0x13, 0xf3, 0x68, 0x38, 0x5e, 0x6c, 0x32, 0x8f,
++ 0x08, 0xf8, 0x68, 0xb0, 0x27, 0xd9, 0xcf, 0xf3, 0xc5, 0x15, 0x0b, 0xf3,
++ 0x7e, 0xac, 0x72, 0x2e, 0x66, 0x1b, 0xdc, 0x86, 0xed, 0xac, 0x8c, 0x63,
++ 0x2e, 0xb7, 0x1f, 0xc6, 0xbe, 0x7d, 0xb9, 0x1a, 0x75, 0xe4, 0x9e, 0x86,
++ 0xdd, 0x8a, 0xf9, 0x01, 0xc4, 0x68, 0x01, 0xb9, 0xa0, 0xe7, 0x75, 0xe4,
++ 0xbf, 0x00, 0x7a, 0x98, 0x0e, 0xe8, 0xf5, 0x2c, 0xf3, 0x95, 0xfe, 0x40,
++ 0xe4, 0x5c, 0x2d, 0xdf, 0xce, 0x6b, 0x38, 0x9e, 0xf3, 0xf9, 0x88, 0x23,
++ 0x8d, 0x3d, 0x88, 0xa5, 0xfe, 0xd9, 0xd0, 0xb1, 0x71, 0x2a, 0x34, 0x3e,
++ 0x8b, 0x9c, 0x93, 0x6d, 0x67, 0x9b, 0x60, 0x9f, 0x67, 0x1a, 0x09, 0xb1,
++ 0x66, 0x8d, 0x2a, 0x0d, 0x39, 0x6c, 0xbf, 0x8a, 0xb6, 0x12, 0xb6, 0xd7,
++ 0xd1, 0xee, 0x0e, 0xdb, 0xd7, 0xd0, 0x56, 0xc3, 0xf6, 0xcf, 0xd0, 0x4e,
++ 0x86, 0xed, 0x9f, 0xa3, 0x9d, 0x0a, 0xdb, 0x37, 0xd1, 0x4e, 0x87, 0xed,
++ 0x5b, 0x68, 0x6b, 0x61, 0xfb, 0x3d, 0xb4, 0x13, 0xb0, 0x73, 0x03, 0xef,
++ 0x37, 0x50, 0x2b, 0x66, 0xf1, 0xfc, 0x57, 0xe0, 0x36, 0x08, 0xde, 0x64,
++ 0xc1, 0x8f, 0x5e, 0x8c, 0xe5, 0xd0, 0x87, 0x1c, 0xb1, 0x91, 0xc7, 0xd3,
++ 0xc1, 0x18, 0x95, 0x61, 0x7b, 0x18, 0x1f, 0x2f, 0x16, 0x1a, 0x26, 0x9e,
++ 0x6c, 0x0f, 0xba, 0x4a, 0xc2, 0x65, 0xd8, 0xb9, 0xef, 0x63, 0x72, 0xb6,
++ 0x34, 0x09, 0xdb, 0x9e, 0xa0, 0x7f, 0x74, 0xf7, 0xd3, 0x6b, 0xee, 0x38,
++ 0xe2, 0x46, 0x11, 0x71, 0xc3, 0x42, 0xdc, 0x30, 0x11, 0x37, 0x86, 0x11,
++ 0x37, 0xf2, 0x88, 0x1b, 0x39, 0xc4, 0x0d, 0xa2, 0x33, 0x7e, 0x8c, 0x4a,
++ 0x2a, 0xa8, 0x51, 0x15, 0xcb, 0x2d, 0x82, 0xbf, 0x13, 0x90, 0xcd, 0x24,
++ 0x78, 0x7d, 0x38, 0x3e, 0xd2, 0xcc, 0xc3, 0x9f, 0x69, 0xf0, 0x11, 0x69,
++ 0xf8, 0xf2, 0x1c, 0x6a, 0x13, 0xa2, 0x2b, 0xb3, 0x1a, 0xfc, 0x8f, 0x47,
++ 0x45, 0xc4, 0xfe, 0x69, 0x15, 0xb8, 0x19, 0xbb, 0x7c, 0x9b, 0x91, 0xcc,
++ 0x2f, 0xf6, 0x50, 0xd7, 0x20, 0xe8, 0x39, 0x8b, 0xbe, 0x14, 0xf6, 0x63,
++ 0xbe, 0xde, 0x2a, 0xd9, 0x86, 0x46, 0x0b, 0x6e, 0x1c, 0xfe, 0x9f, 0xdf,
++ 0xe3, 0xcc, 0xe3, 0x43, 0x4f, 0x19, 0x4c, 0x03, 0xea, 0x3c, 0x23, 0xad,
++ 0x14, 0x1c, 0x81, 0x24, 0x93, 0x9f, 0xed, 0x1c, 0xe2, 0xcf, 0x90, 0x43,
++ 0x74, 0x41, 0x06, 0x55, 0xc4, 0x05, 0x9d, 0xf3, 0x0b, 0xe8, 0xf2, 0x27,
++ 0xcd, 0xff, 0x1e, 0xe6, 0xef, 0xc5, 0xd9, 0x3c, 0x8f, 0xcf, 0x39, 0x85,
++ 0xfa, 0xc1, 0xea, 0x91, 0x68, 0x3d, 0x25, 0xa1, 0x9e, 0x28, 0xd0, 0x59,
++ 0x2a, 0x00, 0x9f, 0x82, 0xdb, 0xbe, 0x07, 0xb0, 0x0e, 0x05, 0xfe, 0x6c,
++ 0xe2, 0xd0, 0xb7, 0x0d, 0x0b, 0xeb, 0x18, 0x3f, 0xd6, 0x5b, 0xe0, 0xbe,
++ 0xb1, 0xe7, 0x05, 0xec, 0xf9, 0x4f, 0x49, 0xea, 0x9a, 0x0c, 0xfc, 0x91,
++ 0x5f, 0xf3, 0xca, 0xc2, 0x48, 0xf3, 0x2c, 0xf8, 0xd3, 0x87, 0x1a, 0x05,
++ 0x7e, 0xa4, 0xd4, 0x02, 0x9f, 0xda, 0xf3, 0x5f, 0xc1, 0x7c, 0x7e, 0xf7,
++ 0xef, 0x0e, 0x4a, 0xd2, 0xea, 0x12, 0xe6, 0x69, 0xac, 0x3f, 0x25, 0xb9,
++ 0xff, 0x86, 0xf7, 0xa2, 0x91, 0xa7, 0x5d, 0xab, 0xbc, 0x2e, 0x4b, 0x7d,
++ 0xab, 0x37, 0xbc, 0x9a, 0xa3, 0xd1, 0x62, 0x93, 0xc0, 0xab, 0xf8, 0x6d,
++ 0x8b, 0xf4, 0x35, 0x12, 0xf5, 0x59, 0x0b, 0x7a, 0x5a, 0x1c, 0x12, 0xc9,
++ 0x1e, 0xea, 0x84, 0x8f, 0x32, 0x68, 0x09, 0x7c, 0xdf, 0x35, 0x63, 0xd1,
++ 0x13, 0x43, 0xed, 0x7c, 0x10, 0x51, 0x0f, 0xb8, 0xee, 0x5a, 0xd5, 0x30,
++ 0x87, 0x73, 0x71, 0xa6, 0x45, 0x03, 0x2f, 0x85, 0x60, 0x8d, 0x1f, 0xb3,
++ 0xb8, 0x8e, 0x05, 0xdf, 0xdc, 0xb5, 0xd2, 0xd5, 0x19, 0xd4, 0x1a, 0x90,
++ 0xf3, 0xae, 0x19, 0xae, 0x85, 0xb6, 0x81, 0x2f, 0x31, 0xd8, 0x06, 0xe7,
++ 0xf1, 0x08, 0xf4, 0xf0, 0x87, 0x27, 0xe0, 0xf1, 0x6b, 0xcd, 0x13, 0xd0,
++ 0xfb, 0x2e, 0x2a, 0xcb, 0x3e, 0x11, 0x9f, 0xc0, 0xe3, 0xff, 0xe4, 0xbc,
++ 0x0e, 0xf3, 0xbf, 0x4b, 0xc5, 0xd9, 0x2e, 0xec, 0xb5, 0x9b, 0xa6, 0x93,
++ 0x8c, 0x9b, 0x3e, 0x8c, 0x41, 0x2d, 0x06, 0x7e, 0xc6, 0xcd, 0x8f, 0xe6,
++ 0x7d, 0x6b, 0xa5, 0x2b, 0x33, 0x6b, 0xa5, 0x6b, 0xa0, 0xbf, 0x6e, 0x70,
++ 0x8d, 0x0c, 0x5d, 0x6a, 0x70, 0x6d, 0xcf, 0x79, 0xd1, 0x18, 0x74, 0x64,
++ 0xbf, 0x5f, 0x33, 0xdb, 0x8b, 0x39, 0xea, 0x3b, 0x47, 0xaa, 0x68, 0x96,
++ 0x84, 0x31, 0xe4, 0x45, 0x23, 0xee, 0x49, 0x7f, 0xee, 0x99, 0x06, 0xd7,
++ 0x2b, 0x18, 0x5b, 0x61, 0x5d, 0x18, 0x03, 0x3e, 0x49, 0xba, 0xe8, 0xb2,
++ 0x4f, 0x0a, 0xec, 0x78, 0x0c, 0xfc, 0x5a, 0xf0, 0xe9, 0x4a, 0x71, 0x1c,
++ 0x47, 0xbe, 0xc1, 0xf2, 0xf9, 0x21, 0xc7, 0x41, 0xa1, 0xd3, 0x6c, 0xfb,
++ 0xdb, 0x89, 0x5e, 0xe6, 0x59, 0xa1, 0x01, 0xdf, 0x3f, 0x34, 0x11, 0xe6,
++ 0x1c, 0x7f, 0x8f, 0x39, 0x8c, 0x3b, 0xcd, 0x4a, 0x26, 0xce, 0xc8, 0x33,
++ 0xcf, 0x38, 0xa7, 0xe4, 0x7d, 0xc1, 0x5b, 0xf0, 0x7d, 0x53, 0x6e, 0xe9,
++ 0xc3, 0x74, 0x33, 0x46, 0x95, 0x59, 0xf0, 0x2e, 0x8f, 0x27, 0x9c, 0x6b,
++ 0x1d, 0x7c, 0x03, 0x2d, 0xd5, 0x20, 0x9f, 0x3d, 0xc1, 0x31, 0x0d, 0xfe,
++ 0x06, 0x36, 0xcd, 0x31, 0x6b, 0xe3, 0xde, 0xc9, 0xf7, 0x25, 0x32, 0x19,
++ 0x41, 0xce, 0x2a, 0xe2, 0x2c, 0x3b, 0xcf, 0x7e, 0x10, 0xf8, 0xb8, 0xdf,
++ 0xa5, 0xfa, 0x2c, 0xd3, 0x05, 0x1b, 0x4f, 0xb2, 0x2e, 0xfe, 0x7f, 0xf9,
++ 0x38, 0xba, 0x45, 0x3e, 0x8e, 0x6e, 0x99, 0x8f, 0x12, 0xf8, 0x58, 0xd9,
++ 0xe0, 0xa3, 0x82, 0x3d, 0xf8, 0x3e, 0xe1, 0xab, 0x64, 0x4d, 0x3c, 0x02,
++ 0x3f, 0x0c, 0xff, 0xd1, 0x3c, 0x05, 0x9f, 0x70, 0x52, 0xb8, 0xda, 0xf0,
++ 0x68, 0x1c, 0xb5, 0xb2, 0x74, 0xff, 0x66, 0xfa, 0x33, 0xa0, 0xff, 0xcf,
++ 0x31, 0x5e, 0xa5, 0x6b, 0xb3, 0x94, 0x56, 0xa8, 0x7d, 0x2e, 0xed, 0x92,
++ 0xe9, 0x3b, 0x74, 0x75, 0xb6, 0x8b, 0xae, 0xcf, 0x66, 0xc0, 0xeb, 0x2c,
++ 0xc5, 0x7a, 0x32, 0xc3, 0x15, 0x18, 0xf1, 0xcf, 0x5a, 0xba, 0xc5, 0xba,
++ 0xf8, 0xfb, 0xf3, 0x82, 0xf9, 0x70, 0xd0, 0xe7, 0xc3, 0xd8, 0x47, 0xf8,
++ 0x30, 0x7e, 0x4f, 0x3e, 0x1c, 0xfc, 0x18, 0x1f, 0xc6, 0x3f, 0xc6, 0x07,
++ 0xe6, 0x01, 0xf3, 0xe2, 0xd1, 0xde, 0xf0, 0xff, 0x1f, 0x7d, 0x82, 0x7d,
++ 0x7c, 0x09, 0x74, 0x22, 0xa7, 0xd8, 0x19, 0xe4, 0x50, 0x9c, 0x63, 0xd5,
++ 0x0c, 0xe6, 0x57, 0x60, 0xbf, 0x32, 0x72, 0xea, 0x23, 0xa1, 0xfd, 0x16,
++ 0x1c, 0xe8, 0x65, 0x23, 0xe6, 0xdb, 0xaf, 0x64, 0xe6, 0xe1, 0x03, 0xaa,
++ 0xa5, 0x96, 0xc3, 0xfe, 0x07, 0x6d, 0x87, 0x79, 0xda, 0x0b, 0x5a, 0x12,
++ 0x54, 0x99, 0x54, 0x10, 0x5f, 0x87, 0xa1, 0xb7, 0x71, 0xdf, 0x07, 0x4a,
++ 0x26, 0xeb, 0xe1, 0x7e, 0xcc, 0x3f, 0x1c, 0xe6, 0x45, 0x88, 0x73, 0x38,
++ 0xa3, 0xd6, 0x38, 0x0d, 0xfc, 0xf8, 0x9c, 0x6a, 0xa9, 0xec, 0xf0, 0x9a,
++ 0x34, 0x62, 0x21, 0x3f, 0x37, 0xeb, 0xb7, 0xaf, 0xef, 0xf7, 0xd2, 0x71,
++ 0xe8, 0x26, 0xeb, 0xb4, 0x82, 0xdc, 0x78, 0x02, 0xf1, 0xc5, 0xd7, 0xd3,
++ 0xec, 0x02, 0xb1, 0xdf, 0x7f, 0x06, 0x75, 0xd1, 0x61, 0xfc, 0x34, 0x1a,
++ 0x71, 0x03, 0x9b, 0x5a, 0xf2, 0xcf, 0xfc, 0xb0, 0x4f, 0xaa, 0x39, 0xeb,
++ 0xc8, 0xdf, 0x0d, 0xec, 0xcb, 0xe7, 0x56, 0xc1, 0x1b, 0x09, 0xe7, 0x72,
++ 0x5f, 0x37, 0xe2, 0x00, 0xf8, 0xe4, 0xfe, 0x07, 0xfa, 0x97, 0xe0, 0x1f,
++ 0x39, 0x2f, 0x68, 0xe3, 0x8e, 0x1c, 0xc2, 0xe1, 0x78, 0x9d, 0x07, 0xcd,
++ 0x9c, 0x63, 0x73, 0x2e, 0x81, 0xfc, 0x63, 0xe9, 0x4d, 0xf4, 0x0d, 0xd3,
++ 0xe9, 0xa1, 0x2c, 0xe4, 0xc3, 0x7d, 0x0f, 0x84, 0x7d, 0x3c, 0x8f, 0x94,
++ 0x07, 0x4d, 0xfd, 0x07, 0x55, 0xdf, 0xaf, 0x43, 0x0f, 0x51, 0xf7, 0xd5,
++ 0x96, 0x90, 0x63, 0x00, 0xa7, 0xca, 0x6a, 0x16, 0xb9, 0x3c, 0xdf, 0xab,
++ 0xe9, 0x97, 0x91, 0x07, 0x83, 0x27, 0x0a, 0xf5, 0x1a, 0xa5, 0xd0, 0x0f,
++ 0xe7, 0x40, 0x1f, 0xdf, 0x3d, 0xf5, 0x21, 0xf7, 0x91, 0xc0, 0x08, 0xd8,
++ 0xe9, 0xaa, 0x44, 0x7b, 0xe5, 0x01, 0xb5, 0x46, 0xff, 0x80, 0xb9, 0x32,
++ 0x95, 0x57, 0x39, 0x87, 0x90, 0xe9, 0xc8, 0x2a, 0xd1, 0x5b, 0x33, 0xec,
++ 0x97, 0x19, 0xd8, 0x2f, 0xb3, 0x7f, 0x7d, 0xd0, 0x1f, 0x7b, 0x6b, 0x06,
++ 0x35, 0xf8, 0xcc, 0x00, 0xc7, 0xb0, 0x75, 0x11, 0xbc, 0x44, 0xee, 0xc3,
++ 0xf9, 0xf9, 0x5d, 0xee, 0x98, 0xda, 0xf7, 0x4b, 0x0a, 0x55, 0x66, 0xf8,
++ 0x6e, 0x49, 0xc6, 0xf9, 0x5c, 0x5b, 0x6c, 0x03, 0x7e, 0x02, 0xa1, 0xee,
++ 0x12, 0x38, 0xa6, 0x09, 0xd0, 0xa1, 0x5d, 0x90, 0x3d, 0xf8, 0x1f, 0xb6,
++ 0xdb, 0xfa, 0xf4, 0x2f, 0xd0, 0x27, 0x9e, 0x27, 0x6f, 0xc2, 0x25, 0x33,
++ 0x6b, 0x8b, 0x1c, 0x1f, 0x3e, 0x0d, 0xdb, 0xb3, 0xe2, 0x63, 0xcd, 0x0e,
++ 0x6a, 0xf5, 0xb2, 0x3d, 0xb0, 0x5e, 0x5c, 0x66, 0x9d, 0xc0, 0x19, 0xd0,
++ 0xa1, 0x19, 0xae, 0xe7, 0x65, 0xcc, 0xbb, 0x2f, 0x9c, 0xc7, 0xfc, 0xfe,
++ 0x1e, 0x4d, 0x0f, 0xa9, 0x42, 0x59, 0x0d, 0xe2, 0x45, 0x6d, 0xa8, 0x03,
++ 0x63, 0x22, 0x1d, 0x7c, 0x38, 0x8f, 0xb5, 0x9c, 0x53, 0xc5, 0x85, 0xc0,
++ 0x6f, 0x71, 0x1f, 0xdf, 0xd7, 0xa9, 0x54, 0xbe, 0xd4, 0x4b, 0x95, 0x4b,
++ 0x0a, 0xf8, 0x02, 0x44, 0x17, 0x82, 0x7d, 0xd8, 0x17, 0x1c, 0x87, 0xdc,
++ 0xc4, 0x73, 0x0a, 0xc5, 0xce, 0x21, 0x87, 0xbc, 0xd0, 0x45, 0x1d, 0x17,
++ 0xfa, 0x49, 0xba, 0xa0, 0x73, 0x7e, 0xa8, 0x9d, 0x81, 0x0c, 0x8f, 0x50,
++ 0x9e, 0x9e, 0x73, 0x07, 0x39, 0xc7, 0xc3, 0x39, 0x5c, 0xe7, 0x25, 0x49,
++ 0x42, 0xf2, 0x2f, 0xbe, 0x68, 0xd1, 0x8b, 0x43, 0xc0, 0x2b, 0x8f, 0xf6,
++ 0x8f, 0x91, 0xc7, 0xbb, 0x23, 0xf7, 0x71, 0xcc, 0x96, 0xcd, 0x3e, 0xc8,
++ 0x16, 0x74, 0xe5, 0x1e, 0xf2, 0xef, 0x44, 0x5f, 0x1c, 0x62, 0x7a, 0x34,
++ 0xd0, 0x52, 0x87, 0xae, 0xf3, 0x3d, 0x57, 0x17, 0xd9, 0x32, 0xeb, 0x32,
++ 0xf2, 0xaa, 0x0b, 0x75, 0x9a, 0x6a, 0xe8, 0x90, 0x59, 0x1f, 0xf4, 0x02,
++ 0x32, 0x4b, 0x73, 0x3f, 0xef, 0x2d, 0x84, 0xfb, 0xde, 0xd1, 0xf7, 0x17,
++ 0xef, 0xad, 0xef, 0x3e, 0xd4, 0x9b, 0x8f, 0xc0, 0x67, 0xa3, 0x2e, 0x32,
++ 0xe0, 0xd3, 0x55, 0xe4, 0x72, 0x06, 0xbf, 0x07, 0x77, 0x95, 0x15, 0xe4,
++ 0x85, 0xfc, 0x5e, 0x6b, 0xdd, 0xcd, 0x77, 0x07, 0xf6, 0x7d, 0x06, 0x3c,
++ 0xba, 0x32, 0xf7, 0x00, 0x5d, 0x9d, 0x53, 0xe8, 0x5a, 0x43, 0xcf, 0x16,
++ 0xa8, 0x83, 0xaa, 0xc9, 0x34, 0x5d, 0x5f, 0x6a, 0xe7, 0x93, 0x22, 0xf4,
++ 0xc4, 0x22, 0xce, 0xcd, 0xaf, 0x2c, 0x55, 0x4b, 0x37, 0x76, 0xa7, 0x49,
++ 0x7e, 0x09, 0xb6, 0xfd, 0x92, 0xae, 0xd5, 0xc0, 0xe7, 0xba, 0xe1, 0xa2,
++ 0x56, 0xe3, 0x3a, 0x32, 0x05, 0xbb, 0xd3, 0x53, 0x2d, 0xca, 0x90, 0xb4,
++ 0xa0, 0xd0, 0xaf, 0x66, 0x74, 0x8d, 0x75, 0xee, 0xa2, 0x81, 0x7e, 0x37,
++ 0x7e, 0x7b, 0x3d, 0xd0, 0x43, 0xf4, 0xf5, 0xa3, 0xbe, 0xd5, 0xb3, 0x9a,
++ 0xd8, 0x4d, 0x6f, 0x43, 0x27, 0xca, 0x7e, 0xdf, 0x47, 0xf7, 0xbc, 0x1e,
++ 0xee, 0x59, 0x2d, 0x5d, 0xe1, 0x3a, 0x68, 0x86, 0x75, 0xbe, 0x17, 0xfe,
++ 0x03, 0xef, 0x6e, 0x07, 0x95, 0x27, 0x11, 0xa3, 0x66, 0x1e, 0xa5, 0xc2,
++ 0x90, 0x18, 0xd0, 0xed, 0xf3, 0x82, 0xfb, 0xf8, 0x7e, 0xb2, 0x76, 0x1f,
++ 0xdb, 0xb2, 0xb8, 0x0a, 0xbd, 0x3a, 0xc8, 0x7a, 0x80, 0xdc, 0x0e, 0x39,
++ 0x04, 0xfb, 0x4e, 0x09, 0x39, 0x44, 0xc1, 0x0d, 0x74, 0xa3, 0x75, 0x30,
++ 0x49, 0xc7, 0x5e, 0x62, 0x19, 0x61, 0x6c, 0x43, 0xef, 0x36, 0xee, 0xc4,
++ 0x31, 0x66, 0xd0, 0xf1, 0xef, 0xb7, 0x73, 0x4a, 0xb6, 0xbd, 0x34, 0xe4,
++ 0xa1, 0xa3, 0xf6, 0xe8, 0x53, 0x2b, 0xbe, 0x4f, 0x81, 0x4e, 0xa4, 0x02,
++ 0x19, 0xd4, 0x30, 0x36, 0xed, 0x4e, 0xc2, 0x27, 0xc6, 0xe8, 0xe6, 0xa4,
++ 0x05, 0x9d, 0x68, 0x01, 0x87, 0xc3, 0x71, 0xbe, 0x4b, 0xb8, 0x39, 0x59,
++ 0xc4, 0xfb, 0x61, 0x3f, 0xf7, 0x97, 0xf6, 0x40, 0x97, 0xdc, 0x07, 0xc2,
++ 0xfc, 0x9c, 0xcf, 0xd3, 0x84, 0xda, 0xac, 0x2e, 0x4c, 0xcf, 0x7a, 0x34,
++ 0x9a, 0xeb, 0x4b, 0x5d, 0xa5, 0x4e, 0xff, 0xce, 0xd8, 0xf7, 0x9b, 0xfe,
++ 0x9c, 0x5d, 0x18, 0xff, 0x00, 0x3a, 0x85, 0x27, 0xe2, 0xf5, 0xe9, 0x66,
++ 0x35, 0xd5, 0x41, 0xac, 0x53, 0x24, 0x2c, 0x18, 0xec, 0x3b, 0x04, 0xba,
++ 0xea, 0xdf, 0x47, 0x13, 0x15, 0x9d, 0xd7, 0x99, 0x6e, 0x61, 0xb1, 0xc5,
++ 0x6b, 0x58, 0xce, 0xbc, 0x46, 0xa2, 0x9b, 0x49, 0xd8, 0xe5, 0x9e, 0x3d,
++ 0x7e, 0xbd, 0xf8, 0xf8, 0x10, 0xe3, 0xda, 0x0d, 0x99, 0x42, 0xbf, 0x50,
++ 0xdb, 0x94, 0x83, 0xbe, 0x59, 0xae, 0x4d, 0xa7, 0xf9, 0xde, 0x23, 0xef,
++ 0xeb, 0x5a, 0xa8, 0x1f, 0x1f, 0xd7, 0xb5, 0xe7, 0xb0, 0xf6, 0x2d, 0xf6,
++ 0xab, 0x90, 0x75, 0xe0, 0x23, 0xbe, 0x41, 0x6f, 0xcd, 0x55, 0xb3, 0xfc,
++ 0xcd, 0xa3, 0x35, 0x21, 0xa0, 0x16, 0x3f, 0x4e, 0x6f, 0xcf, 0x3d, 0x4b,
++ 0xbf, 0x9c, 0x65, 0xdd, 0x31, 0x68, 0x14, 0xfa, 0x74, 0x94, 0xe4, 0xec,
++ 0x69, 0x1a, 0x50, 0xaf, 0xfb, 0xb5, 0x8d, 0x9e, 0xf3, 0x6b, 0x3a, 0x33,
++ 0x4b, 0xc5, 0xc6, 0x40, 0xea, 0x1a, 0xfa, 0xca, 0x93, 0xba, 0xb6, 0x8e,
++ 0xdc, 0xa3, 0xd0, 0xfc, 0x80, 0xef, 0x6c, 0xb2, 0x35, 0xd8, 0xde, 0x22,
++ 0x6a, 0x9b, 0xb7, 0x9d, 0xbb, 0xe9, 0x2c, 0xd7, 0x56, 0x81, 0xff, 0x5e,
++ 0x33, 0x50, 0x63, 0xac, 0xaa, 0xa1, 0x0e, 0x31, 0x70, 0x9d, 0xc1, 0xf1,
++ 0x07, 0x4f, 0x37, 0x06, 0x9f, 0xb2, 0x1f, 0x7c, 0x67, 0xd9, 0x42, 0xfe,
++ 0xab, 0xfc, 0x8d, 0x0a, 0xf2, 0x5f, 0x5d, 0xfe, 0x40, 0xeb, 0x65, 0x3f,
++ 0x6b, 0x80, 0x96, 0x41, 0x3a, 0x33, 0xcf, 0xf2, 0x47, 0xec, 0xf5, 0xed,
++ 0x34, 0x0d, 0xfe, 0x72, 0x7c, 0x19, 0xa4, 0x5f, 0x2d, 0x15, 0xfd, 0xfb,
++ 0x6b, 0x1b, 0xb9, 0xd6, 0x11, 0x67, 0x12, 0xf5, 0xfa, 0x77, 0x40, 0x2f,
++ 0xce, 0x1e, 0xda, 0x8d, 0xa7, 0x0a, 0x9b, 0xdc, 0x72, 0x9e, 0x23, 0x07,
++ 0x79, 0xce, 0xde, 0x2d, 0xe6, 0x39, 0x7b, 0xb7, 0x92, 0xe7, 0xc8, 0x9d,
++ 0xe0, 0xab, 0xd6, 0xbb, 0x65, 0xdc, 0xa4, 0x00, 0xb7, 0x03, 0x5b, 0xc4,
++ 0xed, 0xc0, 0x56, 0x70, 0x93, 0x3a, 0xcd, 0xbf, 0x40, 0x8c, 0x35, 0x10,
++ 0xdb, 0xe0, 0xd7, 0x86, 0xfa, 0x59, 0x7f, 0x80, 0xa3, 0x8f, 0xeb, 0xef,
++ 0x8b, 0xa7, 0x18, 0xe0, 0xf9, 0xd8, 0x16, 0xf1, 0x7c, 0x6c, 0x2b, 0x78,
++ 0x8a, 0x9d, 0x26, 0xe3, 0x28, 0xc3, 0xd7, 0x70, 0x6d, 0x83, 0xd8, 0x3c,
++ 0x24, 0x87, 0xba, 0x2e, 0x87, 0x75, 0x0e, 0x03, 0x7c, 0x50, 0xaf, 0x46,
++ 0x4b, 0x4c, 0xcb, 0x46, 0xdf, 0x9d, 0x3a, 0x4b, 0x32, 0x5b, 0xa5, 0x4a,
++ 0x83, 0xef, 0x95, 0xfb, 0xb0, 0x0f, 0xf7, 0xf1, 0x37, 0x2a, 0x8b, 0x64,
++ 0xc4, 0xf7, 0xe7, 0x9a, 0x77, 0xa7, 0xf5, 0x2a, 0x68, 0x9d, 0x0a, 0x69,
++ 0xad, 0xf8, 0xb9, 0xe0, 0xbe, 0x4d, 0xb9, 0x60, 0x40, 0xe3, 0x08, 0x68,
++ 0x2c, 0x86, 0x34, 0x3e, 0xdd, 0x60, 0xda, 0xf6, 0xf9, 0xb4, 0x2d, 0x6d,
++ 0xa2, 0x6d, 0xe4, 0x9e, 0xf9, 0x1f, 0xe3, 0x81, 0x5a, 0x1a, 0xb9, 0xd7,
++ 0x6b, 0x4d, 0xd4, 0xd2, 0x4d, 0xd4, 0xd2, 0xd0, 0xf7, 0x57, 0x9b, 0xa8,
++ 0xa5, 0x9b, 0xa8, 0xa5, 0x61, 0x07, 0xaf, 0xc0, 0x56, 0x82, 0x3b, 0xdc,
++ 0x12, 0x71, 0x0d, 0xee, 0xd7, 0xe3, 0x14, 0xe4, 0x39, 0x05, 0xc4, 0xf0,
++ 0xa3, 0xc8, 0xf1, 0xd8, 0x6e, 0x4f, 0x13, 0xc7, 0x04, 0x3d, 0x87, 0x9a,
++ 0x2f, 0x5b, 0x25, 0x33, 0x5e, 0x9c, 0x1f, 0x50, 0x97, 0x02, 0xfb, 0xd6,
++ 0x5a, 0xc4, 0x71, 0x70, 0x20, 0x85, 0x08, 0xa9, 0xb2, 0x5f, 0xb0, 0x73,
++ 0x4c, 0xe7, 0x76, 0xf0, 0x10, 0xbe, 0xdb, 0x60, 0x1f, 0xc6, 0xbe, 0xb4,
++ 0x4e, 0x0b, 0x8d, 0xf0, 0x1b, 0x9a, 0xcc, 0xfd, 0xfc, 0xce, 0x31, 0xb7,
++ 0xcf, 0xf7, 0x69, 0x76, 0xb6, 0x0f, 0x71, 0x80, 0xfb, 0x15, 0xf8, 0x35,
++ 0xe8, 0xca, 0x52, 0x1b, 0x17, 0x19, 0xeb, 0x55, 0xaa, 0xcf, 0x07, 0x31,
++ 0x7c, 0xca, 0xe0, 0x38, 0x87, 0xf8, 0xbe, 0xc4, 0xdf, 0xb0, 0x10, 0xeb,
++ 0x97, 0xae, 0x68, 0x32, 0x6a, 0xc7, 0x3a, 0x7f, 0xa3, 0x1d, 0xec, 0xc3,
++ 0xf9, 0x1d, 0xfe, 0x1d, 0xed, 0x51, 0xff, 0xae, 0xcd, 0xa0, 0x23, 0xad,
++ 0x80, 0x16, 0xdb, 0xc8, 0xd0, 0xc8, 0x2c, 0xdf, 0x35, 0x51, 0x8f, 0x68,
++ 0xca, 0x54, 0x75, 0xf8, 0x7e, 0x68, 0xe3, 0xbb, 0x49, 0x76, 0x91, 0xeb,
++ 0x4f, 0x23, 0xb8, 0xff, 0x3c, 0xed, 0xbc, 0xc9, 0xf7, 0x9f, 0xe1, 0x3a,
++ 0x8d, 0xde, 0x70, 0x33, 0x34, 0x8e, 0xf8, 0x5a, 0x6c, 0x68, 0xf0, 0x6f,
++ 0xbe, 0x3c, 0x39, 0xa7, 0xad, 0xc6, 0x42, 0x99, 0x8e, 0x84, 0x32, 0xad,
++ 0x34, 0xd6, 0x80, 0xdf, 0x0d, 0xef, 0x8f, 0x43, 0x99, 0xee, 0x3a, 0x47,
++ 0xda, 0xd5, 0x1c, 0xcb, 0x95, 0x65, 0x19, 0xc8, 0x75, 0x7c, 0xb1, 0x24,
++ 0x14, 0x21, 0xd3, 0x51, 0x5f, 0xa6, 0x32, 0xc7, 0x05, 0xec, 0x95, 0x83,
++ 0xfc, 0xd9, 0x8f, 0xe1, 0xe9, 0xb0, 0x8c, 0xb9, 0xde, 0xe0, 0x58, 0x98,
++ 0xa4, 0x4b, 0x9b, 0xe4, 0x5c, 0xbc, 0xa7, 0x0e, 0xe7, 0xa9, 0xff, 0x9c,
++ 0x16, 0xde, 0x9b, 0x66, 0x21, 0xc7, 0x76, 0x2e, 0xf6, 0x23, 0x81, 0x8c,
++ 0xf6, 0x9d, 0x6e, 0xbb, 0xef, 0xe5, 0x4d, 0x7d, 0xed, 0x67, 0x9b, 0x56,
++ 0xc4, 0xb7, 0x0d, 0xde, 0xf3, 0x1d, 0xe4, 0x9d, 0x7e, 0xc9, 0x1f, 0x53,
++ 0x31, 0xd6, 0x4b, 0x85, 0x25, 0x83, 0xac, 0x16, 0xcf, 0x91, 0x49, 0x34,
++ 0xda, 0x72, 0xea, 0xa4, 0xf5, 0x30, 0xc6, 0x2d, 0x34, 0x3c, 0xef, 0xa7,
++ 0xd0, 0x9d, 0x8b, 0x5c, 0x77, 0x3b, 0xbf, 0xf1, 0xd6, 0x93, 0xc8, 0x21,
++ 0x37, 0xce, 0xfc, 0xe6, 0xfd, 0xd4, 0xa5, 0xab, 0x88, 0x09, 0x74, 0xc6,
++ 0x09, 0x51, 0x22, 0x1e, 0xe7, 0x3e, 0xfe, 0x06, 0xef, 0x79, 0x17, 0x8d,
++ 0x3b, 0x78, 0x75, 0x99, 0xc7, 0x69, 0xdf, 0x39, 0xf6, 0xff, 0x3f, 0xd0,
++ 0x2e, 0x1a, 0xd6, 0x9e, 0x38, 0xf2, 0xe7, 0xeb, 0xc4, 0xb1, 0x4f, 0x4e,
++ 0x14, 0x9b, 0xba, 0x7a, 0x09, 0x6b, 0x8b, 0x8e, 0xc2, 0xdf, 0xd6, 0xf9,
++ 0xfb, 0xa8, 0x76, 0x89, 0xda, 0xf7, 0x65, 0x90, 0xa7, 0xa3, 0xf2, 0x77,
++ 0x52, 0xb5, 0x8a, 0xd8, 0x52, 0x70, 0x92, 0x98, 0xaf, 0x62, 0x2e, 0xc7,
++ 0x05, 0x8f, 0x14, 0xd8, 0x50, 0xc1, 0x49, 0x27, 0xc6, 0x9a, 0x9e, 0xa7,
++ 0x7c, 0x5e, 0xa0, 0x87, 0x32, 0x29, 0x1a, 0x73, 0xf8, 0xfe, 0xf7, 0x9b,
++ 0xf4, 0x36, 0xec, 0xac, 0x78, 0x9e, 0x6b, 0x26, 0xf6, 0x29, 0x78, 0x77,
++ 0xf8, 0xbe, 0xea, 0x14, 0x3d, 0xb4, 0x47, 0xcf, 0x5e, 0x22, 0xe0, 0xb3,
++ 0x42, 0xfd, 0x48, 0x72, 0x53, 0xc7, 0xfd, 0xef, 0x6d, 0x8c, 0x6b, 0x9a,
++ 0x96, 0xc0, 0x1b, 0xa7, 0x99, 0xa4, 0x95, 0x66, 0x8a, 0x56, 0xa1, 0x1f,
++ 0xdb, 0xcc, 0x32, 0x7d, 0x03, 0x78, 0x2b, 0x66, 0x95, 0x94, 0x8c, 0xb5,
++ 0xaf, 0x0b, 0x78, 0x67, 0x05, 0x3d, 0x15, 0x17, 0x18, 0x77, 0x5d, 0x2d,
++ 0x03, 0x6f, 0xd6, 0xd1, 0x51, 0xa7, 0x9b, 0x8e, 0x61, 0xed, 0x7e, 0xe4,
++ 0x1f, 0xdf, 0x72, 0xa8, 0x2c, 0x99, 0x29, 0x3a, 0x80, 0xf3, 0x8e, 0x36,
++ 0x38, 0x57, 0x3b, 0x02, 0x5f, 0x23, 0xd0, 0xa3, 0x19, 0x8f, 0x1e, 0xdd,
++ 0xa3, 0x5b, 0x71, 0x01, 0x7b, 0xae, 0xb0, 0x9e, 0xa0, 0xdf, 0x09, 0xce,
++ 0x8d, 0xad, 0xf8, 0xba, 0x08, 0x7f, 0xfa, 0x0c, 0x65, 0xce, 0xad, 0xe5,
++ 0xa6, 0x90, 0x9f, 0x8f, 0x36, 0xe9, 0x8b, 0x31, 0x9c, 0xf7, 0x36, 0xf8,
++ 0x34, 0xea, 0xc8, 0x02, 0xf3, 0xe9, 0x58, 0xc0, 0x27, 0x8c, 0xf1, 0xb7,
++ 0x23, 0xce, 0xd1, 0xf8, 0xec, 0x13, 0x74, 0xb6, 0xc1, 0x77, 0xdd, 0x27,
++ 0xe8, 0x4a, 0xe3, 0x11, 0xba, 0x98, 0xe3, 0x5c, 0x07, 0xfb, 0xf8, 0x67,
++ 0xa0, 0xcf, 0x3f, 0xa3, 0x9b, 0x8e, 0xfb, 0x72, 0xfa, 0x3f, 0xc3, 0x06,
++ 0xd0, 0x70, 0x4c, 0x57, 0x00, 0x00, 0x00 };
++
++static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
++static u32 bnx2_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
++static u32 bnx2_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/linux/ethtool.h kernel-source-2.6.8-2.6.8/include/linux/ethtool.h
+--- kernel-source-2.6.8-2.6.8.orig/include/linux/ethtool.h 2004-08-13 23:36:32.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/linux/ethtool.h 2006-09-19 17:48:35.687160000 -0600
+@@ -429,10 +429,11 @@
+ * it was foced up into this mode or autonegotiated.
+ */
+
+-/* The forced speed, 10Mb, 100Mb, gigabit, 10GbE. */
++/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
+ #define SPEED_10 10
+ #define SPEED_100 100
+ #define SPEED_1000 1000
++#define SPEED_2500 2500
+ #define SPEED_10000 10000
+
+ /* Duplex, half or full. */
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/linux/mii.h kernel-source-2.6.8-2.6.8/include/linux/mii.h
+--- kernel-source-2.6.8-2.6.8.orig/include/linux/mii.h 2006-09-19 17:45:21.755160000 -0600
++++ kernel-source-2.6.8-2.6.8/include/linux/mii.h 2006-09-19 17:48:23.479160000 -0600
+@@ -35,7 +35,8 @@
+ #define MII_NCONFIG 0x1c /* Network interface config */
+
+ /* Basic mode control register. */
+-#define BMCR_RESV 0x007f /* Unused... */
++#define BMCR_RESV 0x003f /* Unused... */
++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
+ #define BMCR_CTST 0x0080 /* Collision test */
+ #define BMCR_FULLDPLX 0x0100 /* Full duplex */
+ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
+@@ -64,9 +65,13 @@
+ #define ADVERTISE_SLCT 0x001f /* Selector bits */
+ #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
+ #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
++#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
+ #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
++#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
+ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
++#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
+ #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
++#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
+ #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+ #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
+ #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
+@@ -83,9 +88,13 @@
+ /* Link partner ability register. */
+ #define LPA_SLCT 0x001f /* Same as advertise selector */
+ #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
++#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
+ #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
++#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
+ #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
++#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
+ #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
++#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
+ #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
+ #define LPA_PAUSE_CAP 0x0400 /* Can pause */
+ #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/linux/pci_ids.h kernel-source-2.6.8-2.6.8/include/linux/pci_ids.h
+--- kernel-source-2.6.8-2.6.8.orig/include/linux/pci_ids.h 2006-09-19 17:45:21.475160000 -0600
++++ kernel-source-2.6.8-2.6.8/include/linux/pci_ids.h 2006-09-19 17:48:35.691160000 -0600
+@@ -1888,6 +1888,8 @@
+ #define PCI_DEVICE_ID_TIGON3_5703 0x1647
+ #define PCI_DEVICE_ID_TIGON3_5704 0x1648
+ #define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
++#define PCI_DEVICE_ID_NX2_5706 0x164a
++#define PCI_DEVICE_ID_NX2_5708 0x164c
+ #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
+ #define PCI_DEVICE_ID_TIGON3_5705 0x1653
+ #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
+@@ -1907,6 +1909,8 @@
+ #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
+ #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
+ #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
++#define PCI_DEVICE_ID_NX2_5706S 0x16aa
++#define PCI_DEVICE_ID_NX2_5708S 0x16ac
+ #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
+ #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
+ #define PCI_DEVICE_ID_TIGON3_5901 0x170d
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/broadcom-mii-constants.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/broadcom-mii-constants.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,87 @@
+diff -Naru a/drivers/net/b44.h b/drivers/net/b44.h
+--- a/drivers/net/b44.h 2006-09-19 00:47:43 -07:00
++++ b/drivers/net/b44.h 2006-09-19 00:47:43 -07:00
+@@ -302,20 +302,6 @@
+ #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */
+ #define MII_TLEDCTRL_ENABLE 0x0040
+
+-/* XXX Add this to mii.h */
+-#ifndef ADVERTISE_PAUSE
+-#define ADVERTISE_PAUSE_CAP 0x0400
+-#endif
+-#ifndef ADVERTISE_PAUSE_ASYM
+-#define ADVERTISE_PAUSE_ASYM 0x0800
+-#endif
+-#ifndef LPA_PAUSE
+-#define LPA_PAUSE_CAP 0x0400
+-#endif
+-#ifndef LPA_PAUSE_ASYM
+-#define LPA_PAUSE_ASYM 0x0800
+-#endif
+-
+ struct dma_desc {
+ u32 ctrl;
+ u32 addr;
+diff -Naru a/drivers/net/tg3.h b/drivers/net/tg3.h
+--- a/drivers/net/tg3.h 2006-09-19 00:47:43 -07:00
++++ b/drivers/net/tg3.h 2006-09-19 00:47:43 -07:00
+@@ -1545,20 +1545,6 @@
+ #define MII_TG3_INT_DUPLEXCHG 0x0008
+ #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
+
+-/* XXX Add this to mii.h */
+-#ifndef ADVERTISE_PAUSE
+-#define ADVERTISE_PAUSE_CAP 0x0400
+-#endif
+-#ifndef ADVERTISE_PAUSE_ASYM
+-#define ADVERTISE_PAUSE_ASYM 0x0800
+-#endif
+-#ifndef LPA_PAUSE
+-#define LPA_PAUSE_CAP 0x0400
+-#endif
+-#ifndef LPA_PAUSE_ASYM
+-#define LPA_PAUSE_ASYM 0x0800
+-#endif
+-
+ /* There are two ways to manage the TX descriptors on the tigon3.
+ * Either the descriptors are in host DMA'able memory, or they
+ * exist only in the cards on-chip SRAM. All 16 send bds are under
+diff -Naru a/include/linux/mii.h b/include/linux/mii.h
+--- a/include/linux/mii.h 2006-09-19 00:47:43 -07:00
++++ b/include/linux/mii.h 2006-09-19 00:47:43 -07:00
+@@ -67,6 +67,8 @@
+ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+ #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+ #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
+ #define ADVERTISE_RESV 0x1c00 /* Unused... */
+ #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
+ #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
+@@ -84,6 +86,8 @@
+ #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+ #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+ #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
++#define LPA_PAUSE_CAP 0x0400 /* Can pause */
++#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
+ #define LPA_RESV 0x1c00 /* Unused... */
+ #define LPA_RFAULT 0x2000 /* Link partner faulted */
+ #define LPA_LPACK 0x4000 /* Link partner acked us */
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2005/01/27 17:18:18-05:00 dhollis at davehollis.com
+# Move MII-related constants from b44/tg3 drivers to linux/mii.h.
+#
+# drivers/net/b44.h
+# 2005/01/27 17:18:11-05:00 dhollis at davehollis.com +0 -14
+# Move MII-related constants from b44/tg3 drivers to linux/mii.h.
+#
+# drivers/net/tg3.h
+# 2005/01/27 17:18:11-05:00 dhollis at davehollis.com +0 -14
+# Move MII-related constants from b44/tg3 drivers to linux/mii.h.
+#
+# include/linux/mii.h
+# 2005/01/27 17:18:11-05:00 dhollis at davehollis.com +4 -0
+# Move MII-related constants from b44/tg3 drivers to linux/mii.h.
+#
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/i386-atomic_add_return-define.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/i386-atomic_add_return-define.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,76 @@
+diff -Naru a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h
+--- a/include/asm-i386/atomic.h 2006-09-19 03:04:53 -07:00
++++ b/include/asm-i386/atomic.h 2006-09-19 03:04:53 -07:00
+@@ -2,6 +2,8 @@
+ #define __ARCH_I386_ATOMIC__
+
+ #include <linux/config.h>
++#include <linux/compiler.h>
++#include <asm/processor.h>
+
+ /*
+ * Atomic operations that C can't guarantee us. Useful for
+@@ -175,6 +177,46 @@
+ :"ir" (i), "m" (v->counter) : "memory");
+ return c;
+ }
++
++/**
++ * atomic_add_return - add and return
++ * @v: pointer of type atomic_t
++ * @i: integer value to add
++ *
++ * Atomically adds @i to @v and returns @i + @v
++ */
++static __inline__ int atomic_add_return(int i, atomic_t *v)
++{
++ int __i;
++#ifdef CONFIG_M386
++ if(unlikely(boot_cpu_data.x86==3))
++ goto no_xadd;
++#endif
++ /* Modern 486+ processor */
++ __i = i;
++ __asm__ __volatile__(
++ LOCK "xaddl %0, %1;"
++ :"=r"(i)
++ :"m"(v->counter), "0"(i));
++ return i + __i;
++
++#ifdef CONFIG_M386
++no_xadd: /* Legacy 386 processor */
++ local_irq_disable();
++ __i = atomic_read(v);
++ atomic_set(v, i + __i);
++ local_irq_enable();
++ return i + __i;
++#endif
++}
++
++static __inline__ int atomic_sub_return(int i, atomic_t *v)
++{
++ return atomic_add_return(-i,v);
++}
++
++#define atomic_inc_return(v) (atomic_add_return(1,v))
++#define atomic_dec_return(v) (atomic_sub_return(1,v))
+
+ /* These are x86-specific, used by some header files */
+ #define atomic_clear_mask(mask, addr) \
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2004/10/20 08:13:14-07:00 kaigai at ak.jp.nec.com
+# [PATCH] atomic_inc_return() for i386
+#
+# This patch implements atomic_inc_return() and so on for i386, and includes
+# runtime check whether CPU is legacy 386.
+#
+# Signed-off-by: KaiGai, Kohei <kaigai at ak.jp.nec.com>
+# Signed-off-by: Andrew Morton <akpm at osdl.org>
+# Signed-off-by: Linus Torvalds <torvalds at osdl.org>
+#
+# include/asm-i386/atomic.h
+# 2004/10/20 01:12:08-07:00 kaigai at ak.jp.nec.com +42 -0
+# atomic_inc_return() for i386
+#
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mii-gige-support.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mii-gige-support.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,263 @@
+diff -Naru a/drivers/net/mii.c b/drivers/net/mii.c
+--- a/drivers/net/mii.c 2006-09-19 00:48:16 -07:00
++++ b/drivers/net/mii.c 2006-09-19 00:48:16 -07:00
+@@ -37,6 +37,7 @@
+ {
+ struct net_device *dev = mii->dev;
+ u32 advert, bmcr, lpa, nego;
++ u32 advert2 = 0, bmcr2 = 0, lpa2 = 0;
+
+ ecmd->supported =
+ (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
+@@ -54,6 +55,9 @@
+
+ ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
+ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
++ if (mii->supports_gmii)
++ advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
++
+ if (advert & ADVERTISE_10HALF)
+ ecmd->advertising |= ADVERTISED_10baseT_Half;
+ if (advert & ADVERTISE_10FULL)
+@@ -62,19 +66,31 @@
+ ecmd->advertising |= ADVERTISED_100baseT_Half;
+ if (advert & ADVERTISE_100FULL)
+ ecmd->advertising |= ADVERTISED_100baseT_Full;
++ if (advert2 & ADVERTISE_1000HALF)
++ ecmd->advertising |= ADVERTISED_1000baseT_Half;
++ if (advert2 & ADVERTISE_1000FULL)
++ ecmd->advertising |= ADVERTISED_1000baseT_Full;
+
+ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
+ lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
++ if (mii->supports_gmii) {
++ bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
++ lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
++ }
+ if (bmcr & BMCR_ANENABLE) {
+ ecmd->advertising |= ADVERTISED_Autoneg;
+ ecmd->autoneg = AUTONEG_ENABLE;
+
+ nego = mii_nway_result(advert & lpa);
+- if (nego == LPA_100FULL || nego == LPA_100HALF)
++ if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) &
++ (lpa2 >> 2))
++ ecmd->speed = SPEED_1000;
++ else if (nego == LPA_100FULL || nego == LPA_100HALF)
+ ecmd->speed = SPEED_100;
+ else
+ ecmd->speed = SPEED_10;
+- if (nego == LPA_100FULL || nego == LPA_10FULL) {
++ if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
++ nego == LPA_10FULL) {
+ ecmd->duplex = DUPLEX_FULL;
+ mii->full_duplex = 1;
+ } else {
+@@ -84,7 +100,9 @@
+ } else {
+ ecmd->autoneg = AUTONEG_DISABLE;
+
+- ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
++ ecmd->speed = ((bmcr2 & BMCR_SPEED1000 &&
++ (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
++ (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
+ ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+ }
+
+@@ -97,7 +115,9 @@
+ {
+ struct net_device *dev = mii->dev;
+
+- if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
++ if (ecmd->speed != SPEED_10 &&
++ ecmd->speed != SPEED_100 &&
++ ecmd->speed != SPEED_1000)
+ return -EINVAL;
+ if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
+ return -EINVAL;
+@@ -109,21 +129,30 @@
+ return -EINVAL;
+ if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
+ return -EINVAL;
++ if ((ecmd->speed == SPEED_1000) && (!mii->supports_gmii))
++ return -EINVAL;
+
+ /* ignore supported, maxtxpkt, maxrxpkt */
+
+ if (ecmd->autoneg == AUTONEG_ENABLE) {
+ u32 bmcr, advert, tmp;
++ u32 advert2 = 0, tmp2 = 0;
+
+ if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+- ADVERTISED_100baseT_Full)) == 0)
++ ADVERTISED_100baseT_Full |
++ ADVERTISED_1000baseT_Half |
++ ADVERTISED_1000baseT_Full)) == 0)
+ return -EINVAL;
+
+ /* advertise only what has been requested */
+ advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
+ tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
++ if (mii->supports_gmii) {
++ advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
++ tmp2 = advert2 & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
++ }
+ if (ecmd->advertising & ADVERTISED_10baseT_Half)
+ tmp |= ADVERTISE_10HALF;
+ if (ecmd->advertising & ADVERTISED_10baseT_Full)
+@@ -132,10 +161,18 @@
+ tmp |= ADVERTISE_100HALF;
+ if (ecmd->advertising & ADVERTISED_100baseT_Full)
+ tmp |= ADVERTISE_100FULL;
++ if (mii->supports_gmii) {
++ if (ecmd->advertising & ADVERTISED_1000baseT_Half)
++ advert2 |= ADVERTISE_1000HALF;
++ if (ecmd->advertising & ADVERTISED_1000baseT_Full)
++ advert2 |= ADVERTISE_1000FULL;
++ }
+ if (advert != tmp) {
+ mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp);
+ mii->advertising = tmp;
+ }
++ if ((mii->supports_gmii) && (advert2 != tmp2))
++ mii->mdio_write(dev, mii->phy_id, MII_CTRL1000, tmp2);
+
+ /* turn on autonegotiation, and force a renegotiate */
+ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
+@@ -148,8 +185,11 @@
+
+ /* turn off auto negotiation, set speed and duplexity */
+ bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
+- tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
+- if (ecmd->speed == SPEED_100)
++ tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
++ BMCR_SPEED1000 | BMCR_FULLDPLX);
++ if (ecmd->speed == SPEED_1000)
++ tmp |= BMCR_SPEED1000;
++ else if (ecmd->speed == SPEED_100)
+ tmp |= BMCR_SPEED100;
+ if (ecmd->duplex == DUPLEX_FULL) {
+ tmp |= BMCR_FULLDPLX;
+@@ -207,6 +247,7 @@
+ {
+ unsigned int old_carrier, new_carrier;
+ int advertise, lpa, media, duplex;
++ int lpa2 = 0;
+
+ /* if forced media, go no further */
+ if (mii->force_media)
+@@ -243,16 +284,20 @@
+ mii->advertising = advertise;
+ }
+ lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
++ if (mii->supports_gmii)
++ lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
+
+ /* figure out media and duplex from advertise and LPA values */
+ media = mii_nway_result(lpa & advertise);
+ duplex = (media & ADVERTISE_FULL) ? 1 : 0;
++ if (lpa2 & LPA_1000FULL)
++ duplex = 1;
+
+ if (ok_to_print)
+ printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
+ mii->dev->name,
+- media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ?
+- "100" : "10",
++ lpa2 & (LPA_1000FULL | LPA_1000HALF) ? "1000" :
++ media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
+ duplex ? "full" : "half",
+ lpa);
+
+diff -Naru a/include/linux/mii.h b/include/linux/mii.h
+--- a/include/linux/mii.h 2006-09-19 00:48:16 -07:00
++++ b/include/linux/mii.h 2006-09-19 00:48:16 -07:00
+@@ -20,6 +20,8 @@
+ #define MII_ADVERTISE 0x04 /* Advertisement control reg */
+ #define MII_LPA 0x05 /* Link partner ability reg */
+ #define MII_EXPANSION 0x06 /* Expansion register */
++#define MII_CTRL1000 0x09 /* 1000BASE-T control */
++#define MII_STAT1000 0x0a /* 1000BASE-T status */
+ #define MII_DCOUNTER 0x12 /* Disconnect counter */
+ #define MII_FCSCOUNTER 0x13 /* False carrier counter */
+ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+@@ -67,9 +69,9 @@
+ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+ #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+ #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+-#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
+-#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
+-#define ADVERTISE_RESV 0x1c00 /* Unused... */
++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
++#define ADVERTISE_RESV 0x1000 /* Unused... */
+ #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
+ #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
+ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
+@@ -86,9 +88,9 @@
+ #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+ #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+ #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
+-#define LPA_PAUSE_CAP 0x0400 /* Can pause */
+-#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
+-#define LPA_RESV 0x1c00 /* Unused... */
++#define LPA_PAUSE_CAP 0x0400 /* Can pause */
++#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
++#define LPA_RESV 0x1000 /* Unused... */
+ #define LPA_RFAULT 0x2000 /* Link partner faulted */
+ #define LPA_LPACK 0x4000 /* Link partner acked us */
+ #define LPA_NPAGE 0x8000 /* Next page bit */
+@@ -109,6 +111,15 @@
+ #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
+ #define NWAYTEST_RESV2 0xfe00 /* Unused... */
+
++/* 1000BASE-T Control register */
++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
++#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
++
++/* 1000BASE-T Status register */
++#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
++#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
++#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
+
+ struct mii_if_info {
+ int phy_id;
+@@ -118,6 +129,7 @@
+
+ unsigned int full_duplex : 1; /* is full duplex? */
+ unsigned int force_media : 1; /* is autoneg. disabled? */
++ unsigned int supports_gmii : 1; /* are GMII registers supported? */
+
+ struct net_device *dev;
+ int (*mdio_read) (struct net_device *dev, int phy_id, int location);
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2005/03/03 00:56:29-05:00 jchapman at katalix.com
+# [PATCH] mii: add GigE support
+#
+# Add support for GigE PHYs in MII support library.
+#
+# This patch allows GigE drivers to use the MII library the same way
+# 10/100 drivers do.
+#
+# Since the MII library is already used by lots of network drivers and the
+# GigE MII register bit definitions were reserved when many 10/100 PHYs
+# were designed, the new GigE registers are accessed only if a driver
+# specifically enables it. Existing 10/100 drivers should see no behavior
+# differences with this change.
+#
+# Signed-off-by: James Chapman <jchapman at katalix.com>
+# Signed-off-by: Jeff Garzik <jgarzik at pobox.com>
+#
+# drivers/net/mii.c
+# 2005/02/25 16:12:07-05:00 jchapman at katalix.com +54 -9
+# mii: add GigE support
+#
+# include/linux/mii.h
+# 2005/02/25 16:12:07-05:00 jchapman at katalix.com +18 -6
+# mii: add GigE support
+#
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mmiowb-define.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mmiowb-define.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,567 @@
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2004/10/25 18:23:50-07:00 jbarnes at engr.sgi.com
+# [PATCH] I/O space write barrier
+#
+# On some platforms (e.g. SGI Challenge, Origin, and Altix machines), writes
+# to I/O space aren't ordered coming from different CPUs. For the most part,
+# this isn't a problem since drivers generally spinlock around code that does
+# writeX calls, but if the last operation a driver does before it releases a
+# lock is a write and some other CPU takes the lock and immediately does a
+# write, it's possible the second CPU's write could arrive before the
+# first's.
+#
+# This patch adds a mmiowb() call to deal with this sort of situation, and
+# adds some documentation describing I/O ordering issues to
+# deviceiobook.tmpl. The idea is to mirror the regular, cacheable memory
+# barrier operation, wmb. Example of the problem this new macro solves:
+#
+# CPU A: spin_lock_irqsave(&dev_lock, flags)
+# CPU A: ...
+# CPU A: writel(newval, ring_ptr);
+# CPU A: spin_unlock_irqrestore(&dev_lock, flags)
+# ...
+# CPU B: spin_lock_irqsave(&dev_lock, flags)
+# CPU B: writel(newval2, ring_ptr);
+# CPU B: ...
+# CPU B: spin_unlock_irqrestore(&dev_lock, flags)
+#
+# In this case, newval2 could be written to ring_ptr before newval. Fixing
+# it is easy though:
+#
+# CPU A: spin_lock_irqsave(&dev_lock, flags)
+# CPU A: ...
+# CPU A: writel(newval, ring_ptr);
+# CPU A: mmiowb(); /* ensure no other writes beat us to the device */
+# CPU A: spin_unlock_irqrestore(&dev_lock, flags)
+# ...
+# CPU B: spin_lock_irqsave(&dev_lock, flags)
+# CPU B: writel(newval2, ring_ptr);
+# CPU B: ...
+# CPU B: mmiowb();
+# CPU B: spin_unlock_irqrestore(&dev_lock, flags)
+#
+# Note that this doesn't address a related case where the driver may want to
+# actually make a given write get to the device before proceeding. This
+# should be dealt with by immediately reading a register from the card that
+# has no side effects. According to the PCI spec, that will guarantee that
+# all writes have arrived before being sent to the target bus. If no such
+# register is available (in the case of card resets perhaps), reading from
+# config space is sufficient (though it may return all ones if the card isn't
+# responding to read cycles). I've tried to describe how mmiowb() differs
+# from PCI posted write flushing in the patch to deviceiobook.tmpl.
+#
+# Signed-off-by: Jesse Barnes <jbarnes at sgi.com>
+# Signed-off-by: Andrew Morton <akpm at osdl.org>
+# Signed-off-by: Linus Torvalds <torvalds at osdl.org>
+#
+# Documentation/DocBook/deviceiobook.tmpl
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +67 -4
+# I/O space write barrier
+#
+# arch/ia64/sn/kernel/iomv.c
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +5 -8
+# I/O space write barrier
+#
+# include/asm-alpha/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-arm/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-arm26/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-cris/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-h8300/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-i386/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-ia64/io.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +16 -0
+# I/O space write barrier
+#
+# include/asm-ia64/machvec.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +7 -0
+# I/O space write barrier
+#
+# include/asm-ia64/machvec_init.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +1 -0
+# I/O space write barrier
+#
+# include/asm-ia64/machvec_sn2.h
+# 2004/10/25 13:06:49-07:00 jbarnes at engr.sgi.com +2 -0
+# I/O space write barrier
+#
+# include/asm-ia64/sn/io.h
+# 2004/10/25diff -Naru a/Documentation/DocBook/deviceiobook.tmpl b/Documentation/DocBook/deviceiobook.tmpl
+
+#
+# Backported to Debian's 2.6.8 by dann frazier <dannf at hp.com>
+# * arch/ia64/sn changes dropped - code had changed significantly away from
+# 2.6.8 when this changeset was created, and we don't build an sn-optimized
+# flavour
+# * include/asm-m32r/io.h change dropped - this arch didn't exist in 2.6.8
+#
+diff -urN kernel-source-2.6.8-2.6.8.orig/Documentation/DocBook/deviceiobook.tmpl kernel-source-2.6.8-2.6.8/Documentation/DocBook/deviceiobook.tmpl
+--- kernel-source-2.6.8-2.6.8.orig/Documentation/DocBook/deviceiobook.tmpl 2004-08-13 23:36:57.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/Documentation/DocBook/deviceiobook.tmpl 2006-09-18 18:22:05.416530160 -0600
+@@ -147,8 +147,7 @@
+ compiler is not permitted to reorder the I/O sequence. When the
+ ordering can be compiler optimised, you can use <function>
+ __readb</function> and friends to indicate the relaxed ordering. Use
+- this with care. The <function>rmb</function> provides a read memory
+- barrier. The <function>wmb</function> provides a write memory barrier.
++ this with care.
+ </para>
+
+ <para>
+@@ -159,8 +158,70 @@
+ asynchronously. A driver author must issue a read from the same
+ device to ensure that writes have occurred in the specific cases the
+ author cares. This kind of property cannot be hidden from driver
+- writers in the API.
+- </para>
++ writers in the API. In some cases, the read used to flush the device
++ may be expected to fail (if the card is resetting, for example). In
++ that case, the read should be done from config space, which is
++ guaranteed to soft-fail if the card doesn't respond.
++ </para>
++
++ <para>
++ The following is an example of flushing a write to a device when
++ the driver would like to ensure the write's effects are visible prior
++ to continuing execution.
++ </para>
++
++<programlisting>
++static inline void
++qla1280_disable_intrs(struct scsi_qla_host *ha)
++{
++ struct device_reg *reg;
++
++ reg = ha->iobase;
++ /* disable risc and host interrupts */
++ WRT_REG_WORD(&reg->ictrl, 0);
++ /*
++ * The following read will ensure that the above write
++ * has been received by the device before we return from this
++ * function.
++ */
++ RD_REG_WORD(&reg->ictrl);
++ ha->flags.ints_enabled = 0;
++}
++</programlisting>
++
++ <para>
++ In addition to write posting, on some large multiprocessing systems
++ (e.g. SGI Challenge, Origin and Altix machines) posted writes won't
++ be strongly ordered coming from different CPUs. Thus it's important
++ to properly protect parts of your driver that do memory-mapped writes
++ with locks and use the <function>mmiowb</function> to make sure they
++ arrive in the order intended.
++ </para>
++
++ <para>
++ Generally, one should use <function>mmiowb</function> prior to
++ releasing a spinlock that protects regions using <function>writeb
++ </function> or similar functions that aren't surrounded by <function>
++ readb</function> calls, which will ensure ordering and flushing. The
++ following example (again from qla1280.c) illustrates its use.
++ </para>
++
++<programlisting>
++ sp->flags |= SRB_SENT;
++ ha->actthreads++;
++ WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
++
++ /*
++ * A Memory Mapped I/O Write Barrier is needed to ensure that this write
++ * of the request queue in register is ordered ahead of writes issued
++ * after this one by other CPUs. Access to the register is protected
++ * by the host_lock. Without the mmiowb, however, it is possible for
++ * this CPU to release the host lock, another CPU acquire the host lock,
++ * and write to the request queue in, and have the second write make it
++ * to the chip first.
++ */
++ mmiowb(); /* posted write ordering */
++</programlisting>
+
+ <para>
+ PCI ordering rules also guarantee that PIO read responses arrive
+@@ -171,7 +232,9 @@
+ <function>readb</function> call has no relation to any previous DMA
+ writes performed by the device. The driver can use
+ <function>readb_relaxed</function> for these cases, although only
+- some platforms will honor the relaxed semantics.
++ some platforms will honor the relaxed semantics. Using the relaxed
++ read functions will provide significant performance benefits on
++ platforms that support it.
+ </para>
+ </sect1>
+
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-alpha/io.h kernel-source-2.6.8-2.6.8/include/asm-alpha/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-alpha/io.h 2004-08-13 23:37:41.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-alpha/io.h 2006-09-18 18:22:12.984379672 -0600
+@@ -488,6 +488,8 @@
+ }
+
+
++#define mmiowb()
++
+ /*
+ * ISA space is mapped to some machine-specific location on Alpha.
+ * Call into the existing hooks to get the address translated.
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-arm/io.h kernel-source-2.6.8-2.6.8/include/asm-arm/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-arm/io.h 2004-08-13 23:36:45.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-arm/io.h 2006-09-18 18:22:12.984379672 -0600
+@@ -135,6 +135,8 @@
+ extern void _memcpy_toio(unsigned long, const void *, size_t);
+ extern void _memset_io(unsigned long, int, size_t);
+
++#define mmiowb()
++
+ /*
+ * Memory access primitives
+ * ------------------------
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-arm26/io.h kernel-source-2.6.8-2.6.8/include/asm-arm26/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-arm26/io.h 2004-08-13 23:37:15.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-arm26/io.h 2006-09-18 18:22:12.985379520 -0600
+@@ -320,6 +320,8 @@
+ #define writesw(p,d,l) __readwrite_bug("writesw")
+ #define writesl(p,d,l) __readwrite_bug("writesl")
+
++#define mmiowb()
++
+ /* the following macro is depreciated */
+ #define ioaddr(port) __ioaddr((port))
+
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-cris/io.h kernel-source-2.6.8-2.6.8/include/asm-cris/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-cris/io.h 2004-08-13 23:37:37.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-cris/io.h 2006-09-18 18:22:12.985379520 -0600
+@@ -56,6 +56,8 @@
+ #define __raw_writew writew
+ #define __raw_writel writel
+
++#define mmiowb()
++
+ #define memset_io(a,b,c) memset((void *)(a),(b),(c))
+ #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+ #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-h8300/io.h kernel-source-2.6.8-2.6.8/include/asm-h8300/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-h8300/io.h 2004-08-13 23:37:14.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-h8300/io.h 2006-09-18 18:22:12.985379520 -0600
+@@ -200,6 +200,8 @@
+ #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+ #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
++#define mmiowb()
++
+ #define inb(addr) ((h8300_buswidth(addr))?readw((addr) & ~1) & 0xff:readb(addr))
+ #define inw(addr) _swapw(readw(addr))
+ #define inl(addr) _swapl(readl(addr))
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-i386/io.h kernel-source-2.6.8-2.6.8/include/asm-i386/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-i386/io.h 2004-08-13 23:38:09.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-i386/io.h 2006-09-18 18:22:58.277494072 -0600
+@@ -156,6 +156,8 @@
+ #define __raw_writew writew
+ #define __raw_writel writel
+
++#define mmiowb()
++
+ #define memset_io(a,b,c) memset((void *)(a),(b),(c))
+ #define memcpy_fromio(a,b,c) __memcpy((a),(void *)(b),(c))
+ #define memcpy_toio(a,b,c) __memcpy((void *)(a),(b),(c))
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/io.h kernel-source-2.6.8-2.6.8/include/asm-ia64/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/io.h 2004-08-13 23:36:13.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ia64/io.h 2006-09-18 18:22:12.986379368 -0600
+@@ -91,6 +91,20 @@
+ */
+ #define __ia64_mf_a() ia64_mfa()
+
++/**
++ * __ia64_mmiowb - I/O write barrier
++ *
++ * Ensure ordering of I/O space writes. This will make sure that writes
++ * following the barrier will arrive after all previous writes. For most
++ * ia64 platforms, this is a simple 'mf.a' instruction.
++ *
++ * See Documentation/DocBook/deviceiobook.tmpl for more information.
++ */
++static inline void __ia64_mmiowb(void)
++{
++ ia64_mfa();
++}
++
+ static inline const unsigned long
+ __ia64_get_io_port_base (void)
+ {
+@@ -267,6 +281,7 @@
+ #define __outb platform_outb
+ #define __outw platform_outw
+ #define __outl platform_outl
++#define __mmiowb platform_mmiowb
+
+ #define inb(p) __inb(p)
+ #define inw(p) __inw(p)
+@@ -280,6 +295,7 @@
+ #define outsb(p,s,c) __outsb(p,s,c)
+ #define outsw(p,s,c) __outsw(p,s,c)
+ #define outsl(p,s,c) __outsl(p,s,c)
++#define mmiowb() __mmiowb()
+
+ /*
+ * The address passed to these functions are ioremap()ped already.
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec.h kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec.h 2004-08-13 23:36:59.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec.h 2006-09-18 18:23:54.021019768 -0600
+@@ -62,6 +62,7 @@
+ typedef void ia64_mv_outb_t (unsigned char, unsigned long);
+ typedef void ia64_mv_outw_t (unsigned short, unsigned long);
+ typedef void ia64_mv_outl_t (unsigned int, unsigned long);
++typedef void ia64_mv_mmiowb_t (void);
+ typedef unsigned char ia64_mv_readb_t (void *);
+ typedef unsigned short ia64_mv_readw_t (void *);
+ typedef unsigned int ia64_mv_readl_t (void *);
+@@ -130,6 +131,7 @@
+ # define platform_outb ia64_mv.outb
+ # define platform_outw ia64_mv.outw
+ # define platform_outl ia64_mv.outl
++# define platform_mmiowb ia64_mv.mmiowb
+ # define platform_readb ia64_mv.readb
+ # define platform_readw ia64_mv.readw
+ # define platform_readl ia64_mv.readl
+@@ -176,6 +178,7 @@
+ ia64_mv_outb_t *outb;
+ ia64_mv_outw_t *outw;
+ ia64_mv_outl_t *outl;
++ ia64_mv_mmiowb_t *mmiowb;
+ ia64_mv_readb_t *readb;
+ ia64_mv_readw_t *readw;
+ ia64_mv_readl_t *readl;
+@@ -218,6 +221,7 @@
+ platform_outb, \
+ platform_outw, \
+ platform_outl, \
++ platform_mmiowb, \
+ platform_readb, \
+ platform_readw, \
+ platform_readl, \
+@@ -344,6 +348,9 @@
+ #ifndef platform_outl
+ # define platform_outl __ia64_outl
+ #endif
++#ifndef platform_mmiowb
++# define platform_mmiowb __ia64_mmiowb
++#endif
+ #ifndef platform_readb
+ # define platform_readb __ia64_readb
+ #endif
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec_init.h kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec_init.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec_init.h 2004-08-13 23:36:12.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec_init.h 2006-09-18 18:22:12.987379216 -0600
+@@ -12,6 +12,7 @@
+ extern ia64_mv_outb_t __ia64_outb;
+ extern ia64_mv_outw_t __ia64_outw;
+ extern ia64_mv_outl_t __ia64_outl;
++extern ia64_mv_mmiowb_t __ia64_mmiowb;
+ extern ia64_mv_readb_t __ia64_readb;
+ extern ia64_mv_readw_t __ia64_readw;
+ extern ia64_mv_readl_t __ia64_readl;
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec_sn2.h kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec_sn2.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ia64/machvec_sn2.h 2004-08-13 23:36:56.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ia64/machvec_sn2.h 2006-09-18 18:22:12.987379216 -0600
+@@ -49,6 +49,7 @@
+ extern ia64_mv_outb_t __sn_outb;
+ extern ia64_mv_outw_t __sn_outw;
+ extern ia64_mv_outl_t __sn_outl;
++extern ia64_mv_mmiowb_t __sn_mmiowb;
+ extern ia64_mv_readb_t __sn_readb;
+ extern ia64_mv_readw_t __sn_readw;
+ extern ia64_mv_readl_t __sn_readl;
+@@ -92,6 +93,7 @@
+ #define platform_outb __sn_outb
+ #define platform_outw __sn_outw
+ #define platform_outl __sn_outl
++#define platform_mmiowb __sn_mmiowb
+ #define platform_readb __sn_readb
+ #define platform_readw __sn_readw
+ #define platform_readl __sn_readl
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-m68k/io.h kernel-source-2.6.8-2.6.8/include/asm-m68k/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-m68k/io.h 2004-08-13 23:37:15.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-m68k/io.h 2006-09-18 18:22:22.934866968 -0600
+@@ -306,6 +306,7 @@
+ #endif
+ #endif /* CONFIG_PCI */
+
++#define mmiowb()
+
+ static inline void *ioremap(unsigned long physaddr, unsigned long size)
+ {
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-m68knommu/io.h kernel-source-2.6.8-2.6.8/include/asm-m68knommu/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-m68knommu/io.h 2004-08-13 23:36:56.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-m68knommu/io.h 2006-09-18 18:22:22.934866968 -0600
+@@ -102,6 +102,8 @@
+ *bp++ = _swapl(*ap);
+ }
+
++#define mmiowb()
++
+ /*
+ * make the short names macros so specific devices
+ * can override them as required
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-mips/io.h kernel-source-2.6.8-2.6.8/include/asm-mips/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-mips/io.h 2004-08-13 23:36:56.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-mips/io.h 2006-09-18 18:22:22.934866968 -0600
+@@ -290,6 +290,10 @@
+ #define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
+ #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
+ #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
++
++/* Depends on MIPS III instruction set */
++#define mmiowb() asm volatile ("sync" ::: "memory")
++
+ #ifdef CONFIG_MIPS32
+ #define ____raw_writeq(val,addr) \
+ ({ \
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-parisc/io.h kernel-source-2.6.8-2.6.8/include/asm-parisc/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-parisc/io.h 2004-08-13 23:36:17.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-parisc/io.h 2006-09-18 18:22:22.935866816 -0600
+@@ -177,6 +177,8 @@
+ #define readl_relaxed(addr) readl(addr)
+ #define readq_relaxed(addr) readq(addr)
+
++#define mmiowb()
++
+ extern void __memcpy_fromio(unsigned long dest, unsigned long src, int count);
+ extern void __memcpy_toio(unsigned long dest, unsigned long src, int count);
+ extern void __memset_io(unsigned long dest, char fill, int count);
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ppc/io.h kernel-source-2.6.8-2.6.8/include/asm-ppc/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ppc/io.h 2004-08-13 23:37:38.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ppc/io.h 2006-09-18 18:22:22.935866816 -0600
+@@ -215,6 +215,8 @@
+ extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
+ unsigned int size, int flags);
+
++#define mmiowb()
++
+ /*
+ * The PCI bus is inherently Little-Endian. The PowerPC is being
+ * run Big-Endian. Thus all values which cross the [PCI] barrier
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-ppc64/io.h kernel-source-2.6.8-2.6.8/include/asm-ppc64/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-ppc64/io.h 2004-08-13 23:38:04.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-ppc64/io.h 2006-09-18 18:22:22.936866664 -0600
+@@ -123,6 +123,8 @@
+ extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+
++#define mmiowb()
++
+ /*
+ * output pause versions need a delay at least for the
+ * w83c105 ide controller in a p610.
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-s390/io.h kernel-source-2.6.8-2.6.8/include/asm-s390/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-s390/io.h 2004-08-13 23:37:25.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-s390/io.h 2006-09-18 18:22:22.936866664 -0600
+@@ -105,6 +105,8 @@
+ #define outb(x,addr) ((void) writeb(x,addr))
+ #define outb_p(x,addr) outb(x,addr)
+
++#define mmiowb()
++
+ #endif /* __KERNEL__ */
+
+ #endif
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-sh/io.h kernel-source-2.6.8-2.6.8/include/asm-sh/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-sh/io.h 2004-08-13 23:37:14.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-sh/io.h 2006-09-18 18:22:22.936866664 -0600
+@@ -134,6 +134,8 @@
+ #define readw_relaxed(a) readw(a)
+ #define readl_relaxed(a) readl(a)
+
++#define mmiowb()
++
+ /*
+ * If the platform has PC-like I/O, this function converts the offset into
+ * an address.
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-sh64/io.h kernel-source-2.6.8-2.6.8/include/asm-sh64/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-sh64/io.h 2004-08-13 23:36:56.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-sh64/io.h 2006-09-18 18:22:22.936866664 -0600
+@@ -86,6 +86,9 @@
+ #define readb(addr) sh64_in8(addr)
+ #define readw(addr) sh64_in16(addr)
+ #define readl(addr) sh64_in32(addr)
++#define readb_relaxed(addr) sh64_in8(addr)
++#define readw_relaxed(addr) sh64_in16(addr)
++#define readl_relaxed(addr) sh64_in32(addr)
+
+ #define writeb(b, addr) sh64_out8(b, addr)
+ #define writew(b, addr) sh64_out16(b, addr)
+@@ -106,6 +109,8 @@
+ void outw(unsigned long value, unsigned long port);
+ void outl(unsigned long value, unsigned long port);
+
++#define mmiowb()
++
+ #ifdef __KERNEL__
+
+ #ifdef CONFIG_SH_CAYMAN
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-sparc/io.h kernel-source-2.6.8-2.6.8/include/asm-sparc/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-sparc/io.h 2004-08-13 23:36:16.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-sparc/io.h 2006-09-18 18:22:22.937866512 -0600
+@@ -23,6 +23,8 @@
+ return ((w&0xff) << 8) | ((w>>8)&0xff);
+ }
+
++#define mmiowb()
++
+ /*
+ * Memory mapped I/O to PCI
+ *
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-sparc64/io.h kernel-source-2.6.8-2.6.8/include/asm-sparc64/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-sparc64/io.h 2004-08-13 23:37:40.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-sparc64/io.h 2006-09-18 18:22:22.937866512 -0600
+@@ -439,6 +439,8 @@
+ return retval;
+ }
+
++#define mmiowb()
++
+ #ifdef __KERNEL__
+
+ /* On sparc64 we have the whole physical IO address space accessible
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-v850/io.h kernel-source-2.6.8-2.6.8/include/asm-v850/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-v850/io.h 2004-08-13 23:36:16.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-v850/io.h 2006-09-18 18:22:22.937866512 -0600
+@@ -102,6 +102,8 @@
+ #define ioremap_writethrough(physaddr, size) (physaddr)
+ #define ioremap_fullcache(physaddr, size) (physaddr)
+
++#define mmiowb()
++
+ #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
+ #if 0
+ /* This is really stupid; don't define it. */
+diff -urN kernel-source-2.6.8-2.6.8.orig/include/asm-x86_64/io.h kernel-source-2.6.8-2.6.8/include/asm-x86_64/io.h
+--- kernel-source-2.6.8-2.6.8.orig/include/asm-x86_64/io.h 2004-08-13 23:36:56.000000000 -0600
++++ kernel-source-2.6.8-2.6.8/include/asm-x86_64/io.h 2006-09-18 18:23:26.133259352 -0600
+@@ -186,6 +186,8 @@
+ #define __raw_readl readl
+ #define __raw_readq readq
+
++#define mmiowb()
++
+ #define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
+ #define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
+ #define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mptscsih-use-common-msleep_interruptible.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/mptscsih-use-common-msleep_interruptible.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,16 @@
+--- kernel-source-2.6.8-2.6.8/drivers/message/fusion/linux_compat.h~ 2006-09-18 18:39:08.996922000 -0600
++++ kernel-source-2.6.8-2.6.8/drivers/message/fusion/linux_compat.h 2006-09-18 19:17:50.317027992 -0600
+@@ -56,13 +56,6 @@
+ schedule_timeout(msecs_to_jiffies(msecs) + 1);
+ }
+ #endif
+-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
+-static void inline msleep_interruptible(unsigned long msecs)
+-{
+- set_current_state(TASK_INTERRUPTIBLE);
+- schedule_timeout(msecs_to_jiffies(msecs) + 1);
+-}
+-#endif
+
+ /* define __iomem which came in lk 2.6.9
+ * to be backward compatible to older variants of lk 2.6
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/msleep_interruptible-add.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/msleep_interruptible-add.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,52 @@
+diff -Naru a/include/linux/delay.h b/include/linux/delay.h
+--- a/include/linux/delay.h 2006-09-19 01:10:29 -07:00
++++ b/include/linux/delay.h 2006-09-19 01:10:29 -07:00
+@@ -39,6 +39,7 @@
+ #endif
+
+ void msleep(unsigned int msecs);
++unsigned long msleep_interruptible(unsigned int msecs);
+
+ static inline void ssleep(unsigned int seconds)
+ {
+diff -Naru a/kernel/timer.c b/kernel/timer.c
+--- a/kernel/timer.c 2006-09-19 01:10:29 -07:00
++++ b/kernel/timer.c 2006-09-19 01:10:29 -07:00
+@@ -1507,3 +1507,19 @@
+
+ EXPORT_SYMBOL(msleep);
+
++/**
++ * msleep_interruptible - sleep waiting for waitqueue interruptions
++ * @msecs: Time in milliseconds to sleep for
++ */
++unsigned long msleep_interruptible(unsigned int msecs)
++{
++ unsigned long timeout = msecs_to_jiffies(msecs);
++
++ while (timeout && !signal_pending(current)) {
++ set_current_state(TASK_INTERRUPTIBLE);
++ timeout = schedule_timeout(timeout);
++ }
++ return jiffies_to_msecs(timeout);
++}
++
++EXPORT_SYMBOL(msleep_interruptible);
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2004/09/03 10:35:44-07:00 janitor at sternwelten.at
+# [PATCH] Add msleep_interruptible() function to kernel/timer.c
+#
+# Signed-off-by: Maximilian Attems <janitor at sternwelten.at>
+# Signed-off-by: Andrew Morton <akpm at osdl.org>
+# Signed-off-by: Linus Torvalds <torvalds at osdl.org>
+#
+# include/linux/delay.h
+# 2004/09/03 02:08:32-07:00 janitor at sternwelten.at +1 -0
+# Add msleep_interruptible() function to kernel/timer.c
+#
+# kernel/timer.c
+# 2004/09/03 02:08:32-07:00 janitor at sternwelten.at +16 -0
+# Add msleep_interruptible() function to kernel/timer.c
+#
Modified: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/series/2.6.8-16sarge5dannf1
==============================================================================
--- people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/series/2.6.8-16sarge5dannf1 (original)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/series/2.6.8-16sarge5dannf1 Wed Oct 11 16:40:55 2006
@@ -7,3 +7,13 @@
+ drivers-net-e1000-6.2.15.dpatch
+ cciss_2.6.2_to_2.6.10.dpatch
+ ata-update-to-2.6.10.dpatch
++ msleep_interruptible-add.dpatch
++ mptscsih-use-common-msleep_interruptible.dpatch
++ skb-header-release.dpatch
++ skb-header-cloned.dpatch
++ broadcom-mii-constants.dpatch
++ mii-gige-support.dpatch
++ mmiowb-define.dpatch
++ i386-atomic_add_return-define.dpatch
++ bnx2-1.4.43-backport.dpatch
++ amd64-atomic_add_return-define.dpatch
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-cloned.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-cloned.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,109 @@
+diff -Naru a/drivers/net/tg3.c b/drivers/net/tg3.c
+--- a/drivers/net/tg3.c 2006-09-19 01:13:37 -07:00
++++ b/drivers/net/tg3.c 2006-09-19 01:13:37 -07:00
+@@ -3110,6 +3110,12 @@
+ (mss = skb_shinfo(skb)->tso_size) != 0) {
+ int tcp_opt_len, ip_tcp_len;
+
++ if (skb_header_cloned(skb) &&
++ pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
++ dev_kfree_skb(skb);
++ goto out_unlock;
++ }
++
+ tcp_opt_len = ((skb->h.th->doff - 5) * 4);
+ ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
+
+diff -Naru a/include/linux/skbuff.h b/include/linux/skbuff.h
+--- a/include/linux/skbuff.h 2006-09-19 01:13:37 -07:00
++++ b/include/linux/skbuff.h 2006-09-19 01:13:37 -07:00
+@@ -391,6 +391,25 @@
+ }
+
+ /**
++ * skb_header_cloned - is the header a clone
++ * @skb: buffer to check
++ *
++ * Returns true if modifying the header part of the buffer requires
++ * the data to be copied.
++ */
++static inline int skb_header_cloned(const struct sk_buff *skb)
++{
++ int dataref;
++
++ if (!skb->cloned)
++ return 0;
++
++ dataref = atomic_read(&skb_shinfo(skb)->dataref);
++ dataref = (dataref & SKB_DATAREF_MASK) - (dataref >> SKB_DATAREF_SHIFT);
++ return dataref != 1;
++}
++
++/**
+ * skb_header_release - release reference to header
+ * @skb: buffer to operate on
+ *
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2005/02/23 19:18:34-08:00 herbert at gondor.apana.org.au
+# [NET]: Add skb_header_cloned and use it in e1000/tg3
+#
+# This patch adds skb_header_cloned which tells us whether we need to
+# copy the data before we can modify the header part of the skb. Again,
+# what constitutes the header is left up to the users of the skb to define.
+#
+# This patch then uses this function in e1000/tg3 to copy the data before
+# the TCP/IP header is modified.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# drivers/net/e1000/e1000_main.c
+# 2005/02/23 19:18:14-08:00 herbert at gondor.apana.org.au +18 -4
+# [NET]: Add skb_header_cloned and use it in e1000/tg3
+#
+# This patch adds skb_header_cloned which tells us whether we need to
+# copy the data before we can modify the header part of the skb. Again,
+# what constitutes the header is left up to the users of the skb to define.
+#
+# This patch then uses this function in e1000/tg3 to copy the data before
+# the TCP/IP header is modified.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# drivers/net/tg3.c
+# 2005/02/23 19:18:14-08:00 herbert at gondor.apana.org.au +6 -0
+# [NET]: Add skb_header_cloned and use it in e1000/tg3
+#
+# This patch adds skb_header_cloned which tells us whether we need to
+# copy the data before we can modify the header part of the skb. Again,
+# what constitutes the header is left up to the users of the skb to define.
+#
+# This patch then uses this function in e1000/tg3 to copy the data before
+# the TCP/IP header is modified.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# include/linux/skbuff.h
+# 2005/02/23 19:18:14-08:00 herbert at gondor.apana.org.au +19 -0
+# [NET]: Add skb_header_cloned and use it in e1000/tg3
+#
+# This patch adds skb_header_cloned which tells us whether we need to
+# copy the data before we can modify the header part of the skb. Again,
+# what constitutes the header is left up to the users of the skb to define.
+#
+# This patch then uses this function in e1000/tg3 to copy the data before
+# the TCP/IP header is modified.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+
+#
+# Backported to Debian's 2.6.8 by dann frazier <dannf at hp.com>
+# * e1000 changes were already backported in a e1000 driver version upgrade
+# so they were dropped from this patch
+#
\ No newline at end of file
Added: people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-release.dpatch
==============================================================================
--- (empty file)
+++ people/dannf/kernel-source-2.6.8-2.6.8/debian/patches/skb-header-release.dpatch Wed Oct 11 16:40:55 2006
@@ -0,0 +1,211 @@
+diff -Naru a/include/linux/skbuff.h b/include/linux/skbuff.h
+--- a/include/linux/skbuff.h 2006-09-19 01:16:54 -07:00
++++ b/include/linux/skbuff.h 2006-09-19 01:16:54 -07:00
+@@ -146,6 +146,20 @@
+ skb_frag_t frags[MAX_SKB_FRAGS];
+ };
+
++/* We divide dataref into two halves. The higher 16 bits hold references
++ * to the payload part of skb->data. The lower 16 bits hold references to
++ * the entire skb->data. It is up to the users of the skb to agree on
++ * where the payload starts.
++ *
++ * All users must obey the rule that the skb->data reference count must be
++ * greater than or equal to the payload reference count.
++ *
++ * Holding a reference to the payload part means that the user does not
++ * care about modifications to the header part of skb->data.
++ */
++#define SKB_DATAREF_SHIFT 16
++#define SKB_DATAREF_MASK ((1 << SKB_DATAREF_SHIFT) - 1)
++
+ /**
+ * struct sk_buff - socket buffer
+ * @next: Next buffer in list
+@@ -167,6 +181,7 @@
+ * @csum: Checksum
+ * @__unused: Dead field, may be reused
+ * @cloned: Head may be cloned (check refcnt to be sure)
++ * @nohdr: Payload reference only, must not modify header
+ * @pkt_type: Packet class
+ * @ip_summed: Driver fed us an IP checksum
+ * @priority: Packet queueing priority
+@@ -238,7 +253,8 @@
+ mac_len,
+ csum;
+ unsigned char local_df,
+- cloned,
++ cloned:1,
++ nohdr:1,
+ pkt_type,
+ ip_summed;
+ __u32 priority;
+@@ -370,7 +386,23 @@
+ */
+ static inline int skb_cloned(const struct sk_buff *skb)
+ {
+- return skb->cloned && atomic_read(&skb_shinfo(skb)->dataref) != 1;
++ return skb->cloned &&
++ (atomic_read(&skb_shinfo(skb)->dataref) & SKB_DATAREF_MASK) != 1;
++}
++
++/**
++ * skb_header_release - release reference to header
++ * @skb: buffer to operate on
++ *
++ * Drop a reference to the header part of the buffer. This is done
++ * by acquiring a payload reference. You must not read from the header
++ * part of skb->data after this.
++ */
++static inline void skb_header_release(struct sk_buff *skb)
++{
++ BUG_ON(skb->nohdr);
++ skb->nohdr = 1;
++ atomic_add(1 << SKB_DATAREF_SHIFT, &skb_shinfo(skb)->dataref);
+ }
+
+ /**
+diff -Naru a/net/core/skbuff.c b/net/core/skbuff.c
+--- a/net/core/skbuff.c 2006-09-19 01:16:54 -07:00
++++ b/net/core/skbuff.c 2006-09-19 01:16:54 -07:00
+@@ -241,7 +241,8 @@
+ void skb_release_data(struct sk_buff *skb)
+ {
+ if (!skb->cloned ||
+- atomic_dec_and_test(&(skb_shinfo(skb)->dataref))) {
++ !atomic_sub_return(skb->nohdr ? (1 << SKB_DATAREF_SHIFT) + 1 : 1,
++ &skb_shinfo(skb)->dataref)) {
+ if (skb_shinfo(skb)->nr_frags) {
+ int i;
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
+@@ -353,6 +354,7 @@
+ C(csum);
+ C(local_df);
+ n->cloned = 1;
++ n->nohdr = 0;
+ C(pkt_type);
+ C(ip_summed);
+ C(priority);
+@@ -604,6 +606,7 @@
+ skb->h.raw += off;
+ skb->nh.raw += off;
+ skb->cloned = 0;
++ skb->nohdr = 0;
+ atomic_set(&skb_shinfo(skb)->dataref, 1);
+ return 0;
+
+diff -Naru a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+--- a/net/ipv4/tcp.c 2006-09-19 01:16:54 -07:00
++++ b/net/ipv4/tcp.c 2006-09-19 01:16:54 -07:00
+@@ -598,6 +598,7 @@
+ TCP_SKB_CB(skb)->end_seq = tp->write_seq;
+ TCP_SKB_CB(skb)->flags = TCPCB_FLAG_ACK;
+ TCP_SKB_CB(skb)->sacked = 0;
++ skb_header_release(skb);
+ __skb_queue_tail(&sk->sk_write_queue, skb);
+ sk_charge_skb(sk, skb);
+ if (!sk->sk_send_head)
+diff -Naru a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
+--- a/net/ipv4/tcp_output.c 2006-09-19 01:16:54 -07:00
++++ b/net/ipv4/tcp_output.c 2006-09-19 01:16:54 -07:00
+@@ -400,6 +400,7 @@
+
+ /* Advance write_seq and place onto the write_queue. */
+ tp->write_seq = TCP_SKB_CB(skb)->end_seq;
++ skb_header_release(skb);
+ __skb_queue_tail(&sk->sk_write_queue, skb);
+ sk_charge_skb(sk, skb);
+
+@@ -1340,6 +1341,7 @@
+ if (nskb == NULL)
+ return -ENOMEM;
+ __skb_unlink(skb, &sk->sk_write_queue);
++ skb_header_release(nskb);
+ __skb_queue_head(&sk->sk_write_queue, nskb);
+ sk_stream_free_skb(sk, skb);
+ sk_charge_skb(sk, nskb);
+@@ -1506,6 +1508,7 @@
+ /* Send it off. */
+ TCP_SKB_CB(buff)->when = tcp_time_stamp;
+ tp->retrans_stamp = TCP_SKB_CB(buff)->when;
++ skb_header_release(buff);
+ __skb_queue_tail(&sk->sk_write_queue, buff);
+ sk_charge_skb(sk, buff);
+ tp->packets_out += tcp_skb_pcount(buff);
+# This is a BitKeeper generated diff -Nru style patch.
+#
+# ChangeSet
+# 2005/02/23 19:17:24-08:00 herbert at gondor.apana.org.au
+# [NET]: Add skb_header_release and use it in net/ipv4/tcp
+#
+# This patch adds skb_header_release which can be called when the owner
+# of an skb no longer needs to access the header at all. What constitutes
+# the header is left up to the users of the skb to define.
+#
+# For instance, for outbound TCP packets we define the header to be
+# anything in front of the TCP payload. Therefore we add skb_header_release
+# calls to all the paths where outound TCP packets are produced.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# include/linux/skbuff.h
+# 2005/02/23 19:16:58-08:00 herbert at gondor.apana.org.au +34 -2
+# [NET]: Add skb_header_release and use it in net/ipv4/tcp
+#
+# This patch adds skb_header_release which can be called when the owner
+# of an skb no longer needs to access the header at all. What constitutes
+# the header is left up to the users of the skb to define.
+#
+# For instance, for outbound TCP packets we define the header to be
+# anything in front of the TCP payload. Therefore we add skb_header_release
+# calls to all the paths where outound TCP packets are produced.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# net/core/skbuff.c
+# 2005/02/23 19:16:58-08:00 herbert at gondor.apana.org.au +4 -1
+# [NET]: Add skb_header_release and use it in net/ipv4/tcp
+#
+# This patch adds skb_header_release which can be called when the owner
+# of an skb no longer needs to access the header at all. What constitutes
+# the header is left up to the users of the skb to define.
+#
+# For instance, for outbound TCP packets we define the header to be
+# anything in front of the TCP payload. Therefore we add skb_header_release
+# calls to all the paths where outound TCP packets are produced.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# net/ipv4/tcp.c
+# 2005/02/23 19:16:58-08:00 herbert at gondor.apana.org.au +1 -0
+# [NET]: Add skb_header_release and use it in net/ipv4/tcp
+#
+# This patch adds skb_header_release which can be called when the owner
+# of an skb no longer needs to access the header at all. What constitutes
+# the header is left up to the users of the skb to define.
+#
+# For instance, for outbound TCP packets we define the header to be
+# anything in front of the TCP payload. Therefore we add skb_header_release
+# calls to all the paths where outound TCP packets are produced.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
+# net/ipv4/tcp_output.c
+# 2005/02/23 19:16:59-08:00 herbert at gondor.apana.org.au +3 -0
+# [NET]: Add skb_header_release and use it in net/ipv4/tcp
+#
+# This patch adds skb_header_release which can be called when the owner
+# of an skb no longer needs to access the header at all. What constitutes
+# the header is left up to the users of the skb to define.
+#
+# For instance, for outbound TCP packets we define the header to be
+# anything in front of the TCP payload. Therefore we add skb_header_release
+# calls to all the paths where outound TCP packets are produced.
+#
+# Signed-off-by: Herbert Xu <herbert at gondor.apana.org.au>
+# Signed-off-by: David S. Miller <davem at davemloft.net>
+#
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