[kernel] r14004 - in people/dannf/lenny-bnx2x/debian/patches: features/all series
Dann Frazier
dannf at alioth.debian.org
Sat Jul 25 00:06:11 UTC 2009
Author: dannf
Date: Sat Jul 25 00:06:07 2009
New Revision: 14004
Log:
update; now it no only loads, but actually works
Modified:
people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-2.6.30.patch
people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-Separated-FW-from-the-source.patch
people/dannf/lenny-bnx2x/debian/patches/series/15lenny2bnx2x
Modified: people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-2.6.30.patch
==============================================================================
--- people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-2.6.30.patch Fri Jul 24 22:11:45 2009 (r14003)
+++ people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-2.6.30.patch Sat Jul 25 00:06:07 2009 (r14004)
@@ -1,45 +1,32 @@
-This is a backport of the majority of changesets between 2.6.26
-and 2.6.30 that apply to the bnx2x driver. The following changesets
-were omitted because they either make changes external to the driver
-or depend on interfaces that were not available in 2.6.26
-
-523cb50b265360e87152382ea0984b624e4f7d29
-74bc8ebcfd56a1ea01d855d9eebc2533cef66f19
-299133cf739c8e5aca4ee7dff3c5673f380f5c2e
-e523287e8edad79b4e5753f98dcf8f75cabd3963
-8d8bb39b9eba32dd70e87fd5ad5c5dd4ba118e06
-228428428138e231a155464239880201e5cc8b44
-fde9403a982218fa8a437f815e7aa0e583e2d6ed
-e174961ca1a0b28f7abf0be47973ad57cb74e5f0
-7c510e4b730a92cecf94ada45c989d8be0200d47
-275f165fa970174f8a98205529750e8abb6c0a33
-babcda74e9d96bb58fd9c6c5112dbdbff169e695
-9eeda9abd1faf489f3df9a1f557975f4c8650363
-c64213cd138cf9815839f7278b5eee89d31fbacb
-908a7a16b852ffd618a9127be8d62432182d81b4
-2d5451d2614583de0c9aaf61cf5f77faf5694105
-025dfdafe77f20b3890981a394774baab7b9c827
-288379f050284087578b77e04f040b57db3db3f8
-3eacdf58c2c0b9507afedfc19108e98b992c31e4
-0c8dfc830aadd978e461dad66c33741b71c6a0be
-555f6c78373f969f14487253abe331d085449360
-8badd27aa0d7c02572fcd1a4a3c6b57d67f40b78
-de832a55d28bdcc38a3f3c160554d2dfa5a62069
-748e543974eec6afb1f55f8430781150d0da8b0a
-1c06328c0345638ea7532b45cadfe713c9e9781e
-8440d2b63667c7d09ccbe43b8bd928d3c4662879
-2059aba7e40afb18e578ce57cc48fc3c782a531b
-c3eefaf676646281c07f93cb523a7be4eab67f8c
-916c775ff297dc60219a4f0e5527ba6ab4a88ed4
-db434ac6bff0d991d0b60166dc9d6405b873d0f7
-d5df2a16133f4eb22f9a6bbc07723443568d362f
-763dccdc8e9775b247c3ea86ae8f5f592c12024e
-6a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01
-284901a90a9e0b812ca3f5f852cbbfb60d10249d
-
-diff -urpN a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
---- a/drivers/net/bnx2x.c 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x.c 1969-12-31 17:00:00.000000000 -0700
+diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
+index f4182cf..0c58943 100644
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -2574,6 +2574,7 @@ config BNX2X
+ tristate "Broadcom NetXtremeII 10Gb support"
+ depends on PCI
+ select ZLIB_INFLATE
++ select LIBCRC32C
+ help
+ This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
+ To compile this driver as a module, choose M here: the module
+diff --git a/drivers/net/Makefile b/drivers/net/Makefile
+index dcbfe84..29c6697 100644
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -67,6 +67,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
+ obj-$(CONFIG_TIGON3) += tg3.o
+ obj-$(CONFIG_BNX2) += bnx2.o
+ obj-$(CONFIG_BNX2X) += bnx2x.o
++bnx2x-objs := bnx2x_main.o bnx2x_link.o
+ spidernet-y += spider_net.o spider_net_ethtool.o
+ obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
+ obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
+diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
+deleted file mode 100644
+index 70cba64..0000000
+--- a/drivers/net/bnx2x.c
++++ /dev/null
@@ -1,9988 +0,0 @@
-/* bnx2x.c: Broadcom Everest network driver.
- *
@@ -10029,1243 +10016,155 @@
-module_init(bnx2x_init);
-module_exit(bnx2x_cleanup);
-
-diff -urpN a/drivers/net/bnx2x_dump.h b/drivers/net/bnx2x_dump.h
---- a/drivers/net/bnx2x_dump.h 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_dump.h 2009-05-28 01:52:09.000000000 -0600
-@@ -0,0 +1,526 @@
-+/* bnx2x_dump.h: Broadcom Everest network driver.
-+ *
-+ * Copyright (c) 2009 Broadcom Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation.
-+ */
-+
-+
-+/* This struct holds a signature to ensure the dump returned from the driver
-+ * match the meta data file inserted to grc_dump.tcl
-+ * The signature is time stamp, diag version and grc_dump version
-+ */
-+
-+struct dump_sign {
-+ u32 time_stamp;
-+ u32 diag_ver;
-+ u32 grc_dump_ver;
-+};
-+
-+#define TSTORM_WAITP_ADDR 0x1b8a80
-+#define CSTORM_WAITP_ADDR 0x238a80
-+#define XSTORM_WAITP_ADDR 0x2b8a80
-+#define USTORM_WAITP_ADDR 0x338a80
-+#define TSTORM_CAM_MODE 0x1b1440
-+
-+#define RI_E1 0x1
-+#define RI_E1H 0x2
-+#define RI_ONLINE 0x100
-+
-+#define RI_E1_OFFLINE (RI_E1)
-+#define RI_E1_ONLINE (RI_E1 | RI_ONLINE)
-+#define RI_E1H_OFFLINE (RI_E1H)
-+#define RI_E1H_ONLINE (RI_E1H | RI_ONLINE)
-+#define RI_ALL_OFFLINE (RI_E1 | RI_E1H)
-+#define RI_ALL_ONLINE (RI_E1 | RI_E1H | RI_ONLINE)
-+
-+#define MAX_TIMER_PENDING 200
-+#define TIMER_SCAN_DONT_CARE 0xFF
-+
-+
-+struct dump_hdr {
-+ u32 hdr_size; /* in dwords, excluding this field */
-+ struct dump_sign dump_sign;
-+ u32 xstorm_waitp;
-+ u32 tstorm_waitp;
-+ u32 ustorm_waitp;
-+ u32 cstorm_waitp;
-+ u16 info;
-+ u8 idle_chk;
-+ u8 reserved;
-+};
-+
-+struct reg_addr {
-+ u32 addr;
-+ u32 size;
-+ u16 info;
-+};
-+
-+struct wreg_addr {
-+ u32 addr;
-+ u32 size;
-+ u32 read_regs_count;
-+ const u32 *read_regs;
-+ u16 info;
-+};
-+
-+
-+#define REGS_COUNT 558
-+static const struct reg_addr reg_addrs[REGS_COUNT] = {
-+ { 0x2000, 341, RI_ALL_ONLINE}, { 0x2800, 103, RI_ALL_ONLINE},
-+ { 0x3000, 287, RI_ALL_ONLINE}, { 0x3800, 331, RI_ALL_ONLINE},
-+ { 0x8800, 6, RI_E1_ONLINE}, { 0xa000, 223, RI_ALL_ONLINE},
-+ { 0xa388, 1, RI_ALL_ONLINE}, { 0xa398, 1, RI_ALL_ONLINE},
-+ { 0xa39c, 7, RI_E1H_ONLINE}, { 0xa3c0, 3, RI_E1H_ONLINE},
-+ { 0xa3d0, 1, RI_E1H_ONLINE}, { 0xa3d8, 1, RI_E1H_ONLINE},
-+ { 0xa3e0, 1, RI_E1H_ONLINE}, { 0xa3e8, 1, RI_E1H_ONLINE},
-+ { 0xa3f0, 1, RI_E1H_ONLINE}, { 0xa3f8, 1, RI_E1H_ONLINE},
-+ { 0xa400, 69, RI_ALL_ONLINE}, { 0xa518, 1, RI_ALL_ONLINE},
-+ { 0xa520, 1, RI_ALL_ONLINE}, { 0xa528, 1, RI_ALL_ONLINE},
-+ { 0xa530, 1, RI_ALL_ONLINE}, { 0xa538, 1, RI_ALL_ONLINE},
-+ { 0xa540, 1, RI_ALL_ONLINE}, { 0xa548, 1, RI_ALL_ONLINE},
-+ { 0xa550, 1, RI_ALL_ONLINE}, { 0xa558, 1, RI_ALL_ONLINE},
-+ { 0xa560, 1, RI_ALL_ONLINE}, { 0xa568, 1, RI_ALL_ONLINE},
-+ { 0xa570, 1, RI_ALL_ONLINE}, { 0xa580, 1, RI_ALL_ONLINE},
-+ { 0xa590, 1, RI_ALL_ONLINE}, { 0xa5a0, 1, RI_ALL_ONLINE},
-+ { 0xa5c0, 1, RI_ALL_ONLINE}, { 0xa5e0, 1, RI_E1H_ONLINE},
-+ { 0xa5e8, 1, RI_E1H_ONLINE}, { 0xa5f0, 1, RI_E1H_ONLINE},
-+ { 0xa5f8, 10, RI_E1H_ONLINE}, { 0x10000, 236, RI_ALL_ONLINE},
-+ { 0x103bc, 1, RI_ALL_ONLINE}, { 0x103cc, 1, RI_ALL_ONLINE},
-+ { 0x103dc, 1, RI_ALL_ONLINE}, { 0x10400, 57, RI_ALL_ONLINE},
-+ { 0x104e8, 2, RI_ALL_ONLINE}, { 0x104f4, 2, RI_ALL_ONLINE},
-+ { 0x10500, 146, RI_ALL_ONLINE}, { 0x10750, 2, RI_ALL_ONLINE},
-+ { 0x10760, 2, RI_ALL_ONLINE}, { 0x10770, 2, RI_ALL_ONLINE},
-+ { 0x10780, 2, RI_ALL_ONLINE}, { 0x10790, 2, RI_ALL_ONLINE},
-+ { 0x107a0, 2, RI_ALL_ONLINE}, { 0x107b0, 2, RI_ALL_ONLINE},
-+ { 0x107c0, 2, RI_ALL_ONLINE}, { 0x107d0, 2, RI_ALL_ONLINE},
-+ { 0x107e0, 2, RI_ALL_ONLINE}, { 0x10880, 2, RI_ALL_ONLINE},
-+ { 0x10900, 2, RI_ALL_ONLINE}, { 0x12000, 1, RI_ALL_ONLINE},
-+ { 0x14000, 1, RI_ALL_ONLINE}, { 0x16000, 26, RI_E1H_ONLINE},
-+ { 0x16070, 18, RI_E1H_ONLINE}, { 0x160c0, 27, RI_E1H_ONLINE},
-+ { 0x16140, 1, RI_E1H_ONLINE}, { 0x16160, 1, RI_E1H_ONLINE},
-+ { 0x16180, 2, RI_E1H_ONLINE}, { 0x161c0, 2, RI_E1H_ONLINE},
-+ { 0x16204, 5, RI_E1H_ONLINE}, { 0x18000, 1, RI_E1H_ONLINE},
-+ { 0x18008, 1, RI_E1H_ONLINE}, { 0x20000, 24, RI_ALL_ONLINE},
-+ { 0x20060, 8, RI_ALL_ONLINE}, { 0x20080, 138, RI_ALL_ONLINE},
-+ { 0x202b4, 1, RI_ALL_ONLINE}, { 0x202c4, 1, RI_ALL_ONLINE},
-+ { 0x20400, 2, RI_ALL_ONLINE}, { 0x2040c, 8, RI_ALL_ONLINE},
-+ { 0x2042c, 18, RI_E1H_ONLINE}, { 0x20480, 1, RI_ALL_ONLINE},
-+ { 0x20500, 1, RI_ALL_ONLINE}, { 0x20600, 1, RI_ALL_ONLINE},
-+ { 0x28000, 1, RI_ALL_ONLINE}, { 0x28004, 8191, RI_ALL_OFFLINE},
-+ { 0x30000, 1, RI_ALL_ONLINE}, { 0x30004, 16383, RI_ALL_OFFLINE},
-+ { 0x40000, 98, RI_ALL_ONLINE}, { 0x40194, 1, RI_ALL_ONLINE},
-+ { 0x401a4, 1, RI_ALL_ONLINE}, { 0x401a8, 11, RI_E1H_ONLINE},
-+ { 0x40200, 4, RI_ALL_ONLINE}, { 0x40400, 43, RI_ALL_ONLINE},
-+ { 0x404b8, 1, RI_ALL_ONLINE}, { 0x404c8, 1, RI_ALL_ONLINE},
-+ { 0x404cc, 3, RI_E1H_ONLINE}, { 0x40500, 2, RI_ALL_ONLINE},
-+ { 0x40510, 2, RI_ALL_ONLINE}, { 0x40520, 2, RI_ALL_ONLINE},
-+ { 0x40530, 2, RI_ALL_ONLINE}, { 0x40540, 2, RI_ALL_ONLINE},
-+ { 0x42000, 164, RI_ALL_ONLINE}, { 0x4229c, 1, RI_ALL_ONLINE},
-+ { 0x422ac, 1, RI_ALL_ONLINE}, { 0x422bc, 1, RI_ALL_ONLINE},
-+ { 0x422d4, 5, RI_E1H_ONLINE}, { 0x42400, 49, RI_ALL_ONLINE},
-+ { 0x424c8, 38, RI_ALL_ONLINE}, { 0x42568, 2, RI_ALL_ONLINE},
-+ { 0x42800, 1, RI_ALL_ONLINE}, { 0x50000, 20, RI_ALL_ONLINE},
-+ { 0x50050, 8, RI_ALL_ONLINE}, { 0x50070, 88, RI_ALL_ONLINE},
-+ { 0x501dc, 1, RI_ALL_ONLINE}, { 0x501ec, 1, RI_ALL_ONLINE},
-+ { 0x501f0, 4, RI_E1H_ONLINE}, { 0x50200, 2, RI_ALL_ONLINE},
-+ { 0x5020c, 7, RI_ALL_ONLINE}, { 0x50228, 6, RI_E1H_ONLINE},
-+ { 0x50240, 1, RI_ALL_ONLINE}, { 0x50280, 1, RI_ALL_ONLINE},
-+ { 0x52000, 1, RI_ALL_ONLINE}, { 0x54000, 1, RI_ALL_ONLINE},
-+ { 0x54004, 3327, RI_ALL_OFFLINE}, { 0x58000, 1, RI_ALL_ONLINE},
-+ { 0x58004, 8191, RI_ALL_OFFLINE}, { 0x60000, 71, RI_ALL_ONLINE},
-+ { 0x60128, 1, RI_ALL_ONLINE}, { 0x60138, 1, RI_ALL_ONLINE},
-+ { 0x6013c, 24, RI_E1H_ONLINE}, { 0x60200, 1, RI_ALL_ONLINE},
-+ { 0x61000, 1, RI_ALL_ONLINE}, { 0x61004, 511, RI_ALL_OFFLINE},
-+ { 0x70000, 8, RI_ALL_ONLINE}, { 0x70020, 21496, RI_ALL_OFFLINE},
-+ { 0x85000, 3, RI_ALL_ONLINE}, { 0x8500c, 4, RI_ALL_OFFLINE},
-+ { 0x8501c, 7, RI_ALL_ONLINE}, { 0x85038, 4, RI_ALL_OFFLINE},
-+ { 0x85048, 1, RI_ALL_ONLINE}, { 0x8504c, 109, RI_ALL_OFFLINE},
-+ { 0x85200, 32, RI_ALL_ONLINE}, { 0x85280, 11104, RI_ALL_OFFLINE},
-+ { 0xa0000, 16384, RI_ALL_ONLINE}, { 0xb0000, 16384, RI_E1H_ONLINE},
-+ { 0xc1000, 7, RI_ALL_ONLINE}, { 0xc1028, 1, RI_ALL_ONLINE},
-+ { 0xc1038, 1, RI_ALL_ONLINE}, { 0xc1800, 2, RI_ALL_ONLINE},
-+ { 0xc2000, 164, RI_ALL_ONLINE}, { 0xc229c, 1, RI_ALL_ONLINE},
-+ { 0xc22ac, 1, RI_ALL_ONLINE}, { 0xc22bc, 1, RI_ALL_ONLINE},
-+ { 0xc2400, 49, RI_ALL_ONLINE}, { 0xc24c8, 38, RI_ALL_ONLINE},
-+ { 0xc2568, 2, RI_ALL_ONLINE}, { 0xc2600, 1, RI_ALL_ONLINE},
-+ { 0xc4000, 165, RI_ALL_ONLINE}, { 0xc42a0, 1, RI_ALL_ONLINE},
-+ { 0xc42b0, 1, RI_ALL_ONLINE}, { 0xc42c0, 1, RI_ALL_ONLINE},
-+ { 0xc42e0, 7, RI_E1H_ONLINE}, { 0xc4400, 51, RI_ALL_ONLINE},
-+ { 0xc44d0, 38, RI_ALL_ONLINE}, { 0xc4570, 2, RI_ALL_ONLINE},
-+ { 0xc4600, 1, RI_ALL_ONLINE}, { 0xd0000, 19, RI_ALL_ONLINE},
-+ { 0xd004c, 8, RI_ALL_ONLINE}, { 0xd006c, 91, RI_ALL_ONLINE},
-+ { 0xd01e4, 1, RI_ALL_ONLINE}, { 0xd01f4, 1, RI_ALL_ONLINE},
-+ { 0xd0200, 2, RI_ALL_ONLINE}, { 0xd020c, 7, RI_ALL_ONLINE},
-+ { 0xd0228, 18, RI_E1H_ONLINE}, { 0xd0280, 1, RI_ALL_ONLINE},
-+ { 0xd0300, 1, RI_ALL_ONLINE}, { 0xd0400, 1, RI_ALL_ONLINE},
-+ { 0xd4000, 1, RI_ALL_ONLINE}, { 0xd4004, 2559, RI_ALL_OFFLINE},
-+ { 0xd8000, 1, RI_ALL_ONLINE}, { 0xd8004, 8191, RI_ALL_OFFLINE},
-+ { 0xe0000, 21, RI_ALL_ONLINE}, { 0xe0054, 8, RI_ALL_ONLINE},
-+ { 0xe0074, 85, RI_ALL_ONLINE}, { 0xe01d4, 1, RI_ALL_ONLINE},
-+ { 0xe01e4, 1, RI_ALL_ONLINE}, { 0xe0200, 2, RI_ALL_ONLINE},
-+ { 0xe020c, 8, RI_ALL_ONLINE}, { 0xe022c, 18, RI_E1H_ONLINE},
-+ { 0xe0280, 1, RI_ALL_ONLINE}, { 0xe0300, 1, RI_ALL_ONLINE},
-+ { 0xe1000, 1, RI_ALL_ONLINE}, { 0xe2000, 1, RI_ALL_ONLINE},
-+ { 0xe2004, 2047, RI_ALL_OFFLINE}, { 0xf0000, 1, RI_ALL_ONLINE},
-+ { 0xf0004, 16383, RI_ALL_OFFLINE}, { 0x101000, 12, RI_ALL_ONLINE},
-+ { 0x10103c, 1, RI_ALL_ONLINE}, { 0x10104c, 1, RI_ALL_ONLINE},
-+ { 0x101050, 1, RI_E1H_ONLINE}, { 0x101100, 1, RI_ALL_ONLINE},
-+ { 0x101800, 8, RI_ALL_ONLINE}, { 0x102000, 18, RI_ALL_ONLINE},
-+ { 0x102054, 1, RI_ALL_ONLINE}, { 0x102064, 1, RI_ALL_ONLINE},
-+ { 0x102080, 17, RI_ALL_ONLINE}, { 0x1020c8, 8, RI_E1H_ONLINE},
-+ { 0x102400, 1, RI_ALL_ONLINE}, { 0x103000, 26, RI_ALL_ONLINE},
-+ { 0x103074, 1, RI_ALL_ONLINE}, { 0x103084, 1, RI_ALL_ONLINE},
-+ { 0x103094, 1, RI_ALL_ONLINE}, { 0x103098, 5, RI_E1H_ONLINE},
-+ { 0x103800, 8, RI_ALL_ONLINE}, { 0x104000, 63, RI_ALL_ONLINE},
-+ { 0x104108, 1, RI_ALL_ONLINE}, { 0x104118, 1, RI_ALL_ONLINE},
-+ { 0x104200, 17, RI_ALL_ONLINE}, { 0x104400, 64, RI_ALL_ONLINE},
-+ { 0x104500, 192, RI_ALL_OFFLINE}, { 0x104800, 64, RI_ALL_ONLINE},
-+ { 0x104900, 192, RI_ALL_OFFLINE}, { 0x105000, 7, RI_ALL_ONLINE},
-+ { 0x10501c, 1, RI_ALL_OFFLINE}, { 0x105020, 3, RI_ALL_ONLINE},
-+ { 0x10502c, 1, RI_ALL_OFFLINE}, { 0x105030, 3, RI_ALL_ONLINE},
-+ { 0x10503c, 1, RI_ALL_OFFLINE}, { 0x105040, 3, RI_ALL_ONLINE},
-+ { 0x10504c, 1, RI_ALL_OFFLINE}, { 0x105050, 3, RI_ALL_ONLINE},
-+ { 0x10505c, 1, RI_ALL_OFFLINE}, { 0x105060, 3, RI_ALL_ONLINE},
-+ { 0x10506c, 1, RI_ALL_OFFLINE}, { 0x105070, 3, RI_ALL_ONLINE},
-+ { 0x10507c, 1, RI_ALL_OFFLINE}, { 0x105080, 3, RI_ALL_ONLINE},
-+ { 0x10508c, 1, RI_ALL_OFFLINE}, { 0x105090, 3, RI_ALL_ONLINE},
-+ { 0x10509c, 1, RI_ALL_OFFLINE}, { 0x1050a0, 3, RI_ALL_ONLINE},
-+ { 0x1050ac, 1, RI_ALL_OFFLINE}, { 0x1050b0, 3, RI_ALL_ONLINE},
-+ { 0x1050bc, 1, RI_ALL_OFFLINE}, { 0x1050c0, 3, RI_ALL_ONLINE},
-+ { 0x1050cc, 1, RI_ALL_OFFLINE}, { 0x1050d0, 3, RI_ALL_ONLINE},
-+ { 0x1050dc, 1, RI_ALL_OFFLINE}, { 0x1050e0, 3, RI_ALL_ONLINE},
-+ { 0x1050ec, 1, RI_ALL_OFFLINE}, { 0x1050f0, 3, RI_ALL_ONLINE},
-+ { 0x1050fc, 1, RI_ALL_OFFLINE}, { 0x105100, 3, RI_ALL_ONLINE},
-+ { 0x10510c, 1, RI_ALL_OFFLINE}, { 0x105110, 3, RI_ALL_ONLINE},
-+ { 0x10511c, 1, RI_ALL_OFFLINE}, { 0x105120, 3, RI_ALL_ONLINE},
-+ { 0x10512c, 1, RI_ALL_OFFLINE}, { 0x105130, 3, RI_ALL_ONLINE},
-+ { 0x10513c, 1, RI_ALL_OFFLINE}, { 0x105140, 3, RI_ALL_ONLINE},
-+ { 0x10514c, 1, RI_ALL_OFFLINE}, { 0x105150, 3, RI_ALL_ONLINE},
-+ { 0x10515c, 1, RI_ALL_OFFLINE}, { 0x105160, 3, RI_ALL_ONLINE},
-+ { 0x10516c, 1, RI_ALL_OFFLINE}, { 0x105170, 3, RI_ALL_ONLINE},
-+ { 0x10517c, 1, RI_ALL_OFFLINE}, { 0x105180, 3, RI_ALL_ONLINE},
-+ { 0x10518c, 1, RI_ALL_OFFLINE}, { 0x105190, 3, RI_ALL_ONLINE},
-+ { 0x10519c, 1, RI_ALL_OFFLINE}, { 0x1051a0, 3, RI_ALL_ONLINE},
-+ { 0x1051ac, 1, RI_ALL_OFFLINE}, { 0x1051b0, 3, RI_ALL_ONLINE},
-+ { 0x1051bc, 1, RI_ALL_OFFLINE}, { 0x1051c0, 3, RI_ALL_ONLINE},
-+ { 0x1051cc, 1, RI_ALL_OFFLINE}, { 0x1051d0, 3, RI_ALL_ONLINE},
-+ { 0x1051dc, 1, RI_ALL_OFFLINE}, { 0x1051e0, 3, RI_ALL_ONLINE},
-+ { 0x1051ec, 1, RI_ALL_OFFLINE}, { 0x1051f0, 3, RI_ALL_ONLINE},
-+ { 0x1051fc, 1, RI_ALL_OFFLINE}, { 0x105200, 3, RI_ALL_ONLINE},
-+ { 0x10520c, 1, RI_ALL_OFFLINE}, { 0x105210, 3, RI_ALL_ONLINE},
-+ { 0x10521c, 1, RI_ALL_OFFLINE}, { 0x105220, 3, RI_ALL_ONLINE},
-+ { 0x10522c, 1, RI_ALL_OFFLINE}, { 0x105230, 3, RI_ALL_ONLINE},
-+ { 0x10523c, 1, RI_ALL_OFFLINE}, { 0x105240, 3, RI_ALL_ONLINE},
-+ { 0x10524c, 1, RI_ALL_OFFLINE}, { 0x105250, 3, RI_ALL_ONLINE},
-+ { 0x10525c, 1, RI_ALL_OFFLINE}, { 0x105260, 3, RI_ALL_ONLINE},
-+ { 0x10526c, 1, RI_ALL_OFFLINE}, { 0x105270, 3, RI_ALL_ONLINE},
-+ { 0x10527c, 1, RI_ALL_OFFLINE}, { 0x105280, 3, RI_ALL_ONLINE},
-+ { 0x10528c, 1, RI_ALL_OFFLINE}, { 0x105290, 3, RI_ALL_ONLINE},
-+ { 0x10529c, 1, RI_ALL_OFFLINE}, { 0x1052a0, 3, RI_ALL_ONLINE},
-+ { 0x1052ac, 1, RI_ALL_OFFLINE}, { 0x1052b0, 3, RI_ALL_ONLINE},
-+ { 0x1052bc, 1, RI_ALL_OFFLINE}, { 0x1052c0, 3, RI_ALL_ONLINE},
-+ { 0x1052cc, 1, RI_ALL_OFFLINE}, { 0x1052d0, 3, RI_ALL_ONLINE},
-+ { 0x1052dc, 1, RI_ALL_OFFLINE}, { 0x1052e0, 3, RI_ALL_ONLINE},
-+ { 0x1052ec, 1, RI_ALL_OFFLINE}, { 0x1052f0, 3, RI_ALL_ONLINE},
-+ { 0x1052fc, 1, RI_ALL_OFFLINE}, { 0x105300, 3, RI_ALL_ONLINE},
-+ { 0x10530c, 1, RI_ALL_OFFLINE}, { 0x105310, 3, RI_ALL_ONLINE},
-+ { 0x10531c, 1, RI_ALL_OFFLINE}, { 0x105320, 3, RI_ALL_ONLINE},
-+ { 0x10532c, 1, RI_ALL_OFFLINE}, { 0x105330, 3, RI_ALL_ONLINE},
-+ { 0x10533c, 1, RI_ALL_OFFLINE}, { 0x105340, 3, RI_ALL_ONLINE},
-+ { 0x10534c, 1, RI_ALL_OFFLINE}, { 0x105350, 3, RI_ALL_ONLINE},
-+ { 0x10535c, 1, RI_ALL_OFFLINE}, { 0x105360, 3, RI_ALL_ONLINE},
-+ { 0x10536c, 1, RI_ALL_OFFLINE}, { 0x105370, 3, RI_ALL_ONLINE},
-+ { 0x10537c, 1, RI_ALL_OFFLINE}, { 0x105380, 3, RI_ALL_ONLINE},
-+ { 0x10538c, 1, RI_ALL_OFFLINE}, { 0x105390, 3, RI_ALL_ONLINE},
-+ { 0x10539c, 1, RI_ALL_OFFLINE}, { 0x1053a0, 3, RI_ALL_ONLINE},
-+ { 0x1053ac, 1, RI_ALL_OFFLINE}, { 0x1053b0, 3, RI_ALL_ONLINE},
-+ { 0x1053bc, 1, RI_ALL_OFFLINE}, { 0x1053c0, 3, RI_ALL_ONLINE},
-+ { 0x1053cc, 1, RI_ALL_OFFLINE}, { 0x1053d0, 3, RI_ALL_ONLINE},
-+ { 0x1053dc, 1, RI_ALL_OFFLINE}, { 0x1053e0, 3, RI_ALL_ONLINE},
-+ { 0x1053ec, 1, RI_ALL_OFFLINE}, { 0x1053f0, 3, RI_ALL_ONLINE},
-+ { 0x1053fc, 769, RI_ALL_OFFLINE}, { 0x108000, 33, RI_ALL_ONLINE},
-+ { 0x108090, 1, RI_ALL_ONLINE}, { 0x1080a0, 1, RI_ALL_ONLINE},
-+ { 0x1080ac, 5, RI_E1H_ONLINE}, { 0x108100, 5, RI_ALL_ONLINE},
-+ { 0x108120, 5, RI_ALL_ONLINE}, { 0x108200, 74, RI_ALL_ONLINE},
-+ { 0x108400, 74, RI_ALL_ONLINE}, { 0x108800, 152, RI_ALL_ONLINE},
-+ { 0x109000, 1, RI_ALL_ONLINE}, { 0x120000, 347, RI_ALL_ONLINE},
-+ { 0x120578, 1, RI_ALL_ONLINE}, { 0x120588, 1, RI_ALL_ONLINE},
-+ { 0x120598, 1, RI_ALL_ONLINE}, { 0x12059c, 23, RI_E1H_ONLINE},
-+ { 0x120614, 1, RI_E1H_ONLINE}, { 0x12061c, 30, RI_E1H_ONLINE},
-+ { 0x12080c, 65, RI_ALL_ONLINE}, { 0x120a00, 2, RI_ALL_ONLINE},
-+ { 0x122000, 2, RI_ALL_ONLINE}, { 0x128000, 2, RI_E1H_ONLINE},
-+ { 0x140000, 114, RI_ALL_ONLINE}, { 0x1401d4, 1, RI_ALL_ONLINE},
-+ { 0x1401e4, 1, RI_ALL_ONLINE}, { 0x140200, 6, RI_ALL_ONLINE},
-+ { 0x144000, 4, RI_ALL_ONLINE}, { 0x148000, 4, RI_ALL_ONLINE},
-+ { 0x14c000, 4, RI_ALL_ONLINE}, { 0x150000, 4, RI_ALL_ONLINE},
-+ { 0x154000, 4, RI_ALL_ONLINE}, { 0x158000, 4, RI_ALL_ONLINE},
-+ { 0x15c000, 7, RI_E1H_ONLINE}, { 0x161000, 7, RI_ALL_ONLINE},
-+ { 0x161028, 1, RI_ALL_ONLINE}, { 0x161038, 1, RI_ALL_ONLINE},
-+ { 0x161800, 2, RI_ALL_ONLINE}, { 0x164000, 60, RI_ALL_ONLINE},
-+ { 0x1640fc, 1, RI_ALL_ONLINE}, { 0x16410c, 1, RI_ALL_ONLINE},
-+ { 0x164110, 2, RI_E1H_ONLINE}, { 0x164200, 1, RI_ALL_ONLINE},
-+ { 0x164208, 1, RI_ALL_ONLINE}, { 0x164210, 1, RI_ALL_ONLINE},
-+ { 0x164218, 1, RI_ALL_ONLINE}, { 0x164220, 1, RI_ALL_ONLINE},
-+ { 0x164228, 1, RI_ALL_ONLINE}, { 0x164230, 1, RI_ALL_ONLINE},
-+ { 0x164238, 1, RI_ALL_ONLINE}, { 0x164240, 1, RI_ALL_ONLINE},
-+ { 0x164248, 1, RI_ALL_ONLINE}, { 0x164250, 1, RI_ALL_ONLINE},
-+ { 0x164258, 1, RI_ALL_ONLINE}, { 0x164260, 1, RI_ALL_ONLINE},
-+ { 0x164270, 2, RI_ALL_ONLINE}, { 0x164280, 2, RI_ALL_ONLINE},
-+ { 0x164800, 2, RI_ALL_ONLINE}, { 0x165000, 2, RI_ALL_ONLINE},
-+ { 0x166000, 164, RI_ALL_ONLINE}, { 0x16629c, 1, RI_ALL_ONLINE},
-+ { 0x1662ac, 1, RI_ALL_ONLINE}, { 0x1662bc, 1, RI_ALL_ONLINE},
-+ { 0x166400, 49, RI_ALL_ONLINE}, { 0x1664c8, 38, RI_ALL_ONLINE},
-+ { 0x166568, 2, RI_ALL_ONLINE}, { 0x166800, 1, RI_ALL_ONLINE},
-+ { 0x168000, 270, RI_ALL_ONLINE}, { 0x168444, 1, RI_ALL_ONLINE},
-+ { 0x168454, 1, RI_ALL_ONLINE}, { 0x168800, 19, RI_ALL_ONLINE},
-+ { 0x168900, 1, RI_ALL_ONLINE}, { 0x168a00, 128, RI_ALL_ONLINE},
-+ { 0x16a000, 1, RI_ALL_ONLINE}, { 0x16a004, 1535, RI_ALL_OFFLINE},
-+ { 0x16c000, 1, RI_ALL_ONLINE}, { 0x16c004, 1535, RI_ALL_OFFLINE},
-+ { 0x16e000, 16, RI_E1H_ONLINE}, { 0x16e100, 1, RI_E1H_ONLINE},
-+ { 0x16e200, 2, RI_E1H_ONLINE}, { 0x16e400, 183, RI_E1H_ONLINE},
-+ { 0x170000, 93, RI_ALL_ONLINE}, { 0x170180, 1, RI_ALL_ONLINE},
-+ { 0x170190, 1, RI_ALL_ONLINE}, { 0x170200, 4, RI_ALL_ONLINE},
-+ { 0x170214, 1, RI_ALL_ONLINE}, { 0x178000, 1, RI_ALL_ONLINE},
-+ { 0x180000, 61, RI_ALL_ONLINE}, { 0x180100, 1, RI_ALL_ONLINE},
-+ { 0x180110, 1, RI_ALL_ONLINE}, { 0x180120, 1, RI_ALL_ONLINE},
-+ { 0x180130, 1, RI_ALL_ONLINE}, { 0x18013c, 2, RI_E1H_ONLINE},
-+ { 0x180200, 58, RI_ALL_ONLINE}, { 0x180340, 4, RI_ALL_ONLINE},
-+ { 0x180400, 1, RI_ALL_ONLINE}, { 0x180404, 255, RI_ALL_OFFLINE},
-+ { 0x181000, 4, RI_ALL_ONLINE}, { 0x181010, 1020, RI_ALL_OFFLINE},
-+ { 0x1a0000, 1, RI_ALL_ONLINE}, { 0x1a0004, 1023, RI_ALL_OFFLINE},
-+ { 0x1a1000, 1, RI_ALL_ONLINE}, { 0x1a1004, 4607, RI_ALL_OFFLINE},
-+ { 0x1a5800, 2560, RI_E1H_OFFLINE}, { 0x1a8000, 64, RI_ALL_OFFLINE},
-+ { 0x1a8100, 1984, RI_E1H_OFFLINE}, { 0x1aa000, 1, RI_E1H_ONLINE},
-+ { 0x1aa004, 6655, RI_E1H_OFFLINE}, { 0x1b1800, 128, RI_ALL_OFFLINE},
-+ { 0x1b1c00, 128, RI_ALL_OFFLINE}, { 0x1b2000, 1, RI_ALL_OFFLINE},
-+ { 0x1b2400, 64, RI_E1H_OFFLINE}, { 0x1b8200, 1, RI_ALL_ONLINE},
-+ { 0x1b8240, 1, RI_ALL_ONLINE}, { 0x1b8280, 1, RI_ALL_ONLINE},
-+ { 0x1b82c0, 1, RI_ALL_ONLINE}, { 0x1b8a00, 1, RI_ALL_ONLINE},
-+ { 0x1b8a80, 1, RI_ALL_ONLINE}, { 0x1c0000, 2, RI_ALL_ONLINE},
-+ { 0x200000, 65, RI_ALL_ONLINE}, { 0x200110, 1, RI_ALL_ONLINE},
-+ { 0x200120, 1, RI_ALL_ONLINE}, { 0x200130, 1, RI_ALL_ONLINE},
-+ { 0x200140, 1, RI_ALL_ONLINE}, { 0x20014c, 2, RI_E1H_ONLINE},
-+ { 0x200200, 58, RI_ALL_ONLINE}, { 0x200340, 4, RI_ALL_ONLINE},
-+ { 0x200400, 1, RI_ALL_ONLINE}, { 0x200404, 255, RI_ALL_OFFLINE},
-+ { 0x202000, 4, RI_ALL_ONLINE}, { 0x202010, 2044, RI_ALL_OFFLINE},
-+ { 0x220000, 1, RI_ALL_ONLINE}, { 0x220004, 1023, RI_ALL_OFFLINE},
-+ { 0x221000, 1, RI_ALL_ONLINE}, { 0x221004, 4607, RI_ALL_OFFLINE},
-+ { 0x225800, 1536, RI_E1H_OFFLINE}, { 0x227000, 1, RI_E1H_ONLINE},
-+ { 0x227004, 1023, RI_E1H_OFFLINE}, { 0x228000, 64, RI_ALL_OFFLINE},
-+ { 0x228100, 8640, RI_E1H_OFFLINE}, { 0x231800, 128, RI_ALL_OFFLINE},
-+ { 0x231c00, 128, RI_ALL_OFFLINE}, { 0x232000, 1, RI_ALL_OFFLINE},
-+ { 0x232400, 64, RI_E1H_OFFLINE}, { 0x238200, 1, RI_ALL_ONLINE},
-+ { 0x238240, 1, RI_ALL_ONLINE}, { 0x238280, 1, RI_ALL_ONLINE},
-+ { 0x2382c0, 1, RI_ALL_ONLINE}, { 0x238a00, 1, RI_ALL_ONLINE},
-+ { 0x238a80, 1, RI_ALL_ONLINE}, { 0x240000, 2, RI_ALL_ONLINE},
-+ { 0x280000, 65, RI_ALL_ONLINE}, { 0x280110, 1, RI_ALL_ONLINE},
-+ { 0x280120, 1, RI_ALL_ONLINE}, { 0x280130, 1, RI_ALL_ONLINE},
-+ { 0x280140, 1, RI_ALL_ONLINE}, { 0x28014c, 2, RI_E1H_ONLINE},
-+ { 0x280200, 58, RI_ALL_ONLINE}, { 0x280340, 4, RI_ALL_ONLINE},
-+ { 0x280400, 1, RI_ALL_ONLINE}, { 0x280404, 255, RI_ALL_OFFLINE},
-+ { 0x282000, 4, RI_ALL_ONLINE}, { 0x282010, 2044, RI_ALL_OFFLINE},
-+ { 0x2a0000, 1, RI_ALL_ONLINE}, { 0x2a0004, 1023, RI_ALL_OFFLINE},
-+ { 0x2a1000, 1, RI_ALL_ONLINE}, { 0x2a1004, 4607, RI_ALL_OFFLINE},
-+ { 0x2a5800, 2560, RI_E1H_OFFLINE}, { 0x2a8000, 64, RI_ALL_OFFLINE},
-+ { 0x2a8100, 960, RI_E1H_OFFLINE}, { 0x2a9000, 1, RI_E1H_ONLINE},
-+ { 0x2a9004, 7679, RI_E1H_OFFLINE}, { 0x2b1800, 128, RI_ALL_OFFLINE},
-+ { 0x2b1c00, 128, RI_ALL_OFFLINE}, { 0x2b2000, 1, RI_ALL_OFFLINE},
-+ { 0x2b2400, 64, RI_E1H_OFFLINE}, { 0x2b8200, 1, RI_ALL_ONLINE},
-+ { 0x2b8240, 1, RI_ALL_ONLINE}, { 0x2b8280, 1, RI_ALL_ONLINE},
-+ { 0x2b82c0, 1, RI_ALL_ONLINE}, { 0x2b8a00, 1, RI_ALL_ONLINE},
-+ { 0x2b8a80, 1, RI_ALL_ONLINE}, { 0x2c0000, 2, RI_ALL_ONLINE},
-+ { 0x300000, 65, RI_ALL_ONLINE}, { 0x300110, 1, RI_ALL_ONLINE},
-+ { 0x300120, 1, RI_ALL_ONLINE}, { 0x300130, 1, RI_ALL_ONLINE},
-+ { 0x300140, 1, RI_ALL_ONLINE}, { 0x30014c, 2, RI_E1H_ONLINE},
-+ { 0x300200, 58, RI_ALL_ONLINE}, { 0x300340, 4, RI_ALL_ONLINE},
-+ { 0x300400, 1, RI_ALL_ONLINE}, { 0x300404, 255, RI_ALL_OFFLINE},
-+ { 0x302000, 4, RI_ALL_ONLINE}, { 0x302010, 2044, RI_ALL_OFFLINE},
-+ { 0x320000, 1, RI_ALL_ONLINE}, { 0x320004, 1023, RI_ALL_OFFLINE},
-+ { 0x321000, 1, RI_ALL_ONLINE}, { 0x321004, 4607, RI_ALL_OFFLINE},
-+ { 0x325800, 2560, RI_E1H_OFFLINE}, { 0x328000, 64, RI_ALL_OFFLINE},
-+ { 0x328100, 536, RI_E1H_OFFLINE}, { 0x328960, 1, RI_E1H_ONLINE},
-+ { 0x328964, 8103, RI_E1H_OFFLINE}, { 0x331800, 128, RI_ALL_OFFLINE},
-+ { 0x331c00, 128, RI_ALL_OFFLINE}, { 0x332000, 1, RI_ALL_OFFLINE},
-+ { 0x332400, 64, RI_E1H_OFFLINE}, { 0x338200, 1, RI_ALL_ONLINE},
-+ { 0x338240, 1, RI_ALL_ONLINE}, { 0x338280, 1, RI_ALL_ONLINE},
-+ { 0x3382c0, 1, RI_ALL_ONLINE}, { 0x338a00, 1, RI_ALL_ONLINE},
-+ { 0x338a80, 1, RI_ALL_ONLINE}, { 0x340000, 2, RI_ALL_ONLINE}
-+};
-+
-+
-+#define IDLEREGS_COUNT 277
-+static const struct reg_addr idle_addrs[IDLEREGS_COUNT] = {
-+ { 0x2114, 1, RI_ALL_ONLINE}, { 0x2120, 1, RI_ALL_ONLINE},
-+ { 0x212c, 4, RI_ALL_ONLINE}, { 0x2814, 1, RI_ALL_ONLINE},
-+ { 0x281c, 2, RI_ALL_ONLINE}, { 0xa38c, 1, RI_ALL_ONLINE},
-+ { 0xa408, 1, RI_ALL_ONLINE}, { 0xa42c, 12, RI_ALL_ONLINE},
-+ { 0xa600, 5, RI_E1H_ONLINE}, { 0xa618, 1, RI_E1H_ONLINE},
-+ { 0xc09c, 1, RI_ALL_ONLINE}, { 0x103b0, 1, RI_ALL_ONLINE},
-+ { 0x103c0, 1, RI_ALL_ONLINE}, { 0x103d0, 1, RI_E1H_ONLINE},
-+ { 0x2021c, 11, RI_ALL_ONLINE}, { 0x202a8, 1, RI_ALL_ONLINE},
-+ { 0x202b8, 1, RI_ALL_ONLINE}, { 0x20404, 1, RI_ALL_ONLINE},
-+ { 0x2040c, 2, RI_ALL_ONLINE}, { 0x2041c, 2, RI_ALL_ONLINE},
-+ { 0x40154, 14, RI_ALL_ONLINE}, { 0x40198, 1, RI_ALL_ONLINE},
-+ { 0x404ac, 1, RI_ALL_ONLINE}, { 0x404bc, 1, RI_ALL_ONLINE},
-+ { 0x42290, 1, RI_ALL_ONLINE}, { 0x422a0, 1, RI_ALL_ONLINE},
-+ { 0x422b0, 1, RI_ALL_ONLINE}, { 0x42548, 1, RI_ALL_ONLINE},
-+ { 0x42550, 1, RI_ALL_ONLINE}, { 0x42558, 1, RI_ALL_ONLINE},
-+ { 0x50160, 8, RI_ALL_ONLINE}, { 0x501d0, 1, RI_ALL_ONLINE},
-+ { 0x501e0, 1, RI_ALL_ONLINE}, { 0x50204, 1, RI_ALL_ONLINE},
-+ { 0x5020c, 2, RI_ALL_ONLINE}, { 0x5021c, 1, RI_ALL_ONLINE},
-+ { 0x60090, 1, RI_ALL_ONLINE}, { 0x6011c, 1, RI_ALL_ONLINE},
-+ { 0x6012c, 1, RI_ALL_ONLINE}, { 0xc101c, 1, RI_ALL_ONLINE},
-+ { 0xc102c, 1, RI_ALL_ONLINE}, { 0xc2290, 1, RI_ALL_ONLINE},
-+ { 0xc22a0, 1, RI_ALL_ONLINE}, { 0xc22b0, 1, RI_ALL_ONLINE},
-+ { 0xc2548, 1, RI_ALL_ONLINE}, { 0xc2550, 1, RI_ALL_ONLINE},
-+ { 0xc2558, 1, RI_ALL_ONLINE}, { 0xc4294, 1, RI_ALL_ONLINE},
-+ { 0xc42a4, 1, RI_ALL_ONLINE}, { 0xc42b4, 1, RI_ALL_ONLINE},
-+ { 0xc4550, 1, RI_ALL_ONLINE}, { 0xc4558, 1, RI_ALL_ONLINE},
-+ { 0xc4560, 1, RI_ALL_ONLINE}, { 0xd016c, 8, RI_ALL_ONLINE},
-+ { 0xd01d8, 1, RI_ALL_ONLINE}, { 0xd01e8, 1, RI_ALL_ONLINE},
-+ { 0xd0204, 1, RI_ALL_ONLINE}, { 0xd020c, 3, RI_ALL_ONLINE},
-+ { 0xe0154, 8, RI_ALL_ONLINE}, { 0xe01c8, 1, RI_ALL_ONLINE},
-+ { 0xe01d8, 1, RI_ALL_ONLINE}, { 0xe0204, 1, RI_ALL_ONLINE},
-+ { 0xe020c, 2, RI_ALL_ONLINE}, { 0xe021c, 2, RI_ALL_ONLINE},
-+ { 0x101014, 1, RI_ALL_ONLINE}, { 0x101030, 1, RI_ALL_ONLINE},
-+ { 0x101040, 1, RI_ALL_ONLINE}, { 0x102058, 1, RI_ALL_ONLINE},
-+ { 0x102080, 16, RI_ALL_ONLINE}, { 0x103004, 2, RI_ALL_ONLINE},
-+ { 0x103068, 1, RI_ALL_ONLINE}, { 0x103078, 1, RI_ALL_ONLINE},
-+ { 0x103088, 1, RI_ALL_ONLINE}, { 0x10309c, 2, RI_E1H_ONLINE},
-+ { 0x104004, 1, RI_ALL_ONLINE}, { 0x104018, 1, RI_ALL_ONLINE},
-+ { 0x104020, 1, RI_ALL_ONLINE}, { 0x10403c, 1, RI_ALL_ONLINE},
-+ { 0x1040fc, 1, RI_ALL_ONLINE}, { 0x10410c, 1, RI_ALL_ONLINE},
-+ { 0x104400, 64, RI_ALL_ONLINE}, { 0x104800, 64, RI_ALL_ONLINE},
-+ { 0x105000, 3, RI_ALL_ONLINE}, { 0x105010, 3, RI_ALL_ONLINE},
-+ { 0x105020, 3, RI_ALL_ONLINE}, { 0x105030, 3, RI_ALL_ONLINE},
-+ { 0x105040, 3, RI_ALL_ONLINE}, { 0x105050, 3, RI_ALL_ONLINE},
-+ { 0x105060, 3, RI_ALL_ONLINE}, { 0x105070, 3, RI_ALL_ONLINE},
-+ { 0x105080, 3, RI_ALL_ONLINE}, { 0x105090, 3, RI_ALL_ONLINE},
-+ { 0x1050a0, 3, RI_ALL_ONLINE}, { 0x1050b0, 3, RI_ALL_ONLINE},
-+ { 0x1050c0, 3, RI_ALL_ONLINE}, { 0x1050d0, 3, RI_ALL_ONLINE},
-+ { 0x1050e0, 3, RI_ALL_ONLINE}, { 0x1050f0, 3, RI_ALL_ONLINE},
-+ { 0x105100, 3, RI_ALL_ONLINE}, { 0x105110, 3, RI_ALL_ONLINE},
-+ { 0x105120, 3, RI_ALL_ONLINE}, { 0x105130, 3, RI_ALL_ONLINE},
-+ { 0x105140, 3, RI_ALL_ONLINE}, { 0x105150, 3, RI_ALL_ONLINE},
-+ { 0x105160, 3, RI_ALL_ONLINE}, { 0x105170, 3, RI_ALL_ONLINE},
-+ { 0x105180, 3, RI_ALL_ONLINE}, { 0x105190, 3, RI_ALL_ONLINE},
-+ { 0x1051a0, 3, RI_ALL_ONLINE}, { 0x1051b0, 3, RI_ALL_ONLINE},
-+ { 0x1051c0, 3, RI_ALL_ONLINE}, { 0x1051d0, 3, RI_ALL_ONLINE},
-+ { 0x1051e0, 3, RI_ALL_ONLINE}, { 0x1051f0, 3, RI_ALL_ONLINE},
-+ { 0x105200, 3, RI_ALL_ONLINE}, { 0x105210, 3, RI_ALL_ONLINE},
-+ { 0x105220, 3, RI_ALL_ONLINE}, { 0x105230, 3, RI_ALL_ONLINE},
-+ { 0x105240, 3, RI_ALL_ONLINE}, { 0x105250, 3, RI_ALL_ONLINE},
-+ { 0x105260, 3, RI_ALL_ONLINE}, { 0x105270, 3, RI_ALL_ONLINE},
-+ { 0x105280, 3, RI_ALL_ONLINE}, { 0x105290, 3, RI_ALL_ONLINE},
-+ { 0x1052a0, 3, RI_ALL_ONLINE}, { 0x1052b0, 3, RI_ALL_ONLINE},
-+ { 0x1052c0, 3, RI_ALL_ONLINE}, { 0x1052d0, 3, RI_ALL_ONLINE},
-+ { 0x1052e0, 3, RI_ALL_ONLINE}, { 0x1052f0, 3, RI_ALL_ONLINE},
-+ { 0x105300, 3, RI_ALL_ONLINE}, { 0x105310, 3, RI_ALL_ONLINE},
-+ { 0x105320, 3, RI_ALL_ONLINE}, { 0x105330, 3, RI_ALL_ONLINE},
-+ { 0x105340, 3, RI_ALL_ONLINE}, { 0x105350, 3, RI_ALL_ONLINE},
-+ { 0x105360, 3, RI_ALL_ONLINE}, { 0x105370, 3, RI_ALL_ONLINE},
-+ { 0x105380, 3, RI_ALL_ONLINE}, { 0x105390, 3, RI_ALL_ONLINE},
-+ { 0x1053a0, 3, RI_ALL_ONLINE}, { 0x1053b0, 3, RI_ALL_ONLINE},
-+ { 0x1053c0, 3, RI_ALL_ONLINE}, { 0x1053d0, 3, RI_ALL_ONLINE},
-+ { 0x1053e0, 3, RI_ALL_ONLINE}, { 0x1053f0, 3, RI_ALL_ONLINE},
-+ { 0x108094, 1, RI_ALL_ONLINE}, { 0x1201b0, 2, RI_ALL_ONLINE},
-+ { 0x12032c, 1, RI_ALL_ONLINE}, { 0x12036c, 3, RI_ALL_ONLINE},
-+ { 0x120408, 2, RI_ALL_ONLINE}, { 0x120414, 15, RI_ALL_ONLINE},
-+ { 0x120478, 2, RI_ALL_ONLINE}, { 0x12052c, 1, RI_ALL_ONLINE},
-+ { 0x120564, 3, RI_ALL_ONLINE}, { 0x12057c, 1, RI_ALL_ONLINE},
-+ { 0x12058c, 1, RI_ALL_ONLINE}, { 0x120608, 1, RI_E1H_ONLINE},
-+ { 0x120808, 1, RI_E1_ONLINE}, { 0x12080c, 2, RI_ALL_ONLINE},
-+ { 0x120818, 1, RI_ALL_ONLINE}, { 0x120820, 1, RI_ALL_ONLINE},
-+ { 0x120828, 1, RI_ALL_ONLINE}, { 0x120830, 1, RI_ALL_ONLINE},
-+ { 0x120838, 1, RI_ALL_ONLINE}, { 0x120840, 1, RI_ALL_ONLINE},
-+ { 0x120848, 1, RI_ALL_ONLINE}, { 0x120850, 1, RI_ALL_ONLINE},
-+ { 0x120858, 1, RI_ALL_ONLINE}, { 0x120860, 1, RI_ALL_ONLINE},
-+ { 0x120868, 1, RI_ALL_ONLINE}, { 0x120870, 1, RI_ALL_ONLINE},
-+ { 0x120878, 1, RI_ALL_ONLINE}, { 0x120880, 1, RI_ALL_ONLINE},
-+ { 0x120888, 1, RI_ALL_ONLINE}, { 0x120890, 1, RI_ALL_ONLINE},
-+ { 0x120898, 1, RI_ALL_ONLINE}, { 0x1208a0, 1, RI_ALL_ONLINE},
-+ { 0x1208a8, 1, RI_ALL_ONLINE}, { 0x1208b0, 1, RI_ALL_ONLINE},
-+ { 0x1208b8, 1, RI_ALL_ONLINE}, { 0x1208c0, 1, RI_ALL_ONLINE},
-+ { 0x1208c8, 1, RI_ALL_ONLINE}, { 0x1208d0, 1, RI_ALL_ONLINE},
-+ { 0x1208d8, 1, RI_ALL_ONLINE}, { 0x1208e0, 1, RI_ALL_ONLINE},
-+ { 0x1208e8, 1, RI_ALL_ONLINE}, { 0x1208f0, 1, RI_ALL_ONLINE},
-+ { 0x1208f8, 1, RI_ALL_ONLINE}, { 0x120900, 1, RI_ALL_ONLINE},
-+ { 0x120908, 1, RI_ALL_ONLINE}, { 0x14005c, 2, RI_ALL_ONLINE},
-+ { 0x1400d0, 2, RI_ALL_ONLINE}, { 0x1400e0, 1, RI_ALL_ONLINE},
-+ { 0x1401c8, 1, RI_ALL_ONLINE}, { 0x140200, 6, RI_ALL_ONLINE},
-+ { 0x16101c, 1, RI_ALL_ONLINE}, { 0x16102c, 1, RI_ALL_ONLINE},
-+ { 0x164014, 2, RI_ALL_ONLINE}, { 0x1640f0, 1, RI_ALL_ONLINE},
-+ { 0x166290, 1, RI_ALL_ONLINE}, { 0x1662a0, 1, RI_ALL_ONLINE},
-+ { 0x1662b0, 1, RI_ALL_ONLINE}, { 0x166548, 1, RI_ALL_ONLINE},
-+ { 0x166550, 1, RI_ALL_ONLINE}, { 0x166558, 1, RI_ALL_ONLINE},
-+ { 0x168000, 1, RI_ALL_ONLINE}, { 0x168008, 1, RI_ALL_ONLINE},
-+ { 0x168010, 1, RI_ALL_ONLINE}, { 0x168018, 1, RI_ALL_ONLINE},
-+ { 0x168028, 2, RI_ALL_ONLINE}, { 0x168058, 4, RI_ALL_ONLINE},
-+ { 0x168070, 1, RI_ALL_ONLINE}, { 0x168238, 1, RI_ALL_ONLINE},
-+ { 0x1682d0, 2, RI_ALL_ONLINE}, { 0x1682e0, 1, RI_ALL_ONLINE},
-+ { 0x168300, 67, RI_ALL_ONLINE}, { 0x168410, 2, RI_ALL_ONLINE},
-+ { 0x168438, 1, RI_ALL_ONLINE}, { 0x168448, 1, RI_ALL_ONLINE},
-+ { 0x168a00, 128, RI_ALL_ONLINE}, { 0x16e200, 128, RI_E1H_ONLINE},
-+ { 0x16e404, 2, RI_E1H_ONLINE}, { 0x16e584, 70, RI_E1H_ONLINE},
-+ { 0x1700a4, 1, RI_ALL_ONLINE}, { 0x1700ac, 2, RI_ALL_ONLINE},
-+ { 0x1700c0, 1, RI_ALL_ONLINE}, { 0x170174, 1, RI_ALL_ONLINE},
-+ { 0x170184, 1, RI_ALL_ONLINE}, { 0x1800f4, 1, RI_ALL_ONLINE},
-+ { 0x180104, 1, RI_ALL_ONLINE}, { 0x180114, 1, RI_ALL_ONLINE},
-+ { 0x180124, 1, RI_ALL_ONLINE}, { 0x18026c, 1, RI_ALL_ONLINE},
-+ { 0x1802a0, 1, RI_ALL_ONLINE}, { 0x1a1000, 1, RI_ALL_ONLINE},
-+ { 0x1aa000, 1, RI_E1H_ONLINE}, { 0x1b8000, 1, RI_ALL_ONLINE},
-+ { 0x1b8040, 1, RI_ALL_ONLINE}, { 0x1b8080, 1, RI_ALL_ONLINE},
-+ { 0x1b80c0, 1, RI_ALL_ONLINE}, { 0x200104, 1, RI_ALL_ONLINE},
-+ { 0x200114, 1, RI_ALL_ONLINE}, { 0x200124, 1, RI_ALL_ONLINE},
-+ { 0x200134, 1, RI_ALL_ONLINE}, { 0x20026c, 1, RI_ALL_ONLINE},
-+ { 0x2002a0, 1, RI_ALL_ONLINE}, { 0x221000, 1, RI_ALL_ONLINE},
-+ { 0x227000, 1, RI_E1H_ONLINE}, { 0x238000, 1, RI_ALL_ONLINE},
-+ { 0x238040, 1, RI_ALL_ONLINE}, { 0x238080, 1, RI_ALL_ONLINE},
-+ { 0x2380c0, 1, RI_ALL_ONLINE}, { 0x280104, 1, RI_ALL_ONLINE},
-+ { 0x280114, 1, RI_ALL_ONLINE}, { 0x280124, 1, RI_ALL_ONLINE},
-+ { 0x280134, 1, RI_ALL_ONLINE}, { 0x28026c, 1, RI_ALL_ONLINE},
-+ { 0x2802a0, 1, RI_ALL_ONLINE}, { 0x2a1000, 1, RI_ALL_ONLINE},
-+ { 0x2a9000, 1, RI_E1H_ONLINE}, { 0x2b8000, 1, RI_ALL_ONLINE},
-+ { 0x2b8040, 1, RI_ALL_ONLINE}, { 0x2b8080, 1, RI_ALL_ONLINE},
-+ { 0x2b80c0, 1, RI_ALL_ONLINE}, { 0x300104, 1, RI_ALL_ONLINE},
-+ { 0x300114, 1, RI_ALL_ONLINE}, { 0x300124, 1, RI_ALL_ONLINE},
-+ { 0x300134, 1, RI_ALL_ONLINE}, { 0x30026c, 1, RI_ALL_ONLINE},
-+ { 0x3002a0, 1, RI_ALL_ONLINE}, { 0x321000, 1, RI_ALL_ONLINE},
-+ { 0x328960, 1, RI_E1H_ONLINE}, { 0x338000, 1, RI_ALL_ONLINE},
-+ { 0x338040, 1, RI_ALL_ONLINE}, { 0x338080, 1, RI_ALL_ONLINE},
-+ { 0x3380c0, 1, RI_ALL_ONLINE}
-+};
-+
-+static const u32 read_reg_e1_0[] = { 0x1b1000 };
-+
-+#define WREGS_COUNT_E1 1
-+static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = {
-+ { 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE }
-+};
-+
-+static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 };
-+
-+#define WREGS_COUNT_E1H 1
-+static const struct wreg_addr wreg_addrs_e1h[WREGS_COUNT_E1H] = {
-+ { 0x1b0c00, 256, 2, read_reg_e1h_0, RI_E1H_OFFLINE }
-+};
-+
-+
-+static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 };
-+
-+
-+#define TIMER_REGS_COUNT_E1 2
-+static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] =
-+ { 0x164014, 0x164018 };
-+static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] =
-+ { 0x1640d0, 0x1640d4 };
-+
-+#define TIMER_REGS_COUNT_E1H 2
-+static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] =
-+ { 0x164014, 0x164018 };
-+static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] =
-+ { 0x1640d0, 0x1640d4 };
-+
-diff -urpN a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
---- a/drivers/net/bnx2x_fw_defs.h 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x_fw_defs.h 2009-05-28 01:52:09.000000000 -0600
+diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
+index 8e68d06..84314b8 100644
+--- a/drivers/net/bnx2x.h
++++ b/drivers/net/bnx2x.h
@@ -1,6 +1,6 @@
- /* bnx2x_fw_defs.h: Broadcom Everest network driver.
+ /* bnx2x.h: Broadcom Everest network driver.
*
- * Copyright (c) 2007-2008 Broadcom Corporation
+ * Copyright (c) 2007-2009 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
-@@ -8,191 +8,395 @@
- */
-
-
--#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
-- (0x1922 + (port * 0x40) + (index * 0x4))
--#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
-- (0x1900 + (port * 0x40))
--#define CSTORM_HC_BTR_OFFSET(port)\
-- (0x1984 + (port * 0xc0))
--#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
-- (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
--#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
-- (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
--#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
-- (0x1400 + (port * 0x280) + (cpu_id * 0x28))
--#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
--#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
-- (0x1510 + (port * 0x240) + (client_id * 0x20))
--#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
-- (0x138a + (port * 0x28) + (index * 0x4))
--#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
-- (0x1370 + (port * 0x28))
--#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
-- (0x4b70 + (port * 0x8))
--#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
-- (0x1418 + (function * 0x30))
--#define TSTORM_HC_BTR_OFFSET(port)\
-- (0x13c4 + (port * 0x18))
--#define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
-- (0x22c8 + (port * 0x80))
--#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
--#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
-- (0x1420 + (port * 0x30))
--#define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
-- (0x1508 + (port * 0x240) + (client_id * 0x20))
--#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8))
--#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
-- (0x191a + (port * 0x28) + (index * 0x4))
--#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
-- (0x1900 + (port * 0x28))
--#define USTORM_HC_BTR_OFFSET(port)\
-- (0x1954 + (port * 0xb8))
--#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
-- (0x5408 + (port * 0x8))
--#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
-- (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
--#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
-- (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
--#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
-- (0x1400 + (port * 0x280) + (cpu_id * 0x28))
--#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
--#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
--#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
-- (0x141a + (port * 0x28) + (index * 0x4))
--#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
-- (0x1400 + (port * 0x28))
--#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
-- (0x5408 + (port * 0x8))
--#define XSTORM_HC_BTR_OFFSET(port)\
-- (0x1454 + (port * 0x18))
--#define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
-- (0x5328 + (port * 0x18))
--#define XSTORM_SPQ_PROD_OFFSET(port)\
-- (0x5330 + (port * 0x18))
--#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
-+#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
-+ (IS_E1H_OFFSET ? 0x7000 : 0x1000)
-+#define CSTORM_ASSERT_LIST_OFFSET(idx) \
-+ (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
-+#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-+ (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
-+ 0x40) + (index * 0x4)))
-+#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
-+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
-+#define CSTORM_FUNCTION_MODE_OFFSET \
-+ (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
-+#define CSTORM_HC_BTR_OFFSET(port) \
-+ (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
-+#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
-+ (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)))
-+#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
-+ (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)))
-+#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
-+ (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
-+ (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
-+#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
-+ (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
-+ (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
-+#define CSTORM_STATS_FLAGS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
-+ (function * 0x8)))
-+#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
-+#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
-+ (IS_E1H_OFFSET ? 0xa000 : 0x1000)
-+#define TSTORM_ASSERT_LIST_OFFSET(idx) \
-+ (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
-+#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
-+ (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
-+ : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
-+#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
-+ (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
-+#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-+ (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
-+ 0x28) + (index * 0x4)))
-+#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
-+#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
-+#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
-+ (function * 0x8)))
-+#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
-+ (function * 0x38)))
-+#define TSTORM_FUNCTION_MODE_OFFSET \
-+ (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
-+#define TSTORM_HC_BTR_OFFSET(port) \
-+ (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
-+#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
-+ (function * 0x80)))
-+#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
-+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
-+ (function * 0x38)))
-+#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
-+ (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
-+ 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
-+#define TSTORM_STATS_FLAGS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
-+ (function * 0x8)))
-+#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
-+#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
-+#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
-+#define USTORM_ASSERT_LIST_INDEX_OFFSET \
-+ (IS_E1H_OFFSET ? 0x8960 : 0x1000)
-+#define USTORM_ASSERT_LIST_OFFSET(idx) \
-+ (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
-+#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
-+ (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
-+ (0x5330 + (port * 0x260) + (clientId * 0x20)))
-+#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-+ (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
-+ 0x40) + (index * 0x4)))
-+#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
-+#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
-+ ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
-+#define USTORM_FUNCTION_MODE_OFFSET \
-+ (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
-+#define USTORM_HC_BTR_OFFSET(port) \
-+ (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
-+#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
-+ (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
-+ (0x5328 + (port * 0x260) + (clientId * 0x20)))
-+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
-+ (function * 0x8)))
-+#define USTORM_RX_PRODS_OFFSET(port, client_id) \
-+ (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
-+ : (0x5318 + (port * 0x260) + (client_id * 0x20)))
-+#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
-+ (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)))
-+#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
-+ (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
-+ (index * 0x4)))
-+#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
-+ (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
-+ (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
-+#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
-+ (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
-+ (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
-+#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
-+ (IS_E1H_OFFSET ? 0x9000 : 0x1000)
-+#define XSTORM_ASSERT_LIST_OFFSET(idx) \
-+ (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
-+#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
-+ (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
-+#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-+ (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
-+ 0x28) + (index * 0x4)))
-+#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
-+#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
-+ ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
-+#define XSTORM_E1HOV_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
-+#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
-+ (function * 0x8)))
-+#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
-+ (function * 0x90)))
-+#define XSTORM_FUNCTION_MODE_OFFSET \
-+ (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
-+#define XSTORM_HC_BTR_OFFSET(port) \
-+ (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
-+#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
-+ (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
-+ 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
-+#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
-+ (function * 0x90)))
-+#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
-+ (function * 0x10)))
-+#define XSTORM_SPQ_PROD_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
-+ (function * 0x10)))
-+#define XSTORM_STATS_FLAGS_OFFSET(function) \
-+ (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
-+ (function * 0x8)))
- #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+@@ -14,39 +14,51 @@
+ #ifndef BNX2X_H
+ #define BNX2X_H
- /**
--* This file defines HSI constatnts for the ETH flow
-+* This file defines HSI constants for the ETH flow
- */
-+#ifdef _EVEREST_MICROCODE
-+#include "microcode_constants.h"
-+#include "eth_rx_bd.h"
-+#include "eth_tx_bd.h"
-+#include "eth_rx_cqe.h"
-+#include "eth_rx_sge.h"
-+#include "eth_rx_cqe_next_page.h"
-+#endif
-+
-+/* RSS hash types */
-+#define DEFAULT_HASH_TYPE 0
-+#define IPV4_HASH_TYPE 1
-+#define TCP_IPV4_HASH_TYPE 2
-+#define IPV6_HASH_TYPE 3
-+#define TCP_IPV6_HASH_TYPE 4
-+
-+
-+/* Ethernet Ring parameters */
-+#define X_ETH_LOCAL_RING_SIZE 13
-+#define FIRST_BD_IN_PKT 0
-+#define PARSE_BD_INDEX 1
-+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
-+
-+
-+/* Rx ring params */
-+#define U_ETH_LOCAL_BD_RING_SIZE 16
-+#define U_ETH_LOCAL_SGE_RING_SIZE 12
-+#define U_ETH_SGL_SIZE 8
-+
++/* compilation time flags */
+
-+#define U_ETH_BDS_PER_PAGE_MASK \
-+ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
-+#define U_ETH_CQE_PER_PAGE_MASK \
-+ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
-+#define U_ETH_SGES_PER_PAGE_MASK \
-+ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
++/* define this to make the driver freeze on error to allow getting debug info
++ * (you will need to reboot afterwards) */
++/* #define BNX2X_STOP_ON_ERROR */
+
-+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
-+ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
++#define BCM_VLAN 1
++#endif
+
+
-+#define TU_ETH_CQES_PER_PAGE \
-+ (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
-+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
-+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
+ /* error/debug prints */
--/* hash types */
--#define DEFAULT_HASH_TYPE 0
--#define IPV4_HASH_TYPE 1
--#define TCP_IPV4_HASH_TYPE 2
--#define IPV6_HASH_TYPE 3
--#define TCP_IPV6_HASH_TYPE 4
-+#define U_ETH_UNDEFINED_Q 0xFF
+-#define DRV_MODULE_NAME "bnx2x"
+-#define PFX DRV_MODULE_NAME ": "
++#define DRV_MODULE_NAME "bnx2x"
++#define PFX DRV_MODULE_NAME ": "
- /* values of command IDs in the ramrod message */
--#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
--#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
--#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
--#define RAMROD_CMD_ID_ETH_UPDATE (100)
--#define RAMROD_CMD_ID_ETH_HALT (105)
--#define RAMROD_CMD_ID_ETH_SET_MAC (110)
--#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
--#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
--#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
-+#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
-+#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
-+#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
-+#define RAMROD_CMD_ID_ETH_UPDATE 100
-+#define RAMROD_CMD_ID_ETH_HALT 105
-+#define RAMROD_CMD_ID_ETH_SET_MAC 110
-+#define RAMROD_CMD_ID_ETH_CFC_DEL 115
-+#define RAMROD_CMD_ID_ETH_PORT_DEL 120
-+#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
+ /* for messages that are currently off */
+-#define BNX2X_MSG_OFF 0
+-#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
+-#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
+-#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
+-#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
++#define BNX2X_MSG_OFF 0
++#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
++#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
++#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
++#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
+ #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
+ #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
+-#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
++#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
- /* command values for set mac command */
--#define T_ETH_MAC_COMMAND_SET 0
--#define T_ETH_MAC_COMMAND_INVALIDATE 1
-+#define T_ETH_MAC_COMMAND_SET 0
-+#define T_ETH_MAC_COMMAND_INVALIDATE 1
+ /* regular debug print */
+ #define DP(__mask, __fmt, __args...) do { \
+ if (bp->msglevel & (__mask)) \
+- printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
++ printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
++ bp->dev ? (bp->dev->name) : "?", ##__args); \
+ } while (0)
--#define T_ETH_INDIRECTION_TABLE_SIZE 128
-+#define T_ETH_INDIRECTION_TABLE_SIZE 128
-+
-+/*The CRC32 seed, that is used for the hash(reduction) multicast address */
-+#define T_ETH_CRC32_HASH_SEED 0x00000000
+-/* for errors (never masked) */
+-#define BNX2X_ERR(__fmt, __args...) do { \
+- printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
++/* errors debug print */
++#define BNX2X_DBG_ERR(__fmt, __args...) do { \
++ if (bp->msglevel & NETIF_MSG_PROBE) \
++ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
++ bp->dev ? (bp->dev->name) : "?", ##__args); \
+ } while (0)
- /* Maximal L2 clients supported */
--#define ETH_MAX_RX_CLIENTS (18)
-+#define ETH_MAX_RX_CLIENTS_E1 19
-+#define ETH_MAX_RX_CLIENTS_E1H 25
-+
-+/* Maximal aggregation queues supported */
-+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
-+#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
-+
+-/* for logging (never masked) */
+-#define BNX2X_LOG(__fmt, __args...) do { \
+- printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
++/* for errors (never masked) */
++#define BNX2X_ERR(__fmt, __args...) do { \
++ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
++ bp->dev ? (bp->dev->name) : "?", ##__args); \
+ } while (0)
- /**
--* This file defines HSI constatnts common to all microcode flows
-+* This file defines HSI constants common to all microcode flows
- */
+ /* before we have a dev->name use dev_info() */
+@@ -60,7 +72,7 @@
+ #define bnx2x_panic() do { \
+ bp->panic = 1; \
+ BNX2X_ERR("driver assert\n"); \
+- bnx2x_disable_int(bp); \
++ bnx2x_int_disable(bp); \
+ bnx2x_panic_dump(bp); \
+ } while (0)
+ #else
+@@ -71,164 +83,413 @@
+ #endif
- /* Connection types */
--#define ETH_CONNECTION_TYPE 0
-+#define ETH_CONNECTION_TYPE 0
-+#define TOE_CONNECTION_TYPE 1
-+#define RDMA_CONNECTION_TYPE 2
-+#define ISCSI_CONNECTION_TYPE 3
-+#define FCOE_CONNECTION_TYPE 4
-+#define RESERVED_CONNECTION_TYPE_0 5
-+#define RESERVED_CONNECTION_TYPE_1 6
-+#define RESERVED_CONNECTION_TYPE_2 7
--#define PROTOCOL_STATE_BIT_OFFSET 6
+-#define U64_LO(x) (((u64)x) & 0xffffffff)
+-#define U64_HI(x) (((u64)x) >> 32)
+-#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
++#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
++#define U64_HI(x) (u32)(((u64)(x)) >> 32)
++#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
--#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
-+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+-#define REG_ADDR(bp, offset) (bp->regview + offset)
++#define REG_ADDR(bp, offset) (bp->regview + offset)
+
+-#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
+-#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
+-#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
++#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
++#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
++#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
+
+-#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
++#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
+ #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
+-#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
+-#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
++#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
++#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
+
-+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
-+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
-+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
++#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
++#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
- /* microcode fixed page page size 4K (chains and ring segments) */
--#define MC_PAGE_SIZE (4096)
-+#define MC_PAGE_SIZE 4096
+-#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
+-#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
++#define REG_RD_DMAE(bp, offset, valp, len32) \
++ do { \
++ bnx2x_read_dmae(bp, offset, len32);\
++ memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
++ } while (0)
--/* Host coalescing constants */
+-#define REG_WR_DMAE(bp, offset, val, len32) \
++#define REG_WR_DMAE(bp, offset, valp, len32) \
+ do { \
+- memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
++ memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
+ bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
+ offset, len32); \
+ } while (0)
--/* IGU constants */
--#define IGU_PORT_BASE 0x0400
--
--#define IGU_ADDR_MSIX 0x0000
--#define IGU_ADDR_INT_ACK 0x0200
--#define IGU_ADDR_PROD_UPD 0x0201
--#define IGU_ADDR_ATTN_BITS_UPD 0x0202
--#define IGU_ADDR_ATTN_BITS_SET 0x0203
--#define IGU_ADDR_ATTN_BITS_CLR 0x0204
--#define IGU_ADDR_COALESCE_NOW 0x0205
--#define IGU_ADDR_SIMD_MASK 0x0206
--#define IGU_ADDR_SIMD_NOMASK 0x0207
--#define IGU_ADDR_MSI_CTL 0x0210
--#define IGU_ADDR_MSI_ADDR_LO 0x0211
--#define IGU_ADDR_MSI_ADDR_HI 0x0212
--#define IGU_ADDR_MSI_DATA 0x0213
--
--#define IGU_INT_ENABLE 0
--#define IGU_INT_DISABLE 1
--#define IGU_INT_NOP 2
--#define IGU_INT_NOP2 3
-+/* Host coalescing constants */
-
- /* index numbers */
--#define HC_USTORM_DEF_SB_NUM_INDICES 4
--#define HC_CSTORM_DEF_SB_NUM_INDICES 8
--#define HC_XSTORM_DEF_SB_NUM_INDICES 4
--#define HC_TSTORM_DEF_SB_NUM_INDICES 4
--#define HC_USTORM_SB_NUM_INDICES 4
--#define HC_CSTORM_SB_NUM_INDICES 4
--
--/* index values - which counterto update */
-+#define HC_USTORM_DEF_SB_NUM_INDICES 8
-+#define HC_CSTORM_DEF_SB_NUM_INDICES 8
-+#define HC_XSTORM_DEF_SB_NUM_INDICES 4
-+#define HC_TSTORM_DEF_SB_NUM_INDICES 4
-+#define HC_USTORM_SB_NUM_INDICES 4
-+#define HC_CSTORM_SB_NUM_INDICES 4
-+
-+/* index values - which counter to update */
-+
-+#define HC_INDEX_U_TOE_RX_CQ_CONS 0
-+#define HC_INDEX_U_ETH_RX_CQ_CONS 1
-+#define HC_INDEX_U_ETH_RX_BD_CONS 2
-+#define HC_INDEX_U_FCOE_EQ_CONS 3
-+
-+#define HC_INDEX_C_TOE_TX_CQ_CONS 0
-+#define HC_INDEX_C_ETH_TX_CQ_CONS 1
-+#define HC_INDEX_C_ISCSI_EQ_CONS 2
-+
-+#define HC_INDEX_DEF_X_SPQ_CONS 0
-+
-+#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
-+#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
-+#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
-+#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
-+#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
-+#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
-+
-+#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
-+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
-+#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
-+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
-
--#define HC_INDEX_U_ETH_RX_CQ_CONS 1
--
--#define HC_INDEX_C_ETH_TX_CQ_CONS 1
--
--#define HC_INDEX_DEF_X_SPQ_CONS 0
--
--#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
--#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
-
- /* used by the driver to get the SB offset */
--#define USTORM_ID 0
--#define CSTORM_ID 1
--#define XSTORM_ID 2
--#define TSTORM_ID 3
--#define ATTENTION_ID 4
-+#define USTORM_ID 0
-+#define CSTORM_ID 1
-+#define XSTORM_ID 2
-+#define TSTORM_ID 3
-+#define ATTENTION_ID 4
-
- /* max number of slow path commands per port */
--#define MAX_RAMRODS_PER_PORT (8)
-+#define MAX_RAMRODS_PER_PORT 8
-
- /* values for RX ETH CQE type field */
--#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
--#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
-+#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
-+#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
-+
-
--/* MAC address list size */
--#define T_MAC_ADDRESS_LIST_SIZE (96)
-+/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
-+#define EMULATION_FREQUENCY_FACTOR 1600
-+#define FPGA_FREQUENCY_FACTOR 100
-+
-+#define TIMERS_TICK_SIZE_CHIP (1e-3)
-+#define TIMERS_TICK_SIZE_EMUL \
-+ ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
-+#define TIMERS_TICK_SIZE_FPGA \
-+ ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
-+
-+#define TSEMI_CLK1_RESUL_CHIP (1e-3)
-+#define TSEMI_CLK1_RESUL_EMUL \
-+ ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
-+#define TSEMI_CLK1_RESUL_FPGA \
-+ ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
-+
-+#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
-+#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
-+#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
-+
-+#define XSEMI_CLK1_RESUL_CHIP (1e-3)
-+#define XSEMI_CLK1_RESUL_EMUL \
-+ ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
-+#define XSEMI_CLK1_RESUL_FPGA \
-+ ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
-+
-+#define XSEMI_CLK2_RESUL_CHIP (1e-6)
-+#define XSEMI_CLK2_RESUL_EMUL \
-+ ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
-+#define XSEMI_CLK2_RESUL_FPGA \
-+ ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
-+
-+#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
-+#define SDM_TIMER_TICK_RESUL_EMUL \
-+ ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
-+#define SDM_TIMER_TICK_RESUL_FPGA \
-+ ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
-
-+
-+/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
- #define XSTORM_IP_ID_ROLL_HALF 0x8000
- #define XSTORM_IP_ID_ROLL_ALL 0
-
--#define FW_LOG_LIST_SIZE (50)
-+#define FW_LOG_LIST_SIZE 50
-+
-+#define NUM_OF_PROTOCOLS 4
-+#define NUM_OF_SAFC_BITS 16
-+#define MAX_COS_NUMBER 4
-+#define MAX_T_STAT_COUNTER_ID 18
-+#define MAX_X_STAT_COUNTER_ID 18
-+#define MAX_U_STAT_COUNTER_ID 18
-+
-+
-+#define UNKNOWN_ADDRESS 0
-+#define UNICAST_ADDRESS 1
-+#define MULTICAST_ADDRESS 2
-+#define BROADCAST_ADDRESS 3
-+
-+#define SINGLE_FUNCTION 0
-+#define MULTI_FUNCTION 1
-
--#define NUM_OF_PROTOCOLS 4
--#define MAX_COS_NUMBER 16
--#define MAX_T_STAT_COUNTER_ID 18
--
--#define T_FAIR 1
--#define FAIR_MEM 2
--#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
--
--#define UNKNOWN_ADDRESS 0
--#define UNICAST_ADDRESS 1
--#define MULTICAST_ADDRESS 2
--#define BROADCAST_ADDRESS 3
-+#define IP_V4 0
-+#define IP_V6 1
-
-diff -urpN a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
---- a/drivers/net/bnx2x.h 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x.h 2009-05-28 01:52:09.000000000 -0600
-@@ -1,6 +1,6 @@
- /* bnx2x.h: Broadcom Everest network driver.
- *
-- * Copyright (c) 2007-2008 Broadcom Corporation
-+ * Copyright (c) 2007-2009 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -14,39 +14,57 @@
- #ifndef BNX2X_H
- #define BNX2X_H
-
-+/* compilation time flags */
-+
-+/* define this to make the driver freeze on error to allow getting debug info
-+ * (you will need to reboot afterwards) */
-+/* #define BNX2X_STOP_ON_ERROR */
-+
-+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
-+#define BCM_VLAN 1
-+#endif
-+
-+
-+
-+#include "bnx2x_reg.h"
-+#include "bnx2x_fw_defs.h"
-+#include "bnx2x_hsi.h"
-+#include "bnx2x_link.h"
-+
- /* error/debug prints */
-
--#define DRV_MODULE_NAME "bnx2x"
--#define PFX DRV_MODULE_NAME ": "
-+#define DRV_MODULE_NAME "bnx2x"
-+#define PFX DRV_MODULE_NAME ": "
-
- /* for messages that are currently off */
--#define BNX2X_MSG_OFF 0
--#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
--#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
--#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
--#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
-+#define BNX2X_MSG_OFF 0
-+#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
-+#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
-+#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
-+#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
- #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
- #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
-
--#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
-+#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
-
- /* regular debug print */
- #define DP(__mask, __fmt, __args...) do { \
- if (bp->msglevel & (__mask)) \
-- printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
-- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
-+ printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-+ bp->dev ? (bp->dev->name) : "?", ##__args); \
- } while (0)
-
--/* for errors (never masked) */
--#define BNX2X_ERR(__fmt, __args...) do { \
-- printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
-- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
-+/* errors debug print */
-+#define BNX2X_DBG_ERR(__fmt, __args...) do { \
-+ if (bp->msglevel & NETIF_MSG_PROBE) \
-+ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-+ bp->dev ? (bp->dev->name) : "?", ##__args); \
- } while (0)
-
--/* for logging (never masked) */
--#define BNX2X_LOG(__fmt, __args...) do { \
-- printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
-- __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
-+/* for errors (never masked) */
-+#define BNX2X_ERR(__fmt, __args...) do { \
-+ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-+ bp->dev ? (bp->dev->name) : "?", ##__args); \
- } while (0)
-
- /* before we have a dev->name use dev_info() */
-@@ -60,7 +78,7 @@
- #define bnx2x_panic() do { \
- bp->panic = 1; \
- BNX2X_ERR("driver assert\n"); \
-- bnx2x_disable_int(bp); \
-+ bnx2x_int_disable(bp); \
- bnx2x_panic_dump(bp); \
- } while (0)
- #else
-@@ -71,164 +89,404 @@
- #endif
-
-
--#define U64_LO(x) (((u64)x) & 0xffffffff)
--#define U64_HI(x) (((u64)x) >> 32)
--#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
-+#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
-+#define U64_HI(x) (u32)(((u64)(x)) >> 32)
-+#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
-
-
--#define REG_ADDR(bp, offset) (bp->regview + offset)
-+#define REG_ADDR(bp, offset) (bp->regview + offset)
-
--#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
--#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
--#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
-+#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
-+#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
-
--#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
-+#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
- #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
--#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
--#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
-+#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
-+
-+#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
-+#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
-
--#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
--#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
-+#define REG_RD_DMAE(bp, offset, valp, len32) \
-+ do { \
-+ bnx2x_read_dmae(bp, offset, len32);\
-+ memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
-+ } while (0)
-
--#define REG_WR_DMAE(bp, offset, val, len32) \
-+#define REG_WR_DMAE(bp, offset, valp, len32) \
- do { \
-- memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
-+ memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
- bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
- offset, len32); \
- } while (0)
-
--#define SHMEM_RD(bp, type) \
-- REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
--#define SHMEM_WR(bp, type, val) \
-- REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
-+#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
-+ offsetof(struct shmem_region, field))
-+#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
-+#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
+-#define SHMEM_RD(bp, type) \
+- REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
+-#define SHMEM_WR(bp, type, val) \
+- REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
++#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
++ offsetof(struct shmem_region, field))
++#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
++#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
-#define NIG_WR(reg, val) REG_WR(bp, reg, val)
-#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
@@ -11411,7 +10310,9 @@
+#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
+#define SGE_PAGE_SIZE PAGE_SIZE
+#define SGE_PAGE_SHIFT PAGE_SHIFT
-+#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr)
++#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
++
++#define BCM_RX_ETH_PAYLOAD_ALIGN 64
+
+/* SGE ring related macros */
+#define NUM_RX_SGE_PAGES 2
@@ -11485,15 +10386,20 @@
+ u8 index; /* number in fp array */
+ u8 cl_id; /* eth client id */
+ u8 sb_id; /* status block number in HW */
++#define FP_IDX(fp) (fp->index)
++#define FP_CL_ID(fp) (fp->cl_id)
++#define BP_CL_ID(bp) (bp->fp[0].cl_id)
++#define FP_SB_ID(fp) (fp->sb_id)
++#define CNIC_SB_ID 0
+
+ u16 tx_pkt_prod;
+ u16 tx_pkt_cons;
+ u16 tx_bd_prod;
+ u16 tx_bd_cons;
-+ __le16 *tx_cons_sb;
++ u16 *tx_cons_sb;
+
-+ __le16 fp_c_idx;
-+ __le16 fp_u_idx;
++ u16 fp_c_idx;
++ u16 fp_u_idx;
+
+ u16 rx_bd_prod;
+ u16 rx_bd_cons;
@@ -11502,8 +10408,8 @@
+ u16 rx_sge_prod;
+ /* The last maximal completed SGE */
+ u16 last_max_sge;
-+ __le16 *rx_cons_sb;
-+ __le16 *rx_bd_cons_sb;
++ u16 *rx_cons_sb;
++ u16 *rx_bd_cons_sb;
+
+ unsigned long tx_pkt,
+ rx_pkt,
@@ -11656,13 +10562,10 @@
+#define BNX2X_RX_CSUM_OK(cqe) \
+ (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
+
-+#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
-+ (((le16_to_cpu(flags) & \
-+ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
-+ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
-+ == PRS_FLAG_OVERETH_IPV4)
+#define BNX2X_RX_SUM_FIX(cqe) \
-+ BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
++ ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
++ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
++ (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
+
+
+#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
@@ -11736,8 +10639,11 @@
+ u32 shmem_base;
+
+ u32 hw_config;
++ u32 board;
+
+ u32 bc_ver;
++
++ char *name;
};
+
@@ -11748,7 +10654,7 @@
struct nig_stats {
u32 brb_discard;
u32 brb_packet;
-@@ -244,13 +502,54 @@ struct nig_stats {
+@@ -244,13 +505,53 @@ struct nig_stats {
u32 pbf_octets;
u32 pbf_packet;
u32 safc_inp;
@@ -11777,7 +10683,6 @@
+
+ /* used to synchronize phy accesses */
+ struct mutex phy_mutex;
-+ int need_hw_lock;
+
+ u32 port_stx;
+
@@ -11807,7 +10712,7 @@
u32 total_bytes_received_hi;
u32 total_bytes_received_lo;
u32 total_bytes_transmitted_hi;
-@@ -267,97 +566,122 @@ struct bnx2x_eth_stats {
+@@ -267,97 +568,122 @@ struct bnx2x_eth_stats {
u32 total_multicast_packets_transmitted_lo;
u32 total_broadcast_packets_transmitted_hi;
u32 total_broadcast_packets_transmitted_lo;
@@ -11868,9 +10773,10 @@
- u32 t_rcv_multicast_bytes_hi;
- u32 t_rcv_multicast_bytes_lo;
- u32 t_total_rcv_pkt;
-
+-
- u32 checksum_discard;
- u32 packets_too_big_discard;
++
+ u32 error_bytes_received_hi;
+ u32 error_bytes_received_lo;
+
@@ -12007,7 +10913,7 @@
#endif
union cdu_context {
-@@ -365,345 +689,195 @@ union cdu_context {
+@@ -365,345 +691,190 @@ union cdu_context {
char pad[1024];
};
@@ -12028,17 +10934,16 @@
/* used by dmae command executer */
- struct dmae_command dmae[MAX_DMAE_C];
+ struct dmae_command dmae[MAX_DMAE_C];
-+
+
+- union mac_stats mac_stats;
+- struct nig_stats nig;
+- struct bnx2x_eth_stats eth_stats;
+ u32 stats_comp;
+ union mac_stats mac_stats;
+ struct nig_stats nig_stats;
+ struct host_port_stats port_stats;
+ struct host_func_stats func_stats;
-- union mac_stats mac_stats;
-- struct nig_stats nig;
-- struct bnx2x_eth_stats eth_stats;
--
- u32 wb_comp;
-#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
- u32 wb_data[4];
@@ -12168,16 +11073,12 @@
-#define ETH_MAX_PACKET_SIZE 1500
-#define ETH_MAX_JUMBO_PACKET_SIZE 9600
+ u32 rx_csum;
++ u32 rx_offset;
+ u32 rx_buf_size;
+#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
+#define ETH_MIN_PACKET_SIZE 60
+#define ETH_MAX_PACKET_SIZE 1500
+#define ETH_MAX_JUMBO_PACKET_SIZE 9600
-+
-+ /* Max supported alignment is 256 (8 shift) */
-+#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
-+ L1_CACHE_SHIFT : 8)
-+#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
struct host_def_status_block *def_status_blk;
-#define DEF_SB_ID 16
@@ -12191,13 +11092,14 @@
- u32 aeu_mask;
- u32 nig_mask;
+#define DEF_SB_ID 16
-+ __le16 def_c_idx;
-+ __le16 def_u_idx;
-+ __le16 def_x_idx;
-+ __le16 def_t_idx;
-+ __le16 def_att_idx;
++ u16 def_c_idx;
++ u16 def_u_idx;
++ u16 def_x_idx;
++ u16 def_t_idx;
++ u16 def_att_idx;
+ u32 attn_state;
+ struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
++ u32 nig_mask;
/* slow path ring */
- struct eth_spe *spq;
@@ -12218,7 +11120,7 @@
+ u16 spq_prod_idx;
+ struct eth_spe *spq_prod_bd;
+ struct eth_spe *spq_last_bd;
-+ __le16 *dsb_sp_prod;
++ u16 *dsb_sp_prod;
+ u16 spq_left; /* serialize spq */
+ /* used to synchronize spq accesses */
+ spinlock_t spq_lock;
@@ -12262,9 +11164,7 @@
- u32 chip_id;
-/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
-#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
-+ int panic;
-+ int msglevel;
-
+-
-#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
-
-#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
@@ -12370,6 +11270,9 @@
-#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
-#define NVRAM_TIMEOUT_COUNT 30000
-#define NVRAM_PAGE_SIZE 256
++ int panic;
++ int msglevel;
++
+ u32 flags;
+#define PCIX_FLAG 1
+#define PCI_32BIT_FLAG 2
@@ -12398,6 +11301,7 @@
+ struct work_struct reset_task;
+
+ struct timer_list timer;
++ int timer_interval;
+ int current_interval;
+
+ u16 fw_seq;
@@ -12410,9 +11314,6 @@
+ struct bnx2x_common common;
+ struct bnx2x_port port;
+
-+ struct cmng_struct_per_port cmng;
-+ u32 vn_weight_sum;
-+
+ u32 mf_config;
+ u16 e1hov;
+ u8 e1hmf;
@@ -12427,32 +11328,29 @@
- u16 tx_quick_cons_trip;
- u16 tx_ticks_int;
- u16 tx_ticks;
--
-- u16 rx_quick_cons_trip_int;
-- u16 rx_quick_cons_trip;
-- u16 rx_ticks_int;
-- u16 rx_ticks;
--
-- u32 stats_ticks;
--
-- int state;
--#define BNX2X_STATE_CLOSED 0x0
--#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
--#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
+ u16 tx_quick_cons_trip_int;
+ u16 tx_quick_cons_trip;
+ u16 tx_ticks_int;
+ u16 tx_ticks;
-+
+
+- u16 rx_quick_cons_trip_int;
+- u16 rx_quick_cons_trip;
+- u16 rx_ticks_int;
+- u16 rx_ticks;
+ u16 rx_quick_cons_trip_int;
+ u16 rx_quick_cons_trip;
+ u16 rx_ticks_int;
+ u16 rx_ticks;
-+
+
+- u32 stats_ticks;
+ u32 lin_cnt;
-+
+
+- int state;
+-#define BNX2X_STATE_CLOSED 0x0
+-#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
+-#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
+ int state;
-+#define BNX2X_STATE_CLOSED 0
++#define BNX2X_STATE_CLOSED 0x0
+#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
+#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
#define BNX2X_STATE_OPEN 0x3000
@@ -12461,9 +11359,14 @@
#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
-#define BNX2X_STATE_ERROR 0xF000
--
++#define BNX2X_STATE_DISABLED 0xd000
++#define BNX2X_STATE_DIAG 0xe000
++#define BNX2X_STATE_ERROR 0xf000
+
- int num_queues;
--
++ int num_queues;
++#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
+
- u32 rx_mode;
-#define BNX2X_RX_MODE_NONE 0
-#define BNX2X_RX_MODE_NORMAL 1
@@ -12471,13 +11374,6 @@
-#define BNX2X_RX_MODE_PROMISC 3
-#define BNX2X_MAX_MULTICAST 64
-#define BNX2X_MAX_EMUL_MULTI 16
-+#define BNX2X_STATE_DISABLED 0xd000
-+#define BNX2X_STATE_DIAG 0xe000
-+#define BNX2X_STATE_ERROR 0xf000
-+
-+ int num_queues;
-+#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
-+
+ u32 rx_mode;
+#define BNX2X_RX_MODE_NONE 0
+#define BNX2X_RX_MODE_NORMAL 1
@@ -12496,7 +11392,7 @@
#ifdef BCM_ISCSI
void *t1;
-@@ -716,30 +890,71 @@ struct bnx2x {
+@@ -716,264 +887,171 @@ struct bnx2x {
dma_addr_t qm_mapping;
#endif
@@ -12540,80 +11436,52 @@
};
+-/* DMAE command defines */
+-#define DMAE_CMD_SRC_PCI 0
+-#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
+#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
-+
+
+-#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
+-#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
+#define for_each_nondefault_queue(bp, var) \
+ for (var = 1; var < bp->num_queues; var++)
+#define is_multi(bp) (bp->num_queues > 1)
-+
-+
+
+-#define DMAE_CMD_C_DST_PCI 0
+-#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
+
+-#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
+void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
+void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
+ u32 len32);
-+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
-+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
-+
+
+-#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
+-#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
+-#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
+-#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
+static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
+ int wait)
+{
+ u32 val;
-+
+
+-#define DMAE_CMD_PORT_0 0
+-#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
+ do {
+ val = REG_RD(bp, reg);
+ if (val == expected)
+ break;
+ ms -= wait;
+ msleep(wait);
-+
-+ } while (ms > 0);
-+
-+ return val;
-+}
-+
-+
-+/* load/unload mode */
-+#define LOAD_NORMAL 0
-+#define LOAD_OPEN 1
-+#define LOAD_DIAG 2
-+#define UNLOAD_NORMAL 0
-+#define UNLOAD_CLOSE 1
-+
-+
- /* DMAE command defines */
- #define DMAE_CMD_SRC_PCI 0
- #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
-@@ -747,233 +962,101 @@ struct bnx2x {
- #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
- #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
-
--#define DMAE_CMD_C_DST_PCI 0
--#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
--
--#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
--
--#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
--#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
--#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
--#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
--
--#define DMAE_CMD_PORT_0 0
--#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
-+#define DMAE_CMD_C_DST_PCI 0
-+#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
-#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
-#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
-+#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
++ } while (ms > 0);
-#define DMAE_LEN32_MAX 0x400
-+#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
-+#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
-+#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
-+#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
++ return val;
++}
-+#define DMAE_CMD_PORT_0 0
-+#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
-/* MC hsi */
-#define RX_COPY_THRESH 92
@@ -12630,9 +11498,12 @@
- (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define TX_BD(x) ((x) & MAX_TX_BD)
-#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
-+#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
-+#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
-+#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
++/* load/unload mode */
++#define LOAD_NORMAL 0
++#define LOAD_OPEN 1
++#define LOAD_DIAG 2
++#define UNLOAD_NORMAL 0
++#define UNLOAD_CLOSE 1
-/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
-#define NUM_RX_RINGS 8
@@ -12645,8 +11516,6 @@
-#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
- (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
-#define RX_BD(x) ((x) & MAX_RX_BD)
-+#define DMAE_LEN32_RD_MAX 0x80
-+#define DMAE_LEN32_WR_MAX 0x400
-#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2)
-#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
@@ -12657,55 +11526,65 @@
-#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
- (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
-#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
-+#define DMAE_COMP_VAL 0xe0d0d0ae
++/* DMAE command defines */
++#define DMAE_CMD_SRC_PCI 0
++#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
-+#define MAX_DMAE_C_PER_PORT 8
-+#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
-+ BP_E1HVN(bp))
-+#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
-+ E1HVN_MAX)
++#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
++#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
-/* used on a CID received from the HW */
-#define SW_CID(x) (le32_to_cpu(x) & \
- (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
-#define CQE_CMD(x) (le32_to_cpu(x) >> \
- COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
++#define DMAE_CMD_C_DST_PCI 0
++#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
-#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
- le32_to_cpu((bd)->addr_lo))
-#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
-+/* PCIE link and speed */
-+#define PCICFG_LINK_WIDTH 0x1f00000
-+#define PCICFG_LINK_WIDTH_SHIFT 20
-+#define PCICFG_LINK_SPEED 0xf0000
-+#define PCICFG_LINK_SPEED_SHIFT 16
++#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
++#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
++#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
++#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
++#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
-#define STROM_ASSERT_ARRAY_SIZE 50
-+#define BNX2X_NUM_STATS 42
-+#define BNX2X_NUM_TESTS 7
++#define DMAE_CMD_PORT_0 0
++#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
-+#define BNX2X_PHY_LOOPBACK 0
-+#define BNX2X_MAC_LOOPBACK 1
-+#define BNX2X_PHY_LOOPBACK_FAILED 1
-+#define BNX2X_MAC_LOOPBACK_FAILED 2
-+#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
-+ BNX2X_PHY_LOOPBACK_FAILED)
++#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
++#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
++#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
-#define MDIO_INDIRECT_REG_ADDR 0x1f
-#define MDIO_SET_REG_BANK(bp, reg_bank) \
- bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
++#define DMAE_LEN32_RD_MAX 0x80
++#define DMAE_LEN32_WR_MAX 0x400
-#define MDIO_ACCESS_TIMEOUT 1000
-+#define STROM_ASSERT_ARRAY_SIZE 50
++#define DMAE_COMP_VAL 0xe0d0d0ae
++#define MAX_DMAE_C_PER_PORT 8
++#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
++ BP_E1HVN(bp))
++#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
++ E1HVN_MAX)
- /* must be used on a CID before placing it on a HW ring */
+-/* must be used on a CID before placing it on a HW ring */
-#define HW_CID(bp, x) (x | (bp->port << 23))
--
+
-#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
-#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
--
++/* PCIE link and speed */
++#define PCICFG_LINK_WIDTH 0x1f00000
++#define PCICFG_LINK_WIDTH_SHIFT 20
++#define PCICFG_LINK_SPEED 0xf0000
++#define PCICFG_LINK_SPEED_SHIFT 16
+
-#define ATTN_NIG_FOR_FUNC (1L << 8)
-#define ATTN_SW_TIMER_4_FUNC (1L << 9)
-#define GPIO_2_FUNC (1L << 10)
@@ -12717,36 +11596,52 @@
-#define ATTN_GENERAL_ATTN_4 (1L << 13)
-#define ATTN_GENERAL_ATTN_5 (1L << 14)
-#define ATTN_GENERAL_ATTN_6 (1L << 15)
-+#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
-#define ATTN_HARD_WIRED_MASK 0xff00
-#define ATTENTION_ID 4
-+#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
-+#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
++#define BNX2X_NUM_STATS 42
++#define BNX2X_NUM_TESTS 8
++#define BNX2X_MAC_LOOPBACK 0
++#define BNX2X_PHY_LOOPBACK 1
++#define BNX2X_MAC_LOOPBACK_FAILED 1
++#define BNX2X_PHY_LOOPBACK_FAILED 2
++#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
++ BNX2X_PHY_LOOPBACK_FAILED)
-#define BNX2X_BTR 3
-#define MAX_SPQ_PENDING 8
-+#define BNX2X_BTR 3
-+#define MAX_SPQ_PENDING 8
++#define STROM_ASSERT_ARRAY_SIZE 50
-#define BNX2X_NUM_STATS 34
-#define BNX2X_NUM_TESTS 1
--
--
+
++/* must be used on a CID before placing it on a HW ring */
++#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
+
-#define DPM_TRIGER_TYPE 0x40
-#define DOORBELL(bp, cid, val) \
- do { \
- writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
- DPM_TRIGER_TYPE); \
- } while (0)
--
++#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
++#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
+
-/* PCIE link and speed */
-#define PCICFG_LINK_WIDTH 0x1f00000
-#define PCICFG_LINK_WIDTH_SHIFT 20
-#define PCICFG_LINK_SPEED 0xf0000
-#define PCICFG_LINK_SPEED_SHIFT 16
+
+-#define BMAC_CONTROL_RX_ENABLE 2
++#define BNX2X_BTR 3
++#define MAX_SPQ_PENDING 8
+
+-#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
+
+-/* stuff added to make the code fit 80Col */
+/* CMNG constants
+ derived from lab experiments, and not from system spec calculations !!! */
+#define DEF_MIN_RATE 100
@@ -12759,8 +11654,20 @@
+ coefficient for calculating the fairness timer */
+#define QM_ARB_BYTES 40000
+#define FAIR_MEM 2
-+
-+
+
+-#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
+-#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
+-#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
+- (TPA_TYPE_START | TPA_TYPE_END))
+-#define BNX2X_RX_SUM_OK(cqe) \
+- (!(cqe->fast_path_cqe.status_flags & \
+- (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
+- ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
+
+-#define BNX2X_RX_SUM_FIX(cqe) \
+- ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
+- PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
+- (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
+#define ATTN_NIG_FOR_FUNC (1L << 8)
+#define ATTN_SW_TIMER_4_FUNC (1L << 9)
+#define GPIO_2_FUNC (1L << 10)
@@ -12773,29 +11680,9 @@
+#define ATTN_GENERAL_ATTN_5 (1L << 14)
+#define ATTN_GENERAL_ATTN_6 (1L << 15)
--#define BMAC_CONTROL_RX_ENABLE 2
+#define ATTN_HARD_WIRED_MASK 0xff00
+#define ATTENTION_ID 4
--#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
-
- /* stuff added to make the code fit 80Col */
-
--#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
--#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
--#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
-- (TPA_TYPE_START | TPA_TYPE_END))
--#define BNX2X_RX_SUM_OK(cqe) \
-- (!(cqe->fast_path_cqe.status_flags & \
-- (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
-- ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
--
--#define BNX2X_RX_SUM_FIX(cqe) \
-- ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
-- PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
-- (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
--
--
-#define MDIO_AN_CL73_OR_37_COMPLETE \
- (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
- MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
@@ -12879,18 +11766,18 @@
- MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
- MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
- MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
--
+
++/* stuff added to make the code fit 80Col */
++
+#define BNX2X_PMF_LINK_ASSERT \
+ GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
#define BNX2X_MC_ASSERT_BITS \
(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
-@@ -984,15 +1067,20 @@ struct bnx2x {
- #define BNX2X_MCP_ASSERT \
- GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
+@@ -987,12 +1065,20 @@ struct bnx2x {
+ #define BNX2X_DOORQ_ASSERT \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
--#define BNX2X_DOORQ_ASSERT \
-- AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
+#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
+#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
+ GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
@@ -12898,7 +11785,7 @@
+ GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
+ GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
+ GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
-
++
#define HW_INTERRUT_ASSERT_SET_0 \
(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
@@ -12909,7 +11796,7 @@
AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
-@@ -1009,7 +1097,7 @@ struct bnx2x {
+@@ -1009,7 +1095,7 @@ struct bnx2x {
AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
@@ -12918,7 +11805,7 @@
AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
-@@ -1026,7 +1114,7 @@ struct bnx2x {
+@@ -1026,7 +1112,7 @@ struct bnx2x {
AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
@@ -12927,7 +11814,7 @@
AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
-@@ -1035,42 +1123,44 @@ struct bnx2x {
+@@ -1035,42 +1121,44 @@ struct bnx2x {
AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
@@ -12993,142 +11880,577 @@
/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
#endif /* bnx2x.h */
-diff -urpN a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
---- a/drivers/net/bnx2x_hsi.h 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x_hsi.h 2009-05-28 01:53:26.000000000 -0600
-@@ -1,6 +1,6 @@
- /* bnx2x_hsi.h: Broadcom Everest network driver.
- *
-- * Copyright (c) 2007-2008 Broadcom Corporation
-+ * Copyright (c) 2007-2009 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -119,29 +119,15 @@ struct shared_hw_cfg { /* NVRAM Off
- #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
+diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
+index 3b96890..2fe14a2 100644
+--- a/drivers/net/bnx2x_fw_defs.h
++++ b/drivers/net/bnx2x_fw_defs.h
+@@ -8,191 +8,398 @@
+ */
- u32 board; /* 0x124 */
--#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
--#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
--#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
--#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
--
--#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
--#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
--#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
--#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
--#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
--#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
--#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
-+#define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
- #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
-+#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
-+#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
+-#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
+- (0x1922 + (port * 0x40) + (index * 0x4))
+-#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
+- (0x1900 + (port * 0x40))
+-#define CSTORM_HC_BTR_OFFSET(port)\
+- (0x1984 + (port * 0xc0))
+-#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
+- (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+-#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
+- (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+-#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
+- (0x1400 + (port * 0x280) + (cpu_id * 0x28))
+-#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
+-#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
+- (0x1510 + (port * 0x240) + (client_id * 0x20))
+-#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
+- (0x138a + (port * 0x28) + (index * 0x4))
+-#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
+- (0x1370 + (port * 0x28))
+-#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
+- (0x4b70 + (port * 0x8))
+-#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
+- (0x1418 + (function * 0x30))
+-#define TSTORM_HC_BTR_OFFSET(port)\
+- (0x13c4 + (port * 0x18))
+-#define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
+- (0x22c8 + (port * 0x80))
+-#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+-#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
+- (0x1420 + (port * 0x30))
+-#define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
+- (0x1508 + (port * 0x240) + (client_id * 0x20))
+-#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8))
+-#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
+- (0x191a + (port * 0x28) + (index * 0x4))
+-#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
+- (0x1900 + (port * 0x28))
+-#define USTORM_HC_BTR_OFFSET(port)\
+- (0x1954 + (port * 0xb8))
+-#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
+- (0x5408 + (port * 0x8))
+-#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
+- (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+-#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
+- (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+-#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
+- (0x1400 + (port * 0x280) + (cpu_id * 0x28))
+-#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+-#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+-#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
+- (0x141a + (port * 0x28) + (index * 0x4))
+-#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
+- (0x1400 + (port * 0x28))
+-#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
+- (0x5408 + (port * 0x8))
+-#define XSTORM_HC_BTR_OFFSET(port)\
+- (0x1454 + (port * 0x18))
+-#define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
+- (0x5328 + (port * 0x18))
+-#define XSTORM_SPQ_PROD_OFFSET(port)\
+- (0x5330 + (port * 0x18))
+-#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
++#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
++ (IS_E1H_OFFSET ? 0x7000 : 0x1000)
++#define CSTORM_ASSERT_LIST_OFFSET(idx) \
++ (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
++#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
++ (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
++ 0x40) + (index * 0x4)))
++#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
++#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
++#define CSTORM_FUNCTION_MODE_OFFSET \
++ (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
++#define CSTORM_HC_BTR_OFFSET(port) \
++ (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
++#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
++ (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)))
++#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
++ (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)))
++#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
++ (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
++ (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
++#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
++ (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
++ (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
++#define CSTORM_STATS_FLAGS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
++ (function * 0x8)))
++#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
++#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
++ (IS_E1H_OFFSET ? 0xa000 : 0x1000)
++#define TSTORM_ASSERT_LIST_OFFSET(idx) \
++ (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
++#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
++ (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
++ : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
++#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
++ (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
++#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
++ (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
++ 0x28) + (index * 0x4)))
++#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
++#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
++#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
++ (function * 0x8)))
++#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
++ (function * 0x38)))
++#define TSTORM_FUNCTION_MODE_OFFSET \
++ (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
++#define TSTORM_HC_BTR_OFFSET(port) \
++ (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
++#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
++ (function * 0x80)))
++#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
++#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
++ (function * 0x38)))
++#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
++ (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
++ 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
++#define TSTORM_STATS_FLAGS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
++ (function * 0x8)))
++#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
++#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
++#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
++#define USTORM_ASSERT_LIST_INDEX_OFFSET \
++ (IS_E1H_OFFSET ? 0x8960 : 0x1000)
++#define USTORM_ASSERT_LIST_OFFSET(idx) \
++ (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
++#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
++ (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
++ (0x5330 + (port * 0x260) + (clientId * 0x20)))
++#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
++ (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
++ 0x40) + (index * 0x4)))
++#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
++#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
++ ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
++#define USTORM_FUNCTION_MODE_OFFSET \
++ (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
++#define USTORM_HC_BTR_OFFSET(port) \
++ (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
++#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
++ (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
++ (0x5328 + (port * 0x260) + (clientId * 0x20)))
++#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
++ (function * 0x8)))
++#define USTORM_RX_PRODS_OFFSET(port, client_id) \
++ (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
++ : (0x5318 + (port * 0x260) + (client_id * 0x20)))
++#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
++ (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)))
++#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
++ (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
++ (index * 0x4)))
++#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
++ (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
++ (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
++#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
++ (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
++ (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
++#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
++ (IS_E1H_OFFSET ? 0x9000 : 0x1000)
++#define XSTORM_ASSERT_LIST_OFFSET(idx) \
++ (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
++#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
++ (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
++#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
++ (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
++ 0x28) + (index * 0x4)))
++#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
++#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
++ ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
++#define XSTORM_E1HOV_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
++#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
++ (function * 0x8)))
++#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
++ (function * 0x90)))
++#define XSTORM_FUNCTION_MODE_OFFSET \
++ (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
++#define XSTORM_HC_BTR_OFFSET(port) \
++ (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
++#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
++ (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
++ 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
++#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
++ (function * 0x90)))
++#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
++ (function * 0x10)))
++#define XSTORM_SPQ_PROD_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
++ (function * 0x10)))
++#define XSTORM_STATS_FLAGS_OFFSET(function) \
++ (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
++ (function * 0x8)))
+ #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+ /**
+ * This file defines HSI constatnts for the ETH flow
+ */
+-
+-/* hash types */
+-#define DEFAULT_HASH_TYPE 0
+-#define IPV4_HASH_TYPE 1
+-#define TCP_IPV4_HASH_TYPE 2
+-#define IPV6_HASH_TYPE 3
+-#define TCP_IPV6_HASH_TYPE 4
++#ifdef _EVEREST_MICROCODE
++#include "microcode_constants.h"
++#include "eth_rx_bd.h"
++#include "eth_tx_bd.h"
++#include "eth_rx_cqe.h"
++#include "eth_rx_sge.h"
++#include "eth_rx_cqe_next_page.h"
++#endif
++
++/* RSS hash types */
++#define DEFAULT_HASH_TYPE 0
++#define IPV4_HASH_TYPE 1
++#define TCP_IPV4_HASH_TYPE 2
++#define IPV6_HASH_TYPE 3
++#define TCP_IPV6_HASH_TYPE 4
++
++/* Ethernet Ring parmaters */
++#define X_ETH_LOCAL_RING_SIZE 13
++#define FIRST_BD_IN_PKT 0
++#define PARSE_BD_INDEX 1
++#define NUM_OF_ETH_BDS_IN_PAGE \
++ ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
+
-+#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
-+#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
+
- u32 reserved; /* 0x128 */
++/* Rx ring params */
++#define U_ETH_LOCAL_BD_RING_SIZE (16)
++#define U_ETH_LOCAL_SGE_RING_SIZE (12)
++#define U_ETH_SGL_SIZE (8)
++
++
++#define U_ETH_BDS_PER_PAGE_MASK \
++ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
++#define U_ETH_CQE_PER_PAGE_MASK \
++ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
++#define U_ETH_SGES_PER_PAGE_MASK \
++ ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
++
++#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
++ (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
++
++
++#define TU_ETH_CQES_PER_PAGE \
++ (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
++#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
++#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
++
++#define U_ETH_UNDEFINED_Q 0xFF
- };
-@@ -192,36 +178,21 @@ struct port_hw_cfg { /* port 0: 0x
- u32 rdma_mac_lower;
+ /* values of command IDs in the ramrod message */
+-#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
+-#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
+-#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
+-#define RAMROD_CMD_ID_ETH_UPDATE (100)
+-#define RAMROD_CMD_ID_ETH_HALT (105)
+-#define RAMROD_CMD_ID_ETH_SET_MAC (110)
+-#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
+-#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
+-#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
++#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
++#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
++#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
++#define RAMROD_CMD_ID_ETH_UPDATE (100)
++#define RAMROD_CMD_ID_ETH_HALT (105)
++#define RAMROD_CMD_ID_ETH_SET_MAC (110)
++#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
++#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
++#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
- u32 serdes_config;
-- /* for external PHY, or forced mode or during AN */
--#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
--#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
--
--#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
--#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
--
-- u16 serdes_tx_driver_pre_emphasis[16];
-- u16 serdes_rx_driver_equalizer[16];
--
-- u32 xgxs_config_lane0;
-- u32 xgxs_config_lane1;
-- u32 xgxs_config_lane2;
-- u32 xgxs_config_lane3;
-- /* for external PHY, or forced mode or during AN */
--#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
--#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
--
--#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
--#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
--
-- u16 xgxs_tx_driver_pre_emphasis_lane0[16];
-- u16 xgxs_tx_driver_pre_emphasis_lane1[16];
-- u16 xgxs_tx_driver_pre_emphasis_lane2[16];
-- u16 xgxs_tx_driver_pre_emphasis_lane3[16];
--
-- u16 xgxs_rx_driver_equalizer_lane0[16];
-- u16 xgxs_rx_driver_equalizer_lane1[16];
-- u16 xgxs_rx_driver_equalizer_lane2[16];
-- u16 xgxs_rx_driver_equalizer_lane3[16];
-+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
-+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
-+
-+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
-+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
-+
-+
-+ u32 Reserved0[16]; /* 0x158 */
-+
-+ /* for external PHY, or forced mode or during AN */
-+ u16 xgxs_config_rx[4]; /* 0x198 */
-+
-+ u16 xgxs_config_tx[4]; /* 0x1A0 */
-+
-+ u32 Reserved1[64]; /* 0x1A8 */
-
- u32 lane_config;
- #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
-@@ -259,7 +230,7 @@ struct port_hw_cfg { /* port 0: 0x
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
--#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
-+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
- #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
-@@ -314,6 +285,13 @@ struct shared_feat_cfg { /* NVRAM Of
- u32 config; /* 0x450 */
- #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
-+ /* Use the values from options 47 and 48 instead of the HW default
-+ values */
-+#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
-+#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
+ /* command values for set mac command */
+-#define T_ETH_MAC_COMMAND_SET 0
+-#define T_ETH_MAC_COMMAND_INVALIDATE 1
++#define T_ETH_MAC_COMMAND_SET 0
++#define T_ETH_MAC_COMMAND_INVALIDATE 1
+
-+#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
++#define T_ETH_INDIRECTION_TABLE_SIZE 128
+
+-#define T_ETH_INDIRECTION_TABLE_SIZE 128
++/*The CRC32 seed, that is used for the hash(reduction) multicast address */
++#define T_ETH_CRC32_HASH_SEED 0x00000000
+
+ /* Maximal L2 clients supported */
+-#define ETH_MAX_RX_CLIENTS (18)
++#define ETH_MAX_RX_CLIENTS_E1 19
++#define ETH_MAX_RX_CLIENTS_E1H 25
+
- };
++/* Maximal aggregation queues supported */
++#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
++#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
++
+
+ /**
+ * This file defines HSI constatnts common to all microcode flows
+ */
+
+ /* Connection types */
+-#define ETH_CONNECTION_TYPE 0
++#define ETH_CONNECTION_TYPE 0
++#define TOE_CONNECTION_TYPE 1
++#define RDMA_CONNECTION_TYPE 2
++#define ISCSI_CONNECTION_TYPE 3
++#define FCOE_CONNECTION_TYPE 4
++#define RESERVED_CONNECTION_TYPE_0 5
++#define RESERVED_CONNECTION_TYPE_1 6
++#define RESERVED_CONNECTION_TYPE_2 7
+
+-#define PROTOCOL_STATE_BIT_OFFSET 6
+
+-#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
++#define PROTOCOL_STATE_BIT_OFFSET 6
++
++#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
++#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
++#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+ /* microcode fixed page page size 4K (chains and ring segments) */
+-#define MC_PAGE_SIZE (4096)
++#define MC_PAGE_SIZE (4096)
+
+-/* Host coalescing constants */
+
+-/* IGU constants */
+-#define IGU_PORT_BASE 0x0400
+-
+-#define IGU_ADDR_MSIX 0x0000
+-#define IGU_ADDR_INT_ACK 0x0200
+-#define IGU_ADDR_PROD_UPD 0x0201
+-#define IGU_ADDR_ATTN_BITS_UPD 0x0202
+-#define IGU_ADDR_ATTN_BITS_SET 0x0203
+-#define IGU_ADDR_ATTN_BITS_CLR 0x0204
+-#define IGU_ADDR_COALESCE_NOW 0x0205
+-#define IGU_ADDR_SIMD_MASK 0x0206
+-#define IGU_ADDR_SIMD_NOMASK 0x0207
+-#define IGU_ADDR_MSI_CTL 0x0210
+-#define IGU_ADDR_MSI_ADDR_LO 0x0211
+-#define IGU_ADDR_MSI_ADDR_HI 0x0212
+-#define IGU_ADDR_MSI_DATA 0x0213
+-
+-#define IGU_INT_ENABLE 0
+-#define IGU_INT_DISABLE 1
+-#define IGU_INT_NOP 2
+-#define IGU_INT_NOP2 3
++/* Host coalescing constants */
+
+ /* index numbers */
+-#define HC_USTORM_DEF_SB_NUM_INDICES 4
+-#define HC_CSTORM_DEF_SB_NUM_INDICES 8
+-#define HC_XSTORM_DEF_SB_NUM_INDICES 4
+-#define HC_TSTORM_DEF_SB_NUM_INDICES 4
+-#define HC_USTORM_SB_NUM_INDICES 4
+-#define HC_CSTORM_SB_NUM_INDICES 4
++#define HC_USTORM_DEF_SB_NUM_INDICES 8
++#define HC_CSTORM_DEF_SB_NUM_INDICES 8
++#define HC_XSTORM_DEF_SB_NUM_INDICES 4
++#define HC_TSTORM_DEF_SB_NUM_INDICES 4
++#define HC_USTORM_SB_NUM_INDICES 4
++#define HC_CSTORM_SB_NUM_INDICES 4
+
+ /* index values - which counterto update */
+
+-#define HC_INDEX_U_ETH_RX_CQ_CONS 1
++#define HC_INDEX_U_TOE_RX_CQ_CONS 0
++#define HC_INDEX_U_ETH_RX_CQ_CONS 1
++#define HC_INDEX_U_ETH_RX_BD_CONS 2
++#define HC_INDEX_U_FCOE_EQ_CONS 3
+
+-#define HC_INDEX_C_ETH_TX_CQ_CONS 1
++#define HC_INDEX_C_TOE_TX_CQ_CONS 0
++#define HC_INDEX_C_ETH_TX_CQ_CONS 1
++#define HC_INDEX_C_ISCSI_EQ_CONS 2
+
+-#define HC_INDEX_DEF_X_SPQ_CONS 0
++#define HC_INDEX_DEF_X_SPQ_CONS 0
++
++#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
++#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
++#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
++#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
++#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
++#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
++
++#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
++#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
++#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
++#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
+
+-#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
+-#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
+
+ /* used by the driver to get the SB offset */
+-#define USTORM_ID 0
+-#define CSTORM_ID 1
+-#define XSTORM_ID 2
+-#define TSTORM_ID 3
+-#define ATTENTION_ID 4
++#define USTORM_ID 0
++#define CSTORM_ID 1
++#define XSTORM_ID 2
++#define TSTORM_ID 3
++#define ATTENTION_ID 4
+
+ /* max number of slow path commands per port */
+-#define MAX_RAMRODS_PER_PORT (8)
++#define MAX_RAMRODS_PER_PORT (8)
+
+ /* values for RX ETH CQE type field */
+-#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
+-#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
+-
+-/* MAC address list size */
+-#define T_MAC_ADDRESS_LIST_SIZE (96)
+-
++#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
++#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
++
++
++/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
++#define EMULATION_FREQUENCY_FACTOR (1600)
++#define FPGA_FREQUENCY_FACTOR (100)
++
++#define TIMERS_TICK_SIZE_CHIP (1e-3)
++#define TIMERS_TICK_SIZE_EMUL \
++ ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
++#define TIMERS_TICK_SIZE_FPGA \
++ ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
++
++#define TSEMI_CLK1_RESUL_CHIP (1e-3)
++#define TSEMI_CLK1_RESUL_EMUL \
++ ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
++#define TSEMI_CLK1_RESUL_FPGA \
++ ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
++
++#define USEMI_CLK1_RESUL_CHIP \
++ (TIMERS_TICK_SIZE_CHIP)
++#define USEMI_CLK1_RESUL_EMUL \
++ (TIMERS_TICK_SIZE_EMUL)
++#define USEMI_CLK1_RESUL_FPGA \
++ (TIMERS_TICK_SIZE_FPGA)
++
++#define XSEMI_CLK1_RESUL_CHIP (1e-3)
++#define XSEMI_CLK1_RESUL_EMUL \
++ ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
++#define XSEMI_CLK1_RESUL_FPGA \
++ ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
++
++#define XSEMI_CLK2_RESUL_CHIP (1e-6)
++#define XSEMI_CLK2_RESUL_EMUL \
++ ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
++#define XSEMI_CLK2_RESUL_FPGA \
++ ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
++
++#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
++#define SDM_TIMER_TICK_RESUL_EMUL \
++ ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
++#define SDM_TIMER_TICK_RESUL_FPGA \
++ ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
++
++
++/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+ #define XSTORM_IP_ID_ROLL_HALF 0x8000
+ #define XSTORM_IP_ID_ROLL_ALL 0
+
+-#define FW_LOG_LIST_SIZE (50)
++#define FW_LOG_LIST_SIZE (50)
++
++#define NUM_OF_PROTOCOLS 4
++#define NUM_OF_SAFC_BITS 16
++#define MAX_COS_NUMBER 4
++#define MAX_T_STAT_COUNTER_ID 18
++#define MAX_X_STAT_COUNTER_ID 18
++#define MAX_U_STAT_COUNTER_ID 18
++
+
+-#define NUM_OF_PROTOCOLS 4
+-#define MAX_COS_NUMBER 16
+-#define MAX_T_STAT_COUNTER_ID 18
++#define UNKNOWN_ADDRESS 0
++#define UNICAST_ADDRESS 1
++#define MULTICAST_ADDRESS 2
++#define BROADCAST_ADDRESS 3
+
+-#define T_FAIR 1
+-#define FAIR_MEM 2
+-#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
++#define SINGLE_FUNCTION 0
++#define MULTI_FUNCTION 1
+-#define UNKNOWN_ADDRESS 0
+-#define UNICAST_ADDRESS 1
+-#define MULTICAST_ADDRESS 2
+-#define BROADCAST_ADDRESS 3
++#define IP_V4 0
++#define IP_V6 1
+
+diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
+index b21075c..c416823 100644
+--- a/drivers/net/bnx2x_hsi.h
++++ b/drivers/net/bnx2x_hsi.h
+@@ -132,6 +132,12 @@ struct shared_hw_cfg { /* NVRAM Offset */
+ #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
+ #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
+ #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
++#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
+
+ #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
+ #define SHARED_HW_CFG_BOARD_VER_SHIFT 16
+@@ -313,6 +319,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
+
+ u32 config; /* 0x450 */
+ #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
++#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
+
+ };
-@@ -365,6 +343,11 @@ struct port_feat_cfg { /* port 0:
- #define PORT_FEATURE_MBA_ENABLED 0x02000000
- #define PORT_FEATURE_MFW_ENABLED 0x04000000
-
-+ /* Check the optic vendor via i2c before allowing it to be used by
-+ SW */
-+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED 0x00000000
-+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED 0x08000000
-+
- u32 wol_config;
- /* Default is used when driver sets to "auto" mode */
- #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
-@@ -502,28 +485,41 @@ struct port_feat_cfg { /* port 0:
+@@ -502,28 +509,41 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
};
@@ -13139,7 +12461,7 @@
+/****************************************************************************
+ * Device Information *
+ ****************************************************************************/
-+struct shm_dev_info { /* size */
++struct dev_info { /* size */
- u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
+ u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
@@ -13180,24 +12502,18 @@
/* This value (in milliseconds) determines the frequency of the driver
-@@ -619,10 +615,14 @@ struct drv_port_mb {
+@@ -619,7 +639,9 @@ struct drv_port_mb {
#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
- u32 reserved[3];
+ u32 port_stx;
-
--};
-+ u32 reserved[2];
-
-+ /* MCP firmware does not use this field */
-+ u32 ext_phy_fw_version;
+
-+};
++ u32 reserved[2];
- struct drv_func_mb {
+ };
-@@ -642,6 +642,11 @@ struct drv_func_mb {
+@@ -642,6 +664,11 @@ struct drv_func_mb {
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
@@ -13209,7 +12525,7 @@
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
u32 drv_mb_param;
-@@ -671,6 +676,11 @@ struct drv_func_mb {
+@@ -671,6 +698,11 @@ struct drv_func_mb {
#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
@@ -13221,7 +12537,7 @@
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
u32 fw_mb_param;
-@@ -696,7 +706,13 @@ struct drv_func_mb {
+@@ -696,7 +728,13 @@ struct drv_func_mb {
u32 iscsi_boot_signature;
u32 iscsi_boot_block_offset;
@@ -13236,7 +12552,7 @@
};
-@@ -713,6 +729,88 @@ struct mgmtfw_state {
+@@ -713,6 +751,92 @@ struct mgmtfw_state {
/****************************************************************************
@@ -13316,7 +12632,11 @@
+
+ struct shared_mf_cfg shared_mf_config;
+ struct port_mf_cfg port_mf_config[PORT_MAX];
++#if defined(b710)
++ struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
++#else
+ struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
++#endif
+
+};
+
@@ -13325,16 +12645,7 @@
* Shared Memory Region *
****************************************************************************/
struct shmem_region { /* SharedMem Offset (size) */
-@@ -738,7 +836,7 @@ struct shmem_region { /* Shar
- #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
- #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
-
-- struct dev_info dev_info; /* 0x8 (0x438) */
-+ struct shm_dev_info dev_info; /* 0x8 (0x438) */
-
- u8 reserved[52*PORT_MAX];
-
-@@ -747,14 +845,350 @@ struct shmem_region { /* Shar
+@@ -747,14 +871,350 @@ struct shmem_region { /* SharedMem Offset (size) */
struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
@@ -13688,31 +12999,7 @@
#define BCM_5710_FW_COMPILE_FLAGS 1
-@@ -762,18 +1196,18 @@ struct shmem_region { /* Shar
- * attention bits
- */
- struct atten_def_status_block {
-- u32 attn_bits;
-- u32 attn_bits_ack;
-+ __le32 attn_bits;
-+ __le32 attn_bits_ack;
- #if defined(__BIG_ENDIAN)
-- u16 attn_bits_index;
-+ __le16 attn_bits_index;
- u8 reserved0;
- u8 status_block_id;
- #elif defined(__LITTLE_ENDIAN)
- u8 status_block_id;
- u8 reserved0;
-- u16 attn_bits_index;
-+ __le16 attn_bits_index;
- #endif
-- u32 reserved1;
-+ __le32 reserved1;
- };
-
-
-@@ -793,7 +1227,7 @@ struct doorbell_hdr {
+@@ -793,7 +1253,7 @@ struct doorbell_hdr {
};
/*
@@ -13721,7 +13008,7 @@
*/
struct doorbell {
#if defined(__BIG_ENDIAN)
-@@ -809,7 +1243,7 @@ struct doorbell {
+@@ -809,7 +1269,7 @@ struct doorbell {
/*
@@ -13730,12 +13017,8 @@
*/
struct igu_ack_register {
#if defined(__BIG_ENDIAN)
-@@ -846,11 +1280,13 @@ struct igu_ack_register {
- * Parser parsing flags field
- */
- struct parsing_flags {
-- u16 flags;
-+ __le16 flags;
+@@ -849,8 +1309,10 @@ struct parsing_flags {
+ u16 flags;
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
-#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
@@ -13747,20 +13030,20 @@
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
-@@ -874,6 +1310,12 @@ struct parsing_flags {
+@@ -874,6 +1336,12 @@ struct parsing_flags {
};
+struct regpair {
-+ __le32 lo;
-+ __le32 hi;
++ u32 lo;
++ u32 hi;
+};
+
+
/*
* dmae command structure
*/
-@@ -901,8 +1343,10 @@ struct dmae_command {
+@@ -901,8 +1369,10 @@ struct dmae_command {
#define DMAE_COMMAND_SRC_RESET_SHIFT 13
#define DMAE_COMMAND_DST_RESET (0x1<<14)
#define DMAE_COMMAND_DST_RESET_SHIFT 14
@@ -13773,14 +13056,25 @@
u32 src_addr_lo;
u32 src_addr_hi;
u32 dst_addr_lo;
-@@ -952,72 +1396,103 @@ struct double_regpair {
+@@ -952,72 +1422,103 @@ struct double_regpair {
/*
+- * The eth Rx Buffer Descriptor
+ * The eth storm context of Ustorm (configuration part)
-+ */
+ */
+-struct eth_rx_bd {
+- u32 addr_lo;
+- u32 addr_hi;
+-};
+-
+-/*
+- * The eth storm context of Ustorm
+- */
+-struct ustorm_eth_st_context {
+struct ustorm_eth_st_context_config {
-+#if defined(__BIG_ENDIAN)
+ #if defined(__BIG_ENDIAN)
+- u8 sb_index_number;
+ u8 flags;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
@@ -13792,21 +13086,33 @@
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
-+ u8 status_block_id;
+ u8 status_block_id;
+- u8 __local_rx_bd_cons;
+- u8 __local_rx_bd_prod;
+ u8 clientId;
+ u8 sb_index_numbers;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
-+#elif defined(__LITTLE_ENDIAN)
+ #elif defined(__LITTLE_ENDIAN)
+- u8 __local_rx_bd_prod;
+- u8 __local_rx_bd_cons;
+ u8 sb_index_numbers;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
+ u8 clientId;
-+ u8 status_block_id;
+ u8 status_block_id;
+- u8 sb_index_number;
+-#endif
+-#if defined(__BIG_ENDIAN)
+- u16 rcq_cons;
+- u16 rx_bd_cons;
+-#elif defined(__LITTLE_ENDIAN)
+- u16 rx_bd_cons;
+- u16 rcq_cons;
+ u8 flags;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
@@ -13818,25 +13124,55 @@
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
-+#endif
-+#if defined(__BIG_ENDIAN)
+ #endif
+- u32 rx_bd_page_base_lo;
+- u32 rx_bd_page_base_hi;
+- u32 rcq_base_address_lo;
+- u32 rcq_base_address_hi;
+ #if defined(__BIG_ENDIAN)
+- u16 __num_of_returned_cqes;
+- u8 num_rss;
+- u8 flags;
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
+-#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
+-#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
+ u16 bd_buff_size;
+ u8 statistics_counter_id;
+ u8 mc_alignment_log_size;
-+#elif defined(__LITTLE_ENDIAN)
+ #elif defined(__LITTLE_ENDIAN)
+- u8 flags;
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
+-#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
+-#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
+-#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
+- u8 num_rss;
+- u16 __num_of_returned_cqes;
+ u8 mc_alignment_log_size;
+ u8 statistics_counter_id;
+ u16 bd_buff_size;
-+#endif
-+#if defined(__BIG_ENDIAN)
+ #endif
+ #if defined(__BIG_ENDIAN)
+- u16 mc_alignment_size;
+- u16 agg_threshold;
+ u8 __local_sge_prod;
+ u8 __local_bd_prod;
+ u16 sge_buff_size;
-+#elif defined(__LITTLE_ENDIAN)
+ #elif defined(__LITTLE_ENDIAN)
+- u16 agg_threshold;
+- u16 mc_alignment_size;
+ u16 sge_buff_size;
+ u8 __local_bd_prod;
+ u8 __local_sge_prod;
-+#endif
+ #endif
+ u32 reserved;
+ u32 bd_page_base_lo;
+ u32 bd_page_base_hi;
@@ -13845,96 +13181,39 @@
+};
+
+/*
- * The eth Rx Buffer Descriptor
- */
- struct eth_rx_bd {
-- u32 addr_lo;
-- u32 addr_hi;
-+ __le32 addr_lo;
-+ __le32 addr_hi;
++ * The eth Rx Buffer Descriptor
++ */
++struct eth_rx_bd {
++ u32 addr_lo;
++ u32 addr_hi;
+};
+
+/*
+ * The eth Rx SGE Descriptor
+ */
+struct eth_rx_sge {
-+ __le32 addr_lo;
-+ __le32 addr_hi;
++ u32 addr_lo;
++ u32 addr_hi;
+};
+
+/*
+ * Local BDs and SGEs rings (in ETH)
+ */
+struct eth_local_rx_rings {
-+ struct eth_rx_bd __local_bd_ring[16];
+ struct eth_rx_bd __local_bd_ring[16];
+ struct eth_rx_sge __local_sge_ring[12];
- };
-
- /*
- * The eth storm context of Ustorm
- */
- struct ustorm_eth_st_context {
--#if defined(__BIG_ENDIAN)
-- u8 sb_index_number;
-- u8 status_block_id;
-- u8 __local_rx_bd_cons;
-- u8 __local_rx_bd_prod;
--#elif defined(__LITTLE_ENDIAN)
-- u8 __local_rx_bd_prod;
-- u8 __local_rx_bd_cons;
-- u8 status_block_id;
-- u8 sb_index_number;
--#endif
--#if defined(__BIG_ENDIAN)
-- u16 rcq_cons;
-- u16 rx_bd_cons;
--#elif defined(__LITTLE_ENDIAN)
-- u16 rx_bd_cons;
-- u16 rcq_cons;
--#endif
-- u32 rx_bd_page_base_lo;
-- u32 rx_bd_page_base_hi;
-- u32 rcq_base_address_lo;
-- u32 rcq_base_address_hi;
--#if defined(__BIG_ENDIAN)
-- u16 __num_of_returned_cqes;
-- u8 num_rss;
-- u8 flags;
--#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
--#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
--#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
--#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
--#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
--#elif defined(__LITTLE_ENDIAN)
-- u8 flags;
--#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
--#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
--#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
--#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
--#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
--#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
-- u8 num_rss;
-- u16 __num_of_returned_cqes;
--#endif
--#if defined(__BIG_ENDIAN)
-- u16 mc_alignment_size;
-- u16 agg_threshold;
--#elif defined(__LITTLE_ENDIAN)
-- u16 agg_threshold;
-- u16 mc_alignment_size;
--#endif
-- struct eth_rx_bd __local_bd_ring[16];
++};
++
++/*
++ * The eth storm context of Ustorm
++ */
++struct ustorm_eth_st_context {
+ struct ustorm_eth_st_context_config common;
+ struct eth_local_rx_rings __rings;
};
/*
-@@ -1088,9 +1563,9 @@ struct xstorm_eth_extra_ag_context_secti
+@@ -1088,9 +1589,9 @@ struct xstorm_eth_extra_ag_context_section {
#if defined(__BIG_ENDIAN)
u16 __reserved3;
u8 __reserved2;
@@ -13946,16 +13225,7 @@
u8 __reserved2;
u16 __reserved3;
#endif
-@@ -1193,7 +1668,7 @@ struct xstorm_eth_ag_context {
- };
-
- /*
-- * The eth aggregative context section of Tstorm
-+ * The eth extra aggregative context section of Tstorm
- */
- struct tstorm_eth_extra_ag_context_section {
- u32 __agg_val1;
-@@ -1368,11 +1843,17 @@ struct timers_block_context {
+@@ -1368,11 +1869,17 @@ struct timers_block_context {
u32 __reserved_0;
u32 __reserved_1;
u32 __reserved_2;
@@ -13975,41 +13245,7 @@
*/
struct eth_tx_bd_flags {
u8 as_bitfield;
-@@ -1398,11 +1879,11 @@ struct eth_tx_bd_flags {
- * The eth Tx Buffer Descriptor
- */
- struct eth_tx_bd {
-- u32 addr_lo;
-- u32 addr_hi;
-- u16 nbd;
-- u16 nbytes;
-- u16 vlan;
-+ __le32 addr_lo;
-+ __le32 addr_hi;
-+ __le16 nbd;
-+ __le16 nbytes;
-+ __le16 vlan;
- struct eth_tx_bd_flags bd_flags;
- u8 general_data;
- #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
-@@ -1445,11 +1926,11 @@ struct eth_tx_parse_bd {
- #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
- u8 ip_hlen;
- s8 cs_offset;
-- u16 total_hlen;
-- u16 lso_mss;
-- u16 tcp_pseudo_csum;
-- u16 ip_id;
-- u32 tcp_send_seq;
-+ __le16 total_hlen;
-+ __le16 lso_mss;
-+ __le16 tcp_pseudo_csum;
-+ __le16 ip_id;
-+ __le32 tcp_send_seq;
- };
-
- /*
-@@ -1478,11 +1959,19 @@ struct xstorm_eth_st_context {
+@@ -1478,11 +1985,19 @@ struct xstorm_eth_st_context {
u32 tx_bd_page_base_hi;
#if defined(__BIG_ENDIAN)
u16 tx_bd_cons;
@@ -14031,7 +13267,7 @@
u16 tx_bd_cons;
#endif
u32 db_data_addr_lo;
-@@ -1526,7 +2015,7 @@ struct eth_context {
+@@ -1526,7 +2041,7 @@ struct eth_context {
/*
@@ -14040,99 +13276,61 @@
*/
struct eth_tx_doorbell {
#if defined(__BIG_ENDIAN)
-@@ -1557,44 +2046,44 @@ struct eth_tx_doorbell {
- * ustorm status block
- */
+@@ -1559,7 +2074,7 @@ struct eth_tx_doorbell {
struct ustorm_def_status_block {
-- u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
- * cstorm status block
- */
+@@ -1570,7 +2085,7 @@ struct ustorm_def_status_block {
struct cstorm_def_status_block {
-- u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
- * xstorm status block
- */
+@@ -1581,7 +2096,7 @@ struct cstorm_def_status_block {
struct xstorm_def_status_block {
-- u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
- * tstorm status block
- */
+@@ -1592,7 +2107,7 @@ struct xstorm_def_status_block {
struct tstorm_def_status_block {
-- u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
-@@ -1613,22 +2102,22 @@ struct host_def_status_block {
- * ustorm status block
- */
+@@ -1615,7 +2130,7 @@ struct host_def_status_block {
struct ustorm_status_block {
-- u16 index_values[HC_USTORM_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_USTORM_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_USTORM_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
- * cstorm status block
- */
+@@ -1626,7 +2141,7 @@ struct ustorm_status_block {
struct cstorm_status_block {
-- u16 index_values[HC_CSTORM_SB_NUM_INDICES];
-- u16 status_block_index;
+ u16 index_values[HC_CSTORM_SB_NUM_INDICES];
+ u16 status_block_index;
- u8 reserved0;
-+ __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
-+ __le16 status_block_index;
+ u8 func;
u8 status_block_id;
-- u32 __flags;
-+ __le32 __flags;
+ u32 __flags;
};
-
- /*
-@@ -1644,9 +2133,9 @@ struct host_status_block {
+@@ -1644,9 +2159,9 @@ struct host_status_block {
* The data for RSS setup ramrod
*/
struct eth_client_setup_ramrod_data {
@@ -14145,7 +13343,7 @@
u16 reserved1;
};
-@@ -1664,20 +2153,21 @@ struct eth_dynamic_hc_config {
+@@ -1664,20 +2179,21 @@ struct eth_dynamic_hc_config {
* regular eth FP CQE parameters struct
*/
struct eth_fast_path_rx_cqe {
@@ -14181,25 +13379,22 @@
u8 status_flags;
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
-@@ -1692,11 +2182,13 @@ struct eth_fast_path_rx_cqe {
+@@ -1692,11 +2208,13 @@ struct eth_fast_path_rx_cqe {
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
u8 placement_offset;
-- u32 rss_hash_result;
-- u16 vlan_tag;
-- u16 pkt_len;
-- u16 queue_index;
+ u8 queue_index;
-+ __le32 rss_hash_result;
-+ __le16 vlan_tag;
-+ __le16 pkt_len;
-+ __le16 len_on_bd;
+ u32 rss_hash_result;
+ u16 vlan_tag;
+ u16 pkt_len;
+- u16 queue_index;
++ u16 len_on_bd;
struct parsing_flags pars_flags;
-+ __le16 sgl[8];
++ u16 sgl[8];
};
-@@ -1704,34 +2196,41 @@ struct eth_fast_path_rx_cqe {
+@@ -1704,12 +2222,29 @@ struct eth_fast_path_rx_cqe {
* The data for RSS setup ramrod
*/
struct eth_halt_ramrod_data {
@@ -14210,12 +13405,8 @@
/*
-- * Place holder for ramrods protocol specific data
+ * The data for statistics query ramrod
- */
--struct ramrod_data {
-- u32 data_lo;
-- u32 data_hi;
++ */
+struct eth_query_ramrod_data {
+#if defined(__BIG_ENDIAN)
+ u8 reserved0;
@@ -14227,104 +13418,72 @@
+ u8 reserved0;
+#endif
+ u32 ctr_id_vector;
- };
-
++};
+
- /*
-- * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
-+ * Place holder for ramrods protocol specific data
++
++/*
+ * Place holder for ramrods protocol specific data
*/
--union eth_ramrod_data {
-- struct ramrod_data general;
-+struct ramrod_data {
-+ __le32 data_lo;
-+ __le32 data_hi;
+ struct ramrod_data {
+@@ -1718,7 +2253,7 @@ struct ramrod_data {
};
--
/*
-- * Rx Last BD in page (in ETH)
+- * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
+ * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
*/
--struct eth_rx_bd_next_page {
-- u32 addr_lo;
-- u32 addr_hi;
-- u8 reserved[8];
-+union eth_ramrod_data {
-+ struct ramrod_data general;
- };
-
-
-@@ -1739,25 +2238,29 @@ struct eth_rx_bd_next_page {
+ union eth_ramrod_data {
+ struct ramrod_data general;
+@@ -1739,15 +2274,20 @@ struct eth_rx_bd_next_page {
* Eth Rx Cqe structure- general structure for ramrods
*/
struct common_ramrod_eth_rx_cqe {
- u8 type;
- u8 conn_type_3b;
- u16 reserved;
-- u32 conn_and_cmd_data;
+ u8 ramrod_type;
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
+ u8 conn_type;
-+ __le16 reserved1;
-+ __le32 conn_and_cmd_data;
++ u16 reserved1;
+ u32 conn_and_cmd_data;
#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
struct ramrod_data protocol_data;
-+ __le32 reserved2[4];
++ u32 reserved2[4];
};
/*
- * Rx Last CQE in page (in ETH)
- */
+@@ -1756,8 +2296,7 @@ struct common_ramrod_eth_rx_cqe {
struct eth_rx_cqe_next_page {
-- u32 addr_lo;
-- u32 addr_hi;
+ u32 addr_lo;
+ u32 addr_hi;
- u32 reserved0;
- u32 reserved1;
-+ __le32 addr_lo;
-+ __le32 addr_hi;
-+ __le32 reserved[6];
++ u32 reserved[6];
};
/*
-@@ -1774,26 +2277,21 @@ union eth_rx_cqe {
- * common data for all protocols
- */
- struct spe_hdr {
-- u32 conn_and_cmd_data;
-+ __le32 conn_and_cmd_data;
- #define SPE_HDR_CID (0xFFFFFF<<0)
- #define SPE_HDR_CID_SHIFT 0
- #define SPE_HDR_CMD_ID (0xFF<<24)
- #define SPE_HDR_CMD_ID_SHIFT 24
-- u16 type;
-+ __le16 type;
- #define SPE_HDR_CONN_TYPE (0xFF<<0)
- #define SPE_HDR_CONN_TYPE_SHIFT 0
- #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
- #define SPE_HDR_COMMON_RAMROD_SHIFT 8
-- u16 reserved;
--};
--
+@@ -1787,13 +2326,8 @@ struct spe_hdr {
+ u16 reserved;
+ };
+
-struct regpair {
- u32 lo;
- u32 hi;
-+ __le16 reserved;
- };
-
+-};
+-
/*
- * ethernet slow path element
+ * Ethernet slow path element
*/
union eth_specific_data {
u8 protocol_data[8];
-@@ -1802,10 +2300,11 @@ union eth_specific_data {
+@@ -1802,10 +2336,11 @@ union eth_specific_data {
struct eth_halt_ramrod_data halt_ramrod_data;
struct regpair leading_cqe_addr;
struct regpair update_data_addr;
@@ -14337,17 +13496,7 @@
*/
struct eth_spe {
struct spe_hdr hdr;
-@@ -1817,17 +2316,20 @@ struct eth_spe {
- * doorbell data in host memory
- */
- struct eth_tx_db_data {
-- u32 packets_prod;
-- u16 bds_prod;
-- u16 reserved;
-+ __le32 packets_prod;
-+ __le16 bds_prod;
-+ __le16 reserved;
- };
+@@ -1824,10 +2359,13 @@ struct eth_tx_db_data {
/*
@@ -14363,7 +13512,7 @@
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
-@@ -1836,21 +2338,40 @@ struct tstorm_eth_function_common_config
+@@ -1836,21 +2374,40 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
@@ -14415,7 +13564,7 @@
};
/*
-@@ -1866,9 +2387,9 @@ struct eth_update_ramrod_data {
+@@ -1866,9 +2423,9 @@ struct eth_update_ramrod_data {
* MAC filtering configuration command header
*/
struct mac_configuration_hdr {
@@ -14427,33 +13576,18 @@
u32 reserved1;
};
-@@ -1876,10 +2397,10 @@ struct mac_configuration_hdr {
- * MAC address in list for ramrod
- */
- struct tstorm_cam_entry {
-- u16 lsb_mac_addr;
-- u16 middle_mac_addr;
-- u16 msb_mac_addr;
-- u16 flags;
-+ __le16 lsb_mac_addr;
-+ __le16 middle_mac_addr;
-+ __le16 msb_mac_addr;
-+ __le16 flags;
- #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
- #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
- #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
-@@ -1925,15 +2446,55 @@ struct mac_configuration_cmd {
+@@ -1925,15 +2482,55 @@ struct mac_configuration_cmd {
/*
+ * MAC address in list for ramrod
+ */
+struct mac_configuration_entry_e1h {
-+ __le16 lsb_mac_addr;
-+ __le16 middle_mac_addr;
-+ __le16 msb_mac_addr;
-+ __le16 vlan_id;
-+ __le16 e1hov_id;
++ u16 lsb_mac_addr;
++ u16 middle_mac_addr;
++ u16 msb_mac_addr;
++ u16 vlan_id;
++ u16 e1hov_id;
+ u8 client_id;
+ u8 flags;
+#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
@@ -14500,7 +13634,7 @@
#endif
#if defined(__BIG_ENDIAN)
u16 drop_flags;
-@@ -1941,42 +2502,46 @@ struct tstorm_eth_client_config {
+@@ -1941,42 +2538,46 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
@@ -14575,257 +13709,230 @@
#endif
};
-@@ -1992,96 +2557,132 @@ struct tstorm_eth_mac_filter_config {
+@@ -1992,103 +2593,119 @@ struct tstorm_eth_mac_filter_config {
u32 bcast_drop_all;
u32 bcast_accept_all;
u32 strict_vlan;
- u32 __secondary_vlan_clients;
+ u32 vlan_filter[2];
+ u32 reserved;
-+};
-+
-+
-+/*
-+ * common flag to indicate existance of TPA.
-+ */
-+struct tstorm_eth_tpa_exist {
-+#if defined(__BIG_ENDIAN)
-+ u16 reserved1;
-+ u8 reserved0;
-+ u8 tpa_exist;
-+#elif defined(__LITTLE_ENDIAN)
-+ u8 tpa_exist;
-+ u8 reserved0;
-+ u16 reserved1;
-+#endif
-+ u32 reserved2;
};
-struct rate_shaping_per_protocol {
+/*
-+ * Three RX producers for ETH
++ * common flag to indicate existance of TPA.
+ */
-+struct ustorm_eth_rx_producers {
++struct tstorm_eth_tpa_exist {
#if defined(__BIG_ENDIAN)
- u16 reserved0;
- u16 protocol_rate;
-+ u16 bd_prod;
-+ u16 cqe_prod;
++ u16 reserved1;
++ u8 reserved0;
++ u8 tpa_exist;
#elif defined(__LITTLE_ENDIAN)
- u16 protocol_rate;
- u16 reserved0;
-+ u16 cqe_prod;
-+ u16 bd_prod;
-+#endif
-+#if defined(__BIG_ENDIAN)
-+ u16 reserved;
-+ u16 sge_prod;
-+#elif defined(__LITTLE_ENDIAN)
-+ u16 sge_prod;
-+ u16 reserved;
++ u8 tpa_exist;
++ u8 reserved0;
++ u16 reserved1;
#endif
- u32 protocol_quota;
- s32 current_credit;
- u32 reserved;
++ u32 reserved2;
};
-struct rate_shaping_vars {
- struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
- u32 pause_mask;
- u32 periodic_stop;
-+
-+/*
-+ * per-port SAFC demo variables
-+ */
-+struct cmng_flags_per_port {
-+ u8 con_number[NUM_OF_PROTOCOLS];
-+ u32 cmng_enables;
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
-+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
-+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
-+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
-+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
-+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
-+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
-+#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
-+};
-+
-+
-+/*
-+ * per-port rate shaping variables
-+ */
-+struct rate_shaping_vars_per_port {
- u32 rs_periodic_timeout;
- u32 rs_threshold;
+- u32 rs_periodic_timeout;
+- u32 rs_threshold;
- u32 last_periodic_time;
- u32 reserved;
- };
+-};
-struct fairness_per_protocol {
- u32 credit_delta;
- s32 fair_credit;
--#if defined(__BIG_ENDIAN)
++/*
++ * Three RX producers for ETH
++ */
++struct ustorm_eth_rx_producers {
+ #if defined(__BIG_ENDIAN)
- u16 reserved0;
- u8 state;
- u8 weight;
--#elif defined(__LITTLE_ENDIAN)
++ u16 bd_prod;
++ u16 cqe_prod;
+ #elif defined(__LITTLE_ENDIAN)
- u8 weight;
- u8 state;
- u16 reserved0;
--#endif
++ u16 cqe_prod;
++ u16 bd_prod;
+ #endif
- u32 reserved1;
-};
-
+-
-struct fairness_vars {
- struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
-+/*
-+ * per-port fairness variables
-+ */
-+struct fairness_vars_per_port {
- u32 upper_bound;
+- u32 upper_bound;
- u32 port_rate;
- u32 pause_mask;
- u32 fair_threshold;
-+ u32 fairness_timeout;
- };
-
+- u32 fair_threshold;
+-};
+-
-struct safc_struct {
- u32 cur_pause_mask;
- u32 expire_time;
-+
-+/*
-+ * per-port SAFC variables
-+ */
-+struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
- u16 reserved0;
- u8 cur_cos_types;
-+ u16 __reserved1;
-+ u8 __reserved0;
- u8 safc_timeout_usec;
+- u8 safc_timeout_usec;
++ u16 reserved;
++ u16 sge_prod;
#elif defined(__LITTLE_ENDIAN)
- u8 safc_timeout_usec;
+- u8 safc_timeout_usec;
- u8 cur_cos_types;
- u16 reserved0;
-+ u8 __reserved0;
-+ u16 __reserved1;
++ u16 sge_prod;
++ u16 reserved;
#endif
- u32 reserved1;
-+ u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
};
-struct demo_struct {
-- u8 con_number[NUM_OF_PROTOCOLS];
--#if defined(__BIG_ENDIAN)
++
++/*
++ * per-port SAFC demo variables
++ */
++struct cmng_flags_per_port {
+ u8 con_number[NUM_OF_PROTOCOLS];
+ #if defined(__BIG_ENDIAN)
- u8 reserved1;
-- u8 fairness_enable;
-- u8 rate_shaping_enable;
+ u8 fairness_enable;
+ u8 rate_shaping_enable;
- u8 cmng_enable;
--#elif defined(__LITTLE_ENDIAN)
++ u8 cmng_protocol_enable;
++ u8 cmng_vn_enable;
+ #elif defined(__LITTLE_ENDIAN)
- u8 cmng_enable;
-- u8 rate_shaping_enable;
-- u8 fairness_enable;
++ u8 cmng_vn_enable;
++ u8 cmng_protocol_enable;
+ u8 rate_shaping_enable;
+ u8 fairness_enable;
- u8 reserved1;
--#endif
--};
+ #endif
+ };
-struct cmng_struct {
- struct rate_shaping_vars rs_vars;
- struct fairness_vars fair_vars;
- struct safc_struct safc_vars;
- struct demo_struct demo_vars;
++
+/*
-+ * Per-port congestion management variables
++ * per-port rate shaping variables
+ */
-+struct cmng_struct_per_port {
-+ struct rate_shaping_vars_per_port rs_vars;
-+ struct fairness_vars_per_port fair_vars;
-+ struct safc_struct_per_port safc_vars;
-+ struct cmng_flags_per_port flags;
++struct rate_shaping_vars_per_port {
++ u32 rs_periodic_timeout;
++ u32 rs_threshold;
};
-struct cos_to_protocol {
- u8 mask[MAX_COS_NUMBER];
+/*
-+ * Protocol-common statistics collected by the Xstorm (per client)
++ * per-port fairness variables
+ */
-+struct xstorm_per_client_stats {
-+ struct regpair total_sent_bytes;
-+ __le32 total_sent_pkts;
-+ __le32 unicast_pkts_sent;
-+ struct regpair unicast_bytes_sent;
-+ struct regpair multicast_bytes_sent;
-+ __le32 multicast_pkts_sent;
-+ __le32 broadcast_pkts_sent;
-+ struct regpair broadcast_bytes_sent;
-+ __le16 stats_counter;
-+ __le16 reserved0;
-+ __le32 reserved1;
++struct fairness_vars_per_port {
++ u32 upper_bound;
++ u32 fair_threshold;
++ u32 fairness_timeout;
};
-@@ -2089,17 +2690,21 @@ struct cos_to_protocol {
- * Common statistics collected by the Xstorm (per port)
+ /*
+- * Common statistics collected by the Xstorm (per port)
++ * per-port SAFC variables
*/
- struct xstorm_common_stats {
-- struct regpair total_sent_bytes;
-- u32 total_sent_pkts;
-- u32 unicast_pkts_sent;
-- struct regpair unicast_bytes_sent;
-- struct regpair multicast_bytes_sent;
-- u32 multicast_pkts_sent;
-- u32 broadcast_pkts_sent;
-- struct regpair broadcast_bytes_sent;
+-struct xstorm_common_stats {
++struct safc_struct_per_port {
++#if defined(__BIG_ENDIAN)
++ u16 __reserved1;
++ u8 __reserved0;
++ u8 safc_timeout_usec;
++#elif defined(__LITTLE_ENDIAN)
++ u8 safc_timeout_usec;
++ u8 __reserved0;
++ u16 __reserved1;
++#endif
++ u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
++};
++
++
++/*
++ * Per-port congestion management variables
++ */
++struct cmng_struct_per_port {
++ struct rate_shaping_vars_per_port rs_vars;
++ struct fairness_vars_per_port fair_vars;
++ struct safc_struct_per_port safc_vars;
++ struct cmng_flags_per_port flags;
++};
++
++
++/*
++ * Protocol-common statistics collected by the Xstorm (per client)
++ */
++struct xstorm_per_client_stats {
+ struct regpair total_sent_bytes;
+ u32 total_sent_pkts;
+ u32 unicast_pkts_sent;
+@@ -2097,9 +2714,31 @@ struct xstorm_common_stats {
+ u32 multicast_pkts_sent;
+ u32 broadcast_pkts_sent;
+ struct regpair broadcast_bytes_sent;
- struct regpair done;
-+ struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
++ u16 stats_counter;
++ u16 reserved0;
++ u32 reserved1;
};
+
+/*
++ * Common statistics collected by the Xstorm (per port)
++ */
++struct xstorm_common_stats {
++ struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
++};
++
++
++/*
+ * Protocol-common statistics collected by the Tstorm (per port)
+ */
+struct tstorm_per_port_stats {
-+ __le32 mac_filter_discard;
-+ __le32 xxoverflow_discard;
-+ __le32 brb_truncate_discard;
-+ __le32 mac_discard;
++ u32 mac_filter_discard;
++ u32 xxoverflow_discard;
++ u32 brb_truncate_discard;
++ u32 mac_discard;
+};
+
+
/*
* Protocol-common statistics collected by the Tstorm (per client)
*/
-@@ -2109,32 +2714,29 @@ struct tstorm_per_client_stats {
- struct regpair rcv_broadcast_bytes;
- struct regpair rcv_multicast_bytes;
- struct regpair rcv_error_bytes;
-- u32 checksum_discard;
-- u32 packets_too_big_discard;
-- u32 total_rcv_pkts;
-- u32 rcv_unicast_pkts;
-- u32 rcv_broadcast_pkts;
-- u32 rcv_multicast_pkts;
-- u32 no_buff_discard;
-- u32 ttl0_discard;
+@@ -2117,24 +2756,21 @@ struct tstorm_per_client_stats {
+ u32 rcv_multicast_pkts;
+ u32 no_buff_discard;
+ u32 ttl0_discard;
- u32 mac_discard;
- u32 reserved;
-+ __le32 checksum_discard;
-+ __le32 packets_too_big_discard;
-+ __le32 total_rcv_pkts;
-+ __le32 rcv_unicast_pkts;
-+ __le32 rcv_broadcast_pkts;
-+ __le32 rcv_multicast_pkts;
-+ __le32 no_buff_discard;
-+ __le32 ttl0_discard;
-+ __le16 stats_counter;
-+ __le16 reserved0;
-+ __le32 reserved1;
++ u16 stats_counter;
++ u16 reserved0;
++ u32 reserved1;
};
/*
@@ -14849,14 +13956,13 @@
*/
struct eth_stats_query {
struct xstorm_common_stats xstorm_common;
-@@ -2143,25 +2745,40 @@ struct eth_stats_query {
+@@ -2143,25 +2779,39 @@ struct eth_stats_query {
/*
+ * per-vnic fairness variables
+ */
+struct fairness_vars_per_vn {
-+ u32 cos_credit_delta[MAX_COS_NUMBER];
+ u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
+ u32 vn_credit_delta;
+ u32 __reserved0;
@@ -14871,15 +13977,14 @@
- u16 patch;
- u8 primary;
- u8 client;
--#elif defined(__LITTLE_ENDIAN)
-- u8 client;
-- u8 primary;
-- u16 patch;
+ u8 engineering;
+ u8 revision;
+ u8 minor;
+ u8 major;
-+#elif defined(__LITTLE_ENDIAN)
+ #elif defined(__LITTLE_ENDIAN)
+- u8 client;
+- u8 primary;
+- u16 patch;
+ u8 major;
+ u8 minor;
+ u8 revision;
@@ -14899,7 +14004,7 @@
};
-@@ -2169,15 +2786,10 @@ struct fw_version {
+@@ -2169,15 +2819,10 @@ struct fw_version {
* FW version stored in first line of pram
*/
struct pram_fw_version {
@@ -14919,7 +14024,7 @@
u8 flags;
#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
-@@ -2185,8 +2797,34 @@ struct pram_fw_version {
+@@ -2185,8 +2830,34 @@ struct pram_fw_version {
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
@@ -14956,35 +14061,21 @@
};
-diff -urpN a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
---- a/drivers/net/bnx2x_init.h 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x_init.h 2009-05-28 01:52:09.000000000 -0600
-@@ -1,6 +1,6 @@
- /* bnx2x_init.h: Broadcom Everest network driver.
- *
-- * Copyright (c) 2007-2008 Broadcom Corporation
-+ * Copyright (c) 2007-2009 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -22,15 +22,19 @@
+diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
+index 370686e..961db49 100644
+--- a/drivers/net/bnx2x_init.h
++++ b/drivers/net/bnx2x_init.h
+@@ -22,7 +22,8 @@
#define INIT_ASIC 0x4
#define INIT_HARDWARE 0x7
-#define STORM_INTMEM_SIZE (0x5800 / 4)
--#define TSTORM_INTMEM_ADDR 0x1a0000
--#define CSTORM_INTMEM_ADDR 0x220000
--#define XSTORM_INTMEM_ADDR 0x2a0000
--#define USTORM_INTMEM_ADDR 0x320000
-+#define TSTORM_INTMEM_ADDR TSEM_REG_FAST_MEMORY
-+#define CSTORM_INTMEM_ADDR CSEM_REG_FAST_MEMORY
-+#define XSTORM_INTMEM_ADDR XSEM_REG_FAST_MEMORY
-+#define USTORM_INTMEM_ADDR USEM_REG_FAST_MEMORY
-+/* RAM0 size in bytes */
-+#define STORM_INTMEM_SIZE_E1 0x5800
-+#define STORM_INTMEM_SIZE_E1H 0x10000
-+#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \
-+ STORM_INTMEM_SIZE_E1) / 4)
++#define STORM_INTMEM_SIZE_E1 (0x5800 / 4)
++#define STORM_INTMEM_SIZE_E1H (0x10000 / 4)
+ #define TSTORM_INTMEM_ADDR 0x1a0000
+ #define CSTORM_INTMEM_ADDR 0x220000
+ #define XSTORM_INTMEM_ADDR 0x2a0000
+@@ -30,7 +31,7 @@
/* Init operation types and structures */
@@ -14993,7 +14084,7 @@
#define OP_RD 0x1 /* read single register */
#define OP_WR 0x2 /* write single register */
#define OP_IW 0x3 /* write single register using mailbox */
-@@ -38,29 +42,59 @@
+@@ -38,29 +39,59 @@
#define OP_SI 0x5 /* copy a string using mailbox */
#define OP_ZR 0x6 /* clear memory */
#define OP_ZP 0x7 /* unzip then copy with DMAE */
@@ -15062,7 +14153,7 @@
#ifdef __LITTLE_ENDIAN
u16 data_off;
u16 data_len;
-@@ -71,8 +105,8 @@ struct op_string_write {
+@@ -71,8 +102,8 @@ struct op_string_write {
};
struct op_zero {
@@ -15073,7 +14164,7 @@
u32 len;
};
-@@ -87,10 +121,6 @@ union init_op {
+@@ -87,10 +118,6 @@ union init_op {
#include "bnx2x_init_values.h"
static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
@@ -15084,7 +14175,7 @@
static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
-@@ -107,9 +137,6 @@ static void bnx2x_init_str_wr(struct bnx
+@@ -107,9 +134,6 @@ static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
}
}
@@ -15094,12 +14185,13 @@
static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
u16 len)
{
-@@ -124,11 +151,116 @@ static void bnx2x_init_ind_wr(struct bnx
+@@ -124,11 +148,117 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
}
}
+static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
+{
++#ifdef USE_DMAE
+ int offset = 0;
+
+ if (bp->dmae_ready) {
@@ -15113,28 +14205,28 @@
+ addr + offset, len);
+ } else
+ bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
++#else
++ bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
++#endif
+}
+
+static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
+{
-+ u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
-+ u32 buf_len32 = buf_len / 4;
-+ int i;
-+
-+ memset(bp->gunzip_buf, fill, buf_len);
-+
-+ for (i = 0; i < len; i += buf_len32) {
-+ u32 cur_len = min(buf_len32, len - i);
-+
-+ bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
++ if ((len * 4) > FW_BUF_SIZE) {
++ BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
++ addr, len*4);
++ return;
+ }
++ memset(bp->gunzip_buf, fill, len * 4);
++
++ bnx2x_write_big_buf(bp, addr, len);
+}
+
+static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
+ u32 len64)
+{
-+ u32 buf_len32 = FW_BUF_SIZE / 4;
-+ u32 len = len64 * 2;
++ u32 buf_len32 = FW_BUF_SIZE/4;
++ u32 len = len64*2;
+ u64 data64 = 0;
+ int i;
+
@@ -15212,15 +14304,12 @@
if (gunzip) {
int rc;
#ifdef __BIG_ENDIAN
-@@ -143,64 +275,62 @@ static void bnx2x_init_wr_wb(struct bnx2
+@@ -143,64 +273,59 @@ static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
#endif
rc = bnx2x_gunzip(bp, (u8 *)data, len);
if (rc) {
- DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc);
+ BNX2X_ERR("gunzip failed ! rc %d\n", rc);
-+#ifdef __BIG_ENDIAN
-+ kfree(temp);
-+#endif
return;
}
len = bp->gunzip_outlen;
@@ -15242,14 +14331,7 @@
}
- while (len > DMAE_LEN32_MAX) {
-+ if (bp->dmae_ready) {
-+ while (len > DMAE_LEN32_WR_MAX) {
-+ bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
-+ addr + offset, DMAE_LEN32_WR_MAX);
-+ offset += DMAE_LEN32_WR_MAX * 4;
-+ len -= DMAE_LEN32_WR_MAX;
-+ }
- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
+- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, DMAE_LEN32_MAX);
- offset += DMAE_LEN32_MAX * 4;
- len -= DMAE_LEN32_MAX;
@@ -15274,7 +14356,14 @@
- memset(bp->gunzip_buf, fill, len * 4);
-
- while (len > DMAE_LEN32_MAX) {
-- bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
++ if (bp->dmae_ready) {
++ while (len > DMAE_LEN32_WR_MAX) {
++ bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
++ addr + offset, DMAE_LEN32_WR_MAX);
++ offset += DMAE_LEN32_WR_MAX * 4;
++ len -= DMAE_LEN32_WR_MAX;
++ }
+ bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
- addr + offset, DMAE_LEN32_MAX);
- offset += DMAE_LEN32_MAX * 4;
- len -= DMAE_LEN32_MAX;
@@ -15311,7 +14400,7 @@
for (i = op_start; i < op_end; i++) {
-@@ -209,7 +339,30 @@ static void bnx2x_init_block(struct bnx2
+@@ -209,7 +334,30 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
op_type = op->str_wr.op;
addr = op->str_wr.offset;
len = op->str_wr.data_len;
@@ -15343,7 +14432,7 @@
switch (op_type) {
case OP_RD:
-@@ -222,7 +375,7 @@ static void bnx2x_init_block(struct bnx2
+@@ -222,7 +370,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
bnx2x_init_str_wr(bp, addr, data, len);
break;
case OP_WB:
@@ -15352,7 +14441,7 @@
break;
case OP_SI:
bnx2x_init_ind_wr(bp, addr, data, len);
-@@ -231,10 +384,21 @@ static void bnx2x_init_block(struct bnx2
+@@ -231,10 +379,21 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
bnx2x_init_fill(bp, addr, 0, op->zero.len);
break;
case OP_ZP:
@@ -15376,7 +14465,7 @@
}
}
}
-@@ -245,7 +409,7 @@ static void bnx2x_init_block(struct bnx2
+@@ -245,7 +404,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
****************************************************************************/
/*
* This code configures the PCI read/write arbiter
@@ -15385,148 +14474,25 @@
* between the virtual queues in the chip.
*
* The values were derived for each PCI max payload and max request size.
-@@ -267,57 +431,57 @@ struct arb_line {
-
- /* derived configuration for each read queue for each max request size */
- static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
-- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
-- {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} },
-- {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} },
-- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
-- {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }
-+/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-+ { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
-+ { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
-+ { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
-+ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
-+/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
-+ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
- };
-
- /* derived configuration for each write queue for each max request size */
- static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
-- {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} },
-- {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
-- {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
-- {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
-- {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} },
-- {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },
-- {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} },
-- {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
-+/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
-+ { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
-+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
-+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
-+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
-+ { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
-+ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
-+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
-+ { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
-+/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
-+ { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
-+ { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
-+ { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
+@@ -315,7 +474,7 @@ static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+ {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
};
-/* register adresses for read queues */
+/* register addresses for read queues */
static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
-- {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
-+/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
PXP2_REG_RQ_BW_RD_UBOUND0},
- {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
- PXP2_REG_PSWRQ_BW_UB1},
-@@ -335,7 +499,7 @@ static const struct arb_line read_arb_ad
- PXP2_REG_PSWRQ_BW_UB7},
- {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
- PXP2_REG_PSWRQ_BW_UB8},
-- {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
-+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
- PXP2_REG_PSWRQ_BW_UB9},
- {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
- PXP2_REG_PSWRQ_BW_UB10},
-@@ -355,7 +519,7 @@ static const struct arb_line read_arb_ad
- PXP2_REG_RQ_BW_RD_UBOUND17},
- {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
- PXP2_REG_RQ_BW_RD_UBOUND18},
-- {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
-+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
- PXP2_REG_RQ_BW_RD_UBOUND19},
- {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
- PXP2_REG_RQ_BW_RD_UBOUND20},
-@@ -375,9 +539,9 @@ static const struct arb_line read_arb_ad
+@@ -375,7 +534,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
PXP2_REG_PSWRQ_BW_UB28}
};
-/* register adresses for wrtie queues */
+/* register addresses for write queues */
static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
-- {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
-+/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
PXP2_REG_PSWRQ_BW_UB1},
- {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
- PXP2_REG_PSWRQ_BW_UB2},
-@@ -395,7 +559,7 @@ static const struct arb_line write_arb_a
- PXP2_REG_PSWRQ_BW_UB10},
- {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
- PXP2_REG_PSWRQ_BW_UB11},
-- {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
-+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
- PXP2_REG_PSWRQ_BW_UB28},
- {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
- PXP2_REG_RQ_BW_WR_UBOUND29},
-@@ -405,14 +569,20 @@ static const struct arb_line write_arb_a
+@@ -405,14 +564,20 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
static void bnx2x_init_pxp(struct bnx2x *bp)
{
@@ -15551,7 +14517,7 @@
if (r_order > MAX_RD_ORD) {
DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
-@@ -424,6 +594,10 @@ static void bnx2x_init_pxp(struct bnx2x
+@@ -424,6 +589,10 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
w_order, MAX_WR_ORD);
w_order = MAX_WR_ORD;
}
@@ -15562,30 +14528,29 @@
DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
for (i = 0; i < NUM_RD_Q-1; i++) {
-@@ -481,7 +655,21 @@ static void bnx2x_init_pxp(struct bnx2x
+@@ -481,7 +650,20 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
- REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16);
+
+ if (CHIP_IS_E1H(bp)) {
-+ val = ((w_order == 0) ? 2 : 3);
-+ REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
-+ REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
++ REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1);
++ REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1);
+ REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
-+ REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
++ REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1);
+ }
}
-@@ -564,6 +752,72 @@ static u8 calc_crc8(u32 data, u8 crc)
+@@ -564,6 +746,72 @@ static u8 calc_crc8(u32 data, u8 crc)
return crc_res;
}
@@ -15658,10 +14623,12 @@
#endif /* BNX2X_INIT_H */
-diff -urpN a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
---- a/drivers/net/bnx2x_link.c 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_link.c 2009-05-28 01:52:09.000000000 -0600
-@@ -0,0 +1,5699 @@
+diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
+new file mode 100644
+index 0000000..ecfda9e
+--- /dev/null
++++ b/drivers/net/bnx2x_link.c
+@@ -0,0 +1,4907 @@
+/* Copyright 2008-2009 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
@@ -15687,9 +14654,14 @@
+#include <linux/mutex.h>
+#include <linux/version.h>
+
++#include "bnx2x_reg.h"
++#include "bnx2x_fw_defs.h"
++#include "bnx2x_hsi.h"
++#include "bnx2x_link.h"
+#include "bnx2x.h"
+
+/********************************************************/
++#define SUPPORT_CL73 0 /* Currently no */
+#define ETH_HLEN 14
+#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
+#define ETH_MIN_PACKET_SIZE 60
@@ -15799,26 +14771,6 @@
+#define PHY_SGMII_FLAG 0x2
+#define PHY_SERDES_FLAG 0x4
+
-+/* */
-+#define SFP_EEPROM_CON_TYPE_ADDR 0x2
-+ #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
-+ #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
-+
-+#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
-+ #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
-+ #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
-+#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
-+#define SFP_EEPROM_VENDOR_NAME_SIZE 16
-+#define SFP_EEPROM_OPTIONS_ADDR 0x40
-+ #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
-+#define SFP_EEPROM_OPTIONS_SIZE 2
-+
-+#define SFP_MODULE_TYPE_UNKNOWN 0x0
-+#define SFP_MODULE_TYPE_LC 0x1
-+#define SFP_MODULE_TYPE_ACTIVE_COPPER_CABLE 0x2
-+#define SFP_MODULE_TYPE_PASSIVE_COPPER_CABLE 0x3
-+
-+#define SFP_LIMITING_MODE_VALUE 0x0044
+/**********************************************************/
+/* INTERFACE */
+/**********************************************************/
@@ -15834,34 +14786,13 @@
+ (_bank + (_addr & 0xf)), \
+ _val)
+
-+static void bnx2x_set_serdes_access(struct link_params *params)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
-+ /* Set Clause 22 */
-+ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
-+ REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
-+ udelay(500);
-+ REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
-+ udelay(500);
-+ /* Set Clause 45 */
-+ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
-+}
-+static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
++static void bnx2x_set_phy_mdio(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
-+ if (phy_flags & PHY_XGXS_FLAG) {
-+ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
-+ params->port*0x18, 0);
-+ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
-+ DEFAULT_PHY_DEV_ADDR);
-+ } else {
-+ bnx2x_set_serdes_access(params);
-+
-+ REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
-+ params->port*0x10,
-+ DEFAULT_PHY_DEV_ADDR);
-+ }
++ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
++ params->port*0x18, 0);
++ REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
++ DEFAULT_PHY_DEV_ADDR);
+}
+
+static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
@@ -15978,10 +14909,8 @@
+ port*4, 0);
+ }
+
-+ bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
-+ EMAC_RX_MODE_RESET);
-+ bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
-+ EMAC_TX_MODE_RESET);
++ /* enable emac */
++ REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
+
+ if (CHIP_REV_IS_SLOW(bp)) {
+ /* config GMII mode */
@@ -16201,7 +15130,7 @@
+ udelay(500);
+ REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
+ val);
-+ bnx2x_set_phy_mdio(params, phy_flags);
++ bnx2x_set_phy_mdio(params);
+}
+
+void bnx2x_link_status_update(struct link_params *params,
@@ -16452,17 +15381,12 @@
+ return 0;
+}
+
-+static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
++static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
+{
+ u32 emac_base;
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ /* All MDC/MDIO is directed through single EMAC */
-+ if (REG_RD(bp, NIG_REG_PORT_SWAP))
-+ emac_base = GRCBASE_EMAC0;
-+ else
-+ emac_base = GRCBASE_EMAC1;
++ emac_base = GRCBASE_EMAC0;
+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
@@ -16480,12 +15404,11 @@
+{
+ u32 tmp, saved_mode;
+ u8 i, rc = 0;
-+ u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
++ u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
+
+ /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
+ * (a value of 49==0x31) and make sure that the AUTO poll is off
+ */
-+
+ saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+ tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
+ EMAC_MDIO_MODE_CLOCK_CNT);
@@ -16550,11 +15473,10 @@
+ u16 i;
+ u8 rc = 0;
+
-+ u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
++ u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
+ /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
+ * (a value of 49==0x31) and make sure that the AUTO poll is off
+ */
-+
+ saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+ val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
+ EMAC_MDIO_MODE_CLOCK_CNT));
@@ -16677,8 +15599,6 @@
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+
-+ bnx2x_set_serdes_access(params);
-+
+ /* wait for the reset to self clear */
+ for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
+ udelay(5);
@@ -16868,9 +15788,62 @@
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ reg_val);
+
-+ /* CL73 Autoneg Disabled */
-+ reg_val = 0;
++ /* Enable Clause 73 Aneg */
++ if ((vars->line_speed == SPEED_AUTO_NEG) &&
++ (SUPPORT_CL73)) {
++ /* Enable BAM Station Manager */
++
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_USERB0,
++ MDIO_CL73_USERB0_CL73_BAM_CTRL1,
++ (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
++ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
++ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
++
++ /* Merge CL73 and CL37 aneg resolution */
++ CL45_RD_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_USERB0,
++ MDIO_CL73_USERB0_CL73_BAM_CTRL3,
++ ®_val);
++
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_USERB0,
++ MDIO_CL73_USERB0_CL73_BAM_CTRL3,
++ (reg_val |
++ MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
++
++ /* Set the CL73 AN speed */
++
++ CL45_RD_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_IEEEB1,
++ MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
++ /* In the SerDes we support only the 1G.
++ In the XGXS we support the 10G KX4
++ but we currently do not support the KR */
++ if (vars->phy_flags & PHY_XGXS_FLAG) {
++ DP(NETIF_MSG_LINK, "XGXS\n");
++ /* 10G KX4 */
++ reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
++ } else {
++ DP(NETIF_MSG_LINK, "SerDes\n");
++ /* 1000M KX */
++ reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
++ }
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_IEEEB1,
++ MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
+
++ /* CL73 Autoneg Enabled */
++ reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
++ } else {
++ /* CL73 Autoneg Disabled */
++ reg_val = 0;
++ }
+ CL45_WR_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_CL73_IEEEB0,
@@ -17003,25 +15976,44 @@
+static void bnx2x_restart_autoneg(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
-+ u16 mii_control;
+ DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
-+ /* Enable and restart BAM/CL37 aneg */
++ if (SUPPORT_CL73) {
++ /* enable and restart clause 73 aneg */
++ u16 an_ctrl;
+
-+ CL45_RD_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ MDIO_REG_BANK_COMBO_IEEE0,
-+ MDIO_COMBO_IEEE0_MII_CONTROL,
-+ &mii_control);
-+ DP(NETIF_MSG_LINK,
-+ "bnx2x_restart_autoneg mii_control before = 0x%x\n",
-+ mii_control);
-+ CL45_WR_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ MDIO_REG_BANK_COMBO_IEEE0,
-+ MDIO_COMBO_IEEE0_MII_CONTROL,
-+ (mii_control |
-+ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
-+ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
++ CL45_RD_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_IEEEB0,
++ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
++ &an_ctrl);
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_CL73_IEEEB0,
++ MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
++ (an_ctrl |
++ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
++ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
++
++ } else {
++ /* Enable and restart BAM/CL37 aneg */
++ u16 mii_control;
++
++ CL45_RD_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_COMBO_IEEE0,
++ MDIO_COMBO_IEEE0_MII_CONTROL,
++ &mii_control);
++ DP(NETIF_MSG_LINK,
++ "bnx2x_restart_autoneg mii_control before = 0x%x\n",
++ mii_control);
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_COMBO_IEEE0,
++ MDIO_COMBO_IEEE0_MII_CONTROL,
++ (mii_control |
++ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
++ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
++ }
+}
+
+static void bnx2x_initialize_sgmii_process(struct link_params *params,
@@ -17366,11 +16358,7 @@
+ ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
+ (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
-+ (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
-+ (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481))) {
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) {
+ vars->autoneg = AUTO_NEG_ENABLED;
+
+ if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -17414,44 +16402,38 @@
+ return rc;
+}
+
-+static void bnx2x_set_gmii_tx_driver(struct link_params *params)
++static void bnx2x_set_sgmii_tx_driver(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
+ u16 lp_up2;
+ u16 tx_driver;
-+ u16 bank;
+
+ /* read precomp */
++
+ CL45_RD_OVER_CL22(bp, params->port,
+ params->phy_addr,
+ MDIO_REG_BANK_OVER_1G,
+ MDIO_OVER_1G_LP_UP2, &lp_up2);
+
++ CL45_RD_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_TX0,
++ MDIO_TX0_TX_DRIVER, &tx_driver);
++
+ /* bits [10:7] at lp_up2, positioned at [15:12] */
+ lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
+ MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
+ MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
+
-+ if (lp_up2 == 0)
-+ return;
-+
-+ for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
-+ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
-+ CL45_RD_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ bank,
-+ MDIO_TX0_TX_DRIVER, &tx_driver);
-+
++ if ((lp_up2 != 0) &&
++ (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
+ /* replace tx_driver bits [15:12] */
-+ if (lp_up2 !=
-+ (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
-+ tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
-+ tx_driver |= lp_up2;
-+ CL45_WR_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ bank,
-+ MDIO_TX0_TX_DRIVER, tx_driver);
-+ }
++ tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
++ tx_driver |= lp_up2;
++ CL45_WR_OVER_CL22(bp, params->port,
++ params->phy_addr,
++ MDIO_REG_BANK_TX0,
++ MDIO_TX0_TX_DRIVER, tx_driver);
+ }
+}
+
@@ -17552,25 +16534,6 @@
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL, 0xa040);
+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+
-+ /* Restore normal power mode*/
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
-+ params->port);
-+
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
-+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
-+ params->port);
-+
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_CTRL,
-+ 1<<15);
-+
-+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+ /* Unset Low Power Mode and SW reset */
+ /* Restore normal power mode*/
@@ -17588,6 +16551,9 @@
+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ {
++ u16 emac_base;
++ emac_base = (params->port) ? GRCBASE_EMAC0 :
++ GRCBASE_EMAC1;
+
+ /* Restore normal power mode*/
+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
@@ -17615,23 +16581,6 @@
+
+ break;
+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-+
-+ /* Restore normal power mode*/
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-+ MISC_REGISTERS_GPIO_OUTPUT_HIGH,
-+ params->port);
-+
-+ /* HW reset */
-+ bnx2x_hw_reset(bp, params->port);
-+
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_CTRL,
-+ 1<<15);
-+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+ DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
+ break;
@@ -17663,31 +16612,6 @@
+ }
+}
+
-+
-+static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
-+ u32 shmem_base, u32 spirom_ver)
-+{
-+ DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
-+ (u16)(spirom_ver>>16), (u16)spirom_ver);
-+ REG_WR(bp, shmem_base +
-+ offsetof(struct shmem_region,
-+ port_mb[port].ext_phy_fw_version),
-+ spirom_ver);
-+}
-+
-+static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
-+ u32 ext_phy_type, u8 ext_phy_addr,
-+ u32 shmem_base)
-+{
-+ u16 fw_ver1, fw_ver2;
-+ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER1, &fw_ver1);
-+ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER2, &fw_ver2);
-+ bnx2x_save_spirom_version(bp, port, shmem_base,
-+ (u32)(fw_ver1<<16 | fw_ver2));
-+}
-+
+static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
@@ -17696,6 +16620,7 @@
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
++ u16 fw_ver1, fw_ver2;
+
+ /* Need to wait 200ms after reset */
+ msleep(200);
@@ -17731,10 +16656,14 @@
+ /* Wait 100ms */
+ msleep(100);
+
-+ bnx2x_save_bcm_spirom_ver(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ params->shmem_base);
++ /* Print the PHY FW version */
++ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER1, &fw_ver1);
++ bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER2, &fw_ver2);
++ DP(NETIF_MSG_LINK, "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
+}
+
+static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
@@ -17749,635 +16678,156 @@
+
+ /* Read 8073 HW revision*/
+ bnx2x_cl45_read(bp, params->port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_CHIP_REV, &val);
-+
-+ if (val != 1) {
-+ /* No need to workaround in 8073 A1 */
-+ return 0;
-+ }
-+
-+ bnx2x_cl45_read(bp, params->port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER2, &val);
-+
-+ /* SNR should be applied only for version 0x102 */
-+ if (val != 0x102)
-+ return 0;
-+
-+ return 1;
-+}
-+
-+static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ u16 val, cnt, cnt1 ;
-+
-+ bnx2x_cl45_read(bp, params->port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_CHIP_REV, &val);
-+
-+ if (val > 0) {
-+ /* No need to workaround in 8073 A1 */
-+ return 0;
-+ }
-+ /* XAUI workaround in 8073 A0: */
-+
-+ /* After loading the boot ROM and restarting Autoneg,
-+ poll Dev1, Reg $C820: */
-+
-+ for (cnt = 0; cnt < 1000; cnt++) {
-+ bnx2x_cl45_read(bp, params->port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
-+ &val);
-+ /* If bit [14] = 0 or bit [13] = 0, continue on with
-+ system initialization (XAUI work-around not required,
-+ as these bits indicate 2.5G or 1G link up). */
-+ if (!(val & (1<<14)) || !(val & (1<<13))) {
-+ DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
-+ return 0;
-+ } else if (!(val & (1<<15))) {
-+ DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
-+ /* If bit 15 is 0, then poll Dev1, Reg $C841 until
-+ it's MSB (bit 15) goes to 1 (indicating that the
-+ XAUI workaround has completed),
-+ then continue on with system initialization.*/
-+ for (cnt1 = 0; cnt1 < 1000; cnt1++) {
-+ bnx2x_cl45_read(bp, params->port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_XAUI_WA, &val);
-+ if (val & (1<<15)) {
-+ DP(NETIF_MSG_LINK,
-+ "XAUI workaround has completed\n");
-+ return 0;
-+ }
-+ msleep(3);
-+ }
-+ break;
-+ }
-+ msleep(3);
-+ }
-+ DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
-+ return -EINVAL;
-+
-+}
-+
-+static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
-+ u8 ext_phy_addr, u32 shmem_base)
-+{
-+ /* Boot port from external ROM */
-+ /* EDC grst */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ 0x0001);
-+
-+ /* ucode reboot and rst */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ 0x008c);
-+
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
-+
-+ /* Reset internal microprocessor */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
-+
-+ /* Release srst bit */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
-+
-+ /* wait for 100ms for code download via SPI port */
-+ msleep(100);
-+
-+ /* Clear ser_boot_ctl bit */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
-+
-+ bnx2x_save_bcm_spirom_ver(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
-+ ext_phy_addr,
-+ shmem_base);
-+}
-+
-+static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u8 port = params->port;
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
-+
-+ /* Need to wait 100ms after reset */
-+ msleep(100);
-+
-+ /* Set serial boot control for external load */
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
-+
-+ /* Micro controller re-boot */
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
-+
-+ /* Set soft reset */
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
-+
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL2,
-+ 0x73A0);
-+
-+ /* Clear soft reset.
-+ Will automatically reset micro-controller re-boot */
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL,
-+ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
-+
-+ /* wait for 150ms for microcode load */
-+ msleep(150);
-+
-+ /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
-+ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
-+
-+ msleep(200);
-+ bnx2x_save_bcm_spirom_ver(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ params->shmem_base);
-+}
-+
-+static void bnx2x_bcm8726_set_transmitter(struct bnx2x *bp, u8 port,
-+ u8 ext_phy_addr, u8 tx_en)
-+{
-+ u16 val;
-+ DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
-+ tx_en, port);
-+ /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
-+ bnx2x_cl45_read(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_PHY_IDENTIFIER,
-+ &val);
-+
-+ if (tx_en)
-+ val &= ~(1<<15);
-+ else
-+ val |= (1<<15);
-+
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_PHY_IDENTIFIER,
-+ val);
-+}
-+
-+
-+static u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
-+ u8 byte_cnt, u8 *o_buf) {
-+ struct bnx2x *bp = params->bp;
-+ u16 val, i;
-+ u8 port = params->port;
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
-+ if (byte_cnt > 16) {
-+ DP(NETIF_MSG_LINK, "Reading from eeprom is"
-+ " is limited to 0xf\n");
-+ return -EINVAL;
-+ }
-+ /* Set the read command byte count */
-+ bnx2x_cl45_write(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT,
-+ (byte_cnt | 0xa000));
-+
-+ /* Set the read command address */
-+ bnx2x_cl45_write(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR,
-+ addr);
-+
-+ /* Activate read command */
-+ bnx2x_cl45_write(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_CTRL,
-+ 0x2c0f);
-+
-+ /* Wait up to 500us for command complete status */
-+ for (i = 0; i < 100; i++) {
-+ bnx2x_cl45_read(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_CTRL, &val);
-+ if ((val & MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK) ==
-+ MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE)
-+ break;
-+ udelay(5);
-+ }
-+
-+ if ((val & MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK) !=
-+ MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE) {
-+ DP(NETIF_MSG_LINK,
-+ "Got bad status 0x%x when reading from SFP+ EEPROM\n",
-+ (val & MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK));
-+ return -EINVAL;
-+ }
-+
-+ /* Read the buffer */
-+ for (i = 0; i < byte_cnt; i++) {
-+ bnx2x_cl45_read(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
-+ o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
-+ }
-+
-+ for (i = 0; i < 100; i++) {
-+ bnx2x_cl45_read(bp, port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TWO_WIRE_CTRL, &val);
-+ if ((val & MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK) ==
-+ MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE)
-+ return 0;;
-+ msleep(1);
-+ }
-+ return -EINVAL;
-+}
-+
-+
-+static u8 bnx2x_get_sfp_module_type(struct link_params *params,
-+ u8 *module_type)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u8 val;
-+ *module_type = SFP_MODULE_TYPE_UNKNOWN;
-+
-+ /* First check for copper cable */
-+ if (bnx2x_read_sfp_module_eeprom(params,
-+ SFP_EEPROM_CON_TYPE_ADDR,
-+ 1,
-+ &val) != 0) {
-+ DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM");
-+ return -EINVAL;
-+ }
-+
-+ switch (val) {
-+ case SFP_EEPROM_CON_TYPE_VAL_COPPER:
-+ {
-+ u8 copper_module_type;
-+ /* Check if its active cable( includes SFP+ module)
-+ of passive cable*/
-+ if (bnx2x_read_sfp_module_eeprom(params,
-+ SFP_EEPROM_FC_TX_TECH_ADDR,
-+ 1,
-+ &copper_module_type) !=
-+ 0) {
-+ DP(NETIF_MSG_LINK,
-+ "Failed to read copper-cable-type"
-+ " from SFP+ EEPROM\n");
-+ return -EINVAL;
-+ }
-+
-+ if (copper_module_type &
-+ SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
-+ DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
-+ *module_type = SFP_MODULE_TYPE_ACTIVE_COPPER_CABLE;
-+ } else if (copper_module_type &
-+ SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
-+ DP(NETIF_MSG_LINK, "Passive Copper"
-+ " cable detected\n");
-+ *module_type =
-+ SFP_MODULE_TYPE_PASSIVE_COPPER_CABLE;
-+ } else {
-+ DP(NETIF_MSG_LINK, "Unknown copper-cable-"
-+ "type 0x%x !!!\n", copper_module_type);
-+ return -EINVAL;
-+ }
-+ break;
-+ }
-+ case SFP_EEPROM_CON_TYPE_VAL_LC:
-+ DP(NETIF_MSG_LINK, "Optic module detected\n");
-+ *module_type = SFP_MODULE_TYPE_LC;
-+ break;
-+
-+ default:
-+ DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
-+ val);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+
-+/* This function read the relevant field from the module ( SFP+ ),
-+ and verify it is compliant with this board */
-+static u8 bnx2x_verify_sfp_module(struct link_params *params,
-+ u8 module_type)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u8 *str_p, *tmp_buf;
-+ u16 i;
-+
-+#define COMPLIANCE_STR_CNT 6
-+ u8 *compliance_str[] = {"Broadcom", "JDSU", "Molex Inc", "PICOLIGHT",
-+ "FINISAR CORP. ", "Amphenol"};
-+ u8 buf[SFP_EEPROM_VENDOR_NAME_SIZE];
-+ /* Passive Copper cables are allowed to participate,
-+ since the module is hardwired to the copper cable */
-+
-+ if (!(params->feature_config_flags &
-+ FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED)) {
-+ DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
-+ return 0;
-+ }
-+
-+ if (module_type != SFP_MODULE_TYPE_LC) {
-+ DP(NETIF_MSG_LINK, "No need to verify copper cable\n");
-+ return 0;
-+ }
-+
-+ /* In case of non copper cable or Active copper cable,
-+ verify that the SFP+ module is compliant with this board*/
-+ if (bnx2x_read_sfp_module_eeprom(params,
-+ SFP_EEPROM_VENDOR_NAME_ADDR,
-+ SFP_EEPROM_VENDOR_NAME_SIZE,
-+ buf) != 0) {
-+ DP(NETIF_MSG_LINK, "Failed to read Vendor-Name from"
-+ " module EEPROM\n");
-+ return -EINVAL;
-+ }
-+ for (i = 0; i < COMPLIANCE_STR_CNT; i++) {
-+ str_p = compliance_str[i];
-+ tmp_buf = buf;
-+ while (*str_p) {
-+ if ((u8)(*tmp_buf) != (u8)(*str_p))
-+ break;
-+ str_p++;
-+ tmp_buf++;
-+ }
-+
-+ if (!(*str_p)) {
-+ DP(NETIF_MSG_LINK, "SFP+ Module verified, "
-+ "index=%x\n", i);
-+ return 0;
-+ }
-+ }
-+ DP(NETIF_MSG_LINK, "Incompliant SFP+ module. Disable module !!!\n");
-+ return -EINVAL;
-+}
-+
-+
-+static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
-+ u8 module_type)
-+{
-+ struct bnx2x *bp = params->bp;
-+ u8 port = params->port;
-+ u8 options[SFP_EEPROM_OPTIONS_SIZE];
-+ u8 limiting_mode;
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ u16 cur_limiting_mode;
-+ if (bnx2x_read_sfp_module_eeprom(params,
-+ SFP_EEPROM_OPTIONS_ADDR,
-+ SFP_EEPROM_OPTIONS_SIZE,
-+ options) != 0) {
-+ DP(NETIF_MSG_LINK, "Failed to read Option field from"
-+ " module EEPROM\n");
-+ return -EINVAL;
-+ }
-+ limiting_mode = !(options[0] &
-+ SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK);
-+
-+ bnx2x_cl45_read(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER2,
-+ &cur_limiting_mode);
-+ DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
-+ cur_limiting_mode);
-+
-+ if (limiting_mode &&
-+ (module_type != SFP_MODULE_TYPE_PASSIVE_COPPER_CABLE)) {
-+ DP(NETIF_MSG_LINK,
-+ "Module options = 0x%x.Setting LIMITING MODE\n",
-+ options[0]);
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER2,
-+ SFP_LIMITING_MODE_VALUE);
-+ } else { /* LRM mode ( default )*/
-+
-+ DP(NETIF_MSG_LINK, "Module options = 0x%x.Setting LRM MODE\n",
-+ options[0]);
-+
-+ /* Changing to LRM mode takes quite few seconds.
-+ So do it only if current mode is limiting
-+ ( default is LRM )*/
-+ if (cur_limiting_mode != SFP_LIMITING_MODE_VALUE)
-+ return 0;
-+
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LRM_MODE,
-+ 0);
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER2,
-+ 0x128);
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_MISC_CTRL0,
-+ 0x4008);
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LRM_MODE,
-+ 0xaaaa);
-+ }
-+ return 0;
-+}
-+
-+static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
-+{
-+ u8 val;
-+ struct bnx2x *bp = params->bp;
-+ u16 timeout;
-+ /* Initialization time after hot-plug may take up to 300ms for some
-+ phys type ( e.g. JDSU ) */
-+ for (timeout = 0; timeout < 60; timeout++) {
-+ if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
-+ == 0) {
-+ DP(NETIF_MSG_LINK, "SFP+ module initialization "
-+ "took %d ms\n", timeout * 5);
-+ return 0;
-+ }
-+ msleep(5);
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ 0xc801, &val);
++
++ if (val != 1) {
++ /* No need to workaround in 8073 A1 */
++ return 0;
+ }
-+ return -EINVAL;
++
++ bnx2x_cl45_read(bp, params->port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER2, &val);
++
++ /* SNR should be applied only for version 0x102 */
++ if (val != 0x102)
++ return 0;
++
++ return 1;
+}
+
-+static u8 bnx2x_sfp_module_detection(struct link_params *params)
++static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
+{
+ struct bnx2x *bp = params->bp;
-+ u8 module_type;
+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
++ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
++ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
++ u16 val, cnt, cnt1 ;
++
++ bnx2x_cl45_read(bp, params->port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ 0xc801, &val);
+
-+ if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
-+ DP(NETIF_MSG_LINK, "Module detection is not required "
-+ "for this phy\n");
++ if (val > 0) {
++ /* No need to workaround in 8073 A1 */
+ return 0;
+ }
++ /* XAUI workaround in 8073 A0: */
+
-+ DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
-+ params->port);
++ /* After loading the boot ROM and restarting Autoneg,
++ poll Dev1, Reg $C820: */
+
-+ if (bnx2x_get_sfp_module_type(params,
-+ &module_type) != 0) {
-+ DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
-+ if (!(params->feature_config_flags &
-+ FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED)) {
-+ /* In case module detection is disabled, it trys to
-+ link up. The issue that can happen here is LRM /
-+ LIMITING mode which set according to the module-type*/
-+ DP(NETIF_MSG_LINK, "Unable to read module-type."
-+ "Probably due to Bit Stretching."
-+ " Proceeding...\n");
-+ } else {
-+ return -EINVAL;
++ for (cnt = 0; cnt < 1000; cnt++) {
++ bnx2x_cl45_read(bp, params->port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ 0xc820, &val);
++ /* If bit [14] = 0 or bit [13] = 0, continue on with
++ system initialization (XAUI work-around not required,
++ as these bits indicate 2.5G or 1G link up). */
++ if (!(val & (1<<14)) || !(val & (1<<13))) {
++ DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
++ return 0;
++ } else if (!(val & (1<<15))) {
++ DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
++ /* If bit 15 is 0, then poll Dev1, Reg $C841 until
++ it's MSB (bit 15) goes to 1 (indicating that the
++ XAUI workaround has completed),
++ then continue on with system initialization.*/
++ for (cnt1 = 0; cnt1 < 1000; cnt1++) {
++ bnx2x_cl45_read(bp, params->port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ 0xc841, &val);
++ if (val & (1<<15)) {
++ DP(NETIF_MSG_LINK,
++ "XAUI workaround has completed\n");
++ return 0;
++ }
++ msleep(3);
++ }
++ break;
+ }
-+ } else if (bnx2x_verify_sfp_module(params, module_type) !=
-+ 0) {
-+ /* check SFP+ module compatibility */
-+ DP(NETIF_MSG_LINK, "Module verification failed!!\n");
-+ /* Turn on fault module-detected led */
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
-+ MISC_REGISTERS_GPIO_HIGH,
-+ params->port);
-+ return -EINVAL;
++ msleep(3);
+ }
++ DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
++ return -EINVAL;
+
-+ /* Turn off fault module-detected led */
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
-+ MISC_REGISTERS_GPIO_LOW,
-+ params->port);
-+
-+ /* Check and set limiting mode / LRM mode */
-+ bnx2x_bcm8726_set_limiting_mode(params, module_type);
-+
-+ /* Enable transmit for this module */
-+ bnx2x_bcm8726_set_transmitter(bp, params->port,
-+ ext_phy_addr, 1);
-+ return 0;
+}
+
-+void bnx2x_handle_module_detect_int(struct link_params *params)
++static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
++ u8 ext_phy_addr)
+{
-+ struct bnx2x *bp = params->bp;
-+ u32 gpio_val;
-+ u8 port = params->port;
-+ /* Set valid module led off */
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
-+ MISC_REGISTERS_GPIO_HIGH,
-+ params->port);
++ u16 fw_ver1, fw_ver2;
++ /* Boot port from external ROM */
++ /* EDC grst */
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_GEN_CTRL,
++ 0x0001);
++
++ /* ucode reboot and rst */
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_GEN_CTRL,
++ 0x008c);
++
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
-+ /* Get current gpio val refelecting module plugged in / out*/
-+ gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
++ /* Reset internal microprocessor */
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_GEN_CTRL,
++ MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+
-+ /* Call the handling function in case module is detected */
-+ if (gpio_val == 0) {
++ /* Release srst bit */
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_GEN_CTRL,
++ MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
-+ bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
-+ MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
-+ port);
++ /* wait for 100ms for code download via SPI port */
++ msleep(100);
++
++ /* Clear ser_boot_ctl bit */
++ bnx2x_cl45_write(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_MISC_CTRL1, 0x0000);
++
++ bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER1, &fw_ver1);
++ bnx2x_cl45_read(bp, port,
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER2, &fw_ver2);
++ DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
+
-+ if (bnx2x_wait_for_sfp_module_initialized(params)
-+ == 0)
-+ bnx2x_sfp_module_detection(params);
-+ else
-+ DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
-+ } else {
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
-+ MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
-+ port);
-+ /* Module was plugged out. */
-+ /* Disable transmit for this module */
-+ bnx2x_bcm8726_set_transmitter(bp, params->port,
-+ ext_phy_addr, 0);
-+ }
+}
+
+static void bnx2x_bcm807x_force_10G(struct link_params *params)
@@ -18421,7 +16871,7 @@
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_CHIP_REV, &val);
++ 0xc801, &val);
+
+ if (val == 0) {
+ /* Mustn't set low power mode in 8073 A0 */
@@ -18559,40 +17009,31 @@
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_ADV_PAUSE, val);
+}
-+static void bnx2x_set_preemphasis(struct link_params *params)
-+{
-+ u16 bank, i = 0;
-+ struct bnx2x *bp = params->bp;
-+
-+ for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
-+ bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
-+ CL45_WR_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ bank,
-+ MDIO_RX0_RX_EQ_BOOST,
-+ params->xgxs_config_rx[i]);
-+ }
+
-+ for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
-+ bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
-+ CL45_WR_OVER_CL22(bp, params->port,
-+ params->phy_addr,
-+ bank,
-+ MDIO_TX0_TX_DRIVER,
-+ params->xgxs_config_tx[i]);
-+ }
-+}
+
+static void bnx2x_init_internal_phy(struct link_params *params,
+ struct link_vars *vars)
+{
+ struct bnx2x *bp = params->bp;
++ u8 port = params->port;
+ if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
-+ if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
-+ (params->feature_config_flags &
-+ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
-+ bnx2x_set_preemphasis(params);
++ u16 bank, rx_eq;
++
++ rx_eq = ((params->serdes_config &
++ PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
++ PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
++
++ DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
++ for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
++ bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
++ CL45_WR_OVER_CL22(bp, port,
++ params->phy_addr,
++ bank ,
++ MDIO_RX0_RX_EQ_BOOST,
++ ((rx_eq &
++ MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
++ MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
++ }
+
+ /* forced speed requested? */
+ if (vars->line_speed != SPEED_AUTO_NEG) {
@@ -18697,53 +17138,12 @@
+ ext_phy_addr,
+ MDIO_WIS_DEVAD,
+ MDIO_WIS_REG_LASI_CNTL, 0x1);
-+
-+ /* BCM8705 doesn't have microcode, hence the 0 */
-+ bnx2x_save_spirom_version(bp, params->port,
-+ params->shmem_base, 0);
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
-+ /* Wait until fw is loaded */
-+ for (cnt = 0; cnt < 100; cnt++) {
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_ROM_VER1, &val);
-+ if (val)
-+ break;
-+ msleep(10);
-+ }
-+ DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
-+ "after %d ms\n", cnt);
-+ if ((params->feature_config_flags &
-+ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
-+ u8 i;
-+ u16 reg;
-+ for (i = 0; i < 4; i++) {
-+ reg = MDIO_XS_8706_REG_BANK_RX0 +
-+ i*(MDIO_XS_8706_REG_BANK_RX1 -
-+ MDIO_XS_8706_REG_BANK_RX0);
-+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_XS_DEVAD,
-+ reg, &val);
-+ /* Clear first 3 bits of the control */
-+ val &= ~0x7;
-+ /* Set control bits according to
-+ configuation */
-+ val |= (params->xgxs_config_rx[i] &
-+ 0x7);
-+ DP(NETIF_MSG_LINK, "Setting RX"
-+ "Equalizer to BCM8706 reg 0x%x"
-+ " <-- val 0x%x\n", reg, val);
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_XS_DEVAD,
-+ reg, val);
-+ }
-+ }
++ DP(NETIF_MSG_LINK, "XGXS 8706\n");
++
++ msleep(10);
+ /* Force speed */
+ /* First enable LASI */
+ bnx2x_cl45_write(bp, params->port,
@@ -18810,95 +17210,9 @@
+ 0x1200);
+
+ }
-+ bnx2x_save_bcm_spirom_ver(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ params->shmem_base);
-+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
-+ bnx2x_bcm8726_external_rom_boot(params);
-+
-+ /* Need to call module detected on initialization since
-+ the module detection triggered by actual module
-+ insertion might occur before driver is loaded, and when
-+ driver is loaded, it reset all registers, including the
-+ transmitter */
-+ bnx2x_sfp_module_detection(params);
-+ if (params->req_line_speed == SPEED_1000) {
-+ DP(NETIF_MSG_LINK, "Setting 1G force\n");
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_CTRL, 0x40);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_10G_CTRL2, 0xD);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LASI_CTRL, 0x5);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_RX_ALARM_CTRL,
-+ 0x400);
-+ } else if ((params->req_line_speed ==
-+ SPEED_AUTO_NEG) &&
-+ ((params->speed_cap_mask &
-+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
-+ DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_AN_DEVAD,
-+ MDIO_AN_REG_ADV, 0x20);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CL37_CL73, 0x040c);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CL37_FC_LD, 0x0020);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CL37_AN, 0x1000);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CTRL, 0x1200);
-+
-+ /* Enable RX-ALARM control to receive
-+ interrupt for 1G speed change */
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LASI_CTRL, 0x4);
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_RX_ALARM_CTRL,
-+ 0x400);
-+
-+ } else { /* Default 10G. Set only LASI control */
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LASI_CTRL, 1);
-+ }
-+
-+ /* Set TX PreEmphasis if needed */
-+ if ((params->feature_config_flags &
-+ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
-+ DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
-+ "TX_CTRL2 0x%x\n",
-+ params->xgxs_config_tx[0],
-+ params->xgxs_config_tx[1]);
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TX_CTRL1,
-+ params->xgxs_config_tx[0]);
+
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8726_TX_CTRL2,
-+ params->xgxs_config_tx[1]);
-+ }
+ break;
++
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ {
@@ -18945,7 +17259,7 @@
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_M8051_MSGOUT_REG,
++ 0xca13,
+ &tmp1);
+
+ bnx2x_cl45_read(bp, params->port,
@@ -19012,7 +17326,7 @@
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_8073_2_5G, &tmp1);
++ 0x8329, &tmp1);
+
+ if (((params->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
@@ -19026,7 +17340,7 @@
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
++ 0xc801, &phy_ver);
+ DP(NETIF_MSG_LINK, "Add 2.5G\n");
+ if (phy_ver > 0)
+ tmp1 |= 1;
@@ -19041,7 +17355,7 @@
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_8073_2_5G, tmp1);
++ 0x8329, tmp1);
+ }
+
+ /* Add support for CL37 (passive mode) II */
@@ -19116,8 +17430,6 @@
+ break;
+ }
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
-+ {
-+ u16 fw_ver1, fw_ver2;
+ DP(NETIF_MSG_LINK,
+ "Setting the SFX7101 LASI indication\n");
+
@@ -19147,50 +17459,6 @@
+ ext_phy_addr,
+ MDIO_AN_DEVAD,
+ MDIO_AN_REG_CTRL, val);
-+
-+ /* Save spirom version */
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_7101_VER1, &fw_ver1);
-+
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr, MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_7101_VER2, &fw_ver2);
-+
-+ bnx2x_save_spirom_version(params->bp, params->port,
-+ params->shmem_base,
-+ (u32)(fw_ver1<<16 | fw_ver2));
-+
-+ break;
-+ }
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-+ DP(NETIF_MSG_LINK,
-+ "Setting the BCM8481 LASI control\n");
-+
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LASI_CTRL, 0x1);
-+
-+ /* Restart autoneg */
-+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CTRL, &val);
-+ val |= 0x200;
-+ bnx2x_cl45_write(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_CTRL, val);
-+
-+ bnx2x_save_bcm_spirom_ver(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ params->shmem_base);
-+
+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+ DP(NETIF_MSG_LINK,
@@ -19274,43 +17542,38 @@
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
-+ /* Clear RX Alarm*/
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
-+ &val2);
-+ /* clear LASI indication*/
++ DP(NETIF_MSG_LINK, "XGXS 8706\n");
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
-+ &val1);
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_LASI_STATUS, &val1);
++ DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
++
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
-+ &val2);
-+ DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
-+ "0x%x\n", val1, val2);
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_LASI_STATUS, &val1);
++ DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
+
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
-+ &rx_sd);
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_RX_SD, &rx_sd);
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
-+ &pcs_status);
++ MDIO_PCS_DEVAD,
++ MDIO_PCS_REG_STATUS, &pcs_status);
++
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
-+ &val2);
++ MDIO_AN_DEVAD,
++ MDIO_AN_REG_LINK_STATUS, &val2);
+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
+ ext_phy_addr,
-+ MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
-+ &val2);
++ MDIO_AN_DEVAD,
++ MDIO_AN_REG_LINK_STATUS, &val2);
+
-+ DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
++ DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
+ " pcs_status 0x%x 1Gbps link_status 0x%x\n",
+ rx_sd, pcs_status, val2);
+ /* link is up if both bit 0 of pmd_rx_sd and
@@ -19320,31 +17583,19 @@
+ ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
+ (val2 & (1<<1)));
+ if (ext_phy_link_up) {
-+ if (ext_phy_type ==
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
-+ /* If transmitter is disabled,
-+ ignore false link up indication */
-+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_PHY_IDENTIFIER,
-+ &val1);
-+ if (val1 & (1<<15)) {
-+ DP(NETIF_MSG_LINK, "Tx is "
-+ "disabled\n");
-+ ext_phy_link_up = 0;
-+ break;
-+ }
-+ }
-+
+ if (val2 & (1<<1))
+ vars->line_speed = SPEED_1000;
+ else
+ vars->line_speed = SPEED_10000;
+ }
+
++ /* clear LASI indication*/
++ bnx2x_cl45_read(bp, params->port, ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_RX_ALARM, &val2);
+ break;
++
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ {
@@ -19399,7 +17650,7 @@
+ ext_phy_type,
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_M8051_MSGOUT_REG,
++ 0xca13,
+ &val1);
+
+ /* Check the LASI */
@@ -19444,17 +17695,17 @@
+ }
+ }
+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_LINK_STATUS,
-+ &an1000_status);
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_AN_DEVAD,
++ 0x8304,
++ &an1000_status);
+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_LINK_STATUS,
-+ &an1000_status);
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_AN_DEVAD,
++ 0x8304,
++ &an1000_status);
+
+ /* Check the link status on 1.1.2 */
+ bnx2x_cl45_read(bp, params->port,
@@ -19471,7 +17722,7 @@
+ "an_link_status=0x%x\n",
+ val2, val1, an1000_status);
+
-+ ext_phy_link_up = (((val1 & 4) == 4) ||
++ ext_phy_link_up = (((val1 & 4) == 4) ||
+ (an1000_status & (1<<1)));
+ if (ext_phy_link_up &&
+ bnx2x_8073_is_snr_needed(params)) {
@@ -19499,11 +17750,11 @@
+
+ }
+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
-+ &link_status);
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ 0xc820,
++ &link_status);
+
+ /* Bits 0..2 --> speed detected,
+ bits 13..15--> link is down */
@@ -19537,17 +17788,17 @@
+ } else {
+ /* See if 1G link is up for the 8072 */
+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_LINK_STATUS,
-+ &an1000_status);
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_AN_DEVAD,
++ 0x8304,
++ &an1000_status);
+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD,
-+ MDIO_AN_REG_LINK_STATUS,
-+ &an1000_status);
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_AN_DEVAD,
++ 0x8304,
++ &an1000_status);
+ if (an1000_status & (1<<1)) {
+ ext_phy_link_up = 1;
+ vars->line_speed = SPEED_1000;
@@ -19607,53 +17858,7 @@
+ (val2 & (1<<14)));
+ }
+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-+ /* Clear LASI interrupt */
-+ bnx2x_cl45_read(bp, params->port,
-+ ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_LASI_STATUS, &val1);
-+ DP(NETIF_MSG_LINK, "8481 LASI status reg = 0x%x\n",
-+ val1);
-+
-+ /* Check 10G-BaseT link status */
-+ /* Check Global PMD signal ok */
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
-+ &rx_sd);
-+ /* Check PCS block lock */
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
-+ &pcs_status);
-+ DP(NETIF_MSG_LINK, "8481 1.a = 0x%x, 1.20 = 0x%x\n",
-+ rx_sd, pcs_status);
-+ if (rx_sd & pcs_status & 0x1) {
-+ vars->line_speed = SPEED_10000;
-+ ext_phy_link_up = 1;
-+ } else {
-+
-+ /* Check 1000-BaseT link status */
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD, 0xFFE1,
-+ &val1);
-+
-+ bnx2x_cl45_read(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_AN_DEVAD, 0xFFE1,
-+ &val2);
-+ DP(NETIF_MSG_LINK, "8481 7.FFE1 ="
-+ "0x%x-->0x%x\n", val1, val2);
-+ if (val2 & (1<<2)) {
-+ vars->line_speed = SPEED_1000;
-+ ext_phy_link_up = 1;
-+ }
-+ }
+
-+ break;
+ default:
+ DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+ params->ext_phy_config);
@@ -19798,7 +18003,7 @@
+ u8 shift = 8*4;
+ u8 digit;
+ if (len < 10) {
-+ /* Need more then 10chars for this format */
++ /* Need more than 10chars for this format */
+ *str_ptr = '\0';
+ return -EINVAL;
+ }
@@ -19853,7 +18058,7 @@
+ ext_phy_addr,
+ MDIO_PMA_DEVAD,
+ MDIO_PMA_REG_CTRL,
-+ &ctrl);
++ &ctrl);
+ if (!(ctrl & (1<<15))) {
+ DP(NETIF_MSG_LINK, "Reset completed\n\n");
+ break;
@@ -19879,39 +18084,91 @@
+{
+ struct bnx2x *bp = params->bp;
+ u32 ext_phy_type = 0;
-+ u32 spirom_ver = 0;
++ u16 val = 0;
++ u8 ext_phy_addr = 0 ;
+ u8 status = 0 ;
++ u32 ver_num;
+
+ if (version == NULL || params == NULL)
+ return -EINVAL;
+
-+ spirom_ver = REG_RD(bp, params->shmem_base +
-+ offsetof(struct shmem_region,
-+ port_mb[params->port].ext_phy_fw_version));
-+
+ /* reset the returned value to zero */
+ ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
++ ext_phy_addr = ((params->ext_phy_config &
++ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
++ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
++
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+
+ if (len < 5)
+ return -EINVAL;
+
-+ version[0] = (spirom_ver & 0xFF);
-+ version[1] = (spirom_ver & 0xFF00) >> 8;
-+ version[2] = (spirom_ver & 0xFF0000) >> 16;
-+ version[3] = (spirom_ver & 0xFF000000) >> 24;
++ /* Take ext phy out of reset */
++ if (!driver_loaded)
++ bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
++ ext_phy_type);
++
++ /* wait for 1ms */
++ msleep(1);
++
++ bnx2x_cl45_read(bp, params->port,
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_7101_VER1, &val);
++ version[2] = (val & 0xFF);
++ version[3] = ((val & 0xFF00)>>8);
++
++ bnx2x_cl45_read(bp, params->port,
++ ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2,
++ &val);
++ version[0] = (val & 0xFF);
++ version[1] = ((val & 0xFF00)>>8);
+ version[4] = '\0';
+
++ if (!driver_loaded)
++ bnx2x_turn_off_sf(bp, params->port);
+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
++ {
++ /* Take ext phy out of reset */
++ if (!driver_loaded)
++ bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
++ ext_phy_type);
++
++ bnx2x_cl45_read(bp, params->port, ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER1, &val);
++ ver_num = val<<16;
++ bnx2x_cl45_read(bp, params->port, ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER2, &val);
++ ver_num |= val;
++ status = bnx2x_format_ver(ver_num, version, len);
++ break;
++ }
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-+ status = bnx2x_format_ver(spirom_ver, version, len);
++
++ bnx2x_cl45_read(bp, params->port, ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER1, &val);
++ ver_num = val<<16;
++ bnx2x_cl45_read(bp, params->port, ext_phy_type,
++ ext_phy_addr,
++ MDIO_PMA_DEVAD,
++ MDIO_PMA_REG_ROM_VER2, &val);
++ ver_num |= val;
++ status = bnx2x_format_ver(ver_num, version, len);
+ break;
++
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ break;
+
@@ -20011,14 +18268,6 @@
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+ DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
-+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
-+ ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_CTRL,
-+ 0x0001);
-+ break;
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+ /* SFX7101_XGXS_TEST1 */
+ bnx2x_cl45_write(bp, params->port, ext_phy_type,
@@ -20289,13 +18538,11 @@
+
+ /* init ext phy and enable link state int */
+ non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
-+ (params->loopback_mode == LOOPBACK_XGXS_10));
++ (params->loopback_mode == LOOPBACK_XGXS_10) ||
++ (params->loopback_mode == LOOPBACK_EXT_PHY));
+
+ if (non_ext_phy ||
-+ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
-+ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
-+ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
-+ (params->loopback_mode == LOOPBACK_EXT_PHY)) {
++ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) {
+ if (params->req_line_speed == SPEED_AUTO_NEG)
+ bnx2x_set_parallel_detection(params, vars->phy_flags);
+ bnx2x_init_internal_phy(params, vars);
@@ -20489,7 +18736,6 @@
+ return -EINVAL;
+ break;
+ }
-+ DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
+
+ bnx2x_link_initialize(params, vars);
+ msleep(30);
@@ -20498,23 +18744,7 @@
+ return 0;
+}
+
-+static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
-+{
-+ DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
-+
-+ /* Set serial boot control for external load */
-+ bnx2x_cl45_write(bp, port,
-+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
-+ MDIO_PMA_DEVAD,
-+ MDIO_PMA_REG_GEN_CTRL, 0x0001);
-+
-+ /* Disable Transmitter */
-+ bnx2x_bcm8726_set_transmitter(bp, port, ext_phy_addr, 0);
-+
-+}
-+
-+u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
-+ u8 reset_ext_phy)
++u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
+{
+
+ struct bnx2x *bp = params->bp;
@@ -20552,37 +18782,28 @@
+ */
+ /* clear link led */
+ bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
-+ if (reset_ext_phy) {
-+ switch (ext_phy_type) {
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
-+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
-+ DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
-+ "low power mode\n",
-+ port);
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
-+ port);
-+ break;
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ {
-+ u8 ext_phy_addr = ((params->ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ /* Set soft reset */
-+ bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
-+ break;
-+ }
-+ default:
++ if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
++ if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
++ (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
+ /* HW reset */
++
+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ port);
++
+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+ MISC_REGISTERS_GPIO_OUTPUT_LOW,
+ port);
++
+ DP(NETIF_MSG_LINK, "reset external PHY\n");
++ } else if (ext_phy_type ==
++ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
++ DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
++ "low power mode\n",
++ port);
++ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
++ MISC_REGISTERS_GPIO_OUTPUT_LOW,
++ port);
+ }
+ }
+ /* reset the SerDes/XGXS */
@@ -20659,7 +18880,7 @@
+ if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+ if (!(vars->phy_flags &
+ PHY_SGMII_FLAG))
-+ bnx2x_set_gmii_tx_driver(params);
++ bnx2x_set_sgmii_tx_driver(params);
+ }
+ }
+
@@ -20748,7 +18969,6 @@
+
+ if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
+ (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
-+ (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
+ (ext_phy_link_up && !vars->phy_link_up))
+ bnx2x_init_internal_phy(params, vars);
+
@@ -20810,7 +19030,7 @@
+ u16 fw_ver1;
+
+ bnx2x_bcm8073_external_rom_boot(bp, port,
-+ ext_phy_addr[port], shmem_base);
++ ext_phy_addr[port]);
+
+ bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+ ext_phy_addr[port],
@@ -20846,7 +19066,7 @@
+
+ /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
+ for (port = PORT_MAX - 1; port >= PORT_0; port--) {
-+ /* Phase2 of POWER_DOWN_RESET */
++ /* Phase2 of POWER_DOWN_RESET*/
+ /* Release bit 10 (Release Tx power down) */
+ bnx2x_cl45_read(bp, port,
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
@@ -20881,51 +19101,12 @@
+
+}
+
-+
-+static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
-+{
-+ u8 ext_phy_addr;
-+ u32 val;
-+ s8 port;
-+ /* Use port1 because of the static port-swap */
-+ /* Enable the module detection interrupt */
-+ val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
-+ val |= ((1<<MISC_REGISTERS_GPIO_3)|
-+ (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
-+ REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
-+
-+ bnx2x_hw_reset(bp, 1);
-+ msleep(5);
-+ for (port = 0; port < PORT_MAX; port++) {
-+ /* Extract the ext phy address for the port */
-+ u32 ext_phy_config = REG_RD(bp, shmem_base +
-+ offsetof(struct shmem_region,
-+ dev_info.port_hw_config[port].external_phy_config));
-+
-+ ext_phy_addr =
-+ ((ext_phy_config &
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-+ DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
-+ ext_phy_addr);
-+
-+ bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
-+
-+ /* Set fault module detected LED on */
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
-+ MISC_REGISTERS_GPIO_HIGH,
-+ port);
-+ }
-+
-+ return 0;
-+}
-+
+u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
+{
+ u8 rc = 0;
+ u32 ext_phy_type;
+
-+ DP(NETIF_MSG_LINK, "Begin common phy init\n");
++ DP(NETIF_MSG_LINK, "bnx2x_common_init_phy\n");
+
+ /* Read the ext_phy_type for arbitrary port(0) */
+ ext_phy_type = XGXS_EXT_PHY_TYPE(
@@ -20939,12 +19120,6 @@
+ rc = bnx2x_8073_common_init_phy(bp, shmem_base);
+ break;
+ }
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ /* GPIO1 affects both ports, so there's need to pull
-+ it for single port alone */
-+ rc = bnx2x_8726_common_init_phy(bp, shmem_base);
-+
-+ break;
+ default:
+ DP(NETIF_MSG_LINK,
+ "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
@@ -21361,11 +19536,13 @@
+ return rc;
+}
+
-diff -urpN a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
---- a/drivers/net/bnx2x_link.h 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_link.h 2009-05-28 01:52:09.000000000 -0600
-@@ -0,0 +1,184 @@
-+/* Copyright 2008-2009 Broadcom Corporation
+diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
+new file mode 100644
+index 0000000..47cb585
+--- /dev/null
++++ b/drivers/net/bnx2x_link.h
+@@ -0,0 +1,173 @@
++/* Copyright 2008 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
@@ -21433,6 +19610,8 @@
+ /* Device parameters */
+ u8 mac_addr[6];
+
++
++
+ /* shmem parameters */
+ u32 shmem_base;
+ u32 speed_cap_mask;
@@ -21442,6 +19621,7 @@
+#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
+
+ u16 hw_led_mode; /* part of the hw_config read from the shmem */
++ u32 serdes_config;
+ u32 lane_config;
+ u32 ext_phy_config;
+#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
@@ -21453,12 +19633,6 @@
+
+ /* phy_addr populated by the CLC */
+ u8 phy_addr;
-+ u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
-+
-+ u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
-+ u32 feature_config_flags;
-+#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
-+#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0)
+ /* Device pointer passed to all callback functions */
+ struct bnx2x *bp;
+};
@@ -21495,11 +19669,8 @@
+/* Initialize the phy */
+u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
+
-+/* Reset the link. Should be called when driver or interface goes down
-+ Before calling phy firmware upgrade, the reset_ext_phy should be set
-+ to 0 */
-+u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
-+ u8 reset_ext_phy);
++/* Reset the link. Should be called when driver or interface goes down */
++u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars);
+
+/* bnx2x_link_update should be called upon link interrupt */
+u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
@@ -21536,10 +19707,6 @@
+
+u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
+ u8 driver_loaded, char data[], u32 size);
-+/* bnx2x_handle_module_detect_int should be called upon module detection
-+ interrupt */
-+void bnx2x_handle_module_detect_int(struct link_params *params);
-+
+/* Get the actual link status. In case it returns 0, link is up,
+ otherwise link is down*/
+u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
@@ -21547,12 +19714,13 @@
+/* One-time initialization for external phy after power up */
+u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
+
-+
+#endif /* BNX2X_LINK_H */
-diff -urpN a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
---- a/drivers/net/bnx2x_main.c 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_main.c 2009-05-28 01:52:09.000000000 -0600
-@@ -0,0 +1,10938 @@
+diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
+new file mode 100644
+index 0000000..9cdd6a9
+--- /dev/null
++++ b/drivers/net/bnx2x_main.c
+@@ -0,0 +1,10661 @@
+/* bnx2x_main.c: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
@@ -21606,13 +19774,15 @@
+#include <linux/zlib.h>
+#include <linux/io.h>
+
-+
++#include "bnx2x_reg.h"
++#include "bnx2x_fw_defs.h"
++#include "bnx2x_hsi.h"
++#include "bnx2x_link.h"
+#include "bnx2x.h"
+#include "bnx2x_init.h"
-+#include "bnx2x_dump.h"
+
-+#define DRV_MODULE_VERSION "1.48.105"
-+#define DRV_MODULE_RELDATE "2009/03/02"
++#define DRV_MODULE_VERSION "1.45.26"
++#define DRV_MODULE_RELDATE "2009/01/26"
+#define BNX2X_BC_VER 0x040200
+
+/* Time in jiffies before concluding the transmitter is hung */
@@ -21628,33 +19798,30 @@
+MODULE_VERSION(DRV_MODULE_VERSION);
+
+static int disable_tpa;
-+module_param(disable_tpa, int, 0);
-+MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
-+
+static int use_inta;
-+module_param(use_inta, int, 0);
-+MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
-+
+static int poll;
++static int debug;
++static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
++static int use_multi;
++
++module_param(disable_tpa, int, 0);
++module_param(use_inta, int, 0);
+module_param(poll, int, 0);
-+MODULE_PARM_DESC(poll, " Use polling (for debug)");
+
+static int mrrs = -1;
+module_param(mrrs, int, 0);
+MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
+
-+static int debug;
+module_param(debug, int, 0);
-+MODULE_PARM_DESC(debug, " Default debug msglevel");
++MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
++MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
++MODULE_PARM_DESC(poll, "use polling (for debug)");
++MODULE_PARM_DESC(debug, "default debug msglevel");
+
-+static int use_multi;
+#ifdef BNX2X_MULTI
+module_param(use_multi, int, 0);
+MODULE_PARM_DESC(use_multi, "use per-CPU queues");
+#endif
-+
-+static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
-+
+static struct workqueue_struct *bnx2x_wq;
+
+enum bnx2x_board_type {
@@ -22030,7 +20197,7 @@
+static void bnx2x_fw_dump(struct bnx2x *bp)
+{
+ u32 mark, offset;
-+ __be32 data[9];
++ u32 data[9];
+ int word;
+
+ mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
@@ -22181,8 +20348,8 @@
+ if (IS_E1HMF(bp)) {
+ val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
+ if (bp->port.pmf)
-+ /* enable nig and gpio3 attention */
-+ val |= 0x1100;
++ /* enable nig attention */
++ val |= 0x0100;
+ } else
+ val = 0xffff;
+
@@ -22208,7 +20375,6 @@
+ REG_WR(bp, addr, val);
+ if (REG_RD(bp, addr) != val)
+ BNX2X_ERR("BUG! proper val not read from IGU!\n");
-+
+}
+
+static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
@@ -22311,6 +20477,7 @@
+ /* Tell compiler that consumer and producer can change */
+ barrier();
+ return (fp->tx_pkt_prod != fp->tx_pkt_cons);
++
+}
+
+/* free skb in the packet ring at pos idx
@@ -22404,7 +20571,7 @@
+ return (s16)(fp->bp->tx_ring_size) - used;
+}
+
-+static void bnx2x_tx_int(struct bnx2x_fastpath *fp)
++static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
+{
+ struct bnx2x *bp = fp->bp;
+ u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
@@ -22436,24 +20603,26 @@
+ bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
+ sw_cons++;
+ done++;
++
++ if (done == work)
++ break;
+ }
+
+ fp->tx_pkt_cons = sw_cons;
+ fp->tx_bd_cons = bd_cons;
+
++ /* Need to make the tx_cons update visible to start_xmit()
++ * before checking for netif_queue_stopped(). Without the
++ * memory barrier, there is a small possibility that start_xmit()
++ * will miss it and cause the queue to be stopped forever.
++ */
++ smp_mb();
++
+ /* TBD need a thresh? */
+ if (unlikely(netif_queue_stopped(bp->dev))) {
+
+ netif_tx_lock(bp->dev);
+
-+ /* Need to make the tx_cons update visible to start_xmit()
-+ * before checking for netif_queue_stopped(). Without the
-+ * memory barrier, there is a small possibility that
-+ * start_xmit() will miss it and cause the queue to be stopped
-+ * forever.
-+ */
-+ smp_mb();
-+
+ if (netif_queue_stopped(bp->dev) &&
+ (bp->state == BNX2X_STATE_OPEN) &&
+ (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
@@ -22473,12 +20642,12 @@
+
+ DP(BNX2X_MSG_SP,
+ "fp %d cid %d got ramrod #%d state is %x type is %d\n",
-+ fp->index, cid, command, bp->state,
++ FP_IDX(fp), cid, command, bp->state,
+ rr_cqe->ramrod_cqe.ramrod_type);
+
+ bp->spq_left++;
+
-+ if (fp->index) {
++ if (FP_IDX(fp)) {
+ switch (command | fp->state) {
+ case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
+ BNX2X_FP_STATE_OPENING):
@@ -22638,7 +20807,8 @@
+
+ pci_dma_sync_single_for_device(bp->pdev,
+ pci_unmap_addr(cons_rx_buf, mapping),
-+ RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
++ bp->rx_offset + RX_COPY_THRESH,
++ PCI_DMA_FROMDEVICE);
+
+ prod_rx_buf->skb = cons_rx_buf->skb;
+ pci_unmap_addr_set(prod_rx_buf, mapping,
@@ -22956,7 +21126,7 @@
+
+ for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
+ REG_WR(bp, BAR_USTRORM_INTMEM +
-+ USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
++ USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
+ ((u32 *)&rx_prods)[i]);
+
+ mmiowb(); /* keep prod updates ordered */
@@ -22997,7 +21167,7 @@
+
+ DP(NETIF_MSG_RX_STATUS,
+ "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
-+ fp->index, hw_comp_cons, sw_comp_cons);
++ FP_IDX(fp), hw_comp_cons, sw_comp_cons);
+
+ while (sw_comp_cons != hw_comp_cons) {
+ struct sw_rx_bd *rx_buf = NULL;
@@ -23194,7 +21364,7 @@
+ struct bnx2x_fastpath *fp = fp_cookie;
+ struct bnx2x *bp = fp->bp;
+ struct net_device *dev = bp->dev;
-+ int index = fp->index;
++ int index = FP_IDX(fp);
+
+ /* Return here if interrupt is disabled */
+ if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
@@ -23203,8 +21373,8 @@
+ }
+
+ DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
-+ index, fp->sb_id);
-+ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
++ index, FP_SB_ID(fp));
++ bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic))
@@ -23233,7 +21403,7 @@
+ DP(NETIF_MSG_INTR, "not our interrupt!\n");
+ return IRQ_NONE;
+ }
-+ DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
++ DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
+
+ /* Return here if interrupt is disabled */
+ if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
@@ -23368,48 +21538,24 @@
+/* HW Lock for shared dual port PHYs */
+static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
+{
++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
++
+ mutex_lock(&bp->port.phy_mutex);
+
-+ if (bp->port.need_hw_lock)
-+ bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
++ if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
++ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
++ bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
+}
+
+static void bnx2x_release_phy_lock(struct bnx2x *bp)
+{
-+ if (bp->port.need_hw_lock)
-+ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
-+
-+ mutex_unlock(&bp->port.phy_mutex);
-+}
-+
-+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
-+{
-+ /* The GPIO should be swapped if swap register is set and active */
-+ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
-+ REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
-+ int gpio_shift = gpio_num +
-+ (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
-+ u32 gpio_mask = (1 << gpio_shift);
-+ u32 gpio_reg;
-+ int value;
-+
-+ if (gpio_num > MISC_REGISTERS_GPIO_3) {
-+ BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
-+ return -EINVAL;
-+ }
++ u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+
-+ /* read GPIO value */
-+ gpio_reg = REG_RD(bp, MISC_REG_GPIO);
++ if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
++ (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
++ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
+
-+ /* get the requested pin value */
-+ if ((gpio_reg & gpio_mask) == gpio_mask)
-+ value = 1;
-+ else
-+ value = 0;
-+
-+ DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
-+
-+ return value;
++ mutex_unlock(&bp->port.phy_mutex);
+}
+
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
@@ -23465,52 +21611,6 @@
+ return 0;
+}
+
-+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
-+{
-+ /* The GPIO should be swapped if swap register is set and active */
-+ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
-+ REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
-+ int gpio_shift = gpio_num +
-+ (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
-+ u32 gpio_mask = (1 << gpio_shift);
-+ u32 gpio_reg;
-+
-+ if (gpio_num > MISC_REGISTERS_GPIO_3) {
-+ BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
-+ return -EINVAL;
-+ }
-+
-+ bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
-+ /* read GPIO int */
-+ gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
-+
-+ switch (mode) {
-+ case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
-+ DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
-+ "output low\n", gpio_num, gpio_shift);
-+ /* clear SET and set CLR */
-+ gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
-+ gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
-+ break;
-+
-+ case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
-+ DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
-+ "output high\n", gpio_num, gpio_shift);
-+ /* clear CLR and set SET */
-+ gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
-+ gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
-+ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
-+
-+ return 0;
-+}
-+
+static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
+{
+ u32 spio_mask = (1 << spio_num);
@@ -23565,16 +21665,13 @@
+ bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
+ ADVERTISED_Pause);
+ break;
-+
+ case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
+ bp->port.advertising |= (ADVERTISED_Asym_Pause |
+ ADVERTISED_Pause);
+ break;
-+
+ case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
+ bp->port.advertising |= ADVERTISED_Asym_Pause;
+ break;
-+
+ default:
+ bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
+ ADVERTISED_Pause);
@@ -23599,8 +21696,7 @@
+ if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
+ if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
+ printk(", receive ");
-+ if (bp->link_vars.flow_ctrl &
-+ BNX2X_FLOW_CTRL_TX)
++ if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
+ printk("& transmit ");
+ } else {
+ printk(", transmit ");
@@ -23615,7 +21711,7 @@
+ }
+}
+
-+static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
++static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
+{
+ if (!BP_NOMCP(bp)) {
+ u8 rc;
@@ -23631,24 +21727,18 @@
+ bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
+
+ bnx2x_acquire_phy_lock(bp);
-+
-+ if (load_mode == LOAD_DIAG)
-+ bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
-+
+ rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
-+
+ bnx2x_release_phy_lock(bp);
+
+ bnx2x_calc_fc_adv(bp);
+
-+ if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
-+ bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
++ if (bp->link_vars.link_up)
+ bnx2x_link_report(bp);
-+ }
++
+
+ return rc;
+ }
-+ BNX2X_ERR("Bootcode is missing - can not initialize link\n");
++ BNX2X_ERR("Bootcode is missing -not initializing link\n");
+ return -EINVAL;
+}
+
@@ -23659,68 +21749,145 @@
+ bnx2x_phy_init(&bp->link_params, &bp->link_vars);
+ bnx2x_release_phy_lock(bp);
+
-+ bnx2x_calc_fc_adv(bp);
-+ } else
-+ BNX2X_ERR("Bootcode is missing - can not set link\n");
-+}
++ bnx2x_calc_fc_adv(bp);
++ } else
++ BNX2X_ERR("Bootcode is missing -not setting link\n");
++}
++
++static void bnx2x__link_reset(struct bnx2x *bp)
++{
++ if (!BP_NOMCP(bp)) {
++ bnx2x_acquire_phy_lock(bp);
++ bnx2x_link_reset(&bp->link_params, &bp->link_vars);
++ bnx2x_release_phy_lock(bp);
++ } else
++ BNX2X_ERR("Bootcode is missing -not resetting link\n");
++}
++
++static u8 bnx2x_link_test(struct bnx2x *bp)
++{
++ u8 rc;
++
++ bnx2x_acquire_phy_lock(bp);
++ rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
++ bnx2x_release_phy_lock(bp);
++
++ return rc;
++}
++
++/* Calculates the sum of vn_min_rates.
++ It's needed for further normalizing of the min_rates.
++
++ Returns:
++ sum of vn_min_rates
++ or
++ 0 - if all the min_rates are 0.
++ In the later case fairness algorithm should be deactivated.
++ If not all min_rates are zero then those that are zeroes will
++ be set to 1.
++ */
++static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
++{
++ int i, port = BP_PORT(bp);
++ u32 wsum = 0;
++ int all_zero = 1;
++
++ for (i = 0; i < E1HVN_MAX; i++) {
++ u32 vn_cfg =
++ SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
++ u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
++ FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
++ if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
++ /* If min rate is zero - set it to 1 */
++ if (!vn_min_rate)
++ vn_min_rate = DEF_MIN_RATE;
++ else
++ all_zero = 0;
++
++ wsum += vn_min_rate;
++ }
++ }
+
-+static void bnx2x__link_reset(struct bnx2x *bp)
-+{
-+ if (!BP_NOMCP(bp)) {
-+ bnx2x_acquire_phy_lock(bp);
-+ bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
-+ bnx2x_release_phy_lock(bp);
-+ } else
-+ BNX2X_ERR("Bootcode is missing - can not reset link\n");
++ /* ... only if all min rates are zeros - disable FAIRNESS */
++ if (all_zero)
++ return 0;
++
++ return wsum;
+}
+
-+static u8 bnx2x_link_test(struct bnx2x *bp)
++static void bnx2x_init_port_minmax(struct bnx2x *bp,
++ int en_fness,
++ u16 port_rate,
++ struct cmng_struct_per_port *m_cmng_port)
+{
-+ u8 rc;
++ u32 r_param = port_rate / 8;
++ int port = BP_PORT(bp);
++ int i;
+
-+ bnx2x_acquire_phy_lock(bp);
-+ rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
-+ bnx2x_release_phy_lock(bp);
++ memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
+
-+ return rc;
-+}
++ /* Enable minmax only if we are in e1hmf mode */
++ if (IS_E1HMF(bp)) {
++ u32 fair_periodic_timeout_usec;
++ u32 t_fair;
+
-+static void bnx2x_init_port_minmax(struct bnx2x *bp)
-+{
-+ u32 r_param = bp->link_vars.line_speed / 8;
-+ u32 fair_periodic_timeout_usec;
-+ u32 t_fair;
-+
-+ memset(&(bp->cmng.rs_vars), 0,
-+ sizeof(struct rate_shaping_vars_per_port));
-+ memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
-+
-+ /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
-+ bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
-+
-+ /* this is the threshold below which no timer arming will occur
-+ 1.25 coefficient is for the threshold to be a little bigger
-+ than the real time, to compensate for timer in-accuracy */
-+ bp->cmng.rs_vars.rs_threshold =
++ /* Enable rate shaping and fairness */
++ m_cmng_port->flags.cmng_vn_enable = 1;
++ m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
++ m_cmng_port->flags.rate_shaping_enable = 1;
++
++ if (!en_fness)
++ DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
++ " fairness will be disabled\n");
++
++ /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
++ m_cmng_port->rs_vars.rs_periodic_timeout =
++ RS_PERIODIC_TIMEOUT_USEC / 4;
++
++ /* this is the threshold below which no timer arming will occur
++ 1.25 coefficient is for the threshold to be a little bigger
++ than the real time, to compensate for timer in-accuracy */
++ m_cmng_port->rs_vars.rs_threshold =
+ (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
+
-+ /* resolution of fairness timer */
-+ fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
-+ /* for 10G it is 1000usec. for 1G it is 10000usec. */
-+ t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
-+
-+ /* this is the threshold below which we won't arm the timer anymore */
-+ bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
-+
-+ /* we multiply by 1e3/8 to get bytes/msec.
-+ We don't want the credits to pass a credit
-+ of the t_fair*FAIR_MEM (algorithm resolution) */
-+ bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
-+ /* since each tick is 4 usec */
-+ bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
++ /* resolution of fairness timer */
++ fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
++ /* for 10G it is 1000usec. for 1G it is 10000usec. */
++ t_fair = T_FAIR_COEF / port_rate;
++
++ /* this is the threshold below which we won't arm
++ the timer anymore */
++ m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
++
++ /* we multiply by 1e3/8 to get bytes/msec.
++ We don't want the credits to pass a credit
++ of the T_FAIR*FAIR_MEM (algorithm resolution) */
++ m_cmng_port->fair_vars.upper_bound =
++ r_param * t_fair * FAIR_MEM;
++ /* since each tick is 4 usec */
++ m_cmng_port->fair_vars.fairness_timeout =
++ fair_periodic_timeout_usec / 4;
++
++ } else {
++ /* Disable rate shaping and fairness */
++ m_cmng_port->flags.cmng_vn_enable = 0;
++ m_cmng_port->flags.fairness_enable = 0;
++ m_cmng_port->flags.rate_shaping_enable = 0;
++
++ DP(NETIF_MSG_IFUP,
++ "Single function mode minmax will be disabled\n");
++ }
++
++ /* Store it to internal memory */
++ for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
++ REG_WR(bp, BAR_XSTRORM_INTMEM +
++ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
++ ((u32 *)(m_cmng_port))[i]);
+}
+
-+static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
++static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
++ u32 wsum, u16 port_rate,
++ struct cmng_struct_per_port *m_cmng_port)
+{
+ struct rate_shaping_vars_per_vn m_rs_vn;
+ struct fairness_vars_per_vn m_fair_vn;
@@ -23736,18 +21903,17 @@
+ } else {
+ vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+ FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
-+ /* If fairness is enabled (not all min rates are zeroes) and
++ /* If FAIRNESS is enabled (not all min rates are zeroes) and
+ if current min rate is zero - set it to 1.
+ This is a requirement of the algorithm. */
-+ if (bp->vn_weight_sum && (vn_min_rate == 0))
++ if ((vn_min_rate == 0) && wsum)
+ vn_min_rate = DEF_MIN_RATE;
+ vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+ FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+ }
+
-+ DP(NETIF_MSG_IFUP,
-+ "func %d: vn_min_rate=%d vn_max_rate=%d vn_weight_sum=%d\n",
-+ func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
++ DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d vn_max_rate=%d "
++ "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
+
+ memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
+ memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
@@ -23759,20 +21925,55 @@
+ m_rs_vn.vn_counter.quota =
+ (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
+
-+ if (bp->vn_weight_sum) {
++#ifdef BNX2X_PER_PROT_QOS
++ /* per protocol counter */
++ for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
++ /* maximal Mbps for this protocol */
++ m_rs_vn.protocol_counters[protocol].rate =
++ protocol_max_rate[protocol];
++ /* the quota in each timer period -
++ number of bytes transmitted in this period */
++ m_rs_vn.protocol_counters[protocol].quota =
++ (u32)(rs_periodic_timeout_usec *
++ ((double)m_rs_vn.
++ protocol_counters[protocol].rate/8));
++ }
++#endif
++
++ if (wsum) {
+ /* credit for each period of the fairness algorithm:
+ number of bytes in T_FAIR (the vn share the port rate).
-+ vn_weight_sum should not be larger than 10000, thus
-+ T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
-+ than zero */
++ wsum should not be larger than 10000, thus
++ T_FAIR_COEF / (8 * wsum) will always be grater than zero */
+ m_fair_vn.vn_credit_delta =
-+ max((u32)(vn_min_rate * (T_FAIR_COEF /
-+ (8 * bp->vn_weight_sum))),
-+ (u32)(bp->cmng.fair_vars.fair_threshold * 2));
++ max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
++ (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
+ DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
+ m_fair_vn.vn_credit_delta);
+ }
+
++#ifdef BNX2X_PER_PROT_QOS
++ do {
++ u32 protocolWeightSum = 0;
++
++ for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
++ protocolWeightSum +=
++ drvInit.protocol_min_rate[protocol];
++ /* per protocol counter -
++ NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
++ if (protocolWeightSum > 0) {
++ for (protocol = 0;
++ protocol < NUM_OF_PROTOCOLS; protocol++)
++ /* credit for each period of the
++ fairness algorithm - number of bytes in
++ T_FAIR (the protocol share the vn rate) */
++ m_fair_vn.protocol_credit_delta[protocol] =
++ (u32)((vn_min_rate / 8) * t_fair *
++ protocol_min_rate / protocolWeightSum);
++ }
++ } while (0);
++#endif
++
+ /* Store it to internal memory */
+ for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
+ REG_WR(bp, BAR_XSTRORM_INTMEM +
@@ -23785,10 +21986,11 @@
+ ((u32 *)(&m_fair_vn))[i]);
+}
+
-+
+/* This function is called upon link interrupt */
+static void bnx2x_link_attn(struct bnx2x *bp)
+{
++ int vn;
++
+ /* Make sure that we are synced with the current statistics */
+ bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+
@@ -23813,38 +22015,36 @@
+ bnx2x_link_report(bp);
+
+ if (IS_E1HMF(bp)) {
-+ int port = BP_PORT(bp);
+ int func;
-+ int vn;
+
+ for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+ if (vn == BP_E1HVN(bp))
+ continue;
+
-+ func = ((vn << 1) | port);
++ func = ((vn << 1) | BP_PORT(bp));
+
+ /* Set the attention towards other drivers
+ on the same port */
+ REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
+ (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
+ }
++ }
+
-+ if (bp->link_vars.link_up) {
-+ int i;
-+
-+ /* Init rate shaping and fairness contexts */
-+ bnx2x_init_port_minmax(bp);
++ if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
++ struct cmng_struct_per_port m_cmng_port;
++ u32 wsum;
++ int port = BP_PORT(bp);
+
++ /* Init RATE SHAPING and FAIRNESS contexts */
++ wsum = bnx2x_calc_vn_wsum(bp);
++ bnx2x_init_port_minmax(bp, (int)wsum,
++ bp->link_vars.line_speed,
++ &m_cmng_port);
++ if (IS_E1HMF(bp))
+ for (vn = VN_0; vn < E1HVN_MAX; vn++)
-+ bnx2x_init_vn_minmax(bp, 2*vn + port);
-+
-+ /* Store it to internal memory */
-+ for (i = 0;
-+ i < sizeof(struct cmng_struct_per_port) / 4; i++)
-+ REG_WR(bp, BAR_XSTRORM_INTMEM +
-+ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
-+ ((u32 *)(&bp->cmng))[i]);
-+ }
++ bnx2x_init_vn_minmax(bp, 2*vn + port,
++ wsum, bp->link_vars.line_speed,
++ &m_cmng_port);
+ }
+}
+
@@ -24021,7 +22221,6 @@
+ u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
+ NIG_REG_MASK_INTERRUPT_PORT0;
+ u32 aeu_mask;
-+ u32 nig_mask = 0;
+
+ if (bp->attn_state & asserted)
+ BNX2X_ERR("IGU ERROR\n");
@@ -24047,7 +22246,7 @@
+ bnx2x_acquire_phy_lock(bp);
+
+ /* save nig interrupt mask */
-+ nig_mask = REG_RD(bp, nig_int_mask_addr);
++ bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
+ REG_WR(bp, nig_int_mask_addr, 0);
+
+ bnx2x_link_attn(bp);
@@ -24102,7 +22301,7 @@
+
+ /* now set back the mask */
+ if (asserted & ATTN_NIG_FOR_FUNC) {
-+ REG_WR(bp, nig_int_mask_addr, nig_mask);
++ REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
+ bnx2x_release_phy_lock(bp);
+ }
+}
@@ -24124,8 +22323,9 @@
+
+ BNX2X_ERR("SPIO5 hw attention\n");
+
-+ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
++ switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
+ /* Fan failure attention */
+
+ /* The PHY reset is controlled by GPIO 1 */
@@ -24156,13 +22356,6 @@
+ }
+ }
+
-+ if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
-+ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
-+ bnx2x_acquire_phy_lock(bp);
-+ bnx2x_handle_module_detect_int(&bp->link_params);
-+ bnx2x_release_phy_lock(bp);
-+ }
-+
+ if (attn & HW_INTERRUT_ASSERT_SET_0) {
+
+ val = REG_RD(bp, reg_offset);
@@ -24179,7 +22372,7 @@
+{
+ u32 val;
+
-+ if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
++ if (attn & BNX2X_DOORQ_ASSERT) {
+
+ val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
+ BNX2X_ERR("DB hw attention 0x%x\n", val);
@@ -24542,15 +22735,15 @@
+
+#define UPDATE_EXTEND_TSTAT(s, t) \
+ do { \
-+ diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
-+ old_tclient->s = tclient->s; \
++ diff = le32_to_cpu(tclient->s) - old_tclient->s; \
++ old_tclient->s = le32_to_cpu(tclient->s); \
+ ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
+ } while (0)
+
+#define UPDATE_EXTEND_XSTAT(s, t) \
+ do { \
-+ diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
-+ old_xclient->s = xclient->s; \
++ diff = le32_to_cpu(xclient->s) - old_xclient->s; \
++ old_xclient->s = le32_to_cpu(xclient->s); \
+ ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
+ } while (0)
+
@@ -24582,7 +22775,7 @@
+
+ ramrod_data.drv_counter = bp->stats_counter++;
+ ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
-+ ramrod_data.ctr_id_vector = (1 << bp->fp->cl_id);
++ ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
+
+ rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
+ ((u32 *)&ramrod_data)[1],
@@ -25025,10 +23218,7 @@
+{
+ struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
+ struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
-+ struct {
-+ u32 lo;
-+ u32 hi;
-+ } diff;
++ struct regpair diff;
+
+ UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
+ UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
@@ -25105,10 +23295,7 @@
+ struct nig_stats *old = &(bp->port.old_nig_stats);
+ struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
+ struct bnx2x_eth_stats *estats = &bp->eth_stats;
-+ struct {
-+ u32 lo;
-+ u32 hi;
-+ } diff;
++ struct regpair diff;
+
+ if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
+ bnx2x_bmac_stats_update(bp);
@@ -25145,7 +23332,7 @@
+static int bnx2x_storm_stats_update(struct bnx2x *bp)
+{
+ struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
-+ int cl_id = bp->fp->cl_id;
++ int cl_id = BP_CL_ID(bp);
+ struct tstorm_per_port_stats *tport =
+ &stats->tstorm_common.port_statistics;
+ struct tstorm_per_client_stats *tclient =
@@ -25378,12 +23565,12 @@
+ "mac_discard %u mac_filter_discard %u "
+ "xxovrflow_discard %u brb_truncate_discard %u "
+ "ttl0_discard %u\n",
-+ le32_to_cpu(old_tclient->checksum_discard),
++ old_tclient->checksum_discard,
+ old_tclient->packets_too_big_discard,
+ old_tclient->no_buff_discard, estats->mac_discard,
+ estats->mac_filter_discard, estats->xxoverflow_discard,
+ estats->brb_truncate_discard,
-+ le32_to_cpu(old_tclient->ttl0_discard));
++ old_tclient->ttl0_discard);
+
+ for_each_queue(bp, i) {
+ printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
@@ -25532,7 +23719,7 @@
+ struct bnx2x_fastpath *fp = &bp->fp[0];
+ int rc;
+
-+ bnx2x_tx_int(fp);
++ bnx2x_tx_int(fp, 1000);
+ rc = bnx2x_rx_int(fp, 1000);
+ }
+
@@ -25580,10 +23767,10 @@
+{
+ int port = BP_PORT(bp);
+
-+ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
++ bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
+ USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
+ sizeof(struct ustorm_status_block)/4);
-+ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
++ bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
+ sizeof(struct cstorm_status_block)/4);
+}
@@ -25637,18 +23824,18 @@
+{
+ int func = BP_FUNC(bp);
+
-+ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
-+ TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
-+ sizeof(struct tstorm_def_status_block)/4);
-+ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
++ bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
+ USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+ sizeof(struct ustorm_def_status_block)/4);
-+ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
++ bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
+ CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+ sizeof(struct cstorm_def_status_block)/4);
-+ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
++ bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
+ XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+ sizeof(struct xstorm_def_status_block)/4);
++ bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
++ TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
++ sizeof(struct tstorm_def_status_block)/4);
+}
+
+static void bnx2x_init_def_sb(struct bnx2x *bp,
@@ -25814,7 +24001,8 @@
+ if (fp->tpa_state[i] == BNX2X_TPA_START)
+ pci_unmap_single(bp->pdev,
+ pci_unmap_addr(rx_buf, mapping),
-+ bp->rx_buf_size, PCI_DMA_FROMDEVICE);
++ bp->rx_buf_size,
++ PCI_DMA_FROMDEVICE);
+
+ dev_kfree_skb(skb);
+ rx_buf->skb = NULL;
@@ -25829,11 +24017,14 @@
+ u16 ring_prod, cqe_ring_prod;
+ int i, j;
+
-+ bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN;
-+ DP(NETIF_MSG_IFUP,
-+ "mtu %d rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
++ bp->rx_buf_size = bp->dev->mtu;
++ bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD +
++ BCM_RX_ETH_PAYLOAD_ALIGN;
+
+ if (bp->flags & TPA_ENABLE_FLAG) {
++ DP(NETIF_MSG_IFUP,
++ "rx_buf_size %d effective_mtu %d\n",
++ bp->rx_buf_size, bp->dev->mtu + ETH_OVREHEAD);
+
+ for_each_queue(bp, j) {
+ struct bnx2x_fastpath *fp = &bp->fp[j];
@@ -26023,17 +24214,16 @@
+ for_each_queue(bp, i) {
+ struct eth_context *context = bnx2x_sp(bp, context[i].eth);
+ struct bnx2x_fastpath *fp = &bp->fp[i];
-+ u8 cl_id = fp->cl_id;
-+ u8 sb_id = fp->sb_id;
++ u8 sb_id = FP_SB_ID(fp);
+
+ context->ustorm_st_context.common.sb_index_numbers =
+ BNX2X_RX_SB_INDEX_NUM;
-+ context->ustorm_st_context.common.clientId = cl_id;
++ context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
+ context->ustorm_st_context.common.status_block_id = sb_id;
+ context->ustorm_st_context.common.flags =
+ USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
+ context->ustorm_st_context.common.mc_alignment_log_size =
-+ BNX2X_RX_ALIGN_SHIFT;
++ 6 /*BCM_RX_ETH_PAYLOAD_ALIGN*/;
+ context->ustorm_st_context.common.bd_buff_size =
+ bp->rx_buf_size;
+ context->ustorm_st_context.common.bd_page_base_hi =
@@ -26066,7 +24256,7 @@
+ U64_HI(fp->tx_prods_mapping);
+ context->xstorm_st_context.db_data_addr_lo =
+ U64_LO(fp->tx_prods_mapping);
-+ context->xstorm_st_context.statistics_data = (cl_id |
++ context->xstorm_st_context.statistics_data = (fp->cl_id |
+ XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
+ context->cstorm_st_context.sb_index_number =
+ C_SB_ETH_TX_CQ_INDEX;
@@ -26091,7 +24281,7 @@
+ for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
+ REG_WR8(bp, BAR_TSTRORM_INTMEM +
+ TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
-+ bp->fp->cl_id + (i % bp->num_queues));
++ BP_CL_ID(bp) + (i % bp->num_queues));
+}
+
+static void bnx2x_set_client_config(struct bnx2x *bp)
@@ -26101,7 +24291,7 @@
+ int i;
+
+ tstorm_client.mtu = bp->dev->mtu;
-+ tstorm_client.statistics_counter_id = bp->fp->cl_id;
++ tstorm_client.statistics_counter_id = BP_CL_ID(bp);
+ tstorm_client.config_flags =
+ TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
+#ifdef BCM_VLAN
@@ -26153,22 +24343,18 @@
+ tstorm_mac_filter.mcast_drop_all = mask;
+ tstorm_mac_filter.bcast_drop_all = mask;
+ break;
-+
+ case BNX2X_RX_MODE_NORMAL:
+ tstorm_mac_filter.bcast_accept_all = mask;
+ break;
-+
+ case BNX2X_RX_MODE_ALLMULTI:
+ tstorm_mac_filter.mcast_accept_all = mask;
+ tstorm_mac_filter.bcast_accept_all = mask;
+ break;
-+
+ case BNX2X_RX_MODE_PROMISC:
+ tstorm_mac_filter.ucast_accept_all = mask;
+ tstorm_mac_filter.mcast_accept_all = mask;
+ tstorm_mac_filter.bcast_accept_all = mask;
+ break;
-+
+ default:
+ BNX2X_ERR("BAD rx mode (%d)\n", mode);
+ break;
@@ -26219,47 +24405,6 @@
+ REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+}
+
-+/* Calculates the sum of vn_min_rates.
-+ It's needed for further normalizing of the min_rates.
-+ Returns:
-+ sum of vn_min_rates.
-+ or
-+ 0 - if all the min_rates are 0.
-+ In the later case fainess algorithm should be deactivated.
-+ If not all min_rates are zero then those that are zeroes will be set to 1.
-+ */
-+static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
-+{
-+ int all_zero = 1;
-+ int port = BP_PORT(bp);
-+ int vn;
-+
-+ bp->vn_weight_sum = 0;
-+ for (vn = VN_0; vn < E1HVN_MAX; vn++) {
-+ int func = 2*vn + port;
-+ u32 vn_cfg =
-+ SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
-+ u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
-+ FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
-+
-+ /* Skip hidden vns */
-+ if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
-+ continue;
-+
-+ /* If min rate is zero - set it to 1 */
-+ if (!vn_min_rate)
-+ vn_min_rate = DEF_MIN_RATE;
-+ else
-+ all_zero = 0;
-+
-+ bp->vn_weight_sum += vn_min_rate;
-+ }
-+
-+ /* ... only if all min rates are zeros - disable fairness */
-+ if (all_zero)
-+ bp->vn_weight_sum = 0;
-+}
-+
+static void bnx2x_init_internal_func(struct bnx2x *bp)
+{
+ struct tstorm_eth_function_common_config tstorm_config = {0};
@@ -26289,13 +24434,13 @@
+ /* reset xstorm per client statistics */
+ for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
+ REG_WR(bp, BAR_XSTRORM_INTMEM +
-+ XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, bp->fp->cl_id) +
++ XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
+ i*4, 0);
+ }
+ /* reset tstorm per client statistics */
+ for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
+ REG_WR(bp, BAR_TSTRORM_INTMEM +
-+ TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, bp->fp->cl_id) +
++ TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
+ i*4, 0);
+ }
+
@@ -26354,55 +24499,16 @@
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ REG_WR(bp, BAR_USTRORM_INTMEM +
-+ USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
++ USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
+ U64_LO(fp->rx_comp_mapping));
+ REG_WR(bp, BAR_USTRORM_INTMEM +
-+ USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
++ USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
+ U64_HI(fp->rx_comp_mapping));
+
+ REG_WR16(bp, BAR_USTRORM_INTMEM +
-+ USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
++ USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
+ max_agg_size);
+ }
-+
-+ memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
-+
-+ /* Init rate shaping and fairness contexts */
-+ if (IS_E1HMF(bp)) {
-+ int vn;
-+
-+ /* During init there is no active link
-+ Until link is up, set link rate to 10Gbps */
-+ bp->link_vars.line_speed = SPEED_10000;
-+ bnx2x_init_port_minmax(bp);
-+
-+ bnx2x_calc_vn_weight_sum(bp);
-+
-+ for (vn = VN_0; vn < E1HVN_MAX; vn++)
-+ bnx2x_init_vn_minmax(bp, 2*vn + port);
-+
-+ /* Enable rate shaping and fairness */
-+ bp->cmng.flags.cmng_enables =
-+ CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
-+ if (bp->vn_weight_sum)
-+ bp->cmng.flags.cmng_enables |=
-+ CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
-+ else
-+ DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
-+ " fairness will be disabled\n");
-+ } else {
-+ /* rate shaping and fairness are disabled */
-+ DP(NETIF_MSG_IFUP,
-+ "single function mode minmax will be disabled\n");
-+ }
-+
-+
-+ /* Store it to internal memory */
-+ if (bp->port.pmf)
-+ for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
-+ REG_WR(bp, BAR_XSTRORM_INTMEM +
-+ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
-+ ((u32 *)(&bp->cmng))[i]);
+}
+
+static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
@@ -26439,17 +24545,13 @@
+ fp->cl_id = BP_L_ID(bp) + i;
+ fp->sb_id = fp->cl_id;
+ DP(NETIF_MSG_IFUP,
-+ "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n",
-+ i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
++ "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
++ bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
+ bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
-+ fp->sb_id);
++ FP_SB_ID(fp));
+ bnx2x_update_fpsb_idx(fp);
+ }
+
-+ /* ensure status block indices were read */
-+ rmb();
-+
-+
+ bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
+ DEF_SB_ID);
+ bnx2x_update_dsb_idx(bp);
@@ -26915,10 +25017,37 @@
+ bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
+ bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
+
-+ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
-+ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
-+ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
-+ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
++ if (CHIP_IS_E1H(bp)) {
++ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp,
++ TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
++ 0, STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp,
++ CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
++ 0, STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp,
++ XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
++ 0, STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1H/2);
++ bnx2x_init_fill(bp,
++ USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
++ 0, STORM_INTMEM_SIZE_E1H/2);
++ } else { /* E1 */
++ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1);
++ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1);
++ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1);
++ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
++ STORM_INTMEM_SIZE_E1);
++ }
+
+ bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
+ bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
@@ -27016,14 +25145,9 @@
+ return -EBUSY;
+ }
+
-+ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ bp->port.need_hw_lock = 1;
-+ break;
-+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
++ switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
+ /* Fan failure is indicated by SPIO 5 */
+ bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
+ MISC_REGISTERS_SPIO_INPUT_HI_Z);
@@ -27114,7 +25238,6 @@
+ /* Port CSDM comes here */
+ /* Port USDM comes here */
+ /* Port XSDM comes here */
-+
+ bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
+ port ? TSEM_PORT1_END : TSEM_PORT0_END);
+ bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
@@ -27123,7 +25246,6 @@
+ port ? CSEM_PORT1_END : CSEM_PORT0_END);
+ bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
+ port ? XSEM_PORT1_END : XSEM_PORT0_END);
-+
+ /* Port UPB comes here */
+ /* Port XPB comes here */
+
@@ -27182,55 +25304,36 @@
+ /* Port EMAC1 comes here */
+ /* Port DBU comes here */
+ /* Port DBG comes here */
-+
+ bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
+ port ? NIG_PORT1_END : NIG_PORT0_END);
+
+ REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
+
+ if (CHIP_IS_E1H(bp)) {
++ u32 wsum;
++ struct cmng_struct_per_port m_cmng_port;
++ int vn;
++
+ /* 0x2 disable e1hov, 0x1 enable */
+ REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
+ (IS_E1HMF(bp) ? 0x1 : 0x2));
+
++ /* Init RATE SHAPING and FAIRNESS contexts.
++ Initialize as if there is 10G link. */
++ wsum = bnx2x_calc_vn_wsum(bp);
++ bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
++ if (IS_E1HMF(bp))
++ for (vn = VN_0; vn < E1HVN_MAX; vn++)
++ bnx2x_init_vn_minmax(bp, 2*vn + port,
++ wsum, 10000, &m_cmng_port);
+ }
+
+ /* Port MCP comes here */
+ /* Port DMAE comes here */
+
-+ switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ {
-+ u32 swap_val, swap_override, aeu_gpio_mask, offset;
-+
-+ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
-+ MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
-+
-+ /* The GPIO should be swapped if the swap register is
-+ set and active */
-+ swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
-+ swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
-+
-+ /* Select function upon port-swap configuration */
-+ if (port == 0) {
-+ offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
-+ aeu_gpio_mask = (swap_val && swap_override) ?
-+ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
-+ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
-+ } else {
-+ offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
-+ aeu_gpio_mask = (swap_val && swap_override) ?
-+ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
-+ AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
-+ }
-+ val = REG_RD(bp, offset);
-+ /* add GPIO3 to group */
-+ val |= aeu_gpio_mask;
-+ REG_WR(bp, offset, val);
-+ }
-+ break;
-+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
++ switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
++ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
+ /* add SPIO 5 to group 0 */
+ val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
+ val |= AEU_INPUTS_ATTN_BITS_SPIO5;
@@ -27633,7 +25736,8 @@
+
+ pci_unmap_single(bp->pdev,
+ pci_unmap_addr(rx_buf, mapping),
-+ bp->rx_buf_size, PCI_DMA_FROMDEVICE);
++ bp->rx_buf_size,
++ PCI_DMA_FROMDEVICE);
+
+ rx_buf->skb = NULL;
+ dev_kfree_skb(skb);
@@ -27782,8 +25886,10 @@
+{
+ bnx2x_int_disable_sync(bp, disable_hw);
+ bnx2x_napi_disable(bp);
-+ netif_tx_disable(bp->dev);
-+ bp->dev->trans_start = jiffies; /* prevent tx timeout */
++ if (netif_running(bp->dev)) {
++ netif_tx_disable(bp->dev);
++ bp->dev->trans_start = jiffies; /* prevent tx timeout */
++ }
+}
+
+/*
@@ -27801,7 +25907,7 @@
+ */
+ config->hdr.length = 2;
+ config->hdr.offset = port ? 32 : 0;
-+ config->hdr.client_id = bp->fp->cl_id;
++ config->hdr.client_id = BP_CL_ID(bp);
+ config->hdr.reserved1 = 0;
+
+ /* primary MAC */
@@ -27826,9 +25932,9 @@
+ config->config_table[0].cam_entry.lsb_mac_addr);
+
+ /* broadcast */
-+ config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff);
-+ config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff);
-+ config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff);
++ config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
++ config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
++ config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
+ config->config_table[1].cam_entry.flags = cpu_to_le16(port);
+ if (set)
+ config->config_table[1].target_table_entry.flags =
@@ -27859,7 +25965,7 @@
+ */
+ config->hdr.length = 1;
+ config->hdr.offset = BP_FUNC(bp);
-+ config->hdr.client_id = bp->fp->cl_id;
++ config->hdr.client_id = BP_CL_ID(bp);
+ config->hdr.reserved1 = 0;
+
+ /* primary MAC */
@@ -27893,7 +25999,7 @@
+ int *state_p, int poll)
+{
+ /* can take a while if any port is running */
-+ int cnt = 5000;
++ int cnt = 500;
+
+ DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
+ poll ? "polling" : "waiting", state, idx);
@@ -27911,12 +26017,8 @@
+ }
+
+ mb(); /* state is changed by bnx2x_sp_event() */
-+ if (*state_p == state) {
-+#ifdef BNX2X_STOP_ON_ERROR
-+ DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
-+#endif
++ if (*state_p == state)
+ return 0;
-+ }
+
+ msleep(1);
+ }
@@ -28067,11 +26169,11 @@
+ } else {
+ int port = BP_PORT(bp);
+
-+ DP(NETIF_MSG_IFUP, "NO MCP - load counts %d, %d, %d\n",
++ DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
+ load_count[0], load_count[1], load_count[2]);
+ load_count[0]++;
+ load_count[1 + port]++;
-+ DP(NETIF_MSG_IFUP, "NO MCP - new load counts %d, %d, %d\n",
++ DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
+ load_count[0], load_count[1], load_count[2]);
+ if (load_count[0] == 1)
+ load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
@@ -28118,7 +26220,7 @@
+
+ if (CHIP_IS_E1H(bp))
+ if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
-+ DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
++ BNX2X_ERR("!!! mf_cfg function disabled\n");
+ bp->state = BNX2X_STATE_DISABLED;
+ }
+
@@ -28135,7 +26237,7 @@
+ bnx2x_set_mac_addr_e1h(bp, 1);
+
+ if (bp->port.pmf)
-+ bnx2x_initial_phy_init(bp, load_mode);
++ bnx2x_initial_phy_init(bp);
+
+ /* Start fast path */
+ switch (load_mode) {
@@ -28189,6 +26291,8 @@
+ bnx2x_napi_disable(bp);
+ bnx2x_free_mem(bp);
+
++ /* TBD we really need to reset the chip
++ if we want to recover from this */
+ return rc;
+}
+
@@ -28217,7 +26321,7 @@
+
+static int bnx2x_stop_leading(struct bnx2x *bp)
+{
-+ __le16 dsb_sp_prod_idx;
++ u16 dsb_sp_prod_idx;
+ /* if the other port is handling traffic,
+ this can take a lot of time */
+ int cnt = 500;
@@ -28227,7 +26331,7 @@
+
+ /* Send HALT ramrod */
+ bp->fp[0].state = BNX2X_FP_STATE_HALTING;
-+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0);
++ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, BP_CL_ID(bp), 0);
+
+ /* Wait for completion */
+ rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
@@ -28251,8 +26355,9 @@
+ *bp->dsb_sp_prod, dsb_sp_prod_idx);
+#ifdef BNX2X_STOP_ON_ERROR
+ bnx2x_panic();
-+#endif
++#else
+ rc = -EBUSY;
++#endif
+ break;
+ }
+ cnt--;
@@ -28363,9 +26468,10 @@
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ cnt = 1000;
++ smp_rmb();
+ while (bnx2x_has_tx_work_unload(fp)) {
+
-+ bnx2x_tx_int(fp);
++ bnx2x_tx_int(fp, 1000);
+ if (!cnt) {
+ BNX2X_ERR("timeout waiting for queue[%d]\n",
+ i);
@@ -28378,6 +26484,7 @@
+ }
+ cnt--;
+ msleep(1);
++ smp_rmb();
+ }
+ }
+ /* Give HW time to discard old tx messages */
@@ -28397,7 +26504,7 @@
+ config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
+ else
+ config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
-+ config->hdr.client_id = bp->fp->cl_id;
++ config->hdr.client_id = BP_CL_ID(bp);
+ config->hdr.reserved1 = 0;
+
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
@@ -28461,11 +26568,11 @@
+ if (!BP_NOMCP(bp))
+ reset_code = bnx2x_fw_command(bp, reset_code);
+ else {
-+ DP(NETIF_MSG_IFDOWN, "NO MCP - load counts %d, %d, %d\n",
++ DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
+ load_count[0], load_count[1], load_count[2]);
+ load_count[0]--;
+ load_count[1 + port]--;
-+ DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts %d, %d, %d\n",
++ DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
+ load_count[0], load_count[1], load_count[2]);
+ if (load_count[0] == 0)
+ reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
@@ -28485,7 +26592,6 @@
+ /* Report UNLOAD_DONE to MCP */
+ if (!BP_NOMCP(bp))
+ bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
-+
+ bp->port.pmf = 0;
+
+ /* Free SKBs, SGEs, TPA pool and driver internals */
@@ -28532,64 +26638,6 @@
+ * Init service functions
+ */
+
-+static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func)
-+{
-+ switch (func) {
-+ case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0;
-+ case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1;
-+ case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2;
-+ case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3;
-+ case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4;
-+ case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5;
-+ case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6;
-+ case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7;
-+ default:
-+ BNX2X_ERR("Unsupported function index: %d\n", func);
-+ return (u32)(-1);
-+ }
-+}
-+
-+static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
-+{
-+ u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val;
-+
-+ /* Flush all outstanding writes */
-+ mmiowb();
-+
-+ /* Pretend to be function 0 */
-+ REG_WR(bp, reg, 0);
-+ /* Flush the GRC transaction (in the chip) */
-+ new_val = REG_RD(bp, reg);
-+ if (new_val != 0) {
-+ BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
-+ new_val);
-+ BUG();
-+ }
-+
-+ /* From now we are in the "like-E1" mode */
-+ bnx2x_int_disable(bp);
-+
-+ /* Flush all outstanding writes */
-+ mmiowb();
-+
-+ /* Restore the original funtion settings */
-+ REG_WR(bp, reg, orig_func);
-+ new_val = REG_RD(bp, reg);
-+ if (new_val != orig_func) {
-+ BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
-+ orig_func, new_val);
-+ BUG();
-+ }
-+}
-+
-+static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func)
-+{
-+ if (CHIP_IS_E1H(bp))
-+ bnx2x_undi_int_disable_e1h(bp, func);
-+ else
-+ bnx2x_int_disable(bp);
-+}
-+
+static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
+{
+ u32 val;
@@ -28640,7 +26688,8 @@
+ /* now it's safe to release the lock */
+ bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
+
-+ bnx2x_undi_int_disable(bp, func);
++ REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 :
++ HC_REG_CONFIG_0), 0x1000);
+
+ /* close input traffic and wait for it */
+ /* Do not rcv packets to BRB */
@@ -28732,21 +26781,15 @@
+ BNX2X_ERR("BAD MCP validity signature\n");
+
+ bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
-+ BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
++ bp->common.board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
++
++ BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n",
++ bp->common.hw_config, bp->common.board);
+
+ bp->link_params.hw_led_mode = ((bp->common.hw_config &
+ SHARED_HW_CFG_LED_MODE_MASK) >>
+ SHARED_HW_CFG_LED_MODE_SHIFT);
+
-+ bp->link_params.feature_config_flags = 0;
-+ val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
-+ if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
-+ bp->link_params.feature_config_flags |=
-+ FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
-+ else
-+ bp->link_params.feature_config_flags &=
-+ ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
-+
+ val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
+ bp->common.bc_ver = val;
+ BNX2X_DEV_INFO("bc_ver %X\n", val);
@@ -28765,7 +26808,7 @@
+ bp->flags |= NO_WOL_FLAG;
+ }
+ BNX2X_DEV_INFO("%sWoL capable\n",
-+ (bp->flags & NO_WOL_FLAG) ? "not " : "");
++ (bp->flags & NO_WOL_FLAG) ? "Not " : "");
+
+ val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
+ val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
@@ -28858,31 +26901,6 @@
+ SUPPORTED_Asym_Pause);
+ break;
+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
-+ BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
-+ ext_phy_type);
-+
-+ bp->port.supported |= (SUPPORTED_10000baseT_Full |
-+ SUPPORTED_1000baseT_Full |
-+ SUPPORTED_FIBRE |
-+ SUPPORTED_Autoneg |
-+ SUPPORTED_Pause |
-+ SUPPORTED_Asym_Pause);
-+ break;
-+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
-+ BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
-+ ext_phy_type);
-+
-+ bp->port.supported |= (SUPPORTED_10000baseT_Full |
-+ SUPPORTED_2500baseX_Full |
-+ SUPPORTED_1000baseT_Full |
-+ SUPPORTED_FIBRE |
-+ SUPPORTED_Autoneg |
-+ SUPPORTED_Pause |
-+ SUPPORTED_Asym_Pause);
-+ break;
-+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
+ ext_phy_type);
@@ -28904,39 +26922,36 @@
+ SUPPORTED_Asym_Pause);
+ break;
+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-+ BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
+ ext_phy_type);
+
+ bp->port.supported |= (SUPPORTED_10000baseT_Full |
+ SUPPORTED_1000baseT_Full |
-+ SUPPORTED_Autoneg |
+ SUPPORTED_FIBRE |
++ SUPPORTED_Autoneg |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+ break;
+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
-+ BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
++ BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
+ ext_phy_type);
+
+ bp->port.supported |= (SUPPORTED_10000baseT_Full |
-+ SUPPORTED_TP |
++ SUPPORTED_2500baseX_Full |
++ SUPPORTED_1000baseT_Full |
++ SUPPORTED_FIBRE |
+ SUPPORTED_Autoneg |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+ break;
+
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
-+ BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
++ BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
+ ext_phy_type);
+
-+ bp->port.supported |= (SUPPORTED_10baseT_Half |
-+ SUPPORTED_10baseT_Full |
-+ SUPPORTED_100baseT_Half |
-+ SUPPORTED_100baseT_Full |
-+ SUPPORTED_1000baseT_Full |
-+ SUPPORTED_10000baseT_Full |
++ bp->port.supported |= (SUPPORTED_10000baseT_Full |
+ SUPPORTED_TP |
+ SUPPORTED_Autoneg |
+ SUPPORTED_Pause |
@@ -29168,12 +27183,12 @@
+{
+ int port = BP_PORT(bp);
+ u32 val, val2;
-+ u32 config;
-+ u16 i;
+
+ bp->link_params.bp = bp;
+ bp->link_params.port = port;
+
++ bp->link_params.serdes_config =
++ SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
+ bp->link_params.lane_config =
+ SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
+ bp->link_params.ext_phy_config =
@@ -29186,35 +27201,10 @@
+ bp->port.link_config =
+ SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
+
-+ /* Get the 4 lanes xgxs config rx and tx */
-+ for (i = 0; i < 2; i++) {
-+ val = SHMEM_RD(bp,
-+ dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
-+ bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
-+ bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
-+
-+ val = SHMEM_RD(bp,
-+ dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
-+ bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
-+ bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
-+ }
-+
-+ config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
-+ if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
-+ bp->link_params.feature_config_flags |=
-+ FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
-+ else
-+ bp->link_params.feature_config_flags &=
-+ ~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
-+
-+ /* If the device is capable of WoL, set the default state according
-+ * to the HW
-+ */
-+ bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
-+ (config & PORT_FEATURE_WOL_ENABLED));
-+
-+ BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x"
-+ " speed_cap_mask 0x%08x link_config 0x%08x\n",
++ BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
++ KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
++ " link_config 0x%08x\n",
++ bp->link_params.serdes_config,
+ bp->link_params.lane_config,
+ bp->link_params.ext_phy_config,
+ bp->link_params.speed_cap_mask, bp->port.link_config);
@@ -29261,7 +27251,7 @@
+ "(0x%04x)\n",
+ func, bp->e1hov, bp->e1hov);
+ } else {
-+ BNX2X_DEV_INFO("single function mode\n");
++ BNX2X_DEV_INFO("Single function mode\n");
+ if (BP_E1HVN(bp)) {
+ BNX2X_ERR("!!! No valid E1HOV for func %d,"
+ " aborting\n", func);
@@ -29311,7 +27301,6 @@
+static int __devinit bnx2x_init_bp(struct bnx2x *bp)
+{
+ int func = BP_FUNC(bp);
-+ int timer_interval;
+ int rc;
+
+ /* Disable interrupt handling until HW is initialized */
@@ -29350,12 +27339,13 @@
+ bp->rx_ring_size = MAX_RX_AVAIL;
+
+ bp->rx_csum = 1;
++ bp->rx_offset = 0;
+
+ bp->tx_ticks = 50;
+ bp->rx_ticks = 25;
+
-+ timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
-+ bp->current_interval = (poll ? poll : timer_interval);
++ bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
++ bp->current_interval = (poll ? poll : bp->timer_interval);
+
+ init_timer(&bp->timer);
+ bp->timer.expires = jiffies + bp->current_interval;
@@ -29400,16 +27390,14 @@
+
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
++ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+ cmd->port = PORT_FIBRE;
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
-+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+ cmd->port = PORT_TP;
+ break;
+
@@ -29631,84 +27619,6 @@
+ info->regdump_len = 0;
+}
+
-+#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
-+#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
-+
-+static int bnx2x_get_regs_len(struct net_device *dev)
-+{
-+ static u32 regdump_len;
-+ struct bnx2x *bp = netdev_priv(dev);
-+ int i;
-+
-+ if (regdump_len)
-+ return regdump_len;
-+
-+ if (CHIP_IS_E1(bp)) {
-+ for (i = 0; i < REGS_COUNT; i++)
-+ if (IS_E1_ONLINE(reg_addrs[i].info))
-+ regdump_len += reg_addrs[i].size;
-+
-+ for (i = 0; i < WREGS_COUNT_E1; i++)
-+ if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
-+ regdump_len += wreg_addrs_e1[i].size *
-+ (1 + wreg_addrs_e1[i].read_regs_count);
-+
-+ } else { /* E1H */
-+ for (i = 0; i < REGS_COUNT; i++)
-+ if (IS_E1H_ONLINE(reg_addrs[i].info))
-+ regdump_len += reg_addrs[i].size;
-+
-+ for (i = 0; i < WREGS_COUNT_E1H; i++)
-+ if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
-+ regdump_len += wreg_addrs_e1h[i].size *
-+ (1 + wreg_addrs_e1h[i].read_regs_count);
-+ }
-+ regdump_len *= 4;
-+ regdump_len += sizeof(struct dump_hdr);
-+
-+ return regdump_len;
-+}
-+
-+static void bnx2x_get_regs(struct net_device *dev,
-+ struct ethtool_regs *regs, void *_p)
-+{
-+ u32 *p = _p, i, j;
-+ struct bnx2x *bp = netdev_priv(dev);
-+ struct dump_hdr dump_hdr = {0};
-+
-+ regs->version = 0;
-+ memset(p, 0, regs->len);
-+
-+ if (!netif_running(bp->dev))
-+ return;
-+
-+ dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
-+ dump_hdr.dump_sign = dump_sign_all;
-+ dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
-+ dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
-+ dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
-+ dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
-+ dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
-+
-+ memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
-+ p += dump_hdr.hdr_size + 1;
-+
-+ if (CHIP_IS_E1(bp)) {
-+ for (i = 0; i < REGS_COUNT; i++)
-+ if (IS_E1_ONLINE(reg_addrs[i].info))
-+ for (j = 0; j < reg_addrs[i].size; j++)
-+ *p++ = REG_RD(bp,
-+ reg_addrs[i].addr + j*4);
-+
-+ } else { /* E1H */
-+ for (i = 0; i < REGS_COUNT; i++)
-+ if (IS_E1H_ONLINE(reg_addrs[i].info))
-+ for (j = 0; j < reg_addrs[i].size; j++)
-+ *p++ = REG_RD(bp,
-+ reg_addrs[i].addr + j*4);
-+ }
-+}
-+
+static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+ struct bnx2x *bp = netdev_priv(dev);
@@ -29867,7 +27777,7 @@
+ MCPR_NVM_ACCESS_ENABLE_WR_EN)));
+}
+
-+static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
++static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
+ u32 cmd_flags)
+{
+ int count, i, rc;
@@ -29903,7 +27813,8 @@
+ /* we read nvram data in cpu order
+ * but ethtool sees it as an array of bytes
+ * converting to big-endian will do the work */
-+ *ret_val = cpu_to_be32(val);
++ val = cpu_to_be32(val);
++ *ret_val = val;
+ rc = 0;
+ break;
+ }
@@ -29917,7 +27828,7 @@
+{
+ int rc;
+ u32 cmd_flags;
-+ __be32 val;
++ u32 val;
+
+ if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+ DP(BNX2X_MSG_NVM,
@@ -30036,7 +27947,7 @@
+ int rc;
+ u32 cmd_flags;
+ u32 align_offset;
-+ __be32 val;
++ u32 val;
+
+ if (offset + buf_size > bp->common.flash_size) {
+ DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
@@ -30165,7 +28076,7 @@
+ if ((bp->state == BNX2X_STATE_OPEN) ||
+ (bp->state == BNX2X_STATE_DISABLED)) {
+ rc |= bnx2x_link_reset(&bp->link_params,
-+ &bp->link_vars, 1);
++ &bp->link_vars);
+ rc |= bnx2x_phy_init(&bp->link_params,
+ &bp->link_vars);
+ }
@@ -30255,8 +28166,7 @@
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
-+ epause->autoneg = (bp->link_params.req_flow_ctrl ==
-+ BNX2X_FLOW_CTRL_AUTO) &&
++ epause->autoneg = (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
+ (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
+
+ epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
@@ -30388,7 +28298,8 @@
+ { "nvram_test (online)" },
+ { "interrupt_test (online)" },
+ { "link_test (online)" },
-+ { "idle check (online)" }
++ { "idle check (online)" },
++ { "MC errors (online)" }
+};
+
+static int bnx2x_self_test_count(struct net_device *dev)
@@ -30576,23 +28487,23 @@
+ u16 len;
+ int rc = -ENODEV;
+
-+ /* check the loopback mode */
-+ switch (loopback_mode) {
-+ case BNX2X_PHY_LOOPBACK:
-+ if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
-+ return -EINVAL;
-+ break;
-+ case BNX2X_MAC_LOOPBACK:
++ if (loopback_mode == BNX2X_MAC_LOOPBACK) {
+ bp->link_params.loopback_mode = LOOPBACK_BMAC;
+ bnx2x_phy_init(&bp->link_params, &bp->link_vars);
-+ break;
-+ default:
++
++ } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
++ u16 cnt = 1000;
++ bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
++ bnx2x_phy_init(&bp->link_params, &bp->link_vars);
++ /* wait until link state is restored */
++ if (link_up)
++ while (cnt-- && bnx2x_test_link(&bp->link_params,
++ &bp->link_vars))
++ msleep(10);
++ } else
+ return -EINVAL;
-+ }
+
-+ /* prepare the loopback packet */
-+ pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
-+ bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
++ pkt_size = 1514;
+ skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+ if (!skb) {
+ rc = -ENOMEM;
@@ -30604,7 +28515,6 @@
+ for (i = ETH_HLEN; i < pkt_size; i++)
+ packet[i] = (unsigned char) (i & 0xff);
+
-+ /* send the loopback packet */
+ num_pkts = 0;
+ tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
+ rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
@@ -30629,10 +28539,12 @@
+
+ wmb();
+
-+ le16_add_cpu(&fp->hw_tx_prods->bds_prod, 1);
++ fp->hw_tx_prods->bds_prod =
++ cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + 1);
+ mb(); /* FW restriction: must not reorder writing nbd and packets */
-+ le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
-+ DOORBELL(bp, fp->index, 0);
++ fp->hw_tx_prods->packets_prod =
++ cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
++ DOORBELL(bp, FP_IDX(fp), 0);
+
+ mmiowb();
+
@@ -30688,7 +28600,7 @@
+
+static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
+{
-+ int rc = 0, res;
++ int rc = 0;
+
+ if (!netif_running(bp->dev))
+ return BNX2X_LOOPBACK_FAILED;
@@ -30696,16 +28608,14 @@
+ bnx2x_netif_stop(bp, 1);
+ bnx2x_acquire_phy_lock(bp);
+
-+ res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
-+ if (res) {
-+ DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
-+ rc |= BNX2X_PHY_LOOPBACK_FAILED;
++ if (bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up)) {
++ DP(NETIF_MSG_PROBE, "MAC loopback failed\n");
++ rc |= BNX2X_MAC_LOOPBACK_FAILED;
+ }
+
-+ res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
-+ if (res) {
-+ DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
-+ rc |= BNX2X_MAC_LOOPBACK_FAILED;
++ if (bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up)) {
++ DP(NETIF_MSG_PROBE, "PHY loopback failed\n");
++ rc |= BNX2X_PHY_LOOPBACK_FAILED;
+ }
+
+ bnx2x_release_phy_lock(bp);
@@ -30732,14 +28642,14 @@
+ { 0x778, 0x70 },
+ { 0, 0 }
+ };
-+ __be32 buf[0x350 / 4];
++ u32 buf[0x350 / 4];
+ u8 *data = (u8 *)buf;
+ int i, rc;
+ u32 magic, csum;
+
+ rc = bnx2x_nvram_read(bp, 0, data, 4);
+ if (rc) {
-+ DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
++ DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc);
+ goto test_nvram_exit;
+ }
+
@@ -30756,7 +28666,7 @@
+ nvram_tbl[i].size);
+ if (rc) {
+ DP(NETIF_MSG_PROBE,
-+ "nvram_tbl[%d] read data (rc %d)\n", i, rc);
++ "nvram_tbl[%d] read data (rc -%d)\n", i, -rc);
+ goto test_nvram_exit;
+ }
+
@@ -30786,7 +28696,7 @@
+ config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
+ else
+ config->hdr.offset = BP_FUNC(bp);
-+ config->hdr.client_id = bp->fp->cl_id;
++ config->hdr.client_id = BP_CL_ID(bp);
+ config->hdr.reserved1 = 0;
+
+ rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
@@ -30859,6 +28769,9 @@
+ buf[5] = 1;
+ etest->flags |= ETH_TEST_FL_FAILED;
+ }
++ buf[7] = bnx2x_mc_assert(bp);
++ if (buf[7] != 0)
++ etest->flags |= ETH_TEST_FL_FAILED;
+
+#ifdef BNX2X_EXTRA_DEBUG
+ bnx2x_panic_dump(bp);
@@ -31070,8 +28983,6 @@
+ .get_settings = bnx2x_get_settings,
+ .set_settings = bnx2x_set_settings,
+ .get_drvinfo = bnx2x_get_drvinfo,
-+ .get_regs_len = bnx2x_get_regs_len,
-+ .get_regs = bnx2x_get_regs,
+ .get_wol = bnx2x_get_wol,
+ .set_wol = bnx2x_set_wol,
+ .get_msglevel = bnx2x_get_msglevel,
@@ -31184,41 +29095,25 @@
+ bnx2x_update_fpsb_idx(fp);
+
+ if (bnx2x_has_tx_work(fp))
-+ bnx2x_tx_int(fp);
++ bnx2x_tx_int(fp, budget);
+
-+ if (bnx2x_has_rx_work(fp)) {
++ if (bnx2x_has_rx_work(fp))
+ work_done = bnx2x_rx_int(fp, budget);
++ rmb(); /* BNX2X_HAS_WORK() reads the status block */
+
-+ /* must not complete if we consumed full budget */
-+ if (work_done >= budget)
-+ goto poll_again;
-+ }
-+
-+ /* BNX2X_HAS_WORK() reads the status block, thus we need to
-+ * ensure that status block indices have been actually read
-+ * (bnx2x_update_fpsb_idx) prior to this check (BNX2X_HAS_WORK)
-+ * so that we won't write the "newer" value of the status block to IGU
-+ * (if there was a DMA right after BNX2X_HAS_WORK and
-+ * if there is no rmb, the memory reading (bnx2x_update_fpsb_idx)
-+ * may be postponed to right before bnx2x_ack_sb). In this case
-+ * there will never be another interrupt until there is another update
-+ * of the status block, while there is still unhandled work.
-+ */
-+ rmb();
++ /* must not complete if we consumed full budget */
++ if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) {
+
-+ if (!BNX2X_HAS_WORK(fp)) {
+#ifdef BNX2X_STOP_ON_ERROR
+poll_panic:
+#endif
+ netif_rx_complete(bp->dev, napi);
+
-+ bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
++ bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID,
+ le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
-+ bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
++ bnx2x_ack_sb(bp, FP_SB_ID(fp), CSTORM_ID,
+ le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
+ }
-+
-+poll_again:
+ return work_done;
+}
+
@@ -31294,7 +29189,7 @@
+ rc = XMIT_PLAIN;
+
+ else {
-+ if (skb->protocol == htons(ETH_P_IPV6)) {
++ if (skb->protocol == ntohs(ETH_P_IPV6)) {
+ rc = XMIT_CSUM_V6;
+ if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
+ rc |= XMIT_CSUM_TCP;
@@ -31316,9 +29211,7 @@
+}
+
+#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
-+/* check if packet requires linearization (packet is too fragmented)
-+ no need to check fragmentation if page size > 8K (there will be no
-+ violation to FW restrictions) */
++/* check if packet requires linearization (packet is too fragmented) */
+static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
+ u32 xmit_type)
+{
@@ -31377,6 +29270,7 @@
+ wnd_sum -=
+ skb_shinfo(skb)->frags[wnd_idx].size;
+ }
++
+ } else {
+ /* in non-LSO too fragmented packet should always
+ be linearized */
@@ -31436,9 +29330,8 @@
+ ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
+
+#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
-+ /* First, check if we need to linearize the skb (due to FW
-+ restrictions). No need to check fragmentation if page size > 8K
-+ (there will be no violation to FW restrictions) */
++ /* First, check if we need to linearize the skb
++ (due to FW restrictions) */
+ if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
+ /* Statistics of linearization */
+ bp->lin_cnt++;
@@ -31503,9 +29396,9 @@
+ hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
+
+ /* for now NS flag is not used in Linux */
-+ pbd->global_data =
-+ (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
-+ ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
++ pbd->global_data = (hlen |
++ ((skb->protocol == ntohs(ETH_P_8021Q)) <<
++ ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
+
+ pbd->ip_hlen = (skb_transport_header(skb) -
+ skb_network_header(skb)) / 2;
@@ -31649,10 +29542,12 @@
+ */
+ wmb();
+
-+ le16_add_cpu(&fp->hw_tx_prods->bds_prod, nbd);
++ fp->hw_tx_prods->bds_prod =
++ cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd);
+ mb(); /* FW restriction: must not reorder writing nbd and packets */
-+ le32_add_cpu(&fp->hw_tx_prods->packets_prod, 1);
-+ DOORBELL(bp, fp->index, 0);
++ fp->hw_tx_prods->packets_prod =
++ cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
++ DOORBELL(bp, FP_IDX(fp), 0);
+
+ mmiowb();
+
@@ -31699,7 +29594,7 @@
+ return 0;
+}
+
-+/* called with netif_tx_lock from dev_mcast.c */
++/* called with netif_tx_lock from set_multicast */
+static void bnx2x_set_rx_mode(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
@@ -31799,11 +29694,8 @@
+ mclist && (i < dev->mc_count);
+ i++, mclist = mclist->next) {
+
-+ DP(NETIF_MSG_IFUP, "Adding mcast MAC: "
-+ "%02x:%02x:%02x:%02x:%02x:%02x\n",
-+ mclist->dmi_addr[0], mclist->dmi_addr[1],
-+ mclist->dmi_addr[2], mclist->dmi_addr[3],
-+ mclist->dmi_addr[4], mclist->dmi_addr[5]);
++ DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
++ mclist->dmi_addr);
+
+ crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
+ bit = (crc >> 24) & 0xff;
@@ -32151,7 +30043,6 @@
+ struct net_device *dev = NULL;
+ struct bnx2x *bp;
+ int rc;
-+ DECLARE_MAC_BUF(mac);
+
+ if (version_printed++ == 0)
+ printk(KERN_INFO "%s", version);
@@ -32184,14 +30075,14 @@
+ goto init_one_exit;
+ }
+
++ bp->common.name = board_info[ent->driver_data].name;
+ printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
-+ " IRQ %d, ", dev->name, board_info[ent->driver_data].name,
++ " IRQ %d, ", dev->name, bp->common.name,
+ (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
+ bnx2x_get_pcie_width(bp),
+ (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
+ dev->base_addr, bp->pdev->irq);
-+ printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr));
-+
++ printk(KERN_CONT "node addr %pM\n", dev->dev_addr);
+ return 0;
+
+init_one_exit:
@@ -32456,8 +30347,8 @@
+
+static struct pci_error_handlers bnx2x_err_handler = {
+ .error_detected = bnx2x_io_error_detected,
-+ .slot_reset = bnx2x_io_slot_reset,
-+ .resume = bnx2x_io_resume,
++ .slot_reset = bnx2x_io_slot_reset,
++ .resume = bnx2x_io_resume,
+};
+
+static struct pci_driver bnx2x_pci_driver = {
@@ -32491,9 +30382,10 @@
+module_init(bnx2x_init);
+module_exit(bnx2x_cleanup);
+
-diff -urpN a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
---- a/drivers/net/bnx2x_reg.h 2008-07-13 15:51:29.000000000 -0600
-+++ b/drivers/net/bnx2x_reg.h 2009-05-28 01:52:09.000000000 -0600
+diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
+index 5a1aa0b..fc957fa 100644
+--- a/drivers/net/bnx2x_reg.h
++++ b/drivers/net/bnx2x_reg.h
@@ -1,12 +1,12 @@
/* bnx2x_reg.h: Broadcom Everest network driver.
*
@@ -33279,33 +31171,10 @@
/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
these bits is written as a '1'; the corresponding SPIO bit will turn off
it's drivers and become an input. This is the reset state of all GPIO
-@@ -1240,6 +1425,41 @@
+@@ -1240,6 +1425,18 @@
This is the result value of the pin; not the drive value. Writing these
bits will have not effect. */
#define MISC_REG_GPIO 0xa490
-+/* [RW 8] These bits enable the GPIO_INTs to signals event to the
-+ IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
-+ p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
-+ [7] p1_gpio_3; */
-+#define MISC_REG_GPIO_EVENT_EN 0xa2bc
-+/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
-+ '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
-+ This will acknowledge an interrupt on the falling edge of corresponding
-+ GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
-+ Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
-+ register. This will acknowledge an interrupt on the rising edge of
-+ corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
-+ OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
-+ value. When the ~INT_STATE bit is set; this bit indicates the OLD value
-+ of the pin such that if ~INT_STATE is set and this bit is '0'; then the
-+ interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
-+ is '1'; then the interrupt is due to a high to low edge (reset value 0).
-+ [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
-+ current GPIO interrupt state for each GPIO pin. This bit is cleared when
-+ the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
-+ set when the GPIO input does not match the current value in #OLD_VALUE
-+ (reset value 0). */
-+#define MISC_REG_GPIO_INT 0xa494
+/* [R 28] this field hold the last information that caused reserved
+ attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ [27:24] the master that caused the attention - according to the following
@@ -33321,7 +31190,7 @@
/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
access that does not finish within
~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
-@@ -1282,6 +1502,11 @@
+@@ -1282,6 +1479,11 @@
#define MISC_REG_MISC_PRTY_MASK 0xa398
/* [R 1] Parity register #0 read */
#define MISC_REG_MISC_PRTY_STS 0xa38c
@@ -33333,7 +31202,7 @@
/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
-@@ -1303,7 +1528,7 @@
+@@ -1303,7 +1505,7 @@
#define MISC_REG_PLL_STORM_CTRL_2 0xa298
#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
@@ -33342,7 +31211,7 @@
write/read zero = the specific block is in reset; addr 0-wr- the write
value will be written to the register; addr 1-set - one will be written
to all the bits that have the value of one in the data written (bits that
-@@ -1311,14 +1536,12 @@
+@@ -1311,14 +1513,12 @@
written to all the bits that have the value of one in the data written
(bits that have the value of zero will not be change); addr 3-ignore;
read ignore from all addr except addr 00; inside order of the bits is:
@@ -33363,7 +31232,7 @@
#define MISC_REG_RESET_REG_2 0xa590
/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
shared with the driver resides */
-@@ -1345,7 +1568,7 @@
+@@ -1345,7 +1545,7 @@
select VAUX supply. (This is an output pin only; it is not controlled by
the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
field is not applicable for this pin; only the VALUE fields is relevant -
@@ -33372,7 +31241,7 @@
Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
device ID select; read by UMP firmware. */
#define MISC_REG_SPIO 0xa4fc
-@@ -1369,6 +1592,14 @@
+@@ -1369,6 +1569,14 @@
command bit is written. This bit is set when the SPIO input does not
match the current value in #OLD_VALUE (reset value 0). */
#define MISC_REG_SPIO_INT 0xa500
@@ -33387,7 +31256,7 @@
/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
loaded; 0-prepare; -unprepare */
#define MISC_REG_UNPREPARED 0xa424
-@@ -1394,8 +1625,9 @@
+@@ -1394,8 +1602,9 @@
#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
/* [RW 1] output enable for RX BRB1 LP IF */
#define NIG_REG_BRB_LB_OUT_EN 0x10100
@@ -33399,7 +31268,7 @@
#define NIG_REG_DEBUG_PACKET_LB 0x10800
/* [RW 1] Input enable for TX Debug packet */
#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
-@@ -1409,6 +1641,8 @@
+@@ -1409,6 +1618,8 @@
/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
to emac for port0; other way to bmac for port0 */
#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
@@ -33408,7 +31277,7 @@
/* [RW 1] Input enable for TX PBF user packet port0 IF */
#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
/* [RW 1] Input enable for TX PBF user packet port1 IF */
-@@ -1438,6 +1672,8 @@
+@@ -1438,6 +1649,8 @@
#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
/* [RW 1] led 10g for port 0 */
#define NIG_REG_LED_10G_P0 0x10320
@@ -33417,7 +31286,7 @@
/* [RW 1] Port0: This bit is set to enable the use of the
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
defined below. If this bit is cleared; then the blink rate will be about
-@@ -1448,7 +1684,7 @@
+@@ -1448,7 +1661,7 @@
is reset to 0x080; giving a default blink period of approximately 8Hz. */
#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
/* [RW 1] Port0: If set along with the
@@ -33426,7 +31295,7 @@
bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
bit; the Traffic LED will blink with the blink rate specified in
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
-@@ -1470,19 +1706,48 @@
+@@ -1470,19 +1683,48 @@
/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
9-11PHY7; 12 MAC4; 13-15 PHY10; */
#define NIG_REG_LED_MODE_P0 0x102f0
@@ -33475,7 +31344,7 @@
/* [RW 32] cm header for llh1 */
#define NIG_REG_LLH1_CM_HEADER 0x10080
#define NIG_REG_LLH1_ERROR_MASK 0x10090
-@@ -1491,13 +1756,26 @@
+@@ -1491,13 +1733,26 @@
/* [RW 8] init credit counter for port1 in LLH */
#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
#define NIG_REG_LLH1_XCM_MASK 0x10134
@@ -33502,18 +31371,7 @@
/* [RW 1] Input enable for RX PBF LP IF */
#define NIG_REG_PBF_LB_IN_EN 0x100b4
/* [RW 1] Value of this register will be transmitted to port swap when
-@@ -1507,6 +1785,10 @@
- #define NIG_REG_PRS_EOP_OUT_EN 0x10104
- /* [RW 1] Input enable for RX parser request IF */
- #define NIG_REG_PRS_REQ_IN_EN 0x100b8
-+/* [RW 5] control to serdes - CL45 DEVAD */
-+#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
-+/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
-+#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
- /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
- #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
- /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
-@@ -1514,9 +1796,24 @@
+@@ -1514,9 +1769,24 @@
/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
for port0 */
#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
@@ -33538,7 +31396,7 @@
/* [WB_R 64] Rx statistics : User octets received for LP */
#define NIG_REG_STAT2_BRB_OCTET 0x107e0
#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
-@@ -1529,8 +1826,12 @@
+@@ -1529,8 +1799,12 @@
#define NIG_REG_XCM0_OUT_EN 0x100f0
/* [RW 1] output enable for RX_XCM1 IF */
#define NIG_REG_XCM1_OUT_EN 0x100f4
@@ -33551,7 +31409,7 @@
/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
-@@ -1626,7 +1927,6 @@
+@@ -1626,7 +1900,6 @@
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
/* [RW 24] CID for port 0 if no match */
#define PRS_REG_CID_PORT_0 0x400fc
@@ -33559,7 +31417,7 @@
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is reset and packet type is 0. Used in packet start message
to TCM. */
-@@ -1635,6 +1935,7 @@
+@@ -1635,6 +1908,7 @@
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
@@ -33567,7 +31425,7 @@
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is set and packet type is 0. Used in packet start message
to TCM. */
-@@ -1643,6 +1944,7 @@
+@@ -1643,6 +1917,7 @@
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
@@ -33575,7 +31433,7 @@
/* [RW 32] The CM header for a match and packet type 1 for loopback port.
Used in packet start message to TCM. */
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
-@@ -1658,11 +1960,15 @@
+@@ -1658,11 +1933,15 @@
#define PRS_REG_CM_HDR_TYPE_4 0x40088
/* [RW 32] The CM header in case there was not a match on the connection */
#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
@@ -33591,7 +31449,7 @@
/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
load request message. */
#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
-@@ -1730,8 +2036,17 @@
+@@ -1730,8 +2009,17 @@
#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
/* [R 7] Debug only: Number of used entries in the header FIFO */
#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
@@ -33609,23 +31467,7 @@
/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
its[15:0]-address */
#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
-@@ -1772,11 +2087,23 @@
- #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
- #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
- #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
-+/* [RW 3] this field allows one function to pretend being another function
-+ when accessing any BAR mapped resource within the device. the value of
-+ the field is the number of the function that will be accessed
-+ effectively. after software write to this bit it must read it in order to
-+ know that the new value is updated */
-+#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
-+#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
-+#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
-+#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
-+#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
-+#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
-+#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
-+#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
+@@ -1775,8 +2063,7 @@
/* [R 1] this bit indicates that a read request was blocked because of
bus_master_en was deasserted */
#define PXP2_REG_PGL_READ_BLOCKED 0x120568
@@ -33635,7 +31477,7 @@
/* [R 18] debug only */
#define PXP2_REG_PGL_TXW_CDTS 0x12052c
/* [R 1] this bit indicates that a write request was blocked because of
-@@ -1828,12 +2155,14 @@
+@@ -1828,12 +2115,14 @@
#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
@@ -33656,7 +31498,7 @@
/* [RW 32] Parity mask register #0 read/write */
#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
-@@ -2016,8 +2345,12 @@
+@@ -2016,8 +2305,12 @@
#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
/* [RW 7] Bandwidth upper bound for VQ30 */
#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
@@ -33669,7 +31511,7 @@
/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
-128k */
#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
-@@ -2029,18 +2362,30 @@
+@@ -2029,18 +2322,30 @@
/* [RW 1] When '1'; requests will enter input buffers but wont get out
towards the glue */
#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
@@ -33701,7 +31543,7 @@
#define PXP2_REG_RQ_RBC_DONE 0x1201b0
/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
-@@ -2050,16 +2395,22 @@
+@@ -2050,16 +2355,22 @@
#define PXP2_REG_RQ_RD_MBS1 0x120168
/* [RW 2] Endian mode for src */
#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
@@ -33724,7 +31566,7 @@
/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
-@@ -2130,19 +2481,63 @@
+@@ -2130,19 +2441,63 @@
/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
001:256B; 010: 512B; */
#define PXP2_REG_RQ_WR_MBS1 0x120164
@@ -33790,7 +31632,7 @@
/* [WB 160] Used for initialization of the inbound interrupts memory */
#define PXP_REG_HST_INBOUND_INT 0x103800
/* [RW 32] Interrupt mask register #0 read/write */
-@@ -2165,18 +2560,30 @@
+@@ -2165,18 +2520,30 @@
#define QM_REG_ACTCTRINITVAL_3 0x16804c
/* [RW 32] The base logical address (in bytes) of each physical queue. The
index I represents the physical queue number. The 12 lsbs are ignore and
@@ -33824,7 +31666,7 @@
/* [RW 16] The byte credit value that if above the QM is considered almost
full */
#define QM_REG_BYTECREDITAFULLTHR 0x168094
-@@ -2203,7 +2610,7 @@
+@@ -2203,7 +2570,7 @@
#define QM_REG_CMINTVOQMASK_6 0x16820c
#define QM_REG_CMINTVOQMASK_7 0x168210
/* [RW 20] The number of connections divided by 16 which dictates the size
@@ -33833,7 +31675,7 @@
#define QM_REG_CONNNUM_0 0x168020
/* [R 6] Keep the fill level of the fifo from write client 4 */
#define QM_REG_CQM_WRC_FIFOLVL 0x168018
-@@ -2216,74 +2623,179 @@
+@@ -2216,74 +2583,179 @@
bypass enable */
#define QM_REG_ENBYPVOQMASK 0x16823c
/* [RW 32] A bit mask per each physical queue. If a bit is set then the
@@ -34030,7 +31872,7 @@
#define QM_REG_QVOQIDX_32 0x168174
#define QM_REG_QVOQIDX_33 0x168178
#define QM_REG_QVOQIDX_34 0x16817c
-@@ -2328,17 +2840,79 @@
+@@ -2328,17 +2800,79 @@
#define QM_REG_QVOQIDX_61 0x1681e8
#define QM_REG_QVOQIDX_62 0x1681ec
#define QM_REG_QVOQIDX_63 0x1681f0
@@ -34114,7 +31956,7 @@
/* [RW 1] Initialization bit command */
#define QM_REG_SOFT_RESET 0x168428
/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
-@@ -2372,44 +2946,103 @@
+@@ -2372,44 +2906,103 @@
#define QM_REG_VOQINITCREDIT_4 0x168070
#define QM_REG_VOQINITCREDIT_5 0x168074
/* [RW 1] The port of which VOQ belongs */
@@ -34235,7 +32077,7 @@
/* [RW 32] Wrr weights */
#define QM_REG_WRRWEIGHTS_0 0x16880c
#define QM_REG_WRRWEIGHTS_1 0x168810
-@@ -2431,14 +3064,78 @@
+@@ -2431,14 +3024,78 @@
#define QM_REG_WRRWEIGHTS_15 0x168828
#define QM_REG_WRRWEIGHTS_15_SIZE 1
/* [RW 32] Wrr weights */
@@ -34314,7 +32156,7 @@
#define QM_REG_WRRWEIGHTS_4 0x168834
#define QM_REG_WRRWEIGHTS_5 0x168838
#define QM_REG_WRRWEIGHTS_6 0x16883c
-@@ -2447,6 +3144,70 @@
+@@ -2447,6 +3104,70 @@
#define QM_REG_WRRWEIGHTS_9 0x168848
/* [R 6] Keep the fill level of the fifo from write client 1 */
#define QM_REG_XQM_WRC_FIFOLVL 0x168000
@@ -34385,7 +32227,7 @@
#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-@@ -2455,6 +3216,22 @@
+@@ -2455,6 +3176,22 @@
#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
@@ -34408,7 +32250,7 @@
#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
-@@ -2463,6 +3240,70 @@
+@@ -2463,6 +3200,70 @@
#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
@@ -34479,7 +32321,7 @@
#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
-@@ -2471,18 +3312,98 @@
+@@ -2471,18 +3272,98 @@
#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
@@ -34580,7 +32422,7 @@
/* [RW 32] Wrr weights */
#define QM_REG_WRRWEIGHTS_0 0x16880c
#define QM_REG_WRRWEIGHTS_0_SIZE 1
-@@ -2531,20 +3452,77 @@
+@@ -2531,20 +3412,77 @@
/* [RW 32] Wrr weights */
#define QM_REG_WRRWEIGHTS_9 0x168848
#define QM_REG_WRRWEIGHTS_9_SIZE 1
@@ -34664,7 +32506,7 @@
#define SRC_REG_SRC_INT_STS 0x404ac
/* [RW 3] Parity mask register #0 read/write */
#define SRC_REG_SRC_PRTY_MASK 0x404c8
-@@ -2583,6 +3561,10 @@
+@@ -2583,6 +3521,10 @@
/* [RC 1] Message length mismatch (relative to last indication) at the In#9
interface. */
#define TCM_REG_CSEM_LENGTH_MIS 0x50174
@@ -34675,7 +32517,7 @@
/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
#define TCM_REG_ERR_EVNT_ID 0x500a0
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
-@@ -2626,6 +3608,7 @@
+@@ -2626,6 +3568,7 @@
#define TCM_REG_N_SM_CTX_LD_2 0x50058
#define TCM_REG_N_SM_CTX_LD_3 0x5005c
#define TCM_REG_N_SM_CTX_LD_4 0x50060
@@ -34683,7 +32525,7 @@
/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
-@@ -2637,11 +3620,14 @@
+@@ -2637,11 +3580,14 @@
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define TCM_REG_PBF_WEIGHT 0x500b4
@@ -34700,7 +32542,7 @@
/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
-@@ -2662,6 +3648,10 @@
+@@ -2662,6 +3608,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define TCM_REG_STORM_TCM_IFEN 0x50010
@@ -34711,7 +32553,7 @@
/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
-@@ -2670,6 +3660,8 @@
+@@ -2670,6 +3620,8 @@
#define TCM_REG_TCM_INT_MASK 0x501dc
/* [R 11] Interrupt register #0 read */
#define TCM_REG_TCM_INT_STS 0x501d0
@@ -34720,7 +32562,7 @@
/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
Is used to determine the number of the AG context REG-pairs written back;
-@@ -2695,10 +3687,22 @@
+@@ -2695,10 +3647,22 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define TCM_REG_TM_TCM_IFEN 0x5001c
@@ -34743,7 +32585,7 @@
/* [RW 28] The CM header value for QM request (primary). */
#define TCM_REG_TQM_TCM_HDR_P 0x50090
/* [RW 28] The CM header value for QM request (secondary). */
-@@ -2725,10 +3729,15 @@
+@@ -2725,10 +3689,15 @@
/* [RC 1] Message length mismatch (relative to last indication) at the In#8
interface. */
#define TCM_REG_USEM_LENGTH_MIS 0x50170
@@ -34759,7 +32601,7 @@
/* [R 6] Use to read the value of XX protection Free counter. */
#define TCM_REG_XX_FREE 0x50178
/* [RW 6] Initial value for the credit counter; responsible for fulfilling
-@@ -2773,6 +3782,7 @@
+@@ -2773,6 +3742,7 @@
#define TM_REG_EN_CL1_INPUT 0x16400c
/* [RW 1] Enable client2 input. */
#define TM_REG_EN_CL2_INPUT 0x164010
@@ -34767,7 +32609,7 @@
/* [RW 1] Enable real time counter. */
#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
/* [RW 1] Enable for Timers state machines. */
-@@ -2780,14 +3790,22 @@
+@@ -2780,14 +3750,22 @@
/* [RW 4] Load value for expiration credit cnt. CFC max number of
outstanding load requests for timers (expiration) context loading. */
#define TM_REG_EXP_CRDCNT_VAL 0x164238
@@ -34791,7 +32633,7 @@
/* [RW 6] Linear timer set_clear fifo threshold. */
#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
/* [RW 2] Load value for pci arbiter credit cnt. */
-@@ -2804,6 +3822,45 @@
+@@ -2804,6 +3782,45 @@
#define TM_REG_TM_INT_STS 0x1640f0
/* [RW 8] The event id for aggregated interrupt 0 */
#define TSDM_REG_AGG_INT_EVENT_0 0x42038
@@ -34837,7 +32679,7 @@
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
/* [RW 16] The maximum value of the competion counter #0 */
-@@ -2868,6 +3925,9 @@
+@@ -2868,6 +3885,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
@@ -34847,7 +32689,7 @@
/* [RW 11] Parity mask register #0 read/write */
#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
/* [R 11] Parity register #0 read */
-@@ -2908,9 +3968,8 @@
+@@ -2908,9 +3928,8 @@
#define TSEM_REG_ENABLE_OUT 0x1800a8
/* [RW 32] This address space contains all registers and memories that are
placed in SEM_FAST block. The SEM_FAST registers are described in
@@ -34859,7 +32701,7 @@
#define TSEM_REG_FAST_MEMORY 0x1a0000
/* [RW 1] Disables input messages from FIC0 May be updated during run_time
by the microcode */
-@@ -2993,6 +4052,9 @@
+@@ -2993,6 +4012,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define TSEM_REG_TSEM_INT_MASK_0 0x180100
#define TSEM_REG_TSEM_INT_MASK_1 0x180110
@@ -34869,7 +32711,7 @@
/* [RW 32] Parity mask register #0 read/write */
#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
-@@ -3043,6 +4105,10 @@
+@@ -3043,6 +4065,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the dorq interface is detected. */
#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
@@ -34880,7 +32722,7 @@
/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
#define UCM_REG_ERR_EVNT_ID 0xe00a4
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
-@@ -3088,12 +4154,15 @@
+@@ -3088,12 +4114,15 @@
#define UCM_REG_N_SM_CTX_LD_2 0xe005c
#define UCM_REG_N_SM_CTX_LD_3 0xe0060
#define UCM_REG_N_SM_CTX_LD_4 0xe0064
@@ -34898,7 +32740,7 @@
/* [RW 8] The Event ID for Timers formatting in case of stop done. */
#define UCM_REG_STOP_EVNT_ID 0xe00ac
/* [RC 1] Set when the message length mismatch (relative to last indication)
-@@ -3103,6 +4172,10 @@
+@@ -3103,6 +4132,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define UCM_REG_STORM_UCM_IFEN 0xe0010
@@ -34909,7 +32751,7 @@
/* [RW 4] Timers output initial credit. Max credit available - 15.Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 4 at start-up. */
-@@ -3113,6 +4186,10 @@
+@@ -3113,6 +4146,10 @@
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define UCM_REG_TM_UCM_IFEN 0xe001c
@@ -34920,7 +32762,7 @@
/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
-@@ -3132,6 +4209,8 @@
+@@ -3132,6 +4169,8 @@
#define UCM_REG_UCM_INT_MASK 0xe01d4
/* [R 11] Interrupt register #0 read */
#define UCM_REG_UCM_INT_STS 0xe01c8
@@ -34929,7 +32771,7 @@
/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
Is used to determine the number of the AG context REG-pairs written back;
-@@ -3163,6 +4242,10 @@
+@@ -3163,6 +4202,10 @@
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define UCM_REG_UQM_P_WEIGHT 0xe00cc
@@ -34940,7 +32782,7 @@
/* [RW 28] The CM header value for QM request (primary). */
#define UCM_REG_UQM_UCM_HDR_P 0xe0094
/* [RW 28] The CM header value for QM request (secondary). */
-@@ -3178,6 +4261,10 @@
+@@ -3178,6 +4221,10 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the SDM interface is detected. */
#define UCM_REG_USDM_LENGTH_MIS 0xe0158
@@ -34951,7 +32793,7 @@
/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
-@@ -3185,10 +4272,15 @@
+@@ -3185,10 +4232,15 @@
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the xsem interface isdetected. */
#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
@@ -34967,7 +32809,7 @@
/* [R 6] Use to read the XX protection Free counter. */
#define UCM_REG_XX_FREE 0xe016c
/* [RW 6] Initial value for the credit counter; responsible for fulfilling
-@@ -3218,6 +4310,22 @@
+@@ -3218,6 +4270,22 @@
#define USDM_REG_AGG_INT_EVENT_17 0xc407c
#define USDM_REG_AGG_INT_EVENT_18 0xc4080
#define USDM_REG_AGG_INT_EVENT_19 0xc4084
@@ -34990,7 +32832,7 @@
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */
#define USDM_REG_AGG_INT_MODE_0 0xc41b8
-@@ -3232,6 +4340,8 @@
+@@ -3232,6 +4300,8 @@
#define USDM_REG_AGG_INT_MODE_17 0xc41fc
#define USDM_REG_AGG_INT_MODE_18 0xc4200
#define USDM_REG_AGG_INT_MODE_19 0xc4204
@@ -34999,7 +32841,7 @@
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
/* [RW 16] The maximum value of the competion counter #0 */
-@@ -3298,6 +4408,9 @@
+@@ -3298,6 +4368,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define USDM_REG_USDM_INT_MASK_0 0xc42a0
#define USDM_REG_USDM_INT_MASK_1 0xc42b0
@@ -35009,7 +32851,7 @@
/* [RW 11] Parity mask register #0 read/write */
#define USDM_REG_USDM_PRTY_MASK 0xc42c0
/* [R 11] Parity register #0 read */
-@@ -3338,9 +4451,8 @@
+@@ -3338,9 +4411,8 @@
#define USEM_REG_ENABLE_OUT 0x3000a8
/* [RW 32] This address space contains all registers and memories that are
placed in SEM_FAST block. The SEM_FAST registers are described in
@@ -35021,7 +32863,7 @@
#define USEM_REG_FAST_MEMORY 0x320000
/* [RW 1] Disables input messages from FIC0 May be updated during run_time
by the microcode */
-@@ -3423,6 +4535,9 @@
+@@ -3423,6 +4495,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define USEM_REG_USEM_INT_MASK_0 0x300110
#define USEM_REG_USEM_INT_MASK_1 0x300120
@@ -35031,7 +32873,7 @@
/* [RW 32] Parity mask register #0 read/write */
#define USEM_REG_USEM_PRTY_MASK_0 0x300130
#define USEM_REG_USEM_PRTY_MASK_1 0x300140
-@@ -3477,6 +4592,10 @@
+@@ -3477,6 +4552,10 @@
/* [RC 1] Set at message length mismatch (relative to last indication) at
the dorq interface. */
#define XCM_REG_DORQ_LENGTH_MIS 0x20230
@@ -35042,7 +32884,7 @@
/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
#define XCM_REG_ERR_EVNT_ID 0x200b0
/* [RW 28] The CM erroneous header for QM and Timers formatting. */
-@@ -3491,11 +4610,8 @@
+@@ -3491,11 +4570,8 @@
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 64 at start-up. */
#define XCM_REG_FIC1_INIT_CRD 0x20410
@@ -35054,7 +32896,7 @@
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
-@@ -3518,6 +4634,10 @@
+@@ -3518,6 +4594,10 @@
/* [RC 1] Set at message length mismatch (relative to last indication) at
the nig0 interface. */
#define XCM_REG_NIG0_LENGTH_MIS 0x20238
@@ -35065,7 +32907,7 @@
/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
-@@ -3545,6 +4665,7 @@
+@@ -3545,6 +4625,7 @@
#define XCM_REG_N_SM_CTX_LD_2 0x20068
#define XCM_REG_N_SM_CTX_LD_3 0x2006c
#define XCM_REG_N_SM_CTX_LD_4 0x20070
@@ -35073,7 +32915,7 @@
/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
-@@ -3556,6 +4677,8 @@
+@@ -3556,6 +4637,8 @@
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_PBF_WEIGHT 0x200d0
@@ -35082,7 +32924,7 @@
/* [RW 8] The Event ID for Timers formatting in case of stop done. */
#define XCM_REG_STOP_EVNT_ID 0x200b8
/* [RC 1] Set at message length mismatch (relative to last indication) at
-@@ -3573,6 +4696,10 @@
+@@ -3573,6 +4656,10 @@
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 4 at start-up. */
#define XCM_REG_TM_INIT_CRD 0x2041c
@@ -35093,7 +32935,7 @@
/* [RW 28] The CM header for Timers expiration command. */
#define XCM_REG_TM_XCM_HDR 0x200a8
/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
-@@ -3603,53 +4730,17 @@
+@@ -3603,53 +4690,17 @@
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_USEM_WEIGHT 0x200c8
@@ -35147,7 +32989,7 @@
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
-@@ -3659,6 +4750,8 @@
+@@ -3659,6 +4710,8 @@
#define XCM_REG_XCM_INT_MASK 0x202b4
/* [R 14] Interrupt register #0 read */
#define XCM_REG_XCM_INT_STS 0x202a8
@@ -35156,7 +32998,7 @@
/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
Is used to determine the number of the AG context REG-pairs written back;
-@@ -3692,6 +4785,10 @@
+@@ -3692,6 +4745,10 @@
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define XCM_REG_XQM_P_WEIGHT 0x200e4
@@ -35167,7 +33009,7 @@
/* [RW 28] The CM header value for QM request (primary). */
#define XCM_REG_XQM_XCM_HDR_P 0x200a0
/* [RW 28] The CM header value for QM request (secondary). */
-@@ -3715,6 +4812,7 @@
+@@ -3715,6 +4772,7 @@
mechanism. The fields are: [5:0] - message length; 11:6] - message
pointer; 16:12] - next pointer. */
#define XCM_REG_XX_DESCR_TABLE 0x20480
@@ -35175,7 +33017,7 @@
/* [R 6] Used to read the XX protection Free counter. */
#define XCM_REG_XX_FREE 0x20240
/* [RW 6] Initial value for the credit counter; responsible for fulfilling
-@@ -3728,7 +4826,7 @@
+@@ -3728,7 +4786,7 @@
#define XCM_REG_XX_MSG_NUM 0x20428
/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
@@ -35184,7 +33026,7 @@
The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
header pointer. */
#define XCM_REG_XX_TABLE 0x20500
-@@ -3745,6 +4843,11 @@
+@@ -3745,6 +4803,11 @@
#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
#define XSDM_REG_AGG_INT_EVENT_18 0x166080
#define XSDM_REG_AGG_INT_EVENT_19 0x166084
@@ -35196,7 +33038,7 @@
#define XSDM_REG_AGG_INT_EVENT_2 0x166040
#define XSDM_REG_AGG_INT_EVENT_20 0x166088
#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
-@@ -3756,6 +4859,15 @@
+@@ -3756,6 +4819,15 @@
#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
@@ -35212,7 +33054,7 @@
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */
#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
-@@ -3832,6 +4944,9 @@
+@@ -3832,6 +4904,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
@@ -35222,7 +33064,7 @@
/* [RW 11] Parity mask register #0 read/write */
#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
/* [R 11] Parity register #0 read */
-@@ -3872,9 +4987,8 @@
+@@ -3872,9 +4947,8 @@
#define XSEM_REG_ENABLE_OUT 0x2800a8
/* [RW 32] This address space contains all registers and memories that are
placed in SEM_FAST block. The SEM_FAST registers are described in
@@ -35234,7 +33076,7 @@
#define XSEM_REG_FAST_MEMORY 0x2a0000
/* [RW 1] Disables input messages from FIC0 May be updated during run_time
by the microcode */
-@@ -3957,6 +5071,9 @@
+@@ -3957,6 +5031,9 @@
/* [RW 32] Interrupt mask register #0 read/write */
#define XSEM_REG_XSEM_INT_MASK_0 0x280110
#define XSEM_REG_XSEM_INT_MASK_1 0x280120
@@ -35244,7 +33086,7 @@
/* [RW 32] Parity mask register #0 read/write */
#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
-@@ -3993,10 +5110,14 @@
+@@ -3993,10 +5070,14 @@
#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
@@ -35261,7 +33103,7 @@
#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
-@@ -4005,14 +5126,12 @@
+@@ -4005,14 +5086,12 @@
#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
#define EMAC_MODE_25G_MODE (1L<<5)
@@ -35277,15 +33119,12 @@
#define EMAC_REG_EMAC_MAC_MATCH 0x10
#define EMAC_REG_EMAC_MDIO_COMM 0xac
#define EMAC_REG_EMAC_MDIO_MODE 0xb4
-@@ -4028,21 +5147,31 @@
- #define EMAC_RX_MODE_FLOW_EN (1L<<2)
- #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+@@ -4030,19 +5109,23 @@
#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
-+#define EMAC_RX_MODE_RESET (1L<<0)
#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+-#define EMAC_TX_MODE_RESET (1L<<0)
+#define EMAC_TX_MODE_FLOW_EN (1L<<4)
- #define EMAC_TX_MODE_RESET (1L<<0)
+#define MISC_REGISTERS_GPIO_0 0
#define MISC_REGISTERS_GPIO_1 1
#define MISC_REGISTERS_GPIO_2 2
@@ -35295,10 +33134,6 @@
#define MISC_REGISTERS_GPIO_FLOAT_POS 24
+#define MISC_REGISTERS_GPIO_HIGH 1
#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
-+#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
-+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
-+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
-+#define MISC_REGISTERS_GPIO_INT_SET_POS 16
+#define MISC_REGISTERS_GPIO_LOW 0
#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
@@ -35309,30 +33144,17 @@
#define MISC_REGISTERS_RESET_REG_1_SET 0x584
#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
-@@ -4075,9 +5204,12 @@
- #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
- #define MISC_REGISTERS_SPIO_SET_POS 8
+@@ -4077,7 +5160,9 @@
#define HW_LOCK_MAX_RESOURCE_VALUE 31
--#define HW_LOCK_RESOURCE_8072_MDIO 0
+ #define HW_LOCK_RESOURCE_8072_MDIO 0
#define HW_LOCK_RESOURCE_GPIO 1
-+#define HW_LOCK_RESOURCE_MDIO 0
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
#define HW_LOCK_RESOURCE_SPIO 2
+#define HW_LOCK_RESOURCE_UNDI 5
-+#define PRS_FLAG_OVERETH_IPV4 1
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
-@@ -4092,6 +5224,8 @@
- #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
- #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
- #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
-+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
-+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
- #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
- #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
- #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
-@@ -4127,7 +5261,7 @@
+@@ -4127,7 +5212,7 @@
#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
#define RESERVED_GENERAL_ATTENTION_BIT_0 0
@@ -35341,7 +33163,7 @@
#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
#define RESERVED_GENERAL_ATTENTION_BIT_6 6
-@@ -4156,6 +5290,17 @@
+@@ -4156,6 +5241,17 @@
/* mcp error attention bit */
#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
@@ -35359,7 +33181,7 @@
#define LATCHED_ATTN_RBCR 23
#define LATCHED_ATTN_RBCT 24
#define LATCHED_ATTN_RBCN 25
-@@ -4217,40 +5362,73 @@
+@@ -4217,40 +5313,73 @@
#define GRCBASE_MISC_AEU GRCBASE_MISC
@@ -35386,7 +33208,7 @@
+#define PCICFG_COMMAND_INT_DISABLE (1<<10)
+#define PCICFG_COMMAND_RESERVED (0x1f<<11)
+#define PCICFG_STATUS_OFFSET 0x06
-+#define PCICFG_REVESION_ID_OFFSET 0x08
++#define PCICFG_REVESION_ID 0x08
#define PCICFG_CACHE_LINE_SIZE 0x0c
#define PCICFG_LATENCY_TIMER 0x0d
-#define PCICFG_REVESION_ID 0x08
@@ -35442,7 +33264,7 @@
#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
-@@ -4267,11 +5445,11 @@
+@@ -4267,11 +5396,11 @@
#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
@@ -35459,7 +33281,7 @@
#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
-@@ -4288,46 +5466,44 @@
+@@ -4288,46 +5417,44 @@
#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
@@ -35508,11 +33330,6 @@
-#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
-#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
-#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
--
--#define PCI_PM_DATA_A (0x410)
--#define PCI_PM_DATA_B (0x414)
--#define PCI_ID_VAL1 (0x434)
--#define PCI_ID_VAL2 (0x438)
+#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
@@ -35536,11 +33353,15 @@
+#define PCI_PM_DATA_B 0x414
+#define PCI_ID_VAL1 0x434
+#define PCI_ID_VAL2 0x438
-+
+
+-#define PCI_PM_DATA_A (0x410)
+-#define PCI_PM_DATA_B (0x414)
+-#define PCI_ID_VAL1 (0x434)
+-#define PCI_ID_VAL2 (0x438)
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
-@@ -4336,7 +5512,7 @@
+@@ -4336,7 +5463,7 @@
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
#define MDIO_REG_BANK_CL73_IEEEB1 0x10
@@ -35549,7 +33370,7 @@
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
-@@ -4365,7 +5541,7 @@
+@@ -4365,7 +5492,7 @@
#define MDIO_REG_BANK_RX_ALL 0x80f0
#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
@@ -35558,50 +33379,7 @@
#define MDIO_REG_BANK_TX0 0x8060
#define MDIO_TX0_TX_DRIVER 0x17
-@@ -4379,6 +5555,42 @@
- #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
- #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
-
-+#define MDIO_REG_BANK_TX1 0x8070
-+#define MDIO_TX1_TX_DRIVER 0x17
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-+#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
-+
-+#define MDIO_REG_BANK_TX2 0x8080
-+#define MDIO_TX2_TX_DRIVER 0x17
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-+#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
-+
-+#define MDIO_REG_BANK_TX3 0x8090
-+#define MDIO_TX3_TX_DRIVER 0x17
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
-+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
-+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
-+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
-+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
-+#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
-+
- #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
- #define MDIO_BLOCK0_XGXS_CONTROL 0x10
-
-@@ -4392,213 +5604,307 @@
+@@ -4392,213 +5519,278 @@
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
@@ -35813,100 +33591,6 @@
-#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
-#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
-#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
--
--#define MDIO_REG_BANK_CL73_USERB0 0x8370
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
--#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
--
--#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
--#define MDIO_AER_BLOCK_AER_REG 0x1E
--
--#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
--#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
--#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
--#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
--#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
--#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
--#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
--#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
--#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
--#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
--#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
--#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
--#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
--#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
--#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
-- 0x0000
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
-- 0x0180
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
--#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
--
--
--#define EXT_PHY_AUTO_NEG_DEVAD 0x7
--#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
--#define EXT_PHY_OPT_WIS_DEVAD 0x2
--#define EXT_PHY_OPT_PCS_DEVAD 0x3
--#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
--#define EXT_PHY_OPT_CNTL 0x0
--#define EXT_PHY_OPT_CNTL2 0x7
--#define EXT_PHY_OPT_PMD_RX_SD 0xa
--#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
--#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
--#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
--#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
--#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
--#define EXT_PHY_OPT_LASI_CNTL 0x9002
--#define EXT_PHY_OPT_RX_ALARM 0x9003
--#define EXT_PHY_OPT_LASI_STATUS 0x9005
--#define EXT_PHY_OPT_PCS_STATUS 0x0020
--#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
--#define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
--#define EXT_PHY_OPT_AN_CL37_CL73 0x8370
--#define EXT_PHY_OPT_AN_CL37_FD 0xffe4
--#define EXT_PHY_OPT_AN_CL37_AN 0xffe0
--#define EXT_PHY_OPT_AN_ADV 0x11
--
--#define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
--#define EXT_PHY_KR_PCS_DEVAD 0x3
--#define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
--#define EXT_PHY_KR_CTRL 0x0000
--#define EXT_PHY_KR_STATUS 0x0001
--#define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
--#define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
--#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
--#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
--#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
--#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
--#define EXT_PHY_KR_LP_AUTO_NEG 0x0013
--#define EXT_PHY_KR_CTRL2 0x0007
--#define EXT_PHY_KR_PCS_STATUS 0x0020
--#define EXT_PHY_KR_PMD_CTRL 0x0096
--#define EXT_PHY_KR_LASI_CNTL 0x9002
--#define EXT_PHY_KR_LASI_STATUS 0x9005
--#define EXT_PHY_KR_MISC_CTRL1 0xca85
--#define EXT_PHY_KR_GEN_CTRL 0xca10
--#define EXT_PHY_KR_ROM_CODE 0xca19
--#define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
--#define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
@@ -35988,30 +33672,9 @@
+#define MDIO_PMA_REG_ROM_VER2 0xca1a
+#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
+#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
-+#define MDIO_PMA_REG_GEN_CTRL2 0xca1e
-+#define MDIO_PMA_REG_MISC_CTRL0 0xca23
-+#define MDIO_PMA_REG_LRM_MODE 0xca3f
+#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
+#define MDIO_PMA_REG_MISC_CTRL1 0xca85
+
-+#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000
-+#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c
-+#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000
-+#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004
-+#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
-+#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c
-+#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002
-+#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003
-+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
-+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
-+#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
-+#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
-+
-+
-+#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
-+#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
-+#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
-+
+#define MDIO_PMA_REG_7101_RESET 0xc000
+#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
+#define MDIO_PMA_REG_7101_VER1 0xc026
@@ -36040,13 +33703,14 @@
+#define MDIO_XS_DEVAD 0x4
+#define MDIO_XS_PLL_SEQUENCER 0x8000
+#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
-+
-+#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
-+#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
-+#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
-+#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
-+#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
-+
+
+-#define MDIO_REG_BANK_CL73_USERB0 0x8370
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
+-#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
+#define MDIO_AN_DEVAD 0x7
+/*ieee*/
+#define MDIO_AN_REG_CTRL 0x0000
@@ -36067,12 +33731,46 @@
+#define MDIO_AN_REG_CL37_AN 0xffe0
+#define MDIO_AN_REG_CL37_FC_LD 0xffe4
+#define MDIO_AN_REG_CL37_FC_LP 0xffe5
-+
-+#define MDIO_AN_REG_8073_2_5G 0x8329
-+
-+
+
+-#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
+-#define MDIO_AER_BLOCK_AER_REG 0x1E
+
+-#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
+-#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
+-#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
+-#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
+-#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
+-#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
+-#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
+-#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
+-#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
+-#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
+-#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
+-#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
+-#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
+-#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
+- 0x0000
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
+- 0x0180
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
+-#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
+#define IGU_FUNC_BASE 0x0400
-+
+
+#define IGU_ADDR_MSIX 0x0000
+#define IGU_ADDR_INT_ACK 0x0200
+#define IGU_ADDR_PROD_UPD 0x0201
@@ -36086,12 +33784,57 @@
+#define IGU_ADDR_MSI_ADDR_LO 0x0211
+#define IGU_ADDR_MSI_ADDR_HI 0x0212
+#define IGU_ADDR_MSI_DATA 0x0213
-+
+
+-#define EXT_PHY_AUTO_NEG_DEVAD 0x7
+-#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
+-#define EXT_PHY_OPT_WIS_DEVAD 0x2
+-#define EXT_PHY_OPT_PCS_DEVAD 0x3
+-#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
+-#define EXT_PHY_OPT_CNTL 0x0
+-#define EXT_PHY_OPT_CNTL2 0x7
+-#define EXT_PHY_OPT_PMD_RX_SD 0xa
+-#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
+-#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
+-#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
+-#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
+-#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
+-#define EXT_PHY_OPT_LASI_CNTL 0x9002
+-#define EXT_PHY_OPT_RX_ALARM 0x9003
+-#define EXT_PHY_OPT_LASI_STATUS 0x9005
+-#define EXT_PHY_OPT_PCS_STATUS 0x0020
+-#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
+-#define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
+-#define EXT_PHY_OPT_AN_CL37_CL73 0x8370
+-#define EXT_PHY_OPT_AN_CL37_FD 0xffe4
+-#define EXT_PHY_OPT_AN_CL37_AN 0xffe0
+-#define EXT_PHY_OPT_AN_ADV 0x11
+#define IGU_INT_ENABLE 0
+#define IGU_INT_DISABLE 1
+#define IGU_INT_NOP 2
+#define IGU_INT_NOP2 3
-+
+
+-#define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
+-#define EXT_PHY_KR_PCS_DEVAD 0x3
+-#define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
+-#define EXT_PHY_KR_CTRL 0x0000
+-#define EXT_PHY_KR_STATUS 0x0001
+-#define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
+-#define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
+-#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
+-#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
+-#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
+-#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
+-#define EXT_PHY_KR_LP_AUTO_NEG 0x0013
+-#define EXT_PHY_KR_CTRL2 0x0007
+-#define EXT_PHY_KR_PCS_STATUS 0x0020
+-#define EXT_PHY_KR_PMD_CTRL 0x0096
+-#define EXT_PHY_KR_LASI_CNTL 0x9002
+-#define EXT_PHY_KR_LASI_STATUS 0x9005
+-#define EXT_PHY_KR_MISC_CTRL1 0xca85
+-#define EXT_PHY_KR_GEN_CTRL 0xca10
+-#define EXT_PHY_KR_ROM_CODE 0xca19
+-#define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
+-#define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
+#define COMMAND_REG_INT_ACK 0x0
+#define COMMAND_REG_PROD_UPD 0x4
+#define COMMAND_REG_ATTN_BITS_UPD 0x8
@@ -36103,32 +33846,11 @@
-#define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a
-diff -urpN a/drivers/net/Kconfig b/drivers/net/Kconfig
---- a/drivers/net/Kconfig 2009-05-28 01:49:59.000000000 -0600
-+++ b/drivers/net/Kconfig 2009-05-28 01:52:09.000000000 -0600
-@@ -2588,6 +2588,7 @@ config BNX2X
- tristate "Broadcom NetXtremeII 10Gb support"
- depends on PCI
- select ZLIB_INFLATE
-+ select LIBCRC32C
- help
- This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
- To compile this driver as a module, choose M here: the module
-diff -urpN a/drivers/net/Makefile b/drivers/net/Makefile
---- a/drivers/net/Makefile 2009-05-28 01:49:53.000000000 -0600
-+++ b/drivers/net/Makefile 2009-05-28 01:52:09.000000000 -0600
-@@ -68,6 +68,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
- obj-$(CONFIG_TIGON3) += tg3.o
- obj-$(CONFIG_BNX2) += bnx2.o
- obj-$(CONFIG_BNX2X) += bnx2x.o
-+bnx2x-objs := bnx2x_main.o bnx2x_link.o
- spidernet-y += spider_net.o spider_net_ethtool.o
- obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
- obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
-diff -urpN a/include/linux/pci_ids.h b/include/linux/pci_ids.h
---- a/include/linux/pci_ids.h 2009-05-28 01:49:54.000000000 -0600
-+++ b/include/linux/pci_ids.h 2009-05-28 01:52:09.000000000 -0600
-@@ -1952,6 +1952,8 @@
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 6595382..14475f5 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1950,6 +1950,8 @@
#define PCI_DEVICE_ID_NX2_5708 0x164c
#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
#define PCI_DEVICE_ID_NX2_57710 0x164e
Modified: people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-Separated-FW-from-the-source.patch
==============================================================================
--- people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-Separated-FW-from-the-source.patch Fri Jul 24 22:11:45 2009 (r14003)
+++ people/dannf/lenny-bnx2x/debian/patches/features/all/bnx2x-Separated-FW-from-the-source.patch Sat Jul 25 00:06:07 2009 (r14004)
@@ -1,6 +1,6 @@
-diff -urpN a/drivers/net/bnx2x_fw_file_hdr.h b/drivers/net/bnx2x_fw_file_hdr.h
---- a/drivers/net/bnx2x_fw_file_hdr.h 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_fw_file_hdr.h 2009-05-28 01:30:04.095243262 -0600
+diff -urpN linux-source-2.6.26.orig/drivers/net/bnx2x_fw_file_hdr.h linux-source-2.6.26/drivers/net/bnx2x_fw_file_hdr.h
+--- linux-source-2.6.26.orig/drivers/net/bnx2x_fw_file_hdr.h 1969-12-31 17:00:00.000000000 -0700
++++ linux-source-2.6.26/drivers/net/bnx2x_fw_file_hdr.h 2009-07-24 16:42:53.000000000 -0600
@@ -0,0 +1,37 @@
+/* bnx2x_fw_file_hdr.h: FW binary file header structure.
+ *
@@ -39,10 +39,10 @@
+};
+
+#endif /* BNX2X_INIT_FILE_HDR_H */
-diff -urpN a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
---- a/drivers/net/bnx2x.h 2009-05-28 00:48:35.237455515 -0600
-+++ b/drivers/net/bnx2x.h 2009-05-28 01:30:04.095243262 -0600
-@@ -912,6 +912,21 @@ struct bnx2x {
+diff -urpN linux-source-2.6.26.orig/drivers/net/bnx2x.h linux-source-2.6.26/drivers/net/bnx2x.h
+--- linux-source-2.6.26.orig/drivers/net/bnx2x.h 2009-07-24 16:42:24.000000000 -0600
++++ linux-source-2.6.26/drivers/net/bnx2x.h 2009-07-24 16:42:53.000000000 -0600
+@@ -909,6 +909,21 @@ struct bnx2x {
int gunzip_outlen;
#define FW_BUF_SIZE 0x8000
@@ -64,14 +64,14 @@
};
-diff -urpN a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
---- a/drivers/net/bnx2x_init.h 2009-05-28 00:46:32.866808376 -0600
-+++ b/drivers/net/bnx2x_init.h 2009-05-28 01:30:04.095243262 -0600
+diff -urpN linux-source-2.6.26.orig/drivers/net/bnx2x_init.h linux-source-2.6.26/drivers/net/bnx2x_init.h
+--- linux-source-2.6.26.orig/drivers/net/bnx2x_init.h 2009-07-24 16:42:24.000000000 -0600
++++ linux-source-2.6.26/drivers/net/bnx2x_init.h 2009-07-24 16:43:18.000000000 -0600
@@ -1,4 +1,5 @@
/* bnx2x_init.h: Broadcom Everest network driver.
+ * Structures and macroes needed during the initialization.
*
- * Copyright (c) 2007-2009 Broadcom Corporation
+ * Copyright (c) 2007-2008 Broadcom Corporation
*
@@ -8,6 +9,7 @@
*
@@ -81,7 +81,7 @@
*/
#ifndef BNX2X_INIT_H
-@@ -45,33 +47,71 @@
+@@ -42,33 +44,71 @@
#define OP_WR_64 0x8 /* write 64 bit pattern */
#define OP_WB 0x9 /* copy a string using DMAE */
@@ -179,7 +179,7 @@
struct raw_op {
-@@ -118,292 +158,6 @@ union init_op {
+@@ -115,290 +155,6 @@ union init_op {
struct raw_op raw;
};
@@ -218,6 +218,7 @@
-
-static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
-{
+-#ifdef USE_DMAE
- int offset = 0;
-
- if (bp->dmae_ready) {
@@ -231,28 +232,28 @@
- addr + offset, len);
- } else
- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
+-#else
+- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
+-#endif
-}
-
-static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
-{
-- u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
-- u32 buf_len32 = buf_len / 4;
-- int i;
--
-- memset(bp->gunzip_buf, fill, buf_len);
--
-- for (i = 0; i < len; i += buf_len32) {
-- u32 cur_len = min(buf_len32, len - i);
--
-- bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
+- if ((len * 4) > FW_BUF_SIZE) {
+- BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
+- addr, len*4);
+- return;
- }
+- memset(bp->gunzip_buf, fill, len * 4);
+-
+- bnx2x_write_big_buf(bp, addr, len);
-}
-
-static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
- u32 len64)
-{
-- u32 buf_len32 = FW_BUF_SIZE / 4;
-- u32 len = len64 * 2;
+- u32 buf_len32 = FW_BUF_SIZE/4;
+- u32 len = len64*2;
- u64 data64 = 0;
- int i;
-
@@ -341,9 +342,6 @@
- rc = bnx2x_gunzip(bp, (u8 *)data, len);
- if (rc) {
- BNX2X_ERR("gunzip failed ! rc %d\n", rc);
--#ifdef __BIG_ENDIAN
-- kfree(temp);
--#endif
- return;
- }
- len = bp->gunzip_outlen;
@@ -472,7 +470,7 @@
/****************************************************************************
* PXP
****************************************************************************/
-@@ -567,111 +321,6 @@ static const struct arb_line write_arb_a
+@@ -562,111 +318,6 @@ static const struct arb_line write_arb_a
PXP2_REG_RQ_BW_WR_UBOUND30}
};
@@ -566,25 +564,25 @@
- REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
-
- if (CHIP_IS_E1H(bp)) {
-- val = ((w_order == 0) ? 2 : 3);
-- REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
-- REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
+- REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1);
+- REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1);
- REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
-- REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
+- REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1);
- }
-}
-
-
+-
/****************************************************************************
* CDU
-@@ -695,128 +344,12 @@ static void bnx2x_init_pxp(struct bnx2x
+ ****************************************************************************/
+@@ -689,128 +340,12 @@ static void bnx2x_init_pxp(struct bnx2x
(0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
@@ -716,9 +714,9 @@
};
#endif /* BNX2X_INIT_H */
-diff -urpN a/drivers/net/bnx2x_init_ops.h b/drivers/net/bnx2x_init_ops.h
---- a/drivers/net/bnx2x_init_ops.h 1969-12-31 17:00:00.000000000 -0700
-+++ b/drivers/net/bnx2x_init_ops.h 2009-05-28 01:30:04.099239409 -0600
+diff -urpN linux-source-2.6.26.orig/drivers/net/bnx2x_init_ops.h linux-source-2.6.26/drivers/net/bnx2x_init_ops.h
+--- linux-source-2.6.26.orig/drivers/net/bnx2x_init_ops.h 1969-12-31 17:00:00.000000000 -0700
++++ linux-source-2.6.26/drivers/net/bnx2x_init_ops.h 2009-07-24 16:42:53.000000000 -0600
@@ -0,0 +1,442 @@
+/* bnx2x_init_ops.h: Broadcom Everest network driver.
+ * Static functions needed during the initialization.
@@ -1162,18 +1160,17 @@
+}
+
+#endif /* BNX2X_INIT_OPS_H */
-diff -urpN a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
---- a/drivers/net/bnx2x_main.c 2009-05-28 01:24:45.898697237 -0600
-+++ b/drivers/net/bnx2x_main.c 2009-05-28 01:35:15.875529028 -0600
-@@ -54,12 +54,19 @@
-
+diff -urpN linux-source-2.6.26.orig/drivers/net/bnx2x_main.c linux-source-2.6.26/drivers/net/bnx2x_main.c
+--- linux-source-2.6.26.orig/drivers/net/bnx2x_main.c 2009-07-24 16:42:24.000000000 -0600
++++ linux-source-2.6.26/drivers/net/bnx2x_main.c 2009-07-24 16:42:53.000000000 -0600
+@@ -57,11 +57,18 @@
+ #include "bnx2x_link.h"
#include "bnx2x.h"
#include "bnx2x_init.h"
+#include "bnx2x_init_ops.h"
- #include "bnx2x_dump.h"
- #define DRV_MODULE_VERSION "1.48.105"
- #define DRV_MODULE_RELDATE "2009/03/02"
+ #define DRV_MODULE_VERSION "1.45.26"
+ #define DRV_MODULE_RELDATE "2009/01/26"
#define BNX2X_BC_VER 0x040200
+#include <linux/firmware.h>
@@ -1181,11 +1178,11 @@
+/* FW files */
+#define FW_FILE_PREFIX_E1 "bnx2x-e1-"
+#define FW_FILE_PREFIX_E1H "bnx2x-e1h-"
-+
++
/* Time in jiffies before concluding the transmitter is hung */
#define TX_TIMEOUT (5*HZ)
-@@ -4970,13 +4977,15 @@ static void bnx2x_gunzip_end(struct bnx2
+@@ -4904,13 +4911,15 @@ static void bnx2x_gunzip_end(struct bnx2
}
}
@@ -1203,7 +1200,7 @@
n = 10;
-@@ -4985,7 +4994,7 @@ static int bnx2x_gunzip(struct bnx2x *bp
+@@ -4919,7 +4928,7 @@ static int bnx2x_gunzip(struct bnx2x *bp
if (zbuf[3] & FNAME)
while ((zbuf[n++] != 0) && (n < len));
@@ -1212,7 +1209,7 @@
bp->strm->avail_in = len - n;
bp->strm->next_out = bp->gunzip_buf;
bp->strm->avail_out = FW_BUF_SIZE;
-@@ -5107,8 +5116,8 @@ static int bnx2x_int_mem_test(struct bnx
+@@ -5041,8 +5050,8 @@ static int bnx2x_int_mem_test(struct bnx
msleep(50);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
msleep(50);
@@ -1223,7 +1220,7 @@
DP(NETIF_MSG_HW, "part2\n");
-@@ -5172,8 +5181,8 @@ static int bnx2x_int_mem_test(struct bnx
+@@ -5106,8 +5115,8 @@ static int bnx2x_int_mem_test(struct bnx
msleep(50);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
msleep(50);
@@ -1234,7 +1231,7 @@
#ifndef BCM_ISCSI
/* set NIC mode */
REG_WR(bp, PRS_REG_NIC_MODE, 1);
-@@ -5248,7 +5257,7 @@ static int bnx2x_init_common(struct bnx2
+@@ -5182,7 +5191,7 @@ static int bnx2x_init_common(struct bnx2
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
@@ -1243,7 +1240,7 @@
if (CHIP_IS_E1H(bp))
REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
-@@ -5256,14 +5265,14 @@ static int bnx2x_init_common(struct bnx2
+@@ -5190,14 +5199,14 @@ static int bnx2x_init_common(struct bnx2
msleep(30);
REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
@@ -1260,7 +1257,7 @@
bnx2x_init_pxp(bp);
#ifdef __BIG_ENDIAN
-@@ -5307,39 +5316,39 @@ static int bnx2x_init_common(struct bnx2
+@@ -5241,39 +5250,39 @@ static int bnx2x_init_common(struct bnx2
REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
@@ -1309,7 +1306,7 @@
if (CHIP_REV_IS_SLOW(bp)) {
/* fix for emulation and FPGA for no pause */
REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
-@@ -5348,27 +5357,27 @@ static int bnx2x_init_common(struct bnx2
+@@ -5282,17 +5291,17 @@ static int bnx2x_init_common(struct bnx2
REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
}
@@ -1330,10 +1327,11 @@
+ bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
+ bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
- bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
- bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
+ if (CHIP_IS_E1H(bp)) {
+ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
+@@ -5326,10 +5335,10 @@ static int bnx2x_init_common(struct bnx2
+ STORM_INTMEM_SIZE_E1);
+ }
- bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
- bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
@@ -1346,7 +1344,7 @@
/* sync semi rtc */
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
-@@ -5376,16 +5385,16 @@ static int bnx2x_init_common(struct bnx2
+@@ -5337,16 +5346,16 @@ static int bnx2x_init_common(struct bnx2
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
0x80000000);
@@ -1367,7 +1365,7 @@
REG_WR(bp, SRC_REG_SOFT_RST, 0);
if (sizeof(union cdu_context) != 1024)
-@@ -5393,7 +5402,7 @@ static int bnx2x_init_common(struct bnx2
+@@ -5354,7 +5363,7 @@ static int bnx2x_init_common(struct bnx2
printk(KERN_ALERT PFX "please adjust the size of"
" cdu_context(%ld)\n", (long)sizeof(union cdu_context));
@@ -1376,7 +1374,7 @@
val = (4 << 24) + (0 << 12) + 1024;
REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
if (CHIP_IS_E1(bp)) {
-@@ -5402,7 +5411,7 @@ static int bnx2x_init_common(struct bnx2
+@@ -5363,7 +5372,7 @@ static int bnx2x_init_common(struct bnx2
REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
}
@@ -1385,7 +1383,7 @@
REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
/* enable context validation interrupt from CFC */
REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
-@@ -5410,20 +5419,25 @@ static int bnx2x_init_common(struct bnx2
+@@ -5371,20 +5380,25 @@ static int bnx2x_init_common(struct bnx2
/* set the thresholds to prevent CFC/CDU race */
REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
@@ -1414,7 +1412,7 @@
if (CHIP_IS_E1H(bp)) {
REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
-@@ -5507,6 +5521,7 @@ static int bnx2x_init_common(struct bnx2
+@@ -5463,6 +5477,7 @@ static int bnx2x_init_common(struct bnx2
static int bnx2x_init_port(struct bnx2x *bp)
{
int port = BP_PORT(bp);
@@ -1422,7 +1420,7 @@
u32 val;
DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
-@@ -5514,7 +5529,9 @@ static int bnx2x_init_port(struct bnx2x
+@@ -5470,7 +5485,9 @@ static int bnx2x_init_port(struct bnx2x
REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
/* Port PXP comes here */
@@ -1432,7 +1430,7 @@
#ifdef BCM_ISCSI
/* Port0 1
* Port1 385 */
-@@ -5541,39 +5558,40 @@ static int bnx2x_init_port(struct bnx2x
+@@ -5497,37 +5514,39 @@ static int bnx2x_init_port(struct bnx2x
REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
#endif
/* Port CMs come here */
@@ -1461,8 +1459,6 @@
/* Port USDM comes here */
+ bnx2x_init_block(bp, USDM_BLOCK, init_stage);
/* Port XSDM comes here */
-+ bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
-
- bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
- port ? TSEM_PORT1_END : TSEM_PORT0_END);
- bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
@@ -1471,11 +1467,12 @@
- port ? CSEM_PORT1_END : CSEM_PORT0_END);
- bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
- port ? XSEM_PORT1_END : XSEM_PORT0_END);
++ bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
++
+ bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, USEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
+ bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
-
/* Port UPB comes here */
+ bnx2x_init_block(bp, UPB_BLOCK, init_stage);
/* Port XPB comes here */
@@ -1487,7 +1484,7 @@
/* configure PBF to work without PAUSE mtu 9000 */
REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
-@@ -5603,18 +5621,17 @@ static int bnx2x_init_port(struct bnx2x
+@@ -5557,18 +5576,17 @@ static int bnx2x_init_port(struct bnx2x
/* Port SRCH comes here */
#endif
/* Port CDU comes here */
@@ -1510,7 +1507,7 @@
/* init aeu_mask_attn_func_0/1:
* - SF mode: bits 3-7 are masked. only bits 0-2 are in use
* - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
-@@ -5623,13 +5640,17 @@ static int bnx2x_init_port(struct bnx2x
+@@ -5577,12 +5595,17 @@ static int bnx2x_init_port(struct bnx2x
(IS_E1HMF(bp) ? 0xF7 : 0x7));
/* Port PXPCS comes here */
@@ -1522,15 +1519,15 @@
/* Port DBU comes here */
+ bnx2x_init_block(bp, DBU_BLOCK, init_stage);
/* Port DBG comes here */
-+ bnx2x_init_block(bp, DBG_BLOCK, init_stage);
-
- bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
- port ? NIG_PORT1_END : NIG_PORT0_END);
++ bnx2x_init_block(bp, DBG_BLOCK, init_stage);
++
+ bnx2x_init_block(bp, NIG_BLOCK, init_stage);
REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
-@@ -5641,7 +5662,9 @@ static int bnx2x_init_port(struct bnx2x
+@@ -5606,7 +5629,9 @@ static int bnx2x_init_port(struct bnx2x
}
/* Port MCP comes here */
@@ -1538,9 +1535,9 @@
/* Port DMAE comes here */
+ bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
- switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
- case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
-@@ -5739,7 +5762,7 @@ static int bnx2x_init_func(struct bnx2x
+ switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
+ case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
+@@ -5674,7 +5699,7 @@ static int bnx2x_init_func(struct bnx2x
if (CHIP_IS_E1H(bp)) {
for (i = 0; i < 9; i++)
bnx2x_init_block(bp,
@@ -1549,7 +1546,7 @@
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
-@@ -5752,7 +5775,7 @@ static int bnx2x_init_func(struct bnx2x
+@@ -5687,7 +5712,7 @@ static int bnx2x_init_func(struct bnx2x
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
}
@@ -1558,7 +1555,7 @@
/* Reset PCIE errors for debug */
REG_WR(bp, 0x2114, 0xffffffff);
-@@ -10588,6 +10611,190 @@ static int __devinit bnx2x_get_pcie_spee
+@@ -10312,6 +10337,190 @@ static int __devinit bnx2x_get_pcie_spee
val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
return val;
}
@@ -1749,7 +1746,7 @@
static int __devinit bnx2x_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
-@@ -10623,6 +10830,13 @@ static int __devinit bnx2x_init_one(stru
+@@ -10346,6 +10555,13 @@ static int __devinit bnx2x_init_one(stru
if (rc)
goto init_one_exit;
@@ -1763,7 +1760,7 @@
rc = register_netdev(dev);
if (rc) {
dev_err(&pdev->dev, "Cannot register net device\n");
-@@ -10670,6 +10884,11 @@ static void __devexit bnx2x_remove_one(s
+@@ -10393,6 +10609,11 @@ static void __devexit bnx2x_remove_one(s
unregister_netdev(dev);
@@ -1775,14 +1772,14 @@
if (bp->regview)
iounmap(bp->regview);
-@@ -10936,3 +11155,4 @@ static void __exit bnx2x_cleanup(void)
+@@ -10659,3 +10880,4 @@ static void __exit bnx2x_cleanup(void)
module_init(bnx2x_init);
module_exit(bnx2x_cleanup);
+
-diff -urpN a/drivers/net/Kconfig b/drivers/net/Kconfig
---- a/drivers/net/Kconfig 2009-05-27 20:04:50.748489687 -0600
-+++ b/drivers/net/Kconfig 2009-05-28 01:30:04.111240055 -0600
+diff -urpN linux-source-2.6.26.orig/drivers/net/Kconfig linux-source-2.6.26/drivers/net/Kconfig
+--- linux-source-2.6.26.orig/drivers/net/Kconfig 2009-07-24 16:42:24.000000000 -0600
++++ linux-source-2.6.26/drivers/net/Kconfig 2009-07-24 16:42:53.000000000 -0600
@@ -2587,6 +2587,7 @@ config TEHUTI
config BNX2X
tristate "Broadcom NetXtremeII 10Gb support"
Modified: people/dannf/lenny-bnx2x/debian/patches/series/15lenny2bnx2x
==============================================================================
--- people/dannf/lenny-bnx2x/debian/patches/series/15lenny2bnx2x Fri Jul 24 22:11:45 2009 (r14003)
+++ people/dannf/lenny-bnx2x/debian/patches/series/15lenny2bnx2x Sat Jul 25 00:06:07 2009 (r14004)
@@ -1,4 +1,3 @@
- debian/dfsg/drivers-net-bnx2x-disable.patch
+ features/all/bnx2x-2.6.30.patch
+ features/all/bnx2x-Separated-FW-from-the-source.patch
-+ features/all/bnx2x-driver-version-1.48.105-1.patch
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