[kernel] r16073 - in dists/sid/linux-2.6/debian/patches: bugfix/all series
Ben Hutchings
benh at alioth.debian.org
Tue Aug 3 03:11:38 UTC 2010
Author: benh
Date: Tue Aug 3 03:11:23 2010
New Revision: 16073
Log:
Apply ssb SPROM fixes properly
Added:
dists/sid/linux-2.6/debian/patches/bugfix/all/revert-ssb-Handle-Netbook-devices-where-the-SPROM-ad.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Look-for-SPROM-at-different-offset-on-higher-rev.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Use-relative-offsets-for-SPROM.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-do-not-read-SPROM-if-it-does-not-exist.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-fix-NULL-ptr-deref-when-pcihost_wrapper-is-used.patch
Modified:
dists/sid/linux-2.6/debian/patches/series/19
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/revert-ssb-Handle-Netbook-devices-where-the-SPROM-ad.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/revert-ssb-Handle-Netbook-devices-where-the-SPROM-ad.patch Tue Aug 3 03:11:23 2010 (r16073)
@@ -0,0 +1,239 @@
+From 103b72af07ce6c145640d7b190df900d9ae6a719 Mon Sep 17 00:00:00 2001
+From: Ben Hutchings <ben at decadent.org.uk>
+Date: Tue, 3 Aug 2010 03:23:19 +0100
+Subject: [PATCH 1/5] Revert "ssb: Handle Netbook devices where the SPROM address is changed"
+
+This reverts commit ea158563643b3c28c5dd3f286ab61aadddfd7b88.
+That commit combined incomplete changes from several upstream commits,
+which will now be applied properly.
+---
+ drivers/ssb/driver_chipcommon.c | 3 --
+ drivers/ssb/driver_chipcommon_pmu.c | 17 ++++++----
+ drivers/ssb/pci.c | 46 ++++-------------------------
+ drivers/ssb/sprom.c | 15 ---------
+ include/linux/ssb/ssb.h | 1 -
+ include/linux/ssb/ssb_driver_chipcommon.h | 2 -
+ include/linux/ssb/ssb_regs.h | 3 +-
+ 7 files changed, 17 insertions(+), 70 deletions(-)
+
+diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
+index bbf1cb2..9681536 100644
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,9 +233,6 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+ return; /* We don't have a ChipCommon */
+- if (cc->dev->id.revision >= 11)
+- cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+- ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
+ ssb_pmu_init(cc);
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
+index 8e194d5..64abd11 100644
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -495,9 +495,9 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
+ chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
+ }
+
+-/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
+ void ssb_pmu_init(struct ssb_chipcommon *cc)
+ {
++ struct ssb_bus *bus = cc->dev->bus;
+ u32 pmucap;
+
+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
+@@ -509,12 +509,15 @@ void ssb_pmu_init(struct ssb_chipcommon *cc)
+ ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
+ cc->pmu.rev, pmucap);
+
+- if (cc->pmu.rev == 1)
+- chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
+- ~SSB_CHIPCO_PMU_CTL_NOILPONW);
+- else
+- chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
+- SSB_CHIPCO_PMU_CTL_NOILPONW);
++ if (cc->pmu.rev >= 1) {
++ if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
++ chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
++ ~SSB_CHIPCO_PMU_CTL_NOILPONW);
++ } else {
++ chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
++ SSB_CHIPCO_PMU_CTL_NOILPONW);
++ }
++ }
+ ssb_pmu_pll_init(cc);
+ ssb_pmu_resources_init(cc);
+ }
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index 17a1781..9e50896 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -22,7 +22,6 @@
+
+ #include "ssb_private.h"
+
+-bool ssb_is_sprom_available(struct ssb_bus *bus);
+
+ /* Define the following to 1 to enable a printk on each coreswitch. */
+ #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
+@@ -168,7 +167,7 @@ err_pci:
+ }
+
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset) ((offset) / sizeof(u16))
++#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift) \
+ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+@@ -253,13 +252,8 @@ static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
+ {
+ int i;
+
+- /* Check if SPROM can be read */
+- if (ioread16(bus->mmio + bus->sprom_offset) == 0xFFFF) {
+- ssb_printk(KERN_ERR PFX "Unable to read SPROM\n");
+- return -ENODEV;
+- }
+ for (i = 0; i < bus->sprom_size; i++)
+- sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
++ sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
+
+ return 0;
+ }
+@@ -290,7 +284,7 @@ static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
+ ssb_printk("75%%");
+ else if (i % 2)
+ ssb_printk(".");
+- writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
++ writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
+ mmiowb();
+ msleep(20);
+ }
+@@ -626,49 +620,21 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ int err = -ENOMEM;
+ u16 *buf;
+
+- if (!ssb_is_sprom_available(bus)) {
+- ssb_printk(KERN_ERR PFX "No SPROM available!\n");
+- return -ENODEV;
+- }
+- if (bus->chipco.dev) { /* can be unavailible! */
+- /*
+- * get SPROM offset: SSB_SPROM_BASE1 except for
+- * chipcommon rev >= 31 or chip ID is 0x4312 and
+- * chipcommon status & 3 == 2
+- */
+- if (bus->chipco.dev->id.revision >= 31)
+- bus->sprom_offset = SSB_SPROM_BASE31;
+- else if (bus->chip_id == 0x4312 &&
+- (bus->chipco.status & 0x03) == 2)
+- bus->sprom_offset = SSB_SPROM_BASE31;
+- else
+- bus->sprom_offset = SSB_SPROM_BASE1;
+- } else {
+- bus->sprom_offset = SSB_SPROM_BASE1;
+- }
+- ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
+-
+ buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ if (!buf)
+ goto out;
+ bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
+- err = sprom_do_read(bus, buf);
+- if (err)
+- goto out_free;
++ sprom_do_read(bus, buf);
+ err = sprom_check_crc(buf, bus->sprom_size);
+ if (err) {
+ /* try for a 440 byte SPROM - revision 4 and higher */
+ kfree(buf);
+ buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
+ GFP_KERNEL);
+- if (!buf) {
+- err = -ENOMEM;
++ if (!buf)
+ goto out;
+- }
+ bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
+- err = sprom_do_read(bus, buf);
+- if (err)
+- goto out_free;
++ sprom_do_read(bus, buf);
+ err = sprom_check_crc(buf, bus->sprom_size);
+ if (err) {
+ /* All CRC attempts failed.
+diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
+index 5f7154d..eb70843 100644
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -179,18 +179,3 @@ const struct ssb_sprom *ssb_get_fallback_sprom(void)
+ {
+ return fallback_sprom;
+ }
+-
+-/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
+-bool ssb_is_sprom_available(struct ssb_bus *bus)
+-{
+- /* status register only exists on chipcomon rev >= 11 and we need check
+- for >= 31 only */
+- /* this routine differs from specs as we do not access SPROM directly
+- on PCMCIA */
+- if (bus->bustype == SSB_BUSTYPE_PCI &&
+- bus->chipco.dev && /* can be unavailible! */
+- bus->chipco.dev->id.revision >= 31)
+- return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
+-
+- return true;
+-}
+diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
+index a28c37d..3d0a9ff 100644
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -302,7 +302,6 @@ struct ssb_bus {
+ u16 chip_id;
+ u16 chip_rev;
+ u16 sprom_size; /* number of words in sprom */
+- u16 sprom_offset;
+ u8 chip_package;
+
+ /* List of devices (cores) on the backplane. */
+diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
+index 7600f38..4e27acf 100644
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -46,7 +46,6 @@
+ #define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
+ #define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */
+ #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
+-#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
+ #define SSB_CHIPCO_CAP_OTPS_SHIFT 19
+ #define SSB_CHIPCO_CAP_OTPS_BASE 5
+ #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
+@@ -565,7 +564,6 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ struct ssb_device *dev;
+ u32 capabilities;
+- u32 status;
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct ssb_chipcommon_pmu pmu;
+diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
+index b8be23c..9ae9082 100644
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -170,8 +170,7 @@
+ #define SSB_SPROMSIZE_WORDS_R4 220
+ #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE1 0x1000
+-#define SSB_SPROM_BASE31 0x0800
++#define SSB_SPROM_BASE 0x1000
+ #define SSB_SPROM_REVISION 0x107E
+ #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
+ #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Look-for-SPROM-at-different-offset-on-higher-rev.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Look-for-SPROM-at-different-offset-on-higher-rev.patch Tue Aug 3 03:11:23 2010 (r16073)
@@ -0,0 +1,93 @@
+From 74f79d2cd0da49323da94381abc582dfb3bdbece Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5 at gmail.com>
+Date: Wed, 31 Mar 2010 21:59:21 +0200
+Subject: [PATCH 3/5] ssb: Look for SPROM at different offset on higher rev CC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit ea2db495f92ad2cf3301623e60cb95b4062bc484 upstream.
+
+Our offset handling becomes even a little more hackish now. For some reason I
+do not understand all offsets as inrelative. It assumes base offset is 0x1000
+but it will work for now as we make offsets relative anyway by removing base
+0x1000. Should be cleaner however.
+
+Signed-off-by: Rafał Miłecki <zajec5 at gmail.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+ drivers/ssb/pci.c | 9 ++++++---
+ include/linux/ssb/ssb.h | 1 +
+ include/linux/ssb/ssb_regs.h | 3 ++-
+ 3 files changed, 9 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index a4b2b99..5bb1278 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -167,7 +167,7 @@ err_pci:
+ }
+
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
++#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift) \
+ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+@@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
+ int i;
+
+ for (i = 0; i < bus->sprom_size; i++)
+- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
++ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
+
+ return 0;
+ }
+@@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
+ ssb_printk("75%%");
+ else if (i % 2)
+ ssb_printk(".");
+- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
++ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ mmiowb();
+ msleep(20);
+ }
+@@ -625,6 +625,9 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ return -ENODEV;
+ }
+
++ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++
+ buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ if (!buf)
+ goto out;
+diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
+index 38bac23..3cbf483 100644
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -301,6 +301,7 @@ struct ssb_bus {
+ /* ID information about the Chip. */
+ u16 chip_id;
+ u16 chip_rev;
++ u16 sprom_offset;
+ u16 sprom_size; /* number of words in sprom */
+ u8 chip_package;
+
+diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
+index 9ae9082..b8be23c 100644
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -170,7 +170,8 @@
+ #define SSB_SPROMSIZE_WORDS_R4 220
+ #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+-#define SSB_SPROM_BASE 0x1000
++#define SSB_SPROM_BASE1 0x1000
++#define SSB_SPROM_BASE31 0x0800
+ #define SSB_SPROM_REVISION 0x107E
+ #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
+ #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Use-relative-offsets-for-SPROM.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-Use-relative-offsets-for-SPROM.patch Tue Aug 3 03:11:23 2010 (r16073)
@@ -0,0 +1,382 @@
+From c1385c40a2b93b5a300f1a8dd56891c74026e5a3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5 at gmail.com>
+Date: Wed, 31 Mar 2010 22:54:18 +0200
+Subject: [PATCH 4/5] ssb: Use relative offsets for SPROM
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit 0a182fd88f8180b342f753f04c7d5507b5891c96 upstream.
+
+Signed-off-by: Rafał Miłecki <zajec5 at gmail.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+ drivers/ssb/pci.c | 2 +-
+ include/linux/ssb/ssb_regs.h | 196 +++++++++++++++++++++---------------------
+ 2 files changed, 99 insertions(+), 99 deletions(-)
+
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index 5bb1278..3f556d6 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -167,7 +167,7 @@ err_pci:
+ }
+
+ /* Get the word-offset for a SSB_SPROM_XXX define. */
+-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
++#define SPOFF(offset) ((offset) / sizeof(u16))
+ /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
+ #define SPEX16(_outvar, _offset, _mask, _shift) \
+ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
+index b8be23c..8990e30 100644
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -172,25 +172,25 @@
+ #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
+ #define SSB_SPROM_BASE1 0x1000
+ #define SSB_SPROM_BASE31 0x0800
+-#define SSB_SPROM_REVISION 0x107E
++#define SSB_SPROM_REVISION 0x007E
+ #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
+ #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
+ #define SSB_SPROM_REVISION_CRC_SHIFT 8
+
+ /* SPROM Revision 1 */
+-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
+-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
+-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
+-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
+-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
+-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
++#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
++#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
++#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
++#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
++#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
++#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
+ #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
+ #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
+ #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
+ #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
+ #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
+-#define SSB_SPROM1_BINF 0x105C /* Board info */
++#define SSB_SPROM1_BINF 0x005C /* Board info */
+ #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
+ #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
+ #define SSB_SPROM1_BINF_CCODE_SHIFT 8
+@@ -198,63 +198,63 @@
+ #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
+ #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
+ #define SSB_SPROM1_BINF_ANTA_SHIFT 14
+-#define SSB_SPROM1_PA0B0 0x105E
+-#define SSB_SPROM1_PA0B1 0x1060
+-#define SSB_SPROM1_PA0B2 0x1062
+-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
++#define SSB_SPROM1_PA0B0 0x005E
++#define SSB_SPROM1_PA0B1 0x0060
++#define SSB_SPROM1_PA0B2 0x0062
++#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
+ #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
+ #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
+ #define SSB_SPROM1_GPIOA_P1_SHIFT 8
+-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
++#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
+ #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
+ #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
+ #define SSB_SPROM1_GPIOB_P3_SHIFT 8
+-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
++#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
+ #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
+ #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
+ #define SSB_SPROM1_MAXPWR_A_SHIFT 8
+-#define SSB_SPROM1_PA1B0 0x106A
+-#define SSB_SPROM1_PA1B1 0x106C
+-#define SSB_SPROM1_PA1B2 0x106E
+-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
++#define SSB_SPROM1_PA1B0 0x006A
++#define SSB_SPROM1_PA1B1 0x006C
++#define SSB_SPROM1_PA1B2 0x006E
++#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
+ #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
+ #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
+ #define SSB_SPROM1_ITSSI_A_SHIFT 8
+-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
+-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
++#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
+ #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
+ #define SSB_SPROM1_AGAIN_BG_SHIFT 0
+ #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
+ #define SSB_SPROM1_AGAIN_A_SHIFT 8
+
+ /* SPROM Revision 2 (inherits from rev 1) */
+-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
+-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
++#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
++#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
+ #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
+ #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
+ #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
+-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
+-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
+-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
++#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
++#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
++#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
+ #define SSB_SPROM2_OPO_VALUE 0x00FF
+ #define SSB_SPROM2_OPO_UNUSED 0xFF00
+-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
++#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
+
+ /* SPROM Revision 3 (inherits most data from rev 2) */
+-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
+-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
++#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
++#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
++#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+ #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
+ #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
+ #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
+ #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
+-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
++#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
+ #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
+ #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
+ #define SSB_SPROM3_CCKPO_2M_SHIFT 4
+@@ -265,100 +265,100 @@
+ #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+
+ /* SPROM Revision 4 */
+-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
++#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
+ #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
+ #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
+ #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
+ #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
+ #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
+-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
+-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
++#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
++#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
+ #define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
+ #define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
+ #define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
+ #define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
+-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
+-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
++#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
+ #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
+ #define SSB_SPROM4_AGAIN0_SHIFT 0
+ #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
+ #define SSB_SPROM4_AGAIN1_SHIFT 8
+-#define SSB_SPROM4_AGAIN23 0x1060
++#define SSB_SPROM4_AGAIN23 0x0060
+ #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
+ #define SSB_SPROM4_AGAIN2_SHIFT 0
+ #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
+ #define SSB_SPROM4_AGAIN3_SHIFT 8
+-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
+-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
++#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
++#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
+ #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
+ #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
+ #define SSB_SPROM4_ITSSI_BG_SHIFT 8
+-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
++#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
+ #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
+ #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
+ #define SSB_SPROM4_ITSSI_A_SHIFT 8
+-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
+ #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
+ #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
+ #define SSB_SPROM4_GPIOA_P1_SHIFT 8
+-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
+ #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
+ #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
+ #define SSB_SPROM4_GPIOB_P3_SHIFT 8
+-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
+-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
+-#define SSB_SPROM4_PA0B2 0x1086
+-#define SSB_SPROM4_PA1B0 0x108E
+-#define SSB_SPROM4_PA1B1 0x1090
+-#define SSB_SPROM4_PA1B2 0x1092
++#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
++#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
++#define SSB_SPROM4_PA0B2 0x0086
++#define SSB_SPROM4_PA1B0 0x008E
++#define SSB_SPROM4_PA1B1 0x0090
++#define SSB_SPROM4_PA1B2 0x0092
+
+ /* SPROM Revision 5 (inherits most data from rev 4) */
+-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
+-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
+-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
+-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
+-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
++#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
++#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
++#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
++#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
+ #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
+ #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
+ #define SSB_SPROM5_GPIOA_P1_SHIFT 8
+-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
+ #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
+ #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
+ #define SSB_SPROM5_GPIOB_P3_SHIFT 8
+
+ /* SPROM Revision 8 */
+-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
+-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
+-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
+-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
+-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
+-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
+-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
+-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
++#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
++#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
++#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
++#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
++#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
++#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
++#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
++#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
+ #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
+ #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
+ #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
+ #define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
+-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
++#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
+ #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
+ #define SSB_SPROM8_AGAIN0_SHIFT 0
+ #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
+ #define SSB_SPROM8_AGAIN1_SHIFT 8
+-#define SSB_SPROM8_AGAIN23 0x10A0
++#define SSB_SPROM8_AGAIN23 0x00A0
+ #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
+ #define SSB_SPROM8_AGAIN2_SHIFT 0
+ #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
+ #define SSB_SPROM8_AGAIN3_SHIFT 8
+-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
++#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
+ #define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
+ #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
+ #define SSB_SPROM8_GPIOA_P1_SHIFT 8
+-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
++#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
+ #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
+ #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
+ #define SSB_SPROM8_GPIOB_P3_SHIFT 8
+-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
++#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
+ #define SSB_SPROM8_RSSISMF2G 0x000F
+ #define SSB_SPROM8_RSSISMC2G 0x00F0
+ #define SSB_SPROM8_RSSISMC2G_SHIFT 4
+@@ -366,7 +366,7 @@
+ #define SSB_SPROM8_RSSISAV2G_SHIFT 8
+ #define SSB_SPROM8_BXA2G 0x1800
+ #define SSB_SPROM8_BXA2G_SHIFT 11
+-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
++#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
+ #define SSB_SPROM8_RSSISMF5G 0x000F
+ #define SSB_SPROM8_RSSISMC5G 0x00F0
+ #define SSB_SPROM8_RSSISMC5G_SHIFT 4
+@@ -374,47 +374,47 @@
+ #define SSB_SPROM8_RSSISAV5G_SHIFT 8
+ #define SSB_SPROM8_BXA5G 0x1800
+ #define SSB_SPROM8_BXA5G_SHIFT 11
+-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
++#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
+ #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
+ #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
+ #define SSB_SPROM8_TRI5G_SHIFT 8
+-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
++#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
+ #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
+ #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
+ #define SSB_SPROM8_TRI5GH_SHIFT 8
+-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
++#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
+ #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
+ #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
+ #define SSB_SPROM8_RXPO5G_SHIFT 8
+-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
++#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
+ #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
+ #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
+ #define SSB_SPROM8_ITSSI_BG_SHIFT 8
+-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
+-#define SSB_SPROM8_PA0B1 0x10C4
+-#define SSB_SPROM8_PA0B2 0x10C6
+-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
++#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
++#define SSB_SPROM8_PA0B1 0x00C4
++#define SSB_SPROM8_PA0B2 0x00C6
++#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
+ #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
+ #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
+ #define SSB_SPROM8_ITSSI_A_SHIFT 8
+-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
++#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
+ #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
+ #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
+ #define SSB_SPROM8_MAXP_AL_SHIFT 8
+-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
+-#define SSB_SPROM8_PA1B1 0x10CE
+-#define SSB_SPROM8_PA1B2 0x10D0
+-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
+-#define SSB_SPROM8_PA1LOB1 0x10D4
+-#define SSB_SPROM8_PA1LOB2 0x10D6
+-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
+-#define SSB_SPROM8_PA1HIB1 0x10DA
+-#define SSB_SPROM8_PA1HIB2 0x10DC
+-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
+-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
+-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
++#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
++#define SSB_SPROM8_PA1B1 0x00CE
++#define SSB_SPROM8_PA1B2 0x00D0
++#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
++#define SSB_SPROM8_PA1LOB1 0x00D4
++#define SSB_SPROM8_PA1LOB2 0x00D6
++#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
++#define SSB_SPROM8_PA1HIB1 0x00DA
++#define SSB_SPROM8_PA1HIB2 0x00DC
++#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
++#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
++#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
+
+ /* Values for SSB_SPROM1_BINF_CCODE */
+ enum {
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-do-not-read-SPROM-if-it-does-not-exist.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-do-not-read-SPROM-if-it-does-not-exist.patch Tue Aug 3 03:11:23 2010 (r16073)
@@ -0,0 +1,149 @@
+From eb0ab50cc128044e2d785a4a7a21bb342e1fd3e1 Mon Sep 17 00:00:00 2001
+From: John W. Linville <linville at tuxdriver.com>
+Date: Wed, 31 Mar 2010 21:39:35 +0200
+Subject: [PATCH 2/5] ssb: do not read SPROM if it does not exist
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit d53cdbb94a52a920d5420ed64d986c3523a56743 upstream.
+
+Attempting to read registers that don't exist on the SSB bus can cause
+hangs on some boxes. At least some b43 devices are 'in the wild' that
+don't have SPROMs at all. When the SSB bus support loads, it attempts
+to read these (non-existant) SPROMs and causes hard hangs on the box --
+no console output, etc.
+
+This patch adds some intelligence to determine whether or not the SPROM
+is present before attempting to read it. This avoids those hard hangs
+on those devices with no SPROM attached to their SSB bus. The
+SSB-attached devices (e.g. b43, et al.) won't work, but at least the box
+will survive to test further patches. :-)
+
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+Signed-off-by: Rafał Miłecki <zajec5 at gmail.com>
+Cc: Larry Finger <Larry.Finger at lwfinger.net>
+Cc: Michael Buesch <mb at bu3sch.de>
+---
+ drivers/ssb/driver_chipcommon.c | 2 ++
+ drivers/ssb/pci.c | 5 +++++
+ drivers/ssb/sprom.c | 14 ++++++++++++++
+ include/linux/ssb/ssb.h | 3 +++
+ include/linux/ssb/ssb_driver_chipcommon.h | 15 +++++++++++++++
+ 5 files changed, 39 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
+index 9681536..a55cff8 100644
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ {
+ if (!cc->dev)
+ return; /* We don't have a ChipCommon */
++ if (cc->dev->id.revision >= 11)
++ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ ssb_pmu_init(cc);
+ chipco_powercontrol_init(cc);
+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index 9e50896..a4b2b99 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -620,6 +620,11 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ int err = -ENOMEM;
+ u16 *buf;
+
++ if (!ssb_is_sprom_available(bus)) {
++ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++ return -ENODEV;
++ }
++
+ buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ if (!buf)
+ goto out;
+diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
+index eb70843..042c643 100644
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -179,3 +179,17 @@ const struct ssb_sprom *ssb_get_fallback_sprom(void)
+ {
+ return fallback_sprom;
+ }
++
++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
++bool ssb_is_sprom_available(struct ssb_bus *bus)
++{
++ /* status register only exists on chipcomon rev >= 11 and we need check
++ for >= 31 only */
++ /* this routine differs from specs as we do not access SPROM directly
++ on PCMCIA */
++ if (bus->bustype == SSB_BUSTYPE_PCI &&
++ bus->chipco.dev->id.revision >= 31)
++ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
++
++ return true;
++}
+diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
+index 3d0a9ff..38bac23 100644
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -390,6 +390,9 @@ extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
+
+ extern void ssb_bus_unregister(struct ssb_bus *bus);
+
++/* Does the device have an SPROM? */
++extern bool ssb_is_sprom_available(struct ssb_bus *bus);
++
+ /* Set a fallback SPROM.
+ * See kdoc at the function definition for complete documentation. */
+ extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
+diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
+index 4e27acf..2cdf249 100644
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -53,6 +53,7 @@
+ #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
+ #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
+ #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
++#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
+ #define SSB_CHIPCO_CORECTL 0x0008
+ #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
+ #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
+@@ -385,6 +386,7 @@
+
+
+ /** Chip specific Chip-Status register contents. */
++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
+ #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
+ #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
+ #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
+@@ -398,6 +400,18 @@
+ #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
+ #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
+
++/** Macros to determine SPROM presence based on Chip-Status register. */
++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++ SSB_CHIPCO_CHST_4325_OTP_SEL)
++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
++ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
++ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
++ SSB_CHIPCO_CHST_4325_OTP_SEL))
++
+
+
+ /** Clockcontrol masks and values **/
+@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
+ struct ssb_chipcommon {
+ struct ssb_device *dev;
+ u32 capabilities;
++ u32 status;
+ /* Fast Powerup Delay constant */
+ u16 fast_pwrup_delay;
+ struct ssb_chipcommon_pmu pmu;
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-fix-NULL-ptr-deref-when-pcihost_wrapper-is-used.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/ssb-fix-NULL-ptr-deref-when-pcihost_wrapper-is-used.patch Tue Aug 3 03:11:23 2010 (r16073)
@@ -0,0 +1,57 @@
+From 7b7e14345bf7b5dad9dea298ec8b2bac3cebc5e1 Mon Sep 17 00:00:00 2001
+From: Christoph Fritz <chf.fritz at googlemail.com>
+Date: Fri, 28 May 2010 10:45:59 +0200
+Subject: [PATCH 5/5] ssb: fix NULL ptr deref when pcihost_wrapper is used
+
+commit da1fdb02d9200ff28b6f3a380d21930335fe5429 upstream.
+
+Ethernet driver b44 does register ssb by it's pcihost_wrapper
+and doesn't set ssb_chipcommon. A check on this value
+introduced with commit d53cdbb94a52a920d5420ed64d986c3523a56743
+and ea2db495f92ad2cf3301623e60cb95b4062bc484 triggers:
+
+BUG: unable to handle kernel NULL pointer dereference at 00000010
+IP: [<c1266c36>] ssb_is_sprom_available+0x16/0x30
+
+Signed-off-by: Christoph Fritz <chf.fritz at googlemail.com>
+Signed-off-by: John W. Linville <linville at tuxdriver.com>
+---
+ drivers/ssb/pci.c | 9 ++++++---
+ drivers/ssb/sprom.c | 1 +
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index 3f556d6..e6585ea 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -624,9 +624,12 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
+ return -ENODEV;
+ }
+-
+- bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
+- SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++ if (bus->chipco.dev) { /* can be unavailible! */
++ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
++ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
++ } else {
++ bus->sprom_offset = SSB_SPROM_BASE1;
++ }
+
+ buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ if (!buf)
+diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
+index 042c643..5f7154d 100644
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -188,6 +188,7 @@ bool ssb_is_sprom_available(struct ssb_bus *bus)
+ /* this routine differs from specs as we do not access SPROM directly
+ on PCMCIA */
+ if (bus->bustype == SSB_BUSTYPE_PCI &&
++ bus->chipco.dev && /* can be unavailible! */
+ bus->chipco.dev->id.revision >= 31)
+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
+
+--
+1.7.1
+
Modified: dists/sid/linux-2.6/debian/patches/series/19
==============================================================================
--- dists/sid/linux-2.6/debian/patches/series/19 Tue Aug 3 03:00:02 2010 (r16072)
+++ dists/sid/linux-2.6/debian/patches/series/19 Tue Aug 3 03:11:23 2010 (r16073)
@@ -21,3 +21,8 @@
- bugfix/x86/drm-i915-add-reclaimable-to-i915-self-reclaimable-pa.patch
- bugfix/x86/drm-i915-fix-hibernation-since-i915-self-reclaim-fix.patch
+ bugfix/all/stable/2.6.33.7.patch
++ bugfix/all/revert-ssb-Handle-Netbook-devices-where-the-SPROM-ad.patch
++ bugfix/all/ssb-do-not-read-SPROM-if-it-does-not-exist.patch
++ bugfix/all/ssb-Look-for-SPROM-at-different-offset-on-higher-rev.patch
++ bugfix/all/ssb-Use-relative-offsets-for-SPROM.patch
++ bugfix/all/ssb-fix-NULL-ptr-deref-when-pcihost_wrapper-is-used.patch
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