[kernel] r16114 - in dists/sid/linux-2.6/debian: . patches/bugfix/all patches/bugfix/x86 patches/series
Ben Hutchings
benh at alioth.debian.org
Wed Aug 11 01:11:01 UTC 2010
Author: benh
Date: Wed Aug 11 01:10:53 2010
New Revision: 16114
Log:
Add drm changes from stable 2.6.34.2 and 2.6.34.3
Added:
dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-add-new-pci-ids.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-flush-HDP-cache-on-GART-table-updates.patch
dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-r7xx-add-workaround-for-hw-issue-with.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Check-overlay-stride-errata-for-i830-and-i8.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Hold-the-spinlock-whilst-resetting-unpin_wo.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-add-PANEL_UNLOCK_REGS-definition.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-access-FW_BLC_SELF-on-965G.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-queue-flips-during-a-flip-pending-eve.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-gen3-page-flipping-fixes.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-handle-shared-framebuffers-when-flipping.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-eDP-panel-is-turned-on.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-we-shut-off-the-panel-in-eDP-conf.patch
dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-radeon-kms-igp-sideport-is-AMD-only.patch
Modified:
dists/sid/linux-2.6/debian/changelog
dists/sid/linux-2.6/debian/patches/series/20
Modified: dists/sid/linux-2.6/debian/changelog
==============================================================================
--- dists/sid/linux-2.6/debian/changelog Tue Aug 10 22:52:44 2010 (r16113)
+++ dists/sid/linux-2.6/debian/changelog Wed Aug 11 01:10:53 2010 (r16114)
@@ -17,6 +17,8 @@
* V4L/DVB: Add Elgato EyeTV Diversity to dibcom driver (Closes: #591710)
* [s390] dasd: use correct label location for diag fba disks
(Closes: #582281)
+ * Add drm changes from stable 2.6.34.2 (thanks to Stefan Bader) and
+ 2.6.34.3
[ Martin Michlmayr ]
* [armel/orion5x] Add a missing #include to fix a build issue.
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-add-new-pci-ids.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-add-new-pci-ids.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,72 @@
+From 50f8946cdcb43f891e77c7fb351d4bada72fd6d8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed, 4 Aug 2010 11:40:00 -0400
+Subject: [PATCH 2/5] drm/radeon: add new pci ids
+
+commit 1297c05a8dfb568c689f057d51a65eebe5ddc86f upstream.
+
+New evergreen and r7xx ids.
+
+Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+Cc: stable at kernel.org
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+---
+ include/drm/drm_pciids.h | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
+index 897a348..6b90399 100644
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -146,6 +146,8 @@
+ {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x688C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x688D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+@@ -161,6 +163,7 @@
+ {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x68c7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+@@ -174,6 +177,7 @@
+ {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x68f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+@@ -314,6 +318,7 @@
+ {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x945E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -324,6 +329,7 @@
+ {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x948A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -366,6 +372,7 @@
+ {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9557, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x955f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-flush-HDP-cache-on-GART-table-updates.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-flush-HDP-cache-on-GART-table-updates.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,31 @@
+From fe9b710690bb528f65298500571dbc736c310a3f Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied at redhat.com>
+Date: Mon, 15 Feb 2010 15:54:45 +1000
+Subject: [PATCH 3/5] drm/radeon/kms: flush HDP cache on GART table updates.
+
+commit 2e98f10a7a87ebae4dcc3949028a32008b46ceef upstream.
+
+Suggested by Alex Deucher @ AMD
+
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+---
+ drivers/gpu/drm/radeon/r600.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
+index 2ffcf5a..0cf176f 100644
+--- a/drivers/gpu/drm/radeon/r600.c
++++ b/drivers/gpu/drm/radeon/r600.c
+@@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
+ unsigned i;
+ u32 tmp;
+
++ /* flush hdp cache so updates hit vram */
++ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
++
+ WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+ WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-r7xx-add-workaround-for-hw-issue-with.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/all/drm-radeon-kms-r7xx-add-workaround-for-hw-issue-with.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,103 @@
+From eb2cad7462d1c85b815ed708f6e6c3f366971635 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher at gmail.com>
+Date: Mon, 26 Jul 2010 18:51:53 -0400
+Subject: [PATCH 4/5] drm/radeon/kms/r7xx: add workaround for hw issue with HDP flush
+
+commit 812d046915f48236657f02c06d7dc47140e9ceda upstream.
+
+Use of HDP_*_COHERENCY_FLUSH_CNTL can cause a hang in certain
+situations. Add workaround.
+
+Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+Cc: stable at kernel.org
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+---
+ drivers/gpu/drm/radeon/r600.c | 24 ++++++++++++++++++++++--
+ drivers/gpu/drm/radeon/r600d.h | 1 +
+ drivers/gpu/drm/radeon/rv770.c | 5 ++++-
+ drivers/gpu/drm/radeon/rv770d.h | 1 +
+ 4 files changed, 28 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
+index 0cf176f..1d75b0e 100644
+--- a/drivers/gpu/drm/radeon/r600.c
++++ b/drivers/gpu/drm/radeon/r600.c
+@@ -371,7 +371,17 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
+ u32 tmp;
+
+ /* flush hdp cache so updates hit vram */
+- WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
++ if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
++ u32 tmp;
++
++ /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
++ * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ WREG32(HDP_DEBUG1, 0);
++ tmp = readl((void __iomem *)ptr);
++ } else
++ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+
+ WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+@@ -2929,5 +2939,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
+ */
+ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
+ {
+- WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
++ /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
++ * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
++ u32 tmp;
++
++ WREG32(HDP_DEBUG1, 0);
++ tmp = readl((void __iomem *)ptr);
++ } else
++ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+ }
+diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
+index 3048088..f5df349 100644
+--- a/drivers/gpu/drm/radeon/r600d.h
++++ b/drivers/gpu/drm/radeon/r600d.h
+@@ -196,6 +196,7 @@
+ #define HDP_NONSURFACE_SIZE 0x2C0C
+ #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+ #define HDP_TILING_CONFIG 0x2F3C
++#define HDP_DEBUG1 0x2F34
+
+ #define MC_VM_AGP_TOP 0x2184
+ #define MC_VM_AGP_BOT 0x2188
+diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
+index 0302167..d689d4c 100644
+--- a/drivers/gpu/drm/radeon/rv770.c
++++ b/drivers/gpu/drm/radeon/rv770.c
+@@ -171,7 +171,10 @@ static void rv770_mc_program(struct radeon_device *rdev)
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ }
+- WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
++ /* r7xx hw bug. Read from HDP_DEBUG1 rather
++ * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ tmp = RREG32(HDP_DEBUG1);
+
+ rv515_mc_stop(rdev, &save);
+ if (r600_mc_wait_for_idle(rdev)) {
+diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
+index 9506f8c..6111a02 100644
+--- a/drivers/gpu/drm/radeon/rv770d.h
++++ b/drivers/gpu/drm/radeon/rv770d.h
+@@ -128,6 +128,7 @@
+ #define HDP_NONSURFACE_SIZE 0x2C0C
+ #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+ #define HDP_TILING_CONFIG 0x2F3C
++#define HDP_DEBUG1 0x2F34
+
+ #define MC_SHARED_CHMAP 0x2004
+ #define NOOFCHAN_SHIFT 12
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Check-overlay-stride-errata-for-i830-and-i8.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Check-overlay-stride-errata-for-i830-and-i8.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,45 @@
+From 929d21282fe49d201dde97b5e6ad793404978f44 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris at chris-wilson.co.uk>
+Date: Mon, 12 Jul 2010 19:35:38 +0100
+Subject: [PATCH 5/5] drm/i915: Check overlay stride errata for i830 and i845
+
+commit a1efd14a99483a4fb9308902397ed86b69454c99 upstream.
+
+Apparently i830 and i845 cannot handle any stride that is not a multiple
+of 256, unlike their brethren which do support 64 byte aligned strides.
+
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Cc: stable at kernel.org
+Signed-off-by: Eric Anholt <eric at anholt.net>
+---
+ drivers/gpu/drm/i915/intel_overlay.c | 7 +++++--
+ 1 files changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
+index 6b89042..ed4058e 100644
+--- a/drivers/gpu/drm/i915/intel_overlay.c
++++ b/drivers/gpu/drm/i915/intel_overlay.c
+@@ -965,7 +965,7 @@ static int check_overlay_src(struct drm_device *dev,
+ || rec->src_width < N_HORIZ_Y_TAPS*4)
+ return -EINVAL;
+
+- /* check alingment constrains */
++ /* check alignment constraints */
+ switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
+ case I915_OVERLAY_RGB:
+ /* not implemented */
+@@ -997,7 +997,10 @@ static int check_overlay_src(struct drm_device *dev,
+ return -EINVAL;
+
+ /* stride checking */
+- stride_mask = 63;
++ if (IS_I830(dev) || IS_845G(dev))
++ stride_mask = 255;
++ else
++ stride_mask = 63;
+
+ if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
+ return -EINVAL;
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Hold-the-spinlock-whilst-resetting-unpin_wo.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-Hold-the-spinlock-whilst-resetting-unpin_wo.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,77 @@
+From 737b7d33a27fa18a977c7fa8fff9e6ab63e24250 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris at chris-wilson.co.uk>
+Date: Thu, 27 May 2010 13:18:13 +0100
+Subject: [PATCH 4/8] drm/i915: Hold the spinlock whilst resetting unpin_work along error path
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit 468f0b44ce4b002ca7d9260f802a341854752c02 upstream.
+
+Delay taking the mutex until we need to and ensure that we hold the
+spinlock when resetting unpin_work on the error path. Also defer the
+debugging print messages until after we have released the spinlock.
+
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Cc: Jesse Barnes <jbarnes at virtuousgeek.org>
+Cc: Kristian Høgsberg <krh at bitplanet.net>
+Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++-------
+ 1 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 622e747..eb5a13b 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -4208,8 +4208,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ if (work == NULL)
+ return -ENOMEM;
+
+- mutex_lock(&dev->struct_mutex);
+-
+ work->event = event;
+ work->dev = crtc->dev;
+ intel_fb = to_intel_framebuffer(crtc->fb);
+@@ -4219,10 +4217,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ /* We borrow the event spin lock for protecting unpin_work */
+ spin_lock_irqsave(&dev->event_lock, flags);
+ if (intel_crtc->unpin_work) {
+- DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
+ spin_unlock_irqrestore(&dev->event_lock, flags);
+ kfree(work);
+- mutex_unlock(&dev->struct_mutex);
++
++ DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
+ return -EBUSY;
+ }
+ intel_crtc->unpin_work = work;
+@@ -4231,13 +4229,19 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ intel_fb = to_intel_framebuffer(fb);
+ obj = intel_fb->obj;
+
++ mutex_lock(&dev->struct_mutex);
+ ret = intel_pin_and_fence_fb_obj(dev, obj);
+ if (ret != 0) {
++ mutex_unlock(&dev->struct_mutex);
++
++ spin_lock_irqsave(&dev->event_lock, flags);
++ intel_crtc->unpin_work = NULL;
++ spin_unlock_irqrestore(&dev->event_lock, flags);
++
++ kfree(work);
++
+ DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
+ obj->driver_private);
+- kfree(work);
+- intel_crtc->unpin_work = NULL;
+- mutex_unlock(&dev->struct_mutex);
+ return ret;
+ }
+
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-add-PANEL_UNLOCK_REGS-definition.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-add-PANEL_UNLOCK_REGS-definition.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,58 @@
+From 92c7c265b58669d87714a256447a92df3e69380a Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Thu, 22 Jul 2010 13:18:18 -0700
+Subject: [PATCH 6/8] drm/i915: add PANEL_UNLOCK_REGS definition
+
+commit 4a655f043160eeae447efd3be297b6b4c397a640 upstream.
+
+In some cases, unlocking the panel regs is safe and can help us avoid a
+flickery, full mode set sequence. So define the unlock key and use it.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/i915_reg.h | 1 +
+ drivers/gpu/drm/i915/intel_display.c | 6 ++++--
+ 2 files changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index 5acc4ca..b463a0b 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -2513,6 +2513,7 @@
+
+ #define PCH_PP_STATUS 0xc7200
+ #define PCH_PP_CONTROL 0xc7204
++#define PANEL_UNLOCK_REGS (0xabcd << 16)
+ #define EDP_FORCE_VDD (1 << 3)
+ #define EDP_BLC_ENABLE (1 << 2)
+ #define PANEL_POWER_RESET (1 << 1)
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 52896ba..26e7d22 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -3934,7 +3934,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
+ DRM_DEBUG_DRIVER("upclocking LVDS\n");
+
+ /* Unlock panel regs */
+- I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
++ PANEL_UNLOCK_REGS);
+
+ dpll &= ~DISPLAY_RATE_SELECT_FPA1;
+ I915_WRITE(dpll_reg, dpll);
+@@ -3977,7 +3978,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
+ DRM_DEBUG_DRIVER("downclocking LVDS\n");
+
+ /* Unlock panel regs */
+- I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
++ I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
++ PANEL_UNLOCK_REGS);
+
+ dpll |= DISPLAY_RATE_SELECT_FPA1;
+ I915_WRITE(dpll_reg, dpll);
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-access-FW_BLC_SELF-on-965G.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-access-FW_BLC_SELF-on-965G.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,46 @@
+From e09fc23ba74a55ee2d44faafca0270dec828ce84 Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Wed, 30 Jun 2010 13:49:37 -0700
+Subject: [PATCH 1/8] drm/i915: don't access FW_BLC_SELF on 965G
+
+commit adcdbc6651a7086b99827cf50623a02d941261f1 upstream.
+
+The register offset for FW_BLC_SELF is a totally different set of bits
+on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
+FW_BLC_SELF on 965G chips.
+
+Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874.
+
+Tested-by: Norman Yarvin <yarvin at yarchive.net>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_display.c | 8 +++++---
+ 1 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index d63173a..9502353 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2685,11 +2685,13 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
+ if (srwm < 0)
+ srwm = 1;
+ srwm &= 0x3f;
+- I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ if (IS_I965GM(dev))
++ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+ } else {
+ /* Turn off self refresh if both pipes are enabled */
+- I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+- & ~FW_BLC_SELF_EN);
++ if (IS_I965GM(dev))
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-queue-flips-during-a-flip-pending-eve.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-don-t-queue-flips-during-a-flip-pending-eve.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,54 @@
+From e2407f4f5e49d9a471df0500be4847d42f7e35ae Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Mon, 5 Apr 2010 14:03:51 -0700
+Subject: [PATCH 3/8] drm/i915: don't queue flips during a flip pending event
+
+commit 83f7fd055eb3f1e843803cd906179d309553967b upstream.
+
+Hardware will set the flip pending ISR bit as soon as it receives the
+flip instruction, and (supposedly) clear it once the flip completes
+(e.g. at the next vblank). If we try to send down a flip instruction
+while the ISR bit is set, the hardware can become very confused, and we
+may never receive the corresponding flip pending interrupt, effectively
+hanging the chip.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
+ 1 files changed, 11 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index f4018fc..622e747 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -4201,6 +4201,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ unsigned long flags;
+ int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
+ int ret, pipesrc;
++ u32 flip_mask;
+ RING_LOCALS;
+
+ work = kzalloc(sizeof *work, GFP_KERNEL);
+@@ -4251,6 +4252,16 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ atomic_inc(&obj_priv->pending_flip);
+ work->pending_flip_obj = obj;
+
++ if (intel_crtc->plane)
++ flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
++ else
++ flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
++
++ /* Wait for any previous flip to finish */
++ if (IS_GEN3(dev))
++ while (I915_READ(ISR) & flip_mask)
++ ;
++
+ BEGIN_LP_RING(4);
+ if (IS_I965G(dev)) {
+ OUT_RING(MI_DISPLAY_FLIP |
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-gen3-page-flipping-fixes.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-gen3-page-flipping-fixes.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,192 @@
+From 4754f69f0396f6c859d3b59b1dc848c8a46fea5b Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Fri, 26 Mar 2010 10:35:20 -0700
+Subject: [PATCH 2/8] drm/i915: gen3 page flipping fixes
+
+commit 1afe3e9d4335bf3bc5615e37243dc8fef65dac8f upstream.
+
+Gen3 chips have slightly different flip commands, and also contain a bit
+that indicates whether a "flip pending" interrupt means the flip has
+been queued or has been completed.
+
+So implement support for the gen3 flip command, and make sure we use the
+flip pending interrupt correctly depending on the value of ECOSKPD bit
+0.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/i915_dma.c | 4 ++++
+ drivers/gpu/drm/i915/i915_drv.h | 1 +
+ drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++++++----
+ drivers/gpu/drm/i915/i915_reg.h | 4 ++++
+ drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++-----
+ drivers/gpu/drm/i915/intel_drv.h | 1 +
+ 6 files changed, 46 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
+index d642efd..2918fbc 100644
+--- a/drivers/gpu/drm/i915/i915_dma.c
++++ b/drivers/gpu/drm/i915/i915_dma.c
+@@ -1266,6 +1266,10 @@ static int i915_load_modeset_init(struct drm_device *dev,
+ if (ret)
+ goto destroy_ringbuffer;
+
++ /* IIR "flip pending" bit means done if this bit is set */
++ if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
++ dev_priv->flip_pending_is_done = true;
++
+ intel_modeset_init(dev);
+
+ ret = drm_irq_install(dev);
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index 6679741..b26d0ed 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -581,6 +581,7 @@ typedef struct drm_i915_private {
+ struct drm_crtc *plane_to_crtc_mapping[2];
+ struct drm_crtc *pipe_to_crtc_mapping[2];
+ wait_queue_head_t pending_flip_queue;
++ bool flip_pending_is_done;
+
+ /* Reclocking support */
+ bool render_reclock_avail;
+diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
+index d6466d5..345b60f 100644
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -661,22 +661,30 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
+ mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
+ }
+
+- if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
++ if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
+ intel_prepare_page_flip(dev, 0);
++ if (dev_priv->flip_pending_is_done)
++ intel_finish_page_flip_plane(dev, 0);
++ }
+
+- if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
++ if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
++ if (dev_priv->flip_pending_is_done)
++ intel_finish_page_flip_plane(dev, 1);
+ intel_prepare_page_flip(dev, 1);
++ }
+
+ if (pipea_stats & vblank_status) {
+ vblank++;
+ drm_handle_vblank(dev, 0);
+- intel_finish_page_flip(dev, 0);
++ if (!dev_priv->flip_pending_is_done)
++ intel_finish_page_flip(dev, 0);
+ }
+
+ if (pipeb_stats & vblank_status) {
+ vblank++;
+ drm_handle_vblank(dev, 1);
+- intel_finish_page_flip(dev, 1);
++ if (!dev_priv->flip_pending_is_done)
++ intel_finish_page_flip(dev, 1);
+ }
+
+ if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index 635d349..5acc4ca 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -158,6 +158,7 @@
+ #define MI_OVERLAY_OFF (0x2<<21)
+ #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
+ #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
++#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
+ #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+ #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
+ #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
+@@ -399,6 +400,9 @@
+ #define CM0_DEPTH_WRITE_DISABLE (1<<1)
+ #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
+ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
++#define ECOSKPD 0x021d0
++#define ECO_GATING_CX_ONLY (1<<3)
++#define ECO_FLIP_DONE (1<<0)
+
+
+ /*
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index 9502353..f4018fc 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -4102,10 +4102,10 @@ static void intel_unpin_work_fn(struct work_struct *__work)
+ kfree(work);
+ }
+
+-void intel_finish_page_flip(struct drm_device *dev, int pipe)
++static void do_intel_finish_page_flip(struct drm_device *dev,
++ struct drm_crtc *crtc)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+- struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_unpin_work *work;
+ struct drm_i915_gem_object *obj_priv;
+@@ -4155,6 +4155,22 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
+ schedule_work(&work->work);
+ }
+
++void intel_finish_page_flip(struct drm_device *dev, int pipe)
++{
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
++
++ do_intel_finish_page_flip(dev, crtc);
++}
++
++void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
++{
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
++
++ do_intel_finish_page_flip(dev, crtc);
++}
++
+ void intel_prepare_page_flip(struct drm_device *dev, int plane)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+@@ -4236,14 +4252,17 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ work->pending_flip_obj = obj;
+
+ BEGIN_LP_RING(4);
+- OUT_RING(MI_DISPLAY_FLIP |
+- MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+- OUT_RING(fb->pitch);
+ if (IS_I965G(dev)) {
++ OUT_RING(MI_DISPLAY_FLIP |
++ MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
++ OUT_RING(fb->pitch);
+ OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+ pipesrc = I915_READ(pipesrc_reg);
+ OUT_RING(pipesrc & 0x0fff0fff);
+ } else {
++ OUT_RING(MI_DISPLAY_FLIP_I915 |
++ MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
++ OUT_RING(fb->pitch);
+ OUT_RING(obj_priv->gtt_offset);
+ OUT_RING(MI_NOOP);
+ }
+diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
+index a51573d..46034dc 100644
+--- a/drivers/gpu/drm/i915/intel_drv.h
++++ b/drivers/gpu/drm/i915/intel_drv.h
+@@ -217,6 +217,7 @@ extern int intel_framebuffer_create(struct drm_device *dev,
+
+ extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
+ extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
++extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
+
+ extern void intel_setup_overlay(struct drm_device *dev);
+ extern void intel_cleanup_overlay(struct drm_device *dev);
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-handle-shared-framebuffers-when-flipping.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-handle-shared-framebuffers-when-flipping.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,66 @@
+From 10956a262d3d548f9d908f5f4742e44bc36a36d5 Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Fri, 23 Jul 2010 12:03:37 -0700
+Subject: [PATCH 5/8] drm/i915: handle shared framebuffers when flipping
+
+commit be9a3dbf65a69933b06011f049b1e2fdfa6bc8b9 upstream.
+
+If a framebuffer is shared across CRTCs, the x,y position of one of them
+is likely to be something other than the origin (e.g. for extended
+desktop configs). So calculate the offset at flip time so such
+configurations can work.
+
+Fixes https://bugs.freedesktop.org/show_bug.cgi?id=28518.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Thomas M. <tmezzadra at gmail.com>
+Tested-by: fangxun <xunx.fang at intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_display.c | 10 +++++++---
+ 1 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index eb5a13b..52896ba 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -4198,7 +4198,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ struct drm_gem_object *obj;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_unpin_work *work;
+- unsigned long flags;
++ unsigned long flags, offset;
+ int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
+ int ret, pipesrc;
+ u32 flip_mask;
+@@ -4266,19 +4266,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+ while (I915_READ(ISR) & flip_mask)
+ ;
+
++ /* Offset into the new buffer for cases of shared fbs between CRTCs */
++ offset = obj_priv->gtt_offset;
++ offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
++
+ BEGIN_LP_RING(4);
+ if (IS_I965G(dev)) {
+ OUT_RING(MI_DISPLAY_FLIP |
+ MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+ OUT_RING(fb->pitch);
+- OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
++ OUT_RING(offset | obj_priv->tiling_mode);
+ pipesrc = I915_READ(pipesrc_reg);
+ OUT_RING(pipesrc & 0x0fff0fff);
+ } else {
+ OUT_RING(MI_DISPLAY_FLIP_I915 |
+ MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+ OUT_RING(fb->pitch);
+- OUT_RING(obj_priv->gtt_offset);
++ OUT_RING(offset);
+ OUT_RING(MI_NOOP);
+ }
+ ADVANCE_LP_RING();
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-eDP-panel-is-turned-on.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-eDP-panel-is-turned-on.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,106 @@
+From 6e834f6fca690a64df1a2f7e6857067e06408558 Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Thu, 22 Jul 2010 13:18:19 -0700
+Subject: [PATCH 7/8] drm/i915: make sure eDP panel is turned on
+
+commit 9934c132989d5c488d2e15188220ce240960ce96 upstream.
+
+When enabling the eDP port, we need to make sure the panel is turned on
+after training the link. If we don't, it likely won't come back after
+suspend or may not come up at all.
+
+For unknown reasons, unlocking the panel regs before initiating a power
+on sequence is necessary. There are known bugs in the PCH panel
+sequencing logic, apparently this is one possible workaround.
+
+Fixes https://bugs.freedesktop.org/show_bug.cgi?id=28739.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: "Paulo J. S. Silva" <pjssilva at gmail.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 53 +++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 51 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 439506c..40ca37a 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -676,6 +676,51 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+ }
+ }
+
++static void ironlake_edp_panel_on (struct drm_device *dev)
++{
++ struct drm_i915_private *dev_priv = dev->dev_private;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5000);
++ u32 pp, pp_status;
++
++ pp_status = I915_READ(PCH_PP_STATUS);
++ if (pp_status & PP_ON)
++ return;
++
++ pp = I915_READ(PCH_PP_CONTROL);
++ pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
++ I915_WRITE(PCH_PP_CONTROL, pp);
++ do {
++ pp_status = I915_READ(PCH_PP_STATUS);
++ } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
++
++ if (time_after(jiffies, timeout))
++ DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
++
++ pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
++ I915_WRITE(PCH_PP_CONTROL, pp);
++}
++
++static void ironlake_edp_panel_off (struct drm_device *dev)
++{
++ struct drm_i915_private *dev_priv = dev->dev_private;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5000);
++ u32 pp, pp_status;
++
++ pp = I915_READ(PCH_PP_CONTROL);
++ pp &= ~POWER_TARGET_ON;
++ I915_WRITE(PCH_PP_CONTROL, pp);
++ do {
++ pp_status = I915_READ(PCH_PP_STATUS);
++ } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
++
++ if (time_after(jiffies, timeout))
++ DRM_DEBUG_KMS("panel off wait timed out\n");
++
++ /* Make sure VDD is enabled so DP AUX will work */
++ pp |= EDP_FORCE_VDD;
++ I915_WRITE(PCH_PP_CONTROL, pp);
++}
++
+ static void ironlake_edp_backlight_on (struct drm_device *dev)
+ {
+ struct drm_i915_private *dev_priv = dev->dev_private;
+@@ -710,14 +755,18 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
+ if (mode != DRM_MODE_DPMS_ON) {
+ if (dp_reg & DP_PORT_EN) {
+ intel_dp_link_down(intel_output, dp_priv->DP);
+- if (IS_eDP(intel_output))
++ if (IS_eDP(intel_output)) {
+ ironlake_edp_backlight_off(dev);
++ ironlake_edp_backlight_off(dev);
++ }
+ }
+ } else {
+ if (!(dp_reg & DP_PORT_EN)) {
+ intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
+- if (IS_eDP(intel_output))
++ if (IS_eDP(intel_output)) {
++ ironlake_edp_panel_on(dev);
+ ironlake_edp_backlight_on(dev);
++ }
+ }
+ }
+ dp_priv->dpms_mode = mode;
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-we-shut-off-the-panel-in-eDP-conf.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-i915-make-sure-we-shut-off-the-panel-in-eDP-conf.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,34 @@
+From c4c556fe14db045460f04be489650cf6c32fafd6 Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Mon, 26 Jul 2010 13:51:22 -0700
+Subject: [PATCH 8/8] drm/i915: make sure we shut off the panel in eDP configs
+
+commit 5620ae29f1eabe655f44335231b580a78c8364ea upstream.
+
+Fix error from the last pull request. Making sure we shut the panel off
+is more correct and saves power.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+Signed-off-by: Stefan Bader <stefan.bader at canonical.com>
+---
+ drivers/gpu/drm/i915/intel_dp.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 40ca37a..6b62762 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -757,7 +757,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
+ intel_dp_link_down(intel_output, dp_priv->DP);
+ if (IS_eDP(intel_output)) {
+ ironlake_edp_backlight_off(dev);
+- ironlake_edp_backlight_off(dev);
++ ironlake_edp_panel_off(dev);
+ }
+ }
+ } else {
+--
+1.7.1
+
Added: dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-radeon-kms-igp-sideport-is-AMD-only.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/x86/drm-radeon-kms-igp-sideport-is-AMD-only.patch Wed Aug 11 01:10:53 2010 (r16114)
@@ -0,0 +1,103 @@
+From 241617ebf9bdc41f901dfedf6daf96cbbebb24c9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher at gmail.com>
+Date: Mon, 2 Aug 2010 19:39:15 -0400
+Subject: [PATCH 1/5] drm/radeon/kms/igp: sideport is AMD only
+
+commit 4c70b2eae371ebe83019ac47de6088b78124ab36 upstream.
+
+Intel variants don't support it.
+
+Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+Cc: stable at kernel.org
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+[bwh: Backport to 2.6.33]
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 15 ++++++---------
+ drivers/gpu/drm/radeon/radeon_combios.c | 4 ++++
+ drivers/gpu/drm/radeon/rs600.c | 1 -
+ drivers/gpu/drm/radeon/rs690.c | 2 +-
+ 4 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
+index d3d6d86..44f00b6 100644
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -1002,6 +1002,10 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
+ u8 frev, crev;
+ u16 data_offset;
+
++ /* sideport is AMD only */
++ if (rdev->family == CHIP_RS600)
++ return false;
++
+ atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+ &crev, &data_offset);
+
+@@ -1011,15 +1015,8 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
+ if (igp_info) {
+ switch (crev) {
+ case 1:
+- /* AMD IGPS */
+- if ((rdev->family == CHIP_RS690) ||
+- (rdev->family == CHIP_RS740)) {
+- if (igp_info->info.ulBootUpMemoryClock)
+- return true;
+- } else {
+- if (igp_info->info.ucMemoryType & 0xf0)
+- return true;
+- }
++ if (igp_info->info.ulBootUpMemoryClock)
++ return true;
+ break;
+ case 2:
+ if (igp_info->info_2.ucMemoryType & 0x0f)
+diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
+index f611123..f357585 100644
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -601,6 +601,10 @@ bool radeon_combios_sideport_present(struct radeon_device *rdev)
+ struct drm_device *dev = rdev->ddev;
+ u16 igp_info;
+
++ /* sideport is AMD only */
++ if (rdev->family == CHIP_RS400)
++ return false;
++
+ igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
+
+ if (igp_info) {
+diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
+index a27c09f..d9a0187 100644
+--- a/drivers/gpu/drm/radeon/rs600.c
++++ b/drivers/gpu/drm/radeon/rs600.c
+@@ -56,7 +56,6 @@ int rs600_mc_init(struct radeon_device *rdev)
+ rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
+ rdev->mc.gtt_location = 0xffffffffUL;
+ r = radeon_mc_setup(rdev);
+- rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+ if (r)
+ return r;
+ return 0;
+diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
+index 06e2771..eb4816f 100644
+--- a/drivers/gpu/drm/radeon/rs690.c
++++ b/drivers/gpu/drm/radeon/rs690.c
+@@ -150,6 +150,7 @@ void rs690_vram_info(struct radeon_device *rdev)
+ if (rdev->mc.real_vram_size > rdev->mc.aper_size)
+ rdev->mc.real_vram_size = rdev->mc.aper_size;
+
++ rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+ rs690_pm_info(rdev);
+ /* FIXME: we should enforce default clock in case GPU is not in
+ * default setup
+@@ -172,7 +173,6 @@ static int rs690_mc_init(struct radeon_device *rdev)
+ rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
+ rdev->mc.gtt_location = 0xFFFFFFFFUL;
+ r = radeon_mc_setup(rdev);
+- rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+ if (r)
+ return r;
+ return 0;
+--
+1.7.1
+
Modified: dists/sid/linux-2.6/debian/patches/series/20
==============================================================================
--- dists/sid/linux-2.6/debian/patches/series/20 Tue Aug 10 22:52:44 2010 (r16113)
+++ dists/sid/linux-2.6/debian/patches/series/20 Wed Aug 11 01:10:53 2010 (r16114)
@@ -10,3 +10,16 @@
+ features/all/V4L-DVB-Add-Elgato-EyeTV-Diversity-to-dibcom-driver.patch
+ bugfix/s390/dasd-use-correct-label-location-for-diag-fba-disks.patch
+ features/arm/orion5x-fix-soft-reset-add-include.patch
++ bugfix/x86/drm-i915-don-t-access-FW_BLC_SELF-on-965G.patch
++ bugfix/x86/drm-i915-gen3-page-flipping-fixes.patch
++ bugfix/x86/drm-i915-don-t-queue-flips-during-a-flip-pending-eve.patch
++ bugfix/x86/drm-i915-Hold-the-spinlock-whilst-resetting-unpin_wo.patch
++ bugfix/x86/drm-i915-handle-shared-framebuffers-when-flipping.patch
++ bugfix/x86/drm-i915-add-PANEL_UNLOCK_REGS-definition.patch
++ bugfix/x86/drm-i915-make-sure-eDP-panel-is-turned-on.patch
++ bugfix/x86/drm-i915-make-sure-we-shut-off-the-panel-in-eDP-conf.patch
++ bugfix/x86/drm-radeon-kms-igp-sideport-is-AMD-only.patch
++ bugfix/all/drm-radeon-add-new-pci-ids.patch
++ bugfix/all/drm-radeon-kms-flush-HDP-cache-on-GART-table-updates.patch
++ bugfix/all/drm-radeon-kms-r7xx-add-workaround-for-hw-issue-with.patch
++ bugfix/x86/drm-i915-Check-overlay-stride-errata-for-i830-and-i8.patch
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