[kernel] r15987 - in dists/sid/linux-2.6/debian: . patches/features/arm patches/series
Martin Michlmayr
tbm at alioth.debian.org
Thu Jul 15 19:45:04 UTC 2010
Author: tbm
Date: Thu Jul 15 19:45:00 2010
New Revision: 15987
Log:
Add some patches from the Orion tree, including support for Marvell's
Armada 300 (88F6282).
Added:
dists/sid/linux-2.6/debian/patches/features/arm/arm-add-pci_sys_data.patch
dists/sid/linux-2.6/debian/patches/features/arm/dns-323-add-rev-c1.patch
dists/sid/linux-2.6/debian/patches/features/arm/fix-t5325-after-mpp-update.patch
dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-88f6282-support.patch
dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-pcie1.patch
dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-f6192-f6180-add-a1-rev.patch
dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-factorize-pcie-init-code
dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-add-slab.patch
dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-blink-set.patch
dists/sid/linux-2.6/debian/patches/features/arm/marvell-phy-expose-ids.patch
dists/sid/linux-2.6/debian/patches/features/arm/mpp-update-for-f6282.patch
dists/sid/linux-2.6/debian/patches/features/arm/orion-add-rnb-line-support.patch
dists/sid/linux-2.6/debian/patches/features/arm/orion-allow-rnb-callback
dists/sid/linux-2.6/debian/patches/features/arm/orion5x-fix-soft-reset.patch
Modified:
dists/sid/linux-2.6/debian/changelog
dists/sid/linux-2.6/debian/patches/series/18
Modified: dists/sid/linux-2.6/debian/changelog
==============================================================================
--- dists/sid/linux-2.6/debian/changelog Wed Jul 14 00:56:24 2010 (r15986)
+++ dists/sid/linux-2.6/debian/changelog Thu Jul 15 19:45:00 2010 (r15987)
@@ -4,6 +4,23 @@
* iwlwifi: Allocate pages for RX buffers, reducing the probability of
allocation failure (Closes: #580124)
+ [ Martin Michlmayr ]
+ * Add some patches from the Orion tree, including support for Marvell's
+ Armada 300 (88F6282):
+ - Kirkwood: update MPP definition.
+ - Kirkwood: fix HP t5325 after updating MPP definitions
+ - leds: leds-gpio: Change blink_set callback to be able to turn off blinking
+ - net/phy/marvell: Expose IDs and flags in a .h and add dns323 LEDs setup flag
+ - orion5x: Base support for DNS-323 rev C1
+ - orion5x: Fix soft-reset for some platforms
+ - mtd: orion/kirkwood: add RnB line support to orion mtd driver
+ - mtd: kirkwood: allow machines to register RnB callback
+ - Kirkwood: add support for rev A1 of the 88f6192 and 88f6180 chips.
+ - Kirkwood: Add support for 88f6282
+ - PCI: add platform private data to pci_sys_data
+ - Kirkwood: add support for PCIe1
+ - Kirkwood: more factorization of the PCIe init code
+
-- Ben Hutchings <ben at decadent.org.uk> Wed, 14 Jul 2010 01:52:56 +0100
linux-2.6 (2.6.32-17) unstable; urgency=low
Added: dists/sid/linux-2.6/debian/patches/features/arm/arm-add-pci_sys_data.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/arm-add-pci_sys_data.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,26 @@
+From: Saeed Bishara <saeed at marvell.com>
+Date: Thu, 3 Jun 2010 11:58:46 +0000 (+0300)
+Subject: [ARM] PCI: add platform private data to pci_sys_data
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=bb50df36d2b275485c205b4fd5fc154f9de0b06a
+
+[ARM] PCI: add platform private data to pci_sys_data
+
+Add private_data pointer to the pci_sys_data, this pointer can be
+used for holding platform specific data for each pci controller.
+
+Signed-off-by: Saeed Bishara <saeed at marvell.com>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
+index 52f0da1..16330bd 100644
+--- a/arch/arm/include/asm/mach/pci.h
++++ b/arch/arm/include/asm/mach/pci.h
+@@ -37,6 +37,7 @@ struct pci_sys_data {
+ /* IRQ mapping */
+ int (*map_irq)(struct pci_dev *, u8, u8);
+ struct hw_pci *hw;
++ void *private_data; /* platform controller private data */
+ };
+
+ /*
Added: dists/sid/linux-2.6/debian/patches/features/arm/dns-323-add-rev-c1.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/dns-323-add-rev-c1.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,558 @@
+From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Date: Mon, 21 Jun 2010 03:21:53 +0000 (+1000)
+Subject: [ARM] orion5x: Base support for DNS-323 rev C1
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=b41d12ff57d2eccdb5d7563a23d70ce558377b64
+
+[ARM] orion5x: Base support for DNS-323 rev C1
+
+This patch adds the base support for this new HW revision to the existing
+dns323-setup.c file. The SoC seems to be the same as rev B1, the GPIOs
+are all wired differently though and the fan control isn't i2c based
+anymore.
+
+Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
+index fdf16e9..a47100d 100644
+--- a/arch/arm/mach-orion5x/dns323-setup.c
++++ b/arch/arm/mach-orion5x/dns323-setup.c
+@@ -3,6 +3,10 @@
+ *
+ * Copyright (C) 2007 Herbert Valerio Riedel <hvr at gnu.org>
+ *
++ * Support for HW Rev C1:
++ *
++ * Copyright (C) 2010 Benjamin Herrenschmidt <benh at kernel.crashing.org>
++ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+@@ -23,6 +27,8 @@
+ #include <linux/input.h>
+ #include <linux/i2c.h>
+ #include <linux/ata_platform.h>
++#include <linux/phy.h>
++#include <linux/marvell_phy.h>
+ #include <asm/mach-types.h>
+ #include <asm/gpio.h>
+ #include <asm/mach/arch.h>
+@@ -31,6 +37,7 @@
+ #include "common.h"
+ #include "mpp.h"
+
++/* Rev A1 and B1 */
+ #define DNS323_GPIO_LED_RIGHT_AMBER 1
+ #define DNS323_GPIO_LED_LEFT_AMBER 2
+ #define DNS323_GPIO_SYSTEM_UP 3
+@@ -42,6 +49,23 @@
+ #define DNS323_GPIO_KEY_POWER 9
+ #define DNS323_GPIO_KEY_RESET 10
+
++/* Rev C1 */
++#define DNS323C_GPIO_KEY_POWER 1
++#define DNS323C_GPIO_POWER_OFF 2
++#define DNS323C_GPIO_LED_RIGHT_AMBER 8
++#define DNS323C_GPIO_LED_LEFT_AMBER 9
++#define DNS323C_GPIO_LED_POWER 17
++#define DNS323C_GPIO_FAN_BIT1 18
++#define DNS323C_GPIO_FAN_BIT0 19
++
++/* Exposed to userspace, do not change */
++enum {
++ DNS323_REV_A1, /* 0 */
++ DNS323_REV_B1, /* 1 */
++ DNS323_REV_C1, /* 2 */
++};
++
++
+ /****************************************************************************
+ * PCI setup
+ */
+@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
+ .map_irq = dns323_pci_map_irq,
+ };
+
+-static int __init dns323_dev_id(void)
+-{
+- u32 dev, rev;
+-
+- orion5x_pcie_id(&dev, &rev);
+-
+- return dev;
+-}
+-
+ static int __init dns323_pci_init(void)
+ {
+- /* The 5182 doesn't really use its PCI bus, and initialising PCI
++ /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
+ * gets in the way of initialising the SATA controller.
+ */
+- if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
++ if (machine_is_dns323() && system_rev == DNS323_REV_A1)
+ pci_common_init(&dns323_pci);
+
+ return 0;
+@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
+ }
+
+ iounmap(mac_page);
+- printk("DNS323: Found ethernet MAC address: ");
++ printk("DNS-323: Found ethernet MAC address: ");
+ for (i = 0; i < 6; i++)
+ printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+@@ -259,7 +274,7 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
+ return 0;
+ }
+
+-static struct gpio_led dns323_leds[] = {
++static struct gpio_led dns323ab_leds[] = {
+ {
+ .name = "power:blue",
+ .gpio = DNS323_GPIO_LED_POWER2,
+@@ -275,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
+ },
+ };
+
+-static struct gpio_led_platform_data dns323_led_data = {
+- .num_leds = ARRAY_SIZE(dns323_leds),
+- .leds = dns323_leds,
++
++static struct gpio_led dns323c_leds[] = {
++ {
++ .name = "power:blue",
++ .gpio = DNS323C_GPIO_LED_POWER,
++ .default_trigger = "timer",
++ .active_low = 1,
++ }, {
++ .name = "right:amber",
++ .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
++ .active_low = 1,
++ }, {
++ .name = "left:amber",
++ .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
++ .active_low = 1,
++ },
++};
++
++
++static struct gpio_led_platform_data dns323ab_led_data = {
++ .num_leds = ARRAY_SIZE(dns323ab_leds),
++ .leds = dns323ab_leds,
++ .gpio_blink_set = dns323_gpio_blink_set,
++};
++
++static struct gpio_led_platform_data dns323c_led_data = {
++ .num_leds = ARRAY_SIZE(dns323c_leds),
++ .leds = dns323c_leds,
+ .gpio_blink_set = dns323_gpio_blink_set,
+ };
+
+@@ -285,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+- .platform_data = &dns323_led_data,
++ .platform_data = &dns323ab_led_data,
+ },
+ };
+
+@@ -293,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
+ * GPIO Attached Keys
+ */
+
+-static struct gpio_keys_button dns323_buttons[] = {
++static struct gpio_keys_button dns323ab_buttons[] = {
+ {
+ .code = KEY_RESTART,
+ .gpio = DNS323_GPIO_KEY_RESET,
+@@ -307,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
+ },
+ };
+
+-static struct gpio_keys_platform_data dns323_button_data = {
+- .buttons = dns323_buttons,
+- .nbuttons = ARRAY_SIZE(dns323_buttons),
++static struct gpio_keys_platform_data dns323ab_button_data = {
++ .buttons = dns323ab_buttons,
++ .nbuttons = ARRAY_SIZE(dns323ab_buttons),
++};
++
++static struct gpio_keys_button dns323c_buttons[] = {
++ {
++ .code = KEY_POWER,
++ .gpio = DNS323C_GPIO_KEY_POWER,
++ .desc = "Power Button",
++ .active_low = 1,
++ },
++};
++
++static struct gpio_keys_platform_data dns323c_button_data = {
++ .buttons = dns323c_buttons,
++ .nbuttons = ARRAY_SIZE(dns323c_buttons),
+ };
+
+ static struct platform_device dns323_button_device = {
+@@ -317,7 +371,7 @@ static struct platform_device dns323_button_device = {
+ .id = -1,
+ .num_resources = 0,
+ .dev = {
+- .platform_data = &dns323_button_data,
++ .platform_data = &dns323ab_button_data,
+ },
+ };
+
+@@ -331,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
+ /****************************************************************************
+ * General Setup
+ */
+-static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
++static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
+ { 0, MPP_PCIE_RST_OUTn },
+ { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
+ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
+@@ -355,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
+ { -1 },
+ };
+
+-static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
++static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
+ { 0, MPP_UNUSED },
+ { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
+ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
+@@ -379,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
+ { -1 },
+ };
+
++static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
++ { 0, MPP_GPIO }, /* ? input */
++ { 1, MPP_GPIO }, /* input power switch (0 = pressed) */
++ { 2, MPP_GPIO }, /* output power off */
++ { 3, MPP_UNUSED }, /* ? output */
++ { 4, MPP_UNUSED }, /* ? output */
++ { 5, MPP_UNUSED }, /* ? output */
++ { 6, MPP_UNUSED }, /* ? output */
++ { 7, MPP_UNUSED }, /* ? output */
++ { 8, MPP_GPIO }, /* i/o right amber LED */
++ { 9, MPP_GPIO }, /* i/o left amber LED */
++ { 10, MPP_GPIO }, /* input */
++ { 11, MPP_UNUSED },
++ { 12, MPP_SATA_LED },
++ { 13, MPP_SATA_LED },
++ { 14, MPP_SATA_LED },
++ { 15, MPP_SATA_LED },
++ { 16, MPP_UNUSED },
++ { 17, MPP_GPIO }, /* power button LED */
++ { 18, MPP_GPIO }, /* fan speed bit 0 */
++ { 19, MPP_GPIO }, /* fan speed bit 1 */
++ { -1 },
++};
++
++/* Rev C1 Fan speed notes:
++ *
++ * The fan is controlled by 2 GPIOs on this board. The settings
++ * of the bits is as follow:
++ *
++ * GPIO 18 GPIO 19 Fan
++ *
++ * 0 0 stopped
++ * 0 1 low speed
++ * 1 0 high speed
++ * 1 1 don't do that (*)
++ *
++ * (*) I think the two bits control two feed-in resistors into a fixed
++ * PWN circuit, setting both bits will basically go a 'bit' faster
++ * than high speed, but d-link doesn't do it and you may get out of
++ * HW spec so don't do it.
++ */
++
+ /*
+- * On the DNS-323 the following devices are attached via I2C:
++ * On the DNS-323 A1 and B1 the following devices are attached via I2C:
+ *
+ * i2c addr | chip | description
+ * 0x3e | GMT G760Af | fan speed PWM controller
+ * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
+ * 0x68 | ST M41T80 | RTC w/ alarm
+ */
+-static struct i2c_board_info __initdata dns323_i2c_devices[] = {
++static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("g760a", 0x3e),
+ }, {
+@@ -397,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
+ },
+ };
+
++/*
++ * On the DNS-323 C1 the following devices are attached via I2C:
++ *
++ * i2c addr | chip | description
++ * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
++ * 0x68 | ST M41T80 | RTC w/ alarm
++ */
++static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("lm75", 0x48),
++ }, {
++ I2C_BOARD_INFO("m41t80", 0x68),
++ },
++};
++
+ /* DNS-323 rev. A specific power off method */
+ static void dns323a_power_off(void)
+ {
+- pr_info("%s: triggering power-off...\n", __func__);
++ pr_info("DNS-323: Triggering power-off...\n");
+ gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
+ }
+
+ /* DNS-323 rev B specific power off method */
+ static void dns323b_power_off(void)
+ {
+- pr_info("%s: triggering power-off...\n", __func__);
++ pr_info("DNS-323: Triggering power-off...\n");
+ /* Pin has to be changed to 1 and back to 0 to do actual power off. */
+ gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
+ mdelay(100);
+ gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
+ }
+
++/* DNS-323 rev. C specific power off method */
++static void dns323c_power_off(void)
++{
++ pr_info("DNS-323: Triggering power-off...\n");
++ gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
++}
++
++static int dns323c_phy_fixup(struct phy_device *phy)
++{
++ phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
++
++ return 0;
++}
++
++static int __init dns323_identify_rev(void)
++{
++ u32 dev, rev, i, reg;
++
++ pr_debug("DNS-323: Identifying board ... \n");
++
++ /* Rev A1 has a 5181 */
++ orion5x_pcie_id(&dev, &rev);
++ if (dev == MV88F5181_DEV_ID) {
++ pr_debug("DNS-323: 5181 found, board is A1\n");
++ return DNS323_REV_A1;
++ }
++ pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
++
++ /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
++ * a bit gross but we want to do that without links into the eth
++ * driver so let's poke at it directly. We default to rev B1 in
++ * case the accesses fail
++ */
++
++#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
++#define SMI_BUSY 0x10000000
++#define SMI_READ_VALID 0x08000000
++#define SMI_OPCODE_READ 0x04000000
++#define SMI_OPCODE_WRITE 0x00000000
++
++ for (i = 0; i < 1000; i++) {
++ reg = readl(ETH_SMI_REG);
++ if (!(reg & SMI_BUSY))
++ break;
++ }
++ if (i >= 1000) {
++ pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
++ return DNS323_REV_B1;
++ }
++ writel((3 << 21) /* phy ID reg */ |
++ (8 << 16) /* phy addr */ |
++ SMI_OPCODE_READ, ETH_SMI_REG);
++ for (i = 0; i < 1000; i++) {
++ reg = readl(ETH_SMI_REG);
++ if (reg & SMI_READ_VALID)
++ break;
++ }
++ if (i >= 1000) {
++ pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
++ return DNS323_REV_B1;
++ }
++ pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
++
++ /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
++ * but I don't see that making a difference here, at least with
++ * any known Marvell PHY ID
++ */
++ switch(reg & 0xfff0) {
++ case 0x0cc0: /* MV88E1111 */
++ return DNS323_REV_B1;
++ case 0x0e10: /* MV88E1118 */
++ return DNS323_REV_C1;
++ default:
++ pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
++ reg & 0xffff);
++ }
++ return DNS323_REV_B1;
++}
++
+ static void __init dns323_init(void)
+ {
+ /* Setup basic Orion functions. Need to be called early. */
+ orion5x_init();
+
++ /* Identify revision */
++ system_rev = dns323_identify_rev();
++ pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
++
+ /* Just to be tricky, the 5182 has a completely different
+ * set of MPP modes to the 5181.
+ */
+- if (dns323_dev_id() == MV88F5182_DEV_ID)
+- orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
+- else {
+- orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
++ switch(system_rev) {
++ case DNS323_REV_A1:
++ orion5x_mpp_conf(dns323a_mpp_modes);
+ writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
++ break;
++ case DNS323_REV_B1:
++ orion5x_mpp_conf(dns323b_mpp_modes);
++ break;
++ case DNS323_REV_C1:
++ orion5x_mpp_conf(dns323c_mpp_modes);
++ break;
+ }
+
+ /* setup flash mapping
+@@ -435,53 +635,96 @@ static void __init dns323_init(void)
+ orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
+ platform_device_register(&dns323_nor_flash);
+
+- /* The 5181 power LED is active low and requires
+- * DNS323_GPIO_LED_POWER1 to also be low.
+- */
+- if (dns323_dev_id() == MV88F5181_DEV_ID) {
+- dns323_leds[0].active_low = 1;
+- gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
+- gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
++ /* Sort out LEDs, Buttons and i2c devices */
++ switch(system_rev) {
++ case DNS323_REV_A1:
++ /* The 5181 power LED is active low and requires
++ * DNS323_GPIO_LED_POWER1 to also be low.
++ */
++ dns323ab_leds[0].active_low = 1;
++ gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
++ gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
++ /* Fall through */
++ case DNS323_REV_B1:
++ i2c_register_board_info(0, dns323ab_i2c_devices,
++ ARRAY_SIZE(dns323ab_i2c_devices));
++ break;
++ case DNS323_REV_C1:
++ /* Hookup LEDs & Buttons */
++ dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
++ dns323_button_device.dev.platform_data = &dns323c_button_data;
++
++ /* Hookup i2c devices and fan driver */
++ i2c_register_board_info(0, dns323c_i2c_devices,
++ ARRAY_SIZE(dns323c_i2c_devices));
++ platform_device_register_simple("dns323c-fan", 0, NULL, 0);
++
++ /* Register fixup for the PHY LEDs */
++ phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
++ MARVELL_PHY_ID_MASK,
++ dns323c_phy_fixup);
+ }
+
+ platform_device_register(&dns323_gpio_leds);
+-
+ platform_device_register(&dns323_button_device);
+
+- i2c_register_board_info(0, dns323_i2c_devices,
+- ARRAY_SIZE(dns323_i2c_devices));
+-
+ /*
+ * Configure peripherals.
+ */
+ if (dns323_read_mac_addr() < 0)
+- printk("DNS323: Failed to read MAC address\n");
+-
++ printk("DNS-323: Failed to read MAC address\n");
+ orion5x_ehci0_init();
+ orion5x_eth_init(&dns323_eth_data);
+ orion5x_i2c_init();
+ orion5x_uart0_init();
+
+- /* The 5182 has its SATA controller on-chip, and needs its own little
+- * init routine.
+- */
+- if (dns323_dev_id() == MV88F5182_DEV_ID)
++ /* Remaining GPIOs */
++ switch(system_rev) {
++ case DNS323_REV_A1:
++ /* Poweroff GPIO */
++ if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
++ gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
++ pr_err("DNS-323: failed to setup power-off GPIO\n");
++ pm_power_off = dns323a_power_off;
++ break;
++ case DNS323_REV_B1:
++ /* 5182 built-in SATA init */
+ orion5x_sata_init(&dns323_sata_data);
+
+- /* The 5182 has flag to indicate the system is up. Without this flag
+- * set, power LED will flash and cannot be controlled via leds-gpio.
+- */
+- if (dns323_dev_id() == MV88F5182_DEV_ID)
+- gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
+-
+- /* Register dns323 specific power-off method */
+- if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+- gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+- pr_err("DNS323: failed to setup power-off GPIO\n");
+- if (dns323_dev_id() == MV88F5182_DEV_ID)
++ /* The DNS323 rev B1 has flag to indicate the system is up.
++ * Without this flag set, power LED will flash and cannot be
++ * controlled via leds-gpio.
++ */
++ if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
++ gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
++
++ /* Poweroff GPIO */
++ if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
++ gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
++ pr_err("DNS-323: failed to setup power-off GPIO\n");
+ pm_power_off = dns323b_power_off;
+- else
+- pm_power_off = dns323a_power_off;
++ break;
++ case DNS323_REV_C1:
++ /* 5182 built-in SATA init */
++ orion5x_sata_init(&dns323_sata_data);
++
++ /* Poweroff GPIO */
++ if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
++ gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
++ pr_err("DNS-323: failed to setup power-off GPIO\n");
++ pm_power_off = dns323c_power_off;
++
++ /* Now, -this- should theorically be done by the sata_mv driver
++ * once I figure out what's going on there. Maybe the behaviour
++ * of the LEDs should be somewhat passed via the platform_data.
++ * for now, just whack the register and make the LEDs happy
++ *
++ * Note: AFAIK, rev B1 needs the same treatement but I'll let
++ * somebody else test it.
++ */
++ writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
++ break;
++ }
+ }
+
+ /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
Added: dists/sid/linux-2.6/debian/patches/features/arm/fix-t5325-after-mpp-update.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/fix-t5325-after-mpp-update.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,42 @@
+From: Nicolas Pitre <nico at fluxnic.net>
+Date: Tue, 22 Jun 2010 03:29:28 +0000 (-0400)
+Subject: [ARM] Kirkwood: fix HP t5325 after commit 6605742f2a
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=603a42b2689ae55c7ba7094126909a31bef67e32
+
+[ARM] Kirkwood: fix HP t5325 after commit 6605742f2a
+
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
+index ad1e0f1..6a94daa 100644
+--- a/arch/arm/mach-kirkwood/t5325-setup.c
++++ b/arch/arm/mach-kirkwood/t5325-setup.c
+@@ -114,8 +114,8 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+- MPP8_TW_SDA,
+- MPP9_TW_SCK,
++ MPP8_TW0_SDA,
++ MPP9_TW0_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+@@ -131,11 +131,11 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP32_GPIO,
+- MPP33_GE1_13,
+- MPP39_AUDIO_I2SBCLK,
+- MPP40_AUDIO_I2SDO,
+- MPP41_AUDIO_I2SLRC,
+- MPP42_AUDIO_I2SMCLK,
++ MPP33_GE1_TXCTL,
++ MPP39_AU_I2SBCLK,
++ MPP40_AU_I2SDO,
++ MPP41_AU_I2SLRCLK,
++ MPP42_AU_I2SMCLK,
+ MPP45_GPIO, /* Power button */
+ MPP48_GPIO, /* Board power off */
+ 0
Added: dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-88f6282-support.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-88f6282-support.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,78 @@
+From: Saeed Bishara <saeed at marvell.com>
+Date: Tue, 1 Jun 2010 15:09:27 +0000 (+0300)
+Subject: [ARM] Kirkwood: Add support for 88f6282
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=33d30695fba469517a172001c43e0c21fa0b82b5
+
+[ARM] Kirkwood: Add support for 88f6282
+
+The 6282 SoC is compatible to 6280 and features faster CPU, DDR3, additional
+PCIe interface, and LCD controller. More information can be found here:
+http://www.marvell.com/products/processors/embedded/armada_300/armada_310.pdf
+
+Signed-off-by: Saeed Bishara <saeed at marvell.com>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
+index c780c4a..4ccfdf9 100644
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -402,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
+ u32 dev, rev;
+
+ kirkwood_pcie_id(&dev, &rev);
+- if (rev == 0) /* catch all Kirkwood Z0's */
++ if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
+ mvsdio_data->clock = 100000000;
+ else
+ mvsdio_data->clock = 200000000;
+@@ -847,8 +847,10 @@ int __init kirkwood_find_tclk(void)
+ u32 dev, rev;
+
+ kirkwood_pcie_id(&dev, &rev);
+- if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+- rev == MV88F6281_REV_A1))
++
++ if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
++ rev == MV88F6281_REV_A1)) ||
++ (dev == MV88F6282_DEV_ID))
+ return 200000000;
+
+ return 166666667;
+@@ -902,6 +904,11 @@ static char * __init kirkwood_id(void)
+ return "MV88F6180-Rev-A1";
+ else
+ return "MV88F6180-Rev-Unsupported";
++ } else if (dev == MV88F6282_DEV_ID) {
++ if (rev == MV88F6282_REV_A0)
++ return "MV88F6282-Rev-A0";
++ else
++ return "MV88F6282-Rev-Unsupported";
+ } else {
+ return "Device-Unknown";
+ }
+diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+index d61b9aa..dd7eddb 100644
+--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
++++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+@@ -113,4 +113,6 @@
+ #define MV88F6180_REV_A0 2
+ #define MV88F6180_REV_A1 3
+
++#define MV88F6282_DEV_ID 0x6282
++#define MV88F6282_REV_A0 0
+ #endif
+diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
+index a5900f6..065187d 100644
+--- a/arch/arm/mach-kirkwood/mpp.c
++++ b/arch/arm/mach-kirkwood/mpp.c
+@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
+
+ kirkwood_pcie_id(&dev, &rev);
+
+- if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
++ if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
++ (dev == MV88F6282_DEV_ID))
+ return MPP_F6281_MASK;
+ if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
+ return MPP_F6192_MASK;
Added: dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-pcie1.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-add-pcie1.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,637 @@
+From: Saeed Bishara <saeed at marvell.com>
+Date: Tue, 8 Jun 2010 11:21:34 +0000 (+0300)
+Subject: [ARM] Kirkwood: add support for PCIe1
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=5ced0d7e0ea58a353923a49974d091460719fe04
+
+[ARM] Kirkwood: add support for PCIe1
+
+This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.
+
+Signed-off-by: Saeed Bishara <saeed at marvell.com>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
+index 2e69168..8d03bce 100644
+--- a/arch/arm/mach-kirkwood/addr-map.c
++++ b/arch/arm/mach-kirkwood/addr-map.c
+@@ -31,6 +31,8 @@
+ #define ATTR_DEV_CS0 0x3e
+ #define ATTR_PCIE_IO 0xe0
+ #define ATTR_PCIE_MEM 0xe8
++#define ATTR_PCIE1_IO 0xd0
++#define ATTR_PCIE1_MEM 0xd8
+ #define ATTR_SRAM 0x01
+
+ /*
+@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
+ TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
+ setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+ TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
++ setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
++ TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
++ setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
++ TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
+
+ /*
+ * Setup window for NAND controller.
+ */
+- setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
++ setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+ TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
+
+ /*
+ * Setup window for SRAM.
+ */
+- setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
++ setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+ TARGET_SRAM, ATTR_SRAM, -1);
+
+ /*
+diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
+index 4ccfdf9..9dd67c7 100644
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
+ .length = KIRKWOOD_PCIE_IO_SIZE,
+ .type = MT_DEVICE,
+ }, {
++ .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
++ .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
++ .length = KIRKWOOD_PCIE1_IO_SIZE,
++ .type = MT_DEVICE,
++ }, {
+ .virtual = KIRKWOOD_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
+ .length = KIRKWOOD_REGS_SIZE,
+@@ -960,12 +965,14 @@ void __init kirkwood_init(void)
+ static int __init kirkwood_clock_gate(void)
+ {
+ unsigned int curr = readl(CLOCK_GATING_CTRL);
++ u32 dev, rev;
+
++ kirkwood_pcie_id(&dev, &rev);
+ printk(KERN_DEBUG "Gating clock of unused units\n");
+ printk(KERN_DEBUG "before: 0x%08x\n", curr);
+
+ /* Make sure those units are accessible */
+- writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
++ writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
+
+ /* For SATA: first shutdown the phy */
+ if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
+@@ -990,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
+ writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
+ }
+
++ /* For PCIe 1: first shutdown the phy */
++ if (dev == MV88F6282_DEV_ID) {
++ if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
++ writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
++ while (1)
++ if (readl(PCIE1_STATUS) & 0x1)
++ break;
++ writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
++ }
++ } else /* keep this bit set for devices that don't have PCIe1 */
++ kirkwood_clk_ctrl |= CGC_PEX1;
++
+ /* Now gate clock the required units */
+ writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
+ printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
+diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
+index 05e8a8a..5b2c1c1 100644
+--- a/arch/arm/mach-kirkwood/common.h
++++ b/arch/arm/mach-kirkwood/common.h
+@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
+ struct mtd_partition;
+ struct mtd_info;
+
++#define KW_PCIE0 (1 << 0)
++#define KW_PCIE1 (1 << 1)
++
+ /*
+ * Basic Kirkwood init functions used early by machine-setup.
+ */
+@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
+ void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+ void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
+ void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
+-void kirkwood_pcie_init(void);
++void kirkwood_pcie_init(unsigned int portmask);
+ void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
+ void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
+ void kirkwood_spi_init(void);
+diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+index db93504..16f6691 100644
+--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
++++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
+
+ static int __init db88f6281_pci_init(void)
+ {
+- if (machine_is_db88f6281_bp())
+- kirkwood_pcie_init();
++ if (machine_is_db88f6281_bp()) {
++ u32 dev, rev;
+
++ kirkwood_pcie_id(&dev, &rev);
++ if (dev == MV88F6282_DEV_ID)
++ kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
++ else
++ kirkwood_pcie_init(KW_PCIE0);
++ }
+ return 0;
+ }
+ subsys_initcall(db88f6281_pci_init);
+diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+index 418f501..aff0e13 100644
+--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
++++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+@@ -59,8 +59,9 @@
+ #define CGC_SATA1 (1 << 15)
+ #define CGC_XOR1 (1 << 16)
+ #define CGC_CRYPTO (1 << 17)
++#define CGC_PEX1 (1 << 18)
+ #define CGC_GE1 (1 << 19)
+ #define CGC_TDM (1 << 20)
+-#define CGC_RESERVED ((1 << 18) | (0x6 << 21))
++#define CGC_RESERVED (0x6 << 21)
+
+ #endif
+diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
+index f00a0a4..9da2eb5 100644
+--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
++++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
+@@ -23,6 +23,7 @@
+ #define IRQ_KIRKWOOD_XOR_10 7
+ #define IRQ_KIRKWOOD_XOR_11 8
+ #define IRQ_KIRKWOOD_PCIE 9
++#define IRQ_KIRKWOOD_PCIE1 10
+ #define IRQ_KIRKWOOD_GE00_SUM 11
+ #define IRQ_KIRKWOOD_GE01_SUM 15
+ #define IRQ_KIRKWOOD_USB 19
+diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+index dd7eddb..d141af4 100644
+--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
++++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+@@ -16,36 +16,48 @@
+ * Marvell Kirkwood address maps.
+ *
+ * phys
+- * e0000000 PCIe Memory space
++ * e0000000 PCIe #0 Memory space
++ * e8000000 PCIe #1 Memory space
+ * f1000000 on-chip peripheral registers
+- * f2000000 PCIe I/O space
+- * f3000000 NAND controller address window
+- * f4000000 Security Accelerator SRAM
++ * f2000000 PCIe #0 I/O space
++ * f3000000 PCIe #1 I/O space
++ * f4000000 NAND controller address window
++ * f5000000 Security Accelerator SRAM
+ *
+ * virt phys size
+- * fee00000 f1000000 1M on-chip peripheral registers
+- * fef00000 f2000000 1M PCIe I/O space
++ * fed00000 f1000000 1M on-chip peripheral registers
++ * fee00000 f2000000 1M PCIe #0 I/O space
++ * fef00000 f3000000 1M PCIe #1 I/O space
+ */
+
+-#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000
++#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
+ #define KIRKWOOD_SRAM_SIZE SZ_2K
+
+-#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
++#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
+ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K
+
++#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
++#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
++#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
++#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
++
+ #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
+-#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
++#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
+ #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
+ #define KIRKWOOD_PCIE_IO_SIZE SZ_1M
+
+ #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
+-#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
++#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
+ #define KIRKWOOD_REGS_SIZE SZ_1M
+
+ #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
+ #define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
+ #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
+
++#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
++#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
++#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
++
+ /*
+ * Register Map
+ */
+@@ -72,6 +84,9 @@
+ #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+ #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
+ #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
++#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
++#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
++#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
+
+ #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+
+diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+index 5e6f711..c6b92b4 100644
+--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
++++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
+ static int __init mv88f6281gtw_ge_pci_init(void)
+ {
+ if (machine_is_mv88f6281gtw_ge())
+- kirkwood_pcie_init();
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
+index a481036..fd64cd2 100644
+--- a/arch/arm/mach-kirkwood/openrd-setup.c
++++ b/arch/arm/mach-kirkwood/openrd-setup.c
+@@ -93,7 +93,7 @@
+ if (machine_is_openrd_base() ||
+ machine_is_openrd_client() ||
+ machine_is_openrd_ultimate())
+- kirkwood_pcie_init();
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
+index dee1eff..49c4fc6 100644
+--- a/arch/arm/mach-kirkwood/pcie.c
++++ b/arch/arm/mach-kirkwood/pcie.c
+@@ -17,29 +17,43 @@
+ #include <mach/bridge-regs.h>
+ #include "common.h"
+
++void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
++{
++ *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
++ *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
++}
+
+-#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
++struct pcie_port {
++ u8 root_bus_nr;
++ void __iomem *base;
++ spinlock_t conf_lock;
++ int irq;
++ struct resource res[2];
++};
+
+-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
++static int pcie_port_map[2];
++static int num_pcie_ports;
++
++static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
+ {
+- *dev = orion_pcie_dev_id(PCIE_BASE);
+- *rev = orion_pcie_rev(PCIE_BASE);
++ struct pci_sys_data *sys = bus->sysdata;
++ return sys->private_data;
+ }
+
+-static int pcie_valid_config(int bus, int dev)
++static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+ {
+ /*
+ * Don't go out when trying to access --
+ * 1. nonexisting device on local bus
+ * 2. where there's no device connected (no link)
+ */
+- if (bus == 0 && dev == 0)
++ if (bus == pp->root_bus_nr && dev == 0)
+ return 1;
+
+- if (!orion_pcie_link_up(PCIE_BASE))
++ if (!orion_pcie_link_up(pp->base))
+ return 0;
+
+- if (bus == 0 && dev != 1)
++ if (bus == pp->root_bus_nr && dev != 1)
+ return 0;
+
+ return 1;
+@@ -51,22 +65,22 @@ static int pcie_valid_config(int bus, int dev)
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
+
+ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+ {
++ struct pcie_port *pp = bus_to_port(bus);
+ unsigned long flags;
+ int ret;
+
+- if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
++ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+- spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+- ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+- spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
++ spin_lock_irqsave(&pp->conf_lock, flags);
++ ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
++ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+ }
+@@ -74,15 +88,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 val)
+ {
++ struct pcie_port *pp = bus_to_port(bus);
+ unsigned long flags;
+ int ret;
+
+- if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
++ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+- ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+- spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
++ spin_lock_irqsave(&pp->conf_lock, flags);
++ ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
++ spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+ }
+@@ -92,50 +107,112 @@ static struct pci_ops pcie_ops = {
+ .write = pcie_wr_conf,
+ };
+
+-
+-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
++static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
+ {
+- struct resource *res;
+- extern unsigned int kirkwood_clk_ctrl;
++ struct pcie_port *pp = (struct pcie_port *)sys->private_data;
+
+ /*
+- * Generic PCIe unit setup.
++ * IORESOURCE_IO
+ */
+- orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
++ pp->res[0].name = "PCIe 0 I/O Space";
++ pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
++ pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
++ pp->res[0].flags = IORESOURCE_IO;
++ if (request_resource(&ioport_resource, &pp->res[0]))
++ panic("Request PCIe 0 IO resource failed\n");
++ sys->resource[0] = &pp->res[0];
+
+ /*
+- * Request resources.
++ * IORESOURCE_MEM
+ */
+- res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+- if (!res)
+- panic("pcie_setup unable to alloc resources");
++ pp->res[1].name = "PCIe 0 MEM";
++ pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
++ pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
++ pp->res[1].flags = IORESOURCE_MEM;
++ if (request_resource(&iomem_resource, &pp->res[1]))
++ panic("Request PCIe 0 Memory resource failed\n");
++ sys->resource[1] = &pp->res[1];
++
++ sys->resource[2] = NULL;
++ sys->io_offset = 0;
++
++ return 1;
++}
++
++static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
++{
++ struct pcie_port *pp = (struct pcie_port *)sys->private_data;
+
+ /*
+ * IORESOURCE_IO
+ */
+- res[0].name = "PCIe I/O Space";
+- res[0].flags = IORESOURCE_IO;
+- res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
+- res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+- if (request_resource(&ioport_resource, &res[0]))
+- panic("Request PCIe IO resource failed\n");
+- sys->resource[0] = &res[0];
++ pp->res[0].name = "PCIe 1 I/O Space";
++ pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
++ pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
++ pp->res[0].flags = IORESOURCE_IO;
++ if (request_resource(&ioport_resource, &pp->res[0]))
++ panic("Request PCIe 1 IO resource failed\n");
++ sys->resource[0] = &pp->res[0];
+
+ /*
+ * IORESOURCE_MEM
+ */
+- res[1].name = "PCIe Memory Space";
+- res[1].flags = IORESOURCE_MEM;
+- res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
+- res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+- if (request_resource(&iomem_resource, &res[1]))
+- panic("Request PCIe Memory resource failed\n");
+- sys->resource[1] = &res[1];
++ pp->res[1].name = "PCIe 1 MEM";
++ pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
++ pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
++ pp->res[1].flags = IORESOURCE_MEM;
++ if (request_resource(&iomem_resource, &pp->res[1]))
++ panic("Request PCIe 1 Memory resource failed\n");
++ sys->resource[1] = &pp->res[1];
+
+ sys->resource[2] = NULL;
+ sys->io_offset = 0;
+
+- kirkwood_clk_ctrl |= CGC_PEX0;
++ return 1;
++}
++
++static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++ extern unsigned int kirkwood_clk_ctrl;
++ struct pcie_port *pp;
++ int index;
++
++ if (nr >= num_pcie_ports)
++ return 0;
++
++ index = pcie_port_map[nr];
++ printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
++
++ pp = kzalloc(sizeof(*pp), GFP_KERNEL);
++ if (!pp)
++ panic("PCIe: failed to allocate pcie_port data");
++ sys->private_data = pp;
++ pp->root_bus_nr = sys->busnr;
++ spin_lock_init(&pp->conf_lock);
++
++ switch (index) {
++ case 0:
++ pp->base = (void __iomem *)PCIE_VIRT_BASE;
++ pp->irq = IRQ_KIRKWOOD_PCIE;
++ kirkwood_clk_ctrl |= CGC_PEX0;
++ pcie0_ioresources_setup(sys);
++ break;
++ case 1:
++ pp->base = (void __iomem *)PCIE1_VIRT_BASE;
++ pp->irq = IRQ_KIRKWOOD_PCIE1;
++ kirkwood_clk_ctrl |= CGC_PEX1;
++ pcie1_ioresources_setup(sys);
++ break;
++ default:
++ panic("PCIe setup: invalid controller");
++ }
++
++ /*
++ * Generic PCIe unit setup.
++ */
++ orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
++
++ orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
+
+ return 1;
+ }
+@@ -162,7 +239,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+ {
+ struct pci_bus *bus;
+
+- if (nr == 0) {
++ if (nr < num_pcie_ports) {
+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ } else {
+ bus = NULL;
+@@ -174,18 +251,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+
+ static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+ {
+- return IRQ_KIRKWOOD_PCIE;
++ struct pcie_port *pp = bus_to_port(dev->bus);
++
++ return pp->irq;
+ }
+
+ static struct hw_pci kirkwood_pci __initdata = {
+- .nr_controllers = 1,
+ .swizzle = pci_std_swizzle,
+ .setup = kirkwood_pcie_setup,
+ .scan = kirkwood_pcie_scan_bus,
+ .map_irq = kirkwood_pcie_map_irq,
+ };
+
+-void __init kirkwood_pcie_init(void)
++static void __init add_pcie_port(int index, unsigned long base)
++{
++ printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
++
++ if (orion_pcie_link_up((void __iomem *)base)) {
++ printk(KERN_INFO "link up\n");
++ pcie_port_map[num_pcie_ports++] = index;
++ } else
++ printk(KERN_INFO "link down, ignoring\n");
++}
++
++void __init kirkwood_pcie_init(unsigned int portmask)
+ {
++ if (portmask & KW_PCIE0)
++ add_pcie_port(0, PCIE_VIRT_BASE);
++
++ if (portmask & KW_PCIE1)
++ add_pcie_port(1, PCIE1_VIRT_BASE);
++
++ kirkwood_pci.nr_controllers = num_pcie_ports;
+ pci_common_init(&kirkwood_pci);
+ }
+diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+index 3bf6304..c34718c 100644
+--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
++++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+@@ -65,7 +65,7 @@ static void __init rd88f6192_init(void)
+ static int __init rd88f6192_pci_init(void)
+ {
+ if (machine_is_rd88f6192_nas())
+- kirkwood_pcie_init();
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
+index 31708dd..3d14771 100644
+--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
++++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
+@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
+ static int __init rd88f6281_pci_init(void)
+ {
+ if (machine_is_rd88f6281())
+- kirkwood_pcie_init();
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
+index 6a94daa..d01bf89 100644
+--- a/arch/arm/mach-kirkwood/t5325-setup.c
++++ b/arch/arm/mach-kirkwood/t5325-setup.c
+@@ -176,7 +176,7 @@ static void __init hp_t5325_init(void)
+ static int __init hp_t5325_pci_init(void)
+ {
+ if (machine_is_t5325())
+- kirkwood_pcie_init();
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
+diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
+index 063979d..a5bd7fd 100644
+--- a/arch/arm/mach-kirkwood/ts219-setup.c
++++ b/arch/arm/mach-kirkwood/ts219-setup.c
+@@ -210,10 +210,10 @@ static void __init qnap_ts219_init(void)
+
+ static int __init ts219_pci_init(void)
+ {
+- if (machine_is_ts219())
+- kirkwood_pcie_init();
++ if (machine_is_ts219())
++ kirkwood_pcie_init(KW_PCIE0);
+
+- return 0;
++ return 0;
+ }
+ subsys_initcall(ts219_pci_init);
+
+diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
+index e9d85d7..2e14afe 100644
+--- a/arch/arm/mach-kirkwood/ts41x-setup.c
++++ b/arch/arm/mach-kirkwood/ts41x-setup.c
+@@ -239,8 +239,8 @@
+
+ static int __init ts41x_pci_init(void)
+ {
+- if (machine_is_ts41x())
+- kirkwood_pcie_init();
++ if (machine_is_ts41x())
++ kirkwood_pcie_init(KW_PCIE0);
+
+ return 0;
+ }
Added: dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-f6192-f6180-add-a1-rev.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-f6192-f6180-add-a1-rev.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,46 @@
+From: Saeed Bishara <saeed at marvell.com>
+Date: Tue, 1 Jun 2010 15:09:26 +0000 (+0300)
+Subject: [ARM] Kirkwood: add support for rev A1 of the 88f6192 and 88f6180 chips.
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=c0eb6394f0aaae6abc172d278feebb94b3a8624f
+
+[ARM] Kirkwood: add support for rev A1 of the 88f6192 and 88f6180 chips.
+
+Signed-off-by: Saeed Bishara <saeed at marvell.com>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
+index 6072eaa..c780c4a 100644
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -891,11 +891,15 @@ static char * __init kirkwood_id(void)
+ return "MV88F6192-Z0";
+ else if (rev == MV88F6192_REV_A0)
+ return "MV88F6192-A0";
++ else if (rev == MV88F6192_REV_A1)
++ return "MV88F6192-A1";
+ else
+ return "MV88F6192-Rev-Unsupported";
+ } else if (dev == MV88F6180_DEV_ID) {
+ if (rev == MV88F6180_REV_A0)
+ return "MV88F6180-Rev-A0";
++ else if (rev == MV88F6180_REV_A1)
++ return "MV88F6180-Rev-A1";
+ else
+ return "MV88F6180-Rev-Unsupported";
+ } else {
+diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+index a15cf0e..d61b9aa 100644
+--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
++++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+@@ -107,8 +107,10 @@
+ #define MV88F6192_DEV_ID 0x6192
+ #define MV88F6192_REV_Z0 0
+ #define MV88F6192_REV_A0 2
++#define MV88F6192_REV_A1 3
+
+ #define MV88F6180_DEV_ID 0x6180
+ #define MV88F6180_REV_A0 2
++#define MV88F6180_REV_A1 3
+
+ #endif
Added: dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-factorize-pcie-init-code
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/kirkwood-factorize-pcie-init-code Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,120 @@
+From: Nicolas Pitre <nico at fluxnic.net>
+Date: Mon, 5 Jul 2010 17:59:56 +0000 (-0400)
+Subject: [ARM] Kirkwood: more factorization of the PCIe init code
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=8a04d063c4e21fae8b290f89588ef59c46b1bf45
+
+[ARM] Kirkwood: more factorization of the PCIe init code
+
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
+index 49c4fc6..55e7f00 100644
+--- a/arch/arm/mach-kirkwood/pcie.c
++++ b/arch/arm/mach-kirkwood/pcie.c
+@@ -107,9 +107,10 @@ static struct pci_ops pcie_ops = {
+ .write = pcie_wr_conf,
+ };
+
+-static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
++static void __init pcie0_ioresources_init(struct pcie_port *pp)
+ {
+- struct pcie_port *pp = (struct pcie_port *)sys->private_data;
++ pp->base = (void __iomem *)PCIE_VIRT_BASE;
++ pp->irq = IRQ_KIRKWOOD_PCIE;
+
+ /*
+ * IORESOURCE_IO
+@@ -118,9 +119,6 @@ static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
+ pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+ pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+ pp->res[0].flags = IORESOURCE_IO;
+- if (request_resource(&ioport_resource, &pp->res[0]))
+- panic("Request PCIe 0 IO resource failed\n");
+- sys->resource[0] = &pp->res[0];
+
+ /*
+ * IORESOURCE_MEM
+@@ -129,19 +127,12 @@ static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
+ pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+ pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+ pp->res[1].flags = IORESOURCE_MEM;
+- if (request_resource(&iomem_resource, &pp->res[1]))
+- panic("Request PCIe 0 Memory resource failed\n");
+- sys->resource[1] = &pp->res[1];
+-
+- sys->resource[2] = NULL;
+- sys->io_offset = 0;
+-
+- return 1;
+ }
+
+-static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
++static void __init pcie1_ioresources_init(struct pcie_port *pp)
+ {
+- struct pcie_port *pp = (struct pcie_port *)sys->private_data;
++ pp->base = (void __iomem *)PCIE1_VIRT_BASE;
++ pp->irq = IRQ_KIRKWOOD_PCIE1;
+
+ /*
+ * IORESOURCE_IO
+@@ -150,9 +141,6 @@ static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
+ pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+ pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+ pp->res[0].flags = IORESOURCE_IO;
+- if (request_resource(&ioport_resource, &pp->res[0]))
+- panic("Request PCIe 1 IO resource failed\n");
+- sys->resource[0] = &pp->res[0];
+
+ /*
+ * IORESOURCE_MEM
+@@ -161,14 +149,6 @@ static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
+ pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+ pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+ pp->res[1].flags = IORESOURCE_MEM;
+- if (request_resource(&iomem_resource, &pp->res[1]))
+- panic("Request PCIe 1 Memory resource failed\n");
+- sys->resource[1] = &pp->res[1];
+-
+- sys->resource[2] = NULL;
+- sys->io_offset = 0;
+-
+- return 1;
+ }
+
+ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+@@ -192,21 +172,27 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+
+ switch (index) {
+ case 0:
+- pp->base = (void __iomem *)PCIE_VIRT_BASE;
+- pp->irq = IRQ_KIRKWOOD_PCIE;
+ kirkwood_clk_ctrl |= CGC_PEX0;
+- pcie0_ioresources_setup(sys);
++ pcie0_ioresources_init(pp);
+ break;
+ case 1:
+- pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+- pp->irq = IRQ_KIRKWOOD_PCIE1;
+ kirkwood_clk_ctrl |= CGC_PEX1;
+- pcie1_ioresources_setup(sys);
++ pcie1_ioresources_init(pp);
+ break;
+ default:
+- panic("PCIe setup: invalid controller");
++ panic("PCIe setup: invalid controller %d", index);
+ }
+
++ if (request_resource(&ioport_resource, &pp->res[0]))
++ panic("Request PCIe%d IO resource failed\n", index);
++ if (request_resource(&iomem_resource, &pp->res[1]))
++ panic("Request PCIe%d Memory resource failed\n", index);
++
++ sys->resource[0] = &pp->res[0];
++ sys->resource[1] = &pp->res[1];
++ sys->resource[2] = NULL;
++ sys->io_offset = 0;
++
+ /*
+ * Generic PCIe unit setup.
+ */
Added: dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-add-slab.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-add-slab.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,110 @@
+From: Tejun Heo <tj at kernel.org>
+Date: Wed, 24 Mar 2010 08:04:11 +0000 (+0900)
+Subject: include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
+X-Git-Tag: v2.6.34-rc4~71^2~5
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=5a0e3ad6af8660be21ca98a971cd00f331318c05
+
+include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
+
+percpu.h is included by sched.h and module.h and thus ends up being
+included when building most .c files. percpu.h includes slab.h which
+in turn includes gfp.h making everything defined by the two files
+universally available and complicating inclusion dependencies.
+
+percpu.h -> slab.h dependency is about to be removed. Prepare for
+this change by updating users of gfp and slab facilities include those
+headers directly instead of assuming availability. As this conversion
+needs to touch large number of source files, the following script is
+used as the basis of conversion.
+
+ http://userweb.kernel.org/~tj/misc/slabh-sweep.py
+
+The script does the followings.
+
+* Scan files for gfp and slab usages and update includes such that
+ only the necessary includes are there. ie. if only gfp is used,
+ gfp.h, if slab is used, slab.h.
+
+* When the script inserts a new include, it looks at the include
+ blocks and try to put the new include such that its order conforms
+ to its surrounding. It's put in the include block which contains
+ core kernel includes, in the same order that the rest are ordered -
+ alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
+ doesn't seem to be any matching order.
+
+* If the script can't find a place to put a new include (mostly
+ because the file doesn't have fitting include block), it prints out
+ an error message indicating which .h file needs to be added to the
+ file.
+
+The conversion was done in the following steps.
+
+1. The initial automatic conversion of all .c files updated slightly
+ over 4000 files, deleting around 700 includes and adding ~480 gfp.h
+ and ~3000 slab.h inclusions. The script emitted errors for ~400
+ files.
+
+2. Each error was manually checked. Some didn't need the inclusion,
+ some needed manual addition while adding it to implementation .h or
+ embedding .c file was more appropriate for others. This step added
+ inclusions to around 150 files.
+
+3. The script was run again and the output was compared to the edits
+ from #2 to make sure no file was left behind.
+
+4. Several build tests were done and a couple of problems were fixed.
+ e.g. lib/decompress_*.c used malloc/free() wrappers around slab
+ APIs requiring slab.h to be added manually.
+
+5. The script was run on all .h files but without automatically
+ editing them as sprinkling gfp.h and slab.h inclusions around .h
+ files could easily lead to inclusion dependency hell. Most gfp.h
+ inclusion directives were ignored as stuff from gfp.h was usually
+ wildly available and often used in preprocessor macros. Each
+ slab.h inclusion directive was examined and added manually as
+ necessary.
+
+6. percpu.h was updated not to include slab.h.
+
+7. Build test were done on the following configurations and failures
+ were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
+ distributed build env didn't work with gcov compiles) and a few
+ more options had to be turned off depending on archs to make things
+ build (like ipr on powerpc/64 which failed due to missing writeq).
+
+ * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
+ * powerpc and powerpc64 SMP allmodconfig
+ * sparc and sparc64 SMP allmodconfig
+ * ia64 SMP allmodconfig
+ * s390 SMP allmodconfig
+ * alpha SMP allmodconfig
+ * um on x86_64 SMP allmodconfig
+
+8. percpu.h modifications were reverted so that it could be applied as
+ a separate patch and serve as bisection point.
+
+Given the fact that I had only a couple of failures from tests on step
+6, I'm fairly confident about the coverage of this conversion patch.
+If there is a breakage, it's likely to be something in one of the arch
+headers which should be easily discoverable easily on most builds of
+the specific arch.
+
+Signed-off-by: Tejun Heo <tj at kernel.org>
+Guess-its-ok-by: Christoph Lameter <cl at linux-foundation.org>
+Cc: Ingo Molnar <mingo at redhat.com>
+Cc: Lee Schermerhorn <Lee.Schermerhorn at hp.com>
+---
+
+diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
+index 0823e26..c6e4b77 100644
+--- a/drivers/leds/leds-gpio.c
++++ b/drivers/leds/leds-gpio.c
+@@ -14,6 +14,7 @@
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/leds.h>
++#include <linux/slab.h>
+ #include <linux/workqueue.h>
+
+ #include <asm/gpio.h>
+
Added: dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-blink-set.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/leds-gpio-blink-set.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,179 @@
+From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Date: Sat, 22 May 2010 10:54:55 +0000 (+1000)
+Subject: leds: leds-gpio: Change blink_set callback to be able to turn off blinking
+X-Git-Tag: v2.6.35-rc1~32^2~5
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=2146325df2c2640059a9e064890c30c6e259b458
+
+leds: leds-gpio: Change blink_set callback to be able to turn off blinking
+
+The leds-gpio blink_set() callback follows the same prototype as the
+main leds subsystem blink_set() one.
+
+The problem is that to stop blink, normally, a leds driver does it
+in the brightness_set() callback when asked to set a new fixed value.
+
+However, with leds-gpio, the platform has no hook to do so, as this
+later callback results in a standard GPIO manipulation.
+
+This changes the leds-gpio specific callback to take a new argument
+that indicates whether the LED should be blinking or not and in what
+state it should be set if not. We also update the dns323 platform
+which seems to be the only user of this so far.
+
+Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Signed-off-by: Richard Purdie <rpurdie at linux.intel.com>
+---
+
+diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
+index 685f34a..fe0de16 100644
+--- a/arch/arm/mach-orion5x/dns323-setup.c
++++ b/arch/arm/mach-orion5x/dns323-setup.c
+@@ -240,22 +240,23 @@ error_fail:
+
+ #define ORION_BLINK_HALF_PERIOD 100 /* ms */
+
+-static int dns323_gpio_blink_set(unsigned gpio,
++static int dns323_gpio_blink_set(unsigned gpio, int state,
+ unsigned long *delay_on, unsigned long *delay_off)
+ {
+- static int value = 0;
+
+- if (!*delay_on && !*delay_off)
++ if (delay_on && delay_off && !*delay_on && !*delay_off)
+ *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
+
+- if (ORION_BLINK_HALF_PERIOD == *delay_on
+- && ORION_BLINK_HALF_PERIOD == *delay_off) {
+- value = !value;
+- orion_gpio_set_blink(gpio, value);
+- return 0;
++ switch(state) {
++ case GPIO_LED_NO_BLINK_LOW:
++ case GPIO_LED_NO_BLINK_HIGH:
++ orion_gpio_set_blink(gpio, 0);
++ gpio_set_value(gpio, state);
++ break;
++ case GPIO_LED_BLINK:
++ orion_gpio_set_blink(gpio, 1);
+ }
+-
+- return -EINVAL;
++ return 0;
+ }
+
+ static struct gpio_led dns323_leds[] = {
+diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
+index 6d94b0b..26843dd 100644
+--- a/drivers/leds/leds-gpio.c
++++ b/drivers/leds/leds-gpio.c
+@@ -26,7 +26,8 @@ struct gpio_led_data {
+ u8 new_level;
+ u8 can_sleep;
+ u8 active_low;
+- int (*platform_gpio_blink_set)(unsigned gpio,
++ u8 blinking;
++ int (*platform_gpio_blink_set)(unsigned gpio, int state,
+ unsigned long *delay_on, unsigned long *delay_off);
+ };
+
+@@ -35,7 +36,13 @@ static void gpio_led_work(struct work_struct *work)
+ struct gpio_led_data *led_dat =
+ container_of(work, struct gpio_led_data, work);
+
+- gpio_set_value_cansleep(led_dat->gpio, led_dat->new_level);
++ if (led_dat->blinking) {
++ led_dat->platform_gpio_blink_set(led_dat->gpio,
++ led_dat->new_level,
++ NULL, NULL);
++ led_dat->blinking = 0;
++ } else
++ gpio_set_value_cansleep(led_dat->gpio, led_dat->new_level);
+ }
+
+ static void gpio_led_set(struct led_classdev *led_cdev,
+@@ -60,8 +67,14 @@ static void gpio_led_set(struct led_classdev *led_cdev,
+ if (led_dat->can_sleep) {
+ led_dat->new_level = level;
+ schedule_work(&led_dat->work);
+- } else
+- gpio_set_value(led_dat->gpio, level);
++ } else {
++ if (led_dat->blinking) {
++ led_dat->platform_gpio_blink_set(led_dat->gpio, level,
++ NULL, NULL);
++ led_dat->blinking = 0;
++ } else
++ gpio_set_value(led_dat->gpio, level);
++ }
+ }
+
+ static int gpio_blink_set(struct led_classdev *led_cdev,
+@@ -70,12 +83,14 @@ static int gpio_blink_set(struct led_classdev *led_cdev,
+ struct gpio_led_data *led_dat =
+ container_of(led_cdev, struct gpio_led_data, cdev);
+
+- return led_dat->platform_gpio_blink_set(led_dat->gpio, delay_on, delay_off);
++ led_dat->blinking = 1;
++ return led_dat->platform_gpio_blink_set(led_dat->gpio, GPIO_LED_BLINK,
++ delay_on, delay_off);
+ }
+
+ static int __devinit create_gpio_led(const struct gpio_led *template,
+ struct gpio_led_data *led_dat, struct device *parent,
+- int (*blink_set)(unsigned, unsigned long *, unsigned long *))
++ int (*blink_set)(unsigned, int, unsigned long *, unsigned long *))
+ {
+ int ret, state;
+
+@@ -97,6 +112,7 @@ static int __devinit create_gpio_led(const struct gpio_led *template,
+ led_dat->gpio = template->gpio;
+ led_dat->can_sleep = gpio_cansleep(template->gpio);
+ led_dat->active_low = template->active_low;
++ led_dat->blinking = 0;
+ if (blink_set) {
+ led_dat->platform_gpio_blink_set = blink_set;
+ led_dat->cdev.blink_set = gpio_blink_set;
+@@ -113,7 +129,7 @@ static int __devinit create_gpio_led(const struct gpio_led *template,
+ ret = gpio_direction_output(led_dat->gpio, led_dat->active_low ^ state);
+ if (ret < 0)
+ goto err;
+-
++
+ INIT_WORK(&led_dat->work, gpio_led_work);
+
+ ret = led_classdev_register(parent, &led_dat->cdev);
+@@ -234,6 +250,7 @@ static int __devinit of_gpio_leds_probe(struct of_device *ofdev,
+ led.gpio = of_get_gpio_flags(child, 0, &flags);
+ led.active_low = flags & OF_GPIO_ACTIVE_LOW;
+ led.name = of_get_property(child, "label", NULL) ? : child->name;
++ led.blinking = 0;
+ led.default_trigger =
+ of_get_property(child, "linux,default-trigger", NULL);
+ state = of_get_property(child, "default-state", NULL);
+diff --git a/include/linux/leds.h b/include/linux/leds.h
+index d8bf966..ba6986a 100644
+--- a/include/linux/leds.h
++++ b/include/linux/leds.h
+@@ -149,14 +149,18 @@ struct gpio_led {
+ unsigned default_state : 2;
+ /* default_state should be one of LEDS_GPIO_DEFSTATE_(ON|OFF|KEEP) */
+ };
+-#define LEDS_GPIO_DEFSTATE_OFF 0
+-#define LEDS_GPIO_DEFSTATE_ON 1
+-#define LEDS_GPIO_DEFSTATE_KEEP 2
++#define LEDS_GPIO_DEFSTATE_OFF 0
++#define LEDS_GPIO_DEFSTATE_ON 1
++#define LEDS_GPIO_DEFSTATE_KEEP 2
+
+ struct gpio_led_platform_data {
+ int num_leds;
+ struct gpio_led *leds;
+- int (*gpio_blink_set)(unsigned gpio,
++
++#define GPIO_LED_NO_BLINK_LOW 0 /* No blink GPIO state low */
++#define GPIO_LED_NO_BLINK_HIGH 1 /* No blink GPIO state high */
++#define GPIO_LED_BLINK 2 /* Plase, blink */
++ int (*gpio_blink_set)(unsigned gpio, int state,
+ unsigned long *delay_on,
+ unsigned long *delay_off);
+ };
Added: dists/sid/linux-2.6/debian/patches/features/arm/marvell-phy-expose-ids.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/marvell-phy-expose-ids.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,170 @@
+From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Date: Mon, 21 Jun 2010 03:20:46 +0000 (+1000)
+Subject: net/phy/marvell: Expose IDs and flags in a .h and add dns323 LEDs setup flag
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=5ca4425e3e9bae222c6c9f399aeaeaa7e85c74d7
+
+net/phy/marvell: Expose IDs and flags in a .h and add dns323 LEDs setup flag
+
+This moves the various known Marvell PHY IDs to include/linux/marvell_phy.h
+along with dev_flags definitions for use by the driver.
+
+I then added a flag that changes the PHY init code to setup the LEDs
+config to the values needed to operate a dns323 rev C1 NAS.
+
+I moved the existing "resistance" flag to the .h as well, though I've
+been unable to find whoever sets this to convert it to use that constant.
+
+Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>
+Acked-by: David S. Miller <davem at davemloft.net>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+
+[adapted line numbers -- tbm]
+
+---
+
+diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
+index 78b74e8..5a1bd5d 100644
+--- a/drivers/net/phy/marvell.c
++++ b/drivers/net/phy/marvell.c
+@@ -30,6 +30,7 @@
+ #include <linux/mii.h>
+ #include <linux/ethtool.h>
+ #include <linux/phy.h>
++#include <linux/marvell_phy.h>
+
+ #include <asm/io.h>
+ #include <asm/irq.h>
+@@ -49,8 +50,6 @@
+ #define MII_M1145_RGMII_RX_DELAY 0x0080
+ #define MII_M1145_RGMII_TX_DELAY 0x0002
+
+-#define M1145_DEV_FLAGS_RESISTANCE 0x00000001
+-
+ #define MII_M1111_PHY_LED_CONTROL 0x18
+ #define MII_M1111_PHY_LED_DIRECT 0x4100
+ #define MII_M1111_PHY_LED_COMBINE 0x411c
+@@ -313,7 +315,10 @@ static int m88e1118_config_init(struct phy_device *phydev)
+ return err;
+
+ /* Adjust LED Control */
+- err = phy_write(phydev, 0x10, 0x021e);
++ if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
++ err = phy_write(phydev, 0x10, 0x1100);
++ else
++ err = phy_write(phydev, 0x10, 0x021e);
+ if (err < 0)
+ return err;
+
+@@ -361,7 +363,7 @@ static int m88e1145_config_init(struct phy_device *phydev)
+ if (err < 0)
+ return err;
+
+- if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
++ if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
+ err = phy_write(phydev, 0x1d, 0x0012);
+ if (err < 0)
+ return err;
+@@ -492,8 +494,8 @@ static int m88e1121_did_interrupt(struct phy_device *phydev)
+
+ static struct phy_driver marvell_drivers[] = {
+ {
+- .phy_id = 0x01410c60,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1101,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1101",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -504,8 +506,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = { .owner = THIS_MODULE },
+ },
+ {
+- .phy_id = 0x01410c90,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1112,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1112",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -517,8 +519,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = { .owner = THIS_MODULE },
+ },
+ {
+- .phy_id = 0x01410cc0,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1111,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1111",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -530,8 +532,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = { .owner = THIS_MODULE },
+ },
+ {
+- .phy_id = 0x01410e10,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1118,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1118",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -543,8 +545,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = {.owner = THIS_MODULE,},
+ },
+ {
+- .phy_id = 0x01410cb0,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1121R,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1121R",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -556,8 +558,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = { .owner = THIS_MODULE },
+ },
+ {
+- .phy_id = 0x01410cd0,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1145,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1145",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+@@ -569,8 +571,8 @@ static struct phy_driver marvell_drivers[] = {
+ .driver = { .owner = THIS_MODULE },
+ },
+ {
+- .phy_id = 0x01410e30,
+- .phy_id_mask = 0xfffffff0,
++ .phy_id = MARVELL_PHY_ID_88E1240,
++ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E1240",
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
+new file mode 100644
+index 0000000..2ed4fb8
+--- /dev/null
++++ b/include/linux/marvell_phy.h
+@@ -0,0 +1,20 @@
++#ifndef _MARVELL_PHY_H
++#define _MARVELL_PHY_H
++
++/* Mask used for ID comparisons */
++#define MARVELL_PHY_ID_MASK 0xfffffff0
++
++/* Known PHY IDs */
++#define MARVELL_PHY_ID_88E1101 0x01410c60
++#define MARVELL_PHY_ID_88E1112 0x01410c90
++#define MARVELL_PHY_ID_88E1111 0x01410cc0
++#define MARVELL_PHY_ID_88E1118 0x01410e10
++#define MARVELL_PHY_ID_88E1121R 0x01410cb0
++#define MARVELL_PHY_ID_88E1145 0x01410cd0
++#define MARVELL_PHY_ID_88E1240 0x01410e30
++
++/* struct phy_device dev_flags definitions */
++#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001
++#define MARVELL_PHY_M1118_DNS323_LEDS 0x00000002
++
++#endif /* _MARVELL_PHY_H */
Added: dists/sid/linux-2.6/debian/patches/features/arm/mpp-update-for-f6282.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/mpp-update-for-f6282.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,698 @@
+From: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
+Date: Tue, 8 Jun 2010 08:00:22 +0000 (+0200)
+Subject: [ARM] Kirkwood: update MPP definition.
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=6605742f2a352c62e56b50e0d4321583181fb287
+
+[ARM] Kirkwood: update MPP definition.
+
+Add MPP definitions for Marvell Kirkwood 88F6282 revision.
+Update some defines to reflect datasheet's MPP names.
+
+Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
+index bc74278..9b0a94d 100644
+--- a/arch/arm/mach-kirkwood/mpp.h
++++ b/arch/arm/mach-kirkwood/mpp.h
+@@ -11,7 +11,7 @@
+ #ifndef __KIRKWOOD_MPP_H
+ #define __KIRKWOOD_MPP_H
+
+-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
++#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
+ /* MPP number */ ((_num) & 0xff) | \
+ /* MPP select value */ (((_sel) & 0xf) << 8) | \
+ /* may be input signal */ ((!!(_in)) << 12) | \
+@@ -19,282 +19,332 @@
+ /* available on F6180 */ ((!!(_F6180)) << 14) | \
+ /* available on F6190 */ ((!!(_F6190)) << 15) | \
+ /* available on F6192 */ ((!!(_F6192)) << 16) | \
+- /* available on F6281 */ ((!!(_F6281)) << 17))
++ /* available on F6281 */ ((!!(_F6281)) << 17) | \
++ /* available on F6282 */ ((!!(_F6282)) << 18))
+
+ #define MPP_NUM(x) ((x) & 0xff)
+ #define MPP_SEL(x) (((x) >> 8) & 0xf)
+
+- /* num sel i o 6180 6190 6192 6281 */
+-
+-#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
+-#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
+-
+-#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
+-#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
+-#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
+-#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
+-
+-#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 )
+-#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 )
+-#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 )
+-#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 )
+-#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 )
+-#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
+-#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 )
+-#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 )
+-#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 )
+-#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 )
+-#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 )
+-#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 )
+-#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 )
+-#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 )
+-#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 )
+-#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 )
+-#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 )
+-#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 )
+-#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 )
+-#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 )
+-#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 )
+-
+-#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 )
+-#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 )
+-#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 )
+-#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 )
+-#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 )
+-#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 )
+-#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 )
+-#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 )
+-#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 )
+-
+-#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 )
+-#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 )
+-
+-#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 )
+-#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 )
+-
+-#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 )
+-#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 )
+-#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 )
+-
+-#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 )
+-#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 )
+-#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 )
+-
+-#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 )
+-
+-#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 )
+-
+-#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 )
+-#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 )
+-
+-#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 )
+-
+-#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 )
+-#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 )
+-
+-#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 )
+-#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 )
+-#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 )
+-#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 )
+-#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 )
+-#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
+-#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
+-
+-#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
+-#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
+-#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 )
+-#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 )
+-#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 )
+-
+-#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 )
+-
+-#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 )
+-#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 )
+-
+-#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 )
+-#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 )
+-
+-#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 )
+-#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 )
+-#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 )
+-
+-#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 )
+-#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 )
+-
+-#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 )
+-#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 )
+-
+-#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 )
+-#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 )
+-
+-#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 )
+-#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )
+-
+-#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 )
+-#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 )
+-#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 )
+-#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 )
++ /* num sel i o 6180 6190 6192 6281 6282 */
++
++#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
++#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
++
++#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
++#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
++#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
++#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 )
++#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++
++#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++
++#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++
++#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
++
++#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
++#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
++
++#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
++#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
++#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
++
++#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
++#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
++#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
++#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
++
++#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
++#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
++#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
++#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++
++#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
++
++#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
++
++#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
++#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
++#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
++
++#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
++#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
++#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
++
++#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
++
++#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
++#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
++
++#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
++#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
++#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
++#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
++#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
++#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
++#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
++#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
++#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
++#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
++
++#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
++#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
++
++#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
++
++#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
++#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
++#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
++#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
++#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
++#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
++#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
++#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
++#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
++#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
++
++#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
++#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
++#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
++#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
++#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
++#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
+
+ #define MPP_MAX 49
+
+diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
+index 3ae158d..b96e43b 100644
+[ removed; not in 2.6.32 -- tbm ]
+diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+index 8a2bb02..2bd14c5 100644
+[ removed; not in 2.6.32 -- tbm ]
+diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
+index 2830f0f..d23aff9 100644
+--- a/arch/arm/mach-kirkwood/ts219-setup.c
++++ b/arch/arm/mach-kirkwood/ts219-setup.c
+@@ -144,8 +144,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
+ MPP3_SPI_MISO,
+ MPP4_SATA1_ACTn,
+ MPP5_SATA0_ACTn,
+- MPP8_TW_SDA,
+- MPP9_TW_SCK,
++ MPP8_TW0_SDA,
++ MPP9_TW0_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP13_UART1_TXD, /* PIC controller */
+diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
+index 821da94..e9d85d7 100644
+--- a/arch/arm/mach-kirkwood/ts41x-setup.c
++++ b/arch/arm/mach-kirkwood/ts41x-setup.c
+@@ -151,26 +151,26 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
+ MPP3_SPI_MISO,
+ MPP6_SYSRST_OUTn,
+ MPP7_PEX_RST_OUTn,
+- MPP8_TW_SDA,
+- MPP9_TW_SCK,
++ MPP8_TW0_SDA,
++ MPP9_TW0_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP13_UART1_TXD, /* PIC controller */
+ MPP14_UART1_RXD, /* PIC controller */
+ MPP15_SATA0_ACTn,
+ MPP16_SATA1_ACTn,
+- MPP20_GE1_0,
+- MPP21_GE1_1,
+- MPP22_GE1_2,
+- MPP23_GE1_3,
+- MPP24_GE1_4,
+- MPP25_GE1_5,
+- MPP26_GE1_6,
+- MPP27_GE1_7,
+- MPP30_GE1_10,
+- MPP31_GE1_11,
+- MPP32_GE1_12,
+- MPP33_GE1_13,
++ MPP20_GE1_TXD0,
++ MPP21_GE1_TXD1,
++ MPP22_GE1_TXD2,
++ MPP23_GE1_TXD3,
++ MPP24_GE1_RXD0,
++ MPP25_GE1_RXD1,
++ MPP26_GE1_RXD2,
++ MPP27_GE1_RXD3,
++ MPP30_GE1_RXCTL,
++ MPP31_GE1_RXCLK,
++ MPP32_GE1_TCLKOUT,
++ MPP33_GE1_TXCTL,
+ MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
+ MPP37_GPIO, /* Reset button */
+ MPP43_GPIO, /* USB Copy button */
Added: dists/sid/linux-2.6/debian/patches/features/arm/orion-add-rnb-line-support.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/orion-add-rnb-line-support.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,41 @@
+From: Ben Dooks <ben at simtec.co.uk>
+Date: Tue, 20 Apr 2010 09:26:18 +0000 (+0100)
+Subject: mtd: orion/kirkwood: add RnB line support to orion mtd driver
+X-Git-Tag: v2.6.35-rc1~465^2~42
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=eedfea252690435858722a8da1109d104d639087
+
+mtd: orion/kirkwood: add RnB line support to orion mtd driver
+
+Add support for a board to register a callback to get the state of the
+RnB line if it has it attached.
+
+Signed-off-by: Ben Dooks <ben at simtec.co.uk>
+Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
+---
+
+diff --git a/arch/arm/plat-orion/include/plat/orion_nand.h b/arch/arm/plat-orion/include/plat/orion_nand.h
+index d6a4cfa..9f3c180 100644
+--- a/arch/arm/plat-orion/include/plat/orion_nand.h
++++ b/arch/arm/plat-orion/include/plat/orion_nand.h
+@@ -14,6 +14,7 @@
+ */
+ struct orion_nand_data {
+ struct mtd_partition *parts;
++ int (*dev_ready)(struct mtd_info *mtd);
+ u32 nr_parts;
+ u8 ale; /* address line number connected to ALE */
+ u8 cle; /* address line number connected to CLE */
+diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
+index f4444fe..da6e753 100644
+--- a/drivers/mtd/nand/orion_nand.c
++++ b/drivers/mtd/nand/orion_nand.c
+@@ -114,6 +114,9 @@ static int __init orion_nand_probe(struct platform_device *pdev)
+ if (board->width == 16)
+ nc->options |= NAND_BUSWIDTH_16;
+
++ if (board->dev_ready)
++ nc->dev_ready = board->dev_ready;
++
+ platform_set_drvdata(pdev, mtd);
+
+ if (nand_scan(mtd, 1)) {
Added: dists/sid/linux-2.6/debian/patches/features/arm/orion-allow-rnb-callback
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/orion-allow-rnb-callback Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,56 @@
+From: Ben Dooks <ben at simtec.co.uk>
+Date: Tue, 20 Apr 2010 09:26:19 +0000 (+0100)
+Subject: mtd: kirkwood: allow machines to register RnB callback
+X-Git-Tag: v2.6.35-rc1~465^2~41
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=010937ec9a550e2df97f87252a9d12d8a534c6d8
+
+mtd: kirkwood: allow machines to register RnB callback
+
+Add a kirkwood_nand_init_rnb() call to allow boards which
+have RnB line detection to register this instead of a
+static delay.
+
+Signed-off-by: Ben Dooks <ben at simtec.co.uk>
+Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>
+---
+
+diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
+index f759ca2..6072eaa 100644
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -305,6 +305,15 @@ void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
+ platform_device_register(&kirkwood_nand_flash);
+ }
+
++void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
++ int (*dev_ready)(struct mtd_info *))
++{
++ kirkwood_clk_ctrl |= CGC_RUNIT;
++ kirkwood_nand_data.parts = parts;
++ kirkwood_nand_data.nr_parts = nr_parts;
++ kirkwood_nand_data.dev_ready = dev_ready;
++ platform_device_register(&kirkwood_nand_flash);
++}
+
+ /*****************************************************************************
+ * SoC RTC
+diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
+index d7de434..05e8a8a 100644
+--- a/arch/arm/mach-kirkwood/common.h
++++ b/arch/arm/mach-kirkwood/common.h
+@@ -16,6 +16,7 @@ struct mv643xx_eth_platform_data;
+ struct mv_sata_platform_data;
+ struct mvsdio_platform_data;
+ struct mtd_partition;
++struct mtd_info;
+
+ /*
+ * Basic Kirkwood init functions used early by machine-setup.
+@@ -41,6 +42,7 @@ void kirkwood_i2c_init(void);
+ void kirkwood_uart0_init(void);
+ void kirkwood_uart1_init(void);
+ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
++void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *));
+
+ extern int kirkwood_tclk;
+ extern struct sys_timer kirkwood_timer;
Added: dists/sid/linux-2.6/debian/patches/features/arm/orion5x-fix-soft-reset.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/features/arm/orion5x-fix-soft-reset.patch Thu Jul 15 19:45:00 2010 (r15987)
@@ -0,0 +1,31 @@
+From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Date: Mon, 21 Jun 2010 03:22:08 +0000 (+1000)
+Subject: [ARM] orion5x: Fix soft-reset for some platforms
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=bdb0eafd534a2319c00bbc7655ddc9749a58aeda
+
+[ARM] orion5x: Fix soft-reset for some platforms
+
+Some platforms, such as the DNS-323 rev C requires the soft reset line
+to be toggled on and back off for the reset to work.
+
+Note: The choice of 200ms delay comes from the 2.6.12 based vendor kernel.
+It seems to be a -lot- though and I had my device working fine with much
+smaller delays but better safe...
+
+Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
+Signed-off-by: Nicolas Pitre <nico at fluxnic.net>
+---
+
+diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
+index 60e734c..a1d6e46 100644
+--- a/arch/arm/mach-orion5x/include/mach/system.h
++++ b/arch/arm/mach-orion5x/include/mach/system.h
+@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
+ */
+ orion5x_setbits(RSTOUTn_MASK, (1 << 2));
+ orion5x_setbits(CPU_SOFT_RESET, 1);
++ mdelay(200);
++ orion5x_clrbits(CPU_SOFT_RESET, 1);
+ }
+
+
Modified: dists/sid/linux-2.6/debian/patches/series/18
==============================================================================
--- dists/sid/linux-2.6/debian/patches/series/18 Wed Jul 14 00:56:24 2010 (r15986)
+++ dists/sid/linux-2.6/debian/patches/series/18 Thu Jul 15 19:45:00 2010 (r15987)
@@ -1,3 +1,17 @@
+ features/all/iwlwifi-use-paged-Rx.patch
+ bugfix/all/iwlwifi-fix-use-after-free-bug-for-paged-rx.patch
+ bugfix/all/iwlwifi-fix-AMSDU-Rx-after-paged-Rx-patch.patch
++ features/arm/mpp-update-for-f6282.patch
++ features/arm/fix-t5325-after-mpp-update.patch
++ features/arm/leds-gpio-add-slab.patch
++ features/arm/leds-gpio-blink-set.patch
++ features/arm/marvell-phy-expose-ids.patch
++ features/arm/dns-323-add-rev-c1.patch
++ features/arm/orion5x-fix-soft-reset.patch
++ features/arm/orion-add-rnb-line-support.patch
++ features/arm/orion-allow-rnb-callback
++ features/arm/kirkwood-f6192-f6180-add-a1-rev.patch
++ features/arm/kirkwood-add-88f6282-support.patch
++ features/arm/arm-add-pci_sys_data.patch
++ features/arm/kirkwood-add-pcie1.patch
++ features/arm/kirkwood-factorize-pcie-init-code
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