[kernel] r15650 - in dists/sid/linux-2.6/debian: . patches/bugfix/mips patches/series
Aurelien Jarno
aurel32 at alioth.debian.org
Sun May 9 08:09:53 UTC 2010
Author: aurel32
Date: Sun May 9 08:09:46 2010
New Revision: 15650
Log:
* backport mips/swarm: fix M3 TLB exception handler.
Added:
dists/sid/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch
Modified:
dists/sid/linux-2.6/debian/changelog
dists/sid/linux-2.6/debian/patches/series/13
Modified: dists/sid/linux-2.6/debian/changelog
==============================================================================
--- dists/sid/linux-2.6/debian/changelog Sun May 9 04:46:58 2010 (r15649)
+++ dists/sid/linux-2.6/debian/changelog Sun May 9 08:09:46 2010 (r15650)
@@ -25,6 +25,7 @@
[ Aurelien Jarno ]
* mips/swarm: fix boot from IDE based media (Sebastian Andrzej Siewior)
(closes: #466977).
+ * backport mips/swarm: fix M3 TLB exception handler.
-- Frederik Schüler <fs at debian.org> Wed, 05 May 2010 17:54:01 +0200
Added: dists/sid/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/sid/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch Sun May 9 08:09:46 2010 (r15650)
@@ -0,0 +1,164 @@
+commit 8d9df29db273ab9a330828f4f4f6669d293a730a
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 00:02:43 2010 +0100
+
+ MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
+
+ Previously it was unconditionally used on all Sibyte family SOCs. The
+ M3 bug has to be handled in the TLB exception handler which is extremly
+ performance sensitive, so this modification is expected to deliver around
+ 2-3% performance improvment. This is important as required changes to the
+ M3 workaround will make it more costly.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
+index 7950ef4..743385d 100644
+--- a/arch/mips/include/asm/mach-sibyte/war.h
++++ b/arch/mips/include/asm/mach-sibyte/war.h
+@@ -16,7 +16,11 @@
+ #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
+ defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
+
+-#define BCM1250_M3_WAR 1
++#ifndef __ASSEMBLY__
++extern int sb1250_m3_workaround_needed(void);
++#endif
++
++#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
+ #define SIBYTE_1956_WAR 1
+
+ #else
+diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
+index 0444da1..92da315 100644
+--- a/arch/mips/sibyte/sb1250/setup.c
++++ b/arch/mips/sibyte/sb1250/setup.c
+@@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
+ return ret;
+ }
+
++int sb1250_m3_workaround_needed(void)
++{
++ switch (soc_type) {
++ case K_SYS_SOC_TYPE_BCM1250:
++ case K_SYS_SOC_TYPE_BCM1250_ALT:
++ case K_SYS_SOC_TYPE_BCM1250_ALT2:
++ case K_SYS_SOC_TYPE_BCM1125:
++ case K_SYS_SOC_TYPE_BCM1125H:
++ return soc_pass < K_SYS_REVISION_BCM1250_C0;
++
++ default:
++ return 0;
++ }
++}
++
+ static int __init setup_bcm112x(void)
+ {
+ int ret = 0;
+
+
+commit 5808184f1b2fe06ef8a54a2b7fb1596d58098acf
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 15:54:50 2010 +0100
+
+ MIPS: uasm: Add OR instruction.
+
+ This is needed for the fix of the M3 workaround.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
+index 32fe2ec..11a8b52 100644
+--- a/arch/mips/mm/uasm.h
++++ b/arch/mips/mm/uasm.h
+@@ -84,6 +84,7 @@ Ip_u2s3u1(_lw);
+ Ip_u1u2u3(_mfc0);
+ Ip_u1u2u3(_mtc0);
+ Ip_u2u1u3(_ori);
++Ip_u3u1u2(_or);
+ Ip_u2s3u1(_pref);
+ Ip_0(_rfe);
+ Ip_u2s3u1(_sc);
+diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
+index d22d7bc..611d564 100644
+--- a/arch/mips/mm/uasm.c
++++ b/arch/mips/mm/uasm.c
+@@ -62,7 +62,7 @@
+ insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
+ insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
+ insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
+- insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
++ insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
+ insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
+ insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
+ };
+@@ -120,6 +120,7 @@ static struct insn insn_table[] __cpuinitdata = {
+ { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
+ { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
++ { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
+ { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
+ { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
+@@ -387,6 +388,7 @@ I_u2s3u1(_lw)
+ I_u1u2u3(_mfc0)
+ I_u1u2u3(_mtc0)
+ I_u2u1u3(_ori)
++I_u3u1u2(_or)
+ I_u2s3u1(_pref)
+ I_0(_rfe)
+ I_u2s3u1(_sc)
+
+
+commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 17:56:38 2010 +0100
+
+ MIPS: Sibyte: Fix M3 TLB exception handler workaround.
+
+ The M3 workaround needs to cmpare the region and VPN2 fields only.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
+index 0de0e41..d1f68aa 100644
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -788,10 +788,15 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
+ * create the plain linear handler
+ */
+ if (bcm1250_m3_war()) {
+- UASM_i_MFC0(&p, K0, C0_BADVADDR);
+- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++ unsigned int segbits = 44;
++
++ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+ uasm_i_xor(&p, K0, K0, K1);
+- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++ uasm_i_dsrl(&p, K0, K0, 12 + 1);
++ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++ uasm_i_or(&p, K0, K0, K1);
+ uasm_il_bnez(&p, &r, K0, label_leave);
+ /* No need for uasm_i_nop */
+ }
+@@ -1312,10 +1317,15 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
+ memset(relocs, 0, sizeof(relocs));
+
+ if (bcm1250_m3_war()) {
+- UASM_i_MFC0(&p, K0, C0_BADVADDR);
+- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++ unsigned int segbits = 44;
++
++ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+ uasm_i_xor(&p, K0, K0, K1);
+- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++ uasm_i_dsrl(&p, K0, K0, 12 + 1);
++ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++ uasm_i_or(&p, K0, K0, K1);
+ uasm_il_bnez(&p, &r, K0, label_leave);
+ /* No need for uasm_i_nop */
+ }
Modified: dists/sid/linux-2.6/debian/patches/series/13
==============================================================================
--- dists/sid/linux-2.6/debian/patches/series/13 Sun May 9 04:46:58 2010 (r15649)
+++ dists/sid/linux-2.6/debian/patches/series/13 Sun May 9 08:09:46 2010 (r15650)
@@ -9,3 +9,4 @@
+ features/all/rtl8192su-add-Support-for-Belkin-F5D8053-v6.patch
+ features/all/rtl8192su-Add-Sitecom-WL-349.patch
+ bugfix/mips/mips-ide-flush-dcache.patch
++ bugfix/mips/sibyte-m3-tlb-exception.patch
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