[kernel] r15737 - in dists/lenny/linux-2.6/debian: . patches/bugfix/mips patches/series
Aurelien Jarno
aurel32 at alioth.debian.org
Tue May 18 07:32:24 UTC 2010
Author: aurel32
Date: Tue May 18 07:32:15 2010
New Revision: 15737
Log:
* mips/swarm: fix boot from IDE based media (Sebastian Andrzej Siewior)
(closes: #466977).
* backport mips/swarm: fix M3 TLB exception handler.
* backport MIPS FPU emulator: allow Cause bits of FCSR to be writeable
by ctc1. (closes: #580602).
Added:
dists/lenny/linux-2.6/debian/patches/bugfix/mips/fpu-emulator.patch
dists/lenny/linux-2.6/debian/patches/bugfix/mips/mips-ide-flush-dcache.patch
dists/lenny/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch
Modified:
dists/lenny/linux-2.6/debian/changelog
dists/lenny/linux-2.6/debian/patches/series/23
Modified: dists/lenny/linux-2.6/debian/changelog
==============================================================================
--- dists/lenny/linux-2.6/debian/changelog Tue May 18 02:43:50 2010 (r15736)
+++ dists/lenny/linux-2.6/debian/changelog Tue May 18 07:32:15 2010 (r15737)
@@ -22,6 +22,13 @@
(closes: #500145)
* ub: incorrect skb is charged in tcp_send_synack.
+ [ Aurelien Jarno ]
+ * mips/swarm: fix boot from IDE based media (Sebastian Andrzej Siewior)
+ (closes: #466977).
+ * backport mips/swarm: fix M3 TLB exception handler.
+ * backport MIPS FPU emulator: allow Cause bits of FCSR to be writeable
+ by ctc1. (closes: #580602).
+
-- dann frazier <dannf at debian.org> Wed, 10 Mar 2010 23:42:11 -0700
linux-2.6 (2.6.26-22) stable; urgency=high
Added: dists/lenny/linux-2.6/debian/patches/bugfix/mips/fpu-emulator.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/lenny/linux-2.6/debian/patches/bugfix/mips/fpu-emulator.patch Tue May 18 07:32:15 2010 (r15737)
@@ -0,0 +1,99 @@
+From: Shane McDonald <mcdonald.shane at gmail.com>
+Date: Fri, 7 May 2010 05:26:57 +0000 (-0600)
+Subject: MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
+X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=2c8fb481214e608f6b9a71aa85651d9ddf7fd6e4
+
+MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
+
+In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
+are not currently writeable by the ctc1 instruction. In odd corner cases,
+this can cause problems. For example, a case existed where a divide-by-zero
+exception was generated by the FPU, and the signal handler attempted to
+restore the FPU registers to their state before the exception occurred. In
+this particular setup, writing the old value to the FCSR register would
+cause another divide-by-zero exception to occur immediately. The solution
+is to change the ctc1 instruction emulator code to allow the Cause bits of
+the FCSR register to be writeable. This is the behaviour of the hardware
+that the code is emulating.
+
+This problem was found by Shane McDonald, but the credit for the fix goes
+to Kevin Kissell. In Kevin's words:
+
+I submit that the bug is indeed in that ctc_op: case of the emulator. The
+Cause bits (17:12) are supposed to be writable by that instruction, but the
+CTC1 emulation won't let them be updated by the instruction. I think that
+actually if you just completely removed lines 387-388 [...] things would
+work a good deal better. At least, it would be a more accurate emulation of
+the architecturally defined FPU. If I wanted to be really, really pedantic
+(which I sometimes do), I'd also protect the reserved bits that aren't
+necessarily writable.
+
+Signed-off-by: Shane McDonald <mcdonald.shane at gmail.com>
+To: anemo at mba.ocn.ne.jp
+To: kevink at paralogos.com
+To: sshtylyov at mvista.com
+Patchwork: http://patchwork.linux-mips.org/patch/1205/
+Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+(cherry picked from commit 635be78c7c80d4c61f0f16b6132a730d7668cb43)
+---
+
+diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
+index a581d60..608dc97 100644
+--- a/include/asm-mips/mipsregs.h
++++ b/include/asm-mips/mipsregs.h
+@@ -135,6 +135,12 @@
+ #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
+
+ /*
++ * Bits 18 - 20 of the FPU Status Register will be read as 0,
++ * and should be written as zero.
++ */
++#define FPU_CSR_RSVD 0x001c0000
++
++/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+@@ -161,7 +167,8 @@
+ #define FPU_CSR_UDF_S 0x00000008
+ #define FPU_CSR_INE_S 0x00000004
+
+-/* rounding mode */
++/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
++#define FPU_CSR_RM 0x00000003
+ #define FPU_CSR_RN 0x0 /* nearest */
+ #define FPU_CSR_RZ 0x1 /* towards zero */
+ #define FPU_CSR_RU 0x2 /* towards +Infinity */
+diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
+index 454b539..c15d94b 100644
+--- a/arch/mips/math-emu/cp1emu.c
++++ b/arch/mips/math-emu/cp1emu.c
+@@ -75,6 +75,9 @@ struct mips_fpu_emulator_stats fpuemustats;
+ #define FPCREG_RID 0 /* $0 = revision id */
+ #define FPCREG_CSR 31 /* $31 = csr */
+
++/* Determine rounding mode from the RM bits of the FCSR */
++#define modeindex(v) ((v) & FPU_CSR_RM)
++
+ /* Convert Mips rounding mode (0..3) to IEEE library modes. */
+ static const unsigned char ieee_rm[4] = {
+ [FPU_CSR_RN] = IEEE754_RN,
+@@ -381,10 +384,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
+ (void *) (xcp->cp0_epc),
+ MIPSInst_RT(ir), value);
+ #endif
+- value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
+- ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
+- /* convert to ieee library modes */
+- ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
++
++ /*
++ * Don't write reserved bits,
++ * and convert to ieee library modes
++ */
++ ctx->fcr31 = (value &
++ ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
++ ieee_rm[modeindex(value)];
+ }
+ if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
+ return SIGFPE;
Added: dists/lenny/linux-2.6/debian/patches/bugfix/mips/mips-ide-flush-dcache.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/lenny/linux-2.6/debian/patches/bugfix/mips/mips-ide-flush-dcache.patch Tue May 18 07:32:15 2010 (r15737)
@@ -0,0 +1,46 @@
+From: Sebastian Andrzej Siewior <sebastian at breakpoint.cc>
+Subject: mips/ide: flush dcache also if icache does not snoop dcache
+
+If this is not done then the new just read data which remains in dcache
+will not make it into icache on time. Thus the CPU loads invalid data
+and executes crap. The result is that the user is not able to execute
+anything from its IDE based media while reading plain data is still
+working well.
+This problem has been reported as Debian #404951.
+
+Cc: stable at kernel.org
+Signed-off-by: Sebastian Andrzej Siewior <sebastian at breakpoint.cc>
+---
+ arch/mips/include/asm/mach-generic/ide.h | 6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
+index 9c93a5b..e80e47f 100644
+--- a/include/asm-mips/mach-generic/ide.h
++++ b/include/asm-mips/mach-generic/ide.h
+@@ -23,7 +23,7 @@
+ static inline void __ide_flush_prologue(void)
+ {
+ #ifdef CONFIG_SMP
+- if (cpu_has_dc_aliases)
++ if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+ preempt_disable();
+ #endif
+ }
+@@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void)
+ static inline void __ide_flush_epilogue(void)
+ {
+ #ifdef CONFIG_SMP
+- if (cpu_has_dc_aliases)
++ if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+ preempt_enable();
+ #endif
+ }
+
+ static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
+ {
+- if (cpu_has_dc_aliases) {
++ if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
+ unsigned long end = addr + size;
+
+ while (addr < end) {
Added: dists/lenny/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ dists/lenny/linux-2.6/debian/patches/bugfix/mips/sibyte-m3-tlb-exception.patch Tue May 18 07:32:15 2010 (r15737)
@@ -0,0 +1,164 @@
+commit 8d9df29db273ab9a330828f4f4f6669d293a730a
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 00:02:43 2010 +0100
+
+ MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
+
+ Previously it was unconditionally used on all Sibyte family SOCs. The
+ M3 bug has to be handled in the TLB exception handler which is extremly
+ performance sensitive, so this modification is expected to deliver around
+ 2-3% performance improvment. This is important as required changes to the
+ M3 workaround will make it more costly.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h
+index 7950ef4..743385d 100644
+--- a/include/asm-mips/mach-sibyte/war.h
++++ b/include/asm-mips/mach-sibyte/war.h
+@@ -16,7 +16,11 @@
+ #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
+ defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
+
+-#define BCM1250_M3_WAR 1
++#ifndef __ASSEMBLY__
++extern int sb1250_m3_workaround_needed(void);
++#endif
++
++#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
+ #define SIBYTE_1956_WAR 1
+
+ #else
+diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
+index 0444da1..92da315 100644
+--- a/arch/mips/sibyte/sb1250/setup.c
++++ b/arch/mips/sibyte/sb1250/setup.c
+@@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
+ return ret;
+ }
+
++int sb1250_m3_workaround_needed(void)
++{
++ switch (soc_type) {
++ case K_SYS_SOC_TYPE_BCM1250:
++ case K_SYS_SOC_TYPE_BCM1250_ALT:
++ case K_SYS_SOC_TYPE_BCM1250_ALT2:
++ case K_SYS_SOC_TYPE_BCM1125:
++ case K_SYS_SOC_TYPE_BCM1125H:
++ return soc_pass < K_SYS_REVISION_BCM1250_C0;
++
++ default:
++ return 0;
++ }
++}
++
+ static int __init setup_bcm112x(void)
+ {
+ int ret = 0;
+
+
+commit 5808184f1b2fe06ef8a54a2b7fb1596d58098acf
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 15:54:50 2010 +0100
+
+ MIPS: uasm: Add OR instruction.
+
+ This is needed for the fix of the M3 workaround.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
+index 32fe2ec..11a8b52 100644
+--- a/arch/mips/mm/uasm.h
++++ b/arch/mips/mm/uasm.h
+@@ -84,6 +84,7 @@ Ip_u2s3u1(_lw);
+ Ip_u1u2u3(_mfc0);
+ Ip_u1u2u3(_mtc0);
+ Ip_u2u1u3(_ori);
++Ip_u3u1u2(_or);
+ Ip_u2s3u1(_pref);
+ Ip_0(_rfe);
+ Ip_u2s3u1(_sc);
+diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
+index d22d7bc..611d564 100644
+--- a/arch/mips/mm/uasm.c
++++ b/arch/mips/mm/uasm.c
+@@ -62,7 +62,7 @@
+ insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
+ insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
+ insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
+- insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
++ insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
+ insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
+ insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
+ };
+@@ -120,6 +120,7 @@ static struct insn insn_table[] __cpuinitdata = {
+ { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
+ { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
++ { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
+ { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
+ { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
+@@ -387,6 +388,7 @@ I_u2s3u1(_lw)
+ I_u1u2u3(_mfc0)
+ I_u1u2u3(_mtc0)
+ I_u2u1u3(_ori)
++I_u3u1u2(_or)
+ I_u2s3u1(_pref)
+ I_0(_rfe)
+ I_u2s3u1(_sc)
+
+
+commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5
+Author: Ralf Baechle <ralf at linux-mips.org>
+Date: Tue Mar 23 17:56:38 2010 +0100
+
+ MIPS: Sibyte: Fix M3 TLB exception handler workaround.
+
+ The M3 workaround needs to cmpare the region and VPN2 fields only.
+
+ Signed-off-by: Ralf Baechle <ralf at linux-mips.org>
+
+diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
+index 0de0e41..d1f68aa 100644
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -788,10 +788,15 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
+ * create the plain linear handler
+ */
+ if (bcm1250_m3_war()) {
+- UASM_i_MFC0(&p, K0, C0_BADVADDR);
+- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++ unsigned int segbits = 44;
++
++ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+ uasm_i_xor(&p, K0, K0, K1);
+- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++ uasm_i_dsrl(&p, K0, K0, 12 + 1);
++ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++ uasm_i_or(&p, K0, K0, K1);
+ uasm_il_bnez(&p, &r, K0, label_leave);
+ /* No need for uasm_i_nop */
+ }
+@@ -1312,10 +1317,15 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
+ memset(relocs, 0, sizeof(relocs));
+
+ if (bcm1250_m3_war()) {
+- UASM_i_MFC0(&p, K0, C0_BADVADDR);
+- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
++ unsigned int segbits = 44;
++
++ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
++ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
+ uasm_i_xor(&p, K0, K0, K1);
+- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
++ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
++ uasm_i_dsrl(&p, K0, K0, 12 + 1);
++ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
++ uasm_i_or(&p, K0, K0, K1);
+ uasm_il_bnez(&p, &r, K0, label_leave);
+ /* No need for uasm_i_nop */
+ }
Modified: dists/lenny/linux-2.6/debian/patches/series/23
==============================================================================
--- dists/lenny/linux-2.6/debian/patches/series/23 Tue May 18 02:43:50 2010 (r15736)
+++ dists/lenny/linux-2.6/debian/patches/series/23 Tue May 18 07:32:15 2010 (r15737)
@@ -8,3 +8,6 @@
+ bugfix/all/md-raid6-Fix-raid-6-read-error-correction-in-degraded-state.patch
+ bugfix/all/r8169/r8169-14-fix-broken-register-writes.patch
+ bugfix/all/r8169/r8169-15-more-broken-register-writes-workaround.patch
++ bugfix/mips/sibyte-m3-tlb-exception.patch
++ bugfix/mips/mips-ide-flush-dcache.patch
++ bugfix/mips/fpu-emulator.patch
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