[linux] 02/02: drm, agp: Update to 3.4.109
debian-kernel at lists.debian.org
debian-kernel at lists.debian.org
Mon Sep 21 11:08:03 UTC 2015
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benh pushed a commit to branch wheezy
in repository linux.
commit c813f2599fefe0418480a5bb72994ab9aefe29ad
Author: Ben Hutchings <ben at decadent.org.uk>
Date: Mon Sep 21 13:03:36 2015 +0200
drm, agp: Update to 3.4.109
---
debian/changelog | 6 +-
debian/patches/features/all/drm/drm-3.4.patch | 213 +++++++++++++++-----------
2 files changed, 130 insertions(+), 89 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index f00dbc3..a6c1822 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -207,7 +207,7 @@ linux (3.2.71-1) UNRELEASED; urgency=medium
hypercall
[ Ben Hutchings ]
- * drm, agp: Update to 3.4.108:
+ * drm, agp: Update to 3.4.109:
- [x86] drm/i915: Unlock panel even when LVDS is disabled
- drm/radeon: kernel panic in drm_calc_vbltimestamp_from_scanoutpos with
3.18.0-rc6
@@ -224,6 +224,10 @@ linux (3.2.71-1) UNRELEASED; urgency=medium
- drm/radeon: fix DRM_IOCTL_RADEON_CS oops
- [x86] drm/vmwgfx: Reorder device takedown somewhat
- radeon: Do not directly dereference pointers to BIOS area.
+ - drm/radeon: fix doublescan modes (v2)
+ - drm/radeon: Use drm_calloc_ab for CS relocs
+ - drm/radeon: fix VM_CONTEXT*_PAGE_TABLE_END_ADDR handling
+ - [x86] drm/i915: Don't skip request retirement if the active list is empty
* Revert "ACPICA: Utilities: split IO address types from data type models."
to avoid ABI change on i386
* Adjust for migration to git:
diff --git a/debian/patches/features/all/drm/drm-3.4.patch b/debian/patches/features/all/drm/drm-3.4.patch
index fab11b5..ea08058 100644
--- a/debian/patches/features/all/drm/drm-3.4.patch
+++ b/debian/patches/features/all/drm/drm-3.4.patch
@@ -44516,7 +44516,7 @@ index 61274bf..a8f00d0 100644
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
-index 315a49e..b1f1d10 100644
+index 315a49e..e1c744d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -58,6 +58,7 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
@@ -45063,7 +45063,7 @@ index 315a49e..b1f1d10 100644
if (!dev_priv->mm.suspended) {
if (i915_enable_hangcheck) {
-@@ -1837,7 +1773,7 @@ void i915_gem_reset(struct drm_device *dev)
+@@ -1837,15 +1773,12 @@ void i915_gem_reset(struct drm_device *dev)
/**
* This function clears the request list as sequence numbers are passed.
*/
@@ -45072,7 +45072,15 @@ index 315a49e..b1f1d10 100644
i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
{
uint32_t seqno;
-@@ -1865,6 +1801,12 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
+ int i;
+
+- if (list_empty(&ring->request_list))
+- return;
+-
+ WARN_ON(i915_verify_lists(ring->dev));
+
+ seqno = ring->get_seqno(ring);
+@@ -1865,6 +1798,12 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
break;
trace_i915_gem_request_retire(ring, request->seqno);
@@ -45085,7 +45093,7 @@ index 315a49e..b1f1d10 100644
list_del(&request->list);
i915_gem_request_remove_from_client(request);
-@@ -1977,7 +1919,8 @@ i915_gem_retire_work_handler(struct work_struct *work)
+@@ -1977,7 +1916,8 @@ i915_gem_retire_work_handler(struct work_struct *work)
*/
int
i915_wait_request(struct intel_ring_buffer *ring,
@@ -45095,7 +45103,7 @@ index 315a49e..b1f1d10 100644
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
u32 ier;
-@@ -2040,9 +1983,9 @@ i915_wait_request(struct intel_ring_buffer *ring,
+@@ -2040,9 +1980,9 @@ i915_wait_request(struct intel_ring_buffer *ring,
|| atomic_read(&dev_priv->mm.wedged));
ring->irq_put(ring);
@@ -45108,7 +45116,7 @@ index 315a49e..b1f1d10 100644
ret = -EBUSY;
ring->waiting_seqno = 0;
-@@ -2051,17 +1994,12 @@ i915_wait_request(struct intel_ring_buffer *ring,
+@@ -2051,17 +1991,12 @@ i915_wait_request(struct intel_ring_buffer *ring,
if (atomic_read(&dev_priv->mm.wedged))
ret = -EAGAIN;
@@ -45127,7 +45135,7 @@ index 315a49e..b1f1d10 100644
i915_gem_retire_requests_ring(ring);
return ret;
-@@ -2085,7 +2023,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
+@@ -2085,7 +2020,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
* it.
*/
if (obj->active) {
@@ -45137,7 +45145,7 @@ index 315a49e..b1f1d10 100644
if (ret)
return ret;
}
-@@ -2123,6 +2062,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
+@@ -2123,6 +2059,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
int
i915_gem_object_unbind(struct drm_i915_gem_object *obj)
{
@@ -45145,7 +45153,7 @@ index 315a49e..b1f1d10 100644
int ret = 0;
if (obj->gtt_space == NULL)
-@@ -2167,6 +2107,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
+@@ -2167,6 +2104,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
trace_i915_gem_object_unbind(obj);
i915_gem_gtt_unbind_object(obj);
@@ -45157,7 +45165,7 @@ index 315a49e..b1f1d10 100644
i915_gem_object_put_pages_gtt(obj);
list_del_init(&obj->gtt_list);
-@@ -2206,7 +2151,7 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
+@@ -2206,7 +2148,7 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
return 0;
}
@@ -45166,7 +45174,7 @@ index 315a49e..b1f1d10 100644
{
int ret;
-@@ -2220,18 +2165,18 @@ static int i915_ring_idle(struct intel_ring_buffer *ring)
+@@ -2220,18 +2162,18 @@ static int i915_ring_idle(struct intel_ring_buffer *ring)
return ret;
}
@@ -45189,7 +45197,7 @@ index 315a49e..b1f1d10 100644
if (ret)
return ret;
}
-@@ -2448,7 +2393,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
+@@ -2448,7 +2390,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
if (!ring_passed_seqno(obj->last_fenced_ring,
obj->last_fenced_seqno)) {
ret = i915_wait_request(obj->last_fenced_ring,
@@ -45199,7 +45207,7 @@ index 315a49e..b1f1d10 100644
if (ret)
return ret;
}
-@@ -2480,6 +2426,8 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
+@@ -2480,6 +2423,8 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
if (obj->fence_reg != I915_FENCE_REG_NONE) {
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
@@ -45208,7 +45216,7 @@ index 315a49e..b1f1d10 100644
i915_gem_clear_fence_reg(obj->base.dev,
&dev_priv->fence_regs[obj->fence_reg]);
-@@ -2504,7 +2452,7 @@ i915_find_fence_reg(struct drm_device *dev,
+@@ -2504,7 +2449,7 @@ i915_find_fence_reg(struct drm_device *dev,
if (!reg->obj)
return reg;
@@ -45217,7 +45225,7 @@ index 315a49e..b1f1d10 100644
avail = reg;
}
-@@ -2514,7 +2462,7 @@ i915_find_fence_reg(struct drm_device *dev,
+@@ -2514,7 +2459,7 @@ i915_find_fence_reg(struct drm_device *dev,
/* None available, try to steal one or wait for a user to finish */
avail = first = NULL;
list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
@@ -45226,7 +45234,7 @@ index 315a49e..b1f1d10 100644
continue;
if (first == NULL)
-@@ -2594,7 +2542,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+@@ -2594,7 +2539,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
if (!ring_passed_seqno(obj->last_fenced_ring,
reg->setup_seqno)) {
ret = i915_wait_request(obj->last_fenced_ring,
@@ -45236,7 +45244,7 @@ index 315a49e..b1f1d10 100644
if (ret)
return ret;
}
-@@ -2613,7 +2562,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+@@ -2613,7 +2559,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
reg = i915_find_fence_reg(dev, pipelined);
if (reg == NULL)
@@ -45245,7 +45253,7 @@ index 315a49e..b1f1d10 100644
ret = i915_gem_object_flush_fence(obj, pipelined);
if (ret)
-@@ -2724,6 +2673,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
+@@ -2724,6 +2670,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
list_del_init(®->lru_list);
reg->obj = NULL;
reg->setup_seqno = 0;
@@ -45253,7 +45261,7 @@ index 315a49e..b1f1d10 100644
}
/**
-@@ -3010,6 +2960,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
+@@ -3010,6 +2957,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level)
{
@@ -45262,7 +45270,7 @@ index 315a49e..b1f1d10 100644
int ret;
if (obj->cache_level == cache_level)
-@@ -3038,6 +2990,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+@@ -3038,6 +2987,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
}
i915_gem_gtt_rebind_object(obj, cache_level);
@@ -45272,7 +45280,7 @@ index 315a49e..b1f1d10 100644
}
if (cache_level == I915_CACHE_NONE) {
-@@ -3376,8 +3331,8 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
+@@ -3376,8 +3328,8 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
ret = -EIO;
@@ -45283,7 +45291,7 @@ index 315a49e..b1f1d10 100644
atomic_read(&dev_priv->mm.wedged), 3000)) {
ret = -EBUSY;
}
-@@ -3688,8 +3643,8 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
+@@ -3688,8 +3640,8 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
@@ -45294,7 +45302,7 @@ index 315a49e..b1f1d10 100644
* cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than
* display scanout are coherent with the CPU in
-@@ -3779,7 +3734,7 @@ i915_gem_idle(struct drm_device *dev)
+@@ -3779,7 +3731,7 @@ i915_gem_idle(struct drm_device *dev)
return 0;
}
@@ -45303,7 +45311,7 @@ index 315a49e..b1f1d10 100644
if (ret) {
mutex_unlock(&dev->struct_mutex);
return ret;
-@@ -3814,12 +3769,91 @@ i915_gem_idle(struct drm_device *dev)
+@@ -3814,12 +3766,91 @@ i915_gem_idle(struct drm_device *dev)
return 0;
}
@@ -45396,7 +45404,7 @@ index 315a49e..b1f1d10 100644
ret = intel_init_render_ring_buffer(dev);
if (ret)
return ret;
-@@ -3838,6 +3872,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
+@@ -3838,6 +3869,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
dev_priv->next_seqno = 1;
@@ -45405,7 +45413,7 @@ index 315a49e..b1f1d10 100644
return 0;
cleanup_bsd_ring:
-@@ -3875,7 +3911,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
+@@ -3875,7 +3908,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
mutex_lock(&dev->struct_mutex);
dev_priv->mm.suspended = 0;
@@ -45414,7 +45422,7 @@ index 315a49e..b1f1d10 100644
if (ret != 0) {
mutex_unlock(&dev->struct_mutex);
return ret;
-@@ -4270,7 +4306,7 @@ rescan:
+@@ -4270,7 +4303,7 @@ rescan:
* This has a dramatic impact to reduce the number of
* OOM-killer events whilst running the GPU aggressively.
*/
@@ -71776,7 +71784,7 @@ index 4760466..4b04ba3 100644
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
-index 76c4f2a..d51c08d 100644
+index 76c4f2a..af6790c 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -231,6 +231,22 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
@@ -71820,31 +71828,7 @@ index 76c4f2a..d51c08d 100644
atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
atombios_enable_crtc(crtc, ATOM_DISABLE);
radeon_crtc->enabled = false;
-@@ -302,10 +318,8 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
- misc |= ATOM_COMPOSITESYNC;
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- misc |= ATOM_INTERLACE;
-- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-- misc |= ATOM_DOUBLE_CLOCK_MODE;
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-- misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
-+ misc |= ATOM_DOUBLE_CLOCK_MODE;
-
- args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
- args.ucCRTC = radeon_crtc->crtc_id;
-@@ -348,10 +362,8 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
- misc |= ATOM_COMPOSITESYNC;
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- misc |= ATOM_INTERLACE;
-- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-- misc |= ATOM_DOUBLE_CLOCK_MODE;
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-- misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
-+ misc |= ATOM_DOUBLE_CLOCK_MODE;
-
- args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
- args.ucCRTC = radeon_crtc->crtc_id;
-@@ -359,15 +371,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
+@@ -359,15 +375,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}
@@ -71862,7 +71846,7 @@ index 76c4f2a..d51c08d 100644
case ATOM_PPLL1:
ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
-@@ -383,7 +392,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
+@@ -383,7 +396,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
return;
}
} else if (ASIC_IS_AVIVO(rdev)) {
@@ -71871,7 +71855,7 @@ index 76c4f2a..d51c08d 100644
case ATOM_PPLL1:
ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
ss_cntl &= ~1;
-@@ -410,16 +419,31 @@ union atom_enable_ss {
+@@ -410,16 +423,31 @@ union atom_enable_ss {
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
};
@@ -71906,7 +71890,7 @@ index 76c4f2a..d51c08d 100644
memset(&args, 0, sizeof(args));
if (ASIC_IS_DCE5(rdev)) {
-@@ -445,7 +469,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -445,7 +473,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
return;
}
args.v3.ucEnable = enable;
@@ -71915,7 +71899,7 @@ index 76c4f2a..d51c08d 100644
args.v3.ucEnable = ATOM_DISABLE;
} else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -483,7 +507,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -483,7 +511,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
} else if (ASIC_IS_AVIVO(rdev)) {
if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
(ss->type & ATOM_EXTERNAL_SS_MASK)) {
@@ -71924,7 +71908,7 @@ index 76c4f2a..d51c08d 100644
return;
}
args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -495,7 +519,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -495,7 +523,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
} else {
if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
(ss->type & ATOM_EXTERNAL_SS_MASK)) {
@@ -71933,7 +71917,7 @@ index 76c4f2a..d51c08d 100644
return;
}
args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -527,6 +551,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -527,6 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
int encoder_mode = 0;
u32 dp_clock = mode->clock;
int bpc = 8;
@@ -71941,7 +71925,7 @@ index 76c4f2a..d51c08d 100644
/* reset the pll flags */
pll->flags = 0;
-@@ -546,7 +571,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -546,7 +575,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
if (rdev->family < CHIP_RV770)
pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
/* use frac fb div on APUs */
@@ -71950,7 +71934,7 @@ index 76c4f2a..d51c08d 100644
pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
/* use frac fb div on RS780/RS880 */
if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
-@@ -566,9 +591,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -566,9 +595,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
if (encoder->crtc == crtc) {
radeon_encoder = to_radeon_encoder(encoder);
connector = radeon_get_connector_for_encoder(encoder);
@@ -71963,7 +71947,7 @@ index 76c4f2a..d51c08d 100644
if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
if (connector) {
-@@ -664,7 +690,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -664,7 +694,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
if (dig->coherent_mode)
args.v3.sInput.ucDispPllConfig |=
DISPPLL_CONFIG_COHERENT_MODE;
@@ -71972,7 +71956,7 @@ index 76c4f2a..d51c08d 100644
args.v3.sInput.ucDispPllConfig |=
DISPPLL_CONFIG_DUAL_LINK;
}
-@@ -714,11 +740,9 @@ union set_pixel_clock {
+@@ -714,11 +744,9 @@ union set_pixel_clock {
/* on DCE5, make sure the voltage is high enough to support the
* required disp clk.
*/
@@ -71985,7 +71969,7 @@ index 76c4f2a..d51c08d 100644
u8 frev, crev;
int index;
union set_pixel_clock args;
-@@ -746,7 +770,12 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
+@@ -746,7 +774,12 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
* SetPixelClock provides the dividers
*/
args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
@@ -71999,7 +71983,7 @@ index 76c4f2a..d51c08d 100644
break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
-@@ -943,7 +972,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -943,7 +976,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
int dp_clock;
@@ -72010,7 +71994,7 @@ index 76c4f2a..d51c08d 100644
switch (encoder_mode) {
case ATOM_ENCODER_MODE_DP_MST:
-@@ -964,13 +995,10 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -964,13 +999,10 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
ss_enabled =
radeon_atombios_get_ppll_ss_info(rdev, &ss,
ATOM_DP_SS_ID1);
@@ -72025,7 +72009,7 @@ index 76c4f2a..d51c08d 100644
}
break;
case ATOM_ENCODER_MODE_LVDS:
-@@ -1015,7 +1043,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -1015,7 +1047,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
&ref_div, &post_div);
@@ -72034,7 +72018,7 @@ index 76c4f2a..d51c08d 100644
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
encoder_mode, radeon_encoder->encoder_id, mode->clock,
-@@ -1038,7 +1066,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -1038,7 +1070,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
ss.step = step_size;
}
@@ -72043,7 +72027,7 @@ index 76c4f2a..d51c08d 100644
}
}
-@@ -1055,6 +1083,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1055,6 +1087,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
struct radeon_bo *rbo;
uint64_t fb_location;
uint32_t fb_format, fb_pitch_pixels, tiling_flags;
@@ -72051,7 +72035,7 @@ index 76c4f2a..d51c08d 100644
u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
u32 tmp, viewport_w, viewport_h;
int r;
-@@ -1145,20 +1174,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1145,20 +1178,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
break;
}
@@ -72078,7 +72062,7 @@ index 76c4f2a..d51c08d 100644
} else if (tiling_flags & RADEON_TILING_MICRO)
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
-@@ -1203,7 +1225,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1203,7 +1229,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
@@ -72087,7 +72071,7 @@ index 76c4f2a..d51c08d 100644
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
-@@ -1372,7 +1394,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1372,7 +1398,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
@@ -72096,7 +72080,7 @@ index 76c4f2a..d51c08d 100644
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
-@@ -1474,7 +1496,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1474,7 +1500,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
struct drm_crtc *test_crtc;
uint32_t pll_in_use = 0;
@@ -72134,7 +72118,7 @@ index 76c4f2a..d51c08d 100644
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
-@@ -1489,6 +1540,8 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1489,6 +1544,8 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
if (rdev->clock.dp_extclk)
return ATOM_PPLL_INVALID;
@@ -72143,7 +72127,7 @@ index 76c4f2a..d51c08d 100644
else if (ASIC_IS_DCE5(rdev))
return ATOM_DCPLL;
}
-@@ -1515,6 +1568,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1515,6 +1572,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
}
@@ -72170,7 +72154,7 @@ index 76c4f2a..d51c08d 100644
int atombios_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
-@@ -1536,19 +1609,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
+@@ -1536,19 +1613,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
}
}
@@ -72190,7 +72174,7 @@ index 76c4f2a..d51c08d 100644
atombios_crtc_set_pll(crtc, adjusted_mode);
if (ASIC_IS_DCE4(rdev))
-@@ -1582,18 +1642,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
+@@ -1582,18 +1646,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
static void atombios_crtc_prepare(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -72219,7 +72203,7 @@ index 76c4f2a..d51c08d 100644
}
static void atombios_crtc_disable(struct drm_crtc *crtc)
-@@ -1605,6 +1675,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
+@@ -1605,6 +1679,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
int i;
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
@@ -72228,7 +72212,7 @@ index 76c4f2a..d51c08d 100644
for (i = 0; i < rdev->num_crtc; i++) {
if (rdev->mode_info.crtcs[i] &&
-@@ -1625,6 +1697,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
+@@ -1625,6 +1701,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
@@ -72978,7 +72962,7 @@ index 7b4eeb7..19a0114 100644
#include <linux/kernel.h>
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
-index 5d78973..c5fe79e 100644
+index 5d78973..db4df97 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -50,6 +50,39 @@ static const u32 crtc_offsets[6] =
@@ -73030,6 +73014,15 @@ index 5d78973..c5fe79e 100644
{
u32 tmp = RREG32(MC_SHARED_CHMAP);
+@@ -1046,7 +1079,7 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+- WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -1136,11 +1169,24 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
if (crtc_enabled) {
@@ -76778,7 +76771,7 @@ index 47f3bd2..52aabf2 100644
#define CAYMAN_DB_DEPTH_INFO 0x2803C
#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
-index 77e6fb1..461262e 100644
+index 77e6fb1..1f45179 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -42,6 +42,8 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev);
@@ -77026,7 +77019,15 @@ index 77e6fb1..461262e 100644
SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
/* Setup L2 cache */
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
-@@ -977,9 +1082,26 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
+@@ -970,16 +1075,33 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
+ L2_CACHE_BIGK_FRAGMENT_SIZE(6));
+ /* setup context0 */
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+- WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
WREG32(VM_CONTEXT0_CNTL2, 0);
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -79220,7 +79221,7 @@ index f36a5c9..57be784 100644
if (r) {
/* Somethings want wront with the accel init stop accel */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
-index e5299a0..9c7062d 100644
+index e5299a0..d441aed 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -49,6 +49,7 @@
@@ -79231,6 +79232,15 @@ index e5299a0..9c7062d 100644
/* Firmware Names */
MODULE_FIRMWARE("radeon/R600_pfp.bin");
+@@ -929,7 +930,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
+ WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+ WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+- WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -1134,7 +1135,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
}
if (rdev->flags & RADEON_IS_AGP) {
@@ -86122,9 +86132,18 @@ index 72ae826..0ebb7d4 100644
dev_priv->flags |= RADEON_IS_AGP;
else if (pci_is_pcie(dev->pdev))
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
-index 0ddc08c..f3ee360 100644
+index 0ddc08c..d66d2cd 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
+@@ -49,7 +49,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
+ if (p->relocs_ptr == NULL) {
+ return -ENOMEM;
+ }
+- p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
++ p->relocs = drm_calloc_large(p->nrelocs, sizeof(struct radeon_bo_list));
+ if (p->relocs == NULL) {
+ return -ENOMEM;
+ }
@@ -58,7 +58,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
duplicate = false;
@@ -86348,6 +86367,15 @@ index 0ddc08c..f3ee360 100644
return 0;
}
+@@ -216,7 +324,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
+ }
+ }
+ kfree(parser->track);
+- kfree(parser->relocs);
++ drm_free_large(parser->relocs);
+ kfree(parser->relocs_ptr);
+ for (i = 0; i < parser->nchunks; i++) {
+ kfree(parser->chunks[i].kdata);
@@ -228,14 +336,186 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
radeon_ib_free(parser->rdev, &parser->ib);
}
@@ -92187,9 +92215,18 @@ index 9103638..0532bbe 100644
if (r) {
/* Somethings want wront with the accel init stop accel */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
-index 3e72074..1ec1255 100644
+index 3e72074..3358730 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
+@@ -158,7 +158,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
+ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+- WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -359,7 +359,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev)
void r700_cp_fini(struct radeon_device *rdev)
{
@@ -92376,7 +92413,7 @@ index 3e72074..1ec1255 100644
radeon_bo_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
new file mode 100644
-index 0000000..068b21f
+index 0000000..3b6e641
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si.c
@@ -0,0 +1,4157 @@
@@ -94919,7 +94956,7 @@ index 0000000..068b21f
+ L2_CACHE_BIGK_FRAGMENT_SIZE(0));
+ /* setup context0 */
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
-+ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
@@ -94937,7 +94974,7 @@ index 0000000..068b21f
+ */
+ /* set vm size, must be a multiple of 4 */
+ WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
-+ WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
++ WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
+ for (i = 1; i < 16; i++) {
+ if (i < 8)
+ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
--
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