[linux] 01/03: Add USB support for NVIDIA Jetson TX1 Developer Kit
debian-kernel at lists.debian.org
debian-kernel at lists.debian.org
Tue Aug 2 23:43:45 UTC 2016
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commit 02b2135a4bebe62b87283fe6d22ce8ed40b9914b
Author: Martin Michlmayr <tbm at cyrius.com>
Date: Tue Aug 2 15:51:49 2016 -0700
Add USB support for NVIDIA Jetson TX1 Developer Kit
Add patches from 4.8-rc1 required for USB support on the NVIDIA Jetson
TX1 Developer Kit.
---
debian/changelog | 14 +
debian/config/arm64/config | 12 +-
.../arm64-tegra-add-dsi-panel-on-jetson-tx1.patch | 139 ++++
...rm64-tegra-add-pmic-support-on-jetson-tx1.patch | 351 ++++++++++
.../arm64-tegra-add-tegra210-xusb-controller.patch | 64 ++
...64-tegra-add-tegra210-xusb-pad-controller.patch | 182 +++++
...a-correct-tegra210-xusb-mailbox-interrupt.patch | 33 +
...4-tegra-enable-debug-serial-on-jetson-tx1.patch | 32 +
...egra-enable-xusb-controller-on-jetson-tx1.patch | 198 ++++++
...rm64-tegra-p2597-add-sdmmc-power-supplies.patch | 53 ++
.../arm/gpio-max77620-add-gpio-driver.patch | 295 ++++++++
...ax77620-configure-interrupt-trigger-level.patch | 106 +++
...ax77620-get-gpio-value-based-on-direction.patch | 34 +
...-max77620-use-the-new-open-drain-callback.patch | 59 ++
.../pinctrl-max77620-add-pincontrol-driver.patch | 738 +++++++++++++++++++++
debian/patches/series | 14 +
16 files changed, 2318 insertions(+), 6 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index c29efab..5d770bf 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -10,6 +10,20 @@ linux (4.7~rc7-1~exp2) UNRELEASED; urgency=medium
[ Martin Michlmayr ]
* [armhf] Enable MMC_SDHCI_IPROC and HW_RANDOM_BCM2835 for BCM2835.
+ * [arm64] Add USB support for NVIDIA Jetson TX1 Developer Kit:
+ - pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
+ - gpio: max77620: add gpio driver for MAX77620/MAX20024
+ - gpio: max77620: Configure interrupt trigger level
+ - gpio: max77620: use the new open drain callback
+ - gpio: max77620: get gpio value based on direction
+ - arm64: tegra: Add PMIC support on Jetson TX1
+ - arm64: tegra: p2597: Add SDMMC power supplies
+ - arm64: tegra: Add DSI panel on Jetson TX1
+ - arm64: tegra: Add Tegra210 XUSB pad controller
+ - arm64: tegra: Add Tegra210 XUSB controller
+ - arm64: tegra: Enable debug serial on Jetson TX1
+ - arm64: tegra: Enable XUSB controller on Jetson TX1
+ - arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
-- Ben Hutchings <ben at decadent.org.uk> Wed, 20 Jul 2016 03:50:18 +0100
diff --git a/debian/config/arm64/config b/debian/config/arm64/config
index 6a4c90d..42da1fa 100644
--- a/debian/config/arm64/config
+++ b/debian/config/arm64/config
@@ -89,6 +89,7 @@ CONFIG_EXTCON=m
CONFIG_GPIOLIB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
##
## file: drivers/gpu/drm/Kconfig
@@ -308,6 +309,11 @@ CONFIG_PHY_QCOM_UFS=m
CONFIG_PHY_TEGRA_XUSB=m
##
+## file: drivers/pinctrl/Kconfig
+##
+CONFIG_PINCTRL_MAX77620=y
+
+##
## file: drivers/pinctrl/qcom/Kconfig
##
CONFIG_PINCTRL_MSM8916=y
@@ -486,9 +492,3 @@ CONFIG_SND_SOC_TEGRA_ALC5632=m
CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_TEGRA_RT5677=m
-##
-## file: unknown
-##
-CONFIG_GPIO_MAX77620=y
-CONFIG_PINCTRL_MAX77620=y
-
diff --git a/debian/patches/features/arm/arm64-tegra-add-dsi-panel-on-jetson-tx1.patch b/debian/patches/features/arm/arm64-tegra-add-dsi-panel-on-jetson-tx1.patch
new file mode 100644
index 0000000..7ae6712
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-add-dsi-panel-on-jetson-tx1.patch
@@ -0,0 +1,139 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 7596723ecd54456da4b8bc5afc4a961aa09bd34b
+Author: Thierry Reding <treding at nvidia.com>
+Date: Mon Nov 23 16:21:43 2015 +0100
+
+ arm64: tegra: Add DSI panel on Jetson TX1
+
+ Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel
+ connected via four DSI lanes.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+index 683b339..983775e 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+@@ -6,4 +6,49 @@
+ / {
+ model = "NVIDIA Jetson TX1 Developer Kit";
+ compatible = "nvidia,p2371-2180", "nvidia,tegra210";
++
++ host1x at 50000000 {
++ dsi at 54300000 {
++ status = "okay";
++
++ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
++
++ panel at 0 {
++ compatible = "auo,b080uan01";
++ reg = <0>;
++
++ enable-gpios = <&gpio TEGRA_GPIO(V, 2)
++ GPIO_ACTIVE_HIGH>;
++ power-supply = <&vdd_5v0_io>;
++ backlight = <&backlight>;
++ };
++ };
++ };
++
++ i2c at 7000c400 {
++ backlight: backlight at 2c {
++ compatible = "ti,lp8557";
++ reg = <0x2c>;
++
++ dev-ctrl = /bits/ 8 <0x80>;
++ init-brt = /bits/ 8 <0xff>;
++
++ pwm-period = <29334>;
++
++ pwms = <&pwm 0 29334>;
++ pwm-names = "lp8557";
++
++ /* 3 LED string */
++ rom_14h {
++ rom-addr = /bits/ 8 <0x14>;
++ rom-val = /bits/ 8 <0x87>;
++ };
++
++ /* boost frequency 1 MHz */
++ rom_13h {
++ rom-addr = /bits/ 8 <0x13>;
++ rom-val = /bits/ 8 <0x01>;
++ };
++ };
++ };
+ };
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+index b28aff5..78a16a5 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+@@ -1261,6 +1261,23 @@
+ };
+ };
+
++ pwm at 7000a000 {
++ status = "okay";
++ };
++
++ i2c at 7000c400 {
++ status = "okay";
++ clock-frequency = <100000>;
++
++ exp1: gpio at 74 {
++ compatible = "ti,tca9539";
++ reg = <0x74>;
++
++ #gpio-cells = <2>;
++ gpio-controller;
++ };
++ };
++
+ /* MMC/SD */
+ sdhci at 700b0000 {
+ status = "okay";
+@@ -1340,6 +1357,39 @@
+ regulator-enable-ramp-delay = <472>;
+ regulator-disable-ramp-delay = <4880>;
+ };
++
++ vdd_dsi_csi: regulator at 5 {
++ compatible = "regulator-fixed";
++ reg = <5>;
++ regulator-name = "AVDD_DSI_CSI_1V2";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ vin-supply = <&vdd_sys_1v2>;
++ };
++
++ vdd_3v3_dis: regulator at 6 {
++ compatible = "regulator-fixed";
++ reg = <6>;
++ regulator-name = "VDD_DIS_3V3_LCD";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_3v3_sys>;
++ };
++
++ vdd_1v8_dis: regulator at 7 {
++ compatible = "regulator-fixed";
++ reg = <7>;
++ regulator-name = "VDD_LCD_1V8_DIS";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_1v8>;
++ };
+ };
+
+ gpio-keys {
diff --git a/debian/patches/features/arm/arm64-tegra-add-pmic-support-on-jetson-tx1.patch b/debian/patches/features/arm/arm64-tegra-add-pmic-support-on-jetson-tx1.patch
new file mode 100644
index 0000000..b424a1d
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-add-pmic-support-on-jetson-tx1.patch
@@ -0,0 +1,351 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 77934269438e1a4a32f1b9a357f39422f58dcf89
+Author: Thierry Reding <treding at nvidia.com>
+Date: Mon Nov 23 16:20:35 2015 +0100
+
+ arm64: tegra: Add PMIC support on Jetson TX1
+
+ Add a device tree node for the MAX77620 PMIC found on the p2180
+ processor module (Jetson TX1). Also add supporting power supplies,
+ such as the main 5 V system supply.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+index 316c92c..8335bbe 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+@@ -1,3 +1,5 @@
++#include <dt-bindings/mfd/max77620.h>
++
+ #include "tegra210.dtsi"
+
+ / {
+@@ -5,6 +7,7 @@
+ compatible = "nvidia,p2180", "nvidia,tegra210";
+
+ aliases {
++ rtc0 = "/i2c at 7000d000/pmic at 3c";
+ rtc1 = "/rtc at 7000e000";
+ serial0 = &uarta;
+ };
+@@ -19,6 +22,248 @@
+ status = "okay";
+ };
+
++ i2c at 7000d000 {
++ status = "okay";
++ clock-frequency = <400000>;
++
++ pmic: pmic at 3c {
++ compatible = "maxim,max77620";
++ reg = <0x3c>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++
++ #interrupt-cells = <2>;
++ interrupt-controller;
++
++ #gpio-cells = <2>;
++ gpio-controller;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&max77620_default>;
++
++ max77620_default: pinmux {
++ gpio0 {
++ pins = "gpio0";
++ function = "gpio";
++ };
++
++ gpio1 {
++ pins = "gpio1";
++ function = "fps-out";
++ drive-push-pull = <1>;
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ maxim,active-fps-power-up-slot = <7>;
++ maxim,active-fps-power-down-slot = <0>;
++ };
++
++ gpio2_3 {
++ pins = "gpio2", "gpio3";
++ function = "fps-out";
++ drive-open-drain = <1>;
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ };
++
++ gpio4 {
++ pins = "gpio4";
++ function = "32k-out1";
++ };
++
++ gpio5_6_7 {
++ pins = "gpio5", "gpio6", "gpio7";
++ function = "gpio";
++ drive-push-pull = <1>;
++ };
++ };
++
++ fps {
++ fps0 {
++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
++ maxim,suspend-fps-time-period-us = <1280>;
++ };
++
++ fps1 {
++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
++ maxim,suspend-fps-time-period-us = <1280>;
++ };
++
++ fps2 {
++ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
++ };
++ };
++
++ regulators {
++ in-ldo0-1-supply = <&vdd_pre>;
++ in-ldo7-8-supply = <&vdd_pre>;
++ in-sd3-supply = <&vdd_5v0_sys>;
++
++ vdd_soc: sd0 {
++ regulator-name = "VDD_SOC";
++ regulator-min-microvolt = <600000>;
++ regulator-max-microvolt = <1400000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <146>;
++ regulator-ramp-delay = <27500>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++ };
++
++ vdd_ddr: sd1 {
++ regulator-name = "VDD_DDR_1V1_PMIC";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <130>;
++ regulator-ramp-delay = <27500>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ };
++
++ vdd_pre: sd2 {
++ regulator-name = "VDD_PRE_REG_1V35";
++ regulator-min-microvolt = <1350000>;
++ regulator-max-microvolt = <1350000>;
++
++ regulator-enable-ramp-delay = <176>;
++ regulator-ramp-delay = <27500>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++ };
++
++ vdd_1v8: sd3 {
++ regulator-name = "VDD_1V8";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <242>;
++ regulator-ramp-delay = <27500>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ };
++
++ vdd_sys_1v2: ldo0 {
++ regulator-name = "AVDD_SYS_1V2";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <26>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++ };
++
++ vdd_pex_1v05: ldo1 {
++ regulator-name = "VDD_PEX_1V05";
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1050000>;
++
++ regulator-enable-ramp-delay = <22>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++ };
++
++ vddio_sdmmc: ldo2 {
++ regulator-name = "VDDIO_SDMMC";
++ /*
++ * Technically this supply should have
++ * a supported range from 1.8 - 3.3 V.
++ * However, that would cause the SDHCI
++ * driver to request 2.7 V upon access
++ * and that in turn will cause traffic
++ * to be broken. Leave it at 3.3 V for
++ * now.
++ */
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <62>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++ };
++
++ vdd_cam_hv: ldo3 {
++ regulator-name = "VDD_CAM_HV";
++ regulator-min-microvolt = <2800000>;
++ regulator-max-microvolt = <2800000>;
++
++ regulator-enable-ramp-delay = <50>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++ };
++
++ vdd_rtc: ldo4 {
++ regulator-name = "VDD_RTC";
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <22>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ };
++
++ vdd_ts_hv: ldo5 {
++ regulator-name = "VDD_TS_HV";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-enable-ramp-delay = <62>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
++ };
++
++ vdd_ts: ldo6 {
++ regulator-name = "VDD_TS_1V8";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-enable-ramp-delay = <36>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
++ maxim,active-fps-power-up-slot = <7>;
++ maxim,active-fps-power-down-slot = <0>;
++ };
++
++ avdd_1v05_pll: ldo7 {
++ regulator-name = "AVDD_1V05_PLL";
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-enable-ramp-delay = <24>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++ };
++
++ avdd_1v05: ldo8 {
++ regulator-name = "AVDD_SATA_HDMI_DP_1V05";
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1050000>;
++
++ regulator-enable-ramp-delay = <22>;
++ regulator-ramp-delay = <100000>;
++
++ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
++ };
++ };
++ };
++ };
++
+ pmc at 7000e400 {
+ nvidia,invert-interrupt;
+ };
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+index a2480c0..27bb835 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+@@ -1270,6 +1270,61 @@
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ };
+
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vdd_sys_mux: regulator at 0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ regulator-name = "VDD_SYS_MUX";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ vdd_5v0_sys: regulator at 1 {
++ compatible = "regulator-fixed";
++ reg = <1>;
++ regulator-name = "VDD_5V0_SYS";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_sys_mux>;
++ };
++
++ vdd_3v3_sys: regulator at 2 {
++ compatible = "regulator-fixed";
++ reg = <2>;
++ regulator-name = "VDD_3V3_SYS";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_sys_mux>;
++
++ regulator-enable-ramp-delay = <160>;
++ regulator-disable-ramp-delay = <10000>;
++ };
++
++ vdd_5v0_io: regulator at 3 {
++ compatible = "regulator-fixed";
++ reg = <3>;
++ regulator-name = "VDD_5V0_IO_SYS";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++ };
++
+ gpio-keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
diff --git a/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-controller.patch b/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-controller.patch
new file mode 100644
index 0000000..f26eb88
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-controller.patch
@@ -0,0 +1,64 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit e7a99ac299924b714e2b7c9f36e435b89c035b3b
+Author: Thierry Reding <treding at nvidia.com>
+Date: Thu Nov 12 11:28:36 2015 +0100
+
+ arm64: tegra: Add Tegra210 XUSB controller
+
+ Add a device tree node for the Tegra XUSB controller. It contains a
+ phandle to the XUSB pad controller for control of the PHYs assigned
+ to the USB ports.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+index 694228b..ac1fb88 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+@@ -621,6 +621,41 @@
+ status = "disabled";
+ };
+
++ usb at 70090000 {
++ compatible = "nvidia,tegra210-xusb";
++ reg = <0x0 0x70090000 0x0 0x8000>,
++ <0x0 0x70098000 0x0 0x1000>,
++ <0x0 0x70099000 0x0 0x1000>;
++ reg-names = "hcd", "fpci", "ipfs";
++
++ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
++ <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
++ <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
++ <&tegra_car TEGRA210_CLK_XUSB_SS>,
++ <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
++ <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
++ <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
++ <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
++ <&tegra_car TEGRA210_CLK_PLL_U_480M>,
++ <&tegra_car TEGRA210_CLK_CLK_M>,
++ <&tegra_car TEGRA210_CLK_PLL_E>;
++ clock-names = "xusb_host", "xusb_host_src",
++ "xusb_falcon_src", "xusb_ss",
++ "xusb_ss_div2", "xusb_ss_src",
++ "xusb_hs_src", "xusb_fs_src",
++ "pll_u_480m", "clk_m", "pll_e";
++ resets = <&tegra_car 89>, <&tegra_car 156>,
++ <&tegra_car 143>;
++ reset-names = "xusb_host", "xusb_ss", "xusb_src";
++
++ nvidia,xusb-padctl = <&padctl>;
++
++ status = "disabled";
++ };
++
+ padctl: padctl at 7009f000 {
+ compatible = "nvidia,tegra210-xusb-padctl";
+ reg = <0x0 0x7009f000 0x0 0x1000>;
diff --git a/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-pad-controller.patch b/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-pad-controller.patch
new file mode 100644
index 0000000..9981881
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-add-tegra210-xusb-pad-controller.patch
@@ -0,0 +1,182 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 4e07ac9076beb1341a919c55f3a080d4fe991882
+Author: Thierry Reding <treding at nvidia.com>
+Date: Thu Nov 12 11:28:35 2015 +0100
+
+ arm64: tegra: Add Tegra210 XUSB pad controller
+
+ Add a device tree node for the XUSB pad controller found on Tegra210.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+index 76fe31f..694228b 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+@@ -621,6 +621,161 @@
+ status = "disabled";
+ };
+
++ padctl: padctl at 7009f000 {
++ compatible = "nvidia,tegra210-xusb-padctl";
++ reg = <0x0 0x7009f000 0x0 0x1000>;
++ resets = <&tegra_car 142>;
++ reset-names = "padctl";
++
++ status = "disabled";
++
++ pads {
++ usb2 {
++ clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
++ clock-names = "trk";
++ status = "disabled";
++
++ lanes {
++ usb2-0 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ usb2-1 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ usb2-2 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ usb2-3 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++ };
++ };
++
++ hsic {
++ clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
++ clock-names = "trk";
++ status = "disabled";
++
++ lanes {
++ hsic-0 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ hsic-1 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++ };
++ };
++
++ pcie {
++ clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
++ clock-names = "pll";
++ resets = <&tegra_car 205>;
++ reset-names = "phy";
++ status = "disabled";
++
++ lanes {
++ pcie-0 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-1 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-2 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-3 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-4 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-5 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++
++ pcie-6 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++ };
++ };
++
++ sata {
++ clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
++ clock-names = "pll";
++ resets = <&tegra_car 204>;
++ reset-names = "phy";
++ status = "disabled";
++
++ lanes {
++ sata-0 {
++ status = "disabled";
++ #phy-cells = <0>;
++ };
++ };
++ };
++ };
++
++ ports {
++ usb2-0 {
++ status = "disabled";
++ };
++
++ usb2-1 {
++ status = "disabled";
++ };
++
++ usb2-2 {
++ status = "disabled";
++ };
++
++ usb2-3 {
++ status = "disabled";
++ };
++
++ hsic-0 {
++ status = "disabled";
++ };
++
++ usb3-0 {
++ status = "disabled";
++ };
++
++ usb3-1 {
++ status = "disabled";
++ };
++
++ usb3-2 {
++ status = "disabled";
++ };
++
++ usb3-3 {
++ status = "disabled";
++ };
++ };
++ };
++
+ sdhci at 700b0000 {
+ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ reg = <0x0 0x700b0000 0x0 0x200>;
diff --git a/debian/patches/features/arm/arm64-tegra-correct-tegra210-xusb-mailbox-interrupt.patch b/debian/patches/features/arm/arm64-tegra-correct-tegra210-xusb-mailbox-interrupt.patch
new file mode 100644
index 0000000..eb83452
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-correct-tegra210-xusb-mailbox-interrupt.patch
@@ -0,0 +1,33 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 9168e1db754383ea16b75ffcc1efbb9b09cfae64
+Author: Jon Hunter <jonathanh at nvidia.com>
+Date: Wed Jun 29 12:07:33 2016 +0100
+
+ arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
+
+ The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
+ the XUSB pad controller. For some Tegra210 boards, this is causing USB
+ connect and disconnect events to go undetected. Fix this by changing the
+ interrupt number for the XUSB mailbox to 40.
+
+ Signed-off-by: Jon Hunter <jonathanh at nvidia.com>
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+index ac1fb88..b731880 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+@@ -629,7 +629,7 @@
+ reg-names = "hcd", "fpci", "ipfs";
+
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
+ <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
diff --git a/debian/patches/features/arm/arm64-tegra-enable-debug-serial-on-jetson-tx1.patch b/debian/patches/features/arm/arm64-tegra-enable-debug-serial-on-jetson-tx1.patch
new file mode 100644
index 0000000..85b3a1a
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-enable-debug-serial-on-jetson-tx1.patch
@@ -0,0 +1,32 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 5593eb76b602e3ab2d525cdeecd49c0978e3b0e6
+Author: Thierry Reding <treding at nvidia.com>
+Date: Thu Jun 2 14:07:47 2016 +0200
+
+ arm64: tegra: Enable debug serial on Jetson TX1
+
+ Add a chosen node to the device tree that contains a stdout-path
+ property which defines the debug serial port.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+index 8335bbe..5fda583 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+@@ -12,6 +12,10 @@
+ serial0 = &uarta;
+ };
+
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
diff --git a/debian/patches/features/arm/arm64-tegra-enable-xusb-controller-on-jetson-tx1.patch b/debian/patches/features/arm/arm64-tegra-enable-xusb-controller-on-jetson-tx1.patch
new file mode 100644
index 0000000..40fe840
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-enable-xusb-controller-on-jetson-tx1.patch
@@ -0,0 +1,198 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit d23e054c66ec3daa91ef4ea43d9a99ea65d4e8da
+Author: Thierry Reding <treding at nvidia.com>
+Date: Thu Jun 2 14:22:41 2016 +0200
+
+ arm64: tegra: Enable XUSB controller on Jetson TX1
+
+ Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes
+ to an internal ethernet interface, while a second USB 3.0 lane supports
+ the USB-A receptacle on the I/O board.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+index 78a16a5..8bba178 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+@@ -1278,6 +1278,146 @@
+ };
+ };
+
++ usb at 70090000 {
++ phys = <&{/padctl at 7009f000/pads/usb2/lanes/usb2-0}>,
++ <&{/padctl at 7009f000/pads/usb2/lanes/usb2-1}>,
++ <&{/padctl at 7009f000/pads/usb2/lanes/usb2-2}>,
++ <&{/padctl at 7009f000/pads/usb2/lanes/usb2-3}>,
++ <&{/padctl at 7009f000/pads/pcie/lanes/pcie-6}>,
++ <&{/padctl at 7009f000/pads/pcie/lanes/pcie-5}>;
++ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
++ "usb3-1";
++
++ dvddio-pex-supply = <&vdd_pex_1v05>;
++ hvddio-pex-supply = <&vdd_1v8>;
++ avdd-usb-supply = <&vdd_3v3_sys>;
++ /* XXX what are these? */
++ avdd-pll-utmip-supply = <&vdd_1v8>;
++ avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
++ dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
++ hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
++
++ status = "okay";
++ };
++
++ padctl at 7009f000 {
++ status = "okay";
++
++ pads {
++ usb2 {
++ status = "okay";
++
++ lanes {
++ usb2-0 {
++ nvidia,function = "xusb";
++ status = "okay";
++ };
++
++ usb2-1 {
++ nvidia,function = "xusb";
++ status = "okay";
++ };
++
++ usb2-2 {
++ nvidia,function = "xusb";
++ status = "okay";
++ };
++
++ usb2-3 {
++ nvidia,function = "xusb";
++ status = "okay";
++ };
++ };
++ };
++
++ pcie {
++ status = "okay";
++
++ lanes {
++ pcie-0 {
++ nvidia,function = "pcie-x1";
++ status = "okay";
++ };
++
++ pcie-1 {
++ nvidia,function = "pcie-x4";
++ status = "okay";
++ };
++
++ pcie-2 {
++ nvidia,function = "pcie-x4";
++ status = "okay";
++ };
++
++ pcie-3 {
++ nvidia,function = "pcie-x4";
++ status = "okay";
++ };
++
++ pcie-4 {
++ nvidia,function = "pcie-x4";
++ status = "okay";
++ };
++
++ pcie-5 {
++ nvidia,function = "usb3-ss";
++ status = "okay";
++ };
++
++ pcie-6 {
++ nvidia,function = "usb3-ss";
++ status = "okay";
++ };
++ };
++ };
++
++ sata {
++ status = "okay";
++
++ lanes {
++ sata-0 {
++ nvidia,function = "sata";
++ status = "okay";
++ };
++ };
++ };
++ };
++
++ ports {
++ usb2-0 {
++ status = "okay";
++ mode = "otg";
++ };
++
++ usb2-1 {
++ status = "okay";
++ vbus-supply = <&vdd_5v0_rtl>;
++ mode = "host";
++ };
++
++ usb2-2 {
++ status = "okay";
++ vbus-supply = <&vdd_usb_vbus>;
++ mode = "host";
++ };
++
++ usb2-3 {
++ status = "okay";
++ mode = "host";
++ };
++
++ usb3-0 {
++ nvidia,usb2-companion = <1>;
++ status = "okay";
++ };
++
++ usb3-1 {
++ nvidia,usb2-companion = <2>;
++ status = "okay";
++ };
++ };
++ };
++
+ /* MMC/SD */
+ sdhci at 700b0000 {
+ status = "okay";
+@@ -1390,6 +1530,28 @@
+ enable-active-high;
+ vin-supply = <&vdd_1v8>;
+ };
++
++ vdd_5v0_rtl: regulator at 8 {
++ compatible = "regulator-fixed";
++ reg = <8>;
++ regulator-name = "RTL_5V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_5v0_sys>;
++ };
++
++ vdd_usb_vbus: regulator at 9 {
++ compatible = "regulator-fixed";
++ reg = <9>;
++ regulator-name = "USB_VBUS_EN1";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_5v0_sys>;
++ };
+ };
+
+ gpio-keys {
diff --git a/debian/patches/features/arm/arm64-tegra-p2597-add-sdmmc-power-supplies.patch b/debian/patches/features/arm/arm64-tegra-p2597-add-sdmmc-power-supplies.patch
new file mode 100644
index 0000000..3671fd7
--- /dev/null
+++ b/debian/patches/features/arm/arm64-tegra-p2597-add-sdmmc-power-supplies.patch
@@ -0,0 +1,53 @@
+
+Taken from the Linux Tegra tree. Patch has been accepted for 4.8-rc1
+
+Origin: https://git.kernel.org/cgit/linux/kernel/git/tegra/linux.git/log/?h=for-4.8/arm64/dt
+
+
+commit 6d5aef5b9517974a181d06b0bed4bc66b32f3660
+Author: Thierry Reding <treding at nvidia.com>
+Date: Fri Mar 4 15:26:47 2016 +0100
+
+ arm64: tegra: p2597: Add SDMMC power supplies
+
+ Add power supplies for the SD/MMC card slot. Note that vmmc-supply is
+ currently restricted to 3.3 V because we don't support switching the
+ mode yet.
+
+ Signed-off-by: Thierry Reding <treding at nvidia.com>
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+index 27bb835..b28aff5 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+@@ -1268,6 +1268,9 @@
+ no-1-8-v;
+
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
++
++ vqmmc-supply = <&vddio_sdmmc>;
++ vmmc-supply = <&vdd_3v3_sd>;
+ };
+
+ regulators {
+@@ -1323,6 +1326,20 @@
+ regulator-always-on;
+ regulator-boot-on;
+ };
++
++ vdd_3v3_sd: regulator at 4 {
++ compatible = "regulator-fixed";
++ reg = <4>;
++ regulator-name = "VDD_3V3_SD";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ vin-supply = <&vdd_3v3_sys>;
++
++ regulator-enable-ramp-delay = <472>;
++ regulator-disable-ramp-delay = <4880>;
++ };
+ };
+
+ gpio-keys {
diff --git a/debian/patches/features/arm/gpio-max77620-add-gpio-driver.patch b/debian/patches/features/arm/gpio-max77620-add-gpio-driver.patch
new file mode 100644
index 0000000..ce629c2
--- /dev/null
+++ b/debian/patches/features/arm/gpio-max77620-add-gpio-driver.patch
@@ -0,0 +1,295 @@
+
+Patch has been accepted for 4.8-rc1
+
+
+commit 02c5ba1ee99cd67b27f562c120ae659e8acadded
+Author: Laxman Dewangan <ldewangan at nvidia.com>
+Date: Fri May 13 10:49:14 2016 +0530
+
+ gpio: max77620: add gpio driver for MAX77620/MAX20024
+
+ MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO
+ pins. It also supports interrupts from these pins.
+
+ Add GPIO driver for these pins to control via GPIO APIs.
+
+ Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
+ Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
+ Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
+
+diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
+index 48da857..9244381 100644
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -871,6 +871,15 @@ config GPIO_LP3943
+ LP3943 can be used as a GPIO expander which provides up to 16 GPIOs.
+ Open drain outputs are required for this usage.
+
++config GPIO_MAX77620
++ tristate "GPIO support for PMIC MAX77620 and MAX20024"
++ depends on MFD_MAX77620
++ help
++ GPIO driver for MAX77620 and MAX20024 PMIC from Maxim Semiconductor.
++ MAX77620 PMIC has 8 pins that can be configured as GPIOs. The
++ driver also provides interrupt support for each of the gpios.
++ Say yes here to enable the max77620 to be used as gpio controller.
++
+ config GPIO_MSIC
+ bool "Intel MSIC mixed signal gpio support"
+ depends on MFD_INTEL_MSIC
+diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
+index 991598e..6e111fc 100644
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
+ obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
+ obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
+ obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
++obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o
+ obj-$(CONFIG_GPIO_MB86S7X) += gpio-mb86s7x.o
+ obj-$(CONFIG_GPIO_MENZ127) += gpio-menz127.o
+ obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+new file mode 100644
+index 0000000..d927562
+--- /dev/null
++++ b/drivers/gpio/gpio-max77620.c
+@@ -0,0 +1,238 @@
++/*
++ * MAXIM MAX77620 GPIO driver
++ *
++ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ */
++
++#include <linux/gpio/driver.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/max77620.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
++
++struct max77620_gpio {
++ struct gpio_chip gpio_chip;
++ struct regmap *rmap;
++ struct device *dev;
++ int gpio_irq;
++ int irq_base;
++ int gpio_base;
++};
++
++static const struct regmap_irq max77620_gpio_irqs[] = {
++ REGMAP_IRQ_REG(0, 0, MAX77620_IRQ_LVL2_GPIO_EDGE0),
++ REGMAP_IRQ_REG(1, 0, MAX77620_IRQ_LVL2_GPIO_EDGE1),
++ REGMAP_IRQ_REG(2, 0, MAX77620_IRQ_LVL2_GPIO_EDGE2),
++ REGMAP_IRQ_REG(3, 0, MAX77620_IRQ_LVL2_GPIO_EDGE3),
++ REGMAP_IRQ_REG(4, 0, MAX77620_IRQ_LVL2_GPIO_EDGE4),
++ REGMAP_IRQ_REG(5, 0, MAX77620_IRQ_LVL2_GPIO_EDGE5),
++ REGMAP_IRQ_REG(6, 0, MAX77620_IRQ_LVL2_GPIO_EDGE6),
++ REGMAP_IRQ_REG(7, 0, MAX77620_IRQ_LVL2_GPIO_EDGE7),
++};
++
++static struct regmap_irq_chip max77620_gpio_irq_chip = {
++ .name = "max77620-gpio",
++ .irqs = max77620_gpio_irqs,
++ .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
++ .num_regs = 1,
++ .irq_reg_stride = 1,
++ .status_base = MAX77620_REG_IRQ_LVL2_GPIO,
++};
++
++static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ int ret;
++
++ ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_DIR_MASK,
++ MAX77620_CNFG_GPIO_DIR_INPUT);
++ if (ret < 0)
++ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
++
++ return ret;
++}
++
++static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ unsigned int val;
++ int ret;
++
++ ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
++ if (ret < 0) {
++ dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
++ return ret;
++ }
++
++ return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
++}
++
++static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
++ int value)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ u8 val;
++ int ret;
++
++ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
++ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
++
++ ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
++ if (ret < 0) {
++ dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
++ return ret;
++ }
++
++ ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_DIR_MASK,
++ MAX77620_CNFG_GPIO_DIR_OUTPUT);
++ if (ret < 0)
++ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
++
++ return ret;
++}
++
++static int max77620_gpio_set_debounce(struct gpio_chip *gc,
++ unsigned int offset,
++ unsigned int debounce)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ u8 val;
++ int ret;
++
++ switch (debounce) {
++ case 0:
++ val = MAX77620_CNFG_GPIO_DBNC_None;
++ break;
++ case 1 ... 8:
++ val = MAX77620_CNFG_GPIO_DBNC_8ms;
++ break;
++ case 9 ... 16:
++ val = MAX77620_CNFG_GPIO_DBNC_16ms;
++ break;
++ case 17 ... 32:
++ val = MAX77620_CNFG_GPIO_DBNC_32ms;
++ break;
++ default:
++ dev_err(mgpio->dev, "Illegal value %u\n", debounce);
++ return -EINVAL;
++ }
++
++ ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_DBNC_MASK, val);
++ if (ret < 0)
++ dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
++
++ return ret;
++}
++
++static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
++ int value)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ u8 val;
++ int ret;
++
++ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
++ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
++
++ ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
++ if (ret < 0)
++ dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
++}
++
++static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
++
++ return regmap_irq_get_virq(chip->gpio_irq_data, offset);
++}
++
++static int max77620_gpio_probe(struct platform_device *pdev)
++{
++ struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
++ struct max77620_gpio *mgpio;
++ int gpio_irq;
++ int ret;
++
++ gpio_irq = platform_get_irq(pdev, 0);
++ if (gpio_irq <= 0) {
++ dev_err(&pdev->dev, "GPIO irq not available %d\n", gpio_irq);
++ return -ENODEV;
++ }
++
++ mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
++ if (!mgpio)
++ return -ENOMEM;
++
++ mgpio->rmap = chip->rmap;
++ mgpio->dev = &pdev->dev;
++ mgpio->gpio_irq = gpio_irq;
++
++ mgpio->gpio_chip.label = pdev->name;
++ mgpio->gpio_chip.parent = &pdev->dev;
++ mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
++ mgpio->gpio_chip.get = max77620_gpio_get;
++ mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
++ mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
++ mgpio->gpio_chip.set = max77620_gpio_set;
++ mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
++ mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
++ mgpio->gpio_chip.can_sleep = 1;
++ mgpio->gpio_chip.base = -1;
++ mgpio->irq_base = -1;
++#ifdef CONFIG_OF_GPIO
++ mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
++#endif
++
++ platform_set_drvdata(pdev, mgpio);
++
++ ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
++ return ret;
++ }
++
++ mgpio->gpio_base = mgpio->gpio_chip.base;
++ ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, mgpio->gpio_irq,
++ IRQF_ONESHOT, mgpio->irq_base,
++ &max77620_gpio_irq_chip,
++ &chip->gpio_irq_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static const struct platform_device_id max77620_gpio_devtype[] = {
++ { .name = "max77620-gpio", },
++ {},
++};
++MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
++
++static struct platform_driver max77620_gpio_driver = {
++ .driver.name = "max77620-gpio",
++ .probe = max77620_gpio_probe,
++ .id_table = max77620_gpio_devtype,
++};
++
++module_platform_driver(max77620_gpio_driver);
++
++MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
++MODULE_AUTHOR("Laxman Dewangan <ldewangan at nvidia.com>");
++MODULE_AUTHOR("Chaitanya Bandi <bandik at nvidia.com>");
++MODULE_ALIAS("platform:max77620-gpio");
++MODULE_LICENSE("GPL v2");
diff --git a/debian/patches/features/arm/gpio-max77620-configure-interrupt-trigger-level.patch b/debian/patches/features/arm/gpio-max77620-configure-interrupt-trigger-level.patch
new file mode 100644
index 0000000..c506ee2
--- /dev/null
+++ b/debian/patches/features/arm/gpio-max77620-configure-interrupt-trigger-level.patch
@@ -0,0 +1,106 @@
+
+Patch has been accepted for 4.8-rc1
+
+
+commit ff93ec74966a84538a8129d7d8303a7f841a69c4
+Author: Laxman Dewangan <ldewangan at nvidia.com>
+Date: Tue May 24 18:43:44 2016 +0530
+
+ gpio: max77620: Configure interrupt trigger level
+
+ The GPIO sub modules of MAX77620 offers to configure the GPIO
+ interrupt trigger level as RISING and FALLING edge.
+
+ Pass this information to regmap-irg when registering for GPIO
+ interrupts.
+
+ Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
+ Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index d927562..35f365c 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -27,14 +27,62 @@ struct max77620_gpio {
+ };
+
+ static const struct regmap_irq max77620_gpio_irqs[] = {
+- REGMAP_IRQ_REG(0, 0, MAX77620_IRQ_LVL2_GPIO_EDGE0),
+- REGMAP_IRQ_REG(1, 0, MAX77620_IRQ_LVL2_GPIO_EDGE1),
+- REGMAP_IRQ_REG(2, 0, MAX77620_IRQ_LVL2_GPIO_EDGE2),
+- REGMAP_IRQ_REG(3, 0, MAX77620_IRQ_LVL2_GPIO_EDGE3),
+- REGMAP_IRQ_REG(4, 0, MAX77620_IRQ_LVL2_GPIO_EDGE4),
+- REGMAP_IRQ_REG(5, 0, MAX77620_IRQ_LVL2_GPIO_EDGE5),
+- REGMAP_IRQ_REG(6, 0, MAX77620_IRQ_LVL2_GPIO_EDGE6),
+- REGMAP_IRQ_REG(7, 0, MAX77620_IRQ_LVL2_GPIO_EDGE7),
++ [0] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 0,
++ },
++ [1] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 1,
++ },
++ [2] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 2,
++ },
++ [3] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 3,
++ },
++ [4] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 4,
++ },
++ [5] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 5,
++ },
++ [6] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 6,
++ },
++ [7] = {
++ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
++ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
++ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
++ .reg_offset = 0,
++ .type_reg_offset = 7,
++ },
+ };
+
+ static struct regmap_irq_chip max77620_gpio_irq_chip = {
+@@ -42,8 +90,11 @@ static struct regmap_irq_chip max77620_gpio_irq_chip = {
+ .irqs = max77620_gpio_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
+ .num_regs = 1,
++ .num_type_reg = 8,
+ .irq_reg_stride = 1,
++ .type_reg_stride = 1,
+ .status_base = MAX77620_REG_IRQ_LVL2_GPIO,
++ .type_base = MAX77620_REG_GPIO0,
+ };
+
+ static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
diff --git a/debian/patches/features/arm/gpio-max77620-get-gpio-value-based-on-direction.patch b/debian/patches/features/arm/gpio-max77620-get-gpio-value-based-on-direction.patch
new file mode 100644
index 0000000..43bac53
--- /dev/null
+++ b/debian/patches/features/arm/gpio-max77620-get-gpio-value-based-on-direction.patch
@@ -0,0 +1,34 @@
+
+Patch has been accepted for 4.8-rc1
+
+
+commit 1941b4419a24e026ce8354a2fd40c9387577697e
+Author: Venkat Reddy Talla <vreddytalla at nvidia.com>
+Date: Mon Jun 27 16:26:24 2016 +0530
+
+ gpio: max77620: get gpio value based on direction
+
+ Gpio direction is determined by DIRx bit of GPIO
+ configuration register, return max77620 gpio value
+ based on direction in or out.
+
+ Signed-off-by: Venkat Reddy Talla <vreddytalla at nvidia.com>
+ Reviewed-by: Alexandre Courbot <acourbot at nvidia.com>
+ Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index 8658c32..b46b436 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -123,7 +123,10 @@ static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
+ return ret;
+ }
+
+- return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
++ if (val & MAX77620_CNFG_GPIO_DIR_MASK)
++ return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
++ else
++ return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
+ }
+
+ static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
diff --git a/debian/patches/features/arm/gpio-max77620-use-the-new-open-drain-callback.patch b/debian/patches/features/arm/gpio-max77620-use-the-new-open-drain-callback.patch
new file mode 100644
index 0000000..b0b147c
--- /dev/null
+++ b/debian/patches/features/arm/gpio-max77620-use-the-new-open-drain-callback.patch
@@ -0,0 +1,59 @@
+
+Patch has been accepted for 4.8-rc1
+
+
+commit 23087a05006057bbaa2c1f42163e45586dd77094
+Author: Laxman Dewangan <ldewangan at nvidia.com>
+Date: Tue May 24 18:43:46 2016 +0530
+
+ gpio: max77620: use the new open drain callback
+
+ The MAX77620 have a GPIO pins which can act as open drain or
+ push pull mode. Implement support for controlling this from GPIO
+ descriptor tables or other hardware descriptions such as
+ device tree by implementing the .set_single_ended() callback.
+
+ Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
+ Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
+
+diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
+index 35f365c..8658c32 100644
+--- a/drivers/gpio/gpio-max77620.c
++++ b/drivers/gpio/gpio-max77620.c
+@@ -202,6 +202,28 @@ static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
+ }
+
++static int max77620_gpio_set_single_ended(struct gpio_chip *gc,
++ unsigned int offset,
++ enum single_ended_mode mode)
++{
++ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
++
++ switch (mode) {
++ case LINE_MODE_OPEN_DRAIN:
++ return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_DRV_MASK,
++ MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
++ case LINE_MODE_PUSH_PULL:
++ return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
++ MAX77620_CNFG_GPIO_DRV_MASK,
++ MAX77620_CNFG_GPIO_DRV_PUSHPULL);
++ default:
++ break;
++ }
++
++ return -ENOTSUPP;
++}
++
+ static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
+ {
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+@@ -238,6 +260,7 @@ static int max77620_gpio_probe(struct platform_device *pdev)
+ mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
+ mgpio->gpio_chip.set = max77620_gpio_set;
++ mgpio->gpio_chip.set_single_ended = max77620_gpio_set_single_ended;
+ mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
+ mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
+ mgpio->gpio_chip.can_sleep = 1;
diff --git a/debian/patches/features/arm/pinctrl-max77620-add-pincontrol-driver.patch b/debian/patches/features/arm/pinctrl-max77620-add-pincontrol-driver.patch
new file mode 100644
index 0000000..b69dbac
--- /dev/null
+++ b/debian/patches/features/arm/pinctrl-max77620-add-pincontrol-driver.patch
@@ -0,0 +1,738 @@
+
+Patch has been accepted for 4.8-rc1
+
+commit 2df723d49cdafb6ea97bf7768879c5197666d300
+Author: Laxman Dewangan <ldewangan at nvidia.com>
+Date: Fri May 13 10:49:15 2016 +0530
+
+ pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
+
+ MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
+ which also act as the special function in alternate mode. Also
+ there is configuration like push-pull, open drain, FPS timing
+ etc for these pins.
+
+ Add pin control driver to configure these parameters through
+ pin control APIs.
+
+ Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
+ Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
+ Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
+
+diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
+index f06589c..ea25eee 100644
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -196,6 +196,16 @@ config PINCTRL_COH901
+ COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
+ ports of 8 GPIO pins each.
+
++config PINCTRL_MAX77620
++ tristate "MAX77620/MAX20024 Pincontrol support"
++ depends on MFD_MAX77620
++ select GENERIC_PINCONF
++ help
++ Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
++ This PMIC has 8 GPIO pins that work as GPIO as well as special
++ function in alternate mode. This driver also configure push-pull,
++ open drain, FPS slots etc.
++
+ config PINCTRL_PALMAS
+ bool "Pinctrl driver for the PALMAS Series MFD devices"
+ depends on OF && MFD_PALMAS
+diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
+index f678343..2ed0b3f 100644
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
+ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
+ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
+ obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
++obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
+ obj-$(CONFIG_PINCTRL_MESON) += meson/
+ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
+ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
+diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
+new file mode 100644
+index 0000000..19005a0
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-max77620.c
+@@ -0,0 +1,678 @@
++/*
++ * MAX77620 pin control driver.
++ *
++ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Author:
++ * Chaitanya Bandi <bandik at nvidia.com>
++ * Laxman Dewangan <ldewangan at nvidia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ */
++
++#include <linux/mfd/max77620.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include "core.h"
++#include "pinconf.h"
++#include "pinctrl-utils.h"
++
++#define MAX77620_PIN_NUM 8
++
++enum max77620_pin_ppdrv {
++ MAX77620_PIN_UNCONFIG_DRV,
++ MAX77620_PIN_OD_DRV,
++ MAX77620_PIN_PP_DRV,
++};
++
++enum max77620_pinconf_param {
++ MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
++ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
++ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
++ MAX77620_SUSPEND_FPS_SOURCE,
++ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
++ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
++};
++
++struct max77620_pin_function {
++ const char *name;
++ const char * const *groups;
++ unsigned int ngroups;
++ int mux_option;
++};
++
++struct max77620_cfg_param {
++ const char *property;
++ enum max77620_pinconf_param param;
++};
++
++static const struct pinconf_generic_params max77620_cfg_params[] = {
++ {
++ .property = "maxim,active-fps-source",
++ .param = MAX77620_ACTIVE_FPS_SOURCE,
++ }, {
++ .property = "maxim,active-fps-power-up-slot",
++ .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
++ }, {
++ .property = "maxim,active-fps-power-down-slot",
++ .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
++ }, {
++ .property = "maxim,suspend-fps-source",
++ .param = MAX77620_SUSPEND_FPS_SOURCE,
++ }, {
++ .property = "maxim,suspend-fps-power-up-slot",
++ .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
++ }, {
++ .property = "maxim,suspend-fps-power-down-slot",
++ .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
++ },
++};
++
++enum max77620_alternate_pinmux_option {
++ MAX77620_PINMUX_GPIO = 0,
++ MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
++ MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
++ MAX77620_PINMUX_32K_OUT1 = 3,
++ MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
++ MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
++ MAX77620_PINMUX_REFERENCE_OUT = 6,
++};
++
++struct max77620_pingroup {
++ const char *name;
++ const unsigned int pins[1];
++ unsigned int npins;
++ enum max77620_alternate_pinmux_option alt_option;
++};
++
++struct max77620_pin_info {
++ enum max77620_pin_ppdrv drv_type;
++ int pull_config;
++};
++
++struct max77620_fps_config {
++ int active_fps_src;
++ int active_power_up_slots;
++ int active_power_down_slots;
++ int suspend_fps_src;
++ int suspend_power_up_slots;
++ int suspend_power_down_slots;
++};
++
++struct max77620_pctrl_info {
++ struct device *dev;
++ struct pinctrl_dev *pctl;
++ struct regmap *rmap;
++ int pins_current_opt[MAX77620_GPIO_NR];
++ const struct max77620_pin_function *functions;
++ unsigned int num_functions;
++ const struct max77620_pingroup *pin_groups;
++ int num_pin_groups;
++ const struct pinctrl_pin_desc *pins;
++ unsigned int num_pins;
++ struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
++ struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
++};
++
++static const struct pinctrl_pin_desc max77620_pins_desc[] = {
++ PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
++ PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
++ PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
++ PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
++ PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
++ PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
++ PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
++ PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
++};
++
++static const char * const gpio_groups[] = {
++ "gpio0",
++ "gpio1",
++ "gpio2",
++ "gpio3",
++ "gpio4",
++ "gpio5",
++ "gpio6",
++ "gpio7",
++};
++
++#define FUNCTION_GROUP(fname, mux) \
++ { \
++ .name = fname, \
++ .groups = gpio_groups, \
++ .ngroups = ARRAY_SIZE(gpio_groups), \
++ .mux_option = MAX77620_PINMUX_##mux, \
++ }
++
++static const struct max77620_pin_function max77620_pin_function[] = {
++ FUNCTION_GROUP("gpio", GPIO),
++ FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
++ FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
++ FUNCTION_GROUP("32k-out1", 32K_OUT1),
++ FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
++ FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
++ FUNCTION_GROUP("reference-out", REFERENCE_OUT),
++};
++
++#define MAX77620_PINGROUP(pg_name, pin_id, option) \
++ { \
++ .name = #pg_name, \
++ .pins = {MAX77620_##pin_id}, \
++ .npins = 1, \
++ .alt_option = MAX77620_PINMUX_##option, \
++ }
++
++static const struct max77620_pingroup max77620_pingroups[] = {
++ MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
++ MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
++ MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
++ MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
++ MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
++ MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
++ MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
++ MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
++};
++
++static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ return mpci->num_pin_groups;
++}
++
++static const char *max77620_pinctrl_get_group_name(
++ struct pinctrl_dev *pctldev, unsigned int group)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ return mpci->pin_groups[group].name;
++}
++
++static int max77620_pinctrl_get_group_pins(
++ struct pinctrl_dev *pctldev, unsigned int group,
++ const unsigned int **pins, unsigned int *num_pins)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ *pins = mpci->pin_groups[group].pins;
++ *num_pins = mpci->pin_groups[group].npins;
++
++ return 0;
++}
++
++static const struct pinctrl_ops max77620_pinctrl_ops = {
++ .get_groups_count = max77620_pinctrl_get_groups_count,
++ .get_group_name = max77620_pinctrl_get_group_name,
++ .get_group_pins = max77620_pinctrl_get_group_pins,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
++ .dt_free_map = pinctrl_utils_free_map,
++};
++
++static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ return mpci->num_functions;
++}
++
++static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
++ unsigned int function)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ return mpci->functions[function].name;
++}
++
++static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
++ unsigned int function,
++ const char * const **groups,
++ unsigned int * const num_groups)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++
++ *groups = mpci->functions[function].groups;
++ *num_groups = mpci->functions[function].ngroups;
++
++ return 0;
++}
++
++static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
++ unsigned int function, unsigned int group)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++ u8 val;
++ int ret;
++
++ if (function == MAX77620_PINMUX_GPIO) {
++ val = 0;
++ } else if (function == mpci->pin_groups[group].alt_option) {
++ val = 1 << group;
++ } else {
++ dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
++ group, function);
++ return -EINVAL;
++ }
++ ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
++ BIT(group), val);
++ if (ret < 0)
++ dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
++
++ return ret;
++}
++
++static const struct pinmux_ops max77620_pinmux_ops = {
++ .get_functions_count = max77620_pinctrl_get_funcs_count,
++ .get_function_name = max77620_pinctrl_get_func_name,
++ .get_function_groups = max77620_pinctrl_get_func_groups,
++ .set_mux = max77620_pinctrl_enable,
++};
++
++static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
++ unsigned int pin, unsigned long *config)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++ struct device *dev = mpci->dev;
++ enum pin_config_param param = pinconf_to_config_param(*config);
++ unsigned int val;
++ int arg = 0;
++ int ret;
++
++ switch (param) {
++ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
++ arg = 1;
++ break;
++
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
++ arg = 1;
++ break;
++
++ case PIN_CONFIG_BIAS_PULL_UP:
++ ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
++ if (ret < 0) {
++ dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
++ return ret;
++ }
++ if (val & BIT(pin))
++ arg = 1;
++ break;
++
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
++ if (ret < 0) {
++ dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
++ return ret;
++ }
++ if (val & BIT(pin))
++ arg = 1;
++ break;
++
++ default:
++ dev_err(dev, "Properties not supported\n");
++ return -ENOTSUPP;
++ }
++
++ *config = pinconf_to_config_packed(param, (u16)arg);
++
++ return 0;
++}
++
++static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
++ int addr, int *fps)
++{
++ unsigned int val;
++ int ret;
++
++ ret = regmap_read(mpci->rmap, addr, &val);
++ if (ret < 0) {
++ dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
++ return ret;
++ }
++ *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
++
++ return 0;
++}
++
++static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
++ int pin, int param)
++{
++ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
++ int addr, ret;
++ int param_val;
++ int mask, shift;
++
++ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
++ return 0;
++
++ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
++ switch (param) {
++ case MAX77620_ACTIVE_FPS_SOURCE:
++ case MAX77620_SUSPEND_FPS_SOURCE:
++ mask = MAX77620_FPS_SRC_MASK;
++ shift = MAX77620_FPS_SRC_SHIFT;
++ param_val = fps_config->active_fps_src;
++ if (param == MAX77620_SUSPEND_FPS_SOURCE)
++ param_val = fps_config->suspend_fps_src;
++ break;
++
++ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
++ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
++ mask = MAX77620_FPS_PU_PERIOD_MASK;
++ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
++ param_val = fps_config->active_power_up_slots;
++ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
++ param_val = fps_config->suspend_power_up_slots;
++ break;
++
++ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
++ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
++ mask = MAX77620_FPS_PD_PERIOD_MASK;
++ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
++ param_val = fps_config->active_power_down_slots;
++ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
++ param_val = fps_config->suspend_power_down_slots;
++ break;
++
++ default:
++ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
++ param, pin);
++ return -EINVAL;
++ }
++
++ if (param_val < 0)
++ return 0;
++
++ ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
++ if (ret < 0)
++ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
++
++ return ret;
++}
++
++static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
++ unsigned int pin, unsigned long *configs,
++ unsigned int num_configs)
++{
++ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
++ struct device *dev = mpci->dev;
++ struct max77620_fps_config *fps_config;
++ int param;
++ u16 param_val;
++ unsigned int val;
++ unsigned int pu_val;
++ unsigned int pd_val;
++ int addr, ret;
++ int i;
++
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ param_val = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++ val = param_val ? 0 : 1;
++ ret = regmap_update_bits(mpci->rmap,
++ MAX77620_REG_GPIO0 + pin,
++ MAX77620_CNFG_GPIO_DRV_MASK,
++ val);
++ if (ret < 0) {
++ dev_err(dev, "Reg 0x%02x update failed %d\n",
++ MAX77620_REG_GPIO0 + pin, ret);
++ return ret;
++ }
++ mpci->pin_info[pin].drv_type = val ?
++ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
++ break;
++
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ val = param_val ? 1 : 0;
++ ret = regmap_update_bits(mpci->rmap,
++ MAX77620_REG_GPIO0 + pin,
++ MAX77620_CNFG_GPIO_DRV_MASK,
++ val);
++ if (ret < 0) {
++ dev_err(dev, "Reg 0x%02x update failed %d\n",
++ MAX77620_REG_GPIO0 + pin, ret);
++ return ret;
++ }
++ mpci->pin_info[pin].drv_type = val ?
++ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
++ break;
++
++ case MAX77620_ACTIVE_FPS_SOURCE:
++ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
++ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
++ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
++ return -EINVAL;
++
++ fps_config = &mpci->fps_config[pin];
++
++ if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
++ (param_val == MAX77620_FPS_SRC_DEF)) {
++ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
++ ret = max77620_get_default_fps(
++ mpci, addr,
++ &fps_config->active_fps_src);
++ if (ret < 0)
++ return ret;
++ break;
++ }
++
++ if (param == MAX77620_ACTIVE_FPS_SOURCE)
++ fps_config->active_fps_src = param_val;
++ else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
++ fps_config->active_power_up_slots = param_val;
++ else
++ fps_config->active_power_down_slots = param_val;
++
++ ret = max77620_set_fps_param(mpci, pin, param);
++ if (ret < 0)
++ return ret;
++ break;
++
++ case MAX77620_SUSPEND_FPS_SOURCE:
++ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
++ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
++ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
++ return -EINVAL;
++
++ fps_config = &mpci->fps_config[pin];
++
++ if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
++ (param_val == MAX77620_FPS_SRC_DEF)) {
++ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
++ ret = max77620_get_default_fps(
++ mpci, addr,
++ &fps_config->suspend_fps_src);
++ if (ret < 0)
++ return ret;
++ break;
++ }
++
++ if (param == MAX77620_SUSPEND_FPS_SOURCE)
++ fps_config->suspend_fps_src = param_val;
++ else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
++ fps_config->suspend_power_up_slots = param_val;
++ else
++ fps_config->suspend_power_down_slots =
++ param_val;
++ break;
++
++ case PIN_CONFIG_BIAS_PULL_UP:
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
++ BIT(pin) : 0;
++ pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
++ BIT(pin) : 0;
++
++ ret = regmap_update_bits(mpci->rmap,
++ MAX77620_REG_PUE_GPIO,
++ BIT(pin), pu_val);
++ if (ret < 0) {
++ dev_err(dev, "PUE_GPIO update failed: %d\n",
++ ret);
++ return ret;
++ }
++
++ ret = regmap_update_bits(mpci->rmap,
++ MAX77620_REG_PDE_GPIO,
++ BIT(pin), pd_val);
++ if (ret < 0) {
++ dev_err(dev, "PDE_GPIO update failed: %d\n",
++ ret);
++ return ret;
++ }
++ break;
++
++ default:
++ dev_err(dev, "Properties not supported\n");
++ return -ENOTSUPP;
++ }
++ }
++
++ return 0;
++}
++
++static const struct pinconf_ops max77620_pinconf_ops = {
++ .pin_config_get = max77620_pinconf_get,
++ .pin_config_set = max77620_pinconf_set,
++};
++
++static struct pinctrl_desc max77620_pinctrl_desc = {
++ .pctlops = &max77620_pinctrl_ops,
++ .pmxops = &max77620_pinmux_ops,
++ .confops = &max77620_pinconf_ops,
++};
++
++static int max77620_pinctrl_probe(struct platform_device *pdev)
++{
++ struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
++ struct max77620_pctrl_info *mpci;
++ int i;
++
++ mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
++ if (!mpci)
++ return -ENOMEM;
++
++ mpci->dev = &pdev->dev;
++ mpci->dev->of_node = pdev->dev.parent->of_node;
++ mpci->rmap = max77620->rmap;
++
++ mpci->pins = max77620_pins_desc;
++ mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
++ mpci->functions = max77620_pin_function;
++ mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
++ mpci->pin_groups = max77620_pingroups;
++ mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
++ platform_set_drvdata(pdev, mpci);
++
++ max77620_pinctrl_desc.name = dev_name(&pdev->dev);
++ max77620_pinctrl_desc.pins = max77620_pins_desc;
++ max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
++ max77620_pinctrl_desc.num_custom_params =
++ ARRAY_SIZE(max77620_cfg_params);
++ max77620_pinctrl_desc.custom_params = max77620_cfg_params;
++
++ for (i = 0; i < MAX77620_PIN_NUM; ++i) {
++ mpci->fps_config[i].active_fps_src = -1;
++ mpci->fps_config[i].active_power_up_slots = -1;
++ mpci->fps_config[i].active_power_down_slots = -1;
++ mpci->fps_config[i].suspend_fps_src = -1;
++ mpci->fps_config[i].suspend_power_up_slots = -1;
++ mpci->fps_config[i].suspend_power_down_slots = -1;
++ }
++
++ mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
++ mpci);
++ if (IS_ERR(mpci->pctl)) {
++ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
++ return PTR_ERR(mpci->pctl);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int max77620_suspend_fps_param[] = {
++ MAX77620_SUSPEND_FPS_SOURCE,
++ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
++ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
++};
++
++static int max77620_active_fps_param[] = {
++ MAX77620_ACTIVE_FPS_SOURCE,
++ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
++ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
++};
++
++static int max77620_pinctrl_suspend(struct device *dev)
++{
++ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
++ int pin, p;
++
++ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
++ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
++ continue;
++ for (p = 0; p < 3; ++p)
++ max77620_set_fps_param(
++ mpci, pin, max77620_suspend_fps_param[p]);
++ }
++
++ return 0;
++};
++
++static int max77620_pinctrl_resume(struct device *dev)
++{
++ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
++ int pin, p;
++
++ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
++ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
++ continue;
++ for (p = 0; p < 3; ++p)
++ max77620_set_fps_param(
++ mpci, pin, max77620_active_fps_param[p]);
++ }
++
++ return 0;
++}
++#endif
++
++static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(
++ max77620_pinctrl_suspend, max77620_pinctrl_resume)
++};
++
++static const struct platform_device_id max77620_pinctrl_devtype[] = {
++ { .name = "max77620-pinctrl", },
++ { .name = "max20024-pinctrl", },
++ {},
++};
++MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
++
++static struct platform_driver max77620_pinctrl_driver = {
++ .driver = {
++ .name = "max77620-pinctrl",
++ .pm = &max77620_pinctrl_pm_ops,
++ },
++ .probe = max77620_pinctrl_probe,
++ .id_table = max77620_pinctrl_devtype,
++};
++
++module_platform_driver(max77620_pinctrl_driver);
++
++MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
++MODULE_AUTHOR("Chaitanya Bandi<bandik at nvidia.com>");
++MODULE_AUTHOR("Laxman Dewangan<ldewangan at nvidia.com>");
++MODULE_ALIAS("platform:max77620-pinctrl");
++MODULE_LICENSE("GPL v2");
diff --git a/debian/patches/series b/debian/patches/series
index c3ccd06..75bbe0f 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -53,6 +53,20 @@ features/mips/MIPS-octeon-Add-support-for-the-UBNT-E200-board.patch
features/x86/x86-memtest-WARN-if-bad-RAM-found.patch
features/x86/x86-make-x32-syscall-support-conditional.patch
features/x86/x86-kaslr-x86-power-remove-x86-hibernation-restricti.patch
+# USB for Jetson TX1: is in 4.8-rc1
+features/arm/pinctrl-max77620-add-pincontrol-driver.patch
+features/arm/gpio-max77620-add-gpio-driver.patch
+features/arm/gpio-max77620-configure-interrupt-trigger-level.patch
+features/arm/gpio-max77620-use-the-new-open-drain-callback.patch
+features/arm/gpio-max77620-get-gpio-value-based-on-direction.patch
+features/arm/arm64-tegra-add-pmic-support-on-jetson-tx1.patch
+features/arm/arm64-tegra-p2597-add-sdmmc-power-supplies.patch
+features/arm/arm64-tegra-add-dsi-panel-on-jetson-tx1.patch
+features/arm/arm64-tegra-add-tegra210-xusb-pad-controller.patch
+features/arm/arm64-tegra-add-tegra210-xusb-controller.patch
+features/arm/arm64-tegra-enable-debug-serial-on-jetson-tx1.patch
+features/arm/arm64-tegra-enable-xusb-controller-on-jetson-tx1.patch
+features/arm/arm64-tegra-correct-tegra210-xusb-mailbox-interrupt.patch
# Miscellaneous bug fixes
bugfix/all/kbuild-use-nostdinc-in-compile-tests.patch
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/kernel/linux.git
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